1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/reboot.h> 27 28 #define SMU_11_0_PARTIAL_PPTABLE 29 #define SWSMU_CODE_LAYER_L3 30 31 #include "amdgpu.h" 32 #include "amdgpu_smu.h" 33 #include "atomfirmware.h" 34 #include "amdgpu_atomfirmware.h" 35 #include "amdgpu_atombios.h" 36 #include "smu_v11_0.h" 37 #include "soc15_common.h" 38 #include "atom.h" 39 #include "amdgpu_ras.h" 40 #include "smu_cmn.h" 41 42 #include "asic_reg/thm/thm_11_0_2_offset.h" 43 #include "asic_reg/thm/thm_11_0_2_sh_mask.h" 44 #include "asic_reg/mp/mp_11_0_offset.h" 45 #include "asic_reg/mp/mp_11_0_sh_mask.h" 46 #include "asic_reg/smuio/smuio_11_0_0_offset.h" 47 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h" 48 49 /* 50 * DO NOT use these for err/warn/info/debug messages. 51 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 52 * They are more MGPU friendly. 53 */ 54 #undef pr_err 55 #undef pr_warn 56 #undef pr_info 57 #undef pr_debug 58 59 MODULE_FIRMWARE("amdgpu/arcturus_smc.bin"); 60 MODULE_FIRMWARE("amdgpu/navi10_smc.bin"); 61 MODULE_FIRMWARE("amdgpu/navi14_smc.bin"); 62 MODULE_FIRMWARE("amdgpu/navi12_smc.bin"); 63 MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin"); 64 MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin"); 65 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin"); 66 MODULE_FIRMWARE("amdgpu/beige_goby_smc.bin"); 67 68 #define SMU11_VOLTAGE_SCALE 4 69 70 #define SMU11_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms 71 72 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 73 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L 74 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 75 #define smnPCIE_LC_SPEED_CNTL 0x11140290 76 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000 77 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE 78 79 #define mmTHM_BACO_CNTL_ARCT 0xA7 80 #define mmTHM_BACO_CNTL_ARCT_BASE_IDX 0 81 82 static void smu_v11_0_poll_baco_exit(struct smu_context *smu) 83 { 84 struct amdgpu_device *adev = smu->adev; 85 uint32_t data, loop = 0; 86 87 do { 88 usleep_range(1000, 1100); 89 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL); 90 } while ((data & 0x100) && (++loop < 100)); 91 } 92 93 int smu_v11_0_init_microcode(struct smu_context *smu) 94 { 95 struct amdgpu_device *adev = smu->adev; 96 const char *chip_name; 97 char fw_name[SMU_FW_NAME_LEN]; 98 int err = 0; 99 const struct smc_firmware_header_v1_0 *hdr; 100 const struct common_firmware_header *header; 101 struct amdgpu_firmware_info *ucode = NULL; 102 103 if (amdgpu_sriov_vf(adev) && 104 ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9)) || 105 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)))) 106 return 0; 107 108 switch (adev->ip_versions[MP1_HWIP][0]) { 109 case IP_VERSION(11, 0, 0): 110 chip_name = "navi10"; 111 break; 112 case IP_VERSION(11, 0, 5): 113 chip_name = "navi14"; 114 break; 115 case IP_VERSION(11, 0, 9): 116 chip_name = "navi12"; 117 break; 118 case IP_VERSION(11, 0, 7): 119 chip_name = "sienna_cichlid"; 120 break; 121 case IP_VERSION(11, 0, 11): 122 chip_name = "navy_flounder"; 123 break; 124 case IP_VERSION(11, 0, 12): 125 chip_name = "dimgrey_cavefish"; 126 break; 127 case IP_VERSION(11, 0, 13): 128 chip_name = "beige_goby"; 129 break; 130 case IP_VERSION(11, 0, 2): 131 chip_name = "arcturus"; 132 break; 133 default: 134 dev_err(adev->dev, "Unsupported IP version 0x%x\n", 135 adev->ip_versions[MP1_HWIP][0]); 136 return -EINVAL; 137 } 138 139 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name); 140 141 err = request_firmware(&adev->pm.fw, fw_name, adev->dev); 142 if (err) 143 goto out; 144 err = amdgpu_ucode_validate(adev->pm.fw); 145 if (err) 146 goto out; 147 148 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 149 amdgpu_ucode_print_smc_hdr(&hdr->header); 150 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version); 151 152 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 153 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 154 ucode->ucode_id = AMDGPU_UCODE_ID_SMC; 155 ucode->fw = adev->pm.fw; 156 header = (const struct common_firmware_header *)ucode->fw->data; 157 adev->firmware.fw_size += 158 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 159 } 160 161 out: 162 if (err) { 163 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n", 164 fw_name); 165 release_firmware(adev->pm.fw); 166 adev->pm.fw = NULL; 167 } 168 return err; 169 } 170 171 void smu_v11_0_fini_microcode(struct smu_context *smu) 172 { 173 struct amdgpu_device *adev = smu->adev; 174 175 release_firmware(adev->pm.fw); 176 adev->pm.fw = NULL; 177 adev->pm.fw_version = 0; 178 } 179 180 int smu_v11_0_load_microcode(struct smu_context *smu) 181 { 182 struct amdgpu_device *adev = smu->adev; 183 const uint32_t *src; 184 const struct smc_firmware_header_v1_0 *hdr; 185 uint32_t addr_start = MP1_SRAM; 186 uint32_t i; 187 uint32_t smc_fw_size; 188 uint32_t mp1_fw_flags; 189 190 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 191 src = (const uint32_t *)(adev->pm.fw->data + 192 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 193 smc_fw_size = hdr->header.ucode_size_bytes; 194 195 for (i = 1; i < smc_fw_size/4 - 1; i++) { 196 WREG32_PCIE(addr_start, src[i]); 197 addr_start += 4; 198 } 199 200 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), 201 1 & MP1_SMN_PUB_CTRL__RESET_MASK); 202 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), 203 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK); 204 205 for (i = 0; i < adev->usec_timeout; i++) { 206 mp1_fw_flags = RREG32_PCIE(MP1_Public | 207 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); 208 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 209 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 210 break; 211 udelay(1); 212 } 213 214 if (i == adev->usec_timeout) 215 return -ETIME; 216 217 return 0; 218 } 219 220 int smu_v11_0_check_fw_status(struct smu_context *smu) 221 { 222 struct amdgpu_device *adev = smu->adev; 223 uint32_t mp1_fw_flags; 224 225 mp1_fw_flags = RREG32_PCIE(MP1_Public | 226 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); 227 228 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 229 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 230 return 0; 231 232 return -EIO; 233 } 234 235 int smu_v11_0_check_fw_version(struct smu_context *smu) 236 { 237 struct amdgpu_device *adev = smu->adev; 238 uint32_t if_version = 0xff, smu_version = 0xff; 239 uint8_t smu_program, smu_major, smu_minor, smu_debug; 240 int ret = 0; 241 242 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 243 if (ret) 244 return ret; 245 246 smu_program = (smu_version >> 24) & 0xff; 247 smu_major = (smu_version >> 16) & 0xff; 248 smu_minor = (smu_version >> 8) & 0xff; 249 smu_debug = (smu_version >> 0) & 0xff; 250 if (smu->is_apu) 251 adev->pm.fw_version = smu_version; 252 253 switch (adev->ip_versions[MP1_HWIP][0]) { 254 case IP_VERSION(11, 0, 0): 255 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10; 256 break; 257 case IP_VERSION(11, 0, 9): 258 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12; 259 break; 260 case IP_VERSION(11, 0, 5): 261 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14; 262 break; 263 case IP_VERSION(11, 0, 7): 264 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid; 265 break; 266 case IP_VERSION(11, 0, 11): 267 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder; 268 break; 269 case IP_VERSION(11, 5, 0): 270 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VANGOGH; 271 break; 272 case IP_VERSION(11, 0, 12): 273 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish; 274 break; 275 case IP_VERSION(11, 0, 13): 276 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Beige_Goby; 277 break; 278 case IP_VERSION(11, 0, 8): 279 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Cyan_Skillfish; 280 break; 281 case IP_VERSION(11, 0, 2): 282 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT; 283 break; 284 default: 285 dev_err(smu->adev->dev, "smu unsupported IP version: 0x%x.\n", 286 adev->ip_versions[MP1_HWIP][0]); 287 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV; 288 break; 289 } 290 291 /* 292 * 1. if_version mismatch is not critical as our fw is designed 293 * to be backward compatible. 294 * 2. New fw usually brings some optimizations. But that's visible 295 * only on the paired driver. 296 * Considering above, we just leave user a warning message instead 297 * of halt driver loading. 298 */ 299 if (if_version != smu->smc_driver_if_version) { 300 dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, " 301 "smu fw program = %d, version = 0x%08x (%d.%d.%d)\n", 302 smu->smc_driver_if_version, if_version, 303 smu_program, smu_version, smu_major, smu_minor, smu_debug); 304 dev_warn(smu->adev->dev, "SMU driver if version not matched\n"); 305 } 306 307 return ret; 308 } 309 310 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size) 311 { 312 struct amdgpu_device *adev = smu->adev; 313 uint32_t ppt_offset_bytes; 314 const struct smc_firmware_header_v2_0 *v2; 315 316 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data; 317 318 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes); 319 *size = le32_to_cpu(v2->ppt_size_bytes); 320 *table = (uint8_t *)v2 + ppt_offset_bytes; 321 322 return 0; 323 } 324 325 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table, 326 uint32_t *size, uint32_t pptable_id) 327 { 328 struct amdgpu_device *adev = smu->adev; 329 const struct smc_firmware_header_v2_1 *v2_1; 330 struct smc_soft_pptable_entry *entries; 331 uint32_t pptable_count = 0; 332 int i = 0; 333 334 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data; 335 entries = (struct smc_soft_pptable_entry *) 336 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset)); 337 pptable_count = le32_to_cpu(v2_1->pptable_count); 338 for (i = 0; i < pptable_count; i++) { 339 if (le32_to_cpu(entries[i].id) == pptable_id) { 340 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes)); 341 *size = le32_to_cpu(entries[i].ppt_size_bytes); 342 break; 343 } 344 } 345 346 if (i == pptable_count) 347 return -EINVAL; 348 349 return 0; 350 } 351 352 int smu_v11_0_setup_pptable(struct smu_context *smu) 353 { 354 struct amdgpu_device *adev = smu->adev; 355 const struct smc_firmware_header_v1_0 *hdr; 356 int ret, index; 357 uint32_t size = 0; 358 uint16_t atom_table_size; 359 uint8_t frev, crev; 360 void *table; 361 uint16_t version_major, version_minor; 362 363 if (!amdgpu_sriov_vf(adev)) { 364 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 365 version_major = le16_to_cpu(hdr->header.header_version_major); 366 version_minor = le16_to_cpu(hdr->header.header_version_minor); 367 if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) { 368 dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id); 369 switch (version_minor) { 370 case 0: 371 ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size); 372 break; 373 case 1: 374 ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size, 375 smu->smu_table.boot_values.pp_table_id); 376 break; 377 default: 378 ret = -EINVAL; 379 break; 380 } 381 if (ret) 382 return ret; 383 goto out; 384 } 385 } 386 387 dev_info(adev->dev, "use vbios provided pptable\n"); 388 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 389 powerplayinfo); 390 391 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev, 392 (uint8_t **)&table); 393 if (ret) 394 return ret; 395 size = atom_table_size; 396 397 out: 398 if (!smu->smu_table.power_play_table) 399 smu->smu_table.power_play_table = table; 400 if (!smu->smu_table.power_play_table_size) 401 smu->smu_table.power_play_table_size = size; 402 403 return 0; 404 } 405 406 int smu_v11_0_init_smc_tables(struct smu_context *smu) 407 { 408 struct smu_table_context *smu_table = &smu->smu_table; 409 struct smu_table *tables = smu_table->tables; 410 int ret = 0; 411 412 smu_table->driver_pptable = 413 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL); 414 if (!smu_table->driver_pptable) { 415 ret = -ENOMEM; 416 goto err0_out; 417 } 418 419 smu_table->max_sustainable_clocks = 420 kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks), GFP_KERNEL); 421 if (!smu_table->max_sustainable_clocks) { 422 ret = -ENOMEM; 423 goto err1_out; 424 } 425 426 /* Arcturus does not support OVERDRIVE */ 427 if (tables[SMU_TABLE_OVERDRIVE].size) { 428 smu_table->overdrive_table = 429 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); 430 if (!smu_table->overdrive_table) { 431 ret = -ENOMEM; 432 goto err2_out; 433 } 434 435 smu_table->boot_overdrive_table = 436 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); 437 if (!smu_table->boot_overdrive_table) { 438 ret = -ENOMEM; 439 goto err3_out; 440 } 441 442 smu_table->user_overdrive_table = 443 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); 444 if (!smu_table->user_overdrive_table) { 445 ret = -ENOMEM; 446 goto err4_out; 447 } 448 449 } 450 451 return 0; 452 453 err4_out: 454 kfree(smu_table->boot_overdrive_table); 455 err3_out: 456 kfree(smu_table->overdrive_table); 457 err2_out: 458 kfree(smu_table->max_sustainable_clocks); 459 err1_out: 460 kfree(smu_table->driver_pptable); 461 err0_out: 462 return ret; 463 } 464 465 int smu_v11_0_fini_smc_tables(struct smu_context *smu) 466 { 467 struct smu_table_context *smu_table = &smu->smu_table; 468 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 469 470 kfree(smu_table->gpu_metrics_table); 471 kfree(smu_table->user_overdrive_table); 472 kfree(smu_table->boot_overdrive_table); 473 kfree(smu_table->overdrive_table); 474 kfree(smu_table->max_sustainable_clocks); 475 kfree(smu_table->driver_pptable); 476 kfree(smu_table->clocks_table); 477 smu_table->gpu_metrics_table = NULL; 478 smu_table->user_overdrive_table = NULL; 479 smu_table->boot_overdrive_table = NULL; 480 smu_table->overdrive_table = NULL; 481 smu_table->max_sustainable_clocks = NULL; 482 smu_table->driver_pptable = NULL; 483 smu_table->clocks_table = NULL; 484 kfree(smu_table->hardcode_pptable); 485 smu_table->hardcode_pptable = NULL; 486 487 kfree(smu_table->driver_smu_config_table); 488 kfree(smu_table->ecc_table); 489 kfree(smu_table->metrics_table); 490 kfree(smu_table->watermarks_table); 491 smu_table->driver_smu_config_table = NULL; 492 smu_table->ecc_table = NULL; 493 smu_table->metrics_table = NULL; 494 smu_table->watermarks_table = NULL; 495 smu_table->metrics_time = 0; 496 497 kfree(smu_dpm->dpm_context); 498 kfree(smu_dpm->golden_dpm_context); 499 kfree(smu_dpm->dpm_current_power_state); 500 kfree(smu_dpm->dpm_request_power_state); 501 smu_dpm->dpm_context = NULL; 502 smu_dpm->golden_dpm_context = NULL; 503 smu_dpm->dpm_context_size = 0; 504 smu_dpm->dpm_current_power_state = NULL; 505 smu_dpm->dpm_request_power_state = NULL; 506 507 return 0; 508 } 509 510 int smu_v11_0_init_power(struct smu_context *smu) 511 { 512 struct amdgpu_device *adev = smu->adev; 513 struct smu_power_context *smu_power = &smu->smu_power; 514 size_t size = adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0) ? 515 sizeof(struct smu_11_5_power_context) : 516 sizeof(struct smu_11_0_power_context); 517 518 smu_power->power_context = kzalloc(size, GFP_KERNEL); 519 if (!smu_power->power_context) 520 return -ENOMEM; 521 smu_power->power_context_size = size; 522 523 return 0; 524 } 525 526 int smu_v11_0_fini_power(struct smu_context *smu) 527 { 528 struct smu_power_context *smu_power = &smu->smu_power; 529 530 kfree(smu_power->power_context); 531 smu_power->power_context = NULL; 532 smu_power->power_context_size = 0; 533 534 return 0; 535 } 536 537 static int smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device *adev, 538 uint8_t clk_id, 539 uint8_t syspll_id, 540 uint32_t *clk_freq) 541 { 542 struct atom_get_smu_clock_info_parameters_v3_1 input = {0}; 543 struct atom_get_smu_clock_info_output_parameters_v3_1 *output; 544 int ret, index; 545 546 input.clk_id = clk_id; 547 input.syspll_id = syspll_id; 548 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ; 549 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1, 550 getsmuclockinfo); 551 552 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index, 553 (uint32_t *)&input); 554 if (ret) 555 return -EINVAL; 556 557 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input; 558 *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000; 559 560 return 0; 561 } 562 563 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu) 564 { 565 int ret, index; 566 uint16_t size; 567 uint8_t frev, crev; 568 struct atom_common_table_header *header; 569 struct atom_firmware_info_v3_3 *v_3_3; 570 struct atom_firmware_info_v3_1 *v_3_1; 571 572 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 573 firmwareinfo); 574 575 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev, 576 (uint8_t **)&header); 577 if (ret) 578 return ret; 579 580 if (header->format_revision != 3) { 581 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu11\n"); 582 return -EINVAL; 583 } 584 585 switch (header->content_revision) { 586 case 0: 587 case 1: 588 case 2: 589 v_3_1 = (struct atom_firmware_info_v3_1 *)header; 590 smu->smu_table.boot_values.revision = v_3_1->firmware_revision; 591 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz; 592 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; 593 smu->smu_table.boot_values.socclk = 0; 594 smu->smu_table.boot_values.dcefclk = 0; 595 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv; 596 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv; 597 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv; 598 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv; 599 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id; 600 smu->smu_table.boot_values.pp_table_id = 0; 601 smu->smu_table.boot_values.firmware_caps = v_3_1->firmware_capability; 602 break; 603 case 3: 604 case 4: 605 default: 606 v_3_3 = (struct atom_firmware_info_v3_3 *)header; 607 smu->smu_table.boot_values.revision = v_3_3->firmware_revision; 608 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz; 609 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; 610 smu->smu_table.boot_values.socclk = 0; 611 smu->smu_table.boot_values.dcefclk = 0; 612 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv; 613 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv; 614 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv; 615 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv; 616 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id; 617 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id; 618 smu->smu_table.boot_values.firmware_caps = v_3_3->firmware_capability; 619 } 620 621 smu->smu_table.boot_values.format_revision = header->format_revision; 622 smu->smu_table.boot_values.content_revision = header->content_revision; 623 624 smu_v11_0_atom_get_smu_clockinfo(smu->adev, 625 (uint8_t)SMU11_SYSPLL0_SOCCLK_ID, 626 (uint8_t)0, 627 &smu->smu_table.boot_values.socclk); 628 629 smu_v11_0_atom_get_smu_clockinfo(smu->adev, 630 (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID, 631 (uint8_t)0, 632 &smu->smu_table.boot_values.dcefclk); 633 634 smu_v11_0_atom_get_smu_clockinfo(smu->adev, 635 (uint8_t)SMU11_SYSPLL0_ECLK_ID, 636 (uint8_t)0, 637 &smu->smu_table.boot_values.eclk); 638 639 smu_v11_0_atom_get_smu_clockinfo(smu->adev, 640 (uint8_t)SMU11_SYSPLL0_VCLK_ID, 641 (uint8_t)0, 642 &smu->smu_table.boot_values.vclk); 643 644 smu_v11_0_atom_get_smu_clockinfo(smu->adev, 645 (uint8_t)SMU11_SYSPLL0_DCLK_ID, 646 (uint8_t)0, 647 &smu->smu_table.boot_values.dclk); 648 649 if ((smu->smu_table.boot_values.format_revision == 3) && 650 (smu->smu_table.boot_values.content_revision >= 2)) 651 smu_v11_0_atom_get_smu_clockinfo(smu->adev, 652 (uint8_t)SMU11_SYSPLL1_0_FCLK_ID, 653 (uint8_t)SMU11_SYSPLL1_2_ID, 654 &smu->smu_table.boot_values.fclk); 655 656 smu_v11_0_atom_get_smu_clockinfo(smu->adev, 657 (uint8_t)SMU11_SYSPLL3_1_LCLK_ID, 658 (uint8_t)SMU11_SYSPLL3_1_ID, 659 &smu->smu_table.boot_values.lclk); 660 661 return 0; 662 } 663 664 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu) 665 { 666 struct smu_table_context *smu_table = &smu->smu_table; 667 struct smu_table *memory_pool = &smu_table->memory_pool; 668 int ret = 0; 669 uint64_t address; 670 uint32_t address_low, address_high; 671 672 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL) 673 return ret; 674 675 address = (uintptr_t)memory_pool->cpu_addr; 676 address_high = (uint32_t)upper_32_bits(address); 677 address_low = (uint32_t)lower_32_bits(address); 678 679 ret = smu_cmn_send_smc_msg_with_param(smu, 680 SMU_MSG_SetSystemVirtualDramAddrHigh, 681 address_high, 682 NULL); 683 if (ret) 684 return ret; 685 ret = smu_cmn_send_smc_msg_with_param(smu, 686 SMU_MSG_SetSystemVirtualDramAddrLow, 687 address_low, 688 NULL); 689 if (ret) 690 return ret; 691 692 address = memory_pool->mc_address; 693 address_high = (uint32_t)upper_32_bits(address); 694 address_low = (uint32_t)lower_32_bits(address); 695 696 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh, 697 address_high, NULL); 698 if (ret) 699 return ret; 700 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow, 701 address_low, NULL); 702 if (ret) 703 return ret; 704 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize, 705 (uint32_t)memory_pool->size, NULL); 706 if (ret) 707 return ret; 708 709 return ret; 710 } 711 712 int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk) 713 { 714 int ret; 715 716 ret = smu_cmn_send_smc_msg_with_param(smu, 717 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL); 718 if (ret) 719 dev_err(smu->adev->dev, "SMU11 attempt to set divider for DCEFCLK Failed!"); 720 721 return ret; 722 } 723 724 int smu_v11_0_set_driver_table_location(struct smu_context *smu) 725 { 726 struct smu_table *driver_table = &smu->smu_table.driver_table; 727 int ret = 0; 728 729 if (driver_table->mc_address) { 730 ret = smu_cmn_send_smc_msg_with_param(smu, 731 SMU_MSG_SetDriverDramAddrHigh, 732 upper_32_bits(driver_table->mc_address), 733 NULL); 734 if (!ret) 735 ret = smu_cmn_send_smc_msg_with_param(smu, 736 SMU_MSG_SetDriverDramAddrLow, 737 lower_32_bits(driver_table->mc_address), 738 NULL); 739 } 740 741 return ret; 742 } 743 744 int smu_v11_0_set_tool_table_location(struct smu_context *smu) 745 { 746 int ret = 0; 747 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG]; 748 749 if (tool_table->mc_address) { 750 ret = smu_cmn_send_smc_msg_with_param(smu, 751 SMU_MSG_SetToolsDramAddrHigh, 752 upper_32_bits(tool_table->mc_address), 753 NULL); 754 if (!ret) 755 ret = smu_cmn_send_smc_msg_with_param(smu, 756 SMU_MSG_SetToolsDramAddrLow, 757 lower_32_bits(tool_table->mc_address), 758 NULL); 759 } 760 761 return ret; 762 } 763 764 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count) 765 { 766 struct amdgpu_device *adev = smu->adev; 767 768 /* Navy_Flounder/Dimgrey_Cavefish do not support to change 769 * display num currently 770 */ 771 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11) || 772 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0) || 773 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 12) || 774 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) 775 return 0; 776 777 return smu_cmn_send_smc_msg_with_param(smu, 778 SMU_MSG_NumOfDisplays, 779 count, 780 NULL); 781 } 782 783 784 int smu_v11_0_set_allowed_mask(struct smu_context *smu) 785 { 786 struct smu_feature *feature = &smu->smu_feature; 787 int ret = 0; 788 uint32_t feature_mask[2]; 789 790 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64) { 791 ret = -EINVAL; 792 goto failed; 793 } 794 795 bitmap_to_arr32(feature_mask, feature->allowed, 64); 796 797 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, 798 feature_mask[1], NULL); 799 if (ret) 800 goto failed; 801 802 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow, 803 feature_mask[0], NULL); 804 if (ret) 805 goto failed; 806 807 failed: 808 return ret; 809 } 810 811 int smu_v11_0_system_features_control(struct smu_context *smu, 812 bool en) 813 { 814 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures : 815 SMU_MSG_DisableAllSmuFeatures), NULL); 816 } 817 818 int smu_v11_0_notify_display_change(struct smu_context *smu) 819 { 820 int ret = 0; 821 822 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && 823 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM) 824 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL); 825 826 return ret; 827 } 828 829 static int 830 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock, 831 enum smu_clk_type clock_select) 832 { 833 int ret = 0; 834 int clk_id; 835 836 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) || 837 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0)) 838 return 0; 839 840 clk_id = smu_cmn_to_asic_specific_index(smu, 841 CMN2ASIC_MAPPING_CLK, 842 clock_select); 843 if (clk_id < 0) 844 return -EINVAL; 845 846 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq, 847 clk_id << 16, clock); 848 if (ret) { 849 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!"); 850 return ret; 851 } 852 853 if (*clock != 0) 854 return 0; 855 856 /* if DC limit is zero, return AC limit */ 857 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, 858 clk_id << 16, clock); 859 if (ret) { 860 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!"); 861 return ret; 862 } 863 864 return 0; 865 } 866 867 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu) 868 { 869 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks = 870 smu->smu_table.max_sustainable_clocks; 871 int ret = 0; 872 873 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100; 874 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100; 875 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100; 876 max_sustainable_clocks->display_clock = 0xFFFFFFFF; 877 max_sustainable_clocks->phy_clock = 0xFFFFFFFF; 878 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF; 879 880 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 881 ret = smu_v11_0_get_max_sustainable_clock(smu, 882 &(max_sustainable_clocks->uclock), 883 SMU_UCLK); 884 if (ret) { 885 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!", 886 __func__); 887 return ret; 888 } 889 } 890 891 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 892 ret = smu_v11_0_get_max_sustainable_clock(smu, 893 &(max_sustainable_clocks->soc_clock), 894 SMU_SOCCLK); 895 if (ret) { 896 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!", 897 __func__); 898 return ret; 899 } 900 } 901 902 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 903 ret = smu_v11_0_get_max_sustainable_clock(smu, 904 &(max_sustainable_clocks->dcef_clock), 905 SMU_DCEFCLK); 906 if (ret) { 907 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!", 908 __func__); 909 return ret; 910 } 911 912 ret = smu_v11_0_get_max_sustainable_clock(smu, 913 &(max_sustainable_clocks->display_clock), 914 SMU_DISPCLK); 915 if (ret) { 916 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!", 917 __func__); 918 return ret; 919 } 920 ret = smu_v11_0_get_max_sustainable_clock(smu, 921 &(max_sustainable_clocks->phy_clock), 922 SMU_PHYCLK); 923 if (ret) { 924 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!", 925 __func__); 926 return ret; 927 } 928 ret = smu_v11_0_get_max_sustainable_clock(smu, 929 &(max_sustainable_clocks->pixel_clock), 930 SMU_PIXCLK); 931 if (ret) { 932 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!", 933 __func__); 934 return ret; 935 } 936 } 937 938 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock) 939 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock; 940 941 return 0; 942 } 943 944 int smu_v11_0_get_current_power_limit(struct smu_context *smu, 945 uint32_t *power_limit) 946 { 947 int power_src; 948 int ret = 0; 949 950 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) 951 return -EINVAL; 952 953 power_src = smu_cmn_to_asic_specific_index(smu, 954 CMN2ASIC_MAPPING_PWR, 955 smu->adev->pm.ac_power ? 956 SMU_POWER_SOURCE_AC : 957 SMU_POWER_SOURCE_DC); 958 if (power_src < 0) 959 return -EINVAL; 960 961 /* 962 * BIT 24-31: ControllerId (only PPT0 is supported for now) 963 * BIT 16-23: PowerSource 964 */ 965 ret = smu_cmn_send_smc_msg_with_param(smu, 966 SMU_MSG_GetPptLimit, 967 (0 << 24) | (power_src << 16), 968 power_limit); 969 if (ret) 970 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__); 971 972 return ret; 973 } 974 975 int smu_v11_0_set_power_limit(struct smu_context *smu, 976 enum smu_ppt_limit_type limit_type, 977 uint32_t limit) 978 { 979 int power_src; 980 int ret = 0; 981 uint32_t limit_param; 982 983 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 984 return -EINVAL; 985 986 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 987 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n"); 988 return -EOPNOTSUPP; 989 } 990 991 power_src = smu_cmn_to_asic_specific_index(smu, 992 CMN2ASIC_MAPPING_PWR, 993 smu->adev->pm.ac_power ? 994 SMU_POWER_SOURCE_AC : 995 SMU_POWER_SOURCE_DC); 996 if (power_src < 0) 997 return -EINVAL; 998 999 /* 1000 * BIT 24-31: ControllerId (only PPT0 is supported for now) 1001 * BIT 16-23: PowerSource 1002 * BIT 0-15: PowerLimit 1003 */ 1004 limit_param = (limit & 0xFFFF); 1005 limit_param |= 0 << 24; 1006 limit_param |= (power_src) << 16; 1007 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit_param, NULL); 1008 if (ret) { 1009 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__); 1010 return ret; 1011 } 1012 1013 smu->current_power_limit = limit; 1014 1015 return 0; 1016 } 1017 1018 static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu) 1019 { 1020 return smu_cmn_send_smc_msg(smu, 1021 SMU_MSG_ReenableAcDcInterrupt, 1022 NULL); 1023 } 1024 1025 static int smu_v11_0_process_pending_interrupt(struct smu_context *smu) 1026 { 1027 int ret = 0; 1028 1029 if (smu->dc_controlled_by_gpio && 1030 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT)) 1031 ret = smu_v11_0_ack_ac_dc_interrupt(smu); 1032 1033 return ret; 1034 } 1035 1036 void smu_v11_0_interrupt_work(struct smu_context *smu) 1037 { 1038 if (smu_v11_0_ack_ac_dc_interrupt(smu)) 1039 dev_err(smu->adev->dev, "Ack AC/DC interrupt Failed!\n"); 1040 } 1041 1042 int smu_v11_0_enable_thermal_alert(struct smu_context *smu) 1043 { 1044 int ret = 0; 1045 1046 if (smu->smu_table.thermal_controller_type) { 1047 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0); 1048 if (ret) 1049 return ret; 1050 } 1051 1052 /* 1053 * After init there might have been missed interrupts triggered 1054 * before driver registers for interrupt (Ex. AC/DC). 1055 */ 1056 return smu_v11_0_process_pending_interrupt(smu); 1057 } 1058 1059 int smu_v11_0_disable_thermal_alert(struct smu_context *smu) 1060 { 1061 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0); 1062 } 1063 1064 static uint16_t convert_to_vddc(uint8_t vid) 1065 { 1066 return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE); 1067 } 1068 1069 int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value) 1070 { 1071 struct amdgpu_device *adev = smu->adev; 1072 uint32_t vdd = 0, val_vid = 0; 1073 1074 if (!value) 1075 return -EINVAL; 1076 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) & 1077 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >> 1078 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT; 1079 1080 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid); 1081 1082 *value = vdd; 1083 1084 return 0; 1085 1086 } 1087 1088 int 1089 smu_v11_0_display_clock_voltage_request(struct smu_context *smu, 1090 struct pp_display_clock_request 1091 *clock_req) 1092 { 1093 enum amd_pp_clock_type clk_type = clock_req->clock_type; 1094 int ret = 0; 1095 enum smu_clk_type clk_select = 0; 1096 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; 1097 1098 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) || 1099 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1100 switch (clk_type) { 1101 case amd_pp_dcef_clock: 1102 clk_select = SMU_DCEFCLK; 1103 break; 1104 case amd_pp_disp_clock: 1105 clk_select = SMU_DISPCLK; 1106 break; 1107 case amd_pp_pixel_clock: 1108 clk_select = SMU_PIXCLK; 1109 break; 1110 case amd_pp_phy_clock: 1111 clk_select = SMU_PHYCLK; 1112 break; 1113 case amd_pp_mem_clock: 1114 clk_select = SMU_UCLK; 1115 break; 1116 default: 1117 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__); 1118 ret = -EINVAL; 1119 break; 1120 } 1121 1122 if (ret) 1123 goto failed; 1124 1125 if (clk_select == SMU_UCLK && smu->disable_uclk_switch) 1126 return 0; 1127 1128 ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0); 1129 1130 if(clk_select == SMU_UCLK) 1131 smu->hard_min_uclk_req_from_dal = clk_freq; 1132 } 1133 1134 failed: 1135 return ret; 1136 } 1137 1138 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable) 1139 { 1140 int ret = 0; 1141 struct amdgpu_device *adev = smu->adev; 1142 1143 switch (adev->ip_versions[MP1_HWIP][0]) { 1144 case IP_VERSION(11, 0, 0): 1145 case IP_VERSION(11, 0, 5): 1146 case IP_VERSION(11, 0, 9): 1147 case IP_VERSION(11, 0, 7): 1148 case IP_VERSION(11, 0, 11): 1149 case IP_VERSION(11, 0, 12): 1150 case IP_VERSION(11, 0, 13): 1151 case IP_VERSION(11, 5, 0): 1152 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) 1153 return 0; 1154 if (enable) 1155 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL); 1156 else 1157 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL); 1158 break; 1159 default: 1160 break; 1161 } 1162 1163 return ret; 1164 } 1165 1166 uint32_t 1167 smu_v11_0_get_fan_control_mode(struct smu_context *smu) 1168 { 1169 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT)) 1170 return AMD_FAN_CTRL_AUTO; 1171 else 1172 return smu->user_dpm_profile.fan_mode; 1173 } 1174 1175 static int 1176 smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control) 1177 { 1178 int ret = 0; 1179 1180 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT)) 1181 return 0; 1182 1183 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control); 1184 if (ret) 1185 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!", 1186 __func__, (auto_fan_control ? "Start" : "Stop")); 1187 1188 return ret; 1189 } 1190 1191 static int 1192 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode) 1193 { 1194 struct amdgpu_device *adev = smu->adev; 1195 1196 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, 1197 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 1198 CG_FDO_CTRL2, TMIN, 0)); 1199 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, 1200 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 1201 CG_FDO_CTRL2, FDO_PWM_MODE, mode)); 1202 1203 return 0; 1204 } 1205 1206 int 1207 smu_v11_0_set_fan_speed_pwm(struct smu_context *smu, uint32_t speed) 1208 { 1209 struct amdgpu_device *adev = smu->adev; 1210 uint32_t duty100, duty; 1211 uint64_t tmp64; 1212 1213 speed = MIN(speed, 255); 1214 1215 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), 1216 CG_FDO_CTRL1, FMAX_DUTY100); 1217 if (!duty100) 1218 return -EINVAL; 1219 1220 tmp64 = (uint64_t)speed * duty100; 1221 do_div(tmp64, 255); 1222 duty = (uint32_t)tmp64; 1223 1224 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0, 1225 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), 1226 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty)); 1227 1228 return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC); 1229 } 1230 1231 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu, 1232 uint32_t speed) 1233 { 1234 struct amdgpu_device *adev = smu->adev; 1235 /* 1236 * crystal_clock_freq used for fan speed rpm calculation is 1237 * always 25Mhz. So, hardcode it as 2500(in 10K unit). 1238 */ 1239 uint32_t crystal_clock_freq = 2500; 1240 uint32_t tach_period; 1241 1242 if (speed == 0) 1243 return -EINVAL; 1244 /* 1245 * To prevent from possible overheat, some ASICs may have requirement 1246 * for minimum fan speed: 1247 * - For some NV10 SKU, the fan speed cannot be set lower than 1248 * 700 RPM. 1249 * - For some Sienna Cichlid SKU, the fan speed cannot be set 1250 * lower than 500 RPM. 1251 */ 1252 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed); 1253 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL, 1254 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), 1255 CG_TACH_CTRL, TARGET_PERIOD, 1256 tach_period)); 1257 1258 return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM); 1259 } 1260 1261 int smu_v11_0_get_fan_speed_pwm(struct smu_context *smu, 1262 uint32_t *speed) 1263 { 1264 struct amdgpu_device *adev = smu->adev; 1265 uint32_t duty100, duty; 1266 uint64_t tmp64; 1267 1268 /* 1269 * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly 1270 * detected via register retrieving. To workaround this, we will 1271 * report the fan speed as 0 PWM if user just requested such. 1272 */ 1273 if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_PWM) 1274 && !smu->user_dpm_profile.fan_speed_pwm) { 1275 *speed = 0; 1276 return 0; 1277 } 1278 1279 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), 1280 CG_FDO_CTRL1, FMAX_DUTY100); 1281 duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS), 1282 CG_THERMAL_STATUS, FDO_PWM_DUTY); 1283 if (!duty100) 1284 return -EINVAL; 1285 1286 tmp64 = (uint64_t)duty * 255; 1287 do_div(tmp64, duty100); 1288 *speed = MIN((uint32_t)tmp64, 255); 1289 1290 return 0; 1291 } 1292 1293 int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu, 1294 uint32_t *speed) 1295 { 1296 struct amdgpu_device *adev = smu->adev; 1297 uint32_t crystal_clock_freq = 2500; 1298 uint32_t tach_status; 1299 uint64_t tmp64; 1300 1301 /* 1302 * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly 1303 * detected via register retrieving. To workaround this, we will 1304 * report the fan speed as 0 RPM if user just requested such. 1305 */ 1306 if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_RPM) 1307 && !smu->user_dpm_profile.fan_speed_rpm) { 1308 *speed = 0; 1309 return 0; 1310 } 1311 1312 tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000; 1313 1314 tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS); 1315 if (tach_status) { 1316 do_div(tmp64, tach_status); 1317 *speed = (uint32_t)tmp64; 1318 } else { 1319 dev_warn_once(adev->dev, "Got zero output on CG_TACH_STATUS reading!\n"); 1320 *speed = 0; 1321 } 1322 1323 return 0; 1324 } 1325 1326 int 1327 smu_v11_0_set_fan_control_mode(struct smu_context *smu, 1328 uint32_t mode) 1329 { 1330 int ret = 0; 1331 1332 switch (mode) { 1333 case AMD_FAN_CTRL_NONE: 1334 ret = smu_v11_0_auto_fan_control(smu, 0); 1335 if (!ret) 1336 ret = smu_v11_0_set_fan_speed_pwm(smu, 255); 1337 break; 1338 case AMD_FAN_CTRL_MANUAL: 1339 ret = smu_v11_0_auto_fan_control(smu, 0); 1340 break; 1341 case AMD_FAN_CTRL_AUTO: 1342 ret = smu_v11_0_auto_fan_control(smu, 1); 1343 break; 1344 default: 1345 break; 1346 } 1347 1348 if (ret) { 1349 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__); 1350 return -EINVAL; 1351 } 1352 1353 return ret; 1354 } 1355 1356 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu, 1357 uint32_t pstate) 1358 { 1359 return smu_cmn_send_smc_msg_with_param(smu, 1360 SMU_MSG_SetXgmiMode, 1361 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3, 1362 NULL); 1363 } 1364 1365 static int smu_v11_0_set_irq_state(struct amdgpu_device *adev, 1366 struct amdgpu_irq_src *source, 1367 unsigned tyep, 1368 enum amdgpu_interrupt_state state) 1369 { 1370 struct smu_context *smu = adev->powerplay.pp_handle; 1371 uint32_t low, high; 1372 uint32_t val = 0; 1373 1374 switch (state) { 1375 case AMDGPU_IRQ_STATE_DISABLE: 1376 /* For THM irqs */ 1377 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); 1378 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1); 1379 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1); 1380 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); 1381 1382 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0); 1383 1384 /* For MP1 SW irqs */ 1385 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL); 1386 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1); 1387 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val); 1388 1389 break; 1390 case AMDGPU_IRQ_STATE_ENABLE: 1391 /* For THM irqs */ 1392 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, 1393 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES); 1394 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, 1395 smu->thermal_range.software_shutdown_temp); 1396 1397 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); 1398 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); 1399 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); 1400 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); 1401 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0); 1402 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff)); 1403 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff)); 1404 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); 1405 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); 1406 1407 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT); 1408 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT); 1409 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT); 1410 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val); 1411 1412 /* For MP1 SW irqs */ 1413 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT); 1414 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE); 1415 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0); 1416 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val); 1417 1418 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL); 1419 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0); 1420 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val); 1421 1422 break; 1423 default: 1424 break; 1425 } 1426 1427 return 0; 1428 } 1429 1430 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */ 1431 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */ 1432 1433 #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83 1434 1435 static int smu_v11_0_irq_process(struct amdgpu_device *adev, 1436 struct amdgpu_irq_src *source, 1437 struct amdgpu_iv_entry *entry) 1438 { 1439 struct smu_context *smu = adev->powerplay.pp_handle; 1440 uint32_t client_id = entry->client_id; 1441 uint32_t src_id = entry->src_id; 1442 /* 1443 * ctxid is used to distinguish different 1444 * events for SMCToHost interrupt. 1445 */ 1446 uint32_t ctxid = entry->src_data[0]; 1447 uint32_t data; 1448 1449 if (client_id == SOC15_IH_CLIENTID_THM) { 1450 switch (src_id) { 1451 case THM_11_0__SRCID__THM_DIG_THERM_L2H: 1452 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1453 /* 1454 * SW CTF just occurred. 1455 * Try to do a graceful shutdown to prevent further damage. 1456 */ 1457 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1458 orderly_poweroff(true); 1459 break; 1460 case THM_11_0__SRCID__THM_DIG_THERM_H2L: 1461 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n"); 1462 break; 1463 default: 1464 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n", 1465 src_id); 1466 break; 1467 } 1468 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) { 1469 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n"); 1470 /* 1471 * HW CTF just occurred. Shutdown to prevent further damage. 1472 */ 1473 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n"); 1474 orderly_poweroff(true); 1475 } else if (client_id == SOC15_IH_CLIENTID_MP1) { 1476 if (src_id == 0xfe) { 1477 /* ACK SMUToHost interrupt */ 1478 data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL); 1479 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1); 1480 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, data); 1481 1482 switch (ctxid) { 1483 case 0x3: 1484 dev_dbg(adev->dev, "Switched to AC mode!\n"); 1485 schedule_work(&smu->interrupt_work); 1486 break; 1487 case 0x4: 1488 dev_dbg(adev->dev, "Switched to DC mode!\n"); 1489 schedule_work(&smu->interrupt_work); 1490 break; 1491 case 0x7: 1492 /* 1493 * Increment the throttle interrupt counter 1494 */ 1495 atomic64_inc(&smu->throttle_int_counter); 1496 1497 if (!atomic_read(&adev->throttling_logging_enabled)) 1498 return 0; 1499 1500 if (__ratelimit(&adev->throttling_logging_rs)) 1501 schedule_work(&smu->throttling_logging_work); 1502 1503 break; 1504 } 1505 } 1506 } 1507 1508 return 0; 1509 } 1510 1511 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs = 1512 { 1513 .set = smu_v11_0_set_irq_state, 1514 .process = smu_v11_0_irq_process, 1515 }; 1516 1517 int smu_v11_0_register_irq_handler(struct smu_context *smu) 1518 { 1519 struct amdgpu_device *adev = smu->adev; 1520 struct amdgpu_irq_src *irq_src = &smu->irq_source; 1521 int ret = 0; 1522 1523 irq_src->num_types = 1; 1524 irq_src->funcs = &smu_v11_0_irq_funcs; 1525 1526 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, 1527 THM_11_0__SRCID__THM_DIG_THERM_L2H, 1528 irq_src); 1529 if (ret) 1530 return ret; 1531 1532 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, 1533 THM_11_0__SRCID__THM_DIG_THERM_H2L, 1534 irq_src); 1535 if (ret) 1536 return ret; 1537 1538 /* Register CTF(GPIO_19) interrupt */ 1539 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO, 1540 SMUIO_11_0__SRCID__SMUIO_GPIO19, 1541 irq_src); 1542 if (ret) 1543 return ret; 1544 1545 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1, 1546 0xfe, 1547 irq_src); 1548 if (ret) 1549 return ret; 1550 1551 return ret; 1552 } 1553 1554 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu, 1555 struct pp_smu_nv_clock_table *max_clocks) 1556 { 1557 struct smu_table_context *table_context = &smu->smu_table; 1558 struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL; 1559 1560 if (!max_clocks || !table_context->max_sustainable_clocks) 1561 return -EINVAL; 1562 1563 sustainable_clocks = table_context->max_sustainable_clocks; 1564 1565 max_clocks->dcfClockInKhz = 1566 (unsigned int) sustainable_clocks->dcef_clock * 1000; 1567 max_clocks->displayClockInKhz = 1568 (unsigned int) sustainable_clocks->display_clock * 1000; 1569 max_clocks->phyClockInKhz = 1570 (unsigned int) sustainable_clocks->phy_clock * 1000; 1571 max_clocks->pixelClockInKhz = 1572 (unsigned int) sustainable_clocks->pixel_clock * 1000; 1573 max_clocks->uClockInKhz = 1574 (unsigned int) sustainable_clocks->uclock * 1000; 1575 max_clocks->socClockInKhz = 1576 (unsigned int) sustainable_clocks->soc_clock * 1000; 1577 max_clocks->dscClockInKhz = 0; 1578 max_clocks->dppClockInKhz = 0; 1579 max_clocks->fabricClockInKhz = 0; 1580 1581 return 0; 1582 } 1583 1584 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu) 1585 { 1586 return smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL); 1587 } 1588 1589 int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, 1590 enum smu_baco_seq baco_seq) 1591 { 1592 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL); 1593 } 1594 1595 bool smu_v11_0_baco_is_support(struct smu_context *smu) 1596 { 1597 struct smu_baco_context *smu_baco = &smu->smu_baco; 1598 1599 if (amdgpu_sriov_vf(smu->adev) || !smu_baco->platform_support) 1600 return false; 1601 1602 /* return true if ASIC is in BACO state already */ 1603 if (smu_v11_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER) 1604 return true; 1605 1606 /* Arcturus does not support this bit mask */ 1607 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) && 1608 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) 1609 return false; 1610 1611 return true; 1612 } 1613 1614 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu) 1615 { 1616 struct smu_baco_context *smu_baco = &smu->smu_baco; 1617 1618 return smu_baco->state; 1619 } 1620 1621 #define D3HOT_BACO_SEQUENCE 0 1622 #define D3HOT_BAMACO_SEQUENCE 2 1623 1624 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state) 1625 { 1626 struct smu_baco_context *smu_baco = &smu->smu_baco; 1627 struct amdgpu_device *adev = smu->adev; 1628 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1629 uint32_t data; 1630 int ret = 0; 1631 1632 if (smu_v11_0_baco_get_state(smu) == state) 1633 return 0; 1634 1635 if (state == SMU_BACO_STATE_ENTER) { 1636 switch (adev->ip_versions[MP1_HWIP][0]) { 1637 case IP_VERSION(11, 0, 7): 1638 case IP_VERSION(11, 0, 11): 1639 case IP_VERSION(11, 0, 12): 1640 case IP_VERSION(11, 0, 13): 1641 if (amdgpu_runtime_pm == 2) 1642 ret = smu_cmn_send_smc_msg_with_param(smu, 1643 SMU_MSG_EnterBaco, 1644 D3HOT_BAMACO_SEQUENCE, 1645 NULL); 1646 else 1647 ret = smu_cmn_send_smc_msg_with_param(smu, 1648 SMU_MSG_EnterBaco, 1649 D3HOT_BACO_SEQUENCE, 1650 NULL); 1651 break; 1652 default: 1653 if (!ras || !adev->ras_enabled || 1654 adev->gmc.xgmi.pending_reset) { 1655 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 2)) { 1656 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT); 1657 data |= 0x80000000; 1658 WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT, data); 1659 } else { 1660 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL); 1661 data |= 0x80000000; 1662 WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data); 1663 } 1664 1665 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL); 1666 } else { 1667 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1, NULL); 1668 } 1669 break; 1670 } 1671 1672 } else { 1673 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL); 1674 if (ret) 1675 return ret; 1676 1677 /* clear vbios scratch 6 and 7 for coming asic reinit */ 1678 WREG32(adev->bios_scratch_reg_offset + 6, 0); 1679 WREG32(adev->bios_scratch_reg_offset + 7, 0); 1680 } 1681 1682 if (!ret) 1683 smu_baco->state = state; 1684 1685 return ret; 1686 } 1687 1688 int smu_v11_0_baco_enter(struct smu_context *smu) 1689 { 1690 int ret = 0; 1691 1692 ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER); 1693 if (ret) 1694 return ret; 1695 1696 msleep(10); 1697 1698 return ret; 1699 } 1700 1701 int smu_v11_0_baco_exit(struct smu_context *smu) 1702 { 1703 int ret; 1704 1705 ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT); 1706 if (!ret) { 1707 /* 1708 * Poll BACO exit status to ensure FW has completed 1709 * BACO exit process to avoid timing issues. 1710 */ 1711 smu_v11_0_poll_baco_exit(smu); 1712 } 1713 1714 return ret; 1715 } 1716 1717 int smu_v11_0_mode1_reset(struct smu_context *smu) 1718 { 1719 int ret = 0; 1720 1721 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL); 1722 if (!ret) 1723 msleep(SMU11_MODE1_RESET_WAIT_TIME_IN_MS); 1724 1725 return ret; 1726 } 1727 1728 int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable) 1729 { 1730 int ret = 0; 1731 1732 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LightSBR, enable ? 1 : 0, NULL); 1733 1734 return ret; 1735 } 1736 1737 1738 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 1739 uint32_t *min, uint32_t *max) 1740 { 1741 int ret = 0, clk_id = 0; 1742 uint32_t param = 0; 1743 uint32_t clock_limit; 1744 1745 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { 1746 switch (clk_type) { 1747 case SMU_MCLK: 1748 case SMU_UCLK: 1749 clock_limit = smu->smu_table.boot_values.uclk; 1750 break; 1751 case SMU_GFXCLK: 1752 case SMU_SCLK: 1753 clock_limit = smu->smu_table.boot_values.gfxclk; 1754 break; 1755 case SMU_SOCCLK: 1756 clock_limit = smu->smu_table.boot_values.socclk; 1757 break; 1758 default: 1759 clock_limit = 0; 1760 break; 1761 } 1762 1763 /* clock in Mhz unit */ 1764 if (min) 1765 *min = clock_limit / 100; 1766 if (max) 1767 *max = clock_limit / 100; 1768 1769 return 0; 1770 } 1771 1772 clk_id = smu_cmn_to_asic_specific_index(smu, 1773 CMN2ASIC_MAPPING_CLK, 1774 clk_type); 1775 if (clk_id < 0) { 1776 ret = -EINVAL; 1777 goto failed; 1778 } 1779 param = (clk_id & 0xffff) << 16; 1780 1781 if (max) { 1782 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max); 1783 if (ret) 1784 goto failed; 1785 } 1786 1787 if (min) { 1788 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min); 1789 if (ret) 1790 goto failed; 1791 } 1792 1793 failed: 1794 return ret; 1795 } 1796 1797 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, 1798 enum smu_clk_type clk_type, 1799 uint32_t min, 1800 uint32_t max) 1801 { 1802 int ret = 0, clk_id = 0; 1803 uint32_t param; 1804 1805 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1806 return 0; 1807 1808 clk_id = smu_cmn_to_asic_specific_index(smu, 1809 CMN2ASIC_MAPPING_CLK, 1810 clk_type); 1811 if (clk_id < 0) 1812 return clk_id; 1813 1814 if (max > 0) { 1815 param = (uint32_t)((clk_id << 16) | (max & 0xffff)); 1816 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq, 1817 param, NULL); 1818 if (ret) 1819 goto out; 1820 } 1821 1822 if (min > 0) { 1823 param = (uint32_t)((clk_id << 16) | (min & 0xffff)); 1824 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq, 1825 param, NULL); 1826 if (ret) 1827 goto out; 1828 } 1829 1830 out: 1831 return ret; 1832 } 1833 1834 int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu, 1835 enum smu_clk_type clk_type, 1836 uint32_t min, 1837 uint32_t max) 1838 { 1839 int ret = 0, clk_id = 0; 1840 uint32_t param; 1841 1842 if (min <= 0 && max <= 0) 1843 return -EINVAL; 1844 1845 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1846 return 0; 1847 1848 clk_id = smu_cmn_to_asic_specific_index(smu, 1849 CMN2ASIC_MAPPING_CLK, 1850 clk_type); 1851 if (clk_id < 0) 1852 return clk_id; 1853 1854 if (max > 0) { 1855 param = (uint32_t)((clk_id << 16) | (max & 0xffff)); 1856 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq, 1857 param, NULL); 1858 if (ret) 1859 return ret; 1860 } 1861 1862 if (min > 0) { 1863 param = (uint32_t)((clk_id << 16) | (min & 0xffff)); 1864 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq, 1865 param, NULL); 1866 if (ret) 1867 return ret; 1868 } 1869 1870 return ret; 1871 } 1872 1873 int smu_v11_0_set_performance_level(struct smu_context *smu, 1874 enum amd_dpm_forced_level level) 1875 { 1876 struct smu_11_0_dpm_context *dpm_context = 1877 smu->smu_dpm.dpm_context; 1878 struct smu_11_0_dpm_table *gfx_table = 1879 &dpm_context->dpm_tables.gfx_table; 1880 struct smu_11_0_dpm_table *mem_table = 1881 &dpm_context->dpm_tables.uclk_table; 1882 struct smu_11_0_dpm_table *soc_table = 1883 &dpm_context->dpm_tables.soc_table; 1884 struct smu_umd_pstate_table *pstate_table = 1885 &smu->pstate_table; 1886 struct amdgpu_device *adev = smu->adev; 1887 uint32_t sclk_min = 0, sclk_max = 0; 1888 uint32_t mclk_min = 0, mclk_max = 0; 1889 uint32_t socclk_min = 0, socclk_max = 0; 1890 int ret = 0; 1891 1892 switch (level) { 1893 case AMD_DPM_FORCED_LEVEL_HIGH: 1894 sclk_min = sclk_max = gfx_table->max; 1895 mclk_min = mclk_max = mem_table->max; 1896 socclk_min = socclk_max = soc_table->max; 1897 break; 1898 case AMD_DPM_FORCED_LEVEL_LOW: 1899 sclk_min = sclk_max = gfx_table->min; 1900 mclk_min = mclk_max = mem_table->min; 1901 socclk_min = socclk_max = soc_table->min; 1902 break; 1903 case AMD_DPM_FORCED_LEVEL_AUTO: 1904 sclk_min = gfx_table->min; 1905 sclk_max = gfx_table->max; 1906 mclk_min = mem_table->min; 1907 mclk_max = mem_table->max; 1908 socclk_min = soc_table->min; 1909 socclk_max = soc_table->max; 1910 break; 1911 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1912 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard; 1913 mclk_min = mclk_max = pstate_table->uclk_pstate.standard; 1914 socclk_min = socclk_max = pstate_table->socclk_pstate.standard; 1915 break; 1916 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1917 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min; 1918 break; 1919 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1920 mclk_min = mclk_max = pstate_table->uclk_pstate.min; 1921 break; 1922 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1923 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak; 1924 mclk_min = mclk_max = pstate_table->uclk_pstate.peak; 1925 socclk_min = socclk_max = pstate_table->socclk_pstate.peak; 1926 break; 1927 case AMD_DPM_FORCED_LEVEL_MANUAL: 1928 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1929 return 0; 1930 default: 1931 dev_err(adev->dev, "Invalid performance level %d\n", level); 1932 return -EINVAL; 1933 } 1934 1935 /* 1936 * Separate MCLK and SOCCLK soft min/max settings are not allowed 1937 * on Arcturus. 1938 */ 1939 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 2)) { 1940 mclk_min = mclk_max = 0; 1941 socclk_min = socclk_max = 0; 1942 } 1943 1944 if (sclk_min && sclk_max) { 1945 ret = smu_v11_0_set_soft_freq_limited_range(smu, 1946 SMU_GFXCLK, 1947 sclk_min, 1948 sclk_max); 1949 if (ret) 1950 return ret; 1951 } 1952 1953 if (mclk_min && mclk_max) { 1954 ret = smu_v11_0_set_soft_freq_limited_range(smu, 1955 SMU_MCLK, 1956 mclk_min, 1957 mclk_max); 1958 if (ret) 1959 return ret; 1960 } 1961 1962 if (socclk_min && socclk_max) { 1963 ret = smu_v11_0_set_soft_freq_limited_range(smu, 1964 SMU_SOCCLK, 1965 socclk_min, 1966 socclk_max); 1967 if (ret) 1968 return ret; 1969 } 1970 1971 return ret; 1972 } 1973 1974 int smu_v11_0_set_power_source(struct smu_context *smu, 1975 enum smu_power_src_type power_src) 1976 { 1977 int pwr_source; 1978 1979 pwr_source = smu_cmn_to_asic_specific_index(smu, 1980 CMN2ASIC_MAPPING_PWR, 1981 (uint32_t)power_src); 1982 if (pwr_source < 0) 1983 return -EINVAL; 1984 1985 return smu_cmn_send_smc_msg_with_param(smu, 1986 SMU_MSG_NotifyPowerSource, 1987 pwr_source, 1988 NULL); 1989 } 1990 1991 int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu, 1992 enum smu_clk_type clk_type, 1993 uint16_t level, 1994 uint32_t *value) 1995 { 1996 int ret = 0, clk_id = 0; 1997 uint32_t param; 1998 1999 if (!value) 2000 return -EINVAL; 2001 2002 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 2003 return 0; 2004 2005 clk_id = smu_cmn_to_asic_specific_index(smu, 2006 CMN2ASIC_MAPPING_CLK, 2007 clk_type); 2008 if (clk_id < 0) 2009 return clk_id; 2010 2011 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff)); 2012 2013 ret = smu_cmn_send_smc_msg_with_param(smu, 2014 SMU_MSG_GetDpmFreqByIndex, 2015 param, 2016 value); 2017 if (ret) 2018 return ret; 2019 2020 /* 2021 * BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM 2022 * now, we un-support it 2023 */ 2024 *value = *value & 0x7fffffff; 2025 2026 return ret; 2027 } 2028 2029 int smu_v11_0_get_dpm_level_count(struct smu_context *smu, 2030 enum smu_clk_type clk_type, 2031 uint32_t *value) 2032 { 2033 return smu_v11_0_get_dpm_freq_by_index(smu, 2034 clk_type, 2035 0xff, 2036 value); 2037 } 2038 2039 int smu_v11_0_set_single_dpm_table(struct smu_context *smu, 2040 enum smu_clk_type clk_type, 2041 struct smu_11_0_dpm_table *single_dpm_table) 2042 { 2043 int ret = 0; 2044 uint32_t clk; 2045 int i; 2046 2047 ret = smu_v11_0_get_dpm_level_count(smu, 2048 clk_type, 2049 &single_dpm_table->count); 2050 if (ret) { 2051 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__); 2052 return ret; 2053 } 2054 2055 for (i = 0; i < single_dpm_table->count; i++) { 2056 ret = smu_v11_0_get_dpm_freq_by_index(smu, 2057 clk_type, 2058 i, 2059 &clk); 2060 if (ret) { 2061 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__); 2062 return ret; 2063 } 2064 2065 single_dpm_table->dpm_levels[i].value = clk; 2066 single_dpm_table->dpm_levels[i].enabled = true; 2067 2068 if (i == 0) 2069 single_dpm_table->min = clk; 2070 else if (i == single_dpm_table->count - 1) 2071 single_dpm_table->max = clk; 2072 } 2073 2074 return 0; 2075 } 2076 2077 int smu_v11_0_get_dpm_level_range(struct smu_context *smu, 2078 enum smu_clk_type clk_type, 2079 uint32_t *min_value, 2080 uint32_t *max_value) 2081 { 2082 uint32_t level_count = 0; 2083 int ret = 0; 2084 2085 if (!min_value && !max_value) 2086 return -EINVAL; 2087 2088 if (min_value) { 2089 /* by default, level 0 clock value as min value */ 2090 ret = smu_v11_0_get_dpm_freq_by_index(smu, 2091 clk_type, 2092 0, 2093 min_value); 2094 if (ret) 2095 return ret; 2096 } 2097 2098 if (max_value) { 2099 ret = smu_v11_0_get_dpm_level_count(smu, 2100 clk_type, 2101 &level_count); 2102 if (ret) 2103 return ret; 2104 2105 ret = smu_v11_0_get_dpm_freq_by_index(smu, 2106 clk_type, 2107 level_count - 1, 2108 max_value); 2109 if (ret) 2110 return ret; 2111 } 2112 2113 return ret; 2114 } 2115 2116 int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu) 2117 { 2118 struct amdgpu_device *adev = smu->adev; 2119 2120 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & 2121 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) 2122 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; 2123 } 2124 2125 uint16_t smu_v11_0_get_current_pcie_link_width(struct smu_context *smu) 2126 { 2127 uint32_t width_level; 2128 2129 width_level = smu_v11_0_get_current_pcie_link_width_level(smu); 2130 if (width_level > LINK_WIDTH_MAX) 2131 width_level = 0; 2132 2133 return link_width[width_level]; 2134 } 2135 2136 int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu) 2137 { 2138 struct amdgpu_device *adev = smu->adev; 2139 2140 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & 2141 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) 2142 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 2143 } 2144 2145 uint16_t smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu) 2146 { 2147 uint32_t speed_level; 2148 2149 speed_level = smu_v11_0_get_current_pcie_link_speed_level(smu); 2150 if (speed_level > LINK_SPEED_MAX) 2151 speed_level = 0; 2152 2153 return link_speed[speed_level]; 2154 } 2155 2156 int smu_v11_0_gfx_ulv_control(struct smu_context *smu, 2157 bool enablement) 2158 { 2159 int ret = 0; 2160 2161 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT)) 2162 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement); 2163 2164 return ret; 2165 } 2166 2167 int smu_v11_0_deep_sleep_control(struct smu_context *smu, 2168 bool enablement) 2169 { 2170 struct amdgpu_device *adev = smu->adev; 2171 int ret = 0; 2172 2173 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) { 2174 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement); 2175 if (ret) { 2176 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable"); 2177 return ret; 2178 } 2179 } 2180 2181 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) { 2182 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement); 2183 if (ret) { 2184 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable"); 2185 return ret; 2186 } 2187 } 2188 2189 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) { 2190 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement); 2191 if (ret) { 2192 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable"); 2193 return ret; 2194 } 2195 } 2196 2197 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) { 2198 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement); 2199 if (ret) { 2200 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable"); 2201 return ret; 2202 } 2203 } 2204 2205 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) { 2206 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement); 2207 if (ret) { 2208 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable"); 2209 return ret; 2210 } 2211 } 2212 2213 return ret; 2214 } 2215 2216 int smu_v11_0_restore_user_od_settings(struct smu_context *smu) 2217 { 2218 struct smu_table_context *table_context = &smu->smu_table; 2219 void *user_od_table = table_context->user_overdrive_table; 2220 int ret = 0; 2221 2222 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)user_od_table, true); 2223 if (ret) 2224 dev_err(smu->adev->dev, "Failed to import overdrive table!\n"); 2225 2226 return ret; 2227 } 2228 2229 void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu) 2230 { 2231 struct amdgpu_device *adev = smu->adev; 2232 2233 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); 2234 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); 2235 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); 2236 } 2237