1e098bc96SEvan Quan /* 2e098bc96SEvan Quan * Copyright 2019 Advanced Micro Devices, Inc. 3e098bc96SEvan Quan * 4e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"), 6e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation 7e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions: 10e098bc96SEvan Quan * 11e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in 12e098bc96SEvan Quan * all copies or substantial portions of the Software. 13e098bc96SEvan Quan * 14e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21e098bc96SEvan Quan */ 22e098bc96SEvan Quan 23e098bc96SEvan Quan #include <linux/firmware.h> 24e098bc96SEvan Quan #include <linux/module.h> 25e098bc96SEvan Quan #include <linux/pci.h> 26e098bc96SEvan Quan #include <linux/reboot.h> 27e098bc96SEvan Quan 28e098bc96SEvan Quan #define SMU_11_0_PARTIAL_PPTABLE 29e098bc96SEvan Quan #define SWSMU_CODE_LAYER_L3 30e098bc96SEvan Quan 31e098bc96SEvan Quan #include "amdgpu.h" 32e098bc96SEvan Quan #include "amdgpu_smu.h" 33e098bc96SEvan Quan #include "atomfirmware.h" 34e098bc96SEvan Quan #include "amdgpu_atomfirmware.h" 35e098bc96SEvan Quan #include "amdgpu_atombios.h" 36e098bc96SEvan Quan #include "smu_v11_0.h" 37e098bc96SEvan Quan #include "soc15_common.h" 38e098bc96SEvan Quan #include "atom.h" 39e098bc96SEvan Quan #include "amdgpu_ras.h" 40e098bc96SEvan Quan #include "smu_cmn.h" 41e098bc96SEvan Quan 42e098bc96SEvan Quan #include "asic_reg/thm/thm_11_0_2_offset.h" 43e098bc96SEvan Quan #include "asic_reg/thm/thm_11_0_2_sh_mask.h" 44e098bc96SEvan Quan #include "asic_reg/mp/mp_11_0_offset.h" 45e098bc96SEvan Quan #include "asic_reg/mp/mp_11_0_sh_mask.h" 46e098bc96SEvan Quan #include "asic_reg/smuio/smuio_11_0_0_offset.h" 47e098bc96SEvan Quan #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h" 48e098bc96SEvan Quan 49e098bc96SEvan Quan /* 50e098bc96SEvan Quan * DO NOT use these for err/warn/info/debug messages. 51e098bc96SEvan Quan * Use dev_err, dev_warn, dev_info and dev_dbg instead. 52e098bc96SEvan Quan * They are more MGPU friendly. 53e098bc96SEvan Quan */ 54e098bc96SEvan Quan #undef pr_err 55e098bc96SEvan Quan #undef pr_warn 56e098bc96SEvan Quan #undef pr_info 57e098bc96SEvan Quan #undef pr_debug 58e098bc96SEvan Quan 59e098bc96SEvan Quan MODULE_FIRMWARE("amdgpu/arcturus_smc.bin"); 60e098bc96SEvan Quan MODULE_FIRMWARE("amdgpu/navi10_smc.bin"); 61e098bc96SEvan Quan MODULE_FIRMWARE("amdgpu/navi14_smc.bin"); 62e098bc96SEvan Quan MODULE_FIRMWARE("amdgpu/navi12_smc.bin"); 63e098bc96SEvan Quan MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin"); 64e098bc96SEvan Quan MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin"); 65db1f8a8fSTao Zhou MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin"); 664d352669SChengming Gui MODULE_FIRMWARE("amdgpu/beige_goby_smc.bin"); 67e098bc96SEvan Quan 68e098bc96SEvan Quan #define SMU11_VOLTAGE_SCALE 4 69e098bc96SEvan Quan 70e098bc96SEvan Quan #define SMU11_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms 71e098bc96SEvan Quan 72e098bc96SEvan Quan #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 73e098bc96SEvan Quan #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L 74e098bc96SEvan Quan #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 75e098bc96SEvan Quan #define smnPCIE_LC_SPEED_CNTL 0x11140290 76e098bc96SEvan Quan #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000 77e098bc96SEvan Quan #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE 78e098bc96SEvan Quan 79e9995d4aSEvan Quan #define mmTHM_BACO_CNTL_ARCT 0xA7 80e9995d4aSEvan Quan #define mmTHM_BACO_CNTL_ARCT_BASE_IDX 0 81e9995d4aSEvan Quan 82e098bc96SEvan Quan int smu_v11_0_init_microcode(struct smu_context *smu) 83e098bc96SEvan Quan { 84e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 85e098bc96SEvan Quan const char *chip_name; 8610e0d9ebSTao Zhou char fw_name[SMU_FW_NAME_LEN]; 87e098bc96SEvan Quan int err = 0; 88e098bc96SEvan Quan const struct smc_firmware_header_v1_0 *hdr; 89e098bc96SEvan Quan const struct common_firmware_header *header; 90e098bc96SEvan Quan struct amdgpu_firmware_info *ucode = NULL; 91e098bc96SEvan Quan 9286b6037fSStanley.Yang if (amdgpu_sriov_vf(adev) && 9386b6037fSStanley.Yang ((adev->asic_type == CHIP_NAVI12) || 9486b6037fSStanley.Yang (adev->asic_type == CHIP_SIENNA_CICHLID))) 9586b6037fSStanley.Yang return 0; 9686b6037fSStanley.Yang 97e098bc96SEvan Quan switch (adev->asic_type) { 98e098bc96SEvan Quan case CHIP_ARCTURUS: 99e098bc96SEvan Quan chip_name = "arcturus"; 100e098bc96SEvan Quan break; 101e098bc96SEvan Quan case CHIP_NAVI10: 102e098bc96SEvan Quan chip_name = "navi10"; 103e098bc96SEvan Quan break; 104e098bc96SEvan Quan case CHIP_NAVI14: 105e098bc96SEvan Quan chip_name = "navi14"; 106e098bc96SEvan Quan break; 107e098bc96SEvan Quan case CHIP_NAVI12: 108e098bc96SEvan Quan chip_name = "navi12"; 109e098bc96SEvan Quan break; 110e098bc96SEvan Quan case CHIP_SIENNA_CICHLID: 111e098bc96SEvan Quan chip_name = "sienna_cichlid"; 112e098bc96SEvan Quan break; 113e098bc96SEvan Quan case CHIP_NAVY_FLOUNDER: 114e098bc96SEvan Quan chip_name = "navy_flounder"; 115e098bc96SEvan Quan break; 116db1f8a8fSTao Zhou case CHIP_DIMGREY_CAVEFISH: 117db1f8a8fSTao Zhou chip_name = "dimgrey_cavefish"; 118db1f8a8fSTao Zhou break; 1194d352669SChengming Gui case CHIP_BEIGE_GOBY: 1204d352669SChengming Gui chip_name = "beige_goby"; 1214d352669SChengming Gui break; 122e098bc96SEvan Quan default: 123e098bc96SEvan Quan dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type); 124e098bc96SEvan Quan return -EINVAL; 125e098bc96SEvan Quan } 126e098bc96SEvan Quan 127e098bc96SEvan Quan snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name); 128e098bc96SEvan Quan 129e098bc96SEvan Quan err = request_firmware(&adev->pm.fw, fw_name, adev->dev); 130e098bc96SEvan Quan if (err) 131e098bc96SEvan Quan goto out; 132e098bc96SEvan Quan err = amdgpu_ucode_validate(adev->pm.fw); 133e098bc96SEvan Quan if (err) 134e098bc96SEvan Quan goto out; 135e098bc96SEvan Quan 136e098bc96SEvan Quan hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 137e098bc96SEvan Quan amdgpu_ucode_print_smc_hdr(&hdr->header); 138e098bc96SEvan Quan adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version); 139e098bc96SEvan Quan 140e098bc96SEvan Quan if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 141e098bc96SEvan Quan ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 142e098bc96SEvan Quan ucode->ucode_id = AMDGPU_UCODE_ID_SMC; 143e098bc96SEvan Quan ucode->fw = adev->pm.fw; 144e098bc96SEvan Quan header = (const struct common_firmware_header *)ucode->fw->data; 145e098bc96SEvan Quan adev->firmware.fw_size += 146e098bc96SEvan Quan ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 147e098bc96SEvan Quan } 148e098bc96SEvan Quan 149e098bc96SEvan Quan out: 150e098bc96SEvan Quan if (err) { 151e098bc96SEvan Quan DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n", 152e098bc96SEvan Quan fw_name); 153e098bc96SEvan Quan release_firmware(adev->pm.fw); 154e098bc96SEvan Quan adev->pm.fw = NULL; 155e098bc96SEvan Quan } 156e098bc96SEvan Quan return err; 157e098bc96SEvan Quan } 158e098bc96SEvan Quan 159e098bc96SEvan Quan void smu_v11_0_fini_microcode(struct smu_context *smu) 160e098bc96SEvan Quan { 161e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 162e098bc96SEvan Quan 163e098bc96SEvan Quan release_firmware(adev->pm.fw); 164e098bc96SEvan Quan adev->pm.fw = NULL; 165e098bc96SEvan Quan adev->pm.fw_version = 0; 166e098bc96SEvan Quan } 167e098bc96SEvan Quan 168e098bc96SEvan Quan int smu_v11_0_load_microcode(struct smu_context *smu) 169e098bc96SEvan Quan { 170e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 171e098bc96SEvan Quan const uint32_t *src; 172e098bc96SEvan Quan const struct smc_firmware_header_v1_0 *hdr; 173e098bc96SEvan Quan uint32_t addr_start = MP1_SRAM; 174e098bc96SEvan Quan uint32_t i; 175e098bc96SEvan Quan uint32_t smc_fw_size; 176e098bc96SEvan Quan uint32_t mp1_fw_flags; 177e098bc96SEvan Quan 178e098bc96SEvan Quan hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 179e098bc96SEvan Quan src = (const uint32_t *)(adev->pm.fw->data + 180e098bc96SEvan Quan le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 181e098bc96SEvan Quan smc_fw_size = hdr->header.ucode_size_bytes; 182e098bc96SEvan Quan 183e098bc96SEvan Quan for (i = 1; i < smc_fw_size/4 - 1; i++) { 184e098bc96SEvan Quan WREG32_PCIE(addr_start, src[i]); 185e098bc96SEvan Quan addr_start += 4; 186e098bc96SEvan Quan } 187e098bc96SEvan Quan 188e098bc96SEvan Quan WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), 189e098bc96SEvan Quan 1 & MP1_SMN_PUB_CTRL__RESET_MASK); 190e098bc96SEvan Quan WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), 191e098bc96SEvan Quan 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK); 192e098bc96SEvan Quan 193e098bc96SEvan Quan for (i = 0; i < adev->usec_timeout; i++) { 194e098bc96SEvan Quan mp1_fw_flags = RREG32_PCIE(MP1_Public | 195e098bc96SEvan Quan (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); 196e098bc96SEvan Quan if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 197e098bc96SEvan Quan MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 198e098bc96SEvan Quan break; 199e098bc96SEvan Quan udelay(1); 200e098bc96SEvan Quan } 201e098bc96SEvan Quan 202e098bc96SEvan Quan if (i == adev->usec_timeout) 203e098bc96SEvan Quan return -ETIME; 204e098bc96SEvan Quan 205e098bc96SEvan Quan return 0; 206e098bc96SEvan Quan } 207e098bc96SEvan Quan 208e098bc96SEvan Quan int smu_v11_0_check_fw_status(struct smu_context *smu) 209e098bc96SEvan Quan { 210e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 211e098bc96SEvan Quan uint32_t mp1_fw_flags; 212e098bc96SEvan Quan 213e098bc96SEvan Quan mp1_fw_flags = RREG32_PCIE(MP1_Public | 214e098bc96SEvan Quan (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); 215e098bc96SEvan Quan 216e098bc96SEvan Quan if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 217e098bc96SEvan Quan MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 218e098bc96SEvan Quan return 0; 219e098bc96SEvan Quan 220e098bc96SEvan Quan return -EIO; 221e098bc96SEvan Quan } 222e098bc96SEvan Quan 223e098bc96SEvan Quan int smu_v11_0_check_fw_version(struct smu_context *smu) 224e098bc96SEvan Quan { 225dda818a0SAlex Deucher struct amdgpu_device *adev = smu->adev; 226e098bc96SEvan Quan uint32_t if_version = 0xff, smu_version = 0xff; 227e098bc96SEvan Quan uint16_t smu_major; 228e098bc96SEvan Quan uint8_t smu_minor, smu_debug; 229e098bc96SEvan Quan int ret = 0; 230e098bc96SEvan Quan 231e098bc96SEvan Quan ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 232e098bc96SEvan Quan if (ret) 233e098bc96SEvan Quan return ret; 234e098bc96SEvan Quan 235e098bc96SEvan Quan smu_major = (smu_version >> 16) & 0xffff; 236e098bc96SEvan Quan smu_minor = (smu_version >> 8) & 0xff; 237e098bc96SEvan Quan smu_debug = (smu_version >> 0) & 0xff; 238dda818a0SAlex Deucher if (smu->is_apu) 239dda818a0SAlex Deucher adev->pm.fw_version = smu_version; 240e098bc96SEvan Quan 241e098bc96SEvan Quan switch (smu->adev->asic_type) { 242e098bc96SEvan Quan case CHIP_ARCTURUS: 243e098bc96SEvan Quan smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT; 244e098bc96SEvan Quan break; 245e098bc96SEvan Quan case CHIP_NAVI10: 246e098bc96SEvan Quan smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10; 247e098bc96SEvan Quan break; 248e098bc96SEvan Quan case CHIP_NAVI12: 249e098bc96SEvan Quan smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12; 250e098bc96SEvan Quan break; 251e098bc96SEvan Quan case CHIP_NAVI14: 252e098bc96SEvan Quan smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14; 253e098bc96SEvan Quan break; 254e098bc96SEvan Quan case CHIP_SIENNA_CICHLID: 255e098bc96SEvan Quan smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid; 256e098bc96SEvan Quan break; 257e098bc96SEvan Quan case CHIP_NAVY_FLOUNDER: 258e098bc96SEvan Quan smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder; 259e098bc96SEvan Quan break; 26088779658SXiaojian Du case CHIP_VANGOGH: 26188779658SXiaojian Du smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VANGOGH; 26288779658SXiaojian Du break; 263db1f8a8fSTao Zhou case CHIP_DIMGREY_CAVEFISH: 264db1f8a8fSTao Zhou smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish; 265db1f8a8fSTao Zhou break; 2664d352669SChengming Gui case CHIP_BEIGE_GOBY: 2674d352669SChengming Gui smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Beige_Goby; 2684d352669SChengming Gui break; 269e098bc96SEvan Quan default: 270e098bc96SEvan Quan dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type); 271e098bc96SEvan Quan smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV; 272e098bc96SEvan Quan break; 273e098bc96SEvan Quan } 274e098bc96SEvan Quan 275e098bc96SEvan Quan /* 276e098bc96SEvan Quan * 1. if_version mismatch is not critical as our fw is designed 277e098bc96SEvan Quan * to be backward compatible. 278e098bc96SEvan Quan * 2. New fw usually brings some optimizations. But that's visible 279e098bc96SEvan Quan * only on the paired driver. 280e098bc96SEvan Quan * Considering above, we just leave user a warning message instead 281e098bc96SEvan Quan * of halt driver loading. 282e098bc96SEvan Quan */ 283e098bc96SEvan Quan if (if_version != smu->smc_driver_if_version) { 284e098bc96SEvan Quan dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, " 285e098bc96SEvan Quan "smu fw version = 0x%08x (%d.%d.%d)\n", 286e098bc96SEvan Quan smu->smc_driver_if_version, if_version, 287e098bc96SEvan Quan smu_version, smu_major, smu_minor, smu_debug); 288e098bc96SEvan Quan dev_warn(smu->adev->dev, "SMU driver if version not matched\n"); 289e098bc96SEvan Quan } 290e098bc96SEvan Quan 291e098bc96SEvan Quan return ret; 292e098bc96SEvan Quan } 293e098bc96SEvan Quan 294e098bc96SEvan Quan static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size) 295e098bc96SEvan Quan { 296e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 297e098bc96SEvan Quan uint32_t ppt_offset_bytes; 298e098bc96SEvan Quan const struct smc_firmware_header_v2_0 *v2; 299e098bc96SEvan Quan 300e098bc96SEvan Quan v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data; 301e098bc96SEvan Quan 302e098bc96SEvan Quan ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes); 303e098bc96SEvan Quan *size = le32_to_cpu(v2->ppt_size_bytes); 304e098bc96SEvan Quan *table = (uint8_t *)v2 + ppt_offset_bytes; 305e098bc96SEvan Quan 306e098bc96SEvan Quan return 0; 307e098bc96SEvan Quan } 308e098bc96SEvan Quan 309e098bc96SEvan Quan static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table, 310e098bc96SEvan Quan uint32_t *size, uint32_t pptable_id) 311e098bc96SEvan Quan { 312e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 313e098bc96SEvan Quan const struct smc_firmware_header_v2_1 *v2_1; 314e098bc96SEvan Quan struct smc_soft_pptable_entry *entries; 315e098bc96SEvan Quan uint32_t pptable_count = 0; 316e098bc96SEvan Quan int i = 0; 317e098bc96SEvan Quan 318e098bc96SEvan Quan v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data; 319e098bc96SEvan Quan entries = (struct smc_soft_pptable_entry *) 320e098bc96SEvan Quan ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset)); 321e098bc96SEvan Quan pptable_count = le32_to_cpu(v2_1->pptable_count); 322e098bc96SEvan Quan for (i = 0; i < pptable_count; i++) { 323e098bc96SEvan Quan if (le32_to_cpu(entries[i].id) == pptable_id) { 324e098bc96SEvan Quan *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes)); 325e098bc96SEvan Quan *size = le32_to_cpu(entries[i].ppt_size_bytes); 326e098bc96SEvan Quan break; 327e098bc96SEvan Quan } 328e098bc96SEvan Quan } 329e098bc96SEvan Quan 330e098bc96SEvan Quan if (i == pptable_count) 331e098bc96SEvan Quan return -EINVAL; 332e098bc96SEvan Quan 333e098bc96SEvan Quan return 0; 334e098bc96SEvan Quan } 335e098bc96SEvan Quan 336e098bc96SEvan Quan int smu_v11_0_setup_pptable(struct smu_context *smu) 337e098bc96SEvan Quan { 338e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 339e098bc96SEvan Quan const struct smc_firmware_header_v1_0 *hdr; 340e098bc96SEvan Quan int ret, index; 341e098bc96SEvan Quan uint32_t size = 0; 342e098bc96SEvan Quan uint16_t atom_table_size; 343e098bc96SEvan Quan uint8_t frev, crev; 344e098bc96SEvan Quan void *table; 345e098bc96SEvan Quan uint16_t version_major, version_minor; 346e098bc96SEvan Quan 3477c67d74dSJingwen Chen if (!amdgpu_sriov_vf(adev)) { 348e098bc96SEvan Quan hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 349e098bc96SEvan Quan version_major = le16_to_cpu(hdr->header.header_version_major); 350e098bc96SEvan Quan version_minor = le16_to_cpu(hdr->header.header_version_minor); 351ac79f42aSChengming Gui if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) { 352e098bc96SEvan Quan dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id); 353e098bc96SEvan Quan switch (version_minor) { 354e098bc96SEvan Quan case 0: 355e098bc96SEvan Quan ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size); 356e098bc96SEvan Quan break; 357e098bc96SEvan Quan case 1: 358e098bc96SEvan Quan ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size, 359e098bc96SEvan Quan smu->smu_table.boot_values.pp_table_id); 360e098bc96SEvan Quan break; 361e098bc96SEvan Quan default: 362e098bc96SEvan Quan ret = -EINVAL; 363e098bc96SEvan Quan break; 364e098bc96SEvan Quan } 365e098bc96SEvan Quan if (ret) 366e098bc96SEvan Quan return ret; 3677c67d74dSJingwen Chen goto out; 3687c67d74dSJingwen Chen } 3697c67d74dSJingwen Chen } 370e098bc96SEvan Quan 371e098bc96SEvan Quan dev_info(adev->dev, "use vbios provided pptable\n"); 372e098bc96SEvan Quan index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 373e098bc96SEvan Quan powerplayinfo); 374e098bc96SEvan Quan 375e098bc96SEvan Quan ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev, 376e098bc96SEvan Quan (uint8_t **)&table); 377e098bc96SEvan Quan if (ret) 378e098bc96SEvan Quan return ret; 379e098bc96SEvan Quan size = atom_table_size; 380e098bc96SEvan Quan 3817c67d74dSJingwen Chen out: 382e098bc96SEvan Quan if (!smu->smu_table.power_play_table) 383e098bc96SEvan Quan smu->smu_table.power_play_table = table; 384e098bc96SEvan Quan if (!smu->smu_table.power_play_table_size) 385e098bc96SEvan Quan smu->smu_table.power_play_table_size = size; 386e098bc96SEvan Quan 387e098bc96SEvan Quan return 0; 388e098bc96SEvan Quan } 389e098bc96SEvan Quan 390e098bc96SEvan Quan int smu_v11_0_init_smc_tables(struct smu_context *smu) 391e098bc96SEvan Quan { 392e098bc96SEvan Quan struct smu_table_context *smu_table = &smu->smu_table; 393e098bc96SEvan Quan struct smu_table *tables = smu_table->tables; 394e098bc96SEvan Quan int ret = 0; 395e098bc96SEvan Quan 396e098bc96SEvan Quan smu_table->driver_pptable = 397e098bc96SEvan Quan kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL); 398e098bc96SEvan Quan if (!smu_table->driver_pptable) { 399e098bc96SEvan Quan ret = -ENOMEM; 400e098bc96SEvan Quan goto err0_out; 401e098bc96SEvan Quan } 402e098bc96SEvan Quan 403e098bc96SEvan Quan smu_table->max_sustainable_clocks = 404e098bc96SEvan Quan kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks), GFP_KERNEL); 405e098bc96SEvan Quan if (!smu_table->max_sustainable_clocks) { 406e098bc96SEvan Quan ret = -ENOMEM; 407e098bc96SEvan Quan goto err1_out; 408e098bc96SEvan Quan } 409e098bc96SEvan Quan 410e098bc96SEvan Quan /* Arcturus does not support OVERDRIVE */ 411e098bc96SEvan Quan if (tables[SMU_TABLE_OVERDRIVE].size) { 412e098bc96SEvan Quan smu_table->overdrive_table = 413e098bc96SEvan Quan kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); 414e098bc96SEvan Quan if (!smu_table->overdrive_table) { 415e098bc96SEvan Quan ret = -ENOMEM; 416e098bc96SEvan Quan goto err2_out; 417e098bc96SEvan Quan } 418e098bc96SEvan Quan 419e098bc96SEvan Quan smu_table->boot_overdrive_table = 420e098bc96SEvan Quan kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); 421e098bc96SEvan Quan if (!smu_table->boot_overdrive_table) { 422e098bc96SEvan Quan ret = -ENOMEM; 423e098bc96SEvan Quan goto err3_out; 424e098bc96SEvan Quan } 425e098bc96SEvan Quan } 426e098bc96SEvan Quan 427e098bc96SEvan Quan return 0; 428e098bc96SEvan Quan 429e098bc96SEvan Quan err3_out: 430e098bc96SEvan Quan kfree(smu_table->overdrive_table); 431e098bc96SEvan Quan err2_out: 432e098bc96SEvan Quan kfree(smu_table->max_sustainable_clocks); 433e098bc96SEvan Quan err1_out: 434e098bc96SEvan Quan kfree(smu_table->driver_pptable); 435e098bc96SEvan Quan err0_out: 436e098bc96SEvan Quan return ret; 437e098bc96SEvan Quan } 438e098bc96SEvan Quan 439e098bc96SEvan Quan int smu_v11_0_fini_smc_tables(struct smu_context *smu) 440e098bc96SEvan Quan { 441e098bc96SEvan Quan struct smu_table_context *smu_table = &smu->smu_table; 442e098bc96SEvan Quan struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 443e098bc96SEvan Quan 444e098bc96SEvan Quan kfree(smu_table->gpu_metrics_table); 445e098bc96SEvan Quan kfree(smu_table->boot_overdrive_table); 446e098bc96SEvan Quan kfree(smu_table->overdrive_table); 447e098bc96SEvan Quan kfree(smu_table->max_sustainable_clocks); 448e098bc96SEvan Quan kfree(smu_table->driver_pptable); 449c98ee897SXiaojian Du kfree(smu_table->clocks_table); 450e098bc96SEvan Quan smu_table->gpu_metrics_table = NULL; 451e098bc96SEvan Quan smu_table->boot_overdrive_table = NULL; 452e098bc96SEvan Quan smu_table->overdrive_table = NULL; 453e098bc96SEvan Quan smu_table->max_sustainable_clocks = NULL; 454e098bc96SEvan Quan smu_table->driver_pptable = NULL; 455c98ee897SXiaojian Du smu_table->clocks_table = NULL; 456e098bc96SEvan Quan kfree(smu_table->hardcode_pptable); 457e098bc96SEvan Quan smu_table->hardcode_pptable = NULL; 458e098bc96SEvan Quan 459e098bc96SEvan Quan kfree(smu_table->metrics_table); 460e098bc96SEvan Quan kfree(smu_table->watermarks_table); 461e098bc96SEvan Quan smu_table->metrics_table = NULL; 462e098bc96SEvan Quan smu_table->watermarks_table = NULL; 463e098bc96SEvan Quan smu_table->metrics_time = 0; 464e098bc96SEvan Quan 465e098bc96SEvan Quan kfree(smu_dpm->dpm_context); 466e098bc96SEvan Quan kfree(smu_dpm->golden_dpm_context); 467e098bc96SEvan Quan kfree(smu_dpm->dpm_current_power_state); 468e098bc96SEvan Quan kfree(smu_dpm->dpm_request_power_state); 469e098bc96SEvan Quan smu_dpm->dpm_context = NULL; 470e098bc96SEvan Quan smu_dpm->golden_dpm_context = NULL; 471e098bc96SEvan Quan smu_dpm->dpm_context_size = 0; 472e098bc96SEvan Quan smu_dpm->dpm_current_power_state = NULL; 473e098bc96SEvan Quan smu_dpm->dpm_request_power_state = NULL; 474e098bc96SEvan Quan 475e098bc96SEvan Quan return 0; 476e098bc96SEvan Quan } 477e098bc96SEvan Quan 478e098bc96SEvan Quan int smu_v11_0_init_power(struct smu_context *smu) 479e098bc96SEvan Quan { 480e098bc96SEvan Quan struct smu_power_context *smu_power = &smu->smu_power; 481ae07970aSXiaomeng Hou size_t size = smu->adev->asic_type == CHIP_VANGOGH ? 482ae07970aSXiaomeng Hou sizeof(struct smu_11_5_power_context) : 483ae07970aSXiaomeng Hou sizeof(struct smu_11_0_power_context); 484e098bc96SEvan Quan 485ae07970aSXiaomeng Hou smu_power->power_context = kzalloc(size, GFP_KERNEL); 486e098bc96SEvan Quan if (!smu_power->power_context) 487e098bc96SEvan Quan return -ENOMEM; 488ae07970aSXiaomeng Hou smu_power->power_context_size = size; 489e098bc96SEvan Quan 490e098bc96SEvan Quan return 0; 491e098bc96SEvan Quan } 492e098bc96SEvan Quan 493e098bc96SEvan Quan int smu_v11_0_fini_power(struct smu_context *smu) 494e098bc96SEvan Quan { 495e098bc96SEvan Quan struct smu_power_context *smu_power = &smu->smu_power; 496e098bc96SEvan Quan 497e098bc96SEvan Quan kfree(smu_power->power_context); 498e098bc96SEvan Quan smu_power->power_context = NULL; 499e098bc96SEvan Quan smu_power->power_context_size = 0; 500e098bc96SEvan Quan 501e098bc96SEvan Quan return 0; 502e098bc96SEvan Quan } 503e098bc96SEvan Quan 504e098bc96SEvan Quan static int smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device *adev, 505e098bc96SEvan Quan uint8_t clk_id, 506e098bc96SEvan Quan uint8_t syspll_id, 507e098bc96SEvan Quan uint32_t *clk_freq) 508e098bc96SEvan Quan { 509e098bc96SEvan Quan struct atom_get_smu_clock_info_parameters_v3_1 input = {0}; 510e098bc96SEvan Quan struct atom_get_smu_clock_info_output_parameters_v3_1 *output; 511e098bc96SEvan Quan int ret, index; 512e098bc96SEvan Quan 513e098bc96SEvan Quan input.clk_id = clk_id; 514e098bc96SEvan Quan input.syspll_id = syspll_id; 515e098bc96SEvan Quan input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ; 516e098bc96SEvan Quan index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1, 517e098bc96SEvan Quan getsmuclockinfo); 518e098bc96SEvan Quan 519e098bc96SEvan Quan ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index, 520e098bc96SEvan Quan (uint32_t *)&input); 521e098bc96SEvan Quan if (ret) 522e098bc96SEvan Quan return -EINVAL; 523e098bc96SEvan Quan 524e098bc96SEvan Quan output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input; 525e098bc96SEvan Quan *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000; 526e098bc96SEvan Quan 527e098bc96SEvan Quan return 0; 528e098bc96SEvan Quan } 529e098bc96SEvan Quan 530e098bc96SEvan Quan int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu) 531e098bc96SEvan Quan { 532e098bc96SEvan Quan int ret, index; 533e098bc96SEvan Quan uint16_t size; 534e098bc96SEvan Quan uint8_t frev, crev; 535e098bc96SEvan Quan struct atom_common_table_header *header; 536e098bc96SEvan Quan struct atom_firmware_info_v3_3 *v_3_3; 537e098bc96SEvan Quan struct atom_firmware_info_v3_1 *v_3_1; 538e098bc96SEvan Quan 539e098bc96SEvan Quan index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 540e098bc96SEvan Quan firmwareinfo); 541e098bc96SEvan Quan 542e098bc96SEvan Quan ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev, 543e098bc96SEvan Quan (uint8_t **)&header); 544e098bc96SEvan Quan if (ret) 545e098bc96SEvan Quan return ret; 546e098bc96SEvan Quan 547e098bc96SEvan Quan if (header->format_revision != 3) { 548e098bc96SEvan Quan dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu11\n"); 549e098bc96SEvan Quan return -EINVAL; 550e098bc96SEvan Quan } 551e098bc96SEvan Quan 552e098bc96SEvan Quan switch (header->content_revision) { 553e098bc96SEvan Quan case 0: 554e098bc96SEvan Quan case 1: 555e098bc96SEvan Quan case 2: 556e098bc96SEvan Quan v_3_1 = (struct atom_firmware_info_v3_1 *)header; 557e098bc96SEvan Quan smu->smu_table.boot_values.revision = v_3_1->firmware_revision; 558e098bc96SEvan Quan smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz; 559e098bc96SEvan Quan smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; 560e098bc96SEvan Quan smu->smu_table.boot_values.socclk = 0; 561e098bc96SEvan Quan smu->smu_table.boot_values.dcefclk = 0; 562e098bc96SEvan Quan smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv; 563e098bc96SEvan Quan smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv; 564e098bc96SEvan Quan smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv; 565e098bc96SEvan Quan smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv; 566e098bc96SEvan Quan smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id; 567e098bc96SEvan Quan smu->smu_table.boot_values.pp_table_id = 0; 568a7e660e5SEvan Quan smu->smu_table.boot_values.firmware_caps = v_3_1->firmware_capability; 569e098bc96SEvan Quan break; 570e098bc96SEvan Quan case 3: 5713495d3c3SXiaojian Du case 4: 572e098bc96SEvan Quan default: 573e098bc96SEvan Quan v_3_3 = (struct atom_firmware_info_v3_3 *)header; 574e098bc96SEvan Quan smu->smu_table.boot_values.revision = v_3_3->firmware_revision; 575e098bc96SEvan Quan smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz; 576e098bc96SEvan Quan smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; 577e098bc96SEvan Quan smu->smu_table.boot_values.socclk = 0; 578e098bc96SEvan Quan smu->smu_table.boot_values.dcefclk = 0; 579e098bc96SEvan Quan smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv; 580e098bc96SEvan Quan smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv; 581e098bc96SEvan Quan smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv; 582e098bc96SEvan Quan smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv; 583e098bc96SEvan Quan smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id; 584e098bc96SEvan Quan smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id; 585a7e660e5SEvan Quan smu->smu_table.boot_values.firmware_caps = v_3_3->firmware_capability; 586e098bc96SEvan Quan } 587e098bc96SEvan Quan 588e098bc96SEvan Quan smu->smu_table.boot_values.format_revision = header->format_revision; 589e098bc96SEvan Quan smu->smu_table.boot_values.content_revision = header->content_revision; 590e098bc96SEvan Quan 591e098bc96SEvan Quan smu_v11_0_atom_get_smu_clockinfo(smu->adev, 592e098bc96SEvan Quan (uint8_t)SMU11_SYSPLL0_SOCCLK_ID, 593e098bc96SEvan Quan (uint8_t)0, 594e098bc96SEvan Quan &smu->smu_table.boot_values.socclk); 595e098bc96SEvan Quan 596e098bc96SEvan Quan smu_v11_0_atom_get_smu_clockinfo(smu->adev, 597e098bc96SEvan Quan (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID, 598e098bc96SEvan Quan (uint8_t)0, 599e098bc96SEvan Quan &smu->smu_table.boot_values.dcefclk); 600e098bc96SEvan Quan 601e098bc96SEvan Quan smu_v11_0_atom_get_smu_clockinfo(smu->adev, 602e098bc96SEvan Quan (uint8_t)SMU11_SYSPLL0_ECLK_ID, 603e098bc96SEvan Quan (uint8_t)0, 604e098bc96SEvan Quan &smu->smu_table.boot_values.eclk); 605e098bc96SEvan Quan 606e098bc96SEvan Quan smu_v11_0_atom_get_smu_clockinfo(smu->adev, 607e098bc96SEvan Quan (uint8_t)SMU11_SYSPLL0_VCLK_ID, 608e098bc96SEvan Quan (uint8_t)0, 609e098bc96SEvan Quan &smu->smu_table.boot_values.vclk); 610e098bc96SEvan Quan 611e098bc96SEvan Quan smu_v11_0_atom_get_smu_clockinfo(smu->adev, 612e098bc96SEvan Quan (uint8_t)SMU11_SYSPLL0_DCLK_ID, 613e098bc96SEvan Quan (uint8_t)0, 614e098bc96SEvan Quan &smu->smu_table.boot_values.dclk); 615e098bc96SEvan Quan 616e098bc96SEvan Quan if ((smu->smu_table.boot_values.format_revision == 3) && 617e098bc96SEvan Quan (smu->smu_table.boot_values.content_revision >= 2)) 618e098bc96SEvan Quan smu_v11_0_atom_get_smu_clockinfo(smu->adev, 619e098bc96SEvan Quan (uint8_t)SMU11_SYSPLL1_0_FCLK_ID, 620e098bc96SEvan Quan (uint8_t)SMU11_SYSPLL1_2_ID, 621e098bc96SEvan Quan &smu->smu_table.boot_values.fclk); 622e098bc96SEvan Quan 6237d92c1fdSEvan Quan smu_v11_0_atom_get_smu_clockinfo(smu->adev, 6247d92c1fdSEvan Quan (uint8_t)SMU11_SYSPLL3_1_LCLK_ID, 6257d92c1fdSEvan Quan (uint8_t)SMU11_SYSPLL3_1_ID, 6267d92c1fdSEvan Quan &smu->smu_table.boot_values.lclk); 6277d92c1fdSEvan Quan 628e098bc96SEvan Quan return 0; 629e098bc96SEvan Quan } 630e098bc96SEvan Quan 631e098bc96SEvan Quan int smu_v11_0_notify_memory_pool_location(struct smu_context *smu) 632e098bc96SEvan Quan { 633e098bc96SEvan Quan struct smu_table_context *smu_table = &smu->smu_table; 634e098bc96SEvan Quan struct smu_table *memory_pool = &smu_table->memory_pool; 635e098bc96SEvan Quan int ret = 0; 636e098bc96SEvan Quan uint64_t address; 637e098bc96SEvan Quan uint32_t address_low, address_high; 638e098bc96SEvan Quan 639e098bc96SEvan Quan if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL) 640e098bc96SEvan Quan return ret; 641e098bc96SEvan Quan 642e098bc96SEvan Quan address = (uintptr_t)memory_pool->cpu_addr; 643e098bc96SEvan Quan address_high = (uint32_t)upper_32_bits(address); 644e098bc96SEvan Quan address_low = (uint32_t)lower_32_bits(address); 645e098bc96SEvan Quan 646e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, 647e098bc96SEvan Quan SMU_MSG_SetSystemVirtualDramAddrHigh, 648e098bc96SEvan Quan address_high, 649e098bc96SEvan Quan NULL); 650e098bc96SEvan Quan if (ret) 651e098bc96SEvan Quan return ret; 652e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, 653e098bc96SEvan Quan SMU_MSG_SetSystemVirtualDramAddrLow, 654e098bc96SEvan Quan address_low, 655e098bc96SEvan Quan NULL); 656e098bc96SEvan Quan if (ret) 657e098bc96SEvan Quan return ret; 658e098bc96SEvan Quan 659e098bc96SEvan Quan address = memory_pool->mc_address; 660e098bc96SEvan Quan address_high = (uint32_t)upper_32_bits(address); 661e098bc96SEvan Quan address_low = (uint32_t)lower_32_bits(address); 662e098bc96SEvan Quan 663e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh, 664e098bc96SEvan Quan address_high, NULL); 665e098bc96SEvan Quan if (ret) 666e098bc96SEvan Quan return ret; 667e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow, 668e098bc96SEvan Quan address_low, NULL); 669e098bc96SEvan Quan if (ret) 670e098bc96SEvan Quan return ret; 671e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize, 672e098bc96SEvan Quan (uint32_t)memory_pool->size, NULL); 673e098bc96SEvan Quan if (ret) 674e098bc96SEvan Quan return ret; 675e098bc96SEvan Quan 676e098bc96SEvan Quan return ret; 677e098bc96SEvan Quan } 678e098bc96SEvan Quan 679e098bc96SEvan Quan int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk) 680e098bc96SEvan Quan { 681e098bc96SEvan Quan int ret; 682e098bc96SEvan Quan 683e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, 684e098bc96SEvan Quan SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL); 685e098bc96SEvan Quan if (ret) 686e098bc96SEvan Quan dev_err(smu->adev->dev, "SMU11 attempt to set divider for DCEFCLK Failed!"); 687e098bc96SEvan Quan 688e098bc96SEvan Quan return ret; 689e098bc96SEvan Quan } 690e098bc96SEvan Quan 691e098bc96SEvan Quan int smu_v11_0_set_driver_table_location(struct smu_context *smu) 692e098bc96SEvan Quan { 693e098bc96SEvan Quan struct smu_table *driver_table = &smu->smu_table.driver_table; 694e098bc96SEvan Quan int ret = 0; 695e098bc96SEvan Quan 696e098bc96SEvan Quan if (driver_table->mc_address) { 697e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, 698e098bc96SEvan Quan SMU_MSG_SetDriverDramAddrHigh, 699e098bc96SEvan Quan upper_32_bits(driver_table->mc_address), 700e098bc96SEvan Quan NULL); 701e098bc96SEvan Quan if (!ret) 702e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, 703e098bc96SEvan Quan SMU_MSG_SetDriverDramAddrLow, 704e098bc96SEvan Quan lower_32_bits(driver_table->mc_address), 705e098bc96SEvan Quan NULL); 706e098bc96SEvan Quan } 707e098bc96SEvan Quan 708e098bc96SEvan Quan return ret; 709e098bc96SEvan Quan } 710e098bc96SEvan Quan 711e098bc96SEvan Quan int smu_v11_0_set_tool_table_location(struct smu_context *smu) 712e098bc96SEvan Quan { 713e098bc96SEvan Quan int ret = 0; 714e098bc96SEvan Quan struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG]; 715e098bc96SEvan Quan 716e098bc96SEvan Quan if (tool_table->mc_address) { 717e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, 718e098bc96SEvan Quan SMU_MSG_SetToolsDramAddrHigh, 719e098bc96SEvan Quan upper_32_bits(tool_table->mc_address), 720e098bc96SEvan Quan NULL); 721e098bc96SEvan Quan if (!ret) 722e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, 723e098bc96SEvan Quan SMU_MSG_SetToolsDramAddrLow, 724e098bc96SEvan Quan lower_32_bits(tool_table->mc_address), 725e098bc96SEvan Quan NULL); 726e098bc96SEvan Quan } 727e098bc96SEvan Quan 728e098bc96SEvan Quan return ret; 729e098bc96SEvan Quan } 730e098bc96SEvan Quan 731e098bc96SEvan Quan int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count) 732e098bc96SEvan Quan { 733e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 734e098bc96SEvan Quan 735db1f8a8fSTao Zhou /* Navy_Flounder/Dimgrey_Cavefish do not support to change 736db1f8a8fSTao Zhou * display num currently 737db1f8a8fSTao Zhou */ 738db1f8a8fSTao Zhou if (adev->asic_type >= CHIP_NAVY_FLOUNDER && 7394d352669SChengming Gui adev->asic_type <= CHIP_BEIGE_GOBY) 740e098bc96SEvan Quan return 0; 741e098bc96SEvan Quan 74238d11e02SEvan Quan return smu_cmn_send_smc_msg_with_param(smu, 74338d11e02SEvan Quan SMU_MSG_NumOfDisplays, 74438d11e02SEvan Quan count, 74538d11e02SEvan Quan NULL); 746e098bc96SEvan Quan } 747e098bc96SEvan Quan 748e098bc96SEvan Quan 749e098bc96SEvan Quan int smu_v11_0_set_allowed_mask(struct smu_context *smu) 750e098bc96SEvan Quan { 751e098bc96SEvan Quan struct smu_feature *feature = &smu->smu_feature; 752e098bc96SEvan Quan int ret = 0; 753e098bc96SEvan Quan uint32_t feature_mask[2]; 754e098bc96SEvan Quan 755692bd2a0SJia-Ju Bai if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64) { 756692bd2a0SJia-Ju Bai ret = -EINVAL; 757e098bc96SEvan Quan goto failed; 758692bd2a0SJia-Ju Bai } 759e098bc96SEvan Quan 760e098bc96SEvan Quan bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64); 761e098bc96SEvan Quan 762e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, 763e098bc96SEvan Quan feature_mask[1], NULL); 764e098bc96SEvan Quan if (ret) 765e098bc96SEvan Quan goto failed; 766e098bc96SEvan Quan 767e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow, 768e098bc96SEvan Quan feature_mask[0], NULL); 769e098bc96SEvan Quan if (ret) 770e098bc96SEvan Quan goto failed; 771e098bc96SEvan Quan 772e098bc96SEvan Quan failed: 773e098bc96SEvan Quan return ret; 774e098bc96SEvan Quan } 775e098bc96SEvan Quan 776e098bc96SEvan Quan int smu_v11_0_system_features_control(struct smu_context *smu, 777e098bc96SEvan Quan bool en) 778e098bc96SEvan Quan { 779e098bc96SEvan Quan struct smu_feature *feature = &smu->smu_feature; 780e098bc96SEvan Quan uint32_t feature_mask[2]; 781e098bc96SEvan Quan int ret = 0; 782e098bc96SEvan Quan 783e098bc96SEvan Quan ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures : 784e098bc96SEvan Quan SMU_MSG_DisableAllSmuFeatures), NULL); 785e098bc96SEvan Quan if (ret) 786e098bc96SEvan Quan return ret; 787e098bc96SEvan Quan 788e098bc96SEvan Quan bitmap_zero(feature->enabled, feature->feature_num); 789e098bc96SEvan Quan bitmap_zero(feature->supported, feature->feature_num); 790e098bc96SEvan Quan 791e098bc96SEvan Quan if (en) { 792e098bc96SEvan Quan ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2); 793e098bc96SEvan Quan if (ret) 794e098bc96SEvan Quan return ret; 795e098bc96SEvan Quan 796e098bc96SEvan Quan bitmap_copy(feature->enabled, (unsigned long *)&feature_mask, 797e098bc96SEvan Quan feature->feature_num); 798e098bc96SEvan Quan bitmap_copy(feature->supported, (unsigned long *)&feature_mask, 799e098bc96SEvan Quan feature->feature_num); 800e098bc96SEvan Quan } 801e098bc96SEvan Quan 802e098bc96SEvan Quan return ret; 803e098bc96SEvan Quan } 804e098bc96SEvan Quan 805e098bc96SEvan Quan int smu_v11_0_notify_display_change(struct smu_context *smu) 806e098bc96SEvan Quan { 807e098bc96SEvan Quan int ret = 0; 808e098bc96SEvan Quan 809e098bc96SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && 810e098bc96SEvan Quan smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM) 811e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL); 812e098bc96SEvan Quan 813e098bc96SEvan Quan return ret; 814e098bc96SEvan Quan } 815e098bc96SEvan Quan 816e098bc96SEvan Quan static int 817e098bc96SEvan Quan smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock, 818e098bc96SEvan Quan enum smu_clk_type clock_select) 819e098bc96SEvan Quan { 820e098bc96SEvan Quan int ret = 0; 821e098bc96SEvan Quan int clk_id; 822e098bc96SEvan Quan 823e098bc96SEvan Quan if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) || 824e098bc96SEvan Quan (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0)) 825e098bc96SEvan Quan return 0; 826e098bc96SEvan Quan 827e098bc96SEvan Quan clk_id = smu_cmn_to_asic_specific_index(smu, 828e098bc96SEvan Quan CMN2ASIC_MAPPING_CLK, 829e098bc96SEvan Quan clock_select); 830e098bc96SEvan Quan if (clk_id < 0) 831e098bc96SEvan Quan return -EINVAL; 832e098bc96SEvan Quan 833e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq, 834e098bc96SEvan Quan clk_id << 16, clock); 835e098bc96SEvan Quan if (ret) { 836e098bc96SEvan Quan dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!"); 837e098bc96SEvan Quan return ret; 838e098bc96SEvan Quan } 839e098bc96SEvan Quan 840e098bc96SEvan Quan if (*clock != 0) 841e098bc96SEvan Quan return 0; 842e098bc96SEvan Quan 843e098bc96SEvan Quan /* if DC limit is zero, return AC limit */ 844e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, 845e098bc96SEvan Quan clk_id << 16, clock); 846e098bc96SEvan Quan if (ret) { 847e098bc96SEvan Quan dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!"); 848e098bc96SEvan Quan return ret; 849e098bc96SEvan Quan } 850e098bc96SEvan Quan 851e098bc96SEvan Quan return 0; 852e098bc96SEvan Quan } 853e098bc96SEvan Quan 854e098bc96SEvan Quan int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu) 855e098bc96SEvan Quan { 856e098bc96SEvan Quan struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks = 857e098bc96SEvan Quan smu->smu_table.max_sustainable_clocks; 858e098bc96SEvan Quan int ret = 0; 859e098bc96SEvan Quan 860e098bc96SEvan Quan max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100; 861e098bc96SEvan Quan max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100; 862e098bc96SEvan Quan max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100; 863e098bc96SEvan Quan max_sustainable_clocks->display_clock = 0xFFFFFFFF; 864e098bc96SEvan Quan max_sustainable_clocks->phy_clock = 0xFFFFFFFF; 865e098bc96SEvan Quan max_sustainable_clocks->pixel_clock = 0xFFFFFFFF; 866e098bc96SEvan Quan 867e098bc96SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 868e098bc96SEvan Quan ret = smu_v11_0_get_max_sustainable_clock(smu, 869e098bc96SEvan Quan &(max_sustainable_clocks->uclock), 870e098bc96SEvan Quan SMU_UCLK); 871e098bc96SEvan Quan if (ret) { 872e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!", 873e098bc96SEvan Quan __func__); 874e098bc96SEvan Quan return ret; 875e098bc96SEvan Quan } 876e098bc96SEvan Quan } 877e098bc96SEvan Quan 878e098bc96SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 879e098bc96SEvan Quan ret = smu_v11_0_get_max_sustainable_clock(smu, 880e098bc96SEvan Quan &(max_sustainable_clocks->soc_clock), 881e098bc96SEvan Quan SMU_SOCCLK); 882e098bc96SEvan Quan if (ret) { 883e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!", 884e098bc96SEvan Quan __func__); 885e098bc96SEvan Quan return ret; 886e098bc96SEvan Quan } 887e098bc96SEvan Quan } 888e098bc96SEvan Quan 889e098bc96SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 890e098bc96SEvan Quan ret = smu_v11_0_get_max_sustainable_clock(smu, 891e098bc96SEvan Quan &(max_sustainable_clocks->dcef_clock), 892e098bc96SEvan Quan SMU_DCEFCLK); 893e098bc96SEvan Quan if (ret) { 894e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!", 895e098bc96SEvan Quan __func__); 896e098bc96SEvan Quan return ret; 897e098bc96SEvan Quan } 898e098bc96SEvan Quan 899e098bc96SEvan Quan ret = smu_v11_0_get_max_sustainable_clock(smu, 900e098bc96SEvan Quan &(max_sustainable_clocks->display_clock), 901e098bc96SEvan Quan SMU_DISPCLK); 902e098bc96SEvan Quan if (ret) { 903e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!", 904e098bc96SEvan Quan __func__); 905e098bc96SEvan Quan return ret; 906e098bc96SEvan Quan } 907e098bc96SEvan Quan ret = smu_v11_0_get_max_sustainable_clock(smu, 908e098bc96SEvan Quan &(max_sustainable_clocks->phy_clock), 909e098bc96SEvan Quan SMU_PHYCLK); 910e098bc96SEvan Quan if (ret) { 911e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!", 912e098bc96SEvan Quan __func__); 913e098bc96SEvan Quan return ret; 914e098bc96SEvan Quan } 915e098bc96SEvan Quan ret = smu_v11_0_get_max_sustainable_clock(smu, 916e098bc96SEvan Quan &(max_sustainable_clocks->pixel_clock), 917e098bc96SEvan Quan SMU_PIXCLK); 918e098bc96SEvan Quan if (ret) { 919e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!", 920e098bc96SEvan Quan __func__); 921e098bc96SEvan Quan return ret; 922e098bc96SEvan Quan } 923e098bc96SEvan Quan } 924e098bc96SEvan Quan 925e098bc96SEvan Quan if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock) 926e098bc96SEvan Quan max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock; 927e098bc96SEvan Quan 928e098bc96SEvan Quan return 0; 929e098bc96SEvan Quan } 930e098bc96SEvan Quan 931e098bc96SEvan Quan int smu_v11_0_get_current_power_limit(struct smu_context *smu, 932e098bc96SEvan Quan uint32_t *power_limit) 933e098bc96SEvan Quan { 934e098bc96SEvan Quan int power_src; 935e098bc96SEvan Quan int ret = 0; 936e098bc96SEvan Quan 937e098bc96SEvan Quan if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) 938e098bc96SEvan Quan return -EINVAL; 939e098bc96SEvan Quan 940e098bc96SEvan Quan power_src = smu_cmn_to_asic_specific_index(smu, 941e098bc96SEvan Quan CMN2ASIC_MAPPING_PWR, 942e098bc96SEvan Quan smu->adev->pm.ac_power ? 943e098bc96SEvan Quan SMU_POWER_SOURCE_AC : 944e098bc96SEvan Quan SMU_POWER_SOURCE_DC); 945e098bc96SEvan Quan if (power_src < 0) 946e098bc96SEvan Quan return -EINVAL; 947e098bc96SEvan Quan 9480cb4c621SEvan Quan /* 9490cb4c621SEvan Quan * BIT 24-31: ControllerId (only PPT0 is supported for now) 9500cb4c621SEvan Quan * BIT 16-23: PowerSource 9510cb4c621SEvan Quan */ 952e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, 953e098bc96SEvan Quan SMU_MSG_GetPptLimit, 9540cb4c621SEvan Quan (0 << 24) | (power_src << 16), 955e098bc96SEvan Quan power_limit); 956e098bc96SEvan Quan if (ret) 957e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__); 958e098bc96SEvan Quan 959e098bc96SEvan Quan return ret; 960e098bc96SEvan Quan } 961e098bc96SEvan Quan 962e098bc96SEvan Quan int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n) 963e098bc96SEvan Quan { 9640cb4c621SEvan Quan int power_src; 965e098bc96SEvan Quan int ret = 0; 966e098bc96SEvan Quan 967e098bc96SEvan Quan if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 968e098bc96SEvan Quan dev_err(smu->adev->dev, "Setting new power limit is not supported!\n"); 969e098bc96SEvan Quan return -EOPNOTSUPP; 970e098bc96SEvan Quan } 971e098bc96SEvan Quan 9720cb4c621SEvan Quan power_src = smu_cmn_to_asic_specific_index(smu, 9730cb4c621SEvan Quan CMN2ASIC_MAPPING_PWR, 9740cb4c621SEvan Quan smu->adev->pm.ac_power ? 9750cb4c621SEvan Quan SMU_POWER_SOURCE_AC : 9760cb4c621SEvan Quan SMU_POWER_SOURCE_DC); 9770cb4c621SEvan Quan if (power_src < 0) 9780cb4c621SEvan Quan return -EINVAL; 9790cb4c621SEvan Quan 9800cb4c621SEvan Quan /* 9810cb4c621SEvan Quan * BIT 24-31: ControllerId (only PPT0 is supported for now) 9820cb4c621SEvan Quan * BIT 16-23: PowerSource 9830cb4c621SEvan Quan * BIT 0-15: PowerLimit 9840cb4c621SEvan Quan */ 9850cb4c621SEvan Quan n &= 0xFFFF; 9860cb4c621SEvan Quan n |= 0 << 24; 9870cb4c621SEvan Quan n |= (power_src) << 16; 988e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL); 989e098bc96SEvan Quan if (ret) { 990e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__); 991e098bc96SEvan Quan return ret; 992e098bc96SEvan Quan } 993e098bc96SEvan Quan 994e098bc96SEvan Quan smu->current_power_limit = n; 995e098bc96SEvan Quan 996e098bc96SEvan Quan return 0; 997e098bc96SEvan Quan } 998e098bc96SEvan Quan 99971f9404fSEvan Quan static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu) 100071f9404fSEvan Quan { 100171f9404fSEvan Quan return smu_cmn_send_smc_msg(smu, 100271f9404fSEvan Quan SMU_MSG_ReenableAcDcInterrupt, 100371f9404fSEvan Quan NULL); 100471f9404fSEvan Quan } 100571f9404fSEvan Quan 100671f9404fSEvan Quan static int smu_v11_0_process_pending_interrupt(struct smu_context *smu) 100771f9404fSEvan Quan { 100871f9404fSEvan Quan int ret = 0; 100971f9404fSEvan Quan 101071f9404fSEvan Quan if (smu->dc_controlled_by_gpio && 101171f9404fSEvan Quan smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT)) 101271f9404fSEvan Quan ret = smu_v11_0_ack_ac_dc_interrupt(smu); 101371f9404fSEvan Quan 101471f9404fSEvan Quan return ret; 101571f9404fSEvan Quan } 101671f9404fSEvan Quan 1017234676d6SAlex Deucher void smu_v11_0_interrupt_work(struct smu_context *smu) 1018234676d6SAlex Deucher { 1019234676d6SAlex Deucher if (smu_v11_0_ack_ac_dc_interrupt(smu)) 1020234676d6SAlex Deucher dev_err(smu->adev->dev, "Ack AC/DC interrupt Failed!\n"); 1021234676d6SAlex Deucher } 1022234676d6SAlex Deucher 1023e098bc96SEvan Quan int smu_v11_0_enable_thermal_alert(struct smu_context *smu) 1024e098bc96SEvan Quan { 102571f9404fSEvan Quan int ret = 0; 1026e098bc96SEvan Quan 102771f9404fSEvan Quan if (smu->smu_table.thermal_controller_type) { 102871f9404fSEvan Quan ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0); 102971f9404fSEvan Quan if (ret) 103071f9404fSEvan Quan return ret; 103171f9404fSEvan Quan } 103271f9404fSEvan Quan 103371f9404fSEvan Quan /* 103471f9404fSEvan Quan * After init there might have been missed interrupts triggered 103571f9404fSEvan Quan * before driver registers for interrupt (Ex. AC/DC). 103671f9404fSEvan Quan */ 103771f9404fSEvan Quan return smu_v11_0_process_pending_interrupt(smu); 1038e098bc96SEvan Quan } 1039e098bc96SEvan Quan 1040e098bc96SEvan Quan int smu_v11_0_disable_thermal_alert(struct smu_context *smu) 1041e098bc96SEvan Quan { 1042e098bc96SEvan Quan return amdgpu_irq_put(smu->adev, &smu->irq_source, 0); 1043e098bc96SEvan Quan } 1044e098bc96SEvan Quan 1045e098bc96SEvan Quan static uint16_t convert_to_vddc(uint8_t vid) 1046e098bc96SEvan Quan { 1047e098bc96SEvan Quan return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE); 1048e098bc96SEvan Quan } 1049e098bc96SEvan Quan 1050e098bc96SEvan Quan int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value) 1051e098bc96SEvan Quan { 1052e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 1053e098bc96SEvan Quan uint32_t vdd = 0, val_vid = 0; 1054e098bc96SEvan Quan 1055e098bc96SEvan Quan if (!value) 1056e098bc96SEvan Quan return -EINVAL; 1057e098bc96SEvan Quan val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) & 1058e098bc96SEvan Quan SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >> 1059e098bc96SEvan Quan SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT; 1060e098bc96SEvan Quan 1061e098bc96SEvan Quan vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid); 1062e098bc96SEvan Quan 1063e098bc96SEvan Quan *value = vdd; 1064e098bc96SEvan Quan 1065e098bc96SEvan Quan return 0; 1066e098bc96SEvan Quan 1067e098bc96SEvan Quan } 1068e098bc96SEvan Quan 1069e098bc96SEvan Quan int 1070e098bc96SEvan Quan smu_v11_0_display_clock_voltage_request(struct smu_context *smu, 1071e098bc96SEvan Quan struct pp_display_clock_request 1072e098bc96SEvan Quan *clock_req) 1073e098bc96SEvan Quan { 1074e098bc96SEvan Quan enum amd_pp_clock_type clk_type = clock_req->clock_type; 1075e098bc96SEvan Quan int ret = 0; 1076e098bc96SEvan Quan enum smu_clk_type clk_select = 0; 1077e098bc96SEvan Quan uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; 1078e098bc96SEvan Quan 1079e098bc96SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) || 1080e098bc96SEvan Quan smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1081e098bc96SEvan Quan switch (clk_type) { 1082e098bc96SEvan Quan case amd_pp_dcef_clock: 1083e098bc96SEvan Quan clk_select = SMU_DCEFCLK; 1084e098bc96SEvan Quan break; 1085e098bc96SEvan Quan case amd_pp_disp_clock: 1086e098bc96SEvan Quan clk_select = SMU_DISPCLK; 1087e098bc96SEvan Quan break; 1088e098bc96SEvan Quan case amd_pp_pixel_clock: 1089e098bc96SEvan Quan clk_select = SMU_PIXCLK; 1090e098bc96SEvan Quan break; 1091e098bc96SEvan Quan case amd_pp_phy_clock: 1092e098bc96SEvan Quan clk_select = SMU_PHYCLK; 1093e098bc96SEvan Quan break; 1094e098bc96SEvan Quan case amd_pp_mem_clock: 1095e098bc96SEvan Quan clk_select = SMU_UCLK; 1096e098bc96SEvan Quan break; 1097e098bc96SEvan Quan default: 1098e098bc96SEvan Quan dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__); 1099e098bc96SEvan Quan ret = -EINVAL; 1100e098bc96SEvan Quan break; 1101e098bc96SEvan Quan } 1102e098bc96SEvan Quan 1103e098bc96SEvan Quan if (ret) 1104e098bc96SEvan Quan goto failed; 1105e098bc96SEvan Quan 1106e098bc96SEvan Quan if (clk_select == SMU_UCLK && smu->disable_uclk_switch) 1107e098bc96SEvan Quan return 0; 1108e098bc96SEvan Quan 1109e098bc96SEvan Quan ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0); 1110e098bc96SEvan Quan 1111e098bc96SEvan Quan if(clk_select == SMU_UCLK) 1112e098bc96SEvan Quan smu->hard_min_uclk_req_from_dal = clk_freq; 1113e098bc96SEvan Quan } 1114e098bc96SEvan Quan 1115e098bc96SEvan Quan failed: 1116e098bc96SEvan Quan return ret; 1117e098bc96SEvan Quan } 1118e098bc96SEvan Quan 1119e098bc96SEvan Quan int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable) 1120e098bc96SEvan Quan { 1121e098bc96SEvan Quan int ret = 0; 1122e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 1123e098bc96SEvan Quan 1124e098bc96SEvan Quan switch (adev->asic_type) { 1125e098bc96SEvan Quan case CHIP_NAVI10: 1126e098bc96SEvan Quan case CHIP_NAVI14: 1127e098bc96SEvan Quan case CHIP_NAVI12: 1128e098bc96SEvan Quan case CHIP_SIENNA_CICHLID: 1129e098bc96SEvan Quan case CHIP_NAVY_FLOUNDER: 1130413949eeSTao Zhou case CHIP_DIMGREY_CAVEFISH: 1131ece3cbadSChengming Gui case CHIP_BEIGE_GOBY: 11323313ef18SJinzhou Su case CHIP_VANGOGH: 1133e098bc96SEvan Quan if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) 1134e098bc96SEvan Quan return 0; 1135e098bc96SEvan Quan if (enable) 1136e098bc96SEvan Quan ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL); 1137e098bc96SEvan Quan else 1138e098bc96SEvan Quan ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL); 1139e098bc96SEvan Quan break; 1140e098bc96SEvan Quan default: 1141e098bc96SEvan Quan break; 1142e098bc96SEvan Quan } 1143e098bc96SEvan Quan 1144e098bc96SEvan Quan return ret; 1145e098bc96SEvan Quan } 1146e098bc96SEvan Quan 1147e098bc96SEvan Quan uint32_t 1148e098bc96SEvan Quan smu_v11_0_get_fan_control_mode(struct smu_context *smu) 1149e098bc96SEvan Quan { 11504954a76aSAlex Deucher if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT)) 1151e098bc96SEvan Quan return AMD_FAN_CTRL_AUTO; 11524954a76aSAlex Deucher else 11534954a76aSAlex Deucher return smu->user_dpm_profile.fan_mode; 1154e098bc96SEvan Quan } 1155e098bc96SEvan Quan 1156e098bc96SEvan Quan static int 1157e098bc96SEvan Quan smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control) 1158e098bc96SEvan Quan { 1159e098bc96SEvan Quan int ret = 0; 1160e098bc96SEvan Quan 1161e098bc96SEvan Quan if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT)) 1162e098bc96SEvan Quan return 0; 1163e098bc96SEvan Quan 1164e098bc96SEvan Quan ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control); 1165e098bc96SEvan Quan if (ret) 1166e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!", 1167e098bc96SEvan Quan __func__, (auto_fan_control ? "Start" : "Stop")); 1168e098bc96SEvan Quan 1169e098bc96SEvan Quan return ret; 1170e098bc96SEvan Quan } 1171e098bc96SEvan Quan 1172e098bc96SEvan Quan static int 1173e098bc96SEvan Quan smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode) 1174e098bc96SEvan Quan { 1175e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 1176e098bc96SEvan Quan 1177e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, 1178e098bc96SEvan Quan REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 1179e098bc96SEvan Quan CG_FDO_CTRL2, TMIN, 0)); 1180e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, 1181e098bc96SEvan Quan REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 1182e098bc96SEvan Quan CG_FDO_CTRL2, FDO_PWM_MODE, mode)); 1183e098bc96SEvan Quan 1184e098bc96SEvan Quan return 0; 1185e098bc96SEvan Quan } 1186e098bc96SEvan Quan 1187e098bc96SEvan Quan int 1188cd305137SAlex Deucher smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed) 1189cd305137SAlex Deucher { 1190cd305137SAlex Deucher struct amdgpu_device *adev = smu->adev; 1191cd305137SAlex Deucher uint32_t duty100, duty; 1192cd305137SAlex Deucher uint64_t tmp64; 1193cd305137SAlex Deucher 1194cd305137SAlex Deucher if (speed > 100) 1195cd305137SAlex Deucher speed = 100; 1196cd305137SAlex Deucher 1197cd305137SAlex Deucher if (smu_v11_0_auto_fan_control(smu, 0)) 1198cd305137SAlex Deucher return -EINVAL; 1199cd305137SAlex Deucher 1200cd305137SAlex Deucher duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), 1201cd305137SAlex Deucher CG_FDO_CTRL1, FMAX_DUTY100); 1202cd305137SAlex Deucher if (!duty100) 1203cd305137SAlex Deucher return -EINVAL; 1204cd305137SAlex Deucher 1205cd305137SAlex Deucher tmp64 = (uint64_t)speed * duty100; 1206cd305137SAlex Deucher do_div(tmp64, 100); 1207cd305137SAlex Deucher duty = (uint32_t)tmp64; 1208cd305137SAlex Deucher 1209cd305137SAlex Deucher WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0, 1210cd305137SAlex Deucher REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), 1211cd305137SAlex Deucher CG_FDO_CTRL0, FDO_STATIC_DUTY, duty)); 1212cd305137SAlex Deucher 1213cd305137SAlex Deucher return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC); 1214cd305137SAlex Deucher } 1215cd305137SAlex Deucher 1216cd305137SAlex Deucher int 1217e098bc96SEvan Quan smu_v11_0_set_fan_control_mode(struct smu_context *smu, 1218e098bc96SEvan Quan uint32_t mode) 1219e098bc96SEvan Quan { 1220e098bc96SEvan Quan int ret = 0; 1221e098bc96SEvan Quan 1222e098bc96SEvan Quan switch (mode) { 1223e098bc96SEvan Quan case AMD_FAN_CTRL_NONE: 1224cd305137SAlex Deucher ret = smu_v11_0_set_fan_speed_percent(smu, 100); 1225e098bc96SEvan Quan break; 1226e098bc96SEvan Quan case AMD_FAN_CTRL_MANUAL: 1227e098bc96SEvan Quan ret = smu_v11_0_auto_fan_control(smu, 0); 1228e098bc96SEvan Quan break; 1229e098bc96SEvan Quan case AMD_FAN_CTRL_AUTO: 1230e098bc96SEvan Quan ret = smu_v11_0_auto_fan_control(smu, 1); 1231e098bc96SEvan Quan break; 1232e098bc96SEvan Quan default: 1233e098bc96SEvan Quan break; 1234e098bc96SEvan Quan } 1235e098bc96SEvan Quan 1236e098bc96SEvan Quan if (ret) { 1237e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__); 1238e098bc96SEvan Quan return -EINVAL; 1239e098bc96SEvan Quan } 1240e098bc96SEvan Quan 1241e098bc96SEvan Quan return ret; 1242e098bc96SEvan Quan } 1243e098bc96SEvan Quan 1244e098bc96SEvan Quan int smu_v11_0_set_xgmi_pstate(struct smu_context *smu, 1245e098bc96SEvan Quan uint32_t pstate) 1246e098bc96SEvan Quan { 12476c20f157SEvan Quan return smu_cmn_send_smc_msg_with_param(smu, 1248e098bc96SEvan Quan SMU_MSG_SetXgmiMode, 1249e098bc96SEvan Quan pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3, 1250e098bc96SEvan Quan NULL); 1251e098bc96SEvan Quan } 1252e098bc96SEvan Quan 1253e098bc96SEvan Quan static int smu_v11_0_set_irq_state(struct amdgpu_device *adev, 1254e098bc96SEvan Quan struct amdgpu_irq_src *source, 1255e098bc96SEvan Quan unsigned tyep, 1256e098bc96SEvan Quan enum amdgpu_interrupt_state state) 1257e098bc96SEvan Quan { 1258e098bc96SEvan Quan struct smu_context *smu = &adev->smu; 1259e098bc96SEvan Quan uint32_t low, high; 1260e098bc96SEvan Quan uint32_t val = 0; 1261e098bc96SEvan Quan 1262e098bc96SEvan Quan switch (state) { 1263e098bc96SEvan Quan case AMDGPU_IRQ_STATE_DISABLE: 1264e098bc96SEvan Quan /* For THM irqs */ 1265e098bc96SEvan Quan val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); 1266e098bc96SEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1); 1267e098bc96SEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1); 1268e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); 1269e098bc96SEvan Quan 1270e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0); 1271e098bc96SEvan Quan 1272e098bc96SEvan Quan /* For MP1 SW irqs */ 1273e098bc96SEvan Quan val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL); 1274e098bc96SEvan Quan val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1); 1275e098bc96SEvan Quan WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val); 1276e098bc96SEvan Quan 1277e098bc96SEvan Quan break; 1278e098bc96SEvan Quan case AMDGPU_IRQ_STATE_ENABLE: 1279e098bc96SEvan Quan /* For THM irqs */ 1280e098bc96SEvan Quan low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, 1281e098bc96SEvan Quan smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES); 1282e098bc96SEvan Quan high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, 1283e098bc96SEvan Quan smu->thermal_range.software_shutdown_temp); 1284e098bc96SEvan Quan 1285e098bc96SEvan Quan val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); 1286e098bc96SEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); 1287e098bc96SEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); 1288e098bc96SEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); 1289e098bc96SEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0); 1290e098bc96SEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff)); 1291e098bc96SEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff)); 1292e098bc96SEvan Quan val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); 1293e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); 1294e098bc96SEvan Quan 1295e098bc96SEvan Quan val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT); 1296e098bc96SEvan Quan val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT); 1297e098bc96SEvan Quan val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT); 1298e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val); 1299e098bc96SEvan Quan 1300e098bc96SEvan Quan /* For MP1 SW irqs */ 1301e098bc96SEvan Quan val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT); 1302e098bc96SEvan Quan val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE); 1303e098bc96SEvan Quan val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0); 1304e098bc96SEvan Quan WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val); 1305e098bc96SEvan Quan 1306e098bc96SEvan Quan val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL); 1307e098bc96SEvan Quan val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0); 1308e098bc96SEvan Quan WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val); 1309e098bc96SEvan Quan 1310e098bc96SEvan Quan break; 1311e098bc96SEvan Quan default: 1312e098bc96SEvan Quan break; 1313e098bc96SEvan Quan } 1314e098bc96SEvan Quan 1315e098bc96SEvan Quan return 0; 1316e098bc96SEvan Quan } 1317e098bc96SEvan Quan 1318e098bc96SEvan Quan #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */ 1319e098bc96SEvan Quan #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */ 1320e098bc96SEvan Quan 1321e098bc96SEvan Quan #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83 1322e098bc96SEvan Quan 1323e098bc96SEvan Quan static int smu_v11_0_irq_process(struct amdgpu_device *adev, 1324e098bc96SEvan Quan struct amdgpu_irq_src *source, 1325e098bc96SEvan Quan struct amdgpu_iv_entry *entry) 1326e098bc96SEvan Quan { 1327e098bc96SEvan Quan struct smu_context *smu = &adev->smu; 1328e098bc96SEvan Quan uint32_t client_id = entry->client_id; 1329e098bc96SEvan Quan uint32_t src_id = entry->src_id; 1330e098bc96SEvan Quan /* 1331e098bc96SEvan Quan * ctxid is used to distinguish different 1332e098bc96SEvan Quan * events for SMCToHost interrupt. 1333e098bc96SEvan Quan */ 1334e098bc96SEvan Quan uint32_t ctxid = entry->src_data[0]; 1335e098bc96SEvan Quan uint32_t data; 1336e098bc96SEvan Quan 1337e098bc96SEvan Quan if (client_id == SOC15_IH_CLIENTID_THM) { 1338e098bc96SEvan Quan switch (src_id) { 1339e098bc96SEvan Quan case THM_11_0__SRCID__THM_DIG_THERM_L2H: 1340e098bc96SEvan Quan dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1341e098bc96SEvan Quan /* 1342e098bc96SEvan Quan * SW CTF just occurred. 1343e098bc96SEvan Quan * Try to do a graceful shutdown to prevent further damage. 1344e098bc96SEvan Quan */ 1345e098bc96SEvan Quan dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1346e098bc96SEvan Quan orderly_poweroff(true); 1347e098bc96SEvan Quan break; 1348e098bc96SEvan Quan case THM_11_0__SRCID__THM_DIG_THERM_H2L: 1349e098bc96SEvan Quan dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n"); 1350e098bc96SEvan Quan break; 1351e098bc96SEvan Quan default: 1352e098bc96SEvan Quan dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n", 1353e098bc96SEvan Quan src_id); 1354e098bc96SEvan Quan break; 1355e098bc96SEvan Quan } 1356e098bc96SEvan Quan } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) { 1357e098bc96SEvan Quan dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n"); 1358e098bc96SEvan Quan /* 1359e098bc96SEvan Quan * HW CTF just occurred. Shutdown to prevent further damage. 1360e098bc96SEvan Quan */ 1361e098bc96SEvan Quan dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n"); 1362e098bc96SEvan Quan orderly_poweroff(true); 1363e098bc96SEvan Quan } else if (client_id == SOC15_IH_CLIENTID_MP1) { 1364e098bc96SEvan Quan if (src_id == 0xfe) { 1365e098bc96SEvan Quan /* ACK SMUToHost interrupt */ 1366e098bc96SEvan Quan data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL); 1367e098bc96SEvan Quan data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1); 1368e098bc96SEvan Quan WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, data); 1369e098bc96SEvan Quan 1370e098bc96SEvan Quan switch (ctxid) { 1371e098bc96SEvan Quan case 0x3: 1372e098bc96SEvan Quan dev_dbg(adev->dev, "Switched to AC mode!\n"); 1373234676d6SAlex Deucher schedule_work(&smu->interrupt_work); 1374e098bc96SEvan Quan break; 1375e098bc96SEvan Quan case 0x4: 1376e098bc96SEvan Quan dev_dbg(adev->dev, "Switched to DC mode!\n"); 1377234676d6SAlex Deucher schedule_work(&smu->interrupt_work); 1378e098bc96SEvan Quan break; 1379e098bc96SEvan Quan case 0x7: 1380e098bc96SEvan Quan /* 1381e098bc96SEvan Quan * Increment the throttle interrupt counter 1382e098bc96SEvan Quan */ 1383e098bc96SEvan Quan atomic64_inc(&smu->throttle_int_counter); 1384e098bc96SEvan Quan 1385e098bc96SEvan Quan if (!atomic_read(&adev->throttling_logging_enabled)) 1386e098bc96SEvan Quan return 0; 1387e098bc96SEvan Quan 1388e098bc96SEvan Quan if (__ratelimit(&adev->throttling_logging_rs)) 1389e098bc96SEvan Quan schedule_work(&smu->throttling_logging_work); 1390e098bc96SEvan Quan 1391e098bc96SEvan Quan break; 1392e098bc96SEvan Quan } 1393e098bc96SEvan Quan } 1394e098bc96SEvan Quan } 1395e098bc96SEvan Quan 1396e098bc96SEvan Quan return 0; 1397e098bc96SEvan Quan } 1398e098bc96SEvan Quan 1399e098bc96SEvan Quan static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs = 1400e098bc96SEvan Quan { 1401e098bc96SEvan Quan .set = smu_v11_0_set_irq_state, 1402e098bc96SEvan Quan .process = smu_v11_0_irq_process, 1403e098bc96SEvan Quan }; 1404e098bc96SEvan Quan 1405e098bc96SEvan Quan int smu_v11_0_register_irq_handler(struct smu_context *smu) 1406e098bc96SEvan Quan { 1407e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 1408e098bc96SEvan Quan struct amdgpu_irq_src *irq_src = &smu->irq_source; 1409e098bc96SEvan Quan int ret = 0; 1410e098bc96SEvan Quan 1411e098bc96SEvan Quan irq_src->num_types = 1; 1412e098bc96SEvan Quan irq_src->funcs = &smu_v11_0_irq_funcs; 1413e098bc96SEvan Quan 1414e098bc96SEvan Quan ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, 1415e098bc96SEvan Quan THM_11_0__SRCID__THM_DIG_THERM_L2H, 1416e098bc96SEvan Quan irq_src); 1417e098bc96SEvan Quan if (ret) 1418e098bc96SEvan Quan return ret; 1419e098bc96SEvan Quan 1420e098bc96SEvan Quan ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, 1421e098bc96SEvan Quan THM_11_0__SRCID__THM_DIG_THERM_H2L, 1422e098bc96SEvan Quan irq_src); 1423e098bc96SEvan Quan if (ret) 1424e098bc96SEvan Quan return ret; 1425e098bc96SEvan Quan 1426e098bc96SEvan Quan /* Register CTF(GPIO_19) interrupt */ 1427e098bc96SEvan Quan ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO, 1428e098bc96SEvan Quan SMUIO_11_0__SRCID__SMUIO_GPIO19, 1429e098bc96SEvan Quan irq_src); 1430e098bc96SEvan Quan if (ret) 1431e098bc96SEvan Quan return ret; 1432e098bc96SEvan Quan 1433e098bc96SEvan Quan ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1, 1434e098bc96SEvan Quan 0xfe, 1435e098bc96SEvan Quan irq_src); 1436e098bc96SEvan Quan if (ret) 1437e098bc96SEvan Quan return ret; 1438e098bc96SEvan Quan 1439e098bc96SEvan Quan return ret; 1440e098bc96SEvan Quan } 1441e098bc96SEvan Quan 1442e098bc96SEvan Quan int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu, 1443e098bc96SEvan Quan struct pp_smu_nv_clock_table *max_clocks) 1444e098bc96SEvan Quan { 1445e098bc96SEvan Quan struct smu_table_context *table_context = &smu->smu_table; 1446e098bc96SEvan Quan struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL; 1447e098bc96SEvan Quan 1448e098bc96SEvan Quan if (!max_clocks || !table_context->max_sustainable_clocks) 1449e098bc96SEvan Quan return -EINVAL; 1450e098bc96SEvan Quan 1451e098bc96SEvan Quan sustainable_clocks = table_context->max_sustainable_clocks; 1452e098bc96SEvan Quan 1453e098bc96SEvan Quan max_clocks->dcfClockInKhz = 1454e098bc96SEvan Quan (unsigned int) sustainable_clocks->dcef_clock * 1000; 1455e098bc96SEvan Quan max_clocks->displayClockInKhz = 1456e098bc96SEvan Quan (unsigned int) sustainable_clocks->display_clock * 1000; 1457e098bc96SEvan Quan max_clocks->phyClockInKhz = 1458e098bc96SEvan Quan (unsigned int) sustainable_clocks->phy_clock * 1000; 1459e098bc96SEvan Quan max_clocks->pixelClockInKhz = 1460e098bc96SEvan Quan (unsigned int) sustainable_clocks->pixel_clock * 1000; 1461e098bc96SEvan Quan max_clocks->uClockInKhz = 1462e098bc96SEvan Quan (unsigned int) sustainable_clocks->uclock * 1000; 1463e098bc96SEvan Quan max_clocks->socClockInKhz = 1464e098bc96SEvan Quan (unsigned int) sustainable_clocks->soc_clock * 1000; 1465e098bc96SEvan Quan max_clocks->dscClockInKhz = 0; 1466e098bc96SEvan Quan max_clocks->dppClockInKhz = 0; 1467e098bc96SEvan Quan max_clocks->fabricClockInKhz = 0; 1468e098bc96SEvan Quan 1469e098bc96SEvan Quan return 0; 1470e098bc96SEvan Quan } 1471e098bc96SEvan Quan 1472e098bc96SEvan Quan int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu) 1473e098bc96SEvan Quan { 14746c20f157SEvan Quan return smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL); 1475e098bc96SEvan Quan } 1476e098bc96SEvan Quan 1477e098bc96SEvan Quan static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq) 1478e098bc96SEvan Quan { 1479e098bc96SEvan Quan return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL); 1480e098bc96SEvan Quan } 1481e098bc96SEvan Quan 1482e098bc96SEvan Quan bool smu_v11_0_baco_is_support(struct smu_context *smu) 1483e098bc96SEvan Quan { 1484e098bc96SEvan Quan struct smu_baco_context *smu_baco = &smu->smu_baco; 1485e098bc96SEvan Quan 1486*52a9fd7bSLijo Lazar if (amdgpu_sriov_vf(smu->adev) || !smu_baco->platform_support) 1487e098bc96SEvan Quan return false; 1488e098bc96SEvan Quan 1489e098bc96SEvan Quan /* Arcturus does not support this bit mask */ 1490e098bc96SEvan Quan if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) && 1491e098bc96SEvan Quan !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) 1492e098bc96SEvan Quan return false; 1493e098bc96SEvan Quan 1494e098bc96SEvan Quan return true; 1495e098bc96SEvan Quan } 1496e098bc96SEvan Quan 1497e098bc96SEvan Quan enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu) 1498e098bc96SEvan Quan { 1499e098bc96SEvan Quan struct smu_baco_context *smu_baco = &smu->smu_baco; 1500e098bc96SEvan Quan enum smu_baco_state baco_state; 1501e098bc96SEvan Quan 1502e098bc96SEvan Quan mutex_lock(&smu_baco->mutex); 1503e098bc96SEvan Quan baco_state = smu_baco->state; 1504e098bc96SEvan Quan mutex_unlock(&smu_baco->mutex); 1505e098bc96SEvan Quan 1506e098bc96SEvan Quan return baco_state; 1507e098bc96SEvan Quan } 1508e098bc96SEvan Quan 15092261229cSLikun Gao #define D3HOT_BACO_SEQUENCE 0 15102261229cSLikun Gao #define D3HOT_BAMACO_SEQUENCE 2 15112261229cSLikun Gao 1512e098bc96SEvan Quan int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state) 1513e098bc96SEvan Quan { 1514e098bc96SEvan Quan struct smu_baco_context *smu_baco = &smu->smu_baco; 1515e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 1516e098bc96SEvan Quan struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1517e098bc96SEvan Quan uint32_t data; 1518e098bc96SEvan Quan int ret = 0; 1519e098bc96SEvan Quan 1520e098bc96SEvan Quan if (smu_v11_0_baco_get_state(smu) == state) 1521e098bc96SEvan Quan return 0; 1522e098bc96SEvan Quan 1523e098bc96SEvan Quan mutex_lock(&smu_baco->mutex); 1524e098bc96SEvan Quan 1525e098bc96SEvan Quan if (state == SMU_BACO_STATE_ENTER) { 15262261229cSLikun Gao switch (adev->asic_type) { 15272261229cSLikun Gao case CHIP_SIENNA_CICHLID: 15282261229cSLikun Gao case CHIP_NAVY_FLOUNDER: 15292261229cSLikun Gao case CHIP_DIMGREY_CAVEFISH: 15302261229cSLikun Gao if (amdgpu_runtime_pm == 2) 15312261229cSLikun Gao ret = smu_cmn_send_smc_msg_with_param(smu, 15322261229cSLikun Gao SMU_MSG_EnterBaco, 15332261229cSLikun Gao D3HOT_BAMACO_SEQUENCE, 15342261229cSLikun Gao NULL); 15352261229cSLikun Gao else 15362261229cSLikun Gao ret = smu_cmn_send_smc_msg_with_param(smu, 15372261229cSLikun Gao SMU_MSG_EnterBaco, 15382261229cSLikun Gao D3HOT_BACO_SEQUENCE, 15392261229cSLikun Gao NULL); 15402261229cSLikun Gao break; 15412261229cSLikun Gao default: 15428ab0d6f0SLuben Tuikov if (!ras || !adev->ras_enabled || 1543acdae216SLuben Tuikov adev->gmc.xgmi.pending_reset) { 1544e9995d4aSEvan Quan if (adev->asic_type == CHIP_ARCTURUS) { 1545e9995d4aSEvan Quan data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT); 1546e9995d4aSEvan Quan data |= 0x80000000; 1547e9995d4aSEvan Quan WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT, data); 1548e9995d4aSEvan Quan } else { 1549e098bc96SEvan Quan data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL); 1550e098bc96SEvan Quan data |= 0x80000000; 1551e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data); 1552e9995d4aSEvan Quan } 1553e098bc96SEvan Quan 1554e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL); 1555e098bc96SEvan Quan } else { 1556e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1, NULL); 1557e098bc96SEvan Quan } 15582261229cSLikun Gao break; 15592261229cSLikun Gao } 15602261229cSLikun Gao 1561e098bc96SEvan Quan } else { 1562e098bc96SEvan Quan ret = smu_cmn_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL); 1563e098bc96SEvan Quan if (ret) 1564e098bc96SEvan Quan goto out; 1565e098bc96SEvan Quan 1566e098bc96SEvan Quan /* clear vbios scratch 6 and 7 for coming asic reinit */ 1567e098bc96SEvan Quan WREG32(adev->bios_scratch_reg_offset + 6, 0); 1568e098bc96SEvan Quan WREG32(adev->bios_scratch_reg_offset + 7, 0); 1569e098bc96SEvan Quan } 1570e098bc96SEvan Quan if (ret) 1571e098bc96SEvan Quan goto out; 1572e098bc96SEvan Quan 1573e098bc96SEvan Quan smu_baco->state = state; 1574e098bc96SEvan Quan out: 1575e098bc96SEvan Quan mutex_unlock(&smu_baco->mutex); 1576e098bc96SEvan Quan return ret; 1577e098bc96SEvan Quan } 1578e098bc96SEvan Quan 1579e098bc96SEvan Quan int smu_v11_0_baco_enter(struct smu_context *smu) 1580e098bc96SEvan Quan { 1581e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 1582e098bc96SEvan Quan int ret = 0; 1583e098bc96SEvan Quan 1584e098bc96SEvan Quan /* Arcturus does not need this audio workaround */ 1585e098bc96SEvan Quan if (adev->asic_type != CHIP_ARCTURUS) { 1586e098bc96SEvan Quan ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO); 1587e098bc96SEvan Quan if (ret) 1588e098bc96SEvan Quan return ret; 1589e098bc96SEvan Quan } 1590e098bc96SEvan Quan 1591e098bc96SEvan Quan ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER); 1592e098bc96SEvan Quan if (ret) 1593e098bc96SEvan Quan return ret; 1594e098bc96SEvan Quan 1595e098bc96SEvan Quan msleep(10); 1596e098bc96SEvan Quan 1597e098bc96SEvan Quan return ret; 1598e098bc96SEvan Quan } 1599e098bc96SEvan Quan 1600e098bc96SEvan Quan int smu_v11_0_baco_exit(struct smu_context *smu) 1601e098bc96SEvan Quan { 16026c20f157SEvan Quan return smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT); 1603e098bc96SEvan Quan } 1604e098bc96SEvan Quan 1605e098bc96SEvan Quan int smu_v11_0_mode1_reset(struct smu_context *smu) 1606e098bc96SEvan Quan { 1607e098bc96SEvan Quan int ret = 0; 1608e098bc96SEvan Quan 1609e098bc96SEvan Quan ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL); 1610e098bc96SEvan Quan if (!ret) 1611e098bc96SEvan Quan msleep(SMU11_MODE1_RESET_WAIT_TIME_IN_MS); 1612e098bc96SEvan Quan 1613e098bc96SEvan Quan return ret; 1614e098bc96SEvan Quan } 1615e098bc96SEvan Quan 16160e921596Sshaoyunl int smu_v11_0_set_light_sbr(struct smu_context *smu, bool enable) 16170e921596Sshaoyunl { 16180e921596Sshaoyunl int ret = 0; 16190e921596Sshaoyunl 16200e921596Sshaoyunl ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LightSBR, enable ? 1 : 0, NULL); 16210e921596Sshaoyunl 16220e921596Sshaoyunl return ret; 16230e921596Sshaoyunl } 16240e921596Sshaoyunl 16250e921596Sshaoyunl 1626e098bc96SEvan Quan int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 1627e098bc96SEvan Quan uint32_t *min, uint32_t *max) 1628e098bc96SEvan Quan { 1629e098bc96SEvan Quan int ret = 0, clk_id = 0; 1630e098bc96SEvan Quan uint32_t param = 0; 1631e098bc96SEvan Quan uint32_t clock_limit; 1632e098bc96SEvan Quan 1633e098bc96SEvan Quan if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { 1634e098bc96SEvan Quan switch (clk_type) { 1635e098bc96SEvan Quan case SMU_MCLK: 1636e098bc96SEvan Quan case SMU_UCLK: 1637e098bc96SEvan Quan clock_limit = smu->smu_table.boot_values.uclk; 1638e098bc96SEvan Quan break; 1639e098bc96SEvan Quan case SMU_GFXCLK: 1640e098bc96SEvan Quan case SMU_SCLK: 1641e098bc96SEvan Quan clock_limit = smu->smu_table.boot_values.gfxclk; 1642e098bc96SEvan Quan break; 1643e098bc96SEvan Quan case SMU_SOCCLK: 1644e098bc96SEvan Quan clock_limit = smu->smu_table.boot_values.socclk; 1645e098bc96SEvan Quan break; 1646e098bc96SEvan Quan default: 1647e098bc96SEvan Quan clock_limit = 0; 1648e098bc96SEvan Quan break; 1649e098bc96SEvan Quan } 1650e098bc96SEvan Quan 1651e098bc96SEvan Quan /* clock in Mhz unit */ 1652e098bc96SEvan Quan if (min) 1653e098bc96SEvan Quan *min = clock_limit / 100; 1654e098bc96SEvan Quan if (max) 1655e098bc96SEvan Quan *max = clock_limit / 100; 1656e098bc96SEvan Quan 1657e098bc96SEvan Quan return 0; 1658e098bc96SEvan Quan } 1659e098bc96SEvan Quan 1660e098bc96SEvan Quan clk_id = smu_cmn_to_asic_specific_index(smu, 1661e098bc96SEvan Quan CMN2ASIC_MAPPING_CLK, 1662e098bc96SEvan Quan clk_type); 1663e098bc96SEvan Quan if (clk_id < 0) { 1664e098bc96SEvan Quan ret = -EINVAL; 1665e098bc96SEvan Quan goto failed; 1666e098bc96SEvan Quan } 1667e098bc96SEvan Quan param = (clk_id & 0xffff) << 16; 1668e098bc96SEvan Quan 1669e098bc96SEvan Quan if (max) { 1670e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max); 1671e098bc96SEvan Quan if (ret) 1672e098bc96SEvan Quan goto failed; 1673e098bc96SEvan Quan } 1674e098bc96SEvan Quan 1675e098bc96SEvan Quan if (min) { 1676e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min); 1677e098bc96SEvan Quan if (ret) 1678e098bc96SEvan Quan goto failed; 1679e098bc96SEvan Quan } 1680e098bc96SEvan Quan 1681e098bc96SEvan Quan failed: 1682e098bc96SEvan Quan return ret; 1683e098bc96SEvan Quan } 1684e098bc96SEvan Quan 1685e098bc96SEvan Quan int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, 1686e098bc96SEvan Quan enum smu_clk_type clk_type, 1687e098bc96SEvan Quan uint32_t min, 1688e098bc96SEvan Quan uint32_t max) 1689e098bc96SEvan Quan { 1690e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 1691e098bc96SEvan Quan int ret = 0, clk_id = 0; 1692e098bc96SEvan Quan uint32_t param; 1693e098bc96SEvan Quan 1694e098bc96SEvan Quan if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1695e098bc96SEvan Quan return 0; 1696e098bc96SEvan Quan 1697e098bc96SEvan Quan clk_id = smu_cmn_to_asic_specific_index(smu, 1698e098bc96SEvan Quan CMN2ASIC_MAPPING_CLK, 1699e098bc96SEvan Quan clk_type); 1700e098bc96SEvan Quan if (clk_id < 0) 1701e098bc96SEvan Quan return clk_id; 1702e098bc96SEvan Quan 1703e098bc96SEvan Quan if (clk_type == SMU_GFXCLK) 1704e098bc96SEvan Quan amdgpu_gfx_off_ctrl(adev, false); 1705e098bc96SEvan Quan 1706e098bc96SEvan Quan if (max > 0) { 1707e098bc96SEvan Quan param = (uint32_t)((clk_id << 16) | (max & 0xffff)); 1708e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq, 1709e098bc96SEvan Quan param, NULL); 1710e098bc96SEvan Quan if (ret) 1711e098bc96SEvan Quan goto out; 1712e098bc96SEvan Quan } 1713e098bc96SEvan Quan 1714e098bc96SEvan Quan if (min > 0) { 1715e098bc96SEvan Quan param = (uint32_t)((clk_id << 16) | (min & 0xffff)); 1716e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq, 1717e098bc96SEvan Quan param, NULL); 1718e098bc96SEvan Quan if (ret) 1719e098bc96SEvan Quan goto out; 1720e098bc96SEvan Quan } 1721e098bc96SEvan Quan 1722e098bc96SEvan Quan out: 1723e098bc96SEvan Quan if (clk_type == SMU_GFXCLK) 1724e098bc96SEvan Quan amdgpu_gfx_off_ctrl(adev, true); 1725e098bc96SEvan Quan 1726e098bc96SEvan Quan return ret; 1727e098bc96SEvan Quan } 1728e098bc96SEvan Quan 1729e098bc96SEvan Quan int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu, 1730e098bc96SEvan Quan enum smu_clk_type clk_type, 1731e098bc96SEvan Quan uint32_t min, 1732e098bc96SEvan Quan uint32_t max) 1733e098bc96SEvan Quan { 1734e098bc96SEvan Quan int ret = 0, clk_id = 0; 1735e098bc96SEvan Quan uint32_t param; 1736e098bc96SEvan Quan 1737e098bc96SEvan Quan if (min <= 0 && max <= 0) 1738e098bc96SEvan Quan return -EINVAL; 1739e098bc96SEvan Quan 1740e098bc96SEvan Quan if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1741e098bc96SEvan Quan return 0; 1742e098bc96SEvan Quan 1743e098bc96SEvan Quan clk_id = smu_cmn_to_asic_specific_index(smu, 1744e098bc96SEvan Quan CMN2ASIC_MAPPING_CLK, 1745e098bc96SEvan Quan clk_type); 1746e098bc96SEvan Quan if (clk_id < 0) 1747e098bc96SEvan Quan return clk_id; 1748e098bc96SEvan Quan 1749e098bc96SEvan Quan if (max > 0) { 1750e098bc96SEvan Quan param = (uint32_t)((clk_id << 16) | (max & 0xffff)); 1751e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq, 1752e098bc96SEvan Quan param, NULL); 1753e098bc96SEvan Quan if (ret) 1754e098bc96SEvan Quan return ret; 1755e098bc96SEvan Quan } 1756e098bc96SEvan Quan 1757e098bc96SEvan Quan if (min > 0) { 1758e098bc96SEvan Quan param = (uint32_t)((clk_id << 16) | (min & 0xffff)); 1759e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq, 1760e098bc96SEvan Quan param, NULL); 1761e098bc96SEvan Quan if (ret) 1762e098bc96SEvan Quan return ret; 1763e098bc96SEvan Quan } 1764e098bc96SEvan Quan 1765e098bc96SEvan Quan return ret; 1766e098bc96SEvan Quan } 1767e098bc96SEvan Quan 1768e098bc96SEvan Quan int smu_v11_0_set_performance_level(struct smu_context *smu, 1769e098bc96SEvan Quan enum amd_dpm_forced_level level) 1770e098bc96SEvan Quan { 1771e098bc96SEvan Quan struct smu_11_0_dpm_context *dpm_context = 1772e098bc96SEvan Quan smu->smu_dpm.dpm_context; 1773e098bc96SEvan Quan struct smu_11_0_dpm_table *gfx_table = 1774e098bc96SEvan Quan &dpm_context->dpm_tables.gfx_table; 1775e098bc96SEvan Quan struct smu_11_0_dpm_table *mem_table = 1776e098bc96SEvan Quan &dpm_context->dpm_tables.uclk_table; 1777e098bc96SEvan Quan struct smu_11_0_dpm_table *soc_table = 1778e098bc96SEvan Quan &dpm_context->dpm_tables.soc_table; 1779e098bc96SEvan Quan struct smu_umd_pstate_table *pstate_table = 1780e098bc96SEvan Quan &smu->pstate_table; 1781e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 1782e098bc96SEvan Quan uint32_t sclk_min = 0, sclk_max = 0; 1783e098bc96SEvan Quan uint32_t mclk_min = 0, mclk_max = 0; 1784e098bc96SEvan Quan uint32_t socclk_min = 0, socclk_max = 0; 1785e098bc96SEvan Quan int ret = 0; 1786e098bc96SEvan Quan 1787e098bc96SEvan Quan switch (level) { 1788e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_HIGH: 1789e098bc96SEvan Quan sclk_min = sclk_max = gfx_table->max; 1790e098bc96SEvan Quan mclk_min = mclk_max = mem_table->max; 1791e098bc96SEvan Quan socclk_min = socclk_max = soc_table->max; 1792e098bc96SEvan Quan break; 1793e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_LOW: 1794e098bc96SEvan Quan sclk_min = sclk_max = gfx_table->min; 1795e098bc96SEvan Quan mclk_min = mclk_max = mem_table->min; 1796e098bc96SEvan Quan socclk_min = socclk_max = soc_table->min; 1797e098bc96SEvan Quan break; 1798e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_AUTO: 1799e098bc96SEvan Quan sclk_min = gfx_table->min; 1800e098bc96SEvan Quan sclk_max = gfx_table->max; 1801e098bc96SEvan Quan mclk_min = mem_table->min; 1802e098bc96SEvan Quan mclk_max = mem_table->max; 1803e098bc96SEvan Quan socclk_min = soc_table->min; 1804e098bc96SEvan Quan socclk_max = soc_table->max; 1805e098bc96SEvan Quan break; 1806e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1807e098bc96SEvan Quan sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard; 1808e098bc96SEvan Quan mclk_min = mclk_max = pstate_table->uclk_pstate.standard; 1809e098bc96SEvan Quan socclk_min = socclk_max = pstate_table->socclk_pstate.standard; 1810e098bc96SEvan Quan break; 1811e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1812e098bc96SEvan Quan sclk_min = sclk_max = pstate_table->gfxclk_pstate.min; 1813e098bc96SEvan Quan break; 1814e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1815e098bc96SEvan Quan mclk_min = mclk_max = pstate_table->uclk_pstate.min; 1816e098bc96SEvan Quan break; 1817e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1818e098bc96SEvan Quan sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak; 1819e098bc96SEvan Quan mclk_min = mclk_max = pstate_table->uclk_pstate.peak; 1820e098bc96SEvan Quan socclk_min = socclk_max = pstate_table->socclk_pstate.peak; 1821e098bc96SEvan Quan break; 1822e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_MANUAL: 1823e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1824e098bc96SEvan Quan return 0; 1825e098bc96SEvan Quan default: 1826e098bc96SEvan Quan dev_err(adev->dev, "Invalid performance level %d\n", level); 1827e098bc96SEvan Quan return -EINVAL; 1828e098bc96SEvan Quan } 1829e098bc96SEvan Quan 1830e098bc96SEvan Quan /* 1831e098bc96SEvan Quan * Separate MCLK and SOCCLK soft min/max settings are not allowed 1832e098bc96SEvan Quan * on Arcturus. 1833e098bc96SEvan Quan */ 1834e098bc96SEvan Quan if (adev->asic_type == CHIP_ARCTURUS) { 1835e098bc96SEvan Quan mclk_min = mclk_max = 0; 1836e098bc96SEvan Quan socclk_min = socclk_max = 0; 1837e098bc96SEvan Quan } 1838e098bc96SEvan Quan 1839e098bc96SEvan Quan if (sclk_min && sclk_max) { 1840e098bc96SEvan Quan ret = smu_v11_0_set_soft_freq_limited_range(smu, 1841e098bc96SEvan Quan SMU_GFXCLK, 1842e098bc96SEvan Quan sclk_min, 1843e098bc96SEvan Quan sclk_max); 1844e098bc96SEvan Quan if (ret) 1845e098bc96SEvan Quan return ret; 1846e098bc96SEvan Quan } 1847e098bc96SEvan Quan 1848e098bc96SEvan Quan if (mclk_min && mclk_max) { 1849e098bc96SEvan Quan ret = smu_v11_0_set_soft_freq_limited_range(smu, 1850e098bc96SEvan Quan SMU_MCLK, 1851e098bc96SEvan Quan mclk_min, 1852e098bc96SEvan Quan mclk_max); 1853e098bc96SEvan Quan if (ret) 1854e098bc96SEvan Quan return ret; 1855e098bc96SEvan Quan } 1856e098bc96SEvan Quan 1857e098bc96SEvan Quan if (socclk_min && socclk_max) { 1858e098bc96SEvan Quan ret = smu_v11_0_set_soft_freq_limited_range(smu, 1859e098bc96SEvan Quan SMU_SOCCLK, 1860e098bc96SEvan Quan socclk_min, 1861e098bc96SEvan Quan socclk_max); 1862e098bc96SEvan Quan if (ret) 1863e098bc96SEvan Quan return ret; 1864e098bc96SEvan Quan } 1865e098bc96SEvan Quan 1866e098bc96SEvan Quan return ret; 1867e098bc96SEvan Quan } 1868e098bc96SEvan Quan 1869e098bc96SEvan Quan int smu_v11_0_set_power_source(struct smu_context *smu, 1870e098bc96SEvan Quan enum smu_power_src_type power_src) 1871e098bc96SEvan Quan { 1872e098bc96SEvan Quan int pwr_source; 1873e098bc96SEvan Quan 1874e098bc96SEvan Quan pwr_source = smu_cmn_to_asic_specific_index(smu, 1875e098bc96SEvan Quan CMN2ASIC_MAPPING_PWR, 1876e098bc96SEvan Quan (uint32_t)power_src); 1877e098bc96SEvan Quan if (pwr_source < 0) 1878e098bc96SEvan Quan return -EINVAL; 1879e098bc96SEvan Quan 1880e098bc96SEvan Quan return smu_cmn_send_smc_msg_with_param(smu, 1881e098bc96SEvan Quan SMU_MSG_NotifyPowerSource, 1882e098bc96SEvan Quan pwr_source, 1883e098bc96SEvan Quan NULL); 1884e098bc96SEvan Quan } 1885e098bc96SEvan Quan 1886e098bc96SEvan Quan int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu, 1887e098bc96SEvan Quan enum smu_clk_type clk_type, 1888e098bc96SEvan Quan uint16_t level, 1889e098bc96SEvan Quan uint32_t *value) 1890e098bc96SEvan Quan { 1891e098bc96SEvan Quan int ret = 0, clk_id = 0; 1892e098bc96SEvan Quan uint32_t param; 1893e098bc96SEvan Quan 1894e098bc96SEvan Quan if (!value) 1895e098bc96SEvan Quan return -EINVAL; 1896e098bc96SEvan Quan 1897e098bc96SEvan Quan if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1898e098bc96SEvan Quan return 0; 1899e098bc96SEvan Quan 1900e098bc96SEvan Quan clk_id = smu_cmn_to_asic_specific_index(smu, 1901e098bc96SEvan Quan CMN2ASIC_MAPPING_CLK, 1902e098bc96SEvan Quan clk_type); 1903e098bc96SEvan Quan if (clk_id < 0) 1904e098bc96SEvan Quan return clk_id; 1905e098bc96SEvan Quan 1906e098bc96SEvan Quan param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff)); 1907e098bc96SEvan Quan 1908e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, 1909e098bc96SEvan Quan SMU_MSG_GetDpmFreqByIndex, 1910e098bc96SEvan Quan param, 1911e098bc96SEvan Quan value); 1912e098bc96SEvan Quan if (ret) 1913e098bc96SEvan Quan return ret; 1914e098bc96SEvan Quan 1915e098bc96SEvan Quan /* 1916e098bc96SEvan Quan * BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM 1917e098bc96SEvan Quan * now, we un-support it 1918e098bc96SEvan Quan */ 1919e098bc96SEvan Quan *value = *value & 0x7fffffff; 1920e098bc96SEvan Quan 1921e098bc96SEvan Quan return ret; 1922e098bc96SEvan Quan } 1923e098bc96SEvan Quan 1924e098bc96SEvan Quan int smu_v11_0_get_dpm_level_count(struct smu_context *smu, 1925e098bc96SEvan Quan enum smu_clk_type clk_type, 1926e098bc96SEvan Quan uint32_t *value) 1927e098bc96SEvan Quan { 1928e098bc96SEvan Quan return smu_v11_0_get_dpm_freq_by_index(smu, 1929e098bc96SEvan Quan clk_type, 1930e098bc96SEvan Quan 0xff, 1931e098bc96SEvan Quan value); 1932e098bc96SEvan Quan } 1933e098bc96SEvan Quan 1934e098bc96SEvan Quan int smu_v11_0_set_single_dpm_table(struct smu_context *smu, 1935e098bc96SEvan Quan enum smu_clk_type clk_type, 1936e098bc96SEvan Quan struct smu_11_0_dpm_table *single_dpm_table) 1937e098bc96SEvan Quan { 1938e098bc96SEvan Quan int ret = 0; 1939e098bc96SEvan Quan uint32_t clk; 1940e098bc96SEvan Quan int i; 1941e098bc96SEvan Quan 1942e098bc96SEvan Quan ret = smu_v11_0_get_dpm_level_count(smu, 1943e098bc96SEvan Quan clk_type, 1944e098bc96SEvan Quan &single_dpm_table->count); 1945e098bc96SEvan Quan if (ret) { 1946e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__); 1947e098bc96SEvan Quan return ret; 1948e098bc96SEvan Quan } 1949e098bc96SEvan Quan 1950e098bc96SEvan Quan for (i = 0; i < single_dpm_table->count; i++) { 1951e098bc96SEvan Quan ret = smu_v11_0_get_dpm_freq_by_index(smu, 1952e098bc96SEvan Quan clk_type, 1953e098bc96SEvan Quan i, 1954e098bc96SEvan Quan &clk); 1955e098bc96SEvan Quan if (ret) { 1956e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__); 1957e098bc96SEvan Quan return ret; 1958e098bc96SEvan Quan } 1959e098bc96SEvan Quan 1960e098bc96SEvan Quan single_dpm_table->dpm_levels[i].value = clk; 1961e098bc96SEvan Quan single_dpm_table->dpm_levels[i].enabled = true; 1962e098bc96SEvan Quan 1963e098bc96SEvan Quan if (i == 0) 1964e098bc96SEvan Quan single_dpm_table->min = clk; 1965e098bc96SEvan Quan else if (i == single_dpm_table->count - 1) 1966e098bc96SEvan Quan single_dpm_table->max = clk; 1967e098bc96SEvan Quan } 1968e098bc96SEvan Quan 1969e098bc96SEvan Quan return 0; 1970e098bc96SEvan Quan } 1971e098bc96SEvan Quan 1972e098bc96SEvan Quan int smu_v11_0_get_dpm_level_range(struct smu_context *smu, 1973e098bc96SEvan Quan enum smu_clk_type clk_type, 1974e098bc96SEvan Quan uint32_t *min_value, 1975e098bc96SEvan Quan uint32_t *max_value) 1976e098bc96SEvan Quan { 1977e098bc96SEvan Quan uint32_t level_count = 0; 1978e098bc96SEvan Quan int ret = 0; 1979e098bc96SEvan Quan 1980e098bc96SEvan Quan if (!min_value && !max_value) 1981e098bc96SEvan Quan return -EINVAL; 1982e098bc96SEvan Quan 1983e098bc96SEvan Quan if (min_value) { 1984e098bc96SEvan Quan /* by default, level 0 clock value as min value */ 1985e098bc96SEvan Quan ret = smu_v11_0_get_dpm_freq_by_index(smu, 1986e098bc96SEvan Quan clk_type, 1987e098bc96SEvan Quan 0, 1988e098bc96SEvan Quan min_value); 1989e098bc96SEvan Quan if (ret) 1990e098bc96SEvan Quan return ret; 1991e098bc96SEvan Quan } 1992e098bc96SEvan Quan 1993e098bc96SEvan Quan if (max_value) { 1994e098bc96SEvan Quan ret = smu_v11_0_get_dpm_level_count(smu, 1995e098bc96SEvan Quan clk_type, 1996e098bc96SEvan Quan &level_count); 1997e098bc96SEvan Quan if (ret) 1998e098bc96SEvan Quan return ret; 1999e098bc96SEvan Quan 2000e098bc96SEvan Quan ret = smu_v11_0_get_dpm_freq_by_index(smu, 2001e098bc96SEvan Quan clk_type, 2002e098bc96SEvan Quan level_count - 1, 2003e098bc96SEvan Quan max_value); 2004e098bc96SEvan Quan if (ret) 2005e098bc96SEvan Quan return ret; 2006e098bc96SEvan Quan } 2007e098bc96SEvan Quan 2008e098bc96SEvan Quan return ret; 2009e098bc96SEvan Quan } 2010e098bc96SEvan Quan 2011e098bc96SEvan Quan int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu) 2012e098bc96SEvan Quan { 2013e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 2014e098bc96SEvan Quan 2015e098bc96SEvan Quan return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & 2016e098bc96SEvan Quan PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) 2017e098bc96SEvan Quan >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; 2018e098bc96SEvan Quan } 2019e098bc96SEvan Quan 2020152bb95cSEvan Quan uint16_t smu_v11_0_get_current_pcie_link_width(struct smu_context *smu) 2021e098bc96SEvan Quan { 2022e098bc96SEvan Quan uint32_t width_level; 2023e098bc96SEvan Quan 2024e098bc96SEvan Quan width_level = smu_v11_0_get_current_pcie_link_width_level(smu); 2025e098bc96SEvan Quan if (width_level > LINK_WIDTH_MAX) 2026e098bc96SEvan Quan width_level = 0; 2027e098bc96SEvan Quan 2028e098bc96SEvan Quan return link_width[width_level]; 2029e098bc96SEvan Quan } 2030e098bc96SEvan Quan 2031e098bc96SEvan Quan int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu) 2032e098bc96SEvan Quan { 2033e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 2034e098bc96SEvan Quan 2035e098bc96SEvan Quan return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & 2036e098bc96SEvan Quan PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) 2037e098bc96SEvan Quan >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 2038e098bc96SEvan Quan } 2039e098bc96SEvan Quan 2040152bb95cSEvan Quan uint16_t smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu) 2041e098bc96SEvan Quan { 2042e098bc96SEvan Quan uint32_t speed_level; 2043e098bc96SEvan Quan 2044e098bc96SEvan Quan speed_level = smu_v11_0_get_current_pcie_link_speed_level(smu); 2045e098bc96SEvan Quan if (speed_level > LINK_SPEED_MAX) 2046e098bc96SEvan Quan speed_level = 0; 2047e098bc96SEvan Quan 2048e098bc96SEvan Quan return link_speed[speed_level]; 2049e098bc96SEvan Quan } 2050e098bc96SEvan Quan 2051e988026fSEvan Quan int smu_v11_0_gfx_ulv_control(struct smu_context *smu, 2052e988026fSEvan Quan bool enablement) 2053e988026fSEvan Quan { 2054e988026fSEvan Quan int ret = 0; 2055e988026fSEvan Quan 2056e988026fSEvan Quan if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT)) 2057e988026fSEvan Quan ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement); 2058e988026fSEvan Quan 2059e988026fSEvan Quan return ret; 2060e988026fSEvan Quan } 20615ce99853SEvan Quan 20625ce99853SEvan Quan int smu_v11_0_deep_sleep_control(struct smu_context *smu, 20635ce99853SEvan Quan bool enablement) 20645ce99853SEvan Quan { 20655ce99853SEvan Quan struct amdgpu_device *adev = smu->adev; 20665ce99853SEvan Quan int ret = 0; 20675ce99853SEvan Quan 20685ce99853SEvan Quan if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) { 20695ce99853SEvan Quan ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement); 20705ce99853SEvan Quan if (ret) { 20715ce99853SEvan Quan dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable"); 20725ce99853SEvan Quan return ret; 20735ce99853SEvan Quan } 20745ce99853SEvan Quan } 20755ce99853SEvan Quan 207678d907e2SEvan Quan if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) { 207778d907e2SEvan Quan ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement); 207878d907e2SEvan Quan if (ret) { 207978d907e2SEvan Quan dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable"); 208078d907e2SEvan Quan return ret; 208178d907e2SEvan Quan } 208278d907e2SEvan Quan } 208378d907e2SEvan Quan 208478d907e2SEvan Quan if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) { 208578d907e2SEvan Quan ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement); 208678d907e2SEvan Quan if (ret) { 208778d907e2SEvan Quan dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable"); 208878d907e2SEvan Quan return ret; 208978d907e2SEvan Quan } 209078d907e2SEvan Quan } 209178d907e2SEvan Quan 20925ce99853SEvan Quan if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) { 20935ce99853SEvan Quan ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement); 20945ce99853SEvan Quan if (ret) { 20955ce99853SEvan Quan dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable"); 20965ce99853SEvan Quan return ret; 20975ce99853SEvan Quan } 20985ce99853SEvan Quan } 20995ce99853SEvan Quan 21005ce99853SEvan Quan if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) { 21015ce99853SEvan Quan ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement); 21025ce99853SEvan Quan if (ret) { 21035ce99853SEvan Quan dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable"); 21045ce99853SEvan Quan return ret; 21055ce99853SEvan Quan } 21065ce99853SEvan Quan } 21075ce99853SEvan Quan 21085ce99853SEvan Quan return ret; 21095ce99853SEvan Quan } 2110