1e098bc96SEvan Quan /* 2e098bc96SEvan Quan * Copyright 2019 Advanced Micro Devices, Inc. 3e098bc96SEvan Quan * 4e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"), 6e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation 7e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions: 10e098bc96SEvan Quan * 11e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in 12e098bc96SEvan Quan * all copies or substantial portions of the Software. 13e098bc96SEvan Quan * 14e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21e098bc96SEvan Quan */ 22e098bc96SEvan Quan 23e098bc96SEvan Quan #include <linux/firmware.h> 24e098bc96SEvan Quan #include <linux/module.h> 25e098bc96SEvan Quan #include <linux/pci.h> 26e098bc96SEvan Quan #include <linux/reboot.h> 27e098bc96SEvan Quan 28e098bc96SEvan Quan #define SMU_11_0_PARTIAL_PPTABLE 29e098bc96SEvan Quan #define SWSMU_CODE_LAYER_L3 30e098bc96SEvan Quan 31e098bc96SEvan Quan #include "amdgpu.h" 32e098bc96SEvan Quan #include "amdgpu_smu.h" 33e098bc96SEvan Quan #include "atomfirmware.h" 34e098bc96SEvan Quan #include "amdgpu_atomfirmware.h" 35e098bc96SEvan Quan #include "amdgpu_atombios.h" 36e098bc96SEvan Quan #include "smu_v11_0.h" 37e098bc96SEvan Quan #include "soc15_common.h" 38e098bc96SEvan Quan #include "atom.h" 39e098bc96SEvan Quan #include "amdgpu_ras.h" 40e098bc96SEvan Quan #include "smu_cmn.h" 41e098bc96SEvan Quan 42e098bc96SEvan Quan #include "asic_reg/thm/thm_11_0_2_offset.h" 43e098bc96SEvan Quan #include "asic_reg/thm/thm_11_0_2_sh_mask.h" 44e098bc96SEvan Quan #include "asic_reg/mp/mp_11_0_offset.h" 45e098bc96SEvan Quan #include "asic_reg/mp/mp_11_0_sh_mask.h" 46e098bc96SEvan Quan #include "asic_reg/smuio/smuio_11_0_0_offset.h" 47e098bc96SEvan Quan #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h" 48e098bc96SEvan Quan 49e098bc96SEvan Quan /* 50e098bc96SEvan Quan * DO NOT use these for err/warn/info/debug messages. 51e098bc96SEvan Quan * Use dev_err, dev_warn, dev_info and dev_dbg instead. 52e098bc96SEvan Quan * They are more MGPU friendly. 53e098bc96SEvan Quan */ 54e098bc96SEvan Quan #undef pr_err 55e098bc96SEvan Quan #undef pr_warn 56e098bc96SEvan Quan #undef pr_info 57e098bc96SEvan Quan #undef pr_debug 58e098bc96SEvan Quan 59e098bc96SEvan Quan MODULE_FIRMWARE("amdgpu/arcturus_smc.bin"); 60e098bc96SEvan Quan MODULE_FIRMWARE("amdgpu/navi10_smc.bin"); 61e098bc96SEvan Quan MODULE_FIRMWARE("amdgpu/navi14_smc.bin"); 62e098bc96SEvan Quan MODULE_FIRMWARE("amdgpu/navi12_smc.bin"); 63e098bc96SEvan Quan MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin"); 64e098bc96SEvan Quan MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin"); 65db1f8a8fSTao Zhou MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin"); 664d352669SChengming Gui MODULE_FIRMWARE("amdgpu/beige_goby_smc.bin"); 67e098bc96SEvan Quan 68e098bc96SEvan Quan #define SMU11_VOLTAGE_SCALE 4 69e098bc96SEvan Quan 70e098bc96SEvan Quan #define SMU11_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms 71e098bc96SEvan Quan 72e098bc96SEvan Quan #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 73e098bc96SEvan Quan #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L 74e098bc96SEvan Quan #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 75e098bc96SEvan Quan #define smnPCIE_LC_SPEED_CNTL 0x11140290 76e098bc96SEvan Quan #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000 77e098bc96SEvan Quan #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE 78e098bc96SEvan Quan 79e9995d4aSEvan Quan #define mmTHM_BACO_CNTL_ARCT 0xA7 80e9995d4aSEvan Quan #define mmTHM_BACO_CNTL_ARCT_BASE_IDX 0 81e9995d4aSEvan Quan 82e098bc96SEvan Quan int smu_v11_0_init_microcode(struct smu_context *smu) 83e098bc96SEvan Quan { 84e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 85e098bc96SEvan Quan const char *chip_name; 8610e0d9ebSTao Zhou char fw_name[SMU_FW_NAME_LEN]; 87e098bc96SEvan Quan int err = 0; 88e098bc96SEvan Quan const struct smc_firmware_header_v1_0 *hdr; 89e098bc96SEvan Quan const struct common_firmware_header *header; 90e098bc96SEvan Quan struct amdgpu_firmware_info *ucode = NULL; 91e098bc96SEvan Quan 9286b6037fSStanley.Yang if (amdgpu_sriov_vf(adev) && 931d789535SAlex Deucher ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9)) || 941d789535SAlex Deucher (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)))) 9586b6037fSStanley.Yang return 0; 9686b6037fSStanley.Yang 971d789535SAlex Deucher switch (adev->ip_versions[MP1_HWIP][0]) { 98af3b89d3SAlex Deucher case IP_VERSION(11, 0, 0): 99e098bc96SEvan Quan chip_name = "navi10"; 100e098bc96SEvan Quan break; 101af3b89d3SAlex Deucher case IP_VERSION(11, 0, 5): 102e098bc96SEvan Quan chip_name = "navi14"; 103e098bc96SEvan Quan break; 104af3b89d3SAlex Deucher case IP_VERSION(11, 0, 9): 105e098bc96SEvan Quan chip_name = "navi12"; 106e098bc96SEvan Quan break; 107af3b89d3SAlex Deucher case IP_VERSION(11, 0, 7): 108e098bc96SEvan Quan chip_name = "sienna_cichlid"; 109e098bc96SEvan Quan break; 110af3b89d3SAlex Deucher case IP_VERSION(11, 0, 11): 111e098bc96SEvan Quan chip_name = "navy_flounder"; 112e098bc96SEvan Quan break; 113af3b89d3SAlex Deucher case IP_VERSION(11, 0, 12): 114db1f8a8fSTao Zhou chip_name = "dimgrey_cavefish"; 115db1f8a8fSTao Zhou break; 116af3b89d3SAlex Deucher case IP_VERSION(11, 0, 13): 1174d352669SChengming Gui chip_name = "beige_goby"; 1184d352669SChengming Gui break; 1196b726a0aSAlex Deucher case IP_VERSION(11, 0, 2): 120af3b89d3SAlex Deucher chip_name = "arcturus"; 121af3b89d3SAlex Deucher break; 1226b726a0aSAlex Deucher default: 1236b726a0aSAlex Deucher dev_err(adev->dev, "Unsupported IP version 0x%x\n", 1241d789535SAlex Deucher adev->ip_versions[MP1_HWIP][0]); 125e098bc96SEvan Quan return -EINVAL; 126e098bc96SEvan Quan } 127e098bc96SEvan Quan 128e098bc96SEvan Quan snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name); 129e098bc96SEvan Quan 130e098bc96SEvan Quan err = request_firmware(&adev->pm.fw, fw_name, adev->dev); 131e098bc96SEvan Quan if (err) 132e098bc96SEvan Quan goto out; 133e098bc96SEvan Quan err = amdgpu_ucode_validate(adev->pm.fw); 134e098bc96SEvan Quan if (err) 135e098bc96SEvan Quan goto out; 136e098bc96SEvan Quan 137e098bc96SEvan Quan hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 138e098bc96SEvan Quan amdgpu_ucode_print_smc_hdr(&hdr->header); 139e098bc96SEvan Quan adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version); 140e098bc96SEvan Quan 141e098bc96SEvan Quan if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 142e098bc96SEvan Quan ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 143e098bc96SEvan Quan ucode->ucode_id = AMDGPU_UCODE_ID_SMC; 144e098bc96SEvan Quan ucode->fw = adev->pm.fw; 145e098bc96SEvan Quan header = (const struct common_firmware_header *)ucode->fw->data; 146e098bc96SEvan Quan adev->firmware.fw_size += 147e098bc96SEvan Quan ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 148e098bc96SEvan Quan } 149e098bc96SEvan Quan 150e098bc96SEvan Quan out: 151e098bc96SEvan Quan if (err) { 152e098bc96SEvan Quan DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n", 153e098bc96SEvan Quan fw_name); 154e098bc96SEvan Quan release_firmware(adev->pm.fw); 155e098bc96SEvan Quan adev->pm.fw = NULL; 156e098bc96SEvan Quan } 157e098bc96SEvan Quan return err; 158e098bc96SEvan Quan } 159e098bc96SEvan Quan 160e098bc96SEvan Quan void smu_v11_0_fini_microcode(struct smu_context *smu) 161e098bc96SEvan Quan { 162e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 163e098bc96SEvan Quan 164e098bc96SEvan Quan release_firmware(adev->pm.fw); 165e098bc96SEvan Quan adev->pm.fw = NULL; 166e098bc96SEvan Quan adev->pm.fw_version = 0; 167e098bc96SEvan Quan } 168e098bc96SEvan Quan 169e098bc96SEvan Quan int smu_v11_0_load_microcode(struct smu_context *smu) 170e098bc96SEvan Quan { 171e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 172e098bc96SEvan Quan const uint32_t *src; 173e098bc96SEvan Quan const struct smc_firmware_header_v1_0 *hdr; 174e098bc96SEvan Quan uint32_t addr_start = MP1_SRAM; 175e098bc96SEvan Quan uint32_t i; 176e098bc96SEvan Quan uint32_t smc_fw_size; 177e098bc96SEvan Quan uint32_t mp1_fw_flags; 178e098bc96SEvan Quan 179e098bc96SEvan Quan hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 180e098bc96SEvan Quan src = (const uint32_t *)(adev->pm.fw->data + 181e098bc96SEvan Quan le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 182e098bc96SEvan Quan smc_fw_size = hdr->header.ucode_size_bytes; 183e098bc96SEvan Quan 184e098bc96SEvan Quan for (i = 1; i < smc_fw_size/4 - 1; i++) { 185e098bc96SEvan Quan WREG32_PCIE(addr_start, src[i]); 186e098bc96SEvan Quan addr_start += 4; 187e098bc96SEvan Quan } 188e098bc96SEvan Quan 189e098bc96SEvan Quan WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), 190e098bc96SEvan Quan 1 & MP1_SMN_PUB_CTRL__RESET_MASK); 191e098bc96SEvan Quan WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), 192e098bc96SEvan Quan 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK); 193e098bc96SEvan Quan 194e098bc96SEvan Quan for (i = 0; i < adev->usec_timeout; i++) { 195e098bc96SEvan Quan mp1_fw_flags = RREG32_PCIE(MP1_Public | 196e098bc96SEvan Quan (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); 197e098bc96SEvan Quan if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 198e098bc96SEvan Quan MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 199e098bc96SEvan Quan break; 200e098bc96SEvan Quan udelay(1); 201e098bc96SEvan Quan } 202e098bc96SEvan Quan 203e098bc96SEvan Quan if (i == adev->usec_timeout) 204e098bc96SEvan Quan return -ETIME; 205e098bc96SEvan Quan 206e098bc96SEvan Quan return 0; 207e098bc96SEvan Quan } 208e098bc96SEvan Quan 209e098bc96SEvan Quan int smu_v11_0_check_fw_status(struct smu_context *smu) 210e098bc96SEvan Quan { 211e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 212e098bc96SEvan Quan uint32_t mp1_fw_flags; 213e098bc96SEvan Quan 214e098bc96SEvan Quan mp1_fw_flags = RREG32_PCIE(MP1_Public | 215e098bc96SEvan Quan (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); 216e098bc96SEvan Quan 217e098bc96SEvan Quan if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 218e098bc96SEvan Quan MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 219e098bc96SEvan Quan return 0; 220e098bc96SEvan Quan 221e098bc96SEvan Quan return -EIO; 222e098bc96SEvan Quan } 223e098bc96SEvan Quan 224e098bc96SEvan Quan int smu_v11_0_check_fw_version(struct smu_context *smu) 225e098bc96SEvan Quan { 226dda818a0SAlex Deucher struct amdgpu_device *adev = smu->adev; 227e098bc96SEvan Quan uint32_t if_version = 0xff, smu_version = 0xff; 22882890466SMario Limonciello uint8_t smu_program, smu_major, smu_minor, smu_debug; 229e098bc96SEvan Quan int ret = 0; 230e098bc96SEvan Quan 231e098bc96SEvan Quan ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 232e098bc96SEvan Quan if (ret) 233e098bc96SEvan Quan return ret; 234e098bc96SEvan Quan 23582890466SMario Limonciello smu_program = (smu_version >> 24) & 0xff; 23682890466SMario Limonciello smu_major = (smu_version >> 16) & 0xff; 237e098bc96SEvan Quan smu_minor = (smu_version >> 8) & 0xff; 238e098bc96SEvan Quan smu_debug = (smu_version >> 0) & 0xff; 239dda818a0SAlex Deucher if (smu->is_apu) 240dda818a0SAlex Deucher adev->pm.fw_version = smu_version; 241e098bc96SEvan Quan 2421d789535SAlex Deucher switch (adev->ip_versions[MP1_HWIP][0]) { 243af3b89d3SAlex Deucher case IP_VERSION(11, 0, 0): 244e098bc96SEvan Quan smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10; 245e098bc96SEvan Quan break; 246af3b89d3SAlex Deucher case IP_VERSION(11, 0, 9): 247e098bc96SEvan Quan smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12; 248e098bc96SEvan Quan break; 249af3b89d3SAlex Deucher case IP_VERSION(11, 0, 5): 250e098bc96SEvan Quan smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14; 251e098bc96SEvan Quan break; 252af3b89d3SAlex Deucher case IP_VERSION(11, 0, 7): 253e098bc96SEvan Quan smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid; 254e098bc96SEvan Quan break; 255af3b89d3SAlex Deucher case IP_VERSION(11, 0, 11): 256e098bc96SEvan Quan smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder; 257e098bc96SEvan Quan break; 25876c023faSAlex Deucher case IP_VERSION(11, 5, 0): 25988779658SXiaojian Du smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VANGOGH; 26088779658SXiaojian Du break; 261af3b89d3SAlex Deucher case IP_VERSION(11, 0, 12): 262db1f8a8fSTao Zhou smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish; 263db1f8a8fSTao Zhou break; 264af3b89d3SAlex Deucher case IP_VERSION(11, 0, 13): 2654d352669SChengming Gui smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Beige_Goby; 2664d352669SChengming Gui break; 267af3b89d3SAlex Deucher case IP_VERSION(11, 0, 8): 26861ad757dSLang Yu smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Cyan_Skillfish; 26961ad757dSLang Yu break; 2706b726a0aSAlex Deucher case IP_VERSION(11, 0, 2): 271af3b89d3SAlex Deucher smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT; 272af3b89d3SAlex Deucher break; 2736b726a0aSAlex Deucher default: 2746b726a0aSAlex Deucher dev_err(smu->adev->dev, "smu unsupported IP version: 0x%x.\n", 2751d789535SAlex Deucher adev->ip_versions[MP1_HWIP][0]); 276e098bc96SEvan Quan smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV; 277e098bc96SEvan Quan break; 278e098bc96SEvan Quan } 279e098bc96SEvan Quan 280e098bc96SEvan Quan /* 281e098bc96SEvan Quan * 1. if_version mismatch is not critical as our fw is designed 282e098bc96SEvan Quan * to be backward compatible. 283e098bc96SEvan Quan * 2. New fw usually brings some optimizations. But that's visible 284e098bc96SEvan Quan * only on the paired driver. 285e098bc96SEvan Quan * Considering above, we just leave user a warning message instead 286e098bc96SEvan Quan * of halt driver loading. 287e098bc96SEvan Quan */ 288e098bc96SEvan Quan if (if_version != smu->smc_driver_if_version) { 289e098bc96SEvan Quan dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, " 29082890466SMario Limonciello "smu fw program = %d, version = 0x%08x (%d.%d.%d)\n", 291e098bc96SEvan Quan smu->smc_driver_if_version, if_version, 29282890466SMario Limonciello smu_program, smu_version, smu_major, smu_minor, smu_debug); 293e098bc96SEvan Quan dev_warn(smu->adev->dev, "SMU driver if version not matched\n"); 294e098bc96SEvan Quan } 295e098bc96SEvan Quan 296e098bc96SEvan Quan return ret; 297e098bc96SEvan Quan } 298e098bc96SEvan Quan 299e098bc96SEvan Quan static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size) 300e098bc96SEvan Quan { 301e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 302e098bc96SEvan Quan uint32_t ppt_offset_bytes; 303e098bc96SEvan Quan const struct smc_firmware_header_v2_0 *v2; 304e098bc96SEvan Quan 305e098bc96SEvan Quan v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data; 306e098bc96SEvan Quan 307e098bc96SEvan Quan ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes); 308e098bc96SEvan Quan *size = le32_to_cpu(v2->ppt_size_bytes); 309e098bc96SEvan Quan *table = (uint8_t *)v2 + ppt_offset_bytes; 310e098bc96SEvan Quan 311e098bc96SEvan Quan return 0; 312e098bc96SEvan Quan } 313e098bc96SEvan Quan 314e098bc96SEvan Quan static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table, 315e098bc96SEvan Quan uint32_t *size, uint32_t pptable_id) 316e098bc96SEvan Quan { 317e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 318e098bc96SEvan Quan const struct smc_firmware_header_v2_1 *v2_1; 319e098bc96SEvan Quan struct smc_soft_pptable_entry *entries; 320e098bc96SEvan Quan uint32_t pptable_count = 0; 321e098bc96SEvan Quan int i = 0; 322e098bc96SEvan Quan 323e098bc96SEvan Quan v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data; 324e098bc96SEvan Quan entries = (struct smc_soft_pptable_entry *) 325e098bc96SEvan Quan ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset)); 326e098bc96SEvan Quan pptable_count = le32_to_cpu(v2_1->pptable_count); 327e098bc96SEvan Quan for (i = 0; i < pptable_count; i++) { 328e098bc96SEvan Quan if (le32_to_cpu(entries[i].id) == pptable_id) { 329e098bc96SEvan Quan *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes)); 330e098bc96SEvan Quan *size = le32_to_cpu(entries[i].ppt_size_bytes); 331e098bc96SEvan Quan break; 332e098bc96SEvan Quan } 333e098bc96SEvan Quan } 334e098bc96SEvan Quan 335e098bc96SEvan Quan if (i == pptable_count) 336e098bc96SEvan Quan return -EINVAL; 337e098bc96SEvan Quan 338e098bc96SEvan Quan return 0; 339e098bc96SEvan Quan } 340e098bc96SEvan Quan 341e098bc96SEvan Quan int smu_v11_0_setup_pptable(struct smu_context *smu) 342e098bc96SEvan Quan { 343e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 344e098bc96SEvan Quan const struct smc_firmware_header_v1_0 *hdr; 345e098bc96SEvan Quan int ret, index; 346e098bc96SEvan Quan uint32_t size = 0; 347e098bc96SEvan Quan uint16_t atom_table_size; 348e098bc96SEvan Quan uint8_t frev, crev; 349e098bc96SEvan Quan void *table; 350e098bc96SEvan Quan uint16_t version_major, version_minor; 351e098bc96SEvan Quan 3527c67d74dSJingwen Chen if (!amdgpu_sriov_vf(adev)) { 353e098bc96SEvan Quan hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; 354e098bc96SEvan Quan version_major = le16_to_cpu(hdr->header.header_version_major); 355e098bc96SEvan Quan version_minor = le16_to_cpu(hdr->header.header_version_minor); 356ac79f42aSChengming Gui if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) { 357e098bc96SEvan Quan dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id); 358e098bc96SEvan Quan switch (version_minor) { 359e098bc96SEvan Quan case 0: 360e098bc96SEvan Quan ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size); 361e098bc96SEvan Quan break; 362e098bc96SEvan Quan case 1: 363e098bc96SEvan Quan ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size, 364e098bc96SEvan Quan smu->smu_table.boot_values.pp_table_id); 365e098bc96SEvan Quan break; 366e098bc96SEvan Quan default: 367e098bc96SEvan Quan ret = -EINVAL; 368e098bc96SEvan Quan break; 369e098bc96SEvan Quan } 370e098bc96SEvan Quan if (ret) 371e098bc96SEvan Quan return ret; 3727c67d74dSJingwen Chen goto out; 3737c67d74dSJingwen Chen } 3747c67d74dSJingwen Chen } 375e098bc96SEvan Quan 376e098bc96SEvan Quan dev_info(adev->dev, "use vbios provided pptable\n"); 377e098bc96SEvan Quan index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 378e098bc96SEvan Quan powerplayinfo); 379e098bc96SEvan Quan 380e098bc96SEvan Quan ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev, 381e098bc96SEvan Quan (uint8_t **)&table); 382e098bc96SEvan Quan if (ret) 383e098bc96SEvan Quan return ret; 384e098bc96SEvan Quan size = atom_table_size; 385e098bc96SEvan Quan 3867c67d74dSJingwen Chen out: 387e098bc96SEvan Quan if (!smu->smu_table.power_play_table) 388e098bc96SEvan Quan smu->smu_table.power_play_table = table; 389e098bc96SEvan Quan if (!smu->smu_table.power_play_table_size) 390e098bc96SEvan Quan smu->smu_table.power_play_table_size = size; 391e098bc96SEvan Quan 392e098bc96SEvan Quan return 0; 393e098bc96SEvan Quan } 394e098bc96SEvan Quan 395e098bc96SEvan Quan int smu_v11_0_init_smc_tables(struct smu_context *smu) 396e098bc96SEvan Quan { 397e098bc96SEvan Quan struct smu_table_context *smu_table = &smu->smu_table; 398e098bc96SEvan Quan struct smu_table *tables = smu_table->tables; 399e098bc96SEvan Quan int ret = 0; 400e098bc96SEvan Quan 401e098bc96SEvan Quan smu_table->driver_pptable = 402e098bc96SEvan Quan kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL); 403e098bc96SEvan Quan if (!smu_table->driver_pptable) { 404e098bc96SEvan Quan ret = -ENOMEM; 405e098bc96SEvan Quan goto err0_out; 406e098bc96SEvan Quan } 407e098bc96SEvan Quan 408e098bc96SEvan Quan smu_table->max_sustainable_clocks = 409e098bc96SEvan Quan kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks), GFP_KERNEL); 410e098bc96SEvan Quan if (!smu_table->max_sustainable_clocks) { 411e098bc96SEvan Quan ret = -ENOMEM; 412e098bc96SEvan Quan goto err1_out; 413e098bc96SEvan Quan } 414e098bc96SEvan Quan 415e098bc96SEvan Quan /* Arcturus does not support OVERDRIVE */ 416e098bc96SEvan Quan if (tables[SMU_TABLE_OVERDRIVE].size) { 417e098bc96SEvan Quan smu_table->overdrive_table = 418e098bc96SEvan Quan kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); 419e098bc96SEvan Quan if (!smu_table->overdrive_table) { 420e098bc96SEvan Quan ret = -ENOMEM; 421e098bc96SEvan Quan goto err2_out; 422e098bc96SEvan Quan } 423e098bc96SEvan Quan 424e098bc96SEvan Quan smu_table->boot_overdrive_table = 425e098bc96SEvan Quan kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); 426e098bc96SEvan Quan if (!smu_table->boot_overdrive_table) { 427e098bc96SEvan Quan ret = -ENOMEM; 428e098bc96SEvan Quan goto err3_out; 429e098bc96SEvan Quan } 43092cf0508SEvan Quan 43192cf0508SEvan Quan smu_table->user_overdrive_table = 43292cf0508SEvan Quan kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); 43392cf0508SEvan Quan if (!smu_table->user_overdrive_table) { 43492cf0508SEvan Quan ret = -ENOMEM; 43592cf0508SEvan Quan goto err4_out; 43692cf0508SEvan Quan } 43792cf0508SEvan Quan 438e098bc96SEvan Quan } 439e098bc96SEvan Quan 440e098bc96SEvan Quan return 0; 441e098bc96SEvan Quan 44292cf0508SEvan Quan err4_out: 44392cf0508SEvan Quan kfree(smu_table->boot_overdrive_table); 444e098bc96SEvan Quan err3_out: 445e098bc96SEvan Quan kfree(smu_table->overdrive_table); 446e098bc96SEvan Quan err2_out: 447e098bc96SEvan Quan kfree(smu_table->max_sustainable_clocks); 448e098bc96SEvan Quan err1_out: 449e098bc96SEvan Quan kfree(smu_table->driver_pptable); 450e098bc96SEvan Quan err0_out: 451e098bc96SEvan Quan return ret; 452e098bc96SEvan Quan } 453e098bc96SEvan Quan 454e098bc96SEvan Quan int smu_v11_0_fini_smc_tables(struct smu_context *smu) 455e098bc96SEvan Quan { 456e098bc96SEvan Quan struct smu_table_context *smu_table = &smu->smu_table; 457e098bc96SEvan Quan struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 458e098bc96SEvan Quan 459e098bc96SEvan Quan kfree(smu_table->gpu_metrics_table); 46092cf0508SEvan Quan kfree(smu_table->user_overdrive_table); 461e098bc96SEvan Quan kfree(smu_table->boot_overdrive_table); 462e098bc96SEvan Quan kfree(smu_table->overdrive_table); 463e098bc96SEvan Quan kfree(smu_table->max_sustainable_clocks); 464e098bc96SEvan Quan kfree(smu_table->driver_pptable); 465c98ee897SXiaojian Du kfree(smu_table->clocks_table); 466e098bc96SEvan Quan smu_table->gpu_metrics_table = NULL; 46792cf0508SEvan Quan smu_table->user_overdrive_table = NULL; 468e098bc96SEvan Quan smu_table->boot_overdrive_table = NULL; 469e098bc96SEvan Quan smu_table->overdrive_table = NULL; 470e098bc96SEvan Quan smu_table->max_sustainable_clocks = NULL; 471e098bc96SEvan Quan smu_table->driver_pptable = NULL; 472c98ee897SXiaojian Du smu_table->clocks_table = NULL; 473e098bc96SEvan Quan kfree(smu_table->hardcode_pptable); 474e098bc96SEvan Quan smu_table->hardcode_pptable = NULL; 475e098bc96SEvan Quan 476816d61d5SEvan Quan kfree(smu_table->driver_smu_config_table); 4773ddd0c90Smziya kfree(smu_table->ecc_table); 478e098bc96SEvan Quan kfree(smu_table->metrics_table); 479e098bc96SEvan Quan kfree(smu_table->watermarks_table); 480816d61d5SEvan Quan smu_table->driver_smu_config_table = NULL; 4813ddd0c90Smziya smu_table->ecc_table = NULL; 482e098bc96SEvan Quan smu_table->metrics_table = NULL; 483e098bc96SEvan Quan smu_table->watermarks_table = NULL; 484e098bc96SEvan Quan smu_table->metrics_time = 0; 485e098bc96SEvan Quan 486e098bc96SEvan Quan kfree(smu_dpm->dpm_context); 487e098bc96SEvan Quan kfree(smu_dpm->golden_dpm_context); 488e098bc96SEvan Quan kfree(smu_dpm->dpm_current_power_state); 489e098bc96SEvan Quan kfree(smu_dpm->dpm_request_power_state); 490e098bc96SEvan Quan smu_dpm->dpm_context = NULL; 491e098bc96SEvan Quan smu_dpm->golden_dpm_context = NULL; 492e098bc96SEvan Quan smu_dpm->dpm_context_size = 0; 493e098bc96SEvan Quan smu_dpm->dpm_current_power_state = NULL; 494e098bc96SEvan Quan smu_dpm->dpm_request_power_state = NULL; 495e098bc96SEvan Quan 496e098bc96SEvan Quan return 0; 497e098bc96SEvan Quan } 498e098bc96SEvan Quan 499e098bc96SEvan Quan int smu_v11_0_init_power(struct smu_context *smu) 500e098bc96SEvan Quan { 501af3b89d3SAlex Deucher struct amdgpu_device *adev = smu->adev; 502e098bc96SEvan Quan struct smu_power_context *smu_power = &smu->smu_power; 5031d789535SAlex Deucher size_t size = adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0) ? 504ae07970aSXiaomeng Hou sizeof(struct smu_11_5_power_context) : 505ae07970aSXiaomeng Hou sizeof(struct smu_11_0_power_context); 506e098bc96SEvan Quan 507ae07970aSXiaomeng Hou smu_power->power_context = kzalloc(size, GFP_KERNEL); 508e098bc96SEvan Quan if (!smu_power->power_context) 509e098bc96SEvan Quan return -ENOMEM; 510ae07970aSXiaomeng Hou smu_power->power_context_size = size; 511e098bc96SEvan Quan 512e098bc96SEvan Quan return 0; 513e098bc96SEvan Quan } 514e098bc96SEvan Quan 515e098bc96SEvan Quan int smu_v11_0_fini_power(struct smu_context *smu) 516e098bc96SEvan Quan { 517e098bc96SEvan Quan struct smu_power_context *smu_power = &smu->smu_power; 518e098bc96SEvan Quan 519e098bc96SEvan Quan kfree(smu_power->power_context); 520e098bc96SEvan Quan smu_power->power_context = NULL; 521e098bc96SEvan Quan smu_power->power_context_size = 0; 522e098bc96SEvan Quan 523e098bc96SEvan Quan return 0; 524e098bc96SEvan Quan } 525e098bc96SEvan Quan 526e098bc96SEvan Quan static int smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device *adev, 527e098bc96SEvan Quan uint8_t clk_id, 528e098bc96SEvan Quan uint8_t syspll_id, 529e098bc96SEvan Quan uint32_t *clk_freq) 530e098bc96SEvan Quan { 531e098bc96SEvan Quan struct atom_get_smu_clock_info_parameters_v3_1 input = {0}; 532e098bc96SEvan Quan struct atom_get_smu_clock_info_output_parameters_v3_1 *output; 533e098bc96SEvan Quan int ret, index; 534e098bc96SEvan Quan 535e098bc96SEvan Quan input.clk_id = clk_id; 536e098bc96SEvan Quan input.syspll_id = syspll_id; 537e098bc96SEvan Quan input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ; 538e098bc96SEvan Quan index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1, 539e098bc96SEvan Quan getsmuclockinfo); 540e098bc96SEvan Quan 541e098bc96SEvan Quan ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index, 542e098bc96SEvan Quan (uint32_t *)&input); 543e098bc96SEvan Quan if (ret) 544e098bc96SEvan Quan return -EINVAL; 545e098bc96SEvan Quan 546e098bc96SEvan Quan output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input; 547e098bc96SEvan Quan *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000; 548e098bc96SEvan Quan 549e098bc96SEvan Quan return 0; 550e098bc96SEvan Quan } 551e098bc96SEvan Quan 552e098bc96SEvan Quan int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu) 553e098bc96SEvan Quan { 554e098bc96SEvan Quan int ret, index; 555e098bc96SEvan Quan uint16_t size; 556e098bc96SEvan Quan uint8_t frev, crev; 557e098bc96SEvan Quan struct atom_common_table_header *header; 558e098bc96SEvan Quan struct atom_firmware_info_v3_3 *v_3_3; 559e098bc96SEvan Quan struct atom_firmware_info_v3_1 *v_3_1; 560e098bc96SEvan Quan 561e098bc96SEvan Quan index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 562e098bc96SEvan Quan firmwareinfo); 563e098bc96SEvan Quan 564e098bc96SEvan Quan ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev, 565e098bc96SEvan Quan (uint8_t **)&header); 566e098bc96SEvan Quan if (ret) 567e098bc96SEvan Quan return ret; 568e098bc96SEvan Quan 569e098bc96SEvan Quan if (header->format_revision != 3) { 570e098bc96SEvan Quan dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu11\n"); 571e098bc96SEvan Quan return -EINVAL; 572e098bc96SEvan Quan } 573e098bc96SEvan Quan 574e098bc96SEvan Quan switch (header->content_revision) { 575e098bc96SEvan Quan case 0: 576e098bc96SEvan Quan case 1: 577e098bc96SEvan Quan case 2: 578e098bc96SEvan Quan v_3_1 = (struct atom_firmware_info_v3_1 *)header; 579e098bc96SEvan Quan smu->smu_table.boot_values.revision = v_3_1->firmware_revision; 580e098bc96SEvan Quan smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz; 581e098bc96SEvan Quan smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; 582e098bc96SEvan Quan smu->smu_table.boot_values.socclk = 0; 583e098bc96SEvan Quan smu->smu_table.boot_values.dcefclk = 0; 584e098bc96SEvan Quan smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv; 585e098bc96SEvan Quan smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv; 586e098bc96SEvan Quan smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv; 587e098bc96SEvan Quan smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv; 588e098bc96SEvan Quan smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id; 589e098bc96SEvan Quan smu->smu_table.boot_values.pp_table_id = 0; 590a7e660e5SEvan Quan smu->smu_table.boot_values.firmware_caps = v_3_1->firmware_capability; 591e098bc96SEvan Quan break; 592e098bc96SEvan Quan case 3: 5933495d3c3SXiaojian Du case 4: 594e098bc96SEvan Quan default: 595e098bc96SEvan Quan v_3_3 = (struct atom_firmware_info_v3_3 *)header; 596e098bc96SEvan Quan smu->smu_table.boot_values.revision = v_3_3->firmware_revision; 597e098bc96SEvan Quan smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz; 598e098bc96SEvan Quan smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; 599e098bc96SEvan Quan smu->smu_table.boot_values.socclk = 0; 600e098bc96SEvan Quan smu->smu_table.boot_values.dcefclk = 0; 601e098bc96SEvan Quan smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv; 602e098bc96SEvan Quan smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv; 603e098bc96SEvan Quan smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv; 604e098bc96SEvan Quan smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv; 605e098bc96SEvan Quan smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id; 606e098bc96SEvan Quan smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id; 607a7e660e5SEvan Quan smu->smu_table.boot_values.firmware_caps = v_3_3->firmware_capability; 608e098bc96SEvan Quan } 609e098bc96SEvan Quan 610e098bc96SEvan Quan smu->smu_table.boot_values.format_revision = header->format_revision; 611e098bc96SEvan Quan smu->smu_table.boot_values.content_revision = header->content_revision; 612e098bc96SEvan Quan 613e098bc96SEvan Quan smu_v11_0_atom_get_smu_clockinfo(smu->adev, 614e098bc96SEvan Quan (uint8_t)SMU11_SYSPLL0_SOCCLK_ID, 615e098bc96SEvan Quan (uint8_t)0, 616e098bc96SEvan Quan &smu->smu_table.boot_values.socclk); 617e098bc96SEvan Quan 618e098bc96SEvan Quan smu_v11_0_atom_get_smu_clockinfo(smu->adev, 619e098bc96SEvan Quan (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID, 620e098bc96SEvan Quan (uint8_t)0, 621e098bc96SEvan Quan &smu->smu_table.boot_values.dcefclk); 622e098bc96SEvan Quan 623e098bc96SEvan Quan smu_v11_0_atom_get_smu_clockinfo(smu->adev, 624e098bc96SEvan Quan (uint8_t)SMU11_SYSPLL0_ECLK_ID, 625e098bc96SEvan Quan (uint8_t)0, 626e098bc96SEvan Quan &smu->smu_table.boot_values.eclk); 627e098bc96SEvan Quan 628e098bc96SEvan Quan smu_v11_0_atom_get_smu_clockinfo(smu->adev, 629e098bc96SEvan Quan (uint8_t)SMU11_SYSPLL0_VCLK_ID, 630e098bc96SEvan Quan (uint8_t)0, 631e098bc96SEvan Quan &smu->smu_table.boot_values.vclk); 632e098bc96SEvan Quan 633e098bc96SEvan Quan smu_v11_0_atom_get_smu_clockinfo(smu->adev, 634e098bc96SEvan Quan (uint8_t)SMU11_SYSPLL0_DCLK_ID, 635e098bc96SEvan Quan (uint8_t)0, 636e098bc96SEvan Quan &smu->smu_table.boot_values.dclk); 637e098bc96SEvan Quan 638e098bc96SEvan Quan if ((smu->smu_table.boot_values.format_revision == 3) && 639e098bc96SEvan Quan (smu->smu_table.boot_values.content_revision >= 2)) 640e098bc96SEvan Quan smu_v11_0_atom_get_smu_clockinfo(smu->adev, 641e098bc96SEvan Quan (uint8_t)SMU11_SYSPLL1_0_FCLK_ID, 642e098bc96SEvan Quan (uint8_t)SMU11_SYSPLL1_2_ID, 643e098bc96SEvan Quan &smu->smu_table.boot_values.fclk); 644e098bc96SEvan Quan 6457d92c1fdSEvan Quan smu_v11_0_atom_get_smu_clockinfo(smu->adev, 6467d92c1fdSEvan Quan (uint8_t)SMU11_SYSPLL3_1_LCLK_ID, 6477d92c1fdSEvan Quan (uint8_t)SMU11_SYSPLL3_1_ID, 6487d92c1fdSEvan Quan &smu->smu_table.boot_values.lclk); 6497d92c1fdSEvan Quan 650e098bc96SEvan Quan return 0; 651e098bc96SEvan Quan } 652e098bc96SEvan Quan 653e098bc96SEvan Quan int smu_v11_0_notify_memory_pool_location(struct smu_context *smu) 654e098bc96SEvan Quan { 655e098bc96SEvan Quan struct smu_table_context *smu_table = &smu->smu_table; 656e098bc96SEvan Quan struct smu_table *memory_pool = &smu_table->memory_pool; 657e098bc96SEvan Quan int ret = 0; 658e098bc96SEvan Quan uint64_t address; 659e098bc96SEvan Quan uint32_t address_low, address_high; 660e098bc96SEvan Quan 661e098bc96SEvan Quan if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL) 662e098bc96SEvan Quan return ret; 663e098bc96SEvan Quan 664e098bc96SEvan Quan address = (uintptr_t)memory_pool->cpu_addr; 665e098bc96SEvan Quan address_high = (uint32_t)upper_32_bits(address); 666e098bc96SEvan Quan address_low = (uint32_t)lower_32_bits(address); 667e098bc96SEvan Quan 668e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, 669e098bc96SEvan Quan SMU_MSG_SetSystemVirtualDramAddrHigh, 670e098bc96SEvan Quan address_high, 671e098bc96SEvan Quan NULL); 672e098bc96SEvan Quan if (ret) 673e098bc96SEvan Quan return ret; 674e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, 675e098bc96SEvan Quan SMU_MSG_SetSystemVirtualDramAddrLow, 676e098bc96SEvan Quan address_low, 677e098bc96SEvan Quan NULL); 678e098bc96SEvan Quan if (ret) 679e098bc96SEvan Quan return ret; 680e098bc96SEvan Quan 681e098bc96SEvan Quan address = memory_pool->mc_address; 682e098bc96SEvan Quan address_high = (uint32_t)upper_32_bits(address); 683e098bc96SEvan Quan address_low = (uint32_t)lower_32_bits(address); 684e098bc96SEvan Quan 685e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh, 686e098bc96SEvan Quan address_high, NULL); 687e098bc96SEvan Quan if (ret) 688e098bc96SEvan Quan return ret; 689e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow, 690e098bc96SEvan Quan address_low, NULL); 691e098bc96SEvan Quan if (ret) 692e098bc96SEvan Quan return ret; 693e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize, 694e098bc96SEvan Quan (uint32_t)memory_pool->size, NULL); 695e098bc96SEvan Quan if (ret) 696e098bc96SEvan Quan return ret; 697e098bc96SEvan Quan 698e098bc96SEvan Quan return ret; 699e098bc96SEvan Quan } 700e098bc96SEvan Quan 701e098bc96SEvan Quan int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk) 702e098bc96SEvan Quan { 703e098bc96SEvan Quan int ret; 704e098bc96SEvan Quan 705e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, 706e098bc96SEvan Quan SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL); 707e098bc96SEvan Quan if (ret) 708e098bc96SEvan Quan dev_err(smu->adev->dev, "SMU11 attempt to set divider for DCEFCLK Failed!"); 709e098bc96SEvan Quan 710e098bc96SEvan Quan return ret; 711e098bc96SEvan Quan } 712e098bc96SEvan Quan 713e098bc96SEvan Quan int smu_v11_0_set_driver_table_location(struct smu_context *smu) 714e098bc96SEvan Quan { 715e098bc96SEvan Quan struct smu_table *driver_table = &smu->smu_table.driver_table; 716e098bc96SEvan Quan int ret = 0; 717e098bc96SEvan Quan 718e098bc96SEvan Quan if (driver_table->mc_address) { 719e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, 720e098bc96SEvan Quan SMU_MSG_SetDriverDramAddrHigh, 721e098bc96SEvan Quan upper_32_bits(driver_table->mc_address), 722e098bc96SEvan Quan NULL); 723e098bc96SEvan Quan if (!ret) 724e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, 725e098bc96SEvan Quan SMU_MSG_SetDriverDramAddrLow, 726e098bc96SEvan Quan lower_32_bits(driver_table->mc_address), 727e098bc96SEvan Quan NULL); 728e098bc96SEvan Quan } 729e098bc96SEvan Quan 730e098bc96SEvan Quan return ret; 731e098bc96SEvan Quan } 732e098bc96SEvan Quan 733e098bc96SEvan Quan int smu_v11_0_set_tool_table_location(struct smu_context *smu) 734e098bc96SEvan Quan { 735e098bc96SEvan Quan int ret = 0; 736e098bc96SEvan Quan struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG]; 737e098bc96SEvan Quan 738e098bc96SEvan Quan if (tool_table->mc_address) { 739e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, 740e098bc96SEvan Quan SMU_MSG_SetToolsDramAddrHigh, 741e098bc96SEvan Quan upper_32_bits(tool_table->mc_address), 742e098bc96SEvan Quan NULL); 743e098bc96SEvan Quan if (!ret) 744e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, 745e098bc96SEvan Quan SMU_MSG_SetToolsDramAddrLow, 746e098bc96SEvan Quan lower_32_bits(tool_table->mc_address), 747e098bc96SEvan Quan NULL); 748e098bc96SEvan Quan } 749e098bc96SEvan Quan 750e098bc96SEvan Quan return ret; 751e098bc96SEvan Quan } 752e098bc96SEvan Quan 753e098bc96SEvan Quan int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count) 754e098bc96SEvan Quan { 755e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 756e098bc96SEvan Quan 757db1f8a8fSTao Zhou /* Navy_Flounder/Dimgrey_Cavefish do not support to change 758db1f8a8fSTao Zhou * display num currently 759db1f8a8fSTao Zhou */ 7601d789535SAlex Deucher if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11) || 7611d789535SAlex Deucher adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0) || 7624df55857SAlex Deucher adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 12) || 7631d789535SAlex Deucher adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) 764e098bc96SEvan Quan return 0; 765e098bc96SEvan Quan 76638d11e02SEvan Quan return smu_cmn_send_smc_msg_with_param(smu, 76738d11e02SEvan Quan SMU_MSG_NumOfDisplays, 76838d11e02SEvan Quan count, 76938d11e02SEvan Quan NULL); 770e098bc96SEvan Quan } 771e098bc96SEvan Quan 772e098bc96SEvan Quan 773e098bc96SEvan Quan int smu_v11_0_set_allowed_mask(struct smu_context *smu) 774e098bc96SEvan Quan { 775e098bc96SEvan Quan struct smu_feature *feature = &smu->smu_feature; 776e098bc96SEvan Quan int ret = 0; 777e098bc96SEvan Quan uint32_t feature_mask[2]; 778e098bc96SEvan Quan 779692bd2a0SJia-Ju Bai if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64) { 780692bd2a0SJia-Ju Bai ret = -EINVAL; 781e098bc96SEvan Quan goto failed; 782692bd2a0SJia-Ju Bai } 783e098bc96SEvan Quan 784e098bc96SEvan Quan bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64); 785e098bc96SEvan Quan 786e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, 787e098bc96SEvan Quan feature_mask[1], NULL); 788e098bc96SEvan Quan if (ret) 789e098bc96SEvan Quan goto failed; 790e098bc96SEvan Quan 791e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow, 792e098bc96SEvan Quan feature_mask[0], NULL); 793e098bc96SEvan Quan if (ret) 794e098bc96SEvan Quan goto failed; 795e098bc96SEvan Quan 796e098bc96SEvan Quan failed: 797e098bc96SEvan Quan return ret; 798e098bc96SEvan Quan } 799e098bc96SEvan Quan 800e098bc96SEvan Quan int smu_v11_0_system_features_control(struct smu_context *smu, 801e098bc96SEvan Quan bool en) 802e098bc96SEvan Quan { 8033c6591e9SEvan Quan return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures : 804e098bc96SEvan Quan SMU_MSG_DisableAllSmuFeatures), NULL); 805e098bc96SEvan Quan } 806e098bc96SEvan Quan 807e098bc96SEvan Quan int smu_v11_0_notify_display_change(struct smu_context *smu) 808e098bc96SEvan Quan { 809e098bc96SEvan Quan int ret = 0; 810e098bc96SEvan Quan 811e098bc96SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && 812e098bc96SEvan Quan smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM) 813e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL); 814e098bc96SEvan Quan 815e098bc96SEvan Quan return ret; 816e098bc96SEvan Quan } 817e098bc96SEvan Quan 818e098bc96SEvan Quan static int 819e098bc96SEvan Quan smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock, 820e098bc96SEvan Quan enum smu_clk_type clock_select) 821e098bc96SEvan Quan { 822e098bc96SEvan Quan int ret = 0; 823e098bc96SEvan Quan int clk_id; 824e098bc96SEvan Quan 825e098bc96SEvan Quan if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) || 826e098bc96SEvan Quan (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0)) 827e098bc96SEvan Quan return 0; 828e098bc96SEvan Quan 829e098bc96SEvan Quan clk_id = smu_cmn_to_asic_specific_index(smu, 830e098bc96SEvan Quan CMN2ASIC_MAPPING_CLK, 831e098bc96SEvan Quan clock_select); 832e098bc96SEvan Quan if (clk_id < 0) 833e098bc96SEvan Quan return -EINVAL; 834e098bc96SEvan Quan 835e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq, 836e098bc96SEvan Quan clk_id << 16, clock); 837e098bc96SEvan Quan if (ret) { 838e098bc96SEvan Quan dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!"); 839e098bc96SEvan Quan return ret; 840e098bc96SEvan Quan } 841e098bc96SEvan Quan 842e098bc96SEvan Quan if (*clock != 0) 843e098bc96SEvan Quan return 0; 844e098bc96SEvan Quan 845e098bc96SEvan Quan /* if DC limit is zero, return AC limit */ 846e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, 847e098bc96SEvan Quan clk_id << 16, clock); 848e098bc96SEvan Quan if (ret) { 849e098bc96SEvan Quan dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!"); 850e098bc96SEvan Quan return ret; 851e098bc96SEvan Quan } 852e098bc96SEvan Quan 853e098bc96SEvan Quan return 0; 854e098bc96SEvan Quan } 855e098bc96SEvan Quan 856e098bc96SEvan Quan int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu) 857e098bc96SEvan Quan { 858e098bc96SEvan Quan struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks = 859e098bc96SEvan Quan smu->smu_table.max_sustainable_clocks; 860e098bc96SEvan Quan int ret = 0; 861e098bc96SEvan Quan 862e098bc96SEvan Quan max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100; 863e098bc96SEvan Quan max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100; 864e098bc96SEvan Quan max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100; 865e098bc96SEvan Quan max_sustainable_clocks->display_clock = 0xFFFFFFFF; 866e098bc96SEvan Quan max_sustainable_clocks->phy_clock = 0xFFFFFFFF; 867e098bc96SEvan Quan max_sustainable_clocks->pixel_clock = 0xFFFFFFFF; 868e098bc96SEvan Quan 869e098bc96SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 870e098bc96SEvan Quan ret = smu_v11_0_get_max_sustainable_clock(smu, 871e098bc96SEvan Quan &(max_sustainable_clocks->uclock), 872e098bc96SEvan Quan SMU_UCLK); 873e098bc96SEvan Quan if (ret) { 874e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!", 875e098bc96SEvan Quan __func__); 876e098bc96SEvan Quan return ret; 877e098bc96SEvan Quan } 878e098bc96SEvan Quan } 879e098bc96SEvan Quan 880e098bc96SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 881e098bc96SEvan Quan ret = smu_v11_0_get_max_sustainable_clock(smu, 882e098bc96SEvan Quan &(max_sustainable_clocks->soc_clock), 883e098bc96SEvan Quan SMU_SOCCLK); 884e098bc96SEvan Quan if (ret) { 885e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!", 886e098bc96SEvan Quan __func__); 887e098bc96SEvan Quan return ret; 888e098bc96SEvan Quan } 889e098bc96SEvan Quan } 890e098bc96SEvan Quan 891e098bc96SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 892e098bc96SEvan Quan ret = smu_v11_0_get_max_sustainable_clock(smu, 893e098bc96SEvan Quan &(max_sustainable_clocks->dcef_clock), 894e098bc96SEvan Quan SMU_DCEFCLK); 895e098bc96SEvan Quan if (ret) { 896e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!", 897e098bc96SEvan Quan __func__); 898e098bc96SEvan Quan return ret; 899e098bc96SEvan Quan } 900e098bc96SEvan Quan 901e098bc96SEvan Quan ret = smu_v11_0_get_max_sustainable_clock(smu, 902e098bc96SEvan Quan &(max_sustainable_clocks->display_clock), 903e098bc96SEvan Quan SMU_DISPCLK); 904e098bc96SEvan Quan if (ret) { 905e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!", 906e098bc96SEvan Quan __func__); 907e098bc96SEvan Quan return ret; 908e098bc96SEvan Quan } 909e098bc96SEvan Quan ret = smu_v11_0_get_max_sustainable_clock(smu, 910e098bc96SEvan Quan &(max_sustainable_clocks->phy_clock), 911e098bc96SEvan Quan SMU_PHYCLK); 912e098bc96SEvan Quan if (ret) { 913e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!", 914e098bc96SEvan Quan __func__); 915e098bc96SEvan Quan return ret; 916e098bc96SEvan Quan } 917e098bc96SEvan Quan ret = smu_v11_0_get_max_sustainable_clock(smu, 918e098bc96SEvan Quan &(max_sustainable_clocks->pixel_clock), 919e098bc96SEvan Quan SMU_PIXCLK); 920e098bc96SEvan Quan if (ret) { 921e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!", 922e098bc96SEvan Quan __func__); 923e098bc96SEvan Quan return ret; 924e098bc96SEvan Quan } 925e098bc96SEvan Quan } 926e098bc96SEvan Quan 927e098bc96SEvan Quan if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock) 928e098bc96SEvan Quan max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock; 929e098bc96SEvan Quan 930e098bc96SEvan Quan return 0; 931e098bc96SEvan Quan } 932e098bc96SEvan Quan 933e098bc96SEvan Quan int smu_v11_0_get_current_power_limit(struct smu_context *smu, 934e098bc96SEvan Quan uint32_t *power_limit) 935e098bc96SEvan Quan { 936e098bc96SEvan Quan int power_src; 937e098bc96SEvan Quan int ret = 0; 938e098bc96SEvan Quan 939e098bc96SEvan Quan if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) 940e098bc96SEvan Quan return -EINVAL; 941e098bc96SEvan Quan 942e098bc96SEvan Quan power_src = smu_cmn_to_asic_specific_index(smu, 943e098bc96SEvan Quan CMN2ASIC_MAPPING_PWR, 944e098bc96SEvan Quan smu->adev->pm.ac_power ? 945e098bc96SEvan Quan SMU_POWER_SOURCE_AC : 946e098bc96SEvan Quan SMU_POWER_SOURCE_DC); 947e098bc96SEvan Quan if (power_src < 0) 948e098bc96SEvan Quan return -EINVAL; 949e098bc96SEvan Quan 9500cb4c621SEvan Quan /* 9510cb4c621SEvan Quan * BIT 24-31: ControllerId (only PPT0 is supported for now) 9520cb4c621SEvan Quan * BIT 16-23: PowerSource 9530cb4c621SEvan Quan */ 954e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, 955e098bc96SEvan Quan SMU_MSG_GetPptLimit, 9560cb4c621SEvan Quan (0 << 24) | (power_src << 16), 957e098bc96SEvan Quan power_limit); 958e098bc96SEvan Quan if (ret) 959e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__); 960e098bc96SEvan Quan 961e098bc96SEvan Quan return ret; 962e098bc96SEvan Quan } 963e098bc96SEvan Quan 9642d1ac1cbSDarren Powell int smu_v11_0_set_power_limit(struct smu_context *smu, 9652d1ac1cbSDarren Powell enum smu_ppt_limit_type limit_type, 9662d1ac1cbSDarren Powell uint32_t limit) 967e098bc96SEvan Quan { 9680cb4c621SEvan Quan int power_src; 969e098bc96SEvan Quan int ret = 0; 97002f8aa9fSDarren Powell uint32_t limit_param; 971e098bc96SEvan Quan 9722d1ac1cbSDarren Powell if (limit_type != SMU_DEFAULT_PPT_LIMIT) 9732d1ac1cbSDarren Powell return -EINVAL; 9742d1ac1cbSDarren Powell 975e098bc96SEvan Quan if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { 976e098bc96SEvan Quan dev_err(smu->adev->dev, "Setting new power limit is not supported!\n"); 977e098bc96SEvan Quan return -EOPNOTSUPP; 978e098bc96SEvan Quan } 979e098bc96SEvan Quan 9800cb4c621SEvan Quan power_src = smu_cmn_to_asic_specific_index(smu, 9810cb4c621SEvan Quan CMN2ASIC_MAPPING_PWR, 9820cb4c621SEvan Quan smu->adev->pm.ac_power ? 9830cb4c621SEvan Quan SMU_POWER_SOURCE_AC : 9840cb4c621SEvan Quan SMU_POWER_SOURCE_DC); 9850cb4c621SEvan Quan if (power_src < 0) 9860cb4c621SEvan Quan return -EINVAL; 9870cb4c621SEvan Quan 9880cb4c621SEvan Quan /* 9890cb4c621SEvan Quan * BIT 24-31: ControllerId (only PPT0 is supported for now) 9900cb4c621SEvan Quan * BIT 16-23: PowerSource 9910cb4c621SEvan Quan * BIT 0-15: PowerLimit 9920cb4c621SEvan Quan */ 99302f8aa9fSDarren Powell limit_param = (limit & 0xFFFF); 99402f8aa9fSDarren Powell limit_param |= 0 << 24; 99502f8aa9fSDarren Powell limit_param |= (power_src) << 16; 99602f8aa9fSDarren Powell ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit_param, NULL); 997e098bc96SEvan Quan if (ret) { 998e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__); 999e098bc96SEvan Quan return ret; 1000e098bc96SEvan Quan } 1001e098bc96SEvan Quan 10022d1ac1cbSDarren Powell smu->current_power_limit = limit; 1003e098bc96SEvan Quan 1004e098bc96SEvan Quan return 0; 1005e098bc96SEvan Quan } 1006e098bc96SEvan Quan 100771f9404fSEvan Quan static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu) 100871f9404fSEvan Quan { 100971f9404fSEvan Quan return smu_cmn_send_smc_msg(smu, 101071f9404fSEvan Quan SMU_MSG_ReenableAcDcInterrupt, 101171f9404fSEvan Quan NULL); 101271f9404fSEvan Quan } 101371f9404fSEvan Quan 101471f9404fSEvan Quan static int smu_v11_0_process_pending_interrupt(struct smu_context *smu) 101571f9404fSEvan Quan { 101671f9404fSEvan Quan int ret = 0; 101771f9404fSEvan Quan 101871f9404fSEvan Quan if (smu->dc_controlled_by_gpio && 101971f9404fSEvan Quan smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT)) 102071f9404fSEvan Quan ret = smu_v11_0_ack_ac_dc_interrupt(smu); 102171f9404fSEvan Quan 102271f9404fSEvan Quan return ret; 102371f9404fSEvan Quan } 102471f9404fSEvan Quan 1025234676d6SAlex Deucher void smu_v11_0_interrupt_work(struct smu_context *smu) 1026234676d6SAlex Deucher { 1027234676d6SAlex Deucher if (smu_v11_0_ack_ac_dc_interrupt(smu)) 1028234676d6SAlex Deucher dev_err(smu->adev->dev, "Ack AC/DC interrupt Failed!\n"); 1029234676d6SAlex Deucher } 1030234676d6SAlex Deucher 1031e098bc96SEvan Quan int smu_v11_0_enable_thermal_alert(struct smu_context *smu) 1032e098bc96SEvan Quan { 103371f9404fSEvan Quan int ret = 0; 1034e098bc96SEvan Quan 103571f9404fSEvan Quan if (smu->smu_table.thermal_controller_type) { 103671f9404fSEvan Quan ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0); 103771f9404fSEvan Quan if (ret) 103871f9404fSEvan Quan return ret; 103971f9404fSEvan Quan } 104071f9404fSEvan Quan 104171f9404fSEvan Quan /* 104271f9404fSEvan Quan * After init there might have been missed interrupts triggered 104371f9404fSEvan Quan * before driver registers for interrupt (Ex. AC/DC). 104471f9404fSEvan Quan */ 104571f9404fSEvan Quan return smu_v11_0_process_pending_interrupt(smu); 1046e098bc96SEvan Quan } 1047e098bc96SEvan Quan 1048e098bc96SEvan Quan int smu_v11_0_disable_thermal_alert(struct smu_context *smu) 1049e098bc96SEvan Quan { 1050e098bc96SEvan Quan return amdgpu_irq_put(smu->adev, &smu->irq_source, 0); 1051e098bc96SEvan Quan } 1052e098bc96SEvan Quan 1053e098bc96SEvan Quan static uint16_t convert_to_vddc(uint8_t vid) 1054e098bc96SEvan Quan { 1055e098bc96SEvan Quan return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE); 1056e098bc96SEvan Quan } 1057e098bc96SEvan Quan 1058e098bc96SEvan Quan int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value) 1059e098bc96SEvan Quan { 1060e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 1061e098bc96SEvan Quan uint32_t vdd = 0, val_vid = 0; 1062e098bc96SEvan Quan 1063e098bc96SEvan Quan if (!value) 1064e098bc96SEvan Quan return -EINVAL; 1065e098bc96SEvan Quan val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) & 1066e098bc96SEvan Quan SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >> 1067e098bc96SEvan Quan SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT; 1068e098bc96SEvan Quan 1069e098bc96SEvan Quan vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid); 1070e098bc96SEvan Quan 1071e098bc96SEvan Quan *value = vdd; 1072e098bc96SEvan Quan 1073e098bc96SEvan Quan return 0; 1074e098bc96SEvan Quan 1075e098bc96SEvan Quan } 1076e098bc96SEvan Quan 1077e098bc96SEvan Quan int 1078e098bc96SEvan Quan smu_v11_0_display_clock_voltage_request(struct smu_context *smu, 1079e098bc96SEvan Quan struct pp_display_clock_request 1080e098bc96SEvan Quan *clock_req) 1081e098bc96SEvan Quan { 1082e098bc96SEvan Quan enum amd_pp_clock_type clk_type = clock_req->clock_type; 1083e098bc96SEvan Quan int ret = 0; 1084e098bc96SEvan Quan enum smu_clk_type clk_select = 0; 1085e098bc96SEvan Quan uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; 1086e098bc96SEvan Quan 1087e098bc96SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) || 1088e098bc96SEvan Quan smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1089e098bc96SEvan Quan switch (clk_type) { 1090e098bc96SEvan Quan case amd_pp_dcef_clock: 1091e098bc96SEvan Quan clk_select = SMU_DCEFCLK; 1092e098bc96SEvan Quan break; 1093e098bc96SEvan Quan case amd_pp_disp_clock: 1094e098bc96SEvan Quan clk_select = SMU_DISPCLK; 1095e098bc96SEvan Quan break; 1096e098bc96SEvan Quan case amd_pp_pixel_clock: 1097e098bc96SEvan Quan clk_select = SMU_PIXCLK; 1098e098bc96SEvan Quan break; 1099e098bc96SEvan Quan case amd_pp_phy_clock: 1100e098bc96SEvan Quan clk_select = SMU_PHYCLK; 1101e098bc96SEvan Quan break; 1102e098bc96SEvan Quan case amd_pp_mem_clock: 1103e098bc96SEvan Quan clk_select = SMU_UCLK; 1104e098bc96SEvan Quan break; 1105e098bc96SEvan Quan default: 1106e098bc96SEvan Quan dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__); 1107e098bc96SEvan Quan ret = -EINVAL; 1108e098bc96SEvan Quan break; 1109e098bc96SEvan Quan } 1110e098bc96SEvan Quan 1111e098bc96SEvan Quan if (ret) 1112e098bc96SEvan Quan goto failed; 1113e098bc96SEvan Quan 1114e098bc96SEvan Quan if (clk_select == SMU_UCLK && smu->disable_uclk_switch) 1115e098bc96SEvan Quan return 0; 1116e098bc96SEvan Quan 1117e098bc96SEvan Quan ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0); 1118e098bc96SEvan Quan 1119e098bc96SEvan Quan if(clk_select == SMU_UCLK) 1120e098bc96SEvan Quan smu->hard_min_uclk_req_from_dal = clk_freq; 1121e098bc96SEvan Quan } 1122e098bc96SEvan Quan 1123e098bc96SEvan Quan failed: 1124e098bc96SEvan Quan return ret; 1125e098bc96SEvan Quan } 1126e098bc96SEvan Quan 1127e098bc96SEvan Quan int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable) 1128e098bc96SEvan Quan { 1129e098bc96SEvan Quan int ret = 0; 1130e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 1131e098bc96SEvan Quan 11321d789535SAlex Deucher switch (adev->ip_versions[MP1_HWIP][0]) { 1133af3b89d3SAlex Deucher case IP_VERSION(11, 0, 0): 1134af3b89d3SAlex Deucher case IP_VERSION(11, 0, 5): 1135af3b89d3SAlex Deucher case IP_VERSION(11, 0, 9): 1136af3b89d3SAlex Deucher case IP_VERSION(11, 0, 7): 1137af3b89d3SAlex Deucher case IP_VERSION(11, 0, 11): 1138af3b89d3SAlex Deucher case IP_VERSION(11, 0, 12): 1139af3b89d3SAlex Deucher case IP_VERSION(11, 0, 13): 1140af3b89d3SAlex Deucher case IP_VERSION(11, 5, 0): 1141e098bc96SEvan Quan if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) 1142e098bc96SEvan Quan return 0; 1143e098bc96SEvan Quan if (enable) 1144e098bc96SEvan Quan ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL); 1145e098bc96SEvan Quan else 1146e098bc96SEvan Quan ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL); 1147e098bc96SEvan Quan break; 1148e098bc96SEvan Quan default: 1149e098bc96SEvan Quan break; 1150e098bc96SEvan Quan } 1151e098bc96SEvan Quan 1152e098bc96SEvan Quan return ret; 1153e098bc96SEvan Quan } 1154e098bc96SEvan Quan 1155e098bc96SEvan Quan uint32_t 1156e098bc96SEvan Quan smu_v11_0_get_fan_control_mode(struct smu_context *smu) 1157e098bc96SEvan Quan { 11584954a76aSAlex Deucher if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT)) 1159e098bc96SEvan Quan return AMD_FAN_CTRL_AUTO; 11604954a76aSAlex Deucher else 11614954a76aSAlex Deucher return smu->user_dpm_profile.fan_mode; 1162e098bc96SEvan Quan } 1163e098bc96SEvan Quan 1164e098bc96SEvan Quan static int 1165e098bc96SEvan Quan smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control) 1166e098bc96SEvan Quan { 1167e098bc96SEvan Quan int ret = 0; 1168e098bc96SEvan Quan 1169e098bc96SEvan Quan if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT)) 1170e098bc96SEvan Quan return 0; 1171e098bc96SEvan Quan 1172e098bc96SEvan Quan ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control); 1173e098bc96SEvan Quan if (ret) 1174e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!", 1175e098bc96SEvan Quan __func__, (auto_fan_control ? "Start" : "Stop")); 1176e098bc96SEvan Quan 1177e098bc96SEvan Quan return ret; 1178e098bc96SEvan Quan } 1179e098bc96SEvan Quan 1180e098bc96SEvan Quan static int 1181e098bc96SEvan Quan smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode) 1182e098bc96SEvan Quan { 1183e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 1184e098bc96SEvan Quan 1185e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, 1186e098bc96SEvan Quan REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 1187e098bc96SEvan Quan CG_FDO_CTRL2, TMIN, 0)); 1188e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, 1189e098bc96SEvan Quan REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 1190e098bc96SEvan Quan CG_FDO_CTRL2, FDO_PWM_MODE, mode)); 1191e098bc96SEvan Quan 1192e098bc96SEvan Quan return 0; 1193e098bc96SEvan Quan } 1194e098bc96SEvan Quan 1195e098bc96SEvan Quan int 11960d8318e1SEvan Quan smu_v11_0_set_fan_speed_pwm(struct smu_context *smu, uint32_t speed) 1197cd305137SAlex Deucher { 1198cd305137SAlex Deucher struct amdgpu_device *adev = smu->adev; 1199cd305137SAlex Deucher uint32_t duty100, duty; 1200cd305137SAlex Deucher uint64_t tmp64; 1201cd305137SAlex Deucher 12020d8318e1SEvan Quan speed = MIN(speed, 255); 1203cd305137SAlex Deucher 1204cd305137SAlex Deucher duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), 1205cd305137SAlex Deucher CG_FDO_CTRL1, FMAX_DUTY100); 1206cd305137SAlex Deucher if (!duty100) 1207cd305137SAlex Deucher return -EINVAL; 1208cd305137SAlex Deucher 1209cd305137SAlex Deucher tmp64 = (uint64_t)speed * duty100; 12100d8318e1SEvan Quan do_div(tmp64, 255); 1211cd305137SAlex Deucher duty = (uint32_t)tmp64; 1212cd305137SAlex Deucher 1213cd305137SAlex Deucher WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0, 1214cd305137SAlex Deucher REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), 1215cd305137SAlex Deucher CG_FDO_CTRL0, FDO_STATIC_DUTY, duty)); 1216cd305137SAlex Deucher 1217cd305137SAlex Deucher return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC); 1218cd305137SAlex Deucher } 1219cd305137SAlex Deucher 1220f3289d04SEvan Quan int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu, 1221f3289d04SEvan Quan uint32_t speed) 1222f3289d04SEvan Quan { 1223f3289d04SEvan Quan struct amdgpu_device *adev = smu->adev; 1224f3289d04SEvan Quan /* 1225f3289d04SEvan Quan * crystal_clock_freq used for fan speed rpm calculation is 1226f3289d04SEvan Quan * always 25Mhz. So, hardcode it as 2500(in 10K unit). 1227f3289d04SEvan Quan */ 1228f3289d04SEvan Quan uint32_t crystal_clock_freq = 2500; 1229f3289d04SEvan Quan uint32_t tach_period; 1230f3289d04SEvan Quan 1231*1e866f1fSYefim Barashkin if (speed == 0) 1232*1e866f1fSYefim Barashkin return -EINVAL; 1233f3289d04SEvan Quan /* 1234f3289d04SEvan Quan * To prevent from possible overheat, some ASICs may have requirement 1235f3289d04SEvan Quan * for minimum fan speed: 1236f3289d04SEvan Quan * - For some NV10 SKU, the fan speed cannot be set lower than 1237f3289d04SEvan Quan * 700 RPM. 1238f3289d04SEvan Quan * - For some Sienna Cichlid SKU, the fan speed cannot be set 1239f3289d04SEvan Quan * lower than 500 RPM. 1240f3289d04SEvan Quan */ 1241f3289d04SEvan Quan tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed); 1242f3289d04SEvan Quan WREG32_SOC15(THM, 0, mmCG_TACH_CTRL, 1243f3289d04SEvan Quan REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), 1244f3289d04SEvan Quan CG_TACH_CTRL, TARGET_PERIOD, 1245f3289d04SEvan Quan tach_period)); 1246f3289d04SEvan Quan 1247bc08cab6SEvan Quan return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM); 1248f3289d04SEvan Quan } 1249f3289d04SEvan Quan 12500d8318e1SEvan Quan int smu_v11_0_get_fan_speed_pwm(struct smu_context *smu, 1251fb1f667eSEvan Quan uint32_t *speed) 1252fb1f667eSEvan Quan { 1253fb1f667eSEvan Quan struct amdgpu_device *adev = smu->adev; 1254fb1f667eSEvan Quan uint32_t duty100, duty; 1255fb1f667eSEvan Quan uint64_t tmp64; 1256fb1f667eSEvan Quan 1257fb1f667eSEvan Quan /* 1258fb1f667eSEvan Quan * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly 1259fb1f667eSEvan Quan * detected via register retrieving. To workaround this, we will 1260fb1f667eSEvan Quan * report the fan speed as 0 PWM if user just requested such. 1261fb1f667eSEvan Quan */ 1262fb1f667eSEvan Quan if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_PWM) 12630d8318e1SEvan Quan && !smu->user_dpm_profile.fan_speed_pwm) { 1264fb1f667eSEvan Quan *speed = 0; 1265fb1f667eSEvan Quan return 0; 1266fb1f667eSEvan Quan } 1267fb1f667eSEvan Quan 1268fb1f667eSEvan Quan duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), 1269fb1f667eSEvan Quan CG_FDO_CTRL1, FMAX_DUTY100); 1270fb1f667eSEvan Quan duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS), 1271fb1f667eSEvan Quan CG_THERMAL_STATUS, FDO_PWM_DUTY); 1272fb1f667eSEvan Quan if (!duty100) 1273fb1f667eSEvan Quan return -EINVAL; 1274fb1f667eSEvan Quan 12750d8318e1SEvan Quan tmp64 = (uint64_t)duty * 255; 1276fb1f667eSEvan Quan do_div(tmp64, duty100); 12770d8318e1SEvan Quan *speed = MIN((uint32_t)tmp64, 255); 1278fb1f667eSEvan Quan 1279fb1f667eSEvan Quan return 0; 1280fb1f667eSEvan Quan } 1281fb1f667eSEvan Quan 1282d9ca7567SEvan Quan int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu, 1283d9ca7567SEvan Quan uint32_t *speed) 1284d9ca7567SEvan Quan { 1285d9ca7567SEvan Quan struct amdgpu_device *adev = smu->adev; 1286d9ca7567SEvan Quan uint32_t crystal_clock_freq = 2500; 1287d9ca7567SEvan Quan uint32_t tach_status; 1288d9ca7567SEvan Quan uint64_t tmp64; 1289d9ca7567SEvan Quan 1290d9ca7567SEvan Quan /* 1291d9ca7567SEvan Quan * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly 1292d9ca7567SEvan Quan * detected via register retrieving. To workaround this, we will 1293d9ca7567SEvan Quan * report the fan speed as 0 RPM if user just requested such. 1294d9ca7567SEvan Quan */ 1295d9ca7567SEvan Quan if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_RPM) 1296d9ca7567SEvan Quan && !smu->user_dpm_profile.fan_speed_rpm) { 1297d9ca7567SEvan Quan *speed = 0; 1298d9ca7567SEvan Quan return 0; 1299d9ca7567SEvan Quan } 1300d9ca7567SEvan Quan 1301d9ca7567SEvan Quan tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000; 1302d9ca7567SEvan Quan 1303d9ca7567SEvan Quan tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS); 13048ac1696bSEvan Quan if (tach_status) { 1305d9ca7567SEvan Quan do_div(tmp64, tach_status); 1306d9ca7567SEvan Quan *speed = (uint32_t)tmp64; 13078ac1696bSEvan Quan } else { 13088ac1696bSEvan Quan dev_warn_once(adev->dev, "Got zero output on CG_TACH_STATUS reading!\n"); 13098ac1696bSEvan Quan *speed = 0; 13108ac1696bSEvan Quan } 1311d9ca7567SEvan Quan 1312d9ca7567SEvan Quan return 0; 1313d9ca7567SEvan Quan } 1314d9ca7567SEvan Quan 1315cd305137SAlex Deucher int 1316e098bc96SEvan Quan smu_v11_0_set_fan_control_mode(struct smu_context *smu, 1317e098bc96SEvan Quan uint32_t mode) 1318e098bc96SEvan Quan { 1319e098bc96SEvan Quan int ret = 0; 1320e098bc96SEvan Quan 1321e098bc96SEvan Quan switch (mode) { 1322e098bc96SEvan Quan case AMD_FAN_CTRL_NONE: 1323bc08cab6SEvan Quan ret = smu_v11_0_auto_fan_control(smu, 0); 1324bc08cab6SEvan Quan if (!ret) 13250d8318e1SEvan Quan ret = smu_v11_0_set_fan_speed_pwm(smu, 255); 1326e098bc96SEvan Quan break; 1327e098bc96SEvan Quan case AMD_FAN_CTRL_MANUAL: 1328e098bc96SEvan Quan ret = smu_v11_0_auto_fan_control(smu, 0); 1329e098bc96SEvan Quan break; 1330e098bc96SEvan Quan case AMD_FAN_CTRL_AUTO: 1331e098bc96SEvan Quan ret = smu_v11_0_auto_fan_control(smu, 1); 1332e098bc96SEvan Quan break; 1333e098bc96SEvan Quan default: 1334e098bc96SEvan Quan break; 1335e098bc96SEvan Quan } 1336e098bc96SEvan Quan 1337e098bc96SEvan Quan if (ret) { 1338e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__); 1339e098bc96SEvan Quan return -EINVAL; 1340e098bc96SEvan Quan } 1341e098bc96SEvan Quan 1342e098bc96SEvan Quan return ret; 1343e098bc96SEvan Quan } 1344e098bc96SEvan Quan 1345e098bc96SEvan Quan int smu_v11_0_set_xgmi_pstate(struct smu_context *smu, 1346e098bc96SEvan Quan uint32_t pstate) 1347e098bc96SEvan Quan { 13486c20f157SEvan Quan return smu_cmn_send_smc_msg_with_param(smu, 1349e098bc96SEvan Quan SMU_MSG_SetXgmiMode, 1350e098bc96SEvan Quan pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3, 1351e098bc96SEvan Quan NULL); 1352e098bc96SEvan Quan } 1353e098bc96SEvan Quan 1354e098bc96SEvan Quan static int smu_v11_0_set_irq_state(struct amdgpu_device *adev, 1355e098bc96SEvan Quan struct amdgpu_irq_src *source, 1356e098bc96SEvan Quan unsigned tyep, 1357e098bc96SEvan Quan enum amdgpu_interrupt_state state) 1358e098bc96SEvan Quan { 1359ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle; 1360e098bc96SEvan Quan uint32_t low, high; 1361e098bc96SEvan Quan uint32_t val = 0; 1362e098bc96SEvan Quan 1363e098bc96SEvan Quan switch (state) { 1364e098bc96SEvan Quan case AMDGPU_IRQ_STATE_DISABLE: 1365e098bc96SEvan Quan /* For THM irqs */ 1366e098bc96SEvan Quan val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); 1367e098bc96SEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1); 1368e098bc96SEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1); 1369e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); 1370e098bc96SEvan Quan 1371e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0); 1372e098bc96SEvan Quan 1373e098bc96SEvan Quan /* For MP1 SW irqs */ 1374e098bc96SEvan Quan val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL); 1375e098bc96SEvan Quan val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1); 1376e098bc96SEvan Quan WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val); 1377e098bc96SEvan Quan 1378e098bc96SEvan Quan break; 1379e098bc96SEvan Quan case AMDGPU_IRQ_STATE_ENABLE: 1380e098bc96SEvan Quan /* For THM irqs */ 1381e098bc96SEvan Quan low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, 1382e098bc96SEvan Quan smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES); 1383e098bc96SEvan Quan high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, 1384e098bc96SEvan Quan smu->thermal_range.software_shutdown_temp); 1385e098bc96SEvan Quan 1386e098bc96SEvan Quan val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); 1387e098bc96SEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); 1388e098bc96SEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); 1389e098bc96SEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); 1390e098bc96SEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0); 1391e098bc96SEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff)); 1392e098bc96SEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff)); 1393e098bc96SEvan Quan val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); 1394e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); 1395e098bc96SEvan Quan 1396e098bc96SEvan Quan val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT); 1397e098bc96SEvan Quan val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT); 1398e098bc96SEvan Quan val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT); 1399e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val); 1400e098bc96SEvan Quan 1401e098bc96SEvan Quan /* For MP1 SW irqs */ 1402e098bc96SEvan Quan val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT); 1403e098bc96SEvan Quan val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE); 1404e098bc96SEvan Quan val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0); 1405e098bc96SEvan Quan WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val); 1406e098bc96SEvan Quan 1407e098bc96SEvan Quan val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL); 1408e098bc96SEvan Quan val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0); 1409e098bc96SEvan Quan WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val); 1410e098bc96SEvan Quan 1411e098bc96SEvan Quan break; 1412e098bc96SEvan Quan default: 1413e098bc96SEvan Quan break; 1414e098bc96SEvan Quan } 1415e098bc96SEvan Quan 1416e098bc96SEvan Quan return 0; 1417e098bc96SEvan Quan } 1418e098bc96SEvan Quan 1419e098bc96SEvan Quan #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */ 1420e098bc96SEvan Quan #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */ 1421e098bc96SEvan Quan 1422e098bc96SEvan Quan #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83 1423e098bc96SEvan Quan 1424e098bc96SEvan Quan static int smu_v11_0_irq_process(struct amdgpu_device *adev, 1425e098bc96SEvan Quan struct amdgpu_irq_src *source, 1426e098bc96SEvan Quan struct amdgpu_iv_entry *entry) 1427e098bc96SEvan Quan { 1428ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle; 1429e098bc96SEvan Quan uint32_t client_id = entry->client_id; 1430e098bc96SEvan Quan uint32_t src_id = entry->src_id; 1431e098bc96SEvan Quan /* 1432e098bc96SEvan Quan * ctxid is used to distinguish different 1433e098bc96SEvan Quan * events for SMCToHost interrupt. 1434e098bc96SEvan Quan */ 1435e098bc96SEvan Quan uint32_t ctxid = entry->src_data[0]; 1436e098bc96SEvan Quan uint32_t data; 1437e098bc96SEvan Quan 1438e098bc96SEvan Quan if (client_id == SOC15_IH_CLIENTID_THM) { 1439e098bc96SEvan Quan switch (src_id) { 1440e098bc96SEvan Quan case THM_11_0__SRCID__THM_DIG_THERM_L2H: 1441e098bc96SEvan Quan dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1442e098bc96SEvan Quan /* 1443e098bc96SEvan Quan * SW CTF just occurred. 1444e098bc96SEvan Quan * Try to do a graceful shutdown to prevent further damage. 1445e098bc96SEvan Quan */ 1446e098bc96SEvan Quan dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1447e098bc96SEvan Quan orderly_poweroff(true); 1448e098bc96SEvan Quan break; 1449e098bc96SEvan Quan case THM_11_0__SRCID__THM_DIG_THERM_H2L: 1450e098bc96SEvan Quan dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n"); 1451e098bc96SEvan Quan break; 1452e098bc96SEvan Quan default: 1453e098bc96SEvan Quan dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n", 1454e098bc96SEvan Quan src_id); 1455e098bc96SEvan Quan break; 1456e098bc96SEvan Quan } 1457e098bc96SEvan Quan } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) { 1458e098bc96SEvan Quan dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n"); 1459e098bc96SEvan Quan /* 1460e098bc96SEvan Quan * HW CTF just occurred. Shutdown to prevent further damage. 1461e098bc96SEvan Quan */ 1462e098bc96SEvan Quan dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n"); 1463e098bc96SEvan Quan orderly_poweroff(true); 1464e098bc96SEvan Quan } else if (client_id == SOC15_IH_CLIENTID_MP1) { 1465e098bc96SEvan Quan if (src_id == 0xfe) { 1466e098bc96SEvan Quan /* ACK SMUToHost interrupt */ 1467e098bc96SEvan Quan data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL); 1468e098bc96SEvan Quan data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1); 1469e098bc96SEvan Quan WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, data); 1470e098bc96SEvan Quan 1471e098bc96SEvan Quan switch (ctxid) { 1472e098bc96SEvan Quan case 0x3: 1473e098bc96SEvan Quan dev_dbg(adev->dev, "Switched to AC mode!\n"); 1474234676d6SAlex Deucher schedule_work(&smu->interrupt_work); 1475e098bc96SEvan Quan break; 1476e098bc96SEvan Quan case 0x4: 1477e098bc96SEvan Quan dev_dbg(adev->dev, "Switched to DC mode!\n"); 1478234676d6SAlex Deucher schedule_work(&smu->interrupt_work); 1479e098bc96SEvan Quan break; 1480e098bc96SEvan Quan case 0x7: 1481e098bc96SEvan Quan /* 1482e098bc96SEvan Quan * Increment the throttle interrupt counter 1483e098bc96SEvan Quan */ 1484e098bc96SEvan Quan atomic64_inc(&smu->throttle_int_counter); 1485e098bc96SEvan Quan 1486e098bc96SEvan Quan if (!atomic_read(&adev->throttling_logging_enabled)) 1487e098bc96SEvan Quan return 0; 1488e098bc96SEvan Quan 1489e098bc96SEvan Quan if (__ratelimit(&adev->throttling_logging_rs)) 1490e098bc96SEvan Quan schedule_work(&smu->throttling_logging_work); 1491e098bc96SEvan Quan 1492e098bc96SEvan Quan break; 1493e098bc96SEvan Quan } 1494e098bc96SEvan Quan } 1495e098bc96SEvan Quan } 1496e098bc96SEvan Quan 1497e098bc96SEvan Quan return 0; 1498e098bc96SEvan Quan } 1499e098bc96SEvan Quan 1500e098bc96SEvan Quan static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs = 1501e098bc96SEvan Quan { 1502e098bc96SEvan Quan .set = smu_v11_0_set_irq_state, 1503e098bc96SEvan Quan .process = smu_v11_0_irq_process, 1504e098bc96SEvan Quan }; 1505e098bc96SEvan Quan 1506e098bc96SEvan Quan int smu_v11_0_register_irq_handler(struct smu_context *smu) 1507e098bc96SEvan Quan { 1508e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 1509e098bc96SEvan Quan struct amdgpu_irq_src *irq_src = &smu->irq_source; 1510e098bc96SEvan Quan int ret = 0; 1511e098bc96SEvan Quan 1512e098bc96SEvan Quan irq_src->num_types = 1; 1513e098bc96SEvan Quan irq_src->funcs = &smu_v11_0_irq_funcs; 1514e098bc96SEvan Quan 1515e098bc96SEvan Quan ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, 1516e098bc96SEvan Quan THM_11_0__SRCID__THM_DIG_THERM_L2H, 1517e098bc96SEvan Quan irq_src); 1518e098bc96SEvan Quan if (ret) 1519e098bc96SEvan Quan return ret; 1520e098bc96SEvan Quan 1521e098bc96SEvan Quan ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, 1522e098bc96SEvan Quan THM_11_0__SRCID__THM_DIG_THERM_H2L, 1523e098bc96SEvan Quan irq_src); 1524e098bc96SEvan Quan if (ret) 1525e098bc96SEvan Quan return ret; 1526e098bc96SEvan Quan 1527e098bc96SEvan Quan /* Register CTF(GPIO_19) interrupt */ 1528e098bc96SEvan Quan ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO, 1529e098bc96SEvan Quan SMUIO_11_0__SRCID__SMUIO_GPIO19, 1530e098bc96SEvan Quan irq_src); 1531e098bc96SEvan Quan if (ret) 1532e098bc96SEvan Quan return ret; 1533e098bc96SEvan Quan 1534e098bc96SEvan Quan ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1, 1535e098bc96SEvan Quan 0xfe, 1536e098bc96SEvan Quan irq_src); 1537e098bc96SEvan Quan if (ret) 1538e098bc96SEvan Quan return ret; 1539e098bc96SEvan Quan 1540e098bc96SEvan Quan return ret; 1541e098bc96SEvan Quan } 1542e098bc96SEvan Quan 1543e098bc96SEvan Quan int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu, 1544e098bc96SEvan Quan struct pp_smu_nv_clock_table *max_clocks) 1545e098bc96SEvan Quan { 1546e098bc96SEvan Quan struct smu_table_context *table_context = &smu->smu_table; 1547e098bc96SEvan Quan struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL; 1548e098bc96SEvan Quan 1549e098bc96SEvan Quan if (!max_clocks || !table_context->max_sustainable_clocks) 1550e098bc96SEvan Quan return -EINVAL; 1551e098bc96SEvan Quan 1552e098bc96SEvan Quan sustainable_clocks = table_context->max_sustainable_clocks; 1553e098bc96SEvan Quan 1554e098bc96SEvan Quan max_clocks->dcfClockInKhz = 1555e098bc96SEvan Quan (unsigned int) sustainable_clocks->dcef_clock * 1000; 1556e098bc96SEvan Quan max_clocks->displayClockInKhz = 1557e098bc96SEvan Quan (unsigned int) sustainable_clocks->display_clock * 1000; 1558e098bc96SEvan Quan max_clocks->phyClockInKhz = 1559e098bc96SEvan Quan (unsigned int) sustainable_clocks->phy_clock * 1000; 1560e098bc96SEvan Quan max_clocks->pixelClockInKhz = 1561e098bc96SEvan Quan (unsigned int) sustainable_clocks->pixel_clock * 1000; 1562e098bc96SEvan Quan max_clocks->uClockInKhz = 1563e098bc96SEvan Quan (unsigned int) sustainable_clocks->uclock * 1000; 1564e098bc96SEvan Quan max_clocks->socClockInKhz = 1565e098bc96SEvan Quan (unsigned int) sustainable_clocks->soc_clock * 1000; 1566e098bc96SEvan Quan max_clocks->dscClockInKhz = 0; 1567e098bc96SEvan Quan max_clocks->dppClockInKhz = 0; 1568e098bc96SEvan Quan max_clocks->fabricClockInKhz = 0; 1569e098bc96SEvan Quan 1570e098bc96SEvan Quan return 0; 1571e098bc96SEvan Quan } 1572e098bc96SEvan Quan 1573e098bc96SEvan Quan int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu) 1574e098bc96SEvan Quan { 15756c20f157SEvan Quan return smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL); 1576e098bc96SEvan Quan } 1577e098bc96SEvan Quan 157813d75eadSEvan Quan int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, 157913d75eadSEvan Quan enum smu_v11_0_baco_seq baco_seq) 1580e098bc96SEvan Quan { 1581e098bc96SEvan Quan return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL); 1582e098bc96SEvan Quan } 1583e098bc96SEvan Quan 1584e098bc96SEvan Quan bool smu_v11_0_baco_is_support(struct smu_context *smu) 1585e098bc96SEvan Quan { 1586e098bc96SEvan Quan struct smu_baco_context *smu_baco = &smu->smu_baco; 1587e098bc96SEvan Quan 158852a9fd7bSLijo Lazar if (amdgpu_sriov_vf(smu->adev) || !smu_baco->platform_support) 1589e098bc96SEvan Quan return false; 1590e098bc96SEvan Quan 1591e098bc96SEvan Quan /* Arcturus does not support this bit mask */ 1592e098bc96SEvan Quan if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) && 1593e098bc96SEvan Quan !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) 1594e098bc96SEvan Quan return false; 1595e098bc96SEvan Quan 1596e098bc96SEvan Quan return true; 1597e098bc96SEvan Quan } 1598e098bc96SEvan Quan 1599e098bc96SEvan Quan enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu) 1600e098bc96SEvan Quan { 1601e098bc96SEvan Quan struct smu_baco_context *smu_baco = &smu->smu_baco; 1602e098bc96SEvan Quan 16031c4dba5eSEvan Quan return smu_baco->state; 1604e098bc96SEvan Quan } 1605e098bc96SEvan Quan 16062261229cSLikun Gao #define D3HOT_BACO_SEQUENCE 0 16072261229cSLikun Gao #define D3HOT_BAMACO_SEQUENCE 2 16082261229cSLikun Gao 1609e098bc96SEvan Quan int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state) 1610e098bc96SEvan Quan { 1611e098bc96SEvan Quan struct smu_baco_context *smu_baco = &smu->smu_baco; 1612e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 1613e098bc96SEvan Quan struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1614e098bc96SEvan Quan uint32_t data; 1615e098bc96SEvan Quan int ret = 0; 1616e098bc96SEvan Quan 1617e098bc96SEvan Quan if (smu_v11_0_baco_get_state(smu) == state) 1618e098bc96SEvan Quan return 0; 1619e098bc96SEvan Quan 1620e098bc96SEvan Quan if (state == SMU_BACO_STATE_ENTER) { 16211d789535SAlex Deucher switch (adev->ip_versions[MP1_HWIP][0]) { 1622af3b89d3SAlex Deucher case IP_VERSION(11, 0, 7): 1623af3b89d3SAlex Deucher case IP_VERSION(11, 0, 11): 1624af3b89d3SAlex Deucher case IP_VERSION(11, 0, 12): 1625af3b89d3SAlex Deucher case IP_VERSION(11, 0, 13): 16262261229cSLikun Gao if (amdgpu_runtime_pm == 2) 16272261229cSLikun Gao ret = smu_cmn_send_smc_msg_with_param(smu, 16282261229cSLikun Gao SMU_MSG_EnterBaco, 16292261229cSLikun Gao D3HOT_BAMACO_SEQUENCE, 16302261229cSLikun Gao NULL); 16312261229cSLikun Gao else 16322261229cSLikun Gao ret = smu_cmn_send_smc_msg_with_param(smu, 16332261229cSLikun Gao SMU_MSG_EnterBaco, 16342261229cSLikun Gao D3HOT_BACO_SEQUENCE, 16352261229cSLikun Gao NULL); 16362261229cSLikun Gao break; 16372261229cSLikun Gao default: 16388ab0d6f0SLuben Tuikov if (!ras || !adev->ras_enabled || 1639acdae216SLuben Tuikov adev->gmc.xgmi.pending_reset) { 16401d789535SAlex Deucher if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 2)) { 1641e9995d4aSEvan Quan data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT); 1642e9995d4aSEvan Quan data |= 0x80000000; 1643e9995d4aSEvan Quan WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT, data); 1644e9995d4aSEvan Quan } else { 1645e098bc96SEvan Quan data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL); 1646e098bc96SEvan Quan data |= 0x80000000; 1647e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data); 1648e9995d4aSEvan Quan } 1649e098bc96SEvan Quan 1650e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL); 1651e098bc96SEvan Quan } else { 1652e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1, NULL); 1653e098bc96SEvan Quan } 16542261229cSLikun Gao break; 16552261229cSLikun Gao } 16562261229cSLikun Gao 1657e098bc96SEvan Quan } else { 1658e098bc96SEvan Quan ret = smu_cmn_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL); 1659e098bc96SEvan Quan if (ret) 16601c4dba5eSEvan Quan return ret; 1661e098bc96SEvan Quan 1662e098bc96SEvan Quan /* clear vbios scratch 6 and 7 for coming asic reinit */ 1663e098bc96SEvan Quan WREG32(adev->bios_scratch_reg_offset + 6, 0); 1664e098bc96SEvan Quan WREG32(adev->bios_scratch_reg_offset + 7, 0); 1665e098bc96SEvan Quan } 1666e098bc96SEvan Quan 16671c4dba5eSEvan Quan if (!ret) 1668e098bc96SEvan Quan smu_baco->state = state; 16691c4dba5eSEvan Quan 1670e098bc96SEvan Quan return ret; 1671e098bc96SEvan Quan } 1672e098bc96SEvan Quan 1673e098bc96SEvan Quan int smu_v11_0_baco_enter(struct smu_context *smu) 1674e098bc96SEvan Quan { 1675e098bc96SEvan Quan int ret = 0; 1676e098bc96SEvan Quan 1677e098bc96SEvan Quan ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER); 1678e098bc96SEvan Quan if (ret) 1679e098bc96SEvan Quan return ret; 1680e098bc96SEvan Quan 1681e098bc96SEvan Quan msleep(10); 1682e098bc96SEvan Quan 1683e098bc96SEvan Quan return ret; 1684e098bc96SEvan Quan } 1685e098bc96SEvan Quan 1686e098bc96SEvan Quan int smu_v11_0_baco_exit(struct smu_context *smu) 1687e098bc96SEvan Quan { 16886c20f157SEvan Quan return smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT); 1689e098bc96SEvan Quan } 1690e098bc96SEvan Quan 1691e098bc96SEvan Quan int smu_v11_0_mode1_reset(struct smu_context *smu) 1692e098bc96SEvan Quan { 1693e098bc96SEvan Quan int ret = 0; 1694e098bc96SEvan Quan 1695e098bc96SEvan Quan ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL); 1696e098bc96SEvan Quan if (!ret) 1697e098bc96SEvan Quan msleep(SMU11_MODE1_RESET_WAIT_TIME_IN_MS); 1698e098bc96SEvan Quan 1699e098bc96SEvan Quan return ret; 1700e098bc96SEvan Quan } 1701e098bc96SEvan Quan 17024da8b639Ssashank saye int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable) 17030e921596Sshaoyunl { 17040e921596Sshaoyunl int ret = 0; 17050e921596Sshaoyunl 17060e921596Sshaoyunl ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LightSBR, enable ? 1 : 0, NULL); 17070e921596Sshaoyunl 17080e921596Sshaoyunl return ret; 17090e921596Sshaoyunl } 17100e921596Sshaoyunl 17110e921596Sshaoyunl 1712e098bc96SEvan Quan int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 1713e098bc96SEvan Quan uint32_t *min, uint32_t *max) 1714e098bc96SEvan Quan { 1715e098bc96SEvan Quan int ret = 0, clk_id = 0; 1716e098bc96SEvan Quan uint32_t param = 0; 1717e098bc96SEvan Quan uint32_t clock_limit; 1718e098bc96SEvan Quan 1719e098bc96SEvan Quan if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { 1720e098bc96SEvan Quan switch (clk_type) { 1721e098bc96SEvan Quan case SMU_MCLK: 1722e098bc96SEvan Quan case SMU_UCLK: 1723e098bc96SEvan Quan clock_limit = smu->smu_table.boot_values.uclk; 1724e098bc96SEvan Quan break; 1725e098bc96SEvan Quan case SMU_GFXCLK: 1726e098bc96SEvan Quan case SMU_SCLK: 1727e098bc96SEvan Quan clock_limit = smu->smu_table.boot_values.gfxclk; 1728e098bc96SEvan Quan break; 1729e098bc96SEvan Quan case SMU_SOCCLK: 1730e098bc96SEvan Quan clock_limit = smu->smu_table.boot_values.socclk; 1731e098bc96SEvan Quan break; 1732e098bc96SEvan Quan default: 1733e098bc96SEvan Quan clock_limit = 0; 1734e098bc96SEvan Quan break; 1735e098bc96SEvan Quan } 1736e098bc96SEvan Quan 1737e098bc96SEvan Quan /* clock in Mhz unit */ 1738e098bc96SEvan Quan if (min) 1739e098bc96SEvan Quan *min = clock_limit / 100; 1740e098bc96SEvan Quan if (max) 1741e098bc96SEvan Quan *max = clock_limit / 100; 1742e098bc96SEvan Quan 1743e098bc96SEvan Quan return 0; 1744e098bc96SEvan Quan } 1745e098bc96SEvan Quan 1746e098bc96SEvan Quan clk_id = smu_cmn_to_asic_specific_index(smu, 1747e098bc96SEvan Quan CMN2ASIC_MAPPING_CLK, 1748e098bc96SEvan Quan clk_type); 1749e098bc96SEvan Quan if (clk_id < 0) { 1750e098bc96SEvan Quan ret = -EINVAL; 1751e098bc96SEvan Quan goto failed; 1752e098bc96SEvan Quan } 1753e098bc96SEvan Quan param = (clk_id & 0xffff) << 16; 1754e098bc96SEvan Quan 1755e098bc96SEvan Quan if (max) { 1756e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max); 1757e098bc96SEvan Quan if (ret) 1758e098bc96SEvan Quan goto failed; 1759e098bc96SEvan Quan } 1760e098bc96SEvan Quan 1761e098bc96SEvan Quan if (min) { 1762e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min); 1763e098bc96SEvan Quan if (ret) 1764e098bc96SEvan Quan goto failed; 1765e098bc96SEvan Quan } 1766e098bc96SEvan Quan 1767e098bc96SEvan Quan failed: 1768e098bc96SEvan Quan return ret; 1769e098bc96SEvan Quan } 1770e098bc96SEvan Quan 1771e098bc96SEvan Quan int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, 1772e098bc96SEvan Quan enum smu_clk_type clk_type, 1773e098bc96SEvan Quan uint32_t min, 1774e098bc96SEvan Quan uint32_t max) 1775e098bc96SEvan Quan { 1776e098bc96SEvan Quan int ret = 0, clk_id = 0; 1777e098bc96SEvan Quan uint32_t param; 1778e098bc96SEvan Quan 1779e098bc96SEvan Quan if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1780e098bc96SEvan Quan return 0; 1781e098bc96SEvan Quan 1782e098bc96SEvan Quan clk_id = smu_cmn_to_asic_specific_index(smu, 1783e098bc96SEvan Quan CMN2ASIC_MAPPING_CLK, 1784e098bc96SEvan Quan clk_type); 1785e098bc96SEvan Quan if (clk_id < 0) 1786e098bc96SEvan Quan return clk_id; 1787e098bc96SEvan Quan 1788e098bc96SEvan Quan if (max > 0) { 1789e098bc96SEvan Quan param = (uint32_t)((clk_id << 16) | (max & 0xffff)); 1790e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq, 1791e098bc96SEvan Quan param, NULL); 1792e098bc96SEvan Quan if (ret) 1793e098bc96SEvan Quan goto out; 1794e098bc96SEvan Quan } 1795e098bc96SEvan Quan 1796e098bc96SEvan Quan if (min > 0) { 1797e098bc96SEvan Quan param = (uint32_t)((clk_id << 16) | (min & 0xffff)); 1798e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq, 1799e098bc96SEvan Quan param, NULL); 1800e098bc96SEvan Quan if (ret) 1801e098bc96SEvan Quan goto out; 1802e098bc96SEvan Quan } 1803e098bc96SEvan Quan 1804e098bc96SEvan Quan out: 1805e098bc96SEvan Quan return ret; 1806e098bc96SEvan Quan } 1807e098bc96SEvan Quan 1808e098bc96SEvan Quan int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu, 1809e098bc96SEvan Quan enum smu_clk_type clk_type, 1810e098bc96SEvan Quan uint32_t min, 1811e098bc96SEvan Quan uint32_t max) 1812e098bc96SEvan Quan { 1813e098bc96SEvan Quan int ret = 0, clk_id = 0; 1814e098bc96SEvan Quan uint32_t param; 1815e098bc96SEvan Quan 1816e098bc96SEvan Quan if (min <= 0 && max <= 0) 1817e098bc96SEvan Quan return -EINVAL; 1818e098bc96SEvan Quan 1819e098bc96SEvan Quan if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1820e098bc96SEvan Quan return 0; 1821e098bc96SEvan Quan 1822e098bc96SEvan Quan clk_id = smu_cmn_to_asic_specific_index(smu, 1823e098bc96SEvan Quan CMN2ASIC_MAPPING_CLK, 1824e098bc96SEvan Quan clk_type); 1825e098bc96SEvan Quan if (clk_id < 0) 1826e098bc96SEvan Quan return clk_id; 1827e098bc96SEvan Quan 1828e098bc96SEvan Quan if (max > 0) { 1829e098bc96SEvan Quan param = (uint32_t)((clk_id << 16) | (max & 0xffff)); 1830e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq, 1831e098bc96SEvan Quan param, NULL); 1832e098bc96SEvan Quan if (ret) 1833e098bc96SEvan Quan return ret; 1834e098bc96SEvan Quan } 1835e098bc96SEvan Quan 1836e098bc96SEvan Quan if (min > 0) { 1837e098bc96SEvan Quan param = (uint32_t)((clk_id << 16) | (min & 0xffff)); 1838e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq, 1839e098bc96SEvan Quan param, NULL); 1840e098bc96SEvan Quan if (ret) 1841e098bc96SEvan Quan return ret; 1842e098bc96SEvan Quan } 1843e098bc96SEvan Quan 1844e098bc96SEvan Quan return ret; 1845e098bc96SEvan Quan } 1846e098bc96SEvan Quan 1847e098bc96SEvan Quan int smu_v11_0_set_performance_level(struct smu_context *smu, 1848e098bc96SEvan Quan enum amd_dpm_forced_level level) 1849e098bc96SEvan Quan { 1850e098bc96SEvan Quan struct smu_11_0_dpm_context *dpm_context = 1851e098bc96SEvan Quan smu->smu_dpm.dpm_context; 1852e098bc96SEvan Quan struct smu_11_0_dpm_table *gfx_table = 1853e098bc96SEvan Quan &dpm_context->dpm_tables.gfx_table; 1854e098bc96SEvan Quan struct smu_11_0_dpm_table *mem_table = 1855e098bc96SEvan Quan &dpm_context->dpm_tables.uclk_table; 1856e098bc96SEvan Quan struct smu_11_0_dpm_table *soc_table = 1857e098bc96SEvan Quan &dpm_context->dpm_tables.soc_table; 1858e098bc96SEvan Quan struct smu_umd_pstate_table *pstate_table = 1859e098bc96SEvan Quan &smu->pstate_table; 1860e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 1861e098bc96SEvan Quan uint32_t sclk_min = 0, sclk_max = 0; 1862e098bc96SEvan Quan uint32_t mclk_min = 0, mclk_max = 0; 1863e098bc96SEvan Quan uint32_t socclk_min = 0, socclk_max = 0; 1864e098bc96SEvan Quan int ret = 0; 1865e098bc96SEvan Quan 1866e098bc96SEvan Quan switch (level) { 1867e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_HIGH: 1868e098bc96SEvan Quan sclk_min = sclk_max = gfx_table->max; 1869e098bc96SEvan Quan mclk_min = mclk_max = mem_table->max; 1870e098bc96SEvan Quan socclk_min = socclk_max = soc_table->max; 1871e098bc96SEvan Quan break; 1872e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_LOW: 1873e098bc96SEvan Quan sclk_min = sclk_max = gfx_table->min; 1874e098bc96SEvan Quan mclk_min = mclk_max = mem_table->min; 1875e098bc96SEvan Quan socclk_min = socclk_max = soc_table->min; 1876e098bc96SEvan Quan break; 1877e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_AUTO: 1878e098bc96SEvan Quan sclk_min = gfx_table->min; 1879e098bc96SEvan Quan sclk_max = gfx_table->max; 1880e098bc96SEvan Quan mclk_min = mem_table->min; 1881e098bc96SEvan Quan mclk_max = mem_table->max; 1882e098bc96SEvan Quan socclk_min = soc_table->min; 1883e098bc96SEvan Quan socclk_max = soc_table->max; 1884e098bc96SEvan Quan break; 1885e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1886e098bc96SEvan Quan sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard; 1887e098bc96SEvan Quan mclk_min = mclk_max = pstate_table->uclk_pstate.standard; 1888e098bc96SEvan Quan socclk_min = socclk_max = pstate_table->socclk_pstate.standard; 1889e098bc96SEvan Quan break; 1890e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1891e098bc96SEvan Quan sclk_min = sclk_max = pstate_table->gfxclk_pstate.min; 1892e098bc96SEvan Quan break; 1893e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1894e098bc96SEvan Quan mclk_min = mclk_max = pstate_table->uclk_pstate.min; 1895e098bc96SEvan Quan break; 1896e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1897e098bc96SEvan Quan sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak; 1898e098bc96SEvan Quan mclk_min = mclk_max = pstate_table->uclk_pstate.peak; 1899e098bc96SEvan Quan socclk_min = socclk_max = pstate_table->socclk_pstate.peak; 1900e098bc96SEvan Quan break; 1901e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_MANUAL: 1902e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1903e098bc96SEvan Quan return 0; 1904e098bc96SEvan Quan default: 1905e098bc96SEvan Quan dev_err(adev->dev, "Invalid performance level %d\n", level); 1906e098bc96SEvan Quan return -EINVAL; 1907e098bc96SEvan Quan } 1908e098bc96SEvan Quan 1909e098bc96SEvan Quan /* 1910e098bc96SEvan Quan * Separate MCLK and SOCCLK soft min/max settings are not allowed 1911e098bc96SEvan Quan * on Arcturus. 1912e098bc96SEvan Quan */ 19131d789535SAlex Deucher if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 2)) { 1914e098bc96SEvan Quan mclk_min = mclk_max = 0; 1915e098bc96SEvan Quan socclk_min = socclk_max = 0; 1916e098bc96SEvan Quan } 1917e098bc96SEvan Quan 1918e098bc96SEvan Quan if (sclk_min && sclk_max) { 1919e098bc96SEvan Quan ret = smu_v11_0_set_soft_freq_limited_range(smu, 1920e098bc96SEvan Quan SMU_GFXCLK, 1921e098bc96SEvan Quan sclk_min, 1922e098bc96SEvan Quan sclk_max); 1923e098bc96SEvan Quan if (ret) 1924e098bc96SEvan Quan return ret; 1925e098bc96SEvan Quan } 1926e098bc96SEvan Quan 1927e098bc96SEvan Quan if (mclk_min && mclk_max) { 1928e098bc96SEvan Quan ret = smu_v11_0_set_soft_freq_limited_range(smu, 1929e098bc96SEvan Quan SMU_MCLK, 1930e098bc96SEvan Quan mclk_min, 1931e098bc96SEvan Quan mclk_max); 1932e098bc96SEvan Quan if (ret) 1933e098bc96SEvan Quan return ret; 1934e098bc96SEvan Quan } 1935e098bc96SEvan Quan 1936e098bc96SEvan Quan if (socclk_min && socclk_max) { 1937e098bc96SEvan Quan ret = smu_v11_0_set_soft_freq_limited_range(smu, 1938e098bc96SEvan Quan SMU_SOCCLK, 1939e098bc96SEvan Quan socclk_min, 1940e098bc96SEvan Quan socclk_max); 1941e098bc96SEvan Quan if (ret) 1942e098bc96SEvan Quan return ret; 1943e098bc96SEvan Quan } 1944e098bc96SEvan Quan 1945e098bc96SEvan Quan return ret; 1946e098bc96SEvan Quan } 1947e098bc96SEvan Quan 1948e098bc96SEvan Quan int smu_v11_0_set_power_source(struct smu_context *smu, 1949e098bc96SEvan Quan enum smu_power_src_type power_src) 1950e098bc96SEvan Quan { 1951e098bc96SEvan Quan int pwr_source; 1952e098bc96SEvan Quan 1953e098bc96SEvan Quan pwr_source = smu_cmn_to_asic_specific_index(smu, 1954e098bc96SEvan Quan CMN2ASIC_MAPPING_PWR, 1955e098bc96SEvan Quan (uint32_t)power_src); 1956e098bc96SEvan Quan if (pwr_source < 0) 1957e098bc96SEvan Quan return -EINVAL; 1958e098bc96SEvan Quan 1959e098bc96SEvan Quan return smu_cmn_send_smc_msg_with_param(smu, 1960e098bc96SEvan Quan SMU_MSG_NotifyPowerSource, 1961e098bc96SEvan Quan pwr_source, 1962e098bc96SEvan Quan NULL); 1963e098bc96SEvan Quan } 1964e098bc96SEvan Quan 1965e098bc96SEvan Quan int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu, 1966e098bc96SEvan Quan enum smu_clk_type clk_type, 1967e098bc96SEvan Quan uint16_t level, 1968e098bc96SEvan Quan uint32_t *value) 1969e098bc96SEvan Quan { 1970e098bc96SEvan Quan int ret = 0, clk_id = 0; 1971e098bc96SEvan Quan uint32_t param; 1972e098bc96SEvan Quan 1973e098bc96SEvan Quan if (!value) 1974e098bc96SEvan Quan return -EINVAL; 1975e098bc96SEvan Quan 1976e098bc96SEvan Quan if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) 1977e098bc96SEvan Quan return 0; 1978e098bc96SEvan Quan 1979e098bc96SEvan Quan clk_id = smu_cmn_to_asic_specific_index(smu, 1980e098bc96SEvan Quan CMN2ASIC_MAPPING_CLK, 1981e098bc96SEvan Quan clk_type); 1982e098bc96SEvan Quan if (clk_id < 0) 1983e098bc96SEvan Quan return clk_id; 1984e098bc96SEvan Quan 1985e098bc96SEvan Quan param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff)); 1986e098bc96SEvan Quan 1987e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, 1988e098bc96SEvan Quan SMU_MSG_GetDpmFreqByIndex, 1989e098bc96SEvan Quan param, 1990e098bc96SEvan Quan value); 1991e098bc96SEvan Quan if (ret) 1992e098bc96SEvan Quan return ret; 1993e098bc96SEvan Quan 1994e098bc96SEvan Quan /* 1995e098bc96SEvan Quan * BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM 1996e098bc96SEvan Quan * now, we un-support it 1997e098bc96SEvan Quan */ 1998e098bc96SEvan Quan *value = *value & 0x7fffffff; 1999e098bc96SEvan Quan 2000e098bc96SEvan Quan return ret; 2001e098bc96SEvan Quan } 2002e098bc96SEvan Quan 2003e098bc96SEvan Quan int smu_v11_0_get_dpm_level_count(struct smu_context *smu, 2004e098bc96SEvan Quan enum smu_clk_type clk_type, 2005e098bc96SEvan Quan uint32_t *value) 2006e098bc96SEvan Quan { 2007e098bc96SEvan Quan return smu_v11_0_get_dpm_freq_by_index(smu, 2008e098bc96SEvan Quan clk_type, 2009e098bc96SEvan Quan 0xff, 2010e098bc96SEvan Quan value); 2011e098bc96SEvan Quan } 2012e098bc96SEvan Quan 2013e098bc96SEvan Quan int smu_v11_0_set_single_dpm_table(struct smu_context *smu, 2014e098bc96SEvan Quan enum smu_clk_type clk_type, 2015e098bc96SEvan Quan struct smu_11_0_dpm_table *single_dpm_table) 2016e098bc96SEvan Quan { 2017e098bc96SEvan Quan int ret = 0; 2018e098bc96SEvan Quan uint32_t clk; 2019e098bc96SEvan Quan int i; 2020e098bc96SEvan Quan 2021e098bc96SEvan Quan ret = smu_v11_0_get_dpm_level_count(smu, 2022e098bc96SEvan Quan clk_type, 2023e098bc96SEvan Quan &single_dpm_table->count); 2024e098bc96SEvan Quan if (ret) { 2025e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__); 2026e098bc96SEvan Quan return ret; 2027e098bc96SEvan Quan } 2028e098bc96SEvan Quan 2029e098bc96SEvan Quan for (i = 0; i < single_dpm_table->count; i++) { 2030e098bc96SEvan Quan ret = smu_v11_0_get_dpm_freq_by_index(smu, 2031e098bc96SEvan Quan clk_type, 2032e098bc96SEvan Quan i, 2033e098bc96SEvan Quan &clk); 2034e098bc96SEvan Quan if (ret) { 2035e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__); 2036e098bc96SEvan Quan return ret; 2037e098bc96SEvan Quan } 2038e098bc96SEvan Quan 2039e098bc96SEvan Quan single_dpm_table->dpm_levels[i].value = clk; 2040e098bc96SEvan Quan single_dpm_table->dpm_levels[i].enabled = true; 2041e098bc96SEvan Quan 2042e098bc96SEvan Quan if (i == 0) 2043e098bc96SEvan Quan single_dpm_table->min = clk; 2044e098bc96SEvan Quan else if (i == single_dpm_table->count - 1) 2045e098bc96SEvan Quan single_dpm_table->max = clk; 2046e098bc96SEvan Quan } 2047e098bc96SEvan Quan 2048e098bc96SEvan Quan return 0; 2049e098bc96SEvan Quan } 2050e098bc96SEvan Quan 2051e098bc96SEvan Quan int smu_v11_0_get_dpm_level_range(struct smu_context *smu, 2052e098bc96SEvan Quan enum smu_clk_type clk_type, 2053e098bc96SEvan Quan uint32_t *min_value, 2054e098bc96SEvan Quan uint32_t *max_value) 2055e098bc96SEvan Quan { 2056e098bc96SEvan Quan uint32_t level_count = 0; 2057e098bc96SEvan Quan int ret = 0; 2058e098bc96SEvan Quan 2059e098bc96SEvan Quan if (!min_value && !max_value) 2060e098bc96SEvan Quan return -EINVAL; 2061e098bc96SEvan Quan 2062e098bc96SEvan Quan if (min_value) { 2063e098bc96SEvan Quan /* by default, level 0 clock value as min value */ 2064e098bc96SEvan Quan ret = smu_v11_0_get_dpm_freq_by_index(smu, 2065e098bc96SEvan Quan clk_type, 2066e098bc96SEvan Quan 0, 2067e098bc96SEvan Quan min_value); 2068e098bc96SEvan Quan if (ret) 2069e098bc96SEvan Quan return ret; 2070e098bc96SEvan Quan } 2071e098bc96SEvan Quan 2072e098bc96SEvan Quan if (max_value) { 2073e098bc96SEvan Quan ret = smu_v11_0_get_dpm_level_count(smu, 2074e098bc96SEvan Quan clk_type, 2075e098bc96SEvan Quan &level_count); 2076e098bc96SEvan Quan if (ret) 2077e098bc96SEvan Quan return ret; 2078e098bc96SEvan Quan 2079e098bc96SEvan Quan ret = smu_v11_0_get_dpm_freq_by_index(smu, 2080e098bc96SEvan Quan clk_type, 2081e098bc96SEvan Quan level_count - 1, 2082e098bc96SEvan Quan max_value); 2083e098bc96SEvan Quan if (ret) 2084e098bc96SEvan Quan return ret; 2085e098bc96SEvan Quan } 2086e098bc96SEvan Quan 2087e098bc96SEvan Quan return ret; 2088e098bc96SEvan Quan } 2089e098bc96SEvan Quan 2090e098bc96SEvan Quan int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu) 2091e098bc96SEvan Quan { 2092e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 2093e098bc96SEvan Quan 2094e098bc96SEvan Quan return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & 2095e098bc96SEvan Quan PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) 2096e098bc96SEvan Quan >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; 2097e098bc96SEvan Quan } 2098e098bc96SEvan Quan 2099152bb95cSEvan Quan uint16_t smu_v11_0_get_current_pcie_link_width(struct smu_context *smu) 2100e098bc96SEvan Quan { 2101e098bc96SEvan Quan uint32_t width_level; 2102e098bc96SEvan Quan 2103e098bc96SEvan Quan width_level = smu_v11_0_get_current_pcie_link_width_level(smu); 2104e098bc96SEvan Quan if (width_level > LINK_WIDTH_MAX) 2105e098bc96SEvan Quan width_level = 0; 2106e098bc96SEvan Quan 2107e098bc96SEvan Quan return link_width[width_level]; 2108e098bc96SEvan Quan } 2109e098bc96SEvan Quan 2110e098bc96SEvan Quan int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu) 2111e098bc96SEvan Quan { 2112e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev; 2113e098bc96SEvan Quan 2114e098bc96SEvan Quan return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & 2115e098bc96SEvan Quan PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) 2116e098bc96SEvan Quan >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 2117e098bc96SEvan Quan } 2118e098bc96SEvan Quan 2119152bb95cSEvan Quan uint16_t smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu) 2120e098bc96SEvan Quan { 2121e098bc96SEvan Quan uint32_t speed_level; 2122e098bc96SEvan Quan 2123e098bc96SEvan Quan speed_level = smu_v11_0_get_current_pcie_link_speed_level(smu); 2124e098bc96SEvan Quan if (speed_level > LINK_SPEED_MAX) 2125e098bc96SEvan Quan speed_level = 0; 2126e098bc96SEvan Quan 2127e098bc96SEvan Quan return link_speed[speed_level]; 2128e098bc96SEvan Quan } 2129e098bc96SEvan Quan 2130e988026fSEvan Quan int smu_v11_0_gfx_ulv_control(struct smu_context *smu, 2131e988026fSEvan Quan bool enablement) 2132e988026fSEvan Quan { 2133e988026fSEvan Quan int ret = 0; 2134e988026fSEvan Quan 2135e988026fSEvan Quan if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT)) 2136e988026fSEvan Quan ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement); 2137e988026fSEvan Quan 2138e988026fSEvan Quan return ret; 2139e988026fSEvan Quan } 21405ce99853SEvan Quan 21415ce99853SEvan Quan int smu_v11_0_deep_sleep_control(struct smu_context *smu, 21425ce99853SEvan Quan bool enablement) 21435ce99853SEvan Quan { 21445ce99853SEvan Quan struct amdgpu_device *adev = smu->adev; 21455ce99853SEvan Quan int ret = 0; 21465ce99853SEvan Quan 21475ce99853SEvan Quan if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) { 21485ce99853SEvan Quan ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement); 21495ce99853SEvan Quan if (ret) { 21505ce99853SEvan Quan dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable"); 21515ce99853SEvan Quan return ret; 21525ce99853SEvan Quan } 21535ce99853SEvan Quan } 21545ce99853SEvan Quan 215578d907e2SEvan Quan if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) { 215678d907e2SEvan Quan ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement); 215778d907e2SEvan Quan if (ret) { 215878d907e2SEvan Quan dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable"); 215978d907e2SEvan Quan return ret; 216078d907e2SEvan Quan } 216178d907e2SEvan Quan } 216278d907e2SEvan Quan 216378d907e2SEvan Quan if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) { 216478d907e2SEvan Quan ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement); 216578d907e2SEvan Quan if (ret) { 216678d907e2SEvan Quan dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable"); 216778d907e2SEvan Quan return ret; 216878d907e2SEvan Quan } 216978d907e2SEvan Quan } 217078d907e2SEvan Quan 21715ce99853SEvan Quan if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) { 21725ce99853SEvan Quan ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement); 21735ce99853SEvan Quan if (ret) { 21745ce99853SEvan Quan dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable"); 21755ce99853SEvan Quan return ret; 21765ce99853SEvan Quan } 21775ce99853SEvan Quan } 21785ce99853SEvan Quan 21795ce99853SEvan Quan if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) { 21805ce99853SEvan Quan ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement); 21815ce99853SEvan Quan if (ret) { 21825ce99853SEvan Quan dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable"); 21835ce99853SEvan Quan return ret; 21845ce99853SEvan Quan } 21855ce99853SEvan Quan } 21865ce99853SEvan Quan 21875ce99853SEvan Quan return ret; 21885ce99853SEvan Quan } 218992cf0508SEvan Quan 219092cf0508SEvan Quan int smu_v11_0_restore_user_od_settings(struct smu_context *smu) 219192cf0508SEvan Quan { 219292cf0508SEvan Quan struct smu_table_context *table_context = &smu->smu_table; 219392cf0508SEvan Quan void *user_od_table = table_context->user_overdrive_table; 219492cf0508SEvan Quan int ret = 0; 219592cf0508SEvan Quan 219692cf0508SEvan Quan ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)user_od_table, true); 219792cf0508SEvan Quan if (ret) 219892cf0508SEvan Quan dev_err(smu->adev->dev, "Failed to import overdrive table!\n"); 219992cf0508SEvan Quan 220092cf0508SEvan Quan return ret; 220192cf0508SEvan Quan } 2202da1db031SAlex Deucher 2203da1db031SAlex Deucher void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu) 2204da1db031SAlex Deucher { 2205da1db031SAlex Deucher struct amdgpu_device *adev = smu->adev; 2206da1db031SAlex Deucher 2207da1db031SAlex Deucher smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); 2208da1db031SAlex Deucher smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); 2209da1db031SAlex Deucher smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); 2210da1db031SAlex Deucher } 2211