1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include <linux/pci.h> 28 #include <linux/i2c.h> 29 #include "amdgpu.h" 30 #include "amdgpu_dpm.h" 31 #include "amdgpu_smu.h" 32 #include "atomfirmware.h" 33 #include "amdgpu_atomfirmware.h" 34 #include "amdgpu_atombios.h" 35 #include "smu_v11_0.h" 36 #include "smu11_driver_if_sienna_cichlid.h" 37 #include "soc15_common.h" 38 #include "atom.h" 39 #include "sienna_cichlid_ppt.h" 40 #include "smu_v11_0_7_pptable.h" 41 #include "smu_v11_0_7_ppsmc.h" 42 #include "nbio/nbio_2_3_offset.h" 43 #include "nbio/nbio_2_3_sh_mask.h" 44 #include "thm/thm_11_0_2_offset.h" 45 #include "thm/thm_11_0_2_sh_mask.h" 46 #include "mp/mp_11_0_offset.h" 47 #include "mp/mp_11_0_sh_mask.h" 48 49 #include "asic_reg/mp/mp_11_0_sh_mask.h" 50 #include "amdgpu_ras.h" 51 #include "smu_cmn.h" 52 53 /* 54 * DO NOT use these for err/warn/info/debug messages. 55 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 56 * They are more MGPU friendly. 57 */ 58 #undef pr_err 59 #undef pr_warn 60 #undef pr_info 61 #undef pr_debug 62 63 #define FEATURE_MASK(feature) (1ULL << feature) 64 #define SMC_DPM_FEATURE ( \ 65 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \ 66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \ 72 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)) 73 74 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15 75 76 #define GET_PPTABLE_MEMBER(field, member) do {\ 77 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))\ 78 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\ 79 else\ 80 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\ 81 } while(0) 82 83 /* STB FIFO depth is in 64bit units */ 84 #define SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES 8 85 86 /* 87 * SMU support ECCTABLE since version 58.70.0, 88 * use this to check whether ECCTABLE feature is supported. 89 */ 90 #define SUPPORT_ECCTABLE_SMU_VERSION 0x003a4600 91 92 static int get_table_size(struct smu_context *smu) 93 { 94 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) 95 return sizeof(PPTable_beige_goby_t); 96 else 97 return sizeof(PPTable_t); 98 } 99 100 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = { 101 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 102 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 103 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 104 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0), 105 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), 106 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 107 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 108 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1), 109 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1), 110 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1), 111 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1), 112 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1), 113 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1), 114 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 115 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 116 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 117 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 118 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 119 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 120 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 121 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 122 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 123 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 124 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), 125 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1), 126 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), 127 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1), 128 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 129 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), 130 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), 131 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 132 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0), 133 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0), 134 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0), 135 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0), 136 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0), 137 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0), 138 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0), 139 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0), 140 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1), 141 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 142 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 143 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 144 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1), 145 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0), 146 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 147 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 148 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 149 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 150 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0), 151 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0), 152 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0), 153 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0), 154 MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0), 155 MSG_MAP(DisallowGpo, PPSMC_MSG_DisallowGpo, 0), 156 MSG_MAP(Enable2ndUSB20Port, PPSMC_MSG_Enable2ndUSB20Port, 0), 157 }; 158 159 static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = { 160 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 161 CLK_MAP(SCLK, PPCLK_GFXCLK), 162 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 163 CLK_MAP(FCLK, PPCLK_FCLK), 164 CLK_MAP(UCLK, PPCLK_UCLK), 165 CLK_MAP(MCLK, PPCLK_UCLK), 166 CLK_MAP(DCLK, PPCLK_DCLK_0), 167 CLK_MAP(DCLK1, PPCLK_DCLK_1), 168 CLK_MAP(VCLK, PPCLK_VCLK_0), 169 CLK_MAP(VCLK1, PPCLK_VCLK_1), 170 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK), 171 CLK_MAP(DISPCLK, PPCLK_DISPCLK), 172 CLK_MAP(PIXCLK, PPCLK_PIXCLK), 173 CLK_MAP(PHYCLK, PPCLK_PHYCLK), 174 }; 175 176 static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = { 177 FEA_MAP(DPM_PREFETCHER), 178 FEA_MAP(DPM_GFXCLK), 179 FEA_MAP(DPM_GFX_GPO), 180 FEA_MAP(DPM_UCLK), 181 FEA_MAP(DPM_FCLK), 182 FEA_MAP(DPM_SOCCLK), 183 FEA_MAP(DPM_MP0CLK), 184 FEA_MAP(DPM_LINK), 185 FEA_MAP(DPM_DCEFCLK), 186 FEA_MAP(DPM_XGMI), 187 FEA_MAP(MEM_VDDCI_SCALING), 188 FEA_MAP(MEM_MVDD_SCALING), 189 FEA_MAP(DS_GFXCLK), 190 FEA_MAP(DS_SOCCLK), 191 FEA_MAP(DS_FCLK), 192 FEA_MAP(DS_LCLK), 193 FEA_MAP(DS_DCEFCLK), 194 FEA_MAP(DS_UCLK), 195 FEA_MAP(GFX_ULV), 196 FEA_MAP(FW_DSTATE), 197 FEA_MAP(GFXOFF), 198 FEA_MAP(BACO), 199 FEA_MAP(MM_DPM_PG), 200 FEA_MAP(RSMU_SMN_CG), 201 FEA_MAP(PPT), 202 FEA_MAP(TDC), 203 FEA_MAP(APCC_PLUS), 204 FEA_MAP(GTHR), 205 FEA_MAP(ACDC), 206 FEA_MAP(VR0HOT), 207 FEA_MAP(VR1HOT), 208 FEA_MAP(FW_CTF), 209 FEA_MAP(FAN_CONTROL), 210 FEA_MAP(THERMAL), 211 FEA_MAP(GFX_DCS), 212 FEA_MAP(RM), 213 FEA_MAP(LED_DISPLAY), 214 FEA_MAP(GFX_SS), 215 FEA_MAP(OUT_OF_BAND_MONITOR), 216 FEA_MAP(TEMP_DEPENDENT_VMIN), 217 FEA_MAP(MMHUB_PG), 218 FEA_MAP(ATHUB_PG), 219 FEA_MAP(APCC_DFLL), 220 }; 221 222 static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = { 223 TAB_MAP(PPTABLE), 224 TAB_MAP(WATERMARKS), 225 TAB_MAP(AVFS_PSM_DEBUG), 226 TAB_MAP(AVFS_FUSE_OVERRIDE), 227 TAB_MAP(PMSTATUSLOG), 228 TAB_MAP(SMU_METRICS), 229 TAB_MAP(DRIVER_SMU_CONFIG), 230 TAB_MAP(ACTIVITY_MONITOR_COEFF), 231 TAB_MAP(OVERDRIVE), 232 TAB_MAP(I2C_COMMANDS), 233 TAB_MAP(PACE), 234 TAB_MAP(ECCINFO), 235 }; 236 237 static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { 238 PWR_MAP(AC), 239 PWR_MAP(DC), 240 }; 241 242 static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 243 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), 244 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 245 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 246 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 247 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 248 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 249 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 250 }; 251 252 static const uint8_t sienna_cichlid_throttler_map[] = { 253 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT), 254 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT), 255 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 256 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 257 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 258 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT), 259 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 260 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT), 261 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT), 262 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 263 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 264 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 265 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 266 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT), 267 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT), 268 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), 269 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT), 270 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT), 271 }; 272 273 static int 274 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, 275 uint32_t *feature_mask, uint32_t num) 276 { 277 struct amdgpu_device *adev = smu->adev; 278 279 if (num > 2) 280 return -EINVAL; 281 282 memset(feature_mask, 0, sizeof(uint32_t) * num); 283 284 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) 285 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT) 286 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) 287 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) 288 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) 289 | FEATURE_MASK(FEATURE_DS_FCLK_BIT) 290 | FEATURE_MASK(FEATURE_DS_UCLK_BIT) 291 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) 292 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT) 293 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) 294 | FEATURE_MASK(FEATURE_GFX_SS_BIT) 295 | FEATURE_MASK(FEATURE_VR0HOT_BIT) 296 | FEATURE_MASK(FEATURE_PPT_BIT) 297 | FEATURE_MASK(FEATURE_TDC_BIT) 298 | FEATURE_MASK(FEATURE_BACO_BIT) 299 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) 300 | FEATURE_MASK(FEATURE_FW_CTF_BIT) 301 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) 302 | FEATURE_MASK(FEATURE_THERMAL_BIT) 303 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT); 304 305 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { 306 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 307 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT); 308 } 309 310 if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) && 311 (adev->ip_versions[MP1_HWIP][0] > IP_VERSION(11, 0, 7)) && 312 !(adev->flags & AMD_IS_APU)) 313 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT); 314 315 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) 316 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) 317 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) 318 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); 319 320 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) 321 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); 322 323 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) 324 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); 325 326 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) 327 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 328 329 if (adev->pm.pp_feature & PP_ULV_MASK) 330 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); 331 332 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) 333 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 334 335 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 336 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); 337 338 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB) 339 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT); 340 341 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) 342 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); 343 344 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN || 345 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG) 346 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT); 347 348 if (smu->dc_controlled_by_gpio) 349 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT); 350 351 if (amdgpu_device_should_use_aspm(adev)) 352 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT); 353 354 return 0; 355 } 356 357 static void sienna_cichlid_check_bxco_support(struct smu_context *smu) 358 { 359 struct smu_table_context *table_context = &smu->smu_table; 360 struct smu_11_0_7_powerplay_table *powerplay_table = 361 table_context->power_play_table; 362 struct smu_baco_context *smu_baco = &smu->smu_baco; 363 struct amdgpu_device *adev = smu->adev; 364 uint32_t val; 365 366 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) { 367 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); 368 smu_baco->platform_support = 369 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : 370 false; 371 } 372 } 373 374 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu) 375 { 376 struct smu_table_context *table_context = &smu->smu_table; 377 struct smu_11_0_7_powerplay_table *powerplay_table = 378 table_context->power_play_table; 379 380 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC) 381 smu->dc_controlled_by_gpio = true; 382 383 sienna_cichlid_check_bxco_support(smu); 384 385 table_context->thermal_controller_type = 386 powerplay_table->thermal_controller_type; 387 388 /* 389 * Instead of having its own buffer space and get overdrive_table copied, 390 * smu->od_settings just points to the actual overdrive_table 391 */ 392 smu->od_settings = &powerplay_table->overdrive_table; 393 394 return 0; 395 } 396 397 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu) 398 { 399 struct atom_smc_dpm_info_v4_9 *smc_dpm_table; 400 int index, ret; 401 I2cControllerConfig_t *table_member; 402 403 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 404 smc_dpm_info); 405 406 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 407 (uint8_t **)&smc_dpm_table); 408 if (ret) 409 return ret; 410 GET_PPTABLE_MEMBER(I2cControllers, &table_member); 411 memcpy(table_member, smc_dpm_table->I2cControllers, 412 sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header)); 413 414 return 0; 415 } 416 417 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu) 418 { 419 struct smu_table_context *table_context = &smu->smu_table; 420 struct smu_11_0_7_powerplay_table *powerplay_table = 421 table_context->power_play_table; 422 int table_size; 423 424 table_size = get_table_size(smu); 425 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 426 table_size); 427 428 return 0; 429 } 430 431 static int sienna_cichlid_patch_pptable_quirk(struct smu_context *smu) 432 { 433 struct amdgpu_device *adev = smu->adev; 434 uint32_t *board_reserved; 435 uint16_t *freq_table_gfx; 436 uint32_t i; 437 438 /* Fix some OEM SKU specific stability issues */ 439 GET_PPTABLE_MEMBER(BoardReserved, &board_reserved); 440 if ((adev->pdev->device == 0x73DF) && 441 (adev->pdev->revision == 0XC3) && 442 (adev->pdev->subsystem_device == 0x16C2) && 443 (adev->pdev->subsystem_vendor == 0x1043)) 444 board_reserved[0] = 1387; 445 446 GET_PPTABLE_MEMBER(FreqTableGfx, &freq_table_gfx); 447 if ((adev->pdev->device == 0x73DF) && 448 (adev->pdev->revision == 0XC3) && 449 ((adev->pdev->subsystem_device == 0x16C2) || 450 (adev->pdev->subsystem_device == 0x133C)) && 451 (adev->pdev->subsystem_vendor == 0x1043)) { 452 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) { 453 if (freq_table_gfx[i] > 2500) 454 freq_table_gfx[i] = 2500; 455 } 456 } 457 458 return 0; 459 } 460 461 static int sienna_cichlid_setup_pptable(struct smu_context *smu) 462 { 463 int ret = 0; 464 465 ret = smu_v11_0_setup_pptable(smu); 466 if (ret) 467 return ret; 468 469 ret = sienna_cichlid_store_powerplay_table(smu); 470 if (ret) 471 return ret; 472 473 ret = sienna_cichlid_append_powerplay_table(smu); 474 if (ret) 475 return ret; 476 477 ret = sienna_cichlid_check_powerplay_table(smu); 478 if (ret) 479 return ret; 480 481 return sienna_cichlid_patch_pptable_quirk(smu); 482 } 483 484 static int sienna_cichlid_tables_init(struct smu_context *smu) 485 { 486 struct smu_table_context *smu_table = &smu->smu_table; 487 struct smu_table *tables = smu_table->tables; 488 int table_size; 489 490 table_size = get_table_size(smu); 491 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size, 492 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 493 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 494 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 495 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t), 496 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 497 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 498 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 499 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t), 500 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 501 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 502 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 503 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, 504 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE, 505 AMDGPU_GEM_DOMAIN_VRAM); 506 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t), 507 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 508 SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfigExternal_t), 509 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 510 511 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL); 512 if (!smu_table->metrics_table) 513 goto err0_out; 514 smu_table->metrics_time = 0; 515 516 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 517 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 518 if (!smu_table->gpu_metrics_table) 519 goto err1_out; 520 521 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 522 if (!smu_table->watermarks_table) 523 goto err2_out; 524 525 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL); 526 if (!smu_table->ecc_table) 527 goto err3_out; 528 529 smu_table->driver_smu_config_table = 530 kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL); 531 if (!smu_table->driver_smu_config_table) 532 goto err4_out; 533 534 return 0; 535 536 err4_out: 537 kfree(smu_table->ecc_table); 538 err3_out: 539 kfree(smu_table->watermarks_table); 540 err2_out: 541 kfree(smu_table->gpu_metrics_table); 542 err1_out: 543 kfree(smu_table->metrics_table); 544 err0_out: 545 return -ENOMEM; 546 } 547 548 static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu) 549 { 550 struct smu_table_context *smu_table= &smu->smu_table; 551 SmuMetricsExternal_t *metrics_ext = 552 (SmuMetricsExternal_t *)(smu_table->metrics_table); 553 uint32_t throttler_status = 0; 554 int i; 555 556 if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 557 (smu->smc_fw_version >= 0x3A4900)) { 558 for (i = 0; i < THROTTLER_COUNT; i++) 559 throttler_status |= 560 (metrics_ext->SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0); 561 } else if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 562 (smu->smc_fw_version >= 0x3A4300)) { 563 for (i = 0; i < THROTTLER_COUNT; i++) 564 throttler_status |= 565 (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0); 566 } else { 567 throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus; 568 } 569 570 return throttler_status; 571 } 572 573 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu, 574 MetricsMember_t member, 575 uint32_t *value) 576 { 577 struct smu_table_context *smu_table= &smu->smu_table; 578 SmuMetrics_t *metrics = 579 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics); 580 SmuMetrics_V2_t *metrics_v2 = 581 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2); 582 SmuMetrics_V3_t *metrics_v3 = 583 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V3); 584 bool use_metrics_v2 = false; 585 bool use_metrics_v3 = false; 586 uint16_t average_gfx_activity; 587 int ret = 0; 588 589 if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 590 (smu->smc_fw_version >= 0x3A4900)) 591 use_metrics_v3 = true; 592 else if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 593 (smu->smc_fw_version >= 0x3A4300)) 594 use_metrics_v2 = true; 595 596 ret = smu_cmn_get_metrics_table(smu, 597 NULL, 598 false); 599 if (ret) 600 return ret; 601 602 switch (member) { 603 case METRICS_CURR_GFXCLK: 604 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] : 605 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : 606 metrics->CurrClock[PPCLK_GFXCLK]; 607 break; 608 case METRICS_CURR_SOCCLK: 609 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] : 610 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : 611 metrics->CurrClock[PPCLK_SOCCLK]; 612 break; 613 case METRICS_CURR_UCLK: 614 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] : 615 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : 616 metrics->CurrClock[PPCLK_UCLK]; 617 break; 618 case METRICS_CURR_VCLK: 619 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] : 620 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : 621 metrics->CurrClock[PPCLK_VCLK_0]; 622 break; 623 case METRICS_CURR_VCLK1: 624 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] : 625 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : 626 metrics->CurrClock[PPCLK_VCLK_1]; 627 break; 628 case METRICS_CURR_DCLK: 629 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] : 630 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : 631 metrics->CurrClock[PPCLK_DCLK_0]; 632 break; 633 case METRICS_CURR_DCLK1: 634 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] : 635 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : 636 metrics->CurrClock[PPCLK_DCLK_1]; 637 break; 638 case METRICS_CURR_DCEFCLK: 639 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCEFCLK] : 640 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] : 641 metrics->CurrClock[PPCLK_DCEFCLK]; 642 break; 643 case METRICS_CURR_FCLK: 644 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_FCLK] : 645 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] : 646 metrics->CurrClock[PPCLK_FCLK]; 647 break; 648 case METRICS_AVERAGE_GFXCLK: 649 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity : 650 use_metrics_v2 ? metrics_v2->AverageGfxActivity : 651 metrics->AverageGfxActivity; 652 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD) 653 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs : 654 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs : 655 metrics->AverageGfxclkFrequencyPostDs; 656 else 657 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs : 658 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs : 659 metrics->AverageGfxclkFrequencyPreDs; 660 break; 661 case METRICS_AVERAGE_FCLK: 662 *value = use_metrics_v3 ? metrics_v3->AverageFclkFrequencyPostDs : 663 use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs : 664 metrics->AverageFclkFrequencyPostDs; 665 break; 666 case METRICS_AVERAGE_UCLK: 667 *value = use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs : 668 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs : 669 metrics->AverageUclkFrequencyPostDs; 670 break; 671 case METRICS_AVERAGE_GFXACTIVITY: 672 *value = use_metrics_v3 ? metrics_v3->AverageGfxActivity : 673 use_metrics_v2 ? metrics_v2->AverageGfxActivity : 674 metrics->AverageGfxActivity; 675 break; 676 case METRICS_AVERAGE_MEMACTIVITY: 677 *value = use_metrics_v3 ? metrics_v3->AverageUclkActivity : 678 use_metrics_v2 ? metrics_v2->AverageUclkActivity : 679 metrics->AverageUclkActivity; 680 break; 681 case METRICS_AVERAGE_SOCKETPOWER: 682 *value = use_metrics_v3 ? metrics_v3->AverageSocketPower << 8 : 683 use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 : 684 metrics->AverageSocketPower << 8; 685 break; 686 case METRICS_TEMPERATURE_EDGE: 687 *value = (use_metrics_v3 ? metrics_v3->TemperatureEdge : 688 use_metrics_v2 ? metrics_v2->TemperatureEdge : 689 metrics->TemperatureEdge) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 690 break; 691 case METRICS_TEMPERATURE_HOTSPOT: 692 *value = (use_metrics_v3 ? metrics_v3->TemperatureHotspot : 693 use_metrics_v2 ? metrics_v2->TemperatureHotspot : 694 metrics->TemperatureHotspot) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 695 break; 696 case METRICS_TEMPERATURE_MEM: 697 *value = (use_metrics_v3 ? metrics_v3->TemperatureMem : 698 use_metrics_v2 ? metrics_v2->TemperatureMem : 699 metrics->TemperatureMem) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 700 break; 701 case METRICS_TEMPERATURE_VRGFX: 702 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrGfx : 703 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : 704 metrics->TemperatureVrGfx) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 705 break; 706 case METRICS_TEMPERATURE_VRSOC: 707 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrSoc : 708 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : 709 metrics->TemperatureVrSoc) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 710 break; 711 case METRICS_THROTTLER_STATUS: 712 *value = sienna_cichlid_get_throttler_status_locked(smu); 713 break; 714 case METRICS_CURR_FANSPEED: 715 *value = use_metrics_v3 ? metrics_v3->CurrFanSpeed : 716 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed; 717 break; 718 default: 719 *value = UINT_MAX; 720 break; 721 } 722 723 return ret; 724 725 } 726 727 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu) 728 { 729 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 730 731 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 732 GFP_KERNEL); 733 if (!smu_dpm->dpm_context) 734 return -ENOMEM; 735 736 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 737 738 return 0; 739 } 740 741 static void sienna_cichlid_stb_init(struct smu_context *smu); 742 743 static int sienna_cichlid_init_smc_tables(struct smu_context *smu) 744 { 745 int ret = 0; 746 747 ret = sienna_cichlid_tables_init(smu); 748 if (ret) 749 return ret; 750 751 ret = sienna_cichlid_allocate_dpm_context(smu); 752 if (ret) 753 return ret; 754 755 sienna_cichlid_stb_init(smu); 756 757 return smu_v11_0_init_smc_tables(smu); 758 } 759 760 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) 761 { 762 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 763 struct smu_11_0_dpm_table *dpm_table; 764 struct amdgpu_device *adev = smu->adev; 765 int i, ret = 0; 766 DpmDescriptor_t *table_member; 767 768 /* socclk dpm table setup */ 769 dpm_table = &dpm_context->dpm_tables.soc_table; 770 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member); 771 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 772 ret = smu_v11_0_set_single_dpm_table(smu, 773 SMU_SOCCLK, 774 dpm_table); 775 if (ret) 776 return ret; 777 dpm_table->is_fine_grained = 778 !table_member[PPCLK_SOCCLK].SnapToDiscrete; 779 } else { 780 dpm_table->count = 1; 781 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 782 dpm_table->dpm_levels[0].enabled = true; 783 dpm_table->min = dpm_table->dpm_levels[0].value; 784 dpm_table->max = dpm_table->dpm_levels[0].value; 785 } 786 787 /* gfxclk dpm table setup */ 788 dpm_table = &dpm_context->dpm_tables.gfx_table; 789 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 790 ret = smu_v11_0_set_single_dpm_table(smu, 791 SMU_GFXCLK, 792 dpm_table); 793 if (ret) 794 return ret; 795 dpm_table->is_fine_grained = 796 !table_member[PPCLK_GFXCLK].SnapToDiscrete; 797 } else { 798 dpm_table->count = 1; 799 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 800 dpm_table->dpm_levels[0].enabled = true; 801 dpm_table->min = dpm_table->dpm_levels[0].value; 802 dpm_table->max = dpm_table->dpm_levels[0].value; 803 } 804 805 /* uclk dpm table setup */ 806 dpm_table = &dpm_context->dpm_tables.uclk_table; 807 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 808 ret = smu_v11_0_set_single_dpm_table(smu, 809 SMU_UCLK, 810 dpm_table); 811 if (ret) 812 return ret; 813 dpm_table->is_fine_grained = 814 !table_member[PPCLK_UCLK].SnapToDiscrete; 815 } else { 816 dpm_table->count = 1; 817 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 818 dpm_table->dpm_levels[0].enabled = true; 819 dpm_table->min = dpm_table->dpm_levels[0].value; 820 dpm_table->max = dpm_table->dpm_levels[0].value; 821 } 822 823 /* fclk dpm table setup */ 824 dpm_table = &dpm_context->dpm_tables.fclk_table; 825 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 826 ret = smu_v11_0_set_single_dpm_table(smu, 827 SMU_FCLK, 828 dpm_table); 829 if (ret) 830 return ret; 831 dpm_table->is_fine_grained = 832 !table_member[PPCLK_FCLK].SnapToDiscrete; 833 } else { 834 dpm_table->count = 1; 835 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 836 dpm_table->dpm_levels[0].enabled = true; 837 dpm_table->min = dpm_table->dpm_levels[0].value; 838 dpm_table->max = dpm_table->dpm_levels[0].value; 839 } 840 841 /* vclk0/1 dpm table setup */ 842 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 843 if (adev->vcn.harvest_config & (1 << i)) 844 continue; 845 846 dpm_table = &dpm_context->dpm_tables.vclk_table; 847 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 848 ret = smu_v11_0_set_single_dpm_table(smu, 849 i ? SMU_VCLK1 : SMU_VCLK, 850 dpm_table); 851 if (ret) 852 return ret; 853 dpm_table->is_fine_grained = 854 !table_member[i ? PPCLK_VCLK_1 : PPCLK_VCLK_0].SnapToDiscrete; 855 } else { 856 dpm_table->count = 1; 857 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; 858 dpm_table->dpm_levels[0].enabled = true; 859 dpm_table->min = dpm_table->dpm_levels[0].value; 860 dpm_table->max = dpm_table->dpm_levels[0].value; 861 } 862 } 863 864 /* dclk0/1 dpm table setup */ 865 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 866 if (adev->vcn.harvest_config & (1 << i)) 867 continue; 868 dpm_table = &dpm_context->dpm_tables.dclk_table; 869 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 870 ret = smu_v11_0_set_single_dpm_table(smu, 871 i ? SMU_DCLK1 : SMU_DCLK, 872 dpm_table); 873 if (ret) 874 return ret; 875 dpm_table->is_fine_grained = 876 !table_member[i ? PPCLK_DCLK_1 : PPCLK_DCLK_0].SnapToDiscrete; 877 } else { 878 dpm_table->count = 1; 879 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; 880 dpm_table->dpm_levels[0].enabled = true; 881 dpm_table->min = dpm_table->dpm_levels[0].value; 882 dpm_table->max = dpm_table->dpm_levels[0].value; 883 } 884 } 885 886 /* dcefclk dpm table setup */ 887 dpm_table = &dpm_context->dpm_tables.dcef_table; 888 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 889 ret = smu_v11_0_set_single_dpm_table(smu, 890 SMU_DCEFCLK, 891 dpm_table); 892 if (ret) 893 return ret; 894 dpm_table->is_fine_grained = 895 !table_member[PPCLK_DCEFCLK].SnapToDiscrete; 896 } else { 897 dpm_table->count = 1; 898 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 899 dpm_table->dpm_levels[0].enabled = true; 900 dpm_table->min = dpm_table->dpm_levels[0].value; 901 dpm_table->max = dpm_table->dpm_levels[0].value; 902 } 903 904 /* pixelclk dpm table setup */ 905 dpm_table = &dpm_context->dpm_tables.pixel_table; 906 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 907 ret = smu_v11_0_set_single_dpm_table(smu, 908 SMU_PIXCLK, 909 dpm_table); 910 if (ret) 911 return ret; 912 dpm_table->is_fine_grained = 913 !table_member[PPCLK_PIXCLK].SnapToDiscrete; 914 } else { 915 dpm_table->count = 1; 916 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 917 dpm_table->dpm_levels[0].enabled = true; 918 dpm_table->min = dpm_table->dpm_levels[0].value; 919 dpm_table->max = dpm_table->dpm_levels[0].value; 920 } 921 922 /* displayclk dpm table setup */ 923 dpm_table = &dpm_context->dpm_tables.display_table; 924 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 925 ret = smu_v11_0_set_single_dpm_table(smu, 926 SMU_DISPCLK, 927 dpm_table); 928 if (ret) 929 return ret; 930 dpm_table->is_fine_grained = 931 !table_member[PPCLK_DISPCLK].SnapToDiscrete; 932 } else { 933 dpm_table->count = 1; 934 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 935 dpm_table->dpm_levels[0].enabled = true; 936 dpm_table->min = dpm_table->dpm_levels[0].value; 937 dpm_table->max = dpm_table->dpm_levels[0].value; 938 } 939 940 /* phyclk dpm table setup */ 941 dpm_table = &dpm_context->dpm_tables.phy_table; 942 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 943 ret = smu_v11_0_set_single_dpm_table(smu, 944 SMU_PHYCLK, 945 dpm_table); 946 if (ret) 947 return ret; 948 dpm_table->is_fine_grained = 949 !table_member[PPCLK_PHYCLK].SnapToDiscrete; 950 } else { 951 dpm_table->count = 1; 952 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 953 dpm_table->dpm_levels[0].enabled = true; 954 dpm_table->min = dpm_table->dpm_levels[0].value; 955 dpm_table->max = dpm_table->dpm_levels[0].value; 956 } 957 958 return 0; 959 } 960 961 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 962 { 963 struct amdgpu_device *adev = smu->adev; 964 int i, ret = 0; 965 966 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 967 if (adev->vcn.harvest_config & (1 << i)) 968 continue; 969 /* vcn dpm on is a prerequisite for vcn power gate messages */ 970 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 971 ret = smu_cmn_send_smc_msg_with_param(smu, enable ? 972 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn, 973 0x10000 * i, NULL); 974 if (ret) 975 return ret; 976 } 977 } 978 979 return ret; 980 } 981 982 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 983 { 984 int ret = 0; 985 986 if (enable) { 987 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 988 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); 989 if (ret) 990 return ret; 991 } 992 } else { 993 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 994 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); 995 if (ret) 996 return ret; 997 } 998 } 999 1000 return ret; 1001 } 1002 1003 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu, 1004 enum smu_clk_type clk_type, 1005 uint32_t *value) 1006 { 1007 MetricsMember_t member_type; 1008 int clk_id = 0; 1009 1010 clk_id = smu_cmn_to_asic_specific_index(smu, 1011 CMN2ASIC_MAPPING_CLK, 1012 clk_type); 1013 if (clk_id < 0) 1014 return clk_id; 1015 1016 switch (clk_id) { 1017 case PPCLK_GFXCLK: 1018 member_type = METRICS_CURR_GFXCLK; 1019 break; 1020 case PPCLK_UCLK: 1021 member_type = METRICS_CURR_UCLK; 1022 break; 1023 case PPCLK_SOCCLK: 1024 member_type = METRICS_CURR_SOCCLK; 1025 break; 1026 case PPCLK_FCLK: 1027 member_type = METRICS_CURR_FCLK; 1028 break; 1029 case PPCLK_VCLK_0: 1030 member_type = METRICS_CURR_VCLK; 1031 break; 1032 case PPCLK_VCLK_1: 1033 member_type = METRICS_CURR_VCLK1; 1034 break; 1035 case PPCLK_DCLK_0: 1036 member_type = METRICS_CURR_DCLK; 1037 break; 1038 case PPCLK_DCLK_1: 1039 member_type = METRICS_CURR_DCLK1; 1040 break; 1041 case PPCLK_DCEFCLK: 1042 member_type = METRICS_CURR_DCEFCLK; 1043 break; 1044 default: 1045 return -EINVAL; 1046 } 1047 1048 return sienna_cichlid_get_smu_metrics_data(smu, 1049 member_type, 1050 value); 1051 1052 } 1053 1054 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) 1055 { 1056 DpmDescriptor_t *dpm_desc = NULL; 1057 DpmDescriptor_t *table_member; 1058 uint32_t clk_index = 0; 1059 1060 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member); 1061 clk_index = smu_cmn_to_asic_specific_index(smu, 1062 CMN2ASIC_MAPPING_CLK, 1063 clk_type); 1064 dpm_desc = &table_member[clk_index]; 1065 1066 /* 0 - Fine grained DPM, 1 - Discrete DPM */ 1067 return dpm_desc->SnapToDiscrete == 0; 1068 } 1069 1070 static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table, 1071 enum SMU_11_0_7_ODFEATURE_CAP cap) 1072 { 1073 return od_table->cap[cap]; 1074 } 1075 1076 static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table, 1077 enum SMU_11_0_7_ODSETTING_ID setting, 1078 uint32_t *min, uint32_t *max) 1079 { 1080 if (min) 1081 *min = od_table->min[setting]; 1082 if (max) 1083 *max = od_table->max[setting]; 1084 } 1085 1086 static int sienna_cichlid_print_clk_levels(struct smu_context *smu, 1087 enum smu_clk_type clk_type, char *buf) 1088 { 1089 struct amdgpu_device *adev = smu->adev; 1090 struct smu_table_context *table_context = &smu->smu_table; 1091 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1092 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1093 uint16_t *table_member; 1094 1095 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings; 1096 OverDriveTable_t *od_table = 1097 (OverDriveTable_t *)table_context->overdrive_table; 1098 int i, size = 0, ret = 0; 1099 uint32_t cur_value = 0, value = 0, count = 0; 1100 uint32_t freq_values[3] = {0}; 1101 uint32_t mark_index = 0; 1102 uint32_t gen_speed, lane_width; 1103 uint32_t min_value, max_value; 1104 uint32_t smu_version; 1105 1106 smu_cmn_get_sysfs_buf(&buf, &size); 1107 1108 switch (clk_type) { 1109 case SMU_GFXCLK: 1110 case SMU_SCLK: 1111 case SMU_SOCCLK: 1112 case SMU_MCLK: 1113 case SMU_UCLK: 1114 case SMU_FCLK: 1115 case SMU_VCLK: 1116 case SMU_VCLK1: 1117 case SMU_DCLK: 1118 case SMU_DCLK1: 1119 case SMU_DCEFCLK: 1120 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value); 1121 if (ret) 1122 goto print_clk_out; 1123 1124 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); 1125 if (ret) 1126 goto print_clk_out; 1127 1128 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) { 1129 for (i = 0; i < count; i++) { 1130 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); 1131 if (ret) 1132 goto print_clk_out; 1133 1134 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 1135 cur_value == value ? "*" : ""); 1136 } 1137 } else { 1138 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]); 1139 if (ret) 1140 goto print_clk_out; 1141 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]); 1142 if (ret) 1143 goto print_clk_out; 1144 1145 freq_values[1] = cur_value; 1146 mark_index = cur_value == freq_values[0] ? 0 : 1147 cur_value == freq_values[2] ? 2 : 1; 1148 1149 count = 3; 1150 if (mark_index != 1) { 1151 count = 2; 1152 freq_values[1] = freq_values[2]; 1153 } 1154 1155 for (i = 0; i < count; i++) { 1156 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i], 1157 cur_value == freq_values[i] ? "*" : ""); 1158 } 1159 1160 } 1161 break; 1162 case SMU_PCIE: 1163 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); 1164 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); 1165 GET_PPTABLE_MEMBER(LclkFreq, &table_member); 1166 for (i = 0; i < NUM_LINK_LEVELS; i++) 1167 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i, 1168 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," : 1169 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," : 1170 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," : 1171 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "", 1172 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" : 1173 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" : 1174 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" : 1175 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" : 1176 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" : 1177 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "", 1178 table_member[i], 1179 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && 1180 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? 1181 "*" : ""); 1182 break; 1183 case SMU_OD_SCLK: 1184 if (!smu->od_enabled || !od_table || !od_settings) 1185 break; 1186 1187 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) 1188 break; 1189 1190 size += sysfs_emit_at(buf, size, "OD_SCLK:\n"); 1191 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax); 1192 break; 1193 1194 case SMU_OD_MCLK: 1195 if (!smu->od_enabled || !od_table || !od_settings) 1196 break; 1197 1198 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) 1199 break; 1200 1201 size += sysfs_emit_at(buf, size, "OD_MCLK:\n"); 1202 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax); 1203 break; 1204 1205 case SMU_OD_VDDGFX_OFFSET: 1206 if (!smu->od_enabled || !od_table || !od_settings) 1207 break; 1208 1209 /* 1210 * OD GFX Voltage Offset functionality is supported only by 58.41.0 1211 * and onwards SMU firmwares. 1212 */ 1213 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1214 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 1215 (smu_version < 0x003a2900)) 1216 break; 1217 1218 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n"); 1219 size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset); 1220 break; 1221 1222 case SMU_OD_RANGE: 1223 if (!smu->od_enabled || !od_table || !od_settings) 1224 break; 1225 1226 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 1227 1228 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) { 1229 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN, 1230 &min_value, NULL); 1231 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX, 1232 NULL, &max_value); 1233 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 1234 min_value, max_value); 1235 } 1236 1237 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) { 1238 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN, 1239 &min_value, NULL); 1240 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX, 1241 NULL, &max_value); 1242 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n", 1243 min_value, max_value); 1244 } 1245 break; 1246 1247 default: 1248 break; 1249 } 1250 1251 print_clk_out: 1252 return size; 1253 } 1254 1255 static int sienna_cichlid_force_clk_levels(struct smu_context *smu, 1256 enum smu_clk_type clk_type, uint32_t mask) 1257 { 1258 int ret = 0; 1259 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; 1260 1261 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1262 soft_max_level = mask ? (fls(mask) - 1) : 0; 1263 1264 switch (clk_type) { 1265 case SMU_GFXCLK: 1266 case SMU_SCLK: 1267 case SMU_SOCCLK: 1268 case SMU_MCLK: 1269 case SMU_UCLK: 1270 case SMU_FCLK: 1271 /* There is only 2 levels for fine grained DPM */ 1272 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) { 1273 soft_max_level = (soft_max_level >= 1 ? 1 : 0); 1274 soft_min_level = (soft_min_level >= 1 ? 1 : 0); 1275 } 1276 1277 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); 1278 if (ret) 1279 goto forec_level_out; 1280 1281 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq); 1282 if (ret) 1283 goto forec_level_out; 1284 1285 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 1286 if (ret) 1287 goto forec_level_out; 1288 break; 1289 case SMU_DCEFCLK: 1290 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n"); 1291 break; 1292 default: 1293 break; 1294 } 1295 1296 forec_level_out: 1297 return 0; 1298 } 1299 1300 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu) 1301 { 1302 struct smu_11_0_dpm_context *dpm_context = 1303 smu->smu_dpm.dpm_context; 1304 struct smu_11_0_dpm_table *gfx_table = 1305 &dpm_context->dpm_tables.gfx_table; 1306 struct smu_11_0_dpm_table *mem_table = 1307 &dpm_context->dpm_tables.uclk_table; 1308 struct smu_11_0_dpm_table *soc_table = 1309 &dpm_context->dpm_tables.soc_table; 1310 struct smu_umd_pstate_table *pstate_table = 1311 &smu->pstate_table; 1312 struct amdgpu_device *adev = smu->adev; 1313 1314 pstate_table->gfxclk_pstate.min = gfx_table->min; 1315 pstate_table->gfxclk_pstate.peak = gfx_table->max; 1316 1317 pstate_table->uclk_pstate.min = mem_table->min; 1318 pstate_table->uclk_pstate.peak = mem_table->max; 1319 1320 pstate_table->socclk_pstate.min = soc_table->min; 1321 pstate_table->socclk_pstate.peak = soc_table->max; 1322 1323 switch (adev->asic_type) { 1324 case CHIP_SIENNA_CICHLID: 1325 case CHIP_NAVY_FLOUNDER: 1326 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK; 1327 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK; 1328 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK; 1329 break; 1330 case CHIP_DIMGREY_CAVEFISH: 1331 pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK; 1332 pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK; 1333 pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK; 1334 break; 1335 case CHIP_BEIGE_GOBY: 1336 pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK; 1337 pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK; 1338 pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK; 1339 break; 1340 default: 1341 break; 1342 } 1343 1344 return 0; 1345 } 1346 1347 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu) 1348 { 1349 int ret = 0; 1350 uint32_t max_freq = 0; 1351 1352 /* Sienna_Cichlid do not support to change display num currently */ 1353 return 0; 1354 #if 0 1355 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL); 1356 if (ret) 1357 return ret; 1358 #endif 1359 1360 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1361 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq); 1362 if (ret) 1363 return ret; 1364 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq); 1365 if (ret) 1366 return ret; 1367 } 1368 1369 return ret; 1370 } 1371 1372 static int sienna_cichlid_display_config_changed(struct smu_context *smu) 1373 { 1374 int ret = 0; 1375 1376 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1377 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) && 1378 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 1379 #if 0 1380 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 1381 smu->display_config->num_display, 1382 NULL); 1383 #endif 1384 if (ret) 1385 return ret; 1386 } 1387 1388 return ret; 1389 } 1390 1391 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu) 1392 { 1393 int ret = 0; 1394 uint64_t feature_enabled; 1395 1396 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 1397 if (ret) 1398 return false; 1399 1400 return !!(feature_enabled & SMC_DPM_FEATURE); 1401 } 1402 1403 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu, 1404 uint32_t *speed) 1405 { 1406 if (!speed) 1407 return -EINVAL; 1408 1409 /* 1410 * For Sienna_Cichlid and later, the fan speed(rpm) reported 1411 * by pmfw is always trustable(even when the fan control feature 1412 * disabled or 0 RPM kicked in). 1413 */ 1414 return sienna_cichlid_get_smu_metrics_data(smu, 1415 METRICS_CURR_FANSPEED, 1416 speed); 1417 } 1418 1419 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu) 1420 { 1421 uint16_t *table_member; 1422 1423 GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member); 1424 smu->fan_max_rpm = *table_member; 1425 1426 return 0; 1427 } 1428 1429 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf) 1430 { 1431 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 1432 DpmActivityMonitorCoeffInt_t *activity_monitor = 1433 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 1434 uint32_t i, size = 0; 1435 int16_t workload_type = 0; 1436 static const char *title[] = { 1437 "PROFILE_INDEX(NAME)", 1438 "CLOCK_TYPE(NAME)", 1439 "FPS", 1440 "MinFreqType", 1441 "MinActiveFreqType", 1442 "MinActiveFreq", 1443 "BoosterFreqType", 1444 "BoosterFreq", 1445 "PD_Data_limit_c", 1446 "PD_Data_error_coeff", 1447 "PD_Data_error_rate_coeff"}; 1448 int result = 0; 1449 1450 if (!buf) 1451 return -EINVAL; 1452 1453 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n", 1454 title[0], title[1], title[2], title[3], title[4], title[5], 1455 title[6], title[7], title[8], title[9], title[10]); 1456 1457 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1458 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1459 workload_type = smu_cmn_to_asic_specific_index(smu, 1460 CMN2ASIC_MAPPING_WORKLOAD, 1461 i); 1462 if (workload_type < 0) 1463 return -EINVAL; 1464 1465 result = smu_cmn_update_table(smu, 1466 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type, 1467 (void *)(&activity_monitor_external), false); 1468 if (result) { 1469 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1470 return result; 1471 } 1472 1473 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n", 1474 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1475 1476 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1477 " ", 1478 0, 1479 "GFXCLK", 1480 activity_monitor->Gfx_FPS, 1481 activity_monitor->Gfx_MinFreqStep, 1482 activity_monitor->Gfx_MinActiveFreqType, 1483 activity_monitor->Gfx_MinActiveFreq, 1484 activity_monitor->Gfx_BoosterFreqType, 1485 activity_monitor->Gfx_BoosterFreq, 1486 activity_monitor->Gfx_PD_Data_limit_c, 1487 activity_monitor->Gfx_PD_Data_error_coeff, 1488 activity_monitor->Gfx_PD_Data_error_rate_coeff); 1489 1490 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1491 " ", 1492 1, 1493 "SOCCLK", 1494 activity_monitor->Fclk_FPS, 1495 activity_monitor->Fclk_MinFreqStep, 1496 activity_monitor->Fclk_MinActiveFreqType, 1497 activity_monitor->Fclk_MinActiveFreq, 1498 activity_monitor->Fclk_BoosterFreqType, 1499 activity_monitor->Fclk_BoosterFreq, 1500 activity_monitor->Fclk_PD_Data_limit_c, 1501 activity_monitor->Fclk_PD_Data_error_coeff, 1502 activity_monitor->Fclk_PD_Data_error_rate_coeff); 1503 1504 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1505 " ", 1506 2, 1507 "MEMLK", 1508 activity_monitor->Mem_FPS, 1509 activity_monitor->Mem_MinFreqStep, 1510 activity_monitor->Mem_MinActiveFreqType, 1511 activity_monitor->Mem_MinActiveFreq, 1512 activity_monitor->Mem_BoosterFreqType, 1513 activity_monitor->Mem_BoosterFreq, 1514 activity_monitor->Mem_PD_Data_limit_c, 1515 activity_monitor->Mem_PD_Data_error_coeff, 1516 activity_monitor->Mem_PD_Data_error_rate_coeff); 1517 } 1518 1519 return size; 1520 } 1521 1522 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 1523 { 1524 1525 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 1526 DpmActivityMonitorCoeffInt_t *activity_monitor = 1527 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 1528 int workload_type, ret = 0; 1529 1530 smu->power_profile_mode = input[size]; 1531 1532 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 1533 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode); 1534 return -EINVAL; 1535 } 1536 1537 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 1538 1539 ret = smu_cmn_update_table(smu, 1540 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1541 (void *)(&activity_monitor_external), false); 1542 if (ret) { 1543 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1544 return ret; 1545 } 1546 1547 switch (input[0]) { 1548 case 0: /* Gfxclk */ 1549 activity_monitor->Gfx_FPS = input[1]; 1550 activity_monitor->Gfx_MinFreqStep = input[2]; 1551 activity_monitor->Gfx_MinActiveFreqType = input[3]; 1552 activity_monitor->Gfx_MinActiveFreq = input[4]; 1553 activity_monitor->Gfx_BoosterFreqType = input[5]; 1554 activity_monitor->Gfx_BoosterFreq = input[6]; 1555 activity_monitor->Gfx_PD_Data_limit_c = input[7]; 1556 activity_monitor->Gfx_PD_Data_error_coeff = input[8]; 1557 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9]; 1558 break; 1559 case 1: /* Socclk */ 1560 activity_monitor->Fclk_FPS = input[1]; 1561 activity_monitor->Fclk_MinFreqStep = input[2]; 1562 activity_monitor->Fclk_MinActiveFreqType = input[3]; 1563 activity_monitor->Fclk_MinActiveFreq = input[4]; 1564 activity_monitor->Fclk_BoosterFreqType = input[5]; 1565 activity_monitor->Fclk_BoosterFreq = input[6]; 1566 activity_monitor->Fclk_PD_Data_limit_c = input[7]; 1567 activity_monitor->Fclk_PD_Data_error_coeff = input[8]; 1568 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9]; 1569 break; 1570 case 2: /* Memlk */ 1571 activity_monitor->Mem_FPS = input[1]; 1572 activity_monitor->Mem_MinFreqStep = input[2]; 1573 activity_monitor->Mem_MinActiveFreqType = input[3]; 1574 activity_monitor->Mem_MinActiveFreq = input[4]; 1575 activity_monitor->Mem_BoosterFreqType = input[5]; 1576 activity_monitor->Mem_BoosterFreq = input[6]; 1577 activity_monitor->Mem_PD_Data_limit_c = input[7]; 1578 activity_monitor->Mem_PD_Data_error_coeff = input[8]; 1579 activity_monitor->Mem_PD_Data_error_rate_coeff = input[9]; 1580 break; 1581 } 1582 1583 ret = smu_cmn_update_table(smu, 1584 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1585 (void *)(&activity_monitor_external), true); 1586 if (ret) { 1587 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 1588 return ret; 1589 } 1590 } 1591 1592 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1593 workload_type = smu_cmn_to_asic_specific_index(smu, 1594 CMN2ASIC_MAPPING_WORKLOAD, 1595 smu->power_profile_mode); 1596 if (workload_type < 0) 1597 return -EINVAL; 1598 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 1599 1 << workload_type, NULL); 1600 1601 return ret; 1602 } 1603 1604 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu) 1605 { 1606 struct smu_clocks min_clocks = {0}; 1607 struct pp_display_clock_request clock_req; 1608 int ret = 0; 1609 1610 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; 1611 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; 1612 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; 1613 1614 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1615 clock_req.clock_type = amd_pp_dcef_clock; 1616 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; 1617 1618 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req); 1619 if (!ret) { 1620 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) { 1621 ret = smu_cmn_send_smc_msg_with_param(smu, 1622 SMU_MSG_SetMinDeepSleepDcefclk, 1623 min_clocks.dcef_clock_in_sr/100, 1624 NULL); 1625 if (ret) { 1626 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!"); 1627 return ret; 1628 } 1629 } 1630 } else { 1631 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!"); 1632 } 1633 } 1634 1635 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1636 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); 1637 if (ret) { 1638 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__); 1639 return ret; 1640 } 1641 } 1642 1643 return 0; 1644 } 1645 1646 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu, 1647 struct pp_smu_wm_range_sets *clock_ranges) 1648 { 1649 Watermarks_t *table = smu->smu_table.watermarks_table; 1650 int ret = 0; 1651 int i; 1652 1653 if (clock_ranges) { 1654 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 1655 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1656 return -EINVAL; 1657 1658 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1659 table->WatermarkRow[WM_DCEFCLK][i].MinClock = 1660 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1661 table->WatermarkRow[WM_DCEFCLK][i].MaxClock = 1662 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1663 table->WatermarkRow[WM_DCEFCLK][i].MinUclk = 1664 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1665 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk = 1666 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1667 1668 table->WatermarkRow[WM_DCEFCLK][i].WmSetting = 1669 clock_ranges->reader_wm_sets[i].wm_inst; 1670 } 1671 1672 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1673 table->WatermarkRow[WM_SOCCLK][i].MinClock = 1674 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1675 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1676 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1677 table->WatermarkRow[WM_SOCCLK][i].MinUclk = 1678 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1679 table->WatermarkRow[WM_SOCCLK][i].MaxUclk = 1680 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1681 1682 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1683 clock_ranges->writer_wm_sets[i].wm_inst; 1684 } 1685 1686 smu->watermarks_bitmap |= WATERMARKS_EXIST; 1687 } 1688 1689 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1690 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1691 ret = smu_cmn_write_watermarks_table(smu); 1692 if (ret) { 1693 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1694 return ret; 1695 } 1696 smu->watermarks_bitmap |= WATERMARKS_LOADED; 1697 } 1698 1699 return 0; 1700 } 1701 1702 static int sienna_cichlid_read_sensor(struct smu_context *smu, 1703 enum amd_pp_sensors sensor, 1704 void *data, uint32_t *size) 1705 { 1706 int ret = 0; 1707 uint16_t *temp; 1708 1709 if(!data || !size) 1710 return -EINVAL; 1711 1712 switch (sensor) { 1713 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 1714 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp); 1715 *(uint16_t *)data = *temp; 1716 *size = 4; 1717 break; 1718 case AMDGPU_PP_SENSOR_MEM_LOAD: 1719 ret = sienna_cichlid_get_smu_metrics_data(smu, 1720 METRICS_AVERAGE_MEMACTIVITY, 1721 (uint32_t *)data); 1722 *size = 4; 1723 break; 1724 case AMDGPU_PP_SENSOR_GPU_LOAD: 1725 ret = sienna_cichlid_get_smu_metrics_data(smu, 1726 METRICS_AVERAGE_GFXACTIVITY, 1727 (uint32_t *)data); 1728 *size = 4; 1729 break; 1730 case AMDGPU_PP_SENSOR_GPU_POWER: 1731 ret = sienna_cichlid_get_smu_metrics_data(smu, 1732 METRICS_AVERAGE_SOCKETPOWER, 1733 (uint32_t *)data); 1734 *size = 4; 1735 break; 1736 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1737 ret = sienna_cichlid_get_smu_metrics_data(smu, 1738 METRICS_TEMPERATURE_HOTSPOT, 1739 (uint32_t *)data); 1740 *size = 4; 1741 break; 1742 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1743 ret = sienna_cichlid_get_smu_metrics_data(smu, 1744 METRICS_TEMPERATURE_EDGE, 1745 (uint32_t *)data); 1746 *size = 4; 1747 break; 1748 case AMDGPU_PP_SENSOR_MEM_TEMP: 1749 ret = sienna_cichlid_get_smu_metrics_data(smu, 1750 METRICS_TEMPERATURE_MEM, 1751 (uint32_t *)data); 1752 *size = 4; 1753 break; 1754 case AMDGPU_PP_SENSOR_GFX_MCLK: 1755 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 1756 *(uint32_t *)data *= 100; 1757 *size = 4; 1758 break; 1759 case AMDGPU_PP_SENSOR_GFX_SCLK: 1760 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); 1761 *(uint32_t *)data *= 100; 1762 *size = 4; 1763 break; 1764 case AMDGPU_PP_SENSOR_VDDGFX: 1765 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data); 1766 *size = 4; 1767 break; 1768 default: 1769 ret = -EOPNOTSUPP; 1770 break; 1771 } 1772 1773 return ret; 1774 } 1775 1776 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states) 1777 { 1778 uint32_t num_discrete_levels = 0; 1779 uint16_t *dpm_levels = NULL; 1780 uint16_t i = 0; 1781 struct smu_table_context *table_context = &smu->smu_table; 1782 DpmDescriptor_t *table_member1; 1783 uint16_t *table_member2; 1784 1785 if (!clocks_in_khz || !num_states || !table_context->driver_pptable) 1786 return -EINVAL; 1787 1788 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1); 1789 num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels; 1790 GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2); 1791 dpm_levels = table_member2; 1792 1793 if (num_discrete_levels == 0 || dpm_levels == NULL) 1794 return -EINVAL; 1795 1796 *num_states = num_discrete_levels; 1797 for (i = 0; i < num_discrete_levels; i++) { 1798 /* convert to khz */ 1799 *clocks_in_khz = (*dpm_levels) * 1000; 1800 clocks_in_khz++; 1801 dpm_levels++; 1802 } 1803 1804 return 0; 1805 } 1806 1807 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu, 1808 struct smu_temperature_range *range) 1809 { 1810 struct smu_table_context *table_context = &smu->smu_table; 1811 struct smu_11_0_7_powerplay_table *powerplay_table = 1812 table_context->power_play_table; 1813 uint16_t *table_member; 1814 uint16_t temp_edge, temp_hotspot, temp_mem; 1815 1816 if (!range) 1817 return -EINVAL; 1818 1819 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range)); 1820 1821 GET_PPTABLE_MEMBER(TemperatureLimit, &table_member); 1822 temp_edge = table_member[TEMP_EDGE]; 1823 temp_hotspot = table_member[TEMP_HOTSPOT]; 1824 temp_mem = table_member[TEMP_MEM]; 1825 1826 range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1827 range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) * 1828 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1829 range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1830 range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) * 1831 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1832 range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1833 range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)* 1834 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1835 1836 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 1837 1838 return 0; 1839 } 1840 1841 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu, 1842 bool disable_memory_clock_switch) 1843 { 1844 int ret = 0; 1845 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks = 1846 (struct smu_11_0_max_sustainable_clocks *) 1847 smu->smu_table.max_sustainable_clocks; 1848 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal; 1849 uint32_t max_memory_clock = max_sustainable_clocks->uclock; 1850 1851 if(smu->disable_uclk_switch == disable_memory_clock_switch) 1852 return 0; 1853 1854 if(disable_memory_clock_switch) 1855 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0); 1856 else 1857 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0); 1858 1859 if(!ret) 1860 smu->disable_uclk_switch = disable_memory_clock_switch; 1861 1862 return ret; 1863 } 1864 1865 static int sienna_cichlid_get_power_limit(struct smu_context *smu, 1866 uint32_t *current_power_limit, 1867 uint32_t *default_power_limit, 1868 uint32_t *max_power_limit) 1869 { 1870 struct smu_11_0_7_powerplay_table *powerplay_table = 1871 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table; 1872 uint32_t power_limit, od_percent; 1873 uint16_t *table_member; 1874 1875 GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member); 1876 1877 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) { 1878 power_limit = 1879 table_member[PPT_THROTTLER_PPT0]; 1880 } 1881 1882 if (current_power_limit) 1883 *current_power_limit = power_limit; 1884 if (default_power_limit) 1885 *default_power_limit = power_limit; 1886 1887 if (max_power_limit) { 1888 if (smu->od_enabled) { 1889 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]); 1890 1891 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit); 1892 1893 power_limit *= (100 + od_percent); 1894 power_limit /= 100; 1895 } 1896 *max_power_limit = power_limit; 1897 } 1898 1899 return 0; 1900 } 1901 1902 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu, 1903 uint32_t pcie_gen_cap, 1904 uint32_t pcie_width_cap) 1905 { 1906 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 1907 1908 uint32_t smu_pcie_arg; 1909 uint8_t *table_member1, *table_member2; 1910 int ret, i; 1911 1912 GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1); 1913 GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2); 1914 1915 /* lclk dpm table setup */ 1916 for (i = 0; i < MAX_PCIE_CONF; i++) { 1917 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = table_member1[i]; 1918 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = table_member2[i]; 1919 } 1920 1921 for (i = 0; i < NUM_LINK_LEVELS; i++) { 1922 smu_pcie_arg = (i << 16) | 1923 ((table_member1[i] <= pcie_gen_cap) ? 1924 (table_member1[i] << 8) : 1925 (pcie_gen_cap << 8)) | 1926 ((table_member2[i] <= pcie_width_cap) ? 1927 table_member2[i] : 1928 pcie_width_cap); 1929 1930 ret = smu_cmn_send_smc_msg_with_param(smu, 1931 SMU_MSG_OverridePcieParameters, 1932 smu_pcie_arg, 1933 NULL); 1934 if (ret) 1935 return ret; 1936 1937 if (table_member1[i] > pcie_gen_cap) 1938 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap; 1939 if (table_member2[i] > pcie_width_cap) 1940 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap; 1941 } 1942 1943 return 0; 1944 } 1945 1946 static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu, 1947 enum smu_clk_type clk_type, 1948 uint32_t *min, uint32_t *max) 1949 { 1950 return smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max); 1951 } 1952 1953 static void sienna_cichlid_dump_od_table(struct smu_context *smu, 1954 OverDriveTable_t *od_table) 1955 { 1956 struct amdgpu_device *adev = smu->adev; 1957 uint32_t smu_version; 1958 1959 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, 1960 od_table->GfxclkFmax); 1961 dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin, 1962 od_table->UclkFmax); 1963 1964 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1965 if (!((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 1966 (smu_version < 0x003a2900))) 1967 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset); 1968 } 1969 1970 static int sienna_cichlid_set_default_od_settings(struct smu_context *smu) 1971 { 1972 OverDriveTable_t *od_table = 1973 (OverDriveTable_t *)smu->smu_table.overdrive_table; 1974 OverDriveTable_t *boot_od_table = 1975 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table; 1976 OverDriveTable_t *user_od_table = 1977 (OverDriveTable_t *)smu->smu_table.user_overdrive_table; 1978 int ret = 0; 1979 1980 /* 1981 * For S3/S4/Runpm resume, no need to setup those overdrive tables again as 1982 * - either they already have the default OD settings got during cold bootup 1983 * - or they have some user customized OD settings which cannot be overwritten 1984 */ 1985 if (smu->adev->in_suspend) 1986 return 0; 1987 1988 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 1989 0, (void *)boot_od_table, false); 1990 if (ret) { 1991 dev_err(smu->adev->dev, "Failed to get overdrive table!\n"); 1992 return ret; 1993 } 1994 1995 sienna_cichlid_dump_od_table(smu, boot_od_table); 1996 1997 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t)); 1998 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t)); 1999 2000 return 0; 2001 } 2002 2003 static int sienna_cichlid_od_setting_check_range(struct smu_context *smu, 2004 struct smu_11_0_7_overdrive_table *od_table, 2005 enum SMU_11_0_7_ODSETTING_ID setting, 2006 uint32_t value) 2007 { 2008 if (value < od_table->min[setting]) { 2009 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", 2010 setting, value, od_table->min[setting]); 2011 return -EINVAL; 2012 } 2013 if (value > od_table->max[setting]) { 2014 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", 2015 setting, value, od_table->max[setting]); 2016 return -EINVAL; 2017 } 2018 2019 return 0; 2020 } 2021 2022 static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu, 2023 enum PP_OD_DPM_TABLE_COMMAND type, 2024 long input[], uint32_t size) 2025 { 2026 struct smu_table_context *table_context = &smu->smu_table; 2027 OverDriveTable_t *od_table = 2028 (OverDriveTable_t *)table_context->overdrive_table; 2029 struct smu_11_0_7_overdrive_table *od_settings = 2030 (struct smu_11_0_7_overdrive_table *)smu->od_settings; 2031 struct amdgpu_device *adev = smu->adev; 2032 enum SMU_11_0_7_ODSETTING_ID freq_setting; 2033 uint16_t *freq_ptr; 2034 int i, ret = 0; 2035 uint32_t smu_version; 2036 2037 if (!smu->od_enabled) { 2038 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n"); 2039 return -EINVAL; 2040 } 2041 2042 if (!smu->od_settings) { 2043 dev_err(smu->adev->dev, "OD board limits are not set!\n"); 2044 return -ENOENT; 2045 } 2046 2047 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) { 2048 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n"); 2049 return -EINVAL; 2050 } 2051 2052 switch (type) { 2053 case PP_OD_EDIT_SCLK_VDDC_TABLE: 2054 if (!sienna_cichlid_is_od_feature_supported(od_settings, 2055 SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) { 2056 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n"); 2057 return -ENOTSUPP; 2058 } 2059 2060 for (i = 0; i < size; i += 2) { 2061 if (i + 2 > size) { 2062 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size); 2063 return -EINVAL; 2064 } 2065 2066 switch (input[i]) { 2067 case 0: 2068 if (input[i + 1] > od_table->GfxclkFmax) { 2069 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n", 2070 input[i + 1], od_table->GfxclkFmax); 2071 return -EINVAL; 2072 } 2073 2074 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN; 2075 freq_ptr = &od_table->GfxclkFmin; 2076 break; 2077 2078 case 1: 2079 if (input[i + 1] < od_table->GfxclkFmin) { 2080 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n", 2081 input[i + 1], od_table->GfxclkFmin); 2082 return -EINVAL; 2083 } 2084 2085 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX; 2086 freq_ptr = &od_table->GfxclkFmax; 2087 break; 2088 2089 default: 2090 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]); 2091 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n"); 2092 return -EINVAL; 2093 } 2094 2095 ret = sienna_cichlid_od_setting_check_range(smu, od_settings, 2096 freq_setting, input[i + 1]); 2097 if (ret) 2098 return ret; 2099 2100 *freq_ptr = (uint16_t)input[i + 1]; 2101 } 2102 break; 2103 2104 case PP_OD_EDIT_MCLK_VDDC_TABLE: 2105 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) { 2106 dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n"); 2107 return -ENOTSUPP; 2108 } 2109 2110 for (i = 0; i < size; i += 2) { 2111 if (i + 2 > size) { 2112 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size); 2113 return -EINVAL; 2114 } 2115 2116 switch (input[i]) { 2117 case 0: 2118 if (input[i + 1] > od_table->UclkFmax) { 2119 dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n", 2120 input[i + 1], od_table->UclkFmax); 2121 return -EINVAL; 2122 } 2123 2124 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN; 2125 freq_ptr = &od_table->UclkFmin; 2126 break; 2127 2128 case 1: 2129 if (input[i + 1] < od_table->UclkFmin) { 2130 dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n", 2131 input[i + 1], od_table->UclkFmin); 2132 return -EINVAL; 2133 } 2134 2135 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX; 2136 freq_ptr = &od_table->UclkFmax; 2137 break; 2138 2139 default: 2140 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]); 2141 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n"); 2142 return -EINVAL; 2143 } 2144 2145 ret = sienna_cichlid_od_setting_check_range(smu, od_settings, 2146 freq_setting, input[i + 1]); 2147 if (ret) 2148 return ret; 2149 2150 *freq_ptr = (uint16_t)input[i + 1]; 2151 } 2152 break; 2153 2154 case PP_OD_RESTORE_DEFAULT_TABLE: 2155 memcpy(table_context->overdrive_table, 2156 table_context->boot_overdrive_table, 2157 sizeof(OverDriveTable_t)); 2158 fallthrough; 2159 2160 case PP_OD_COMMIT_DPM_TABLE: 2161 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) { 2162 sienna_cichlid_dump_od_table(smu, od_table); 2163 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true); 2164 if (ret) { 2165 dev_err(smu->adev->dev, "Failed to import overdrive table!\n"); 2166 return ret; 2167 } 2168 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t)); 2169 smu->user_dpm_profile.user_od = true; 2170 2171 if (!memcmp(table_context->user_overdrive_table, 2172 table_context->boot_overdrive_table, 2173 sizeof(OverDriveTable_t))) 2174 smu->user_dpm_profile.user_od = false; 2175 } 2176 break; 2177 2178 case PP_OD_EDIT_VDDGFX_OFFSET: 2179 if (size != 1) { 2180 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size); 2181 return -EINVAL; 2182 } 2183 2184 /* 2185 * OD GFX Voltage Offset functionality is supported only by 58.41.0 2186 * and onwards SMU firmwares. 2187 */ 2188 smu_cmn_get_smc_version(smu, NULL, &smu_version); 2189 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 2190 (smu_version < 0x003a2900)) { 2191 dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported " 2192 "only by 58.41.0 and onwards SMU firmwares!\n"); 2193 return -EOPNOTSUPP; 2194 } 2195 2196 od_table->VddGfxOffset = (int16_t)input[0]; 2197 2198 sienna_cichlid_dump_od_table(smu, od_table); 2199 break; 2200 2201 default: 2202 return -ENOSYS; 2203 } 2204 2205 return ret; 2206 } 2207 2208 static int sienna_cichlid_run_btc(struct smu_context *smu) 2209 { 2210 int res; 2211 2212 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); 2213 if (res) 2214 dev_err(smu->adev->dev, "RunDcBtc failed!\n"); 2215 2216 return res; 2217 } 2218 2219 static int sienna_cichlid_baco_enter(struct smu_context *smu) 2220 { 2221 struct amdgpu_device *adev = smu->adev; 2222 2223 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) 2224 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO); 2225 else 2226 return smu_v11_0_baco_enter(smu); 2227 } 2228 2229 static int sienna_cichlid_baco_exit(struct smu_context *smu) 2230 { 2231 struct amdgpu_device *adev = smu->adev; 2232 2233 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) { 2234 /* Wait for PMFW handling for the Dstate change */ 2235 msleep(10); 2236 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS); 2237 } else { 2238 return smu_v11_0_baco_exit(smu); 2239 } 2240 } 2241 2242 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu) 2243 { 2244 struct amdgpu_device *adev = smu->adev; 2245 uint32_t val; 2246 u32 smu_version; 2247 2248 /** 2249 * SRIOV env will not support SMU mode1 reset 2250 * PM FW support mode1 reset from 58.26 2251 */ 2252 smu_cmn_get_smc_version(smu, NULL, &smu_version); 2253 if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00)) 2254 return false; 2255 2256 /** 2257 * mode1 reset relies on PSP, so we should check if 2258 * PSP is alive. 2259 */ 2260 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 2261 return val != 0x0; 2262 } 2263 2264 static void beige_goby_dump_pptable(struct smu_context *smu) 2265 { 2266 struct smu_table_context *table_context = &smu->smu_table; 2267 PPTable_beige_goby_t *pptable = table_context->driver_pptable; 2268 int i; 2269 2270 dev_info(smu->adev->dev, "Dumped PPTable:\n"); 2271 2272 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version); 2273 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]); 2274 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]); 2275 2276 for (i = 0; i < PPT_THROTTLER_COUNT; i++) { 2277 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]); 2278 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]); 2279 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]); 2280 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]); 2281 } 2282 2283 for (i = 0; i < TDC_THROTTLER_COUNT; i++) { 2284 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]); 2285 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]); 2286 } 2287 2288 for (i = 0; i < TEMP_COUNT; i++) { 2289 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]); 2290 } 2291 2292 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit); 2293 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig); 2294 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]); 2295 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]); 2296 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]); 2297 2298 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit); 2299 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) { 2300 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]); 2301 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]); 2302 } 2303 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask); 2304 2305 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask); 2306 2307 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc); 2308 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx); 2309 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx); 2310 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc); 2311 2312 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin); 2313 2314 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold); 2315 2316 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx); 2317 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc); 2318 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx); 2319 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc); 2320 2321 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx); 2322 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc); 2323 2324 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin); 2325 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin); 2326 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp); 2327 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp); 2328 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp); 2329 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp); 2330 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis); 2331 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis); 2332 2333 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n" 2334 " .VoltageMode = 0x%02x\n" 2335 " .SnapToDiscrete = 0x%02x\n" 2336 " .NumDiscreteLevels = 0x%02x\n" 2337 " .padding = 0x%02x\n" 2338 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2339 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2340 " .SsFmin = 0x%04x\n" 2341 " .Padding_16 = 0x%04x\n", 2342 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode, 2343 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete, 2344 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels, 2345 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding, 2346 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m, 2347 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b, 2348 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a, 2349 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b, 2350 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c, 2351 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin, 2352 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16); 2353 2354 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n" 2355 " .VoltageMode = 0x%02x\n" 2356 " .SnapToDiscrete = 0x%02x\n" 2357 " .NumDiscreteLevels = 0x%02x\n" 2358 " .padding = 0x%02x\n" 2359 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2360 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2361 " .SsFmin = 0x%04x\n" 2362 " .Padding_16 = 0x%04x\n", 2363 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode, 2364 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete, 2365 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels, 2366 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding, 2367 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m, 2368 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b, 2369 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a, 2370 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b, 2371 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c, 2372 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin, 2373 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16); 2374 2375 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n" 2376 " .VoltageMode = 0x%02x\n" 2377 " .SnapToDiscrete = 0x%02x\n" 2378 " .NumDiscreteLevels = 0x%02x\n" 2379 " .padding = 0x%02x\n" 2380 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2381 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2382 " .SsFmin = 0x%04x\n" 2383 " .Padding_16 = 0x%04x\n", 2384 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode, 2385 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete, 2386 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels, 2387 pptable->DpmDescriptor[PPCLK_UCLK].Padding, 2388 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m, 2389 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b, 2390 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a, 2391 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b, 2392 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c, 2393 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin, 2394 pptable->DpmDescriptor[PPCLK_UCLK].Padding16); 2395 2396 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n" 2397 " .VoltageMode = 0x%02x\n" 2398 " .SnapToDiscrete = 0x%02x\n" 2399 " .NumDiscreteLevels = 0x%02x\n" 2400 " .padding = 0x%02x\n" 2401 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2402 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2403 " .SsFmin = 0x%04x\n" 2404 " .Padding_16 = 0x%04x\n", 2405 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode, 2406 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete, 2407 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels, 2408 pptable->DpmDescriptor[PPCLK_FCLK].Padding, 2409 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m, 2410 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b, 2411 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a, 2412 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b, 2413 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c, 2414 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin, 2415 pptable->DpmDescriptor[PPCLK_FCLK].Padding16); 2416 2417 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n" 2418 " .VoltageMode = 0x%02x\n" 2419 " .SnapToDiscrete = 0x%02x\n" 2420 " .NumDiscreteLevels = 0x%02x\n" 2421 " .padding = 0x%02x\n" 2422 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2423 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2424 " .SsFmin = 0x%04x\n" 2425 " .Padding_16 = 0x%04x\n", 2426 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode, 2427 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete, 2428 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels, 2429 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding, 2430 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m, 2431 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b, 2432 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a, 2433 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b, 2434 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c, 2435 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin, 2436 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16); 2437 2438 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n" 2439 " .VoltageMode = 0x%02x\n" 2440 " .SnapToDiscrete = 0x%02x\n" 2441 " .NumDiscreteLevels = 0x%02x\n" 2442 " .padding = 0x%02x\n" 2443 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2444 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2445 " .SsFmin = 0x%04x\n" 2446 " .Padding_16 = 0x%04x\n", 2447 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode, 2448 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete, 2449 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels, 2450 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding, 2451 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m, 2452 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b, 2453 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a, 2454 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b, 2455 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c, 2456 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin, 2457 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16); 2458 2459 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n" 2460 " .VoltageMode = 0x%02x\n" 2461 " .SnapToDiscrete = 0x%02x\n" 2462 " .NumDiscreteLevels = 0x%02x\n" 2463 " .padding = 0x%02x\n" 2464 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2465 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2466 " .SsFmin = 0x%04x\n" 2467 " .Padding_16 = 0x%04x\n", 2468 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode, 2469 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete, 2470 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels, 2471 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding, 2472 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m, 2473 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b, 2474 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a, 2475 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b, 2476 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c, 2477 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin, 2478 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16); 2479 2480 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n" 2481 " .VoltageMode = 0x%02x\n" 2482 " .SnapToDiscrete = 0x%02x\n" 2483 " .NumDiscreteLevels = 0x%02x\n" 2484 " .padding = 0x%02x\n" 2485 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2486 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2487 " .SsFmin = 0x%04x\n" 2488 " .Padding_16 = 0x%04x\n", 2489 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode, 2490 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete, 2491 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels, 2492 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding, 2493 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m, 2494 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b, 2495 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a, 2496 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b, 2497 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c, 2498 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin, 2499 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16); 2500 2501 dev_info(smu->adev->dev, "FreqTableGfx\n"); 2502 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) 2503 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]); 2504 2505 dev_info(smu->adev->dev, "FreqTableVclk\n"); 2506 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++) 2507 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]); 2508 2509 dev_info(smu->adev->dev, "FreqTableDclk\n"); 2510 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++) 2511 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]); 2512 2513 dev_info(smu->adev->dev, "FreqTableSocclk\n"); 2514 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) 2515 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]); 2516 2517 dev_info(smu->adev->dev, "FreqTableUclk\n"); 2518 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2519 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]); 2520 2521 dev_info(smu->adev->dev, "FreqTableFclk\n"); 2522 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) 2523 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]); 2524 2525 dev_info(smu->adev->dev, "DcModeMaxFreq\n"); 2526 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]); 2527 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]); 2528 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]); 2529 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]); 2530 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]); 2531 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]); 2532 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]); 2533 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]); 2534 2535 dev_info(smu->adev->dev, "FreqTableUclkDiv\n"); 2536 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2537 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]); 2538 2539 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq); 2540 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding); 2541 2542 dev_info(smu->adev->dev, "Mp0clkFreq\n"); 2543 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 2544 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]); 2545 2546 dev_info(smu->adev->dev, "Mp0DpmVoltage\n"); 2547 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 2548 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]); 2549 2550 dev_info(smu->adev->dev, "MemVddciVoltage\n"); 2551 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2552 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]); 2553 2554 dev_info(smu->adev->dev, "MemMvddVoltage\n"); 2555 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2556 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]); 2557 2558 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry); 2559 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit); 2560 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle); 2561 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource); 2562 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding); 2563 2564 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask); 2565 2566 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask); 2567 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask); 2568 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]); 2569 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow); 2570 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]); 2571 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]); 2572 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]); 2573 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]); 2574 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt); 2575 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt); 2576 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt); 2577 2578 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage); 2579 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime); 2580 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime); 2581 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum); 2582 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis); 2583 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout); 2584 2585 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]); 2586 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]); 2587 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]); 2588 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]); 2589 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]); 2590 2591 dev_info(smu->adev->dev, "FlopsPerByteTable\n"); 2592 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++) 2593 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]); 2594 2595 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv); 2596 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]); 2597 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]); 2598 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]); 2599 2600 dev_info(smu->adev->dev, "UclkDpmPstates\n"); 2601 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2602 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]); 2603 2604 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n"); 2605 dev_info(smu->adev->dev, " .Fmin = 0x%x\n", 2606 pptable->UclkDpmSrcFreqRange.Fmin); 2607 dev_info(smu->adev->dev, " .Fmax = 0x%x\n", 2608 pptable->UclkDpmSrcFreqRange.Fmax); 2609 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n"); 2610 dev_info(smu->adev->dev, " .Fmin = 0x%x\n", 2611 pptable->UclkDpmTargFreqRange.Fmin); 2612 dev_info(smu->adev->dev, " .Fmax = 0x%x\n", 2613 pptable->UclkDpmTargFreqRange.Fmax); 2614 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq); 2615 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding); 2616 2617 dev_info(smu->adev->dev, "PcieGenSpeed\n"); 2618 for (i = 0; i < NUM_LINK_LEVELS; i++) 2619 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]); 2620 2621 dev_info(smu->adev->dev, "PcieLaneCount\n"); 2622 for (i = 0; i < NUM_LINK_LEVELS; i++) 2623 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]); 2624 2625 dev_info(smu->adev->dev, "LclkFreq\n"); 2626 for (i = 0; i < NUM_LINK_LEVELS; i++) 2627 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]); 2628 2629 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp); 2630 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp); 2631 2632 dev_info(smu->adev->dev, "FanGain\n"); 2633 for (i = 0; i < TEMP_COUNT; i++) 2634 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]); 2635 2636 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin); 2637 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm); 2638 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm); 2639 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm); 2640 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm); 2641 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature); 2642 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk); 2643 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16); 2644 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect); 2645 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding); 2646 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable); 2647 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev); 2648 2649 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta); 2650 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta); 2651 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta); 2652 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved); 2653 2654 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]); 2655 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]); 2656 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect); 2657 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs); 2658 2659 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", 2660 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a, 2661 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b, 2662 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c); 2663 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", 2664 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a, 2665 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b, 2666 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c); 2667 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n", 2668 pptable->dBtcGbGfxPll.a, 2669 pptable->dBtcGbGfxPll.b, 2670 pptable->dBtcGbGfxPll.c); 2671 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n", 2672 pptable->dBtcGbGfxDfll.a, 2673 pptable->dBtcGbGfxDfll.b, 2674 pptable->dBtcGbGfxDfll.c); 2675 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n", 2676 pptable->dBtcGbSoc.a, 2677 pptable->dBtcGbSoc.b, 2678 pptable->dBtcGbSoc.c); 2679 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n", 2680 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m, 2681 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b); 2682 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n", 2683 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m, 2684 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b); 2685 2686 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n"); 2687 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) { 2688 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n", 2689 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]); 2690 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n", 2691 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]); 2692 } 2693 2694 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", 2695 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a, 2696 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b, 2697 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c); 2698 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", 2699 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a, 2700 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b, 2701 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c); 2702 2703 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]); 2704 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]); 2705 2706 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]); 2707 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]); 2708 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]); 2709 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]); 2710 2711 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]); 2712 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]); 2713 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]); 2714 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]); 2715 2716 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]); 2717 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]); 2718 2719 dev_info(smu->adev->dev, "XgmiDpmPstates\n"); 2720 for (i = 0; i < NUM_XGMI_LEVELS; i++) 2721 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]); 2722 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]); 2723 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]); 2724 2725 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides); 2726 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n", 2727 pptable->ReservedEquation0.a, 2728 pptable->ReservedEquation0.b, 2729 pptable->ReservedEquation0.c); 2730 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n", 2731 pptable->ReservedEquation1.a, 2732 pptable->ReservedEquation1.b, 2733 pptable->ReservedEquation1.c); 2734 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n", 2735 pptable->ReservedEquation2.a, 2736 pptable->ReservedEquation2.b, 2737 pptable->ReservedEquation2.c); 2738 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n", 2739 pptable->ReservedEquation3.a, 2740 pptable->ReservedEquation3.b, 2741 pptable->ReservedEquation3.c); 2742 2743 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]); 2744 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]); 2745 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]); 2746 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]); 2747 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]); 2748 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]); 2749 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]); 2750 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]); 2751 2752 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]); 2753 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]); 2754 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]); 2755 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]); 2756 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]); 2757 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]); 2758 2759 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) { 2760 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i); 2761 dev_info(smu->adev->dev, " .Enabled = 0x%x\n", 2762 pptable->I2cControllers[i].Enabled); 2763 dev_info(smu->adev->dev, " .Speed = 0x%x\n", 2764 pptable->I2cControllers[i].Speed); 2765 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n", 2766 pptable->I2cControllers[i].SlaveAddress); 2767 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n", 2768 pptable->I2cControllers[i].ControllerPort); 2769 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n", 2770 pptable->I2cControllers[i].ControllerName); 2771 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n", 2772 pptable->I2cControllers[i].ThermalThrotter); 2773 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n", 2774 pptable->I2cControllers[i].I2cProtocol); 2775 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n", 2776 pptable->I2cControllers[i].PaddingConfig); 2777 } 2778 2779 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl); 2780 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda); 2781 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr); 2782 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]); 2783 2784 dev_info(smu->adev->dev, "Board Parameters:\n"); 2785 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping); 2786 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping); 2787 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping); 2788 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping); 2789 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask); 2790 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask); 2791 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask); 2792 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask); 2793 2794 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent); 2795 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset); 2796 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx); 2797 2798 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent); 2799 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset); 2800 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc); 2801 2802 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent); 2803 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset); 2804 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0); 2805 2806 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent); 2807 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset); 2808 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1); 2809 2810 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio); 2811 2812 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio); 2813 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity); 2814 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio); 2815 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity); 2816 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio); 2817 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity); 2818 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio); 2819 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity); 2820 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0); 2821 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1); 2822 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2); 2823 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask); 2824 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie); 2825 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError); 2826 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]); 2827 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]); 2828 2829 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled); 2830 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent); 2831 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq); 2832 2833 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled); 2834 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent); 2835 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq); 2836 2837 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding); 2838 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq); 2839 2840 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled); 2841 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent); 2842 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq); 2843 2844 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled); 2845 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth); 2846 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]); 2847 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]); 2848 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]); 2849 2850 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower); 2851 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding); 2852 2853 dev_info(smu->adev->dev, "XgmiLinkSpeed\n"); 2854 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 2855 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]); 2856 dev_info(smu->adev->dev, "XgmiLinkWidth\n"); 2857 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 2858 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]); 2859 dev_info(smu->adev->dev, "XgmiFclkFreq\n"); 2860 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 2861 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]); 2862 dev_info(smu->adev->dev, "XgmiSocVoltage\n"); 2863 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 2864 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]); 2865 2866 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled); 2867 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled); 2868 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]); 2869 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]); 2870 2871 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]); 2872 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]); 2873 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]); 2874 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]); 2875 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]); 2876 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]); 2877 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]); 2878 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]); 2879 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]); 2880 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]); 2881 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]); 2882 2883 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]); 2884 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]); 2885 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]); 2886 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]); 2887 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]); 2888 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]); 2889 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]); 2890 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]); 2891 } 2892 2893 static void sienna_cichlid_dump_pptable(struct smu_context *smu) 2894 { 2895 struct smu_table_context *table_context = &smu->smu_table; 2896 PPTable_t *pptable = table_context->driver_pptable; 2897 int i; 2898 2899 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) { 2900 beige_goby_dump_pptable(smu); 2901 return; 2902 } 2903 2904 dev_info(smu->adev->dev, "Dumped PPTable:\n"); 2905 2906 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version); 2907 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]); 2908 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]); 2909 2910 for (i = 0; i < PPT_THROTTLER_COUNT; i++) { 2911 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]); 2912 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]); 2913 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]); 2914 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]); 2915 } 2916 2917 for (i = 0; i < TDC_THROTTLER_COUNT; i++) { 2918 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]); 2919 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]); 2920 } 2921 2922 for (i = 0; i < TEMP_COUNT; i++) { 2923 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]); 2924 } 2925 2926 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit); 2927 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig); 2928 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]); 2929 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]); 2930 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]); 2931 2932 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit); 2933 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) { 2934 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]); 2935 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]); 2936 } 2937 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask); 2938 2939 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask); 2940 2941 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc); 2942 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx); 2943 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx); 2944 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc); 2945 2946 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin); 2947 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin); 2948 2949 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold); 2950 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]); 2951 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]); 2952 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]); 2953 2954 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx); 2955 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc); 2956 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx); 2957 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc); 2958 2959 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx); 2960 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc); 2961 2962 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin); 2963 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin); 2964 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp); 2965 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp); 2966 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp); 2967 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp); 2968 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis); 2969 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis); 2970 2971 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n" 2972 " .VoltageMode = 0x%02x\n" 2973 " .SnapToDiscrete = 0x%02x\n" 2974 " .NumDiscreteLevels = 0x%02x\n" 2975 " .padding = 0x%02x\n" 2976 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2977 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2978 " .SsFmin = 0x%04x\n" 2979 " .Padding_16 = 0x%04x\n", 2980 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode, 2981 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete, 2982 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels, 2983 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding, 2984 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m, 2985 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b, 2986 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a, 2987 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b, 2988 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c, 2989 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin, 2990 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16); 2991 2992 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n" 2993 " .VoltageMode = 0x%02x\n" 2994 " .SnapToDiscrete = 0x%02x\n" 2995 " .NumDiscreteLevels = 0x%02x\n" 2996 " .padding = 0x%02x\n" 2997 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2998 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2999 " .SsFmin = 0x%04x\n" 3000 " .Padding_16 = 0x%04x\n", 3001 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode, 3002 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete, 3003 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels, 3004 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding, 3005 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m, 3006 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b, 3007 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a, 3008 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b, 3009 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c, 3010 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin, 3011 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16); 3012 3013 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n" 3014 " .VoltageMode = 0x%02x\n" 3015 " .SnapToDiscrete = 0x%02x\n" 3016 " .NumDiscreteLevels = 0x%02x\n" 3017 " .padding = 0x%02x\n" 3018 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3019 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3020 " .SsFmin = 0x%04x\n" 3021 " .Padding_16 = 0x%04x\n", 3022 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode, 3023 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete, 3024 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels, 3025 pptable->DpmDescriptor[PPCLK_UCLK].Padding, 3026 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m, 3027 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b, 3028 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a, 3029 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b, 3030 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c, 3031 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin, 3032 pptable->DpmDescriptor[PPCLK_UCLK].Padding16); 3033 3034 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n" 3035 " .VoltageMode = 0x%02x\n" 3036 " .SnapToDiscrete = 0x%02x\n" 3037 " .NumDiscreteLevels = 0x%02x\n" 3038 " .padding = 0x%02x\n" 3039 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3040 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3041 " .SsFmin = 0x%04x\n" 3042 " .Padding_16 = 0x%04x\n", 3043 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode, 3044 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete, 3045 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels, 3046 pptable->DpmDescriptor[PPCLK_FCLK].Padding, 3047 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m, 3048 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b, 3049 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a, 3050 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b, 3051 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c, 3052 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin, 3053 pptable->DpmDescriptor[PPCLK_FCLK].Padding16); 3054 3055 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n" 3056 " .VoltageMode = 0x%02x\n" 3057 " .SnapToDiscrete = 0x%02x\n" 3058 " .NumDiscreteLevels = 0x%02x\n" 3059 " .padding = 0x%02x\n" 3060 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3061 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3062 " .SsFmin = 0x%04x\n" 3063 " .Padding_16 = 0x%04x\n", 3064 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode, 3065 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete, 3066 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels, 3067 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding, 3068 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m, 3069 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b, 3070 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a, 3071 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b, 3072 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c, 3073 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin, 3074 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16); 3075 3076 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n" 3077 " .VoltageMode = 0x%02x\n" 3078 " .SnapToDiscrete = 0x%02x\n" 3079 " .NumDiscreteLevels = 0x%02x\n" 3080 " .padding = 0x%02x\n" 3081 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3082 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3083 " .SsFmin = 0x%04x\n" 3084 " .Padding_16 = 0x%04x\n", 3085 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode, 3086 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete, 3087 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels, 3088 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding, 3089 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m, 3090 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b, 3091 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a, 3092 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b, 3093 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c, 3094 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin, 3095 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16); 3096 3097 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n" 3098 " .VoltageMode = 0x%02x\n" 3099 " .SnapToDiscrete = 0x%02x\n" 3100 " .NumDiscreteLevels = 0x%02x\n" 3101 " .padding = 0x%02x\n" 3102 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3103 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3104 " .SsFmin = 0x%04x\n" 3105 " .Padding_16 = 0x%04x\n", 3106 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode, 3107 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete, 3108 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels, 3109 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding, 3110 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m, 3111 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b, 3112 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a, 3113 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b, 3114 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c, 3115 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin, 3116 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16); 3117 3118 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n" 3119 " .VoltageMode = 0x%02x\n" 3120 " .SnapToDiscrete = 0x%02x\n" 3121 " .NumDiscreteLevels = 0x%02x\n" 3122 " .padding = 0x%02x\n" 3123 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3124 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3125 " .SsFmin = 0x%04x\n" 3126 " .Padding_16 = 0x%04x\n", 3127 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode, 3128 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete, 3129 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels, 3130 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding, 3131 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m, 3132 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b, 3133 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a, 3134 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b, 3135 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c, 3136 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin, 3137 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16); 3138 3139 dev_info(smu->adev->dev, "FreqTableGfx\n"); 3140 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) 3141 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]); 3142 3143 dev_info(smu->adev->dev, "FreqTableVclk\n"); 3144 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++) 3145 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]); 3146 3147 dev_info(smu->adev->dev, "FreqTableDclk\n"); 3148 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++) 3149 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]); 3150 3151 dev_info(smu->adev->dev, "FreqTableSocclk\n"); 3152 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) 3153 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]); 3154 3155 dev_info(smu->adev->dev, "FreqTableUclk\n"); 3156 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 3157 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]); 3158 3159 dev_info(smu->adev->dev, "FreqTableFclk\n"); 3160 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) 3161 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]); 3162 3163 dev_info(smu->adev->dev, "DcModeMaxFreq\n"); 3164 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]); 3165 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]); 3166 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]); 3167 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]); 3168 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]); 3169 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]); 3170 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]); 3171 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]); 3172 3173 dev_info(smu->adev->dev, "FreqTableUclkDiv\n"); 3174 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 3175 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]); 3176 3177 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq); 3178 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding); 3179 3180 dev_info(smu->adev->dev, "Mp0clkFreq\n"); 3181 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 3182 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]); 3183 3184 dev_info(smu->adev->dev, "Mp0DpmVoltage\n"); 3185 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 3186 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]); 3187 3188 dev_info(smu->adev->dev, "MemVddciVoltage\n"); 3189 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 3190 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]); 3191 3192 dev_info(smu->adev->dev, "MemMvddVoltage\n"); 3193 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 3194 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]); 3195 3196 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry); 3197 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit); 3198 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle); 3199 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource); 3200 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding); 3201 3202 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask); 3203 3204 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask); 3205 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask); 3206 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]); 3207 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow); 3208 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]); 3209 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]); 3210 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]); 3211 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]); 3212 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt); 3213 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt); 3214 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt); 3215 3216 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage); 3217 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime); 3218 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime); 3219 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum); 3220 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis); 3221 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout); 3222 3223 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]); 3224 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]); 3225 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]); 3226 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]); 3227 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]); 3228 3229 dev_info(smu->adev->dev, "FlopsPerByteTable\n"); 3230 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++) 3231 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]); 3232 3233 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv); 3234 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]); 3235 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]); 3236 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]); 3237 3238 dev_info(smu->adev->dev, "UclkDpmPstates\n"); 3239 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 3240 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]); 3241 3242 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n"); 3243 dev_info(smu->adev->dev, " .Fmin = 0x%x\n", 3244 pptable->UclkDpmSrcFreqRange.Fmin); 3245 dev_info(smu->adev->dev, " .Fmax = 0x%x\n", 3246 pptable->UclkDpmSrcFreqRange.Fmax); 3247 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n"); 3248 dev_info(smu->adev->dev, " .Fmin = 0x%x\n", 3249 pptable->UclkDpmTargFreqRange.Fmin); 3250 dev_info(smu->adev->dev, " .Fmax = 0x%x\n", 3251 pptable->UclkDpmTargFreqRange.Fmax); 3252 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq); 3253 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding); 3254 3255 dev_info(smu->adev->dev, "PcieGenSpeed\n"); 3256 for (i = 0; i < NUM_LINK_LEVELS; i++) 3257 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]); 3258 3259 dev_info(smu->adev->dev, "PcieLaneCount\n"); 3260 for (i = 0; i < NUM_LINK_LEVELS; i++) 3261 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]); 3262 3263 dev_info(smu->adev->dev, "LclkFreq\n"); 3264 for (i = 0; i < NUM_LINK_LEVELS; i++) 3265 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]); 3266 3267 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp); 3268 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp); 3269 3270 dev_info(smu->adev->dev, "FanGain\n"); 3271 for (i = 0; i < TEMP_COUNT; i++) 3272 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]); 3273 3274 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin); 3275 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm); 3276 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm); 3277 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm); 3278 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm); 3279 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature); 3280 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk); 3281 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16); 3282 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect); 3283 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding); 3284 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable); 3285 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev); 3286 3287 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta); 3288 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta); 3289 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta); 3290 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved); 3291 3292 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]); 3293 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]); 3294 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect); 3295 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs); 3296 3297 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", 3298 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a, 3299 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b, 3300 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c); 3301 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", 3302 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a, 3303 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b, 3304 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c); 3305 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n", 3306 pptable->dBtcGbGfxPll.a, 3307 pptable->dBtcGbGfxPll.b, 3308 pptable->dBtcGbGfxPll.c); 3309 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n", 3310 pptable->dBtcGbGfxDfll.a, 3311 pptable->dBtcGbGfxDfll.b, 3312 pptable->dBtcGbGfxDfll.c); 3313 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n", 3314 pptable->dBtcGbSoc.a, 3315 pptable->dBtcGbSoc.b, 3316 pptable->dBtcGbSoc.c); 3317 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n", 3318 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m, 3319 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b); 3320 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n", 3321 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m, 3322 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b); 3323 3324 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n"); 3325 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) { 3326 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n", 3327 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]); 3328 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n", 3329 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]); 3330 } 3331 3332 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", 3333 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a, 3334 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b, 3335 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c); 3336 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", 3337 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a, 3338 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b, 3339 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c); 3340 3341 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]); 3342 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]); 3343 3344 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]); 3345 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]); 3346 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]); 3347 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]); 3348 3349 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]); 3350 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]); 3351 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]); 3352 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]); 3353 3354 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]); 3355 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]); 3356 3357 dev_info(smu->adev->dev, "XgmiDpmPstates\n"); 3358 for (i = 0; i < NUM_XGMI_LEVELS; i++) 3359 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]); 3360 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]); 3361 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]); 3362 3363 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides); 3364 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n", 3365 pptable->ReservedEquation0.a, 3366 pptable->ReservedEquation0.b, 3367 pptable->ReservedEquation0.c); 3368 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n", 3369 pptable->ReservedEquation1.a, 3370 pptable->ReservedEquation1.b, 3371 pptable->ReservedEquation1.c); 3372 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n", 3373 pptable->ReservedEquation2.a, 3374 pptable->ReservedEquation2.b, 3375 pptable->ReservedEquation2.c); 3376 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n", 3377 pptable->ReservedEquation3.a, 3378 pptable->ReservedEquation3.b, 3379 pptable->ReservedEquation3.c); 3380 3381 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]); 3382 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]); 3383 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]); 3384 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]); 3385 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]); 3386 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]); 3387 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]); 3388 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]); 3389 3390 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]); 3391 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]); 3392 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]); 3393 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]); 3394 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]); 3395 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]); 3396 3397 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) { 3398 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i); 3399 dev_info(smu->adev->dev, " .Enabled = 0x%x\n", 3400 pptable->I2cControllers[i].Enabled); 3401 dev_info(smu->adev->dev, " .Speed = 0x%x\n", 3402 pptable->I2cControllers[i].Speed); 3403 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n", 3404 pptable->I2cControllers[i].SlaveAddress); 3405 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n", 3406 pptable->I2cControllers[i].ControllerPort); 3407 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n", 3408 pptable->I2cControllers[i].ControllerName); 3409 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n", 3410 pptable->I2cControllers[i].ThermalThrotter); 3411 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n", 3412 pptable->I2cControllers[i].I2cProtocol); 3413 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n", 3414 pptable->I2cControllers[i].PaddingConfig); 3415 } 3416 3417 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl); 3418 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda); 3419 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr); 3420 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]); 3421 3422 dev_info(smu->adev->dev, "Board Parameters:\n"); 3423 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping); 3424 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping); 3425 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping); 3426 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping); 3427 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask); 3428 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask); 3429 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask); 3430 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask); 3431 3432 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent); 3433 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset); 3434 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx); 3435 3436 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent); 3437 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset); 3438 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc); 3439 3440 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent); 3441 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset); 3442 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0); 3443 3444 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent); 3445 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset); 3446 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1); 3447 3448 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio); 3449 3450 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio); 3451 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity); 3452 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio); 3453 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity); 3454 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio); 3455 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity); 3456 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio); 3457 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity); 3458 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0); 3459 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1); 3460 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2); 3461 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask); 3462 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie); 3463 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError); 3464 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]); 3465 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]); 3466 3467 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled); 3468 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent); 3469 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq); 3470 3471 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled); 3472 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent); 3473 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq); 3474 3475 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding); 3476 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq); 3477 3478 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled); 3479 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent); 3480 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq); 3481 3482 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled); 3483 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth); 3484 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]); 3485 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]); 3486 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]); 3487 3488 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower); 3489 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding); 3490 3491 dev_info(smu->adev->dev, "XgmiLinkSpeed\n"); 3492 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3493 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]); 3494 dev_info(smu->adev->dev, "XgmiLinkWidth\n"); 3495 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3496 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]); 3497 dev_info(smu->adev->dev, "XgmiFclkFreq\n"); 3498 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3499 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]); 3500 dev_info(smu->adev->dev, "XgmiSocVoltage\n"); 3501 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3502 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]); 3503 3504 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled); 3505 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled); 3506 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]); 3507 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]); 3508 3509 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]); 3510 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]); 3511 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]); 3512 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]); 3513 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]); 3514 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]); 3515 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]); 3516 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]); 3517 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]); 3518 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]); 3519 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]); 3520 3521 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]); 3522 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]); 3523 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]); 3524 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]); 3525 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]); 3526 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]); 3527 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]); 3528 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]); 3529 } 3530 3531 static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap, 3532 struct i2c_msg *msg, int num_msgs) 3533 { 3534 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap); 3535 struct amdgpu_device *adev = smu_i2c->adev; 3536 struct smu_context *smu = adev->powerplay.pp_handle; 3537 struct smu_table_context *smu_table = &smu->smu_table; 3538 struct smu_table *table = &smu_table->driver_table; 3539 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 3540 int i, j, r, c; 3541 u16 dir; 3542 3543 if (!adev->pm.dpm_enabled) 3544 return -EBUSY; 3545 3546 req = kzalloc(sizeof(*req), GFP_KERNEL); 3547 if (!req) 3548 return -ENOMEM; 3549 3550 req->I2CcontrollerPort = smu_i2c->port; 3551 req->I2CSpeed = I2C_SPEED_FAST_400K; 3552 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 3553 dir = msg[0].flags & I2C_M_RD; 3554 3555 for (c = i = 0; i < num_msgs; i++) { 3556 for (j = 0; j < msg[i].len; j++, c++) { 3557 SwI2cCmd_t *cmd = &req->SwI2cCmds[c]; 3558 3559 if (!(msg[i].flags & I2C_M_RD)) { 3560 /* write */ 3561 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK; 3562 cmd->ReadWriteData = msg[i].buf[j]; 3563 } 3564 3565 if ((dir ^ msg[i].flags) & I2C_M_RD) { 3566 /* The direction changes. 3567 */ 3568 dir = msg[i].flags & I2C_M_RD; 3569 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK; 3570 } 3571 3572 req->NumCmds++; 3573 3574 /* 3575 * Insert STOP if we are at the last byte of either last 3576 * message for the transaction or the client explicitly 3577 * requires a STOP at this particular message. 3578 */ 3579 if ((j == msg[i].len - 1) && 3580 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) { 3581 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK; 3582 cmd->CmdConfig |= CMDCONFIG_STOP_MASK; 3583 } 3584 } 3585 } 3586 mutex_lock(&adev->pm.mutex); 3587 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 3588 mutex_unlock(&adev->pm.mutex); 3589 if (r) 3590 goto fail; 3591 3592 for (c = i = 0; i < num_msgs; i++) { 3593 if (!(msg[i].flags & I2C_M_RD)) { 3594 c += msg[i].len; 3595 continue; 3596 } 3597 for (j = 0; j < msg[i].len; j++, c++) { 3598 SwI2cCmd_t *cmd = &res->SwI2cCmds[c]; 3599 3600 msg[i].buf[j] = cmd->ReadWriteData; 3601 } 3602 } 3603 r = num_msgs; 3604 fail: 3605 kfree(req); 3606 return r; 3607 } 3608 3609 static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap) 3610 { 3611 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 3612 } 3613 3614 3615 static const struct i2c_algorithm sienna_cichlid_i2c_algo = { 3616 .master_xfer = sienna_cichlid_i2c_xfer, 3617 .functionality = sienna_cichlid_i2c_func, 3618 }; 3619 3620 static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = { 3621 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN, 3622 .max_read_len = MAX_SW_I2C_COMMANDS, 3623 .max_write_len = MAX_SW_I2C_COMMANDS, 3624 .max_comb_1st_msg_len = 2, 3625 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 3626 }; 3627 3628 static int sienna_cichlid_i2c_control_init(struct smu_context *smu) 3629 { 3630 struct amdgpu_device *adev = smu->adev; 3631 int res, i; 3632 3633 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 3634 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 3635 struct i2c_adapter *control = &smu_i2c->adapter; 3636 3637 smu_i2c->adev = adev; 3638 smu_i2c->port = i; 3639 mutex_init(&smu_i2c->mutex); 3640 control->owner = THIS_MODULE; 3641 control->class = I2C_CLASS_HWMON; 3642 control->dev.parent = &adev->pdev->dev; 3643 control->algo = &sienna_cichlid_i2c_algo; 3644 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i); 3645 control->quirks = &sienna_cichlid_i2c_control_quirks; 3646 i2c_set_adapdata(control, smu_i2c); 3647 3648 res = i2c_add_adapter(control); 3649 if (res) { 3650 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 3651 goto Out_err; 3652 } 3653 } 3654 /* assign the buses used for the FRU EEPROM and RAS EEPROM */ 3655 /* XXX ideally this would be something in a vbios data table */ 3656 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter; 3657 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 3658 3659 return 0; 3660 Out_err: 3661 for ( ; i >= 0; i--) { 3662 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 3663 struct i2c_adapter *control = &smu_i2c->adapter; 3664 3665 i2c_del_adapter(control); 3666 } 3667 return res; 3668 } 3669 3670 static void sienna_cichlid_i2c_control_fini(struct smu_context *smu) 3671 { 3672 struct amdgpu_device *adev = smu->adev; 3673 int i; 3674 3675 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 3676 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 3677 struct i2c_adapter *control = &smu_i2c->adapter; 3678 3679 i2c_del_adapter(control); 3680 } 3681 adev->pm.ras_eeprom_i2c_bus = NULL; 3682 adev->pm.fru_eeprom_i2c_bus = NULL; 3683 } 3684 3685 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu, 3686 void **table) 3687 { 3688 struct smu_table_context *smu_table = &smu->smu_table; 3689 struct gpu_metrics_v1_3 *gpu_metrics = 3690 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 3691 SmuMetricsExternal_t metrics_external; 3692 SmuMetrics_t *metrics = 3693 &(metrics_external.SmuMetrics); 3694 SmuMetrics_V2_t *metrics_v2 = 3695 &(metrics_external.SmuMetrics_V2); 3696 SmuMetrics_V3_t *metrics_v3 = 3697 &(metrics_external.SmuMetrics_V3); 3698 struct amdgpu_device *adev = smu->adev; 3699 bool use_metrics_v2 = false; 3700 bool use_metrics_v3 = false; 3701 uint16_t average_gfx_activity; 3702 int ret = 0; 3703 3704 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 3705 (smu->smc_fw_version >= 0x3A4900)) 3706 use_metrics_v3 = true; 3707 else if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 3708 (smu->smc_fw_version >= 0x3A4300)) 3709 use_metrics_v2 = true; 3710 3711 3712 ret = smu_cmn_get_metrics_table(smu, 3713 &metrics_external, 3714 true); 3715 if (ret) 3716 return ret; 3717 3718 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 3719 3720 gpu_metrics->temperature_edge = use_metrics_v3 ? metrics_v3->TemperatureEdge : 3721 use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge; 3722 gpu_metrics->temperature_hotspot = use_metrics_v3 ? metrics_v3->TemperatureHotspot : 3723 use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot; 3724 gpu_metrics->temperature_mem = use_metrics_v3 ? metrics_v3->TemperatureMem : 3725 use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem; 3726 gpu_metrics->temperature_vrgfx = use_metrics_v3 ? metrics_v3->TemperatureVrGfx : 3727 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx; 3728 gpu_metrics->temperature_vrsoc = use_metrics_v3 ? metrics_v3->TemperatureVrSoc : 3729 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc; 3730 gpu_metrics->temperature_vrmem = use_metrics_v3 ? metrics_v3->TemperatureVrMem0 : 3731 use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0; 3732 3733 gpu_metrics->average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity : 3734 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity; 3735 gpu_metrics->average_umc_activity = use_metrics_v3 ? metrics_v3->AverageUclkActivity : 3736 use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity; 3737 gpu_metrics->average_mm_activity = use_metrics_v3 ? 3738 (metrics_v3->VcnUsagePercentage0 + metrics_v3->VcnUsagePercentage1) / 2 : 3739 use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage; 3740 3741 gpu_metrics->average_socket_power = use_metrics_v3 ? metrics_v3->AverageSocketPower : 3742 use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower; 3743 gpu_metrics->energy_accumulator = use_metrics_v3 ? metrics_v3->EnergyAccumulator : 3744 use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator; 3745 3746 if (metrics->CurrGfxVoltageOffset) 3747 gpu_metrics->voltage_gfx = 3748 (155000 - 625 * metrics->CurrGfxVoltageOffset) / 100; 3749 if (metrics->CurrMemVidOffset) 3750 gpu_metrics->voltage_mem = 3751 (155000 - 625 * metrics->CurrMemVidOffset) / 100; 3752 if (metrics->CurrSocVoltageOffset) 3753 gpu_metrics->voltage_soc = 3754 (155000 - 625 * metrics->CurrSocVoltageOffset) / 100; 3755 3756 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity : 3757 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity; 3758 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD) 3759 gpu_metrics->average_gfxclk_frequency = 3760 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs : 3761 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs : 3762 metrics->AverageGfxclkFrequencyPostDs; 3763 else 3764 gpu_metrics->average_gfxclk_frequency = 3765 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs : 3766 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs : 3767 metrics->AverageGfxclkFrequencyPreDs; 3768 3769 gpu_metrics->average_uclk_frequency = 3770 use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs : 3771 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs : 3772 metrics->AverageUclkFrequencyPostDs; 3773 gpu_metrics->average_vclk0_frequency = use_metrics_v3 ? metrics_v3->AverageVclk0Frequency : 3774 use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency; 3775 gpu_metrics->average_dclk0_frequency = use_metrics_v3 ? metrics_v3->AverageDclk0Frequency : 3776 use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency; 3777 gpu_metrics->average_vclk1_frequency = use_metrics_v3 ? metrics_v3->AverageVclk1Frequency : 3778 use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency; 3779 gpu_metrics->average_dclk1_frequency = use_metrics_v3 ? metrics_v3->AverageDclk1Frequency : 3780 use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency; 3781 3782 gpu_metrics->current_gfxclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] : 3783 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK]; 3784 gpu_metrics->current_socclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] : 3785 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK]; 3786 gpu_metrics->current_uclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] : 3787 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK]; 3788 gpu_metrics->current_vclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] : 3789 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0]; 3790 gpu_metrics->current_dclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] : 3791 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0]; 3792 gpu_metrics->current_vclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] : 3793 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1]; 3794 gpu_metrics->current_dclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] : 3795 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1]; 3796 3797 gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu); 3798 gpu_metrics->indep_throttle_status = 3799 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status, 3800 sienna_cichlid_throttler_map); 3801 3802 gpu_metrics->current_fan_speed = use_metrics_v3 ? metrics_v3->CurrFanSpeed : 3803 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed; 3804 3805 if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) || 3806 ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) { 3807 gpu_metrics->pcie_link_width = use_metrics_v3 ? metrics_v3->PcieWidth : 3808 use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth; 3809 gpu_metrics->pcie_link_speed = link_speed[use_metrics_v3 ? metrics_v3->PcieRate : 3810 use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate]; 3811 } else { 3812 gpu_metrics->pcie_link_width = 3813 smu_v11_0_get_current_pcie_link_width(smu); 3814 gpu_metrics->pcie_link_speed = 3815 smu_v11_0_get_current_pcie_link_speed(smu); 3816 } 3817 3818 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 3819 3820 *table = (void *)gpu_metrics; 3821 3822 return sizeof(struct gpu_metrics_v1_3); 3823 } 3824 3825 static int sienna_cichlid_check_ecc_table_support(struct smu_context *smu) 3826 { 3827 uint32_t if_version = 0xff, smu_version = 0xff; 3828 int ret = 0; 3829 3830 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 3831 if (ret) 3832 return -EOPNOTSUPP; 3833 3834 if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION) 3835 ret = -EOPNOTSUPP; 3836 3837 return ret; 3838 } 3839 3840 static ssize_t sienna_cichlid_get_ecc_info(struct smu_context *smu, 3841 void *table) 3842 { 3843 struct smu_table_context *smu_table = &smu->smu_table; 3844 EccInfoTable_t *ecc_table = NULL; 3845 struct ecc_info_per_ch *ecc_info_per_channel = NULL; 3846 int i, ret = 0; 3847 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table; 3848 3849 ret = sienna_cichlid_check_ecc_table_support(smu); 3850 if (ret) 3851 return ret; 3852 3853 ret = smu_cmn_update_table(smu, 3854 SMU_TABLE_ECCINFO, 3855 0, 3856 smu_table->ecc_table, 3857 false); 3858 if (ret) { 3859 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n"); 3860 return ret; 3861 } 3862 3863 ecc_table = (EccInfoTable_t *)smu_table->ecc_table; 3864 3865 for (i = 0; i < SIENNA_CICHLID_UMC_CHANNEL_NUM; i++) { 3866 ecc_info_per_channel = &(eccinfo->ecc[i]); 3867 ecc_info_per_channel->ce_count_lo_chip = 3868 ecc_table->EccInfo[i].ce_count_lo_chip; 3869 ecc_info_per_channel->ce_count_hi_chip = 3870 ecc_table->EccInfo[i].ce_count_hi_chip; 3871 ecc_info_per_channel->mca_umc_status = 3872 ecc_table->EccInfo[i].mca_umc_status; 3873 ecc_info_per_channel->mca_umc_addr = 3874 ecc_table->EccInfo[i].mca_umc_addr; 3875 } 3876 3877 return ret; 3878 } 3879 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu) 3880 { 3881 uint16_t *mgpu_fan_boost_limit_rpm; 3882 3883 GET_PPTABLE_MEMBER(MGpuFanBoostLimitRpm, &mgpu_fan_boost_limit_rpm); 3884 /* 3885 * Skip the MGpuFanBoost setting for those ASICs 3886 * which do not support it 3887 */ 3888 if (*mgpu_fan_boost_limit_rpm == 0) 3889 return 0; 3890 3891 return smu_cmn_send_smc_msg_with_param(smu, 3892 SMU_MSG_SetMGpuFanBoostLimitRpm, 3893 0, 3894 NULL); 3895 } 3896 3897 static int sienna_cichlid_gpo_control(struct smu_context *smu, 3898 bool enablement) 3899 { 3900 uint32_t smu_version; 3901 int ret = 0; 3902 3903 3904 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) { 3905 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 3906 if (ret) 3907 return ret; 3908 3909 if (enablement) { 3910 if (smu_version < 0x003a2500) { 3911 ret = smu_cmn_send_smc_msg_with_param(smu, 3912 SMU_MSG_SetGpoFeaturePMask, 3913 GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK, 3914 NULL); 3915 } else { 3916 ret = smu_cmn_send_smc_msg_with_param(smu, 3917 SMU_MSG_DisallowGpo, 3918 0, 3919 NULL); 3920 } 3921 } else { 3922 if (smu_version < 0x003a2500) { 3923 ret = smu_cmn_send_smc_msg_with_param(smu, 3924 SMU_MSG_SetGpoFeaturePMask, 3925 0, 3926 NULL); 3927 } else { 3928 ret = smu_cmn_send_smc_msg_with_param(smu, 3929 SMU_MSG_DisallowGpo, 3930 1, 3931 NULL); 3932 } 3933 } 3934 } 3935 3936 return ret; 3937 } 3938 3939 static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu) 3940 { 3941 uint32_t smu_version; 3942 int ret = 0; 3943 3944 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 3945 if (ret) 3946 return ret; 3947 3948 /* 3949 * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45 3950 * onwards PMFWs. 3951 */ 3952 if (smu_version < 0x003A2D00) 3953 return 0; 3954 3955 return smu_cmn_send_smc_msg_with_param(smu, 3956 SMU_MSG_Enable2ndUSB20Port, 3957 smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ? 3958 1 : 0, 3959 NULL); 3960 } 3961 3962 static int sienna_cichlid_system_features_control(struct smu_context *smu, 3963 bool en) 3964 { 3965 int ret = 0; 3966 3967 if (en) { 3968 ret = sienna_cichlid_notify_2nd_usb20_port(smu); 3969 if (ret) 3970 return ret; 3971 } 3972 3973 return smu_v11_0_system_features_control(smu, en); 3974 } 3975 3976 static int sienna_cichlid_set_mp1_state(struct smu_context *smu, 3977 enum pp_mp1_state mp1_state) 3978 { 3979 int ret; 3980 3981 switch (mp1_state) { 3982 case PP_MP1_STATE_UNLOAD: 3983 ret = smu_cmn_set_mp1_state(smu, mp1_state); 3984 break; 3985 default: 3986 /* Ignore others */ 3987 ret = 0; 3988 } 3989 3990 return ret; 3991 } 3992 3993 static void sienna_cichlid_stb_init(struct smu_context *smu) 3994 { 3995 struct amdgpu_device *adev = smu->adev; 3996 uint32_t reg; 3997 3998 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_START); 3999 smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE); 4000 4001 /* STB is disabled */ 4002 if (!smu->stb_context.enabled) 4003 return; 4004 4005 spin_lock_init(&smu->stb_context.lock); 4006 4007 /* STB buffer size in bytes as function of FIFO depth */ 4008 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_FIFO); 4009 smu->stb_context.stb_buf_size = 1 << REG_GET_FIELD(reg, MP1_PMI_3_FIFO, DEPTH); 4010 smu->stb_context.stb_buf_size *= SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES; 4011 4012 dev_info(smu->adev->dev, "STB initialized to %d entries", 4013 smu->stb_context.stb_buf_size / SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES); 4014 4015 } 4016 4017 static int sienna_cichlid_get_default_config_table_settings(struct smu_context *smu, 4018 struct config_table_setting *table) 4019 { 4020 struct amdgpu_device *adev = smu->adev; 4021 4022 if (!table) 4023 return -EINVAL; 4024 4025 table->gfxclk_average_tau = 10; 4026 table->socclk_average_tau = 10; 4027 table->fclk_average_tau = 10; 4028 table->uclk_average_tau = 10; 4029 table->gfx_activity_average_tau = 10; 4030 table->mem_activity_average_tau = 10; 4031 table->socket_power_average_tau = 100; 4032 if (adev->asic_type != CHIP_SIENNA_CICHLID) 4033 table->apu_socket_power_average_tau = 100; 4034 4035 return 0; 4036 } 4037 4038 static int sienna_cichlid_set_config_table(struct smu_context *smu, 4039 struct config_table_setting *table) 4040 { 4041 DriverSmuConfigExternal_t driver_smu_config_table; 4042 4043 if (!table) 4044 return -EINVAL; 4045 4046 memset(&driver_smu_config_table, 4047 0, 4048 sizeof(driver_smu_config_table)); 4049 driver_smu_config_table.DriverSmuConfig.GfxclkAverageLpfTau = 4050 table->gfxclk_average_tau; 4051 driver_smu_config_table.DriverSmuConfig.FclkAverageLpfTau = 4052 table->fclk_average_tau; 4053 driver_smu_config_table.DriverSmuConfig.UclkAverageLpfTau = 4054 table->uclk_average_tau; 4055 driver_smu_config_table.DriverSmuConfig.GfxActivityLpfTau = 4056 table->gfx_activity_average_tau; 4057 driver_smu_config_table.DriverSmuConfig.UclkActivityLpfTau = 4058 table->mem_activity_average_tau; 4059 driver_smu_config_table.DriverSmuConfig.SocketPowerLpfTau = 4060 table->socket_power_average_tau; 4061 4062 return smu_cmn_update_table(smu, 4063 SMU_TABLE_DRIVER_SMU_CONFIG, 4064 0, 4065 (void *)&driver_smu_config_table, 4066 true); 4067 } 4068 4069 static int sienna_cichlid_stb_get_data_direct(struct smu_context *smu, 4070 void *buf, 4071 uint32_t size) 4072 { 4073 uint32_t *p = buf; 4074 struct amdgpu_device *adev = smu->adev; 4075 4076 /* No need to disable interrupts for now as we don't lock it yet from ISR */ 4077 spin_lock(&smu->stb_context.lock); 4078 4079 /* 4080 * Read the STB FIFO in units of 32bit since this is the accessor window 4081 * (register width) we have. 4082 */ 4083 buf = ((char *) buf) + size; 4084 while ((void *)p < buf) 4085 *p++ = cpu_to_le32(RREG32_PCIE(MP1_Public | smnMP1_PMI_3)); 4086 4087 spin_unlock(&smu->stb_context.lock); 4088 4089 return 0; 4090 } 4091 4092 static const struct pptable_funcs sienna_cichlid_ppt_funcs = { 4093 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask, 4094 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table, 4095 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable, 4096 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable, 4097 .i2c_init = sienna_cichlid_i2c_control_init, 4098 .i2c_fini = sienna_cichlid_i2c_control_fini, 4099 .print_clk_levels = sienna_cichlid_print_clk_levels, 4100 .force_clk_levels = sienna_cichlid_force_clk_levels, 4101 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk, 4102 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed, 4103 .display_config_changed = sienna_cichlid_display_config_changed, 4104 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config, 4105 .is_dpm_running = sienna_cichlid_is_dpm_running, 4106 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm, 4107 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm, 4108 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode, 4109 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode, 4110 .set_watermarks_table = sienna_cichlid_set_watermarks_table, 4111 .read_sensor = sienna_cichlid_read_sensor, 4112 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states, 4113 .set_performance_level = smu_v11_0_set_performance_level, 4114 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range, 4115 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch, 4116 .get_power_limit = sienna_cichlid_get_power_limit, 4117 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters, 4118 .dump_pptable = sienna_cichlid_dump_pptable, 4119 .init_microcode = smu_v11_0_init_microcode, 4120 .load_microcode = smu_v11_0_load_microcode, 4121 .init_smc_tables = sienna_cichlid_init_smc_tables, 4122 .fini_smc_tables = smu_v11_0_fini_smc_tables, 4123 .init_power = smu_v11_0_init_power, 4124 .fini_power = smu_v11_0_fini_power, 4125 .check_fw_status = smu_v11_0_check_fw_status, 4126 .setup_pptable = sienna_cichlid_setup_pptable, 4127 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, 4128 .check_fw_version = smu_v11_0_check_fw_version, 4129 .write_pptable = smu_cmn_write_pptable, 4130 .set_driver_table_location = smu_v11_0_set_driver_table_location, 4131 .set_tool_table_location = smu_v11_0_set_tool_table_location, 4132 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 4133 .system_features_control = sienna_cichlid_system_features_control, 4134 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 4135 .send_smc_msg = smu_cmn_send_smc_msg, 4136 .init_display_count = NULL, 4137 .set_allowed_mask = smu_v11_0_set_allowed_mask, 4138 .get_enabled_mask = smu_cmn_get_enabled_mask, 4139 .feature_is_enabled = smu_cmn_feature_is_enabled, 4140 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 4141 .notify_display_change = NULL, 4142 .set_power_limit = smu_v11_0_set_power_limit, 4143 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks, 4144 .enable_thermal_alert = smu_v11_0_enable_thermal_alert, 4145 .disable_thermal_alert = smu_v11_0_disable_thermal_alert, 4146 .set_min_dcef_deep_sleep = NULL, 4147 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request, 4148 .get_fan_control_mode = smu_v11_0_get_fan_control_mode, 4149 .set_fan_control_mode = smu_v11_0_set_fan_control_mode, 4150 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm, 4151 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm, 4152 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate, 4153 .gfx_off_control = smu_v11_0_gfx_off_control, 4154 .register_irq_handler = smu_v11_0_register_irq_handler, 4155 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme, 4156 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc, 4157 .baco_is_support = smu_v11_0_baco_is_support, 4158 .baco_get_state = smu_v11_0_baco_get_state, 4159 .baco_set_state = smu_v11_0_baco_set_state, 4160 .baco_enter = sienna_cichlid_baco_enter, 4161 .baco_exit = sienna_cichlid_baco_exit, 4162 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported, 4163 .mode1_reset = smu_v11_0_mode1_reset, 4164 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq, 4165 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, 4166 .set_default_od_settings = sienna_cichlid_set_default_od_settings, 4167 .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table, 4168 .restore_user_od_settings = smu_v11_0_restore_user_od_settings, 4169 .run_btc = sienna_cichlid_run_btc, 4170 .set_power_source = smu_v11_0_set_power_source, 4171 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 4172 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 4173 .get_gpu_metrics = sienna_cichlid_get_gpu_metrics, 4174 .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost, 4175 .gfx_ulv_control = smu_v11_0_gfx_ulv_control, 4176 .deep_sleep_control = smu_v11_0_deep_sleep_control, 4177 .get_fan_parameters = sienna_cichlid_get_fan_parameters, 4178 .interrupt_work = smu_v11_0_interrupt_work, 4179 .gpo_control = sienna_cichlid_gpo_control, 4180 .set_mp1_state = sienna_cichlid_set_mp1_state, 4181 .stb_collect_info = sienna_cichlid_stb_get_data_direct, 4182 .get_ecc_info = sienna_cichlid_get_ecc_info, 4183 .get_default_config_table_settings = sienna_cichlid_get_default_config_table_settings, 4184 .set_config_table = sienna_cichlid_set_config_table, 4185 }; 4186 4187 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu) 4188 { 4189 smu->ppt_funcs = &sienna_cichlid_ppt_funcs; 4190 smu->message_map = sienna_cichlid_message_map; 4191 smu->clock_map = sienna_cichlid_clk_map; 4192 smu->feature_map = sienna_cichlid_feature_mask_map; 4193 smu->table_map = sienna_cichlid_table_map; 4194 smu->pwr_src_map = sienna_cichlid_pwr_src_map; 4195 smu->workload_map = sienna_cichlid_workload_map; 4196 } 4197