1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include <linux/pci.h> 28 #include <linux/i2c.h> 29 #include "amdgpu.h" 30 #include "amdgpu_smu.h" 31 #include "atomfirmware.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "amdgpu_atombios.h" 34 #include "smu_v11_0.h" 35 #include "smu11_driver_if_sienna_cichlid.h" 36 #include "soc15_common.h" 37 #include "atom.h" 38 #include "sienna_cichlid_ppt.h" 39 #include "smu_v11_0_7_pptable.h" 40 #include "smu_v11_0_7_ppsmc.h" 41 #include "nbio/nbio_2_3_offset.h" 42 #include "nbio/nbio_2_3_sh_mask.h" 43 #include "thm/thm_11_0_2_offset.h" 44 #include "thm/thm_11_0_2_sh_mask.h" 45 #include "mp/mp_11_0_offset.h" 46 #include "mp/mp_11_0_sh_mask.h" 47 48 #include "asic_reg/mp/mp_11_0_sh_mask.h" 49 #include "smu_cmn.h" 50 51 /* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56 #undef pr_err 57 #undef pr_warn 58 #undef pr_info 59 #undef pr_debug 60 61 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 62 63 #define FEATURE_MASK(feature) (1ULL << feature) 64 #define SMC_DPM_FEATURE ( \ 65 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \ 66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \ 72 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)) 73 74 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15 75 76 #define GET_PPTABLE_MEMBER(field, member) do {\ 77 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))\ 78 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\ 79 else\ 80 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\ 81 } while(0) 82 83 static int get_table_size(struct smu_context *smu) 84 { 85 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) 86 return sizeof(PPTable_beige_goby_t); 87 else 88 return sizeof(PPTable_t); 89 } 90 91 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = { 92 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 93 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 94 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 95 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0), 96 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), 97 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 98 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 99 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1), 100 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1), 101 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1), 102 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1), 103 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1), 104 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1), 105 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 106 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 107 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 108 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 109 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 110 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 111 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 112 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 113 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 114 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 115 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), 116 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1), 117 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), 118 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1), 119 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 120 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), 121 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), 122 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 123 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0), 124 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0), 125 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0), 126 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0), 127 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0), 128 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0), 129 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0), 130 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0), 131 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1), 132 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 133 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 134 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 135 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1), 136 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0), 137 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 138 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 139 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 140 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 141 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0), 142 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0), 143 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0), 144 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0), 145 MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0), 146 MSG_MAP(DisallowGpo, PPSMC_MSG_DisallowGpo, 0), 147 MSG_MAP(Enable2ndUSB20Port, PPSMC_MSG_Enable2ndUSB20Port, 0), 148 }; 149 150 static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = { 151 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 152 CLK_MAP(SCLK, PPCLK_GFXCLK), 153 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 154 CLK_MAP(FCLK, PPCLK_FCLK), 155 CLK_MAP(UCLK, PPCLK_UCLK), 156 CLK_MAP(MCLK, PPCLK_UCLK), 157 CLK_MAP(DCLK, PPCLK_DCLK_0), 158 CLK_MAP(DCLK1, PPCLK_DCLK_1), 159 CLK_MAP(VCLK, PPCLK_VCLK_0), 160 CLK_MAP(VCLK1, PPCLK_VCLK_1), 161 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK), 162 CLK_MAP(DISPCLK, PPCLK_DISPCLK), 163 CLK_MAP(PIXCLK, PPCLK_PIXCLK), 164 CLK_MAP(PHYCLK, PPCLK_PHYCLK), 165 }; 166 167 static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = { 168 FEA_MAP(DPM_PREFETCHER), 169 FEA_MAP(DPM_GFXCLK), 170 FEA_MAP(DPM_GFX_GPO), 171 FEA_MAP(DPM_UCLK), 172 FEA_MAP(DPM_FCLK), 173 FEA_MAP(DPM_SOCCLK), 174 FEA_MAP(DPM_MP0CLK), 175 FEA_MAP(DPM_LINK), 176 FEA_MAP(DPM_DCEFCLK), 177 FEA_MAP(DPM_XGMI), 178 FEA_MAP(MEM_VDDCI_SCALING), 179 FEA_MAP(MEM_MVDD_SCALING), 180 FEA_MAP(DS_GFXCLK), 181 FEA_MAP(DS_SOCCLK), 182 FEA_MAP(DS_FCLK), 183 FEA_MAP(DS_LCLK), 184 FEA_MAP(DS_DCEFCLK), 185 FEA_MAP(DS_UCLK), 186 FEA_MAP(GFX_ULV), 187 FEA_MAP(FW_DSTATE), 188 FEA_MAP(GFXOFF), 189 FEA_MAP(BACO), 190 FEA_MAP(MM_DPM_PG), 191 FEA_MAP(RSMU_SMN_CG), 192 FEA_MAP(PPT), 193 FEA_MAP(TDC), 194 FEA_MAP(APCC_PLUS), 195 FEA_MAP(GTHR), 196 FEA_MAP(ACDC), 197 FEA_MAP(VR0HOT), 198 FEA_MAP(VR1HOT), 199 FEA_MAP(FW_CTF), 200 FEA_MAP(FAN_CONTROL), 201 FEA_MAP(THERMAL), 202 FEA_MAP(GFX_DCS), 203 FEA_MAP(RM), 204 FEA_MAP(LED_DISPLAY), 205 FEA_MAP(GFX_SS), 206 FEA_MAP(OUT_OF_BAND_MONITOR), 207 FEA_MAP(TEMP_DEPENDENT_VMIN), 208 FEA_MAP(MMHUB_PG), 209 FEA_MAP(ATHUB_PG), 210 FEA_MAP(APCC_DFLL), 211 }; 212 213 static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = { 214 TAB_MAP(PPTABLE), 215 TAB_MAP(WATERMARKS), 216 TAB_MAP(AVFS_PSM_DEBUG), 217 TAB_MAP(AVFS_FUSE_OVERRIDE), 218 TAB_MAP(PMSTATUSLOG), 219 TAB_MAP(SMU_METRICS), 220 TAB_MAP(DRIVER_SMU_CONFIG), 221 TAB_MAP(ACTIVITY_MONITOR_COEFF), 222 TAB_MAP(OVERDRIVE), 223 TAB_MAP(I2C_COMMANDS), 224 TAB_MAP(PACE), 225 }; 226 227 static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { 228 PWR_MAP(AC), 229 PWR_MAP(DC), 230 }; 231 232 static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 233 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), 234 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 235 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 236 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 237 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 238 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 239 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 240 }; 241 242 static const uint8_t sienna_cichlid_throttler_map[] = { 243 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT), 244 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT), 245 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 246 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 247 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 248 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT), 249 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 250 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT), 251 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT), 252 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 253 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 254 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 255 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 256 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT), 257 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT), 258 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), 259 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT), 260 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT), 261 }; 262 263 static int 264 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, 265 uint32_t *feature_mask, uint32_t num) 266 { 267 struct amdgpu_device *adev = smu->adev; 268 269 if (num > 2) 270 return -EINVAL; 271 272 memset(feature_mask, 0, sizeof(uint32_t) * num); 273 274 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) 275 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT) 276 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) 277 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) 278 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) 279 | FEATURE_MASK(FEATURE_DS_FCLK_BIT) 280 | FEATURE_MASK(FEATURE_DS_UCLK_BIT) 281 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) 282 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT) 283 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) 284 | FEATURE_MASK(FEATURE_GFX_SS_BIT) 285 | FEATURE_MASK(FEATURE_VR0HOT_BIT) 286 | FEATURE_MASK(FEATURE_PPT_BIT) 287 | FEATURE_MASK(FEATURE_TDC_BIT) 288 | FEATURE_MASK(FEATURE_BACO_BIT) 289 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) 290 | FEATURE_MASK(FEATURE_FW_CTF_BIT) 291 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) 292 | FEATURE_MASK(FEATURE_THERMAL_BIT) 293 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT); 294 295 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { 296 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 297 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT); 298 } 299 300 if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) && 301 (adev->ip_versions[MP1_HWIP][0] > IP_VERSION(11, 0, 7)) && 302 !(adev->flags & AMD_IS_APU)) 303 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT); 304 305 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) 306 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) 307 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) 308 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); 309 310 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) 311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); 312 313 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) 314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); 315 316 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) 317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 318 319 if (adev->pm.pp_feature & PP_ULV_MASK) 320 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); 321 322 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) 323 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 324 325 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 326 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); 327 328 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB) 329 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT); 330 331 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) 332 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); 333 334 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN || 335 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG) 336 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT); 337 338 if (smu->dc_controlled_by_gpio) 339 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT); 340 341 if (amdgpu_aspm) 342 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT); 343 344 return 0; 345 } 346 347 static void sienna_cichlid_check_bxco_support(struct smu_context *smu) 348 { 349 struct smu_table_context *table_context = &smu->smu_table; 350 struct smu_11_0_7_powerplay_table *powerplay_table = 351 table_context->power_play_table; 352 struct smu_baco_context *smu_baco = &smu->smu_baco; 353 struct amdgpu_device *adev = smu->adev; 354 uint32_t val; 355 356 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) { 357 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); 358 smu_baco->platform_support = 359 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : 360 false; 361 } 362 } 363 364 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu) 365 { 366 struct smu_table_context *table_context = &smu->smu_table; 367 struct smu_11_0_7_powerplay_table *powerplay_table = 368 table_context->power_play_table; 369 370 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC) 371 smu->dc_controlled_by_gpio = true; 372 373 sienna_cichlid_check_bxco_support(smu); 374 375 table_context->thermal_controller_type = 376 powerplay_table->thermal_controller_type; 377 378 /* 379 * Instead of having its own buffer space and get overdrive_table copied, 380 * smu->od_settings just points to the actual overdrive_table 381 */ 382 smu->od_settings = &powerplay_table->overdrive_table; 383 384 return 0; 385 } 386 387 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu) 388 { 389 struct atom_smc_dpm_info_v4_9 *smc_dpm_table; 390 int index, ret; 391 I2cControllerConfig_t *table_member; 392 393 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 394 smc_dpm_info); 395 396 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 397 (uint8_t **)&smc_dpm_table); 398 if (ret) 399 return ret; 400 GET_PPTABLE_MEMBER(I2cControllers, &table_member); 401 memcpy(table_member, smc_dpm_table->I2cControllers, 402 sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header)); 403 404 return 0; 405 } 406 407 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu) 408 { 409 struct smu_table_context *table_context = &smu->smu_table; 410 struct smu_11_0_7_powerplay_table *powerplay_table = 411 table_context->power_play_table; 412 int table_size; 413 414 table_size = get_table_size(smu); 415 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 416 table_size); 417 418 return 0; 419 } 420 421 static int sienna_cichlid_setup_pptable(struct smu_context *smu) 422 { 423 int ret = 0; 424 425 ret = smu_v11_0_setup_pptable(smu); 426 if (ret) 427 return ret; 428 429 ret = sienna_cichlid_store_powerplay_table(smu); 430 if (ret) 431 return ret; 432 433 ret = sienna_cichlid_append_powerplay_table(smu); 434 if (ret) 435 return ret; 436 437 ret = sienna_cichlid_check_powerplay_table(smu); 438 if (ret) 439 return ret; 440 441 return ret; 442 } 443 444 static int sienna_cichlid_tables_init(struct smu_context *smu) 445 { 446 struct smu_table_context *smu_table = &smu->smu_table; 447 struct smu_table *tables = smu_table->tables; 448 int table_size; 449 450 table_size = get_table_size(smu); 451 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size, 452 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 453 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 454 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 455 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t), 456 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 457 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 458 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 459 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t), 460 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 461 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 462 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 463 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, 464 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE, 465 AMDGPU_GEM_DOMAIN_VRAM); 466 467 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL); 468 if (!smu_table->metrics_table) 469 goto err0_out; 470 smu_table->metrics_time = 0; 471 472 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 473 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 474 if (!smu_table->gpu_metrics_table) 475 goto err1_out; 476 477 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 478 if (!smu_table->watermarks_table) 479 goto err2_out; 480 481 return 0; 482 483 err2_out: 484 kfree(smu_table->gpu_metrics_table); 485 err1_out: 486 kfree(smu_table->metrics_table); 487 err0_out: 488 return -ENOMEM; 489 } 490 491 static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu) 492 { 493 struct smu_table_context *smu_table= &smu->smu_table; 494 SmuMetricsExternal_t *metrics_ext = 495 (SmuMetricsExternal_t *)(smu_table->metrics_table); 496 uint32_t throttler_status = 0; 497 int i; 498 499 if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 500 (smu->smc_fw_version >= 0x3A4300)) { 501 for (i = 0; i < THROTTLER_COUNT; i++) 502 throttler_status |= 503 (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0); 504 } else { 505 throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus; 506 } 507 508 return throttler_status; 509 } 510 511 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu, 512 MetricsMember_t member, 513 uint32_t *value) 514 { 515 struct smu_table_context *smu_table= &smu->smu_table; 516 SmuMetrics_t *metrics = 517 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics); 518 SmuMetrics_V2_t *metrics_v2 = 519 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2); 520 bool use_metrics_v2 = ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 521 (smu->smc_fw_version >= 0x3A4300)) ? true : false; 522 uint16_t average_gfx_activity; 523 int ret = 0; 524 525 mutex_lock(&smu->metrics_lock); 526 527 ret = smu_cmn_get_metrics_table_locked(smu, 528 NULL, 529 false); 530 if (ret) { 531 mutex_unlock(&smu->metrics_lock); 532 return ret; 533 } 534 535 switch (member) { 536 case METRICS_CURR_GFXCLK: 537 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : 538 metrics->CurrClock[PPCLK_GFXCLK]; 539 break; 540 case METRICS_CURR_SOCCLK: 541 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : 542 metrics->CurrClock[PPCLK_SOCCLK]; 543 break; 544 case METRICS_CURR_UCLK: 545 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : 546 metrics->CurrClock[PPCLK_UCLK]; 547 break; 548 case METRICS_CURR_VCLK: 549 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : 550 metrics->CurrClock[PPCLK_VCLK_0]; 551 break; 552 case METRICS_CURR_VCLK1: 553 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : 554 metrics->CurrClock[PPCLK_VCLK_1]; 555 break; 556 case METRICS_CURR_DCLK: 557 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : 558 metrics->CurrClock[PPCLK_DCLK_0]; 559 break; 560 case METRICS_CURR_DCLK1: 561 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : 562 metrics->CurrClock[PPCLK_DCLK_1]; 563 break; 564 case METRICS_CURR_DCEFCLK: 565 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] : 566 metrics->CurrClock[PPCLK_DCEFCLK]; 567 break; 568 case METRICS_CURR_FCLK: 569 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] : 570 metrics->CurrClock[PPCLK_FCLK]; 571 break; 572 case METRICS_AVERAGE_GFXCLK: 573 average_gfx_activity = use_metrics_v2 ? metrics_v2->AverageGfxActivity : 574 metrics->AverageGfxActivity; 575 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD) 576 *value = use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs : 577 metrics->AverageGfxclkFrequencyPostDs; 578 else 579 *value = use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs : 580 metrics->AverageGfxclkFrequencyPreDs; 581 break; 582 case METRICS_AVERAGE_FCLK: 583 *value = use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs : 584 metrics->AverageFclkFrequencyPostDs; 585 break; 586 case METRICS_AVERAGE_UCLK: 587 *value = use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs : 588 metrics->AverageUclkFrequencyPostDs; 589 break; 590 case METRICS_AVERAGE_GFXACTIVITY: 591 *value = use_metrics_v2 ? metrics_v2->AverageGfxActivity : 592 metrics->AverageGfxActivity; 593 break; 594 case METRICS_AVERAGE_MEMACTIVITY: 595 *value = use_metrics_v2 ? metrics_v2->AverageUclkActivity : 596 metrics->AverageUclkActivity; 597 break; 598 case METRICS_AVERAGE_SOCKETPOWER: 599 *value = use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 : 600 metrics->AverageSocketPower << 8; 601 break; 602 case METRICS_TEMPERATURE_EDGE: 603 *value = (use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge) * 604 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 605 break; 606 case METRICS_TEMPERATURE_HOTSPOT: 607 *value = (use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot) * 608 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 609 break; 610 case METRICS_TEMPERATURE_MEM: 611 *value = (use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem) * 612 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 613 break; 614 case METRICS_TEMPERATURE_VRGFX: 615 *value = (use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx) * 616 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 617 break; 618 case METRICS_TEMPERATURE_VRSOC: 619 *value = (use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc) * 620 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 621 break; 622 case METRICS_THROTTLER_STATUS: 623 *value = sienna_cichlid_get_throttler_status_locked(smu); 624 break; 625 case METRICS_CURR_FANSPEED: 626 *value = use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed; 627 break; 628 default: 629 *value = UINT_MAX; 630 break; 631 } 632 633 mutex_unlock(&smu->metrics_lock); 634 635 return ret; 636 637 } 638 639 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu) 640 { 641 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 642 643 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 644 GFP_KERNEL); 645 if (!smu_dpm->dpm_context) 646 return -ENOMEM; 647 648 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 649 650 return 0; 651 } 652 653 static int sienna_cichlid_init_smc_tables(struct smu_context *smu) 654 { 655 int ret = 0; 656 657 ret = sienna_cichlid_tables_init(smu); 658 if (ret) 659 return ret; 660 661 ret = sienna_cichlid_allocate_dpm_context(smu); 662 if (ret) 663 return ret; 664 665 return smu_v11_0_init_smc_tables(smu); 666 } 667 668 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) 669 { 670 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 671 struct smu_11_0_dpm_table *dpm_table; 672 struct amdgpu_device *adev = smu->adev; 673 int i, ret = 0; 674 DpmDescriptor_t *table_member; 675 676 /* socclk dpm table setup */ 677 dpm_table = &dpm_context->dpm_tables.soc_table; 678 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member); 679 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 680 ret = smu_v11_0_set_single_dpm_table(smu, 681 SMU_SOCCLK, 682 dpm_table); 683 if (ret) 684 return ret; 685 dpm_table->is_fine_grained = 686 !table_member[PPCLK_SOCCLK].SnapToDiscrete; 687 } else { 688 dpm_table->count = 1; 689 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 690 dpm_table->dpm_levels[0].enabled = true; 691 dpm_table->min = dpm_table->dpm_levels[0].value; 692 dpm_table->max = dpm_table->dpm_levels[0].value; 693 } 694 695 /* gfxclk dpm table setup */ 696 dpm_table = &dpm_context->dpm_tables.gfx_table; 697 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 698 ret = smu_v11_0_set_single_dpm_table(smu, 699 SMU_GFXCLK, 700 dpm_table); 701 if (ret) 702 return ret; 703 dpm_table->is_fine_grained = 704 !table_member[PPCLK_GFXCLK].SnapToDiscrete; 705 } else { 706 dpm_table->count = 1; 707 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 708 dpm_table->dpm_levels[0].enabled = true; 709 dpm_table->min = dpm_table->dpm_levels[0].value; 710 dpm_table->max = dpm_table->dpm_levels[0].value; 711 } 712 713 /* uclk dpm table setup */ 714 dpm_table = &dpm_context->dpm_tables.uclk_table; 715 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 716 ret = smu_v11_0_set_single_dpm_table(smu, 717 SMU_UCLK, 718 dpm_table); 719 if (ret) 720 return ret; 721 dpm_table->is_fine_grained = 722 !table_member[PPCLK_UCLK].SnapToDiscrete; 723 } else { 724 dpm_table->count = 1; 725 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 726 dpm_table->dpm_levels[0].enabled = true; 727 dpm_table->min = dpm_table->dpm_levels[0].value; 728 dpm_table->max = dpm_table->dpm_levels[0].value; 729 } 730 731 /* fclk dpm table setup */ 732 dpm_table = &dpm_context->dpm_tables.fclk_table; 733 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 734 ret = smu_v11_0_set_single_dpm_table(smu, 735 SMU_FCLK, 736 dpm_table); 737 if (ret) 738 return ret; 739 dpm_table->is_fine_grained = 740 !table_member[PPCLK_FCLK].SnapToDiscrete; 741 } else { 742 dpm_table->count = 1; 743 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 744 dpm_table->dpm_levels[0].enabled = true; 745 dpm_table->min = dpm_table->dpm_levels[0].value; 746 dpm_table->max = dpm_table->dpm_levels[0].value; 747 } 748 749 /* vclk0/1 dpm table setup */ 750 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 751 if (adev->vcn.harvest_config & (1 << i)) 752 continue; 753 754 dpm_table = &dpm_context->dpm_tables.vclk_table; 755 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 756 ret = smu_v11_0_set_single_dpm_table(smu, 757 i ? SMU_VCLK1 : SMU_VCLK, 758 dpm_table); 759 if (ret) 760 return ret; 761 dpm_table->is_fine_grained = 762 !table_member[i ? PPCLK_VCLK_1 : PPCLK_VCLK_0].SnapToDiscrete; 763 } else { 764 dpm_table->count = 1; 765 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; 766 dpm_table->dpm_levels[0].enabled = true; 767 dpm_table->min = dpm_table->dpm_levels[0].value; 768 dpm_table->max = dpm_table->dpm_levels[0].value; 769 } 770 } 771 772 /* dclk0/1 dpm table setup */ 773 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 774 if (adev->vcn.harvest_config & (1 << i)) 775 continue; 776 dpm_table = &dpm_context->dpm_tables.dclk_table; 777 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 778 ret = smu_v11_0_set_single_dpm_table(smu, 779 i ? SMU_DCLK1 : SMU_DCLK, 780 dpm_table); 781 if (ret) 782 return ret; 783 dpm_table->is_fine_grained = 784 !table_member[i ? PPCLK_DCLK_1 : PPCLK_DCLK_0].SnapToDiscrete; 785 } else { 786 dpm_table->count = 1; 787 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; 788 dpm_table->dpm_levels[0].enabled = true; 789 dpm_table->min = dpm_table->dpm_levels[0].value; 790 dpm_table->max = dpm_table->dpm_levels[0].value; 791 } 792 } 793 794 /* dcefclk dpm table setup */ 795 dpm_table = &dpm_context->dpm_tables.dcef_table; 796 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 797 ret = smu_v11_0_set_single_dpm_table(smu, 798 SMU_DCEFCLK, 799 dpm_table); 800 if (ret) 801 return ret; 802 dpm_table->is_fine_grained = 803 !table_member[PPCLK_DCEFCLK].SnapToDiscrete; 804 } else { 805 dpm_table->count = 1; 806 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 807 dpm_table->dpm_levels[0].enabled = true; 808 dpm_table->min = dpm_table->dpm_levels[0].value; 809 dpm_table->max = dpm_table->dpm_levels[0].value; 810 } 811 812 /* pixelclk dpm table setup */ 813 dpm_table = &dpm_context->dpm_tables.pixel_table; 814 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 815 ret = smu_v11_0_set_single_dpm_table(smu, 816 SMU_PIXCLK, 817 dpm_table); 818 if (ret) 819 return ret; 820 dpm_table->is_fine_grained = 821 !table_member[PPCLK_PIXCLK].SnapToDiscrete; 822 } else { 823 dpm_table->count = 1; 824 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 825 dpm_table->dpm_levels[0].enabled = true; 826 dpm_table->min = dpm_table->dpm_levels[0].value; 827 dpm_table->max = dpm_table->dpm_levels[0].value; 828 } 829 830 /* displayclk dpm table setup */ 831 dpm_table = &dpm_context->dpm_tables.display_table; 832 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 833 ret = smu_v11_0_set_single_dpm_table(smu, 834 SMU_DISPCLK, 835 dpm_table); 836 if (ret) 837 return ret; 838 dpm_table->is_fine_grained = 839 !table_member[PPCLK_DISPCLK].SnapToDiscrete; 840 } else { 841 dpm_table->count = 1; 842 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 843 dpm_table->dpm_levels[0].enabled = true; 844 dpm_table->min = dpm_table->dpm_levels[0].value; 845 dpm_table->max = dpm_table->dpm_levels[0].value; 846 } 847 848 /* phyclk dpm table setup */ 849 dpm_table = &dpm_context->dpm_tables.phy_table; 850 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 851 ret = smu_v11_0_set_single_dpm_table(smu, 852 SMU_PHYCLK, 853 dpm_table); 854 if (ret) 855 return ret; 856 dpm_table->is_fine_grained = 857 !table_member[PPCLK_PHYCLK].SnapToDiscrete; 858 } else { 859 dpm_table->count = 1; 860 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 861 dpm_table->dpm_levels[0].enabled = true; 862 dpm_table->min = dpm_table->dpm_levels[0].value; 863 dpm_table->max = dpm_table->dpm_levels[0].value; 864 } 865 866 return 0; 867 } 868 869 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 870 { 871 struct amdgpu_device *adev = smu->adev; 872 int i, ret = 0; 873 874 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 875 if (adev->vcn.harvest_config & (1 << i)) 876 continue; 877 /* vcn dpm on is a prerequisite for vcn power gate messages */ 878 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 879 ret = smu_cmn_send_smc_msg_with_param(smu, enable ? 880 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn, 881 0x10000 * i, NULL); 882 if (ret) 883 return ret; 884 } 885 } 886 887 return ret; 888 } 889 890 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 891 { 892 int ret = 0; 893 894 if (enable) { 895 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 896 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); 897 if (ret) 898 return ret; 899 } 900 } else { 901 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 902 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); 903 if (ret) 904 return ret; 905 } 906 } 907 908 return ret; 909 } 910 911 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu, 912 enum smu_clk_type clk_type, 913 uint32_t *value) 914 { 915 MetricsMember_t member_type; 916 int clk_id = 0; 917 918 clk_id = smu_cmn_to_asic_specific_index(smu, 919 CMN2ASIC_MAPPING_CLK, 920 clk_type); 921 if (clk_id < 0) 922 return clk_id; 923 924 switch (clk_id) { 925 case PPCLK_GFXCLK: 926 member_type = METRICS_CURR_GFXCLK; 927 break; 928 case PPCLK_UCLK: 929 member_type = METRICS_CURR_UCLK; 930 break; 931 case PPCLK_SOCCLK: 932 member_type = METRICS_CURR_SOCCLK; 933 break; 934 case PPCLK_FCLK: 935 member_type = METRICS_CURR_FCLK; 936 break; 937 case PPCLK_VCLK_0: 938 member_type = METRICS_CURR_VCLK; 939 break; 940 case PPCLK_VCLK_1: 941 member_type = METRICS_CURR_VCLK1; 942 break; 943 case PPCLK_DCLK_0: 944 member_type = METRICS_CURR_DCLK; 945 break; 946 case PPCLK_DCLK_1: 947 member_type = METRICS_CURR_DCLK1; 948 break; 949 case PPCLK_DCEFCLK: 950 member_type = METRICS_CURR_DCEFCLK; 951 break; 952 default: 953 return -EINVAL; 954 } 955 956 return sienna_cichlid_get_smu_metrics_data(smu, 957 member_type, 958 value); 959 960 } 961 962 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) 963 { 964 DpmDescriptor_t *dpm_desc = NULL; 965 DpmDescriptor_t *table_member; 966 uint32_t clk_index = 0; 967 968 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member); 969 clk_index = smu_cmn_to_asic_specific_index(smu, 970 CMN2ASIC_MAPPING_CLK, 971 clk_type); 972 dpm_desc = &table_member[clk_index]; 973 974 /* 0 - Fine grained DPM, 1 - Discrete DPM */ 975 return dpm_desc->SnapToDiscrete == 0; 976 } 977 978 static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table, 979 enum SMU_11_0_7_ODFEATURE_CAP cap) 980 { 981 return od_table->cap[cap]; 982 } 983 984 static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table, 985 enum SMU_11_0_7_ODSETTING_ID setting, 986 uint32_t *min, uint32_t *max) 987 { 988 if (min) 989 *min = od_table->min[setting]; 990 if (max) 991 *max = od_table->max[setting]; 992 } 993 994 static int sienna_cichlid_print_clk_levels(struct smu_context *smu, 995 enum smu_clk_type clk_type, char *buf) 996 { 997 struct amdgpu_device *adev = smu->adev; 998 struct smu_table_context *table_context = &smu->smu_table; 999 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1000 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1001 uint16_t *table_member; 1002 1003 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings; 1004 OverDriveTable_t *od_table = 1005 (OverDriveTable_t *)table_context->overdrive_table; 1006 int i, size = 0, ret = 0; 1007 uint32_t cur_value = 0, value = 0, count = 0; 1008 uint32_t freq_values[3] = {0}; 1009 uint32_t mark_index = 0; 1010 uint32_t gen_speed, lane_width; 1011 uint32_t min_value, max_value; 1012 uint32_t smu_version; 1013 1014 smu_cmn_get_sysfs_buf(&buf, &size); 1015 1016 switch (clk_type) { 1017 case SMU_GFXCLK: 1018 case SMU_SCLK: 1019 case SMU_SOCCLK: 1020 case SMU_MCLK: 1021 case SMU_UCLK: 1022 case SMU_FCLK: 1023 case SMU_VCLK: 1024 case SMU_VCLK1: 1025 case SMU_DCLK: 1026 case SMU_DCLK1: 1027 case SMU_DCEFCLK: 1028 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value); 1029 if (ret) 1030 goto print_clk_out; 1031 1032 /* no need to disable gfxoff when retrieving the current gfxclk */ 1033 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK)) 1034 amdgpu_gfx_off_ctrl(adev, false); 1035 1036 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); 1037 if (ret) 1038 goto print_clk_out; 1039 1040 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) { 1041 for (i = 0; i < count; i++) { 1042 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); 1043 if (ret) 1044 goto print_clk_out; 1045 1046 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 1047 cur_value == value ? "*" : ""); 1048 } 1049 } else { 1050 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]); 1051 if (ret) 1052 goto print_clk_out; 1053 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]); 1054 if (ret) 1055 goto print_clk_out; 1056 1057 freq_values[1] = cur_value; 1058 mark_index = cur_value == freq_values[0] ? 0 : 1059 cur_value == freq_values[2] ? 2 : 1; 1060 1061 count = 3; 1062 if (mark_index != 1) { 1063 count = 2; 1064 freq_values[1] = freq_values[2]; 1065 } 1066 1067 for (i = 0; i < count; i++) { 1068 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i], 1069 cur_value == freq_values[i] ? "*" : ""); 1070 } 1071 1072 } 1073 break; 1074 case SMU_PCIE: 1075 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); 1076 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); 1077 GET_PPTABLE_MEMBER(LclkFreq, &table_member); 1078 for (i = 0; i < NUM_LINK_LEVELS; i++) 1079 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i, 1080 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," : 1081 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," : 1082 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," : 1083 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "", 1084 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" : 1085 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" : 1086 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" : 1087 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" : 1088 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" : 1089 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "", 1090 table_member[i], 1091 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && 1092 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? 1093 "*" : ""); 1094 break; 1095 case SMU_OD_SCLK: 1096 if (!smu->od_enabled || !od_table || !od_settings) 1097 break; 1098 1099 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) 1100 break; 1101 1102 size += sysfs_emit_at(buf, size, "OD_SCLK:\n"); 1103 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax); 1104 break; 1105 1106 case SMU_OD_MCLK: 1107 if (!smu->od_enabled || !od_table || !od_settings) 1108 break; 1109 1110 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) 1111 break; 1112 1113 size += sysfs_emit_at(buf, size, "OD_MCLK:\n"); 1114 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax); 1115 break; 1116 1117 case SMU_OD_VDDGFX_OFFSET: 1118 if (!smu->od_enabled || !od_table || !od_settings) 1119 break; 1120 1121 /* 1122 * OD GFX Voltage Offset functionality is supported only by 58.41.0 1123 * and onwards SMU firmwares. 1124 */ 1125 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1126 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 1127 (smu_version < 0x003a2900)) 1128 break; 1129 1130 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n"); 1131 size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset); 1132 break; 1133 1134 case SMU_OD_RANGE: 1135 if (!smu->od_enabled || !od_table || !od_settings) 1136 break; 1137 1138 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 1139 1140 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) { 1141 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN, 1142 &min_value, NULL); 1143 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX, 1144 NULL, &max_value); 1145 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 1146 min_value, max_value); 1147 } 1148 1149 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) { 1150 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN, 1151 &min_value, NULL); 1152 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX, 1153 NULL, &max_value); 1154 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n", 1155 min_value, max_value); 1156 } 1157 break; 1158 1159 default: 1160 break; 1161 } 1162 1163 print_clk_out: 1164 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK)) 1165 amdgpu_gfx_off_ctrl(adev, true); 1166 1167 return size; 1168 } 1169 1170 static int sienna_cichlid_force_clk_levels(struct smu_context *smu, 1171 enum smu_clk_type clk_type, uint32_t mask) 1172 { 1173 struct amdgpu_device *adev = smu->adev; 1174 int ret = 0, size = 0; 1175 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; 1176 1177 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1178 soft_max_level = mask ? (fls(mask) - 1) : 0; 1179 1180 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK)) 1181 amdgpu_gfx_off_ctrl(adev, false); 1182 1183 switch (clk_type) { 1184 case SMU_GFXCLK: 1185 case SMU_SCLK: 1186 case SMU_SOCCLK: 1187 case SMU_MCLK: 1188 case SMU_UCLK: 1189 case SMU_FCLK: 1190 /* There is only 2 levels for fine grained DPM */ 1191 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) { 1192 soft_max_level = (soft_max_level >= 1 ? 1 : 0); 1193 soft_min_level = (soft_min_level >= 1 ? 1 : 0); 1194 } 1195 1196 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); 1197 if (ret) 1198 goto forec_level_out; 1199 1200 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq); 1201 if (ret) 1202 goto forec_level_out; 1203 1204 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 1205 if (ret) 1206 goto forec_level_out; 1207 break; 1208 case SMU_DCEFCLK: 1209 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n"); 1210 break; 1211 default: 1212 break; 1213 } 1214 1215 forec_level_out: 1216 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK)) 1217 amdgpu_gfx_off_ctrl(adev, true); 1218 1219 return size; 1220 } 1221 1222 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu) 1223 { 1224 struct smu_11_0_dpm_context *dpm_context = 1225 smu->smu_dpm.dpm_context; 1226 struct smu_11_0_dpm_table *gfx_table = 1227 &dpm_context->dpm_tables.gfx_table; 1228 struct smu_11_0_dpm_table *mem_table = 1229 &dpm_context->dpm_tables.uclk_table; 1230 struct smu_11_0_dpm_table *soc_table = 1231 &dpm_context->dpm_tables.soc_table; 1232 struct smu_umd_pstate_table *pstate_table = 1233 &smu->pstate_table; 1234 1235 pstate_table->gfxclk_pstate.min = gfx_table->min; 1236 pstate_table->gfxclk_pstate.peak = gfx_table->max; 1237 if (gfx_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK) 1238 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK; 1239 1240 pstate_table->uclk_pstate.min = mem_table->min; 1241 pstate_table->uclk_pstate.peak = mem_table->max; 1242 if (mem_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK) 1243 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK; 1244 1245 pstate_table->socclk_pstate.min = soc_table->min; 1246 pstate_table->socclk_pstate.peak = soc_table->max; 1247 if (soc_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK) 1248 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK; 1249 1250 return 0; 1251 } 1252 1253 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu) 1254 { 1255 int ret = 0; 1256 uint32_t max_freq = 0; 1257 1258 /* Sienna_Cichlid do not support to change display num currently */ 1259 return 0; 1260 #if 0 1261 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL); 1262 if (ret) 1263 return ret; 1264 #endif 1265 1266 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1267 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq); 1268 if (ret) 1269 return ret; 1270 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq); 1271 if (ret) 1272 return ret; 1273 } 1274 1275 return ret; 1276 } 1277 1278 static int sienna_cichlid_display_config_changed(struct smu_context *smu) 1279 { 1280 int ret = 0; 1281 1282 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1283 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) && 1284 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 1285 #if 0 1286 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 1287 smu->display_config->num_display, 1288 NULL); 1289 #endif 1290 if (ret) 1291 return ret; 1292 } 1293 1294 return ret; 1295 } 1296 1297 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu) 1298 { 1299 int ret = 0; 1300 uint32_t feature_mask[2]; 1301 uint64_t feature_enabled; 1302 1303 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2); 1304 if (ret) 1305 return false; 1306 1307 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0]; 1308 1309 return !!(feature_enabled & SMC_DPM_FEATURE); 1310 } 1311 1312 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu, 1313 uint32_t *speed) 1314 { 1315 if (!speed) 1316 return -EINVAL; 1317 1318 /* 1319 * For Sienna_Cichlid and later, the fan speed(rpm) reported 1320 * by pmfw is always trustable(even when the fan control feature 1321 * disabled or 0 RPM kicked in). 1322 */ 1323 return sienna_cichlid_get_smu_metrics_data(smu, 1324 METRICS_CURR_FANSPEED, 1325 speed); 1326 } 1327 1328 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu) 1329 { 1330 uint16_t *table_member; 1331 1332 GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member); 1333 smu->fan_max_rpm = *table_member; 1334 1335 return 0; 1336 } 1337 1338 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf) 1339 { 1340 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 1341 DpmActivityMonitorCoeffInt_t *activity_monitor = 1342 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 1343 uint32_t i, size = 0; 1344 int16_t workload_type = 0; 1345 static const char *profile_name[] = { 1346 "BOOTUP_DEFAULT", 1347 "3D_FULL_SCREEN", 1348 "POWER_SAVING", 1349 "VIDEO", 1350 "VR", 1351 "COMPUTE", 1352 "CUSTOM"}; 1353 static const char *title[] = { 1354 "PROFILE_INDEX(NAME)", 1355 "CLOCK_TYPE(NAME)", 1356 "FPS", 1357 "MinFreqType", 1358 "MinActiveFreqType", 1359 "MinActiveFreq", 1360 "BoosterFreqType", 1361 "BoosterFreq", 1362 "PD_Data_limit_c", 1363 "PD_Data_error_coeff", 1364 "PD_Data_error_rate_coeff"}; 1365 int result = 0; 1366 1367 if (!buf) 1368 return -EINVAL; 1369 1370 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n", 1371 title[0], title[1], title[2], title[3], title[4], title[5], 1372 title[6], title[7], title[8], title[9], title[10]); 1373 1374 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1375 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1376 workload_type = smu_cmn_to_asic_specific_index(smu, 1377 CMN2ASIC_MAPPING_WORKLOAD, 1378 i); 1379 if (workload_type < 0) 1380 return -EINVAL; 1381 1382 result = smu_cmn_update_table(smu, 1383 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type, 1384 (void *)(&activity_monitor_external), false); 1385 if (result) { 1386 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1387 return result; 1388 } 1389 1390 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n", 1391 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1392 1393 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1394 " ", 1395 0, 1396 "GFXCLK", 1397 activity_monitor->Gfx_FPS, 1398 activity_monitor->Gfx_MinFreqStep, 1399 activity_monitor->Gfx_MinActiveFreqType, 1400 activity_monitor->Gfx_MinActiveFreq, 1401 activity_monitor->Gfx_BoosterFreqType, 1402 activity_monitor->Gfx_BoosterFreq, 1403 activity_monitor->Gfx_PD_Data_limit_c, 1404 activity_monitor->Gfx_PD_Data_error_coeff, 1405 activity_monitor->Gfx_PD_Data_error_rate_coeff); 1406 1407 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1408 " ", 1409 1, 1410 "SOCCLK", 1411 activity_monitor->Fclk_FPS, 1412 activity_monitor->Fclk_MinFreqStep, 1413 activity_monitor->Fclk_MinActiveFreqType, 1414 activity_monitor->Fclk_MinActiveFreq, 1415 activity_monitor->Fclk_BoosterFreqType, 1416 activity_monitor->Fclk_BoosterFreq, 1417 activity_monitor->Fclk_PD_Data_limit_c, 1418 activity_monitor->Fclk_PD_Data_error_coeff, 1419 activity_monitor->Fclk_PD_Data_error_rate_coeff); 1420 1421 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1422 " ", 1423 2, 1424 "MEMLK", 1425 activity_monitor->Mem_FPS, 1426 activity_monitor->Mem_MinFreqStep, 1427 activity_monitor->Mem_MinActiveFreqType, 1428 activity_monitor->Mem_MinActiveFreq, 1429 activity_monitor->Mem_BoosterFreqType, 1430 activity_monitor->Mem_BoosterFreq, 1431 activity_monitor->Mem_PD_Data_limit_c, 1432 activity_monitor->Mem_PD_Data_error_coeff, 1433 activity_monitor->Mem_PD_Data_error_rate_coeff); 1434 } 1435 1436 return size; 1437 } 1438 1439 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 1440 { 1441 1442 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 1443 DpmActivityMonitorCoeffInt_t *activity_monitor = 1444 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 1445 int workload_type, ret = 0; 1446 1447 smu->power_profile_mode = input[size]; 1448 1449 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 1450 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode); 1451 return -EINVAL; 1452 } 1453 1454 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 1455 1456 ret = smu_cmn_update_table(smu, 1457 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1458 (void *)(&activity_monitor_external), false); 1459 if (ret) { 1460 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1461 return ret; 1462 } 1463 1464 switch (input[0]) { 1465 case 0: /* Gfxclk */ 1466 activity_monitor->Gfx_FPS = input[1]; 1467 activity_monitor->Gfx_MinFreqStep = input[2]; 1468 activity_monitor->Gfx_MinActiveFreqType = input[3]; 1469 activity_monitor->Gfx_MinActiveFreq = input[4]; 1470 activity_monitor->Gfx_BoosterFreqType = input[5]; 1471 activity_monitor->Gfx_BoosterFreq = input[6]; 1472 activity_monitor->Gfx_PD_Data_limit_c = input[7]; 1473 activity_monitor->Gfx_PD_Data_error_coeff = input[8]; 1474 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9]; 1475 break; 1476 case 1: /* Socclk */ 1477 activity_monitor->Fclk_FPS = input[1]; 1478 activity_monitor->Fclk_MinFreqStep = input[2]; 1479 activity_monitor->Fclk_MinActiveFreqType = input[3]; 1480 activity_monitor->Fclk_MinActiveFreq = input[4]; 1481 activity_monitor->Fclk_BoosterFreqType = input[5]; 1482 activity_monitor->Fclk_BoosterFreq = input[6]; 1483 activity_monitor->Fclk_PD_Data_limit_c = input[7]; 1484 activity_monitor->Fclk_PD_Data_error_coeff = input[8]; 1485 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9]; 1486 break; 1487 case 2: /* Memlk */ 1488 activity_monitor->Mem_FPS = input[1]; 1489 activity_monitor->Mem_MinFreqStep = input[2]; 1490 activity_monitor->Mem_MinActiveFreqType = input[3]; 1491 activity_monitor->Mem_MinActiveFreq = input[4]; 1492 activity_monitor->Mem_BoosterFreqType = input[5]; 1493 activity_monitor->Mem_BoosterFreq = input[6]; 1494 activity_monitor->Mem_PD_Data_limit_c = input[7]; 1495 activity_monitor->Mem_PD_Data_error_coeff = input[8]; 1496 activity_monitor->Mem_PD_Data_error_rate_coeff = input[9]; 1497 break; 1498 } 1499 1500 ret = smu_cmn_update_table(smu, 1501 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1502 (void *)(&activity_monitor_external), true); 1503 if (ret) { 1504 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 1505 return ret; 1506 } 1507 } 1508 1509 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1510 workload_type = smu_cmn_to_asic_specific_index(smu, 1511 CMN2ASIC_MAPPING_WORKLOAD, 1512 smu->power_profile_mode); 1513 if (workload_type < 0) 1514 return -EINVAL; 1515 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 1516 1 << workload_type, NULL); 1517 1518 return ret; 1519 } 1520 1521 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu) 1522 { 1523 struct smu_clocks min_clocks = {0}; 1524 struct pp_display_clock_request clock_req; 1525 int ret = 0; 1526 1527 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; 1528 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; 1529 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; 1530 1531 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1532 clock_req.clock_type = amd_pp_dcef_clock; 1533 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; 1534 1535 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req); 1536 if (!ret) { 1537 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) { 1538 ret = smu_cmn_send_smc_msg_with_param(smu, 1539 SMU_MSG_SetMinDeepSleepDcefclk, 1540 min_clocks.dcef_clock_in_sr/100, 1541 NULL); 1542 if (ret) { 1543 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!"); 1544 return ret; 1545 } 1546 } 1547 } else { 1548 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!"); 1549 } 1550 } 1551 1552 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1553 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); 1554 if (ret) { 1555 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__); 1556 return ret; 1557 } 1558 } 1559 1560 return 0; 1561 } 1562 1563 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu, 1564 struct pp_smu_wm_range_sets *clock_ranges) 1565 { 1566 Watermarks_t *table = smu->smu_table.watermarks_table; 1567 int ret = 0; 1568 int i; 1569 1570 if (clock_ranges) { 1571 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 1572 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1573 return -EINVAL; 1574 1575 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1576 table->WatermarkRow[WM_DCEFCLK][i].MinClock = 1577 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1578 table->WatermarkRow[WM_DCEFCLK][i].MaxClock = 1579 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1580 table->WatermarkRow[WM_DCEFCLK][i].MinUclk = 1581 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1582 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk = 1583 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1584 1585 table->WatermarkRow[WM_DCEFCLK][i].WmSetting = 1586 clock_ranges->reader_wm_sets[i].wm_inst; 1587 } 1588 1589 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1590 table->WatermarkRow[WM_SOCCLK][i].MinClock = 1591 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1592 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1593 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1594 table->WatermarkRow[WM_SOCCLK][i].MinUclk = 1595 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1596 table->WatermarkRow[WM_SOCCLK][i].MaxUclk = 1597 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1598 1599 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1600 clock_ranges->writer_wm_sets[i].wm_inst; 1601 } 1602 1603 smu->watermarks_bitmap |= WATERMARKS_EXIST; 1604 } 1605 1606 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1607 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1608 ret = smu_cmn_write_watermarks_table(smu); 1609 if (ret) { 1610 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1611 return ret; 1612 } 1613 smu->watermarks_bitmap |= WATERMARKS_LOADED; 1614 } 1615 1616 return 0; 1617 } 1618 1619 static int sienna_cichlid_read_sensor(struct smu_context *smu, 1620 enum amd_pp_sensors sensor, 1621 void *data, uint32_t *size) 1622 { 1623 int ret = 0; 1624 uint16_t *temp; 1625 1626 if(!data || !size) 1627 return -EINVAL; 1628 1629 mutex_lock(&smu->sensor_lock); 1630 switch (sensor) { 1631 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 1632 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp); 1633 *(uint16_t *)data = *temp; 1634 *size = 4; 1635 break; 1636 case AMDGPU_PP_SENSOR_MEM_LOAD: 1637 ret = sienna_cichlid_get_smu_metrics_data(smu, 1638 METRICS_AVERAGE_MEMACTIVITY, 1639 (uint32_t *)data); 1640 *size = 4; 1641 break; 1642 case AMDGPU_PP_SENSOR_GPU_LOAD: 1643 ret = sienna_cichlid_get_smu_metrics_data(smu, 1644 METRICS_AVERAGE_GFXACTIVITY, 1645 (uint32_t *)data); 1646 *size = 4; 1647 break; 1648 case AMDGPU_PP_SENSOR_GPU_POWER: 1649 ret = sienna_cichlid_get_smu_metrics_data(smu, 1650 METRICS_AVERAGE_SOCKETPOWER, 1651 (uint32_t *)data); 1652 *size = 4; 1653 break; 1654 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1655 ret = sienna_cichlid_get_smu_metrics_data(smu, 1656 METRICS_TEMPERATURE_HOTSPOT, 1657 (uint32_t *)data); 1658 *size = 4; 1659 break; 1660 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1661 ret = sienna_cichlid_get_smu_metrics_data(smu, 1662 METRICS_TEMPERATURE_EDGE, 1663 (uint32_t *)data); 1664 *size = 4; 1665 break; 1666 case AMDGPU_PP_SENSOR_MEM_TEMP: 1667 ret = sienna_cichlid_get_smu_metrics_data(smu, 1668 METRICS_TEMPERATURE_MEM, 1669 (uint32_t *)data); 1670 *size = 4; 1671 break; 1672 case AMDGPU_PP_SENSOR_GFX_MCLK: 1673 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 1674 *(uint32_t *)data *= 100; 1675 *size = 4; 1676 break; 1677 case AMDGPU_PP_SENSOR_GFX_SCLK: 1678 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); 1679 *(uint32_t *)data *= 100; 1680 *size = 4; 1681 break; 1682 case AMDGPU_PP_SENSOR_VDDGFX: 1683 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data); 1684 *size = 4; 1685 break; 1686 default: 1687 ret = -EOPNOTSUPP; 1688 break; 1689 } 1690 mutex_unlock(&smu->sensor_lock); 1691 1692 return ret; 1693 } 1694 1695 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states) 1696 { 1697 uint32_t num_discrete_levels = 0; 1698 uint16_t *dpm_levels = NULL; 1699 uint16_t i = 0; 1700 struct smu_table_context *table_context = &smu->smu_table; 1701 DpmDescriptor_t *table_member1; 1702 uint16_t *table_member2; 1703 1704 if (!clocks_in_khz || !num_states || !table_context->driver_pptable) 1705 return -EINVAL; 1706 1707 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1); 1708 num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels; 1709 GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2); 1710 dpm_levels = table_member2; 1711 1712 if (num_discrete_levels == 0 || dpm_levels == NULL) 1713 return -EINVAL; 1714 1715 *num_states = num_discrete_levels; 1716 for (i = 0; i < num_discrete_levels; i++) { 1717 /* convert to khz */ 1718 *clocks_in_khz = (*dpm_levels) * 1000; 1719 clocks_in_khz++; 1720 dpm_levels++; 1721 } 1722 1723 return 0; 1724 } 1725 1726 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu, 1727 struct smu_temperature_range *range) 1728 { 1729 struct smu_table_context *table_context = &smu->smu_table; 1730 struct smu_11_0_7_powerplay_table *powerplay_table = 1731 table_context->power_play_table; 1732 uint16_t *table_member; 1733 uint16_t temp_edge, temp_hotspot, temp_mem; 1734 1735 if (!range) 1736 return -EINVAL; 1737 1738 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range)); 1739 1740 GET_PPTABLE_MEMBER(TemperatureLimit, &table_member); 1741 temp_edge = table_member[TEMP_EDGE]; 1742 temp_hotspot = table_member[TEMP_HOTSPOT]; 1743 temp_mem = table_member[TEMP_MEM]; 1744 1745 range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1746 range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) * 1747 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1748 range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1749 range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) * 1750 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1751 range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1752 range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)* 1753 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1754 1755 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 1756 1757 return 0; 1758 } 1759 1760 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu, 1761 bool disable_memory_clock_switch) 1762 { 1763 int ret = 0; 1764 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks = 1765 (struct smu_11_0_max_sustainable_clocks *) 1766 smu->smu_table.max_sustainable_clocks; 1767 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal; 1768 uint32_t max_memory_clock = max_sustainable_clocks->uclock; 1769 1770 if(smu->disable_uclk_switch == disable_memory_clock_switch) 1771 return 0; 1772 1773 if(disable_memory_clock_switch) 1774 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0); 1775 else 1776 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0); 1777 1778 if(!ret) 1779 smu->disable_uclk_switch = disable_memory_clock_switch; 1780 1781 return ret; 1782 } 1783 1784 static int sienna_cichlid_get_power_limit(struct smu_context *smu, 1785 uint32_t *current_power_limit, 1786 uint32_t *default_power_limit, 1787 uint32_t *max_power_limit) 1788 { 1789 struct smu_11_0_7_powerplay_table *powerplay_table = 1790 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table; 1791 uint32_t power_limit, od_percent; 1792 uint16_t *table_member; 1793 1794 GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member); 1795 1796 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) { 1797 power_limit = 1798 table_member[PPT_THROTTLER_PPT0]; 1799 } 1800 1801 if (current_power_limit) 1802 *current_power_limit = power_limit; 1803 if (default_power_limit) 1804 *default_power_limit = power_limit; 1805 1806 if (max_power_limit) { 1807 if (smu->od_enabled) { 1808 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]); 1809 1810 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit); 1811 1812 power_limit *= (100 + od_percent); 1813 power_limit /= 100; 1814 } 1815 *max_power_limit = power_limit; 1816 } 1817 1818 return 0; 1819 } 1820 1821 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu, 1822 uint32_t pcie_gen_cap, 1823 uint32_t pcie_width_cap) 1824 { 1825 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 1826 1827 uint32_t smu_pcie_arg; 1828 uint8_t *table_member1, *table_member2; 1829 int ret, i; 1830 1831 GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1); 1832 GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2); 1833 1834 /* lclk dpm table setup */ 1835 for (i = 0; i < MAX_PCIE_CONF; i++) { 1836 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = table_member1[i]; 1837 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = table_member2[i]; 1838 } 1839 1840 for (i = 0; i < NUM_LINK_LEVELS; i++) { 1841 smu_pcie_arg = (i << 16) | 1842 ((table_member1[i] <= pcie_gen_cap) ? 1843 (table_member1[i] << 8) : 1844 (pcie_gen_cap << 8)) | 1845 ((table_member2[i] <= pcie_width_cap) ? 1846 table_member2[i] : 1847 pcie_width_cap); 1848 1849 ret = smu_cmn_send_smc_msg_with_param(smu, 1850 SMU_MSG_OverridePcieParameters, 1851 smu_pcie_arg, 1852 NULL); 1853 if (ret) 1854 return ret; 1855 1856 if (table_member1[i] > pcie_gen_cap) 1857 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap; 1858 if (table_member2[i] > pcie_width_cap) 1859 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap; 1860 } 1861 1862 return 0; 1863 } 1864 1865 static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu, 1866 enum smu_clk_type clk_type, 1867 uint32_t *min, uint32_t *max) 1868 { 1869 struct amdgpu_device *adev = smu->adev; 1870 int ret; 1871 1872 if (clk_type == SMU_GFXCLK) 1873 amdgpu_gfx_off_ctrl(adev, false); 1874 ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max); 1875 if (clk_type == SMU_GFXCLK) 1876 amdgpu_gfx_off_ctrl(adev, true); 1877 1878 return ret; 1879 } 1880 1881 static void sienna_cichlid_dump_od_table(struct smu_context *smu, 1882 OverDriveTable_t *od_table) 1883 { 1884 struct amdgpu_device *adev = smu->adev; 1885 uint32_t smu_version; 1886 1887 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, 1888 od_table->GfxclkFmax); 1889 dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin, 1890 od_table->UclkFmax); 1891 1892 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1893 if (!((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 1894 (smu_version < 0x003a2900))) 1895 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset); 1896 } 1897 1898 static int sienna_cichlid_set_default_od_settings(struct smu_context *smu) 1899 { 1900 OverDriveTable_t *od_table = 1901 (OverDriveTable_t *)smu->smu_table.overdrive_table; 1902 OverDriveTable_t *boot_od_table = 1903 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table; 1904 OverDriveTable_t *user_od_table = 1905 (OverDriveTable_t *)smu->smu_table.user_overdrive_table; 1906 int ret = 0; 1907 1908 /* 1909 * For S3/S4/Runpm resume, no need to setup those overdrive tables again as 1910 * - either they already have the default OD settings got during cold bootup 1911 * - or they have some user customized OD settings which cannot be overwritten 1912 */ 1913 if (smu->adev->in_suspend) 1914 return 0; 1915 1916 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 1917 0, (void *)boot_od_table, false); 1918 if (ret) { 1919 dev_err(smu->adev->dev, "Failed to get overdrive table!\n"); 1920 return ret; 1921 } 1922 1923 sienna_cichlid_dump_od_table(smu, boot_od_table); 1924 1925 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t)); 1926 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t)); 1927 1928 return 0; 1929 } 1930 1931 static int sienna_cichlid_od_setting_check_range(struct smu_context *smu, 1932 struct smu_11_0_7_overdrive_table *od_table, 1933 enum SMU_11_0_7_ODSETTING_ID setting, 1934 uint32_t value) 1935 { 1936 if (value < od_table->min[setting]) { 1937 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", 1938 setting, value, od_table->min[setting]); 1939 return -EINVAL; 1940 } 1941 if (value > od_table->max[setting]) { 1942 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", 1943 setting, value, od_table->max[setting]); 1944 return -EINVAL; 1945 } 1946 1947 return 0; 1948 } 1949 1950 static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu, 1951 enum PP_OD_DPM_TABLE_COMMAND type, 1952 long input[], uint32_t size) 1953 { 1954 struct smu_table_context *table_context = &smu->smu_table; 1955 OverDriveTable_t *od_table = 1956 (OverDriveTable_t *)table_context->overdrive_table; 1957 struct smu_11_0_7_overdrive_table *od_settings = 1958 (struct smu_11_0_7_overdrive_table *)smu->od_settings; 1959 struct amdgpu_device *adev = smu->adev; 1960 enum SMU_11_0_7_ODSETTING_ID freq_setting; 1961 uint16_t *freq_ptr; 1962 int i, ret = 0; 1963 uint32_t smu_version; 1964 1965 if (!smu->od_enabled) { 1966 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n"); 1967 return -EINVAL; 1968 } 1969 1970 if (!smu->od_settings) { 1971 dev_err(smu->adev->dev, "OD board limits are not set!\n"); 1972 return -ENOENT; 1973 } 1974 1975 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) { 1976 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n"); 1977 return -EINVAL; 1978 } 1979 1980 switch (type) { 1981 case PP_OD_EDIT_SCLK_VDDC_TABLE: 1982 if (!sienna_cichlid_is_od_feature_supported(od_settings, 1983 SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) { 1984 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n"); 1985 return -ENOTSUPP; 1986 } 1987 1988 for (i = 0; i < size; i += 2) { 1989 if (i + 2 > size) { 1990 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size); 1991 return -EINVAL; 1992 } 1993 1994 switch (input[i]) { 1995 case 0: 1996 if (input[i + 1] > od_table->GfxclkFmax) { 1997 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n", 1998 input[i + 1], od_table->GfxclkFmax); 1999 return -EINVAL; 2000 } 2001 2002 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN; 2003 freq_ptr = &od_table->GfxclkFmin; 2004 break; 2005 2006 case 1: 2007 if (input[i + 1] < od_table->GfxclkFmin) { 2008 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n", 2009 input[i + 1], od_table->GfxclkFmin); 2010 return -EINVAL; 2011 } 2012 2013 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX; 2014 freq_ptr = &od_table->GfxclkFmax; 2015 break; 2016 2017 default: 2018 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]); 2019 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n"); 2020 return -EINVAL; 2021 } 2022 2023 ret = sienna_cichlid_od_setting_check_range(smu, od_settings, 2024 freq_setting, input[i + 1]); 2025 if (ret) 2026 return ret; 2027 2028 *freq_ptr = (uint16_t)input[i + 1]; 2029 } 2030 break; 2031 2032 case PP_OD_EDIT_MCLK_VDDC_TABLE: 2033 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) { 2034 dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n"); 2035 return -ENOTSUPP; 2036 } 2037 2038 for (i = 0; i < size; i += 2) { 2039 if (i + 2 > size) { 2040 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size); 2041 return -EINVAL; 2042 } 2043 2044 switch (input[i]) { 2045 case 0: 2046 if (input[i + 1] > od_table->UclkFmax) { 2047 dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n", 2048 input[i + 1], od_table->UclkFmax); 2049 return -EINVAL; 2050 } 2051 2052 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN; 2053 freq_ptr = &od_table->UclkFmin; 2054 break; 2055 2056 case 1: 2057 if (input[i + 1] < od_table->UclkFmin) { 2058 dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n", 2059 input[i + 1], od_table->UclkFmin); 2060 return -EINVAL; 2061 } 2062 2063 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX; 2064 freq_ptr = &od_table->UclkFmax; 2065 break; 2066 2067 default: 2068 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]); 2069 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n"); 2070 return -EINVAL; 2071 } 2072 2073 ret = sienna_cichlid_od_setting_check_range(smu, od_settings, 2074 freq_setting, input[i + 1]); 2075 if (ret) 2076 return ret; 2077 2078 *freq_ptr = (uint16_t)input[i + 1]; 2079 } 2080 break; 2081 2082 case PP_OD_RESTORE_DEFAULT_TABLE: 2083 memcpy(table_context->overdrive_table, 2084 table_context->boot_overdrive_table, 2085 sizeof(OverDriveTable_t)); 2086 fallthrough; 2087 2088 case PP_OD_COMMIT_DPM_TABLE: 2089 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) { 2090 sienna_cichlid_dump_od_table(smu, od_table); 2091 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true); 2092 if (ret) { 2093 dev_err(smu->adev->dev, "Failed to import overdrive table!\n"); 2094 return ret; 2095 } 2096 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t)); 2097 smu->user_dpm_profile.user_od = true; 2098 2099 if (!memcmp(table_context->user_overdrive_table, 2100 table_context->boot_overdrive_table, 2101 sizeof(OverDriveTable_t))) 2102 smu->user_dpm_profile.user_od = false; 2103 } 2104 break; 2105 2106 case PP_OD_EDIT_VDDGFX_OFFSET: 2107 if (size != 1) { 2108 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size); 2109 return -EINVAL; 2110 } 2111 2112 /* 2113 * OD GFX Voltage Offset functionality is supported only by 58.41.0 2114 * and onwards SMU firmwares. 2115 */ 2116 smu_cmn_get_smc_version(smu, NULL, &smu_version); 2117 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 2118 (smu_version < 0x003a2900)) { 2119 dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported " 2120 "only by 58.41.0 and onwards SMU firmwares!\n"); 2121 return -EOPNOTSUPP; 2122 } 2123 2124 od_table->VddGfxOffset = (int16_t)input[0]; 2125 2126 sienna_cichlid_dump_od_table(smu, od_table); 2127 break; 2128 2129 default: 2130 return -ENOSYS; 2131 } 2132 2133 return ret; 2134 } 2135 2136 static int sienna_cichlid_run_btc(struct smu_context *smu) 2137 { 2138 return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); 2139 } 2140 2141 static int sienna_cichlid_baco_enter(struct smu_context *smu) 2142 { 2143 struct amdgpu_device *adev = smu->adev; 2144 2145 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) 2146 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO); 2147 else 2148 return smu_v11_0_baco_enter(smu); 2149 } 2150 2151 static int sienna_cichlid_baco_exit(struct smu_context *smu) 2152 { 2153 struct amdgpu_device *adev = smu->adev; 2154 2155 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) { 2156 /* Wait for PMFW handling for the Dstate change */ 2157 msleep(10); 2158 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS); 2159 } else { 2160 return smu_v11_0_baco_exit(smu); 2161 } 2162 } 2163 2164 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu) 2165 { 2166 struct amdgpu_device *adev = smu->adev; 2167 uint32_t val; 2168 u32 smu_version; 2169 2170 /** 2171 * SRIOV env will not support SMU mode1 reset 2172 * PM FW support mode1 reset from 58.26 2173 */ 2174 smu_cmn_get_smc_version(smu, NULL, &smu_version); 2175 if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00)) 2176 return false; 2177 2178 /** 2179 * mode1 reset relies on PSP, so we should check if 2180 * PSP is alive. 2181 */ 2182 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 2183 return val != 0x0; 2184 } 2185 2186 static void beige_goby_dump_pptable(struct smu_context *smu) 2187 { 2188 struct smu_table_context *table_context = &smu->smu_table; 2189 PPTable_beige_goby_t *pptable = table_context->driver_pptable; 2190 int i; 2191 2192 dev_info(smu->adev->dev, "Dumped PPTable:\n"); 2193 2194 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version); 2195 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]); 2196 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]); 2197 2198 for (i = 0; i < PPT_THROTTLER_COUNT; i++) { 2199 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]); 2200 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]); 2201 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]); 2202 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]); 2203 } 2204 2205 for (i = 0; i < TDC_THROTTLER_COUNT; i++) { 2206 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]); 2207 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]); 2208 } 2209 2210 for (i = 0; i < TEMP_COUNT; i++) { 2211 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]); 2212 } 2213 2214 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit); 2215 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig); 2216 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]); 2217 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]); 2218 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]); 2219 2220 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit); 2221 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) { 2222 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]); 2223 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]); 2224 } 2225 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask); 2226 2227 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask); 2228 2229 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc); 2230 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx); 2231 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx); 2232 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc); 2233 2234 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin); 2235 2236 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold); 2237 2238 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx); 2239 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc); 2240 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx); 2241 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc); 2242 2243 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx); 2244 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc); 2245 2246 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin); 2247 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin); 2248 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp); 2249 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp); 2250 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp); 2251 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp); 2252 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis); 2253 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis); 2254 2255 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n" 2256 " .VoltageMode = 0x%02x\n" 2257 " .SnapToDiscrete = 0x%02x\n" 2258 " .NumDiscreteLevels = 0x%02x\n" 2259 " .padding = 0x%02x\n" 2260 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2261 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2262 " .SsFmin = 0x%04x\n" 2263 " .Padding_16 = 0x%04x\n", 2264 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode, 2265 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete, 2266 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels, 2267 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding, 2268 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m, 2269 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b, 2270 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a, 2271 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b, 2272 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c, 2273 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin, 2274 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16); 2275 2276 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n" 2277 " .VoltageMode = 0x%02x\n" 2278 " .SnapToDiscrete = 0x%02x\n" 2279 " .NumDiscreteLevels = 0x%02x\n" 2280 " .padding = 0x%02x\n" 2281 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2282 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2283 " .SsFmin = 0x%04x\n" 2284 " .Padding_16 = 0x%04x\n", 2285 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode, 2286 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete, 2287 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels, 2288 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding, 2289 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m, 2290 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b, 2291 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a, 2292 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b, 2293 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c, 2294 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin, 2295 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16); 2296 2297 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n" 2298 " .VoltageMode = 0x%02x\n" 2299 " .SnapToDiscrete = 0x%02x\n" 2300 " .NumDiscreteLevels = 0x%02x\n" 2301 " .padding = 0x%02x\n" 2302 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2303 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2304 " .SsFmin = 0x%04x\n" 2305 " .Padding_16 = 0x%04x\n", 2306 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode, 2307 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete, 2308 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels, 2309 pptable->DpmDescriptor[PPCLK_UCLK].Padding, 2310 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m, 2311 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b, 2312 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a, 2313 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b, 2314 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c, 2315 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin, 2316 pptable->DpmDescriptor[PPCLK_UCLK].Padding16); 2317 2318 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n" 2319 " .VoltageMode = 0x%02x\n" 2320 " .SnapToDiscrete = 0x%02x\n" 2321 " .NumDiscreteLevels = 0x%02x\n" 2322 " .padding = 0x%02x\n" 2323 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2324 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2325 " .SsFmin = 0x%04x\n" 2326 " .Padding_16 = 0x%04x\n", 2327 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode, 2328 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete, 2329 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels, 2330 pptable->DpmDescriptor[PPCLK_FCLK].Padding, 2331 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m, 2332 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b, 2333 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a, 2334 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b, 2335 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c, 2336 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin, 2337 pptable->DpmDescriptor[PPCLK_FCLK].Padding16); 2338 2339 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n" 2340 " .VoltageMode = 0x%02x\n" 2341 " .SnapToDiscrete = 0x%02x\n" 2342 " .NumDiscreteLevels = 0x%02x\n" 2343 " .padding = 0x%02x\n" 2344 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2345 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2346 " .SsFmin = 0x%04x\n" 2347 " .Padding_16 = 0x%04x\n", 2348 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode, 2349 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete, 2350 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels, 2351 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding, 2352 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m, 2353 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b, 2354 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a, 2355 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b, 2356 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c, 2357 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin, 2358 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16); 2359 2360 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n" 2361 " .VoltageMode = 0x%02x\n" 2362 " .SnapToDiscrete = 0x%02x\n" 2363 " .NumDiscreteLevels = 0x%02x\n" 2364 " .padding = 0x%02x\n" 2365 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2366 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2367 " .SsFmin = 0x%04x\n" 2368 " .Padding_16 = 0x%04x\n", 2369 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode, 2370 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete, 2371 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels, 2372 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding, 2373 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m, 2374 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b, 2375 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a, 2376 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b, 2377 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c, 2378 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin, 2379 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16); 2380 2381 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n" 2382 " .VoltageMode = 0x%02x\n" 2383 " .SnapToDiscrete = 0x%02x\n" 2384 " .NumDiscreteLevels = 0x%02x\n" 2385 " .padding = 0x%02x\n" 2386 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2387 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2388 " .SsFmin = 0x%04x\n" 2389 " .Padding_16 = 0x%04x\n", 2390 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode, 2391 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete, 2392 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels, 2393 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding, 2394 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m, 2395 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b, 2396 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a, 2397 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b, 2398 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c, 2399 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin, 2400 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16); 2401 2402 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n" 2403 " .VoltageMode = 0x%02x\n" 2404 " .SnapToDiscrete = 0x%02x\n" 2405 " .NumDiscreteLevels = 0x%02x\n" 2406 " .padding = 0x%02x\n" 2407 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2408 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2409 " .SsFmin = 0x%04x\n" 2410 " .Padding_16 = 0x%04x\n", 2411 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode, 2412 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete, 2413 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels, 2414 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding, 2415 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m, 2416 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b, 2417 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a, 2418 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b, 2419 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c, 2420 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin, 2421 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16); 2422 2423 dev_info(smu->adev->dev, "FreqTableGfx\n"); 2424 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) 2425 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]); 2426 2427 dev_info(smu->adev->dev, "FreqTableVclk\n"); 2428 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++) 2429 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]); 2430 2431 dev_info(smu->adev->dev, "FreqTableDclk\n"); 2432 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++) 2433 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]); 2434 2435 dev_info(smu->adev->dev, "FreqTableSocclk\n"); 2436 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) 2437 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]); 2438 2439 dev_info(smu->adev->dev, "FreqTableUclk\n"); 2440 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2441 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]); 2442 2443 dev_info(smu->adev->dev, "FreqTableFclk\n"); 2444 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) 2445 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]); 2446 2447 dev_info(smu->adev->dev, "DcModeMaxFreq\n"); 2448 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]); 2449 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]); 2450 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]); 2451 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]); 2452 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]); 2453 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]); 2454 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]); 2455 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]); 2456 2457 dev_info(smu->adev->dev, "FreqTableUclkDiv\n"); 2458 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2459 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]); 2460 2461 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq); 2462 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding); 2463 2464 dev_info(smu->adev->dev, "Mp0clkFreq\n"); 2465 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 2466 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]); 2467 2468 dev_info(smu->adev->dev, "Mp0DpmVoltage\n"); 2469 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 2470 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]); 2471 2472 dev_info(smu->adev->dev, "MemVddciVoltage\n"); 2473 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2474 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]); 2475 2476 dev_info(smu->adev->dev, "MemMvddVoltage\n"); 2477 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2478 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]); 2479 2480 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry); 2481 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit); 2482 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle); 2483 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource); 2484 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding); 2485 2486 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask); 2487 2488 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask); 2489 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask); 2490 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]); 2491 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow); 2492 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]); 2493 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]); 2494 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]); 2495 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]); 2496 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt); 2497 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt); 2498 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt); 2499 2500 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage); 2501 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime); 2502 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime); 2503 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum); 2504 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis); 2505 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout); 2506 2507 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]); 2508 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]); 2509 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]); 2510 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]); 2511 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]); 2512 2513 dev_info(smu->adev->dev, "FlopsPerByteTable\n"); 2514 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++) 2515 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]); 2516 2517 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv); 2518 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]); 2519 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]); 2520 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]); 2521 2522 dev_info(smu->adev->dev, "UclkDpmPstates\n"); 2523 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2524 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]); 2525 2526 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n"); 2527 dev_info(smu->adev->dev, " .Fmin = 0x%x\n", 2528 pptable->UclkDpmSrcFreqRange.Fmin); 2529 dev_info(smu->adev->dev, " .Fmax = 0x%x\n", 2530 pptable->UclkDpmSrcFreqRange.Fmax); 2531 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n"); 2532 dev_info(smu->adev->dev, " .Fmin = 0x%x\n", 2533 pptable->UclkDpmTargFreqRange.Fmin); 2534 dev_info(smu->adev->dev, " .Fmax = 0x%x\n", 2535 pptable->UclkDpmTargFreqRange.Fmax); 2536 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq); 2537 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding); 2538 2539 dev_info(smu->adev->dev, "PcieGenSpeed\n"); 2540 for (i = 0; i < NUM_LINK_LEVELS; i++) 2541 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]); 2542 2543 dev_info(smu->adev->dev, "PcieLaneCount\n"); 2544 for (i = 0; i < NUM_LINK_LEVELS; i++) 2545 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]); 2546 2547 dev_info(smu->adev->dev, "LclkFreq\n"); 2548 for (i = 0; i < NUM_LINK_LEVELS; i++) 2549 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]); 2550 2551 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp); 2552 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp); 2553 2554 dev_info(smu->adev->dev, "FanGain\n"); 2555 for (i = 0; i < TEMP_COUNT; i++) 2556 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]); 2557 2558 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin); 2559 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm); 2560 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm); 2561 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm); 2562 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm); 2563 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature); 2564 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk); 2565 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16); 2566 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect); 2567 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding); 2568 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable); 2569 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev); 2570 2571 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta); 2572 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta); 2573 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta); 2574 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved); 2575 2576 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]); 2577 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]); 2578 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect); 2579 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs); 2580 2581 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", 2582 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a, 2583 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b, 2584 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c); 2585 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", 2586 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a, 2587 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b, 2588 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c); 2589 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n", 2590 pptable->dBtcGbGfxPll.a, 2591 pptable->dBtcGbGfxPll.b, 2592 pptable->dBtcGbGfxPll.c); 2593 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n", 2594 pptable->dBtcGbGfxDfll.a, 2595 pptable->dBtcGbGfxDfll.b, 2596 pptable->dBtcGbGfxDfll.c); 2597 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n", 2598 pptable->dBtcGbSoc.a, 2599 pptable->dBtcGbSoc.b, 2600 pptable->dBtcGbSoc.c); 2601 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n", 2602 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m, 2603 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b); 2604 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n", 2605 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m, 2606 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b); 2607 2608 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n"); 2609 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) { 2610 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n", 2611 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]); 2612 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n", 2613 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]); 2614 } 2615 2616 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", 2617 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a, 2618 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b, 2619 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c); 2620 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", 2621 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a, 2622 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b, 2623 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c); 2624 2625 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]); 2626 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]); 2627 2628 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]); 2629 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]); 2630 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]); 2631 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]); 2632 2633 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]); 2634 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]); 2635 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]); 2636 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]); 2637 2638 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]); 2639 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]); 2640 2641 dev_info(smu->adev->dev, "XgmiDpmPstates\n"); 2642 for (i = 0; i < NUM_XGMI_LEVELS; i++) 2643 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]); 2644 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]); 2645 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]); 2646 2647 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides); 2648 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n", 2649 pptable->ReservedEquation0.a, 2650 pptable->ReservedEquation0.b, 2651 pptable->ReservedEquation0.c); 2652 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n", 2653 pptable->ReservedEquation1.a, 2654 pptable->ReservedEquation1.b, 2655 pptable->ReservedEquation1.c); 2656 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n", 2657 pptable->ReservedEquation2.a, 2658 pptable->ReservedEquation2.b, 2659 pptable->ReservedEquation2.c); 2660 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n", 2661 pptable->ReservedEquation3.a, 2662 pptable->ReservedEquation3.b, 2663 pptable->ReservedEquation3.c); 2664 2665 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]); 2666 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]); 2667 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]); 2668 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]); 2669 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]); 2670 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]); 2671 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]); 2672 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]); 2673 2674 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]); 2675 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]); 2676 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]); 2677 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]); 2678 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]); 2679 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]); 2680 2681 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) { 2682 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i); 2683 dev_info(smu->adev->dev, " .Enabled = 0x%x\n", 2684 pptable->I2cControllers[i].Enabled); 2685 dev_info(smu->adev->dev, " .Speed = 0x%x\n", 2686 pptable->I2cControllers[i].Speed); 2687 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n", 2688 pptable->I2cControllers[i].SlaveAddress); 2689 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n", 2690 pptable->I2cControllers[i].ControllerPort); 2691 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n", 2692 pptable->I2cControllers[i].ControllerName); 2693 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n", 2694 pptable->I2cControllers[i].ThermalThrotter); 2695 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n", 2696 pptable->I2cControllers[i].I2cProtocol); 2697 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n", 2698 pptable->I2cControllers[i].PaddingConfig); 2699 } 2700 2701 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl); 2702 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda); 2703 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr); 2704 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]); 2705 2706 dev_info(smu->adev->dev, "Board Parameters:\n"); 2707 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping); 2708 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping); 2709 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping); 2710 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping); 2711 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask); 2712 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask); 2713 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask); 2714 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask); 2715 2716 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent); 2717 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset); 2718 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx); 2719 2720 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent); 2721 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset); 2722 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc); 2723 2724 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent); 2725 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset); 2726 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0); 2727 2728 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent); 2729 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset); 2730 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1); 2731 2732 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio); 2733 2734 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio); 2735 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity); 2736 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio); 2737 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity); 2738 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio); 2739 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity); 2740 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio); 2741 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity); 2742 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0); 2743 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1); 2744 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2); 2745 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask); 2746 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie); 2747 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError); 2748 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]); 2749 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]); 2750 2751 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled); 2752 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent); 2753 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq); 2754 2755 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled); 2756 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent); 2757 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq); 2758 2759 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding); 2760 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq); 2761 2762 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled); 2763 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent); 2764 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq); 2765 2766 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled); 2767 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth); 2768 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]); 2769 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]); 2770 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]); 2771 2772 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower); 2773 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding); 2774 2775 dev_info(smu->adev->dev, "XgmiLinkSpeed\n"); 2776 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 2777 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]); 2778 dev_info(smu->adev->dev, "XgmiLinkWidth\n"); 2779 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 2780 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]); 2781 dev_info(smu->adev->dev, "XgmiFclkFreq\n"); 2782 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 2783 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]); 2784 dev_info(smu->adev->dev, "XgmiSocVoltage\n"); 2785 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 2786 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]); 2787 2788 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled); 2789 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled); 2790 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]); 2791 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]); 2792 2793 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]); 2794 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]); 2795 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]); 2796 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]); 2797 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]); 2798 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]); 2799 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]); 2800 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]); 2801 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]); 2802 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]); 2803 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]); 2804 2805 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]); 2806 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]); 2807 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]); 2808 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]); 2809 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]); 2810 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]); 2811 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]); 2812 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]); 2813 } 2814 2815 static void sienna_cichlid_dump_pptable(struct smu_context *smu) 2816 { 2817 struct smu_table_context *table_context = &smu->smu_table; 2818 PPTable_t *pptable = table_context->driver_pptable; 2819 int i; 2820 2821 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) { 2822 beige_goby_dump_pptable(smu); 2823 return; 2824 } 2825 2826 dev_info(smu->adev->dev, "Dumped PPTable:\n"); 2827 2828 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version); 2829 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]); 2830 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]); 2831 2832 for (i = 0; i < PPT_THROTTLER_COUNT; i++) { 2833 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]); 2834 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]); 2835 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]); 2836 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]); 2837 } 2838 2839 for (i = 0; i < TDC_THROTTLER_COUNT; i++) { 2840 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]); 2841 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]); 2842 } 2843 2844 for (i = 0; i < TEMP_COUNT; i++) { 2845 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]); 2846 } 2847 2848 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit); 2849 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig); 2850 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]); 2851 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]); 2852 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]); 2853 2854 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit); 2855 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) { 2856 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]); 2857 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]); 2858 } 2859 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask); 2860 2861 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask); 2862 2863 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc); 2864 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx); 2865 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx); 2866 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc); 2867 2868 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin); 2869 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin); 2870 2871 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold); 2872 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]); 2873 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]); 2874 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]); 2875 2876 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx); 2877 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc); 2878 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx); 2879 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc); 2880 2881 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx); 2882 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc); 2883 2884 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin); 2885 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin); 2886 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp); 2887 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp); 2888 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp); 2889 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp); 2890 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis); 2891 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis); 2892 2893 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n" 2894 " .VoltageMode = 0x%02x\n" 2895 " .SnapToDiscrete = 0x%02x\n" 2896 " .NumDiscreteLevels = 0x%02x\n" 2897 " .padding = 0x%02x\n" 2898 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2899 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2900 " .SsFmin = 0x%04x\n" 2901 " .Padding_16 = 0x%04x\n", 2902 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode, 2903 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete, 2904 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels, 2905 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding, 2906 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m, 2907 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b, 2908 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a, 2909 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b, 2910 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c, 2911 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin, 2912 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16); 2913 2914 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n" 2915 " .VoltageMode = 0x%02x\n" 2916 " .SnapToDiscrete = 0x%02x\n" 2917 " .NumDiscreteLevels = 0x%02x\n" 2918 " .padding = 0x%02x\n" 2919 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2920 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2921 " .SsFmin = 0x%04x\n" 2922 " .Padding_16 = 0x%04x\n", 2923 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode, 2924 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete, 2925 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels, 2926 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding, 2927 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m, 2928 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b, 2929 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a, 2930 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b, 2931 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c, 2932 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin, 2933 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16); 2934 2935 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n" 2936 " .VoltageMode = 0x%02x\n" 2937 " .SnapToDiscrete = 0x%02x\n" 2938 " .NumDiscreteLevels = 0x%02x\n" 2939 " .padding = 0x%02x\n" 2940 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2941 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2942 " .SsFmin = 0x%04x\n" 2943 " .Padding_16 = 0x%04x\n", 2944 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode, 2945 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete, 2946 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels, 2947 pptable->DpmDescriptor[PPCLK_UCLK].Padding, 2948 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m, 2949 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b, 2950 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a, 2951 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b, 2952 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c, 2953 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin, 2954 pptable->DpmDescriptor[PPCLK_UCLK].Padding16); 2955 2956 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n" 2957 " .VoltageMode = 0x%02x\n" 2958 " .SnapToDiscrete = 0x%02x\n" 2959 " .NumDiscreteLevels = 0x%02x\n" 2960 " .padding = 0x%02x\n" 2961 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2962 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2963 " .SsFmin = 0x%04x\n" 2964 " .Padding_16 = 0x%04x\n", 2965 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode, 2966 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete, 2967 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels, 2968 pptable->DpmDescriptor[PPCLK_FCLK].Padding, 2969 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m, 2970 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b, 2971 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a, 2972 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b, 2973 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c, 2974 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin, 2975 pptable->DpmDescriptor[PPCLK_FCLK].Padding16); 2976 2977 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n" 2978 " .VoltageMode = 0x%02x\n" 2979 " .SnapToDiscrete = 0x%02x\n" 2980 " .NumDiscreteLevels = 0x%02x\n" 2981 " .padding = 0x%02x\n" 2982 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2983 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2984 " .SsFmin = 0x%04x\n" 2985 " .Padding_16 = 0x%04x\n", 2986 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode, 2987 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete, 2988 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels, 2989 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding, 2990 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m, 2991 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b, 2992 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a, 2993 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b, 2994 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c, 2995 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin, 2996 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16); 2997 2998 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n" 2999 " .VoltageMode = 0x%02x\n" 3000 " .SnapToDiscrete = 0x%02x\n" 3001 " .NumDiscreteLevels = 0x%02x\n" 3002 " .padding = 0x%02x\n" 3003 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3004 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3005 " .SsFmin = 0x%04x\n" 3006 " .Padding_16 = 0x%04x\n", 3007 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode, 3008 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete, 3009 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels, 3010 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding, 3011 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m, 3012 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b, 3013 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a, 3014 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b, 3015 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c, 3016 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin, 3017 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16); 3018 3019 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n" 3020 " .VoltageMode = 0x%02x\n" 3021 " .SnapToDiscrete = 0x%02x\n" 3022 " .NumDiscreteLevels = 0x%02x\n" 3023 " .padding = 0x%02x\n" 3024 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3025 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3026 " .SsFmin = 0x%04x\n" 3027 " .Padding_16 = 0x%04x\n", 3028 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode, 3029 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete, 3030 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels, 3031 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding, 3032 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m, 3033 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b, 3034 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a, 3035 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b, 3036 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c, 3037 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin, 3038 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16); 3039 3040 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n" 3041 " .VoltageMode = 0x%02x\n" 3042 " .SnapToDiscrete = 0x%02x\n" 3043 " .NumDiscreteLevels = 0x%02x\n" 3044 " .padding = 0x%02x\n" 3045 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3046 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3047 " .SsFmin = 0x%04x\n" 3048 " .Padding_16 = 0x%04x\n", 3049 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode, 3050 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete, 3051 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels, 3052 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding, 3053 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m, 3054 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b, 3055 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a, 3056 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b, 3057 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c, 3058 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin, 3059 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16); 3060 3061 dev_info(smu->adev->dev, "FreqTableGfx\n"); 3062 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) 3063 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]); 3064 3065 dev_info(smu->adev->dev, "FreqTableVclk\n"); 3066 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++) 3067 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]); 3068 3069 dev_info(smu->adev->dev, "FreqTableDclk\n"); 3070 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++) 3071 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]); 3072 3073 dev_info(smu->adev->dev, "FreqTableSocclk\n"); 3074 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) 3075 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]); 3076 3077 dev_info(smu->adev->dev, "FreqTableUclk\n"); 3078 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 3079 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]); 3080 3081 dev_info(smu->adev->dev, "FreqTableFclk\n"); 3082 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) 3083 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]); 3084 3085 dev_info(smu->adev->dev, "DcModeMaxFreq\n"); 3086 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]); 3087 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]); 3088 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]); 3089 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]); 3090 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]); 3091 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]); 3092 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]); 3093 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]); 3094 3095 dev_info(smu->adev->dev, "FreqTableUclkDiv\n"); 3096 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 3097 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]); 3098 3099 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq); 3100 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding); 3101 3102 dev_info(smu->adev->dev, "Mp0clkFreq\n"); 3103 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 3104 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]); 3105 3106 dev_info(smu->adev->dev, "Mp0DpmVoltage\n"); 3107 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 3108 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]); 3109 3110 dev_info(smu->adev->dev, "MemVddciVoltage\n"); 3111 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 3112 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]); 3113 3114 dev_info(smu->adev->dev, "MemMvddVoltage\n"); 3115 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 3116 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]); 3117 3118 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry); 3119 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit); 3120 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle); 3121 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource); 3122 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding); 3123 3124 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask); 3125 3126 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask); 3127 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask); 3128 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]); 3129 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow); 3130 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]); 3131 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]); 3132 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]); 3133 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]); 3134 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt); 3135 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt); 3136 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt); 3137 3138 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage); 3139 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime); 3140 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime); 3141 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum); 3142 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis); 3143 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout); 3144 3145 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]); 3146 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]); 3147 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]); 3148 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]); 3149 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]); 3150 3151 dev_info(smu->adev->dev, "FlopsPerByteTable\n"); 3152 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++) 3153 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]); 3154 3155 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv); 3156 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]); 3157 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]); 3158 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]); 3159 3160 dev_info(smu->adev->dev, "UclkDpmPstates\n"); 3161 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 3162 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]); 3163 3164 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n"); 3165 dev_info(smu->adev->dev, " .Fmin = 0x%x\n", 3166 pptable->UclkDpmSrcFreqRange.Fmin); 3167 dev_info(smu->adev->dev, " .Fmax = 0x%x\n", 3168 pptable->UclkDpmSrcFreqRange.Fmax); 3169 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n"); 3170 dev_info(smu->adev->dev, " .Fmin = 0x%x\n", 3171 pptable->UclkDpmTargFreqRange.Fmin); 3172 dev_info(smu->adev->dev, " .Fmax = 0x%x\n", 3173 pptable->UclkDpmTargFreqRange.Fmax); 3174 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq); 3175 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding); 3176 3177 dev_info(smu->adev->dev, "PcieGenSpeed\n"); 3178 for (i = 0; i < NUM_LINK_LEVELS; i++) 3179 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]); 3180 3181 dev_info(smu->adev->dev, "PcieLaneCount\n"); 3182 for (i = 0; i < NUM_LINK_LEVELS; i++) 3183 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]); 3184 3185 dev_info(smu->adev->dev, "LclkFreq\n"); 3186 for (i = 0; i < NUM_LINK_LEVELS; i++) 3187 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]); 3188 3189 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp); 3190 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp); 3191 3192 dev_info(smu->adev->dev, "FanGain\n"); 3193 for (i = 0; i < TEMP_COUNT; i++) 3194 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]); 3195 3196 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin); 3197 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm); 3198 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm); 3199 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm); 3200 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm); 3201 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature); 3202 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk); 3203 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16); 3204 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect); 3205 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding); 3206 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable); 3207 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev); 3208 3209 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta); 3210 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta); 3211 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta); 3212 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved); 3213 3214 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]); 3215 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]); 3216 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect); 3217 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs); 3218 3219 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", 3220 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a, 3221 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b, 3222 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c); 3223 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", 3224 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a, 3225 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b, 3226 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c); 3227 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n", 3228 pptable->dBtcGbGfxPll.a, 3229 pptable->dBtcGbGfxPll.b, 3230 pptable->dBtcGbGfxPll.c); 3231 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n", 3232 pptable->dBtcGbGfxDfll.a, 3233 pptable->dBtcGbGfxDfll.b, 3234 pptable->dBtcGbGfxDfll.c); 3235 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n", 3236 pptable->dBtcGbSoc.a, 3237 pptable->dBtcGbSoc.b, 3238 pptable->dBtcGbSoc.c); 3239 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n", 3240 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m, 3241 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b); 3242 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n", 3243 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m, 3244 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b); 3245 3246 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n"); 3247 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) { 3248 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n", 3249 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]); 3250 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n", 3251 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]); 3252 } 3253 3254 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", 3255 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a, 3256 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b, 3257 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c); 3258 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", 3259 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a, 3260 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b, 3261 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c); 3262 3263 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]); 3264 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]); 3265 3266 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]); 3267 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]); 3268 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]); 3269 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]); 3270 3271 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]); 3272 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]); 3273 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]); 3274 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]); 3275 3276 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]); 3277 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]); 3278 3279 dev_info(smu->adev->dev, "XgmiDpmPstates\n"); 3280 for (i = 0; i < NUM_XGMI_LEVELS; i++) 3281 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]); 3282 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]); 3283 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]); 3284 3285 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides); 3286 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n", 3287 pptable->ReservedEquation0.a, 3288 pptable->ReservedEquation0.b, 3289 pptable->ReservedEquation0.c); 3290 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n", 3291 pptable->ReservedEquation1.a, 3292 pptable->ReservedEquation1.b, 3293 pptable->ReservedEquation1.c); 3294 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n", 3295 pptable->ReservedEquation2.a, 3296 pptable->ReservedEquation2.b, 3297 pptable->ReservedEquation2.c); 3298 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n", 3299 pptable->ReservedEquation3.a, 3300 pptable->ReservedEquation3.b, 3301 pptable->ReservedEquation3.c); 3302 3303 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]); 3304 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]); 3305 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]); 3306 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]); 3307 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]); 3308 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]); 3309 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]); 3310 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]); 3311 3312 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]); 3313 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]); 3314 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]); 3315 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]); 3316 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]); 3317 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]); 3318 3319 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) { 3320 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i); 3321 dev_info(smu->adev->dev, " .Enabled = 0x%x\n", 3322 pptable->I2cControllers[i].Enabled); 3323 dev_info(smu->adev->dev, " .Speed = 0x%x\n", 3324 pptable->I2cControllers[i].Speed); 3325 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n", 3326 pptable->I2cControllers[i].SlaveAddress); 3327 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n", 3328 pptable->I2cControllers[i].ControllerPort); 3329 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n", 3330 pptable->I2cControllers[i].ControllerName); 3331 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n", 3332 pptable->I2cControllers[i].ThermalThrotter); 3333 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n", 3334 pptable->I2cControllers[i].I2cProtocol); 3335 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n", 3336 pptable->I2cControllers[i].PaddingConfig); 3337 } 3338 3339 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl); 3340 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda); 3341 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr); 3342 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]); 3343 3344 dev_info(smu->adev->dev, "Board Parameters:\n"); 3345 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping); 3346 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping); 3347 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping); 3348 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping); 3349 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask); 3350 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask); 3351 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask); 3352 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask); 3353 3354 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent); 3355 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset); 3356 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx); 3357 3358 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent); 3359 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset); 3360 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc); 3361 3362 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent); 3363 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset); 3364 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0); 3365 3366 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent); 3367 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset); 3368 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1); 3369 3370 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio); 3371 3372 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio); 3373 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity); 3374 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio); 3375 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity); 3376 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio); 3377 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity); 3378 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio); 3379 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity); 3380 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0); 3381 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1); 3382 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2); 3383 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask); 3384 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie); 3385 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError); 3386 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]); 3387 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]); 3388 3389 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled); 3390 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent); 3391 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq); 3392 3393 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled); 3394 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent); 3395 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq); 3396 3397 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding); 3398 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq); 3399 3400 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled); 3401 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent); 3402 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq); 3403 3404 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled); 3405 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth); 3406 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]); 3407 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]); 3408 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]); 3409 3410 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower); 3411 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding); 3412 3413 dev_info(smu->adev->dev, "XgmiLinkSpeed\n"); 3414 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3415 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]); 3416 dev_info(smu->adev->dev, "XgmiLinkWidth\n"); 3417 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3418 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]); 3419 dev_info(smu->adev->dev, "XgmiFclkFreq\n"); 3420 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3421 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]); 3422 dev_info(smu->adev->dev, "XgmiSocVoltage\n"); 3423 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3424 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]); 3425 3426 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled); 3427 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled); 3428 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]); 3429 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]); 3430 3431 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]); 3432 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]); 3433 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]); 3434 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]); 3435 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]); 3436 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]); 3437 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]); 3438 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]); 3439 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]); 3440 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]); 3441 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]); 3442 3443 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]); 3444 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]); 3445 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]); 3446 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]); 3447 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]); 3448 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]); 3449 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]); 3450 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]); 3451 } 3452 3453 static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap, 3454 struct i2c_msg *msg, int num_msgs) 3455 { 3456 struct amdgpu_device *adev = to_amdgpu_device(i2c_adap); 3457 struct smu_table_context *smu_table = &adev->smu.smu_table; 3458 struct smu_table *table = &smu_table->driver_table; 3459 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 3460 int i, j, r, c; 3461 u16 dir; 3462 3463 req = kzalloc(sizeof(*req), GFP_KERNEL); 3464 if (!req) 3465 return -ENOMEM; 3466 3467 req->I2CcontrollerPort = 1; 3468 req->I2CSpeed = I2C_SPEED_FAST_400K; 3469 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 3470 dir = msg[0].flags & I2C_M_RD; 3471 3472 for (c = i = 0; i < num_msgs; i++) { 3473 for (j = 0; j < msg[i].len; j++, c++) { 3474 SwI2cCmd_t *cmd = &req->SwI2cCmds[c]; 3475 3476 if (!(msg[i].flags & I2C_M_RD)) { 3477 /* write */ 3478 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK; 3479 cmd->ReadWriteData = msg[i].buf[j]; 3480 } 3481 3482 if ((dir ^ msg[i].flags) & I2C_M_RD) { 3483 /* The direction changes. 3484 */ 3485 dir = msg[i].flags & I2C_M_RD; 3486 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK; 3487 } 3488 3489 req->NumCmds++; 3490 3491 /* 3492 * Insert STOP if we are at the last byte of either last 3493 * message for the transaction or the client explicitly 3494 * requires a STOP at this particular message. 3495 */ 3496 if ((j == msg[i].len - 1) && 3497 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) { 3498 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK; 3499 cmd->CmdConfig |= CMDCONFIG_STOP_MASK; 3500 } 3501 } 3502 } 3503 mutex_lock(&adev->smu.mutex); 3504 r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 3505 mutex_unlock(&adev->smu.mutex); 3506 if (r) 3507 goto fail; 3508 3509 for (c = i = 0; i < num_msgs; i++) { 3510 if (!(msg[i].flags & I2C_M_RD)) { 3511 c += msg[i].len; 3512 continue; 3513 } 3514 for (j = 0; j < msg[i].len; j++, c++) { 3515 SwI2cCmd_t *cmd = &res->SwI2cCmds[c]; 3516 3517 msg[i].buf[j] = cmd->ReadWriteData; 3518 } 3519 } 3520 r = num_msgs; 3521 fail: 3522 kfree(req); 3523 return r; 3524 } 3525 3526 static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap) 3527 { 3528 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 3529 } 3530 3531 3532 static const struct i2c_algorithm sienna_cichlid_i2c_algo = { 3533 .master_xfer = sienna_cichlid_i2c_xfer, 3534 .functionality = sienna_cichlid_i2c_func, 3535 }; 3536 3537 static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = { 3538 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN, 3539 .max_read_len = MAX_SW_I2C_COMMANDS, 3540 .max_write_len = MAX_SW_I2C_COMMANDS, 3541 .max_comb_1st_msg_len = 2, 3542 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 3543 }; 3544 3545 static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control) 3546 { 3547 struct amdgpu_device *adev = to_amdgpu_device(control); 3548 int res; 3549 3550 control->owner = THIS_MODULE; 3551 control->class = I2C_CLASS_HWMON; 3552 control->dev.parent = &adev->pdev->dev; 3553 control->algo = &sienna_cichlid_i2c_algo; 3554 snprintf(control->name, sizeof(control->name), "AMDGPU SMU"); 3555 control->quirks = &sienna_cichlid_i2c_control_quirks; 3556 3557 res = i2c_add_adapter(control); 3558 if (res) 3559 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 3560 3561 return res; 3562 } 3563 3564 static void sienna_cichlid_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control) 3565 { 3566 i2c_del_adapter(control); 3567 } 3568 3569 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu, 3570 void **table) 3571 { 3572 struct smu_table_context *smu_table = &smu->smu_table; 3573 struct gpu_metrics_v1_3 *gpu_metrics = 3574 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 3575 SmuMetricsExternal_t metrics_external; 3576 SmuMetrics_t *metrics = 3577 &(metrics_external.SmuMetrics); 3578 SmuMetrics_V2_t *metrics_v2 = 3579 &(metrics_external.SmuMetrics_V2); 3580 struct amdgpu_device *adev = smu->adev; 3581 bool use_metrics_v2 = ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 3582 (smu->smc_fw_version >= 0x3A4300)) ? true : false; 3583 uint16_t average_gfx_activity; 3584 int ret = 0; 3585 3586 mutex_lock(&smu->metrics_lock); 3587 ret = smu_cmn_get_metrics_table_locked(smu, 3588 &metrics_external, 3589 true); 3590 if (ret) { 3591 mutex_unlock(&smu->metrics_lock); 3592 return ret; 3593 } 3594 3595 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 3596 3597 gpu_metrics->temperature_edge = 3598 use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge; 3599 gpu_metrics->temperature_hotspot = 3600 use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot; 3601 gpu_metrics->temperature_mem = 3602 use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem; 3603 gpu_metrics->temperature_vrgfx = 3604 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx; 3605 gpu_metrics->temperature_vrsoc = 3606 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc; 3607 gpu_metrics->temperature_vrmem = 3608 use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0; 3609 3610 gpu_metrics->average_gfx_activity = 3611 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity; 3612 gpu_metrics->average_umc_activity = 3613 use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity; 3614 gpu_metrics->average_mm_activity = 3615 use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage; 3616 3617 gpu_metrics->average_socket_power = 3618 use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower; 3619 gpu_metrics->energy_accumulator = 3620 use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator; 3621 3622 average_gfx_activity = use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity; 3623 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD) 3624 gpu_metrics->average_gfxclk_frequency = 3625 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs : metrics->AverageGfxclkFrequencyPostDs; 3626 else 3627 gpu_metrics->average_gfxclk_frequency = 3628 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs : metrics->AverageGfxclkFrequencyPreDs; 3629 gpu_metrics->average_uclk_frequency = 3630 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs : metrics->AverageUclkFrequencyPostDs; 3631 gpu_metrics->average_vclk0_frequency = 3632 use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency; 3633 gpu_metrics->average_dclk0_frequency = 3634 use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency; 3635 gpu_metrics->average_vclk1_frequency = 3636 use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency; 3637 gpu_metrics->average_dclk1_frequency = 3638 use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency; 3639 3640 gpu_metrics->current_gfxclk = 3641 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK]; 3642 gpu_metrics->current_socclk = 3643 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK]; 3644 gpu_metrics->current_uclk = 3645 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK]; 3646 gpu_metrics->current_vclk0 = 3647 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0]; 3648 gpu_metrics->current_dclk0 = 3649 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0]; 3650 gpu_metrics->current_vclk1 = 3651 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1]; 3652 gpu_metrics->current_dclk1 = 3653 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1]; 3654 3655 gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu); 3656 gpu_metrics->indep_throttle_status = 3657 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status, 3658 sienna_cichlid_throttler_map); 3659 3660 gpu_metrics->current_fan_speed = use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed; 3661 3662 if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) || 3663 ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) { 3664 gpu_metrics->pcie_link_width = use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth; 3665 gpu_metrics->pcie_link_speed = link_speed[use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate]; 3666 } else { 3667 gpu_metrics->pcie_link_width = 3668 smu_v11_0_get_current_pcie_link_width(smu); 3669 gpu_metrics->pcie_link_speed = 3670 smu_v11_0_get_current_pcie_link_speed(smu); 3671 } 3672 3673 mutex_unlock(&smu->metrics_lock); 3674 3675 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 3676 3677 *table = (void *)gpu_metrics; 3678 3679 return sizeof(struct gpu_metrics_v1_3); 3680 } 3681 3682 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu) 3683 { 3684 struct smu_table_context *table_context = &smu->smu_table; 3685 PPTable_t *smc_pptable = table_context->driver_pptable; 3686 3687 /* 3688 * Skip the MGpuFanBoost setting for those ASICs 3689 * which do not support it 3690 */ 3691 if (!smc_pptable->MGpuFanBoostLimitRpm) 3692 return 0; 3693 3694 return smu_cmn_send_smc_msg_with_param(smu, 3695 SMU_MSG_SetMGpuFanBoostLimitRpm, 3696 0, 3697 NULL); 3698 } 3699 3700 static int sienna_cichlid_gpo_control(struct smu_context *smu, 3701 bool enablement) 3702 { 3703 uint32_t smu_version; 3704 int ret = 0; 3705 3706 3707 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) { 3708 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 3709 if (ret) 3710 return ret; 3711 3712 if (enablement) { 3713 if (smu_version < 0x003a2500) { 3714 ret = smu_cmn_send_smc_msg_with_param(smu, 3715 SMU_MSG_SetGpoFeaturePMask, 3716 GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK, 3717 NULL); 3718 } else { 3719 ret = smu_cmn_send_smc_msg_with_param(smu, 3720 SMU_MSG_DisallowGpo, 3721 0, 3722 NULL); 3723 } 3724 } else { 3725 if (smu_version < 0x003a2500) { 3726 ret = smu_cmn_send_smc_msg_with_param(smu, 3727 SMU_MSG_SetGpoFeaturePMask, 3728 0, 3729 NULL); 3730 } else { 3731 ret = smu_cmn_send_smc_msg_with_param(smu, 3732 SMU_MSG_DisallowGpo, 3733 1, 3734 NULL); 3735 } 3736 } 3737 } 3738 3739 return ret; 3740 } 3741 3742 static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu) 3743 { 3744 uint32_t smu_version; 3745 int ret = 0; 3746 3747 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 3748 if (ret) 3749 return ret; 3750 3751 /* 3752 * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45 3753 * onwards PMFWs. 3754 */ 3755 if (smu_version < 0x003A2D00) 3756 return 0; 3757 3758 return smu_cmn_send_smc_msg_with_param(smu, 3759 SMU_MSG_Enable2ndUSB20Port, 3760 smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ? 3761 1 : 0, 3762 NULL); 3763 } 3764 3765 static int sienna_cichlid_system_features_control(struct smu_context *smu, 3766 bool en) 3767 { 3768 int ret = 0; 3769 3770 if (en) { 3771 ret = sienna_cichlid_notify_2nd_usb20_port(smu); 3772 if (ret) 3773 return ret; 3774 } 3775 3776 return smu_v11_0_system_features_control(smu, en); 3777 } 3778 3779 static int sienna_cichlid_set_mp1_state(struct smu_context *smu, 3780 enum pp_mp1_state mp1_state) 3781 { 3782 int ret; 3783 3784 switch (mp1_state) { 3785 case PP_MP1_STATE_UNLOAD: 3786 ret = smu_cmn_set_mp1_state(smu, mp1_state); 3787 break; 3788 default: 3789 /* Ignore others */ 3790 ret = 0; 3791 } 3792 3793 return ret; 3794 } 3795 3796 static const struct pptable_funcs sienna_cichlid_ppt_funcs = { 3797 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask, 3798 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table, 3799 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable, 3800 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable, 3801 .i2c_init = sienna_cichlid_i2c_control_init, 3802 .i2c_fini = sienna_cichlid_i2c_control_fini, 3803 .print_clk_levels = sienna_cichlid_print_clk_levels, 3804 .force_clk_levels = sienna_cichlid_force_clk_levels, 3805 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk, 3806 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed, 3807 .display_config_changed = sienna_cichlid_display_config_changed, 3808 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config, 3809 .is_dpm_running = sienna_cichlid_is_dpm_running, 3810 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm, 3811 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm, 3812 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode, 3813 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode, 3814 .set_watermarks_table = sienna_cichlid_set_watermarks_table, 3815 .read_sensor = sienna_cichlid_read_sensor, 3816 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states, 3817 .set_performance_level = smu_v11_0_set_performance_level, 3818 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range, 3819 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch, 3820 .get_power_limit = sienna_cichlid_get_power_limit, 3821 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters, 3822 .dump_pptable = sienna_cichlid_dump_pptable, 3823 .init_microcode = smu_v11_0_init_microcode, 3824 .load_microcode = smu_v11_0_load_microcode, 3825 .init_smc_tables = sienna_cichlid_init_smc_tables, 3826 .fini_smc_tables = smu_v11_0_fini_smc_tables, 3827 .init_power = smu_v11_0_init_power, 3828 .fini_power = smu_v11_0_fini_power, 3829 .check_fw_status = smu_v11_0_check_fw_status, 3830 .setup_pptable = sienna_cichlid_setup_pptable, 3831 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, 3832 .check_fw_version = smu_v11_0_check_fw_version, 3833 .write_pptable = smu_cmn_write_pptable, 3834 .set_driver_table_location = smu_v11_0_set_driver_table_location, 3835 .set_tool_table_location = smu_v11_0_set_tool_table_location, 3836 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 3837 .system_features_control = sienna_cichlid_system_features_control, 3838 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 3839 .send_smc_msg = smu_cmn_send_smc_msg, 3840 .init_display_count = NULL, 3841 .set_allowed_mask = smu_v11_0_set_allowed_mask, 3842 .get_enabled_mask = smu_cmn_get_enabled_mask, 3843 .feature_is_enabled = smu_cmn_feature_is_enabled, 3844 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 3845 .notify_display_change = NULL, 3846 .set_power_limit = smu_v11_0_set_power_limit, 3847 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks, 3848 .enable_thermal_alert = smu_v11_0_enable_thermal_alert, 3849 .disable_thermal_alert = smu_v11_0_disable_thermal_alert, 3850 .set_min_dcef_deep_sleep = NULL, 3851 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request, 3852 .get_fan_control_mode = smu_v11_0_get_fan_control_mode, 3853 .set_fan_control_mode = smu_v11_0_set_fan_control_mode, 3854 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm, 3855 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm, 3856 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate, 3857 .gfx_off_control = smu_v11_0_gfx_off_control, 3858 .register_irq_handler = smu_v11_0_register_irq_handler, 3859 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme, 3860 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc, 3861 .baco_is_support = smu_v11_0_baco_is_support, 3862 .baco_get_state = smu_v11_0_baco_get_state, 3863 .baco_set_state = smu_v11_0_baco_set_state, 3864 .baco_enter = sienna_cichlid_baco_enter, 3865 .baco_exit = sienna_cichlid_baco_exit, 3866 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported, 3867 .mode1_reset = smu_v11_0_mode1_reset, 3868 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq, 3869 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, 3870 .set_default_od_settings = sienna_cichlid_set_default_od_settings, 3871 .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table, 3872 .restore_user_od_settings = smu_v11_0_restore_user_od_settings, 3873 .run_btc = sienna_cichlid_run_btc, 3874 .set_power_source = smu_v11_0_set_power_source, 3875 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 3876 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 3877 .get_gpu_metrics = sienna_cichlid_get_gpu_metrics, 3878 .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost, 3879 .gfx_ulv_control = smu_v11_0_gfx_ulv_control, 3880 .deep_sleep_control = smu_v11_0_deep_sleep_control, 3881 .get_fan_parameters = sienna_cichlid_get_fan_parameters, 3882 .interrupt_work = smu_v11_0_interrupt_work, 3883 .gpo_control = sienna_cichlid_gpo_control, 3884 .set_mp1_state = sienna_cichlid_set_mp1_state, 3885 }; 3886 3887 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu) 3888 { 3889 smu->ppt_funcs = &sienna_cichlid_ppt_funcs; 3890 smu->message_map = sienna_cichlid_message_map; 3891 smu->clock_map = sienna_cichlid_clk_map; 3892 smu->feature_map = sienna_cichlid_feature_mask_map; 3893 smu->table_map = sienna_cichlid_table_map; 3894 smu->pwr_src_map = sienna_cichlid_pwr_src_map; 3895 smu->workload_map = sienna_cichlid_workload_map; 3896 } 3897