1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include <linux/pci.h> 28 #include <linux/i2c.h> 29 #include "amdgpu.h" 30 #include "amdgpu_dpm.h" 31 #include "amdgpu_smu.h" 32 #include "atomfirmware.h" 33 #include "amdgpu_atomfirmware.h" 34 #include "amdgpu_atombios.h" 35 #include "smu_v11_0.h" 36 #include "smu11_driver_if_sienna_cichlid.h" 37 #include "soc15_common.h" 38 #include "atom.h" 39 #include "sienna_cichlid_ppt.h" 40 #include "smu_v11_0_7_pptable.h" 41 #include "smu_v11_0_7_ppsmc.h" 42 #include "nbio/nbio_2_3_offset.h" 43 #include "nbio/nbio_2_3_sh_mask.h" 44 #include "thm/thm_11_0_2_offset.h" 45 #include "thm/thm_11_0_2_sh_mask.h" 46 #include "mp/mp_11_0_offset.h" 47 #include "mp/mp_11_0_sh_mask.h" 48 49 #include "asic_reg/mp/mp_11_0_sh_mask.h" 50 #include "amdgpu_ras.h" 51 #include "smu_cmn.h" 52 53 /* 54 * DO NOT use these for err/warn/info/debug messages. 55 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 56 * They are more MGPU friendly. 57 */ 58 #undef pr_err 59 #undef pr_warn 60 #undef pr_info 61 #undef pr_debug 62 63 #define FEATURE_MASK(feature) (1ULL << feature) 64 #define SMC_DPM_FEATURE ( \ 65 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \ 66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \ 72 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)) 73 74 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15 75 76 #define GET_PPTABLE_MEMBER(field, member) do {\ 77 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))\ 78 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\ 79 else\ 80 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\ 81 } while(0) 82 83 /* STB FIFO depth is in 64bit units */ 84 #define SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES 8 85 86 /* 87 * SMU support ECCTABLE since version 58.70.0, 88 * use this to check whether ECCTABLE feature is supported. 89 */ 90 #define SUPPORT_ECCTABLE_SMU_VERSION 0x003a4600 91 92 static int get_table_size(struct smu_context *smu) 93 { 94 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) 95 return sizeof(PPTable_beige_goby_t); 96 else 97 return sizeof(PPTable_t); 98 } 99 100 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = { 101 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 102 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 103 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 104 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0), 105 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), 106 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 107 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 108 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1), 109 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1), 110 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1), 111 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1), 112 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1), 113 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1), 114 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 115 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 116 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 117 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 118 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 119 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 120 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 121 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 122 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 123 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 124 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), 125 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1), 126 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), 127 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1), 128 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 129 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), 130 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), 131 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 132 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0), 133 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0), 134 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0), 135 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0), 136 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0), 137 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0), 138 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0), 139 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0), 140 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1), 141 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 142 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 143 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 144 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1), 145 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0), 146 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 147 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 148 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 149 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 150 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0), 151 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0), 152 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0), 153 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0), 154 MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0), 155 MSG_MAP(DisallowGpo, PPSMC_MSG_DisallowGpo, 0), 156 MSG_MAP(Enable2ndUSB20Port, PPSMC_MSG_Enable2ndUSB20Port, 0), 157 MSG_MAP(DriverMode2Reset, PPSMC_MSG_DriverMode2Reset, 0), 158 }; 159 160 static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = { 161 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 162 CLK_MAP(SCLK, PPCLK_GFXCLK), 163 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 164 CLK_MAP(FCLK, PPCLK_FCLK), 165 CLK_MAP(UCLK, PPCLK_UCLK), 166 CLK_MAP(MCLK, PPCLK_UCLK), 167 CLK_MAP(DCLK, PPCLK_DCLK_0), 168 CLK_MAP(DCLK1, PPCLK_DCLK_1), 169 CLK_MAP(VCLK, PPCLK_VCLK_0), 170 CLK_MAP(VCLK1, PPCLK_VCLK_1), 171 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK), 172 CLK_MAP(DISPCLK, PPCLK_DISPCLK), 173 CLK_MAP(PIXCLK, PPCLK_PIXCLK), 174 CLK_MAP(PHYCLK, PPCLK_PHYCLK), 175 }; 176 177 static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = { 178 FEA_MAP(DPM_PREFETCHER), 179 FEA_MAP(DPM_GFXCLK), 180 FEA_MAP(DPM_GFX_GPO), 181 FEA_MAP(DPM_UCLK), 182 FEA_MAP(DPM_FCLK), 183 FEA_MAP(DPM_SOCCLK), 184 FEA_MAP(DPM_MP0CLK), 185 FEA_MAP(DPM_LINK), 186 FEA_MAP(DPM_DCEFCLK), 187 FEA_MAP(DPM_XGMI), 188 FEA_MAP(MEM_VDDCI_SCALING), 189 FEA_MAP(MEM_MVDD_SCALING), 190 FEA_MAP(DS_GFXCLK), 191 FEA_MAP(DS_SOCCLK), 192 FEA_MAP(DS_FCLK), 193 FEA_MAP(DS_LCLK), 194 FEA_MAP(DS_DCEFCLK), 195 FEA_MAP(DS_UCLK), 196 FEA_MAP(GFX_ULV), 197 FEA_MAP(FW_DSTATE), 198 FEA_MAP(GFXOFF), 199 FEA_MAP(BACO), 200 FEA_MAP(MM_DPM_PG), 201 FEA_MAP(RSMU_SMN_CG), 202 FEA_MAP(PPT), 203 FEA_MAP(TDC), 204 FEA_MAP(APCC_PLUS), 205 FEA_MAP(GTHR), 206 FEA_MAP(ACDC), 207 FEA_MAP(VR0HOT), 208 FEA_MAP(VR1HOT), 209 FEA_MAP(FW_CTF), 210 FEA_MAP(FAN_CONTROL), 211 FEA_MAP(THERMAL), 212 FEA_MAP(GFX_DCS), 213 FEA_MAP(RM), 214 FEA_MAP(LED_DISPLAY), 215 FEA_MAP(GFX_SS), 216 FEA_MAP(OUT_OF_BAND_MONITOR), 217 FEA_MAP(TEMP_DEPENDENT_VMIN), 218 FEA_MAP(MMHUB_PG), 219 FEA_MAP(ATHUB_PG), 220 FEA_MAP(APCC_DFLL), 221 }; 222 223 static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = { 224 TAB_MAP(PPTABLE), 225 TAB_MAP(WATERMARKS), 226 TAB_MAP(AVFS_PSM_DEBUG), 227 TAB_MAP(AVFS_FUSE_OVERRIDE), 228 TAB_MAP(PMSTATUSLOG), 229 TAB_MAP(SMU_METRICS), 230 TAB_MAP(DRIVER_SMU_CONFIG), 231 TAB_MAP(ACTIVITY_MONITOR_COEFF), 232 TAB_MAP(OVERDRIVE), 233 TAB_MAP(I2C_COMMANDS), 234 TAB_MAP(PACE), 235 TAB_MAP(ECCINFO), 236 }; 237 238 static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { 239 PWR_MAP(AC), 240 PWR_MAP(DC), 241 }; 242 243 static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 244 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), 245 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 246 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 247 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 248 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 249 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 250 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 251 }; 252 253 static const uint8_t sienna_cichlid_throttler_map[] = { 254 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT), 255 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT), 256 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 257 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 258 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 259 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT), 260 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 261 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT), 262 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT), 263 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 264 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 265 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 266 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 267 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT), 268 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT), 269 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), 270 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT), 271 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT), 272 }; 273 274 static int 275 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, 276 uint32_t *feature_mask, uint32_t num) 277 { 278 struct amdgpu_device *adev = smu->adev; 279 280 if (num > 2) 281 return -EINVAL; 282 283 memset(feature_mask, 0, sizeof(uint32_t) * num); 284 285 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) 286 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT) 287 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) 288 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) 289 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) 290 | FEATURE_MASK(FEATURE_DS_FCLK_BIT) 291 | FEATURE_MASK(FEATURE_DS_UCLK_BIT) 292 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) 293 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT) 294 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) 295 | FEATURE_MASK(FEATURE_GFX_SS_BIT) 296 | FEATURE_MASK(FEATURE_VR0HOT_BIT) 297 | FEATURE_MASK(FEATURE_PPT_BIT) 298 | FEATURE_MASK(FEATURE_TDC_BIT) 299 | FEATURE_MASK(FEATURE_BACO_BIT) 300 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) 301 | FEATURE_MASK(FEATURE_FW_CTF_BIT) 302 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) 303 | FEATURE_MASK(FEATURE_THERMAL_BIT) 304 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT); 305 306 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { 307 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 308 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT); 309 } 310 311 if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) && 312 (adev->ip_versions[MP1_HWIP][0] > IP_VERSION(11, 0, 7)) && 313 !(adev->flags & AMD_IS_APU)) 314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT); 315 316 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) 317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) 318 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) 319 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); 320 321 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) 322 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); 323 324 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) 325 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); 326 327 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) 328 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 329 330 if (adev->pm.pp_feature & PP_ULV_MASK) 331 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); 332 333 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) 334 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 335 336 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 337 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); 338 339 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB) 340 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT); 341 342 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) 343 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); 344 345 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN || 346 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG) 347 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT); 348 349 if (smu->dc_controlled_by_gpio) 350 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT); 351 352 if (amdgpu_device_should_use_aspm(adev)) 353 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT); 354 355 return 0; 356 } 357 358 static void sienna_cichlid_check_bxco_support(struct smu_context *smu) 359 { 360 struct smu_table_context *table_context = &smu->smu_table; 361 struct smu_11_0_7_powerplay_table *powerplay_table = 362 table_context->power_play_table; 363 struct smu_baco_context *smu_baco = &smu->smu_baco; 364 struct amdgpu_device *adev = smu->adev; 365 uint32_t val; 366 367 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) { 368 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); 369 smu_baco->platform_support = 370 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : 371 false; 372 373 /* 374 * Disable BACO entry/exit completely on below SKUs to 375 * avoid hardware intermittent failures. 376 */ 377 if (((adev->pdev->device == 0x73A1) && 378 (adev->pdev->revision == 0x00)) || 379 ((adev->pdev->device == 0x73BF) && 380 (adev->pdev->revision == 0xCF)) || 381 ((adev->pdev->device == 0x7422) && 382 (adev->pdev->revision == 0x00)) || 383 ((adev->pdev->device == 0x73A3) && 384 (adev->pdev->revision == 0x00)) || 385 ((adev->pdev->device == 0x73E3) && 386 (adev->pdev->revision == 0x00))) 387 smu_baco->platform_support = false; 388 389 } 390 } 391 392 static void sienna_cichlid_check_fan_support(struct smu_context *smu) 393 { 394 struct smu_table_context *table_context = &smu->smu_table; 395 PPTable_t *pptable = table_context->driver_pptable; 396 uint64_t features = *(uint64_t *) pptable->FeaturesToRun; 397 398 /* Fan control is not possible if PPTable has it disabled */ 399 smu->adev->pm.no_fan = 400 !(features & (1ULL << FEATURE_FAN_CONTROL_BIT)); 401 if (smu->adev->pm.no_fan) 402 dev_info_once(smu->adev->dev, 403 "PMFW based fan control disabled"); 404 } 405 406 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu) 407 { 408 struct smu_table_context *table_context = &smu->smu_table; 409 struct smu_11_0_7_powerplay_table *powerplay_table = 410 table_context->power_play_table; 411 412 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC) 413 smu->dc_controlled_by_gpio = true; 414 415 sienna_cichlid_check_bxco_support(smu); 416 sienna_cichlid_check_fan_support(smu); 417 418 table_context->thermal_controller_type = 419 powerplay_table->thermal_controller_type; 420 421 /* 422 * Instead of having its own buffer space and get overdrive_table copied, 423 * smu->od_settings just points to the actual overdrive_table 424 */ 425 smu->od_settings = &powerplay_table->overdrive_table; 426 427 return 0; 428 } 429 430 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu) 431 { 432 struct atom_smc_dpm_info_v4_9 *smc_dpm_table; 433 int index, ret; 434 I2cControllerConfig_t *table_member; 435 436 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 437 smc_dpm_info); 438 439 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 440 (uint8_t **)&smc_dpm_table); 441 if (ret) 442 return ret; 443 GET_PPTABLE_MEMBER(I2cControllers, &table_member); 444 memcpy(table_member, smc_dpm_table->I2cControllers, 445 sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header)); 446 447 return 0; 448 } 449 450 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu) 451 { 452 struct smu_table_context *table_context = &smu->smu_table; 453 struct smu_11_0_7_powerplay_table *powerplay_table = 454 table_context->power_play_table; 455 int table_size; 456 457 table_size = get_table_size(smu); 458 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 459 table_size); 460 461 return 0; 462 } 463 464 static int sienna_cichlid_patch_pptable_quirk(struct smu_context *smu) 465 { 466 struct amdgpu_device *adev = smu->adev; 467 uint32_t *board_reserved; 468 uint16_t *freq_table_gfx; 469 uint32_t i; 470 471 /* Fix some OEM SKU specific stability issues */ 472 GET_PPTABLE_MEMBER(BoardReserved, &board_reserved); 473 if ((adev->pdev->device == 0x73DF) && 474 (adev->pdev->revision == 0XC3) && 475 (adev->pdev->subsystem_device == 0x16C2) && 476 (adev->pdev->subsystem_vendor == 0x1043)) 477 board_reserved[0] = 1387; 478 479 GET_PPTABLE_MEMBER(FreqTableGfx, &freq_table_gfx); 480 if ((adev->pdev->device == 0x73DF) && 481 (adev->pdev->revision == 0XC3) && 482 ((adev->pdev->subsystem_device == 0x16C2) || 483 (adev->pdev->subsystem_device == 0x133C)) && 484 (adev->pdev->subsystem_vendor == 0x1043)) { 485 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) { 486 if (freq_table_gfx[i] > 2500) 487 freq_table_gfx[i] = 2500; 488 } 489 } 490 491 return 0; 492 } 493 494 static int sienna_cichlid_setup_pptable(struct smu_context *smu) 495 { 496 int ret = 0; 497 498 ret = smu_v11_0_setup_pptable(smu); 499 if (ret) 500 return ret; 501 502 ret = sienna_cichlid_store_powerplay_table(smu); 503 if (ret) 504 return ret; 505 506 ret = sienna_cichlid_append_powerplay_table(smu); 507 if (ret) 508 return ret; 509 510 ret = sienna_cichlid_check_powerplay_table(smu); 511 if (ret) 512 return ret; 513 514 return sienna_cichlid_patch_pptable_quirk(smu); 515 } 516 517 static int sienna_cichlid_tables_init(struct smu_context *smu) 518 { 519 struct smu_table_context *smu_table = &smu->smu_table; 520 struct smu_table *tables = smu_table->tables; 521 int table_size; 522 523 table_size = get_table_size(smu); 524 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size, 525 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 526 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 527 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 528 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t), 529 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 530 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 531 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 532 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t), 533 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 534 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 535 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 536 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, 537 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE, 538 AMDGPU_GEM_DOMAIN_VRAM); 539 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t), 540 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 541 SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfigExternal_t), 542 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 543 544 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL); 545 if (!smu_table->metrics_table) 546 goto err0_out; 547 smu_table->metrics_time = 0; 548 549 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 550 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 551 if (!smu_table->gpu_metrics_table) 552 goto err1_out; 553 554 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 555 if (!smu_table->watermarks_table) 556 goto err2_out; 557 558 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL); 559 if (!smu_table->ecc_table) 560 goto err3_out; 561 562 smu_table->driver_smu_config_table = 563 kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL); 564 if (!smu_table->driver_smu_config_table) 565 goto err4_out; 566 567 return 0; 568 569 err4_out: 570 kfree(smu_table->ecc_table); 571 err3_out: 572 kfree(smu_table->watermarks_table); 573 err2_out: 574 kfree(smu_table->gpu_metrics_table); 575 err1_out: 576 kfree(smu_table->metrics_table); 577 err0_out: 578 return -ENOMEM; 579 } 580 581 static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu) 582 { 583 struct smu_table_context *smu_table= &smu->smu_table; 584 SmuMetricsExternal_t *metrics_ext = 585 (SmuMetricsExternal_t *)(smu_table->metrics_table); 586 uint32_t throttler_status = 0; 587 int i; 588 589 if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 590 (smu->smc_fw_version >= 0x3A4900)) { 591 for (i = 0; i < THROTTLER_COUNT; i++) 592 throttler_status |= 593 (metrics_ext->SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0); 594 } else if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 595 (smu->smc_fw_version >= 0x3A4300)) { 596 for (i = 0; i < THROTTLER_COUNT; i++) 597 throttler_status |= 598 (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0); 599 } else { 600 throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus; 601 } 602 603 return throttler_status; 604 } 605 606 static int sienna_cichlid_get_power_limit(struct smu_context *smu, 607 uint32_t *current_power_limit, 608 uint32_t *default_power_limit, 609 uint32_t *max_power_limit) 610 { 611 struct smu_11_0_7_powerplay_table *powerplay_table = 612 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table; 613 uint32_t power_limit, od_percent; 614 uint16_t *table_member; 615 616 GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member); 617 618 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) { 619 power_limit = 620 table_member[PPT_THROTTLER_PPT0]; 621 } 622 623 if (current_power_limit) 624 *current_power_limit = power_limit; 625 if (default_power_limit) 626 *default_power_limit = power_limit; 627 628 if (max_power_limit) { 629 if (smu->od_enabled) { 630 od_percent = 631 le32_to_cpu(powerplay_table->overdrive_table.max[ 632 SMU_11_0_7_ODSETTING_POWERPERCENTAGE]); 633 634 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", 635 od_percent, power_limit); 636 637 power_limit *= (100 + od_percent); 638 power_limit /= 100; 639 } 640 *max_power_limit = power_limit; 641 } 642 643 return 0; 644 } 645 646 static void sienna_cichlid_get_smartshift_power_percentage(struct smu_context *smu, 647 uint32_t *apu_percent, 648 uint32_t *dgpu_percent) 649 { 650 struct smu_table_context *smu_table = &smu->smu_table; 651 SmuMetrics_V4_t *metrics_v4 = 652 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V4); 653 uint16_t powerRatio = 0; 654 uint16_t apu_power_limit = 0; 655 uint16_t dgpu_power_limit = 0; 656 uint32_t apu_boost = 0; 657 uint32_t dgpu_boost = 0; 658 uint32_t cur_power_limit; 659 660 if (metrics_v4->ApuSTAPMSmartShiftLimit != 0) { 661 sienna_cichlid_get_power_limit(smu, &cur_power_limit, NULL, NULL); 662 apu_power_limit = metrics_v4->ApuSTAPMLimit; 663 dgpu_power_limit = cur_power_limit; 664 powerRatio = (((apu_power_limit + 665 dgpu_power_limit) * 100) / 666 metrics_v4->ApuSTAPMSmartShiftLimit); 667 if (powerRatio > 100) { 668 apu_power_limit = (apu_power_limit * 100) / 669 powerRatio; 670 dgpu_power_limit = (dgpu_power_limit * 100) / 671 powerRatio; 672 } 673 if (metrics_v4->AverageApuSocketPower > apu_power_limit && 674 apu_power_limit != 0) { 675 apu_boost = ((metrics_v4->AverageApuSocketPower - 676 apu_power_limit) * 100) / 677 apu_power_limit; 678 if (apu_boost > 100) 679 apu_boost = 100; 680 } 681 682 if (metrics_v4->AverageSocketPower > dgpu_power_limit && 683 dgpu_power_limit != 0) { 684 dgpu_boost = ((metrics_v4->AverageSocketPower - 685 dgpu_power_limit) * 100) / 686 dgpu_power_limit; 687 if (dgpu_boost > 100) 688 dgpu_boost = 100; 689 } 690 691 if (dgpu_boost >= apu_boost) 692 apu_boost = 0; 693 else 694 dgpu_boost = 0; 695 } 696 *apu_percent = apu_boost; 697 *dgpu_percent = dgpu_boost; 698 } 699 700 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu, 701 MetricsMember_t member, 702 uint32_t *value) 703 { 704 struct smu_table_context *smu_table= &smu->smu_table; 705 SmuMetrics_t *metrics = 706 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics); 707 SmuMetrics_V2_t *metrics_v2 = 708 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2); 709 SmuMetrics_V3_t *metrics_v3 = 710 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V3); 711 bool use_metrics_v2 = false; 712 bool use_metrics_v3 = false; 713 uint16_t average_gfx_activity; 714 int ret = 0; 715 uint32_t apu_percent = 0; 716 uint32_t dgpu_percent = 0; 717 718 switch (smu->adev->ip_versions[MP1_HWIP][0]) { 719 case IP_VERSION(11, 0, 7): 720 if (smu->smc_fw_version >= 0x3A4900) 721 use_metrics_v3 = true; 722 else if (smu->smc_fw_version >= 0x3A4300) 723 use_metrics_v2 = true; 724 break; 725 case IP_VERSION(11, 0, 11): 726 if (smu->smc_fw_version >= 0x412D00) 727 use_metrics_v2 = true; 728 break; 729 case IP_VERSION(11, 0, 12): 730 if (smu->smc_fw_version >= 0x3B2300) 731 use_metrics_v2 = true; 732 break; 733 case IP_VERSION(11, 0, 13): 734 if (smu->smc_fw_version >= 0x491100) 735 use_metrics_v2 = true; 736 break; 737 default: 738 break; 739 } 740 741 ret = smu_cmn_get_metrics_table(smu, 742 NULL, 743 false); 744 if (ret) 745 return ret; 746 747 switch (member) { 748 case METRICS_CURR_GFXCLK: 749 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] : 750 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : 751 metrics->CurrClock[PPCLK_GFXCLK]; 752 break; 753 case METRICS_CURR_SOCCLK: 754 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] : 755 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : 756 metrics->CurrClock[PPCLK_SOCCLK]; 757 break; 758 case METRICS_CURR_UCLK: 759 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] : 760 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : 761 metrics->CurrClock[PPCLK_UCLK]; 762 break; 763 case METRICS_CURR_VCLK: 764 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] : 765 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : 766 metrics->CurrClock[PPCLK_VCLK_0]; 767 break; 768 case METRICS_CURR_VCLK1: 769 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] : 770 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : 771 metrics->CurrClock[PPCLK_VCLK_1]; 772 break; 773 case METRICS_CURR_DCLK: 774 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] : 775 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : 776 metrics->CurrClock[PPCLK_DCLK_0]; 777 break; 778 case METRICS_CURR_DCLK1: 779 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] : 780 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : 781 metrics->CurrClock[PPCLK_DCLK_1]; 782 break; 783 case METRICS_CURR_DCEFCLK: 784 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCEFCLK] : 785 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] : 786 metrics->CurrClock[PPCLK_DCEFCLK]; 787 break; 788 case METRICS_CURR_FCLK: 789 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_FCLK] : 790 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] : 791 metrics->CurrClock[PPCLK_FCLK]; 792 break; 793 case METRICS_AVERAGE_GFXCLK: 794 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity : 795 use_metrics_v2 ? metrics_v2->AverageGfxActivity : 796 metrics->AverageGfxActivity; 797 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD) 798 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs : 799 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs : 800 metrics->AverageGfxclkFrequencyPostDs; 801 else 802 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs : 803 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs : 804 metrics->AverageGfxclkFrequencyPreDs; 805 break; 806 case METRICS_AVERAGE_FCLK: 807 *value = use_metrics_v3 ? metrics_v3->AverageFclkFrequencyPostDs : 808 use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs : 809 metrics->AverageFclkFrequencyPostDs; 810 break; 811 case METRICS_AVERAGE_UCLK: 812 *value = use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs : 813 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs : 814 metrics->AverageUclkFrequencyPostDs; 815 break; 816 case METRICS_AVERAGE_GFXACTIVITY: 817 *value = use_metrics_v3 ? metrics_v3->AverageGfxActivity : 818 use_metrics_v2 ? metrics_v2->AverageGfxActivity : 819 metrics->AverageGfxActivity; 820 break; 821 case METRICS_AVERAGE_MEMACTIVITY: 822 *value = use_metrics_v3 ? metrics_v3->AverageUclkActivity : 823 use_metrics_v2 ? metrics_v2->AverageUclkActivity : 824 metrics->AverageUclkActivity; 825 break; 826 case METRICS_AVERAGE_SOCKETPOWER: 827 *value = use_metrics_v3 ? metrics_v3->AverageSocketPower << 8 : 828 use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 : 829 metrics->AverageSocketPower << 8; 830 break; 831 case METRICS_TEMPERATURE_EDGE: 832 *value = (use_metrics_v3 ? metrics_v3->TemperatureEdge : 833 use_metrics_v2 ? metrics_v2->TemperatureEdge : 834 metrics->TemperatureEdge) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 835 break; 836 case METRICS_TEMPERATURE_HOTSPOT: 837 *value = (use_metrics_v3 ? metrics_v3->TemperatureHotspot : 838 use_metrics_v2 ? metrics_v2->TemperatureHotspot : 839 metrics->TemperatureHotspot) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 840 break; 841 case METRICS_TEMPERATURE_MEM: 842 *value = (use_metrics_v3 ? metrics_v3->TemperatureMem : 843 use_metrics_v2 ? metrics_v2->TemperatureMem : 844 metrics->TemperatureMem) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 845 break; 846 case METRICS_TEMPERATURE_VRGFX: 847 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrGfx : 848 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : 849 metrics->TemperatureVrGfx) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 850 break; 851 case METRICS_TEMPERATURE_VRSOC: 852 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrSoc : 853 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : 854 metrics->TemperatureVrSoc) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 855 break; 856 case METRICS_THROTTLER_STATUS: 857 *value = sienna_cichlid_get_throttler_status_locked(smu); 858 break; 859 case METRICS_CURR_FANSPEED: 860 *value = use_metrics_v3 ? metrics_v3->CurrFanSpeed : 861 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed; 862 break; 863 case METRICS_UNIQUE_ID_UPPER32: 864 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */ 865 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumUpper32 : 0; 866 break; 867 case METRICS_UNIQUE_ID_LOWER32: 868 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */ 869 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumLower32 : 0; 870 break; 871 case METRICS_SS_APU_SHARE: 872 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent); 873 *value = apu_percent; 874 break; 875 case METRICS_SS_DGPU_SHARE: 876 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent); 877 *value = dgpu_percent; 878 break; 879 880 default: 881 *value = UINT_MAX; 882 break; 883 } 884 885 return ret; 886 887 } 888 889 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu) 890 { 891 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 892 893 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 894 GFP_KERNEL); 895 if (!smu_dpm->dpm_context) 896 return -ENOMEM; 897 898 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 899 900 return 0; 901 } 902 903 static void sienna_cichlid_stb_init(struct smu_context *smu); 904 905 static int sienna_cichlid_init_smc_tables(struct smu_context *smu) 906 { 907 struct amdgpu_device *adev = smu->adev; 908 int ret = 0; 909 910 ret = sienna_cichlid_tables_init(smu); 911 if (ret) 912 return ret; 913 914 ret = sienna_cichlid_allocate_dpm_context(smu); 915 if (ret) 916 return ret; 917 918 if (!amdgpu_sriov_vf(adev)) 919 sienna_cichlid_stb_init(smu); 920 921 return smu_v11_0_init_smc_tables(smu); 922 } 923 924 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) 925 { 926 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 927 struct smu_11_0_dpm_table *dpm_table; 928 struct amdgpu_device *adev = smu->adev; 929 int i, ret = 0; 930 DpmDescriptor_t *table_member; 931 932 /* socclk dpm table setup */ 933 dpm_table = &dpm_context->dpm_tables.soc_table; 934 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member); 935 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 936 ret = smu_v11_0_set_single_dpm_table(smu, 937 SMU_SOCCLK, 938 dpm_table); 939 if (ret) 940 return ret; 941 dpm_table->is_fine_grained = 942 !table_member[PPCLK_SOCCLK].SnapToDiscrete; 943 } else { 944 dpm_table->count = 1; 945 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 946 dpm_table->dpm_levels[0].enabled = true; 947 dpm_table->min = dpm_table->dpm_levels[0].value; 948 dpm_table->max = dpm_table->dpm_levels[0].value; 949 } 950 951 /* gfxclk dpm table setup */ 952 dpm_table = &dpm_context->dpm_tables.gfx_table; 953 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 954 ret = smu_v11_0_set_single_dpm_table(smu, 955 SMU_GFXCLK, 956 dpm_table); 957 if (ret) 958 return ret; 959 dpm_table->is_fine_grained = 960 !table_member[PPCLK_GFXCLK].SnapToDiscrete; 961 } else { 962 dpm_table->count = 1; 963 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 964 dpm_table->dpm_levels[0].enabled = true; 965 dpm_table->min = dpm_table->dpm_levels[0].value; 966 dpm_table->max = dpm_table->dpm_levels[0].value; 967 } 968 969 /* uclk dpm table setup */ 970 dpm_table = &dpm_context->dpm_tables.uclk_table; 971 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 972 ret = smu_v11_0_set_single_dpm_table(smu, 973 SMU_UCLK, 974 dpm_table); 975 if (ret) 976 return ret; 977 dpm_table->is_fine_grained = 978 !table_member[PPCLK_UCLK].SnapToDiscrete; 979 } else { 980 dpm_table->count = 1; 981 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 982 dpm_table->dpm_levels[0].enabled = true; 983 dpm_table->min = dpm_table->dpm_levels[0].value; 984 dpm_table->max = dpm_table->dpm_levels[0].value; 985 } 986 987 /* fclk dpm table setup */ 988 dpm_table = &dpm_context->dpm_tables.fclk_table; 989 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 990 ret = smu_v11_0_set_single_dpm_table(smu, 991 SMU_FCLK, 992 dpm_table); 993 if (ret) 994 return ret; 995 dpm_table->is_fine_grained = 996 !table_member[PPCLK_FCLK].SnapToDiscrete; 997 } else { 998 dpm_table->count = 1; 999 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 1000 dpm_table->dpm_levels[0].enabled = true; 1001 dpm_table->min = dpm_table->dpm_levels[0].value; 1002 dpm_table->max = dpm_table->dpm_levels[0].value; 1003 } 1004 1005 /* vclk0/1 dpm table setup */ 1006 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1007 if (adev->vcn.harvest_config & (1 << i)) 1008 continue; 1009 1010 dpm_table = &dpm_context->dpm_tables.vclk_table; 1011 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 1012 ret = smu_v11_0_set_single_dpm_table(smu, 1013 i ? SMU_VCLK1 : SMU_VCLK, 1014 dpm_table); 1015 if (ret) 1016 return ret; 1017 dpm_table->is_fine_grained = 1018 !table_member[i ? PPCLK_VCLK_1 : PPCLK_VCLK_0].SnapToDiscrete; 1019 } else { 1020 dpm_table->count = 1; 1021 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; 1022 dpm_table->dpm_levels[0].enabled = true; 1023 dpm_table->min = dpm_table->dpm_levels[0].value; 1024 dpm_table->max = dpm_table->dpm_levels[0].value; 1025 } 1026 } 1027 1028 /* dclk0/1 dpm table setup */ 1029 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1030 if (adev->vcn.harvest_config & (1 << i)) 1031 continue; 1032 dpm_table = &dpm_context->dpm_tables.dclk_table; 1033 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 1034 ret = smu_v11_0_set_single_dpm_table(smu, 1035 i ? SMU_DCLK1 : SMU_DCLK, 1036 dpm_table); 1037 if (ret) 1038 return ret; 1039 dpm_table->is_fine_grained = 1040 !table_member[i ? PPCLK_DCLK_1 : PPCLK_DCLK_0].SnapToDiscrete; 1041 } else { 1042 dpm_table->count = 1; 1043 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; 1044 dpm_table->dpm_levels[0].enabled = true; 1045 dpm_table->min = dpm_table->dpm_levels[0].value; 1046 dpm_table->max = dpm_table->dpm_levels[0].value; 1047 } 1048 } 1049 1050 /* dcefclk dpm table setup */ 1051 dpm_table = &dpm_context->dpm_tables.dcef_table; 1052 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1053 ret = smu_v11_0_set_single_dpm_table(smu, 1054 SMU_DCEFCLK, 1055 dpm_table); 1056 if (ret) 1057 return ret; 1058 dpm_table->is_fine_grained = 1059 !table_member[PPCLK_DCEFCLK].SnapToDiscrete; 1060 } else { 1061 dpm_table->count = 1; 1062 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1063 dpm_table->dpm_levels[0].enabled = true; 1064 dpm_table->min = dpm_table->dpm_levels[0].value; 1065 dpm_table->max = dpm_table->dpm_levels[0].value; 1066 } 1067 1068 /* pixelclk dpm table setup */ 1069 dpm_table = &dpm_context->dpm_tables.pixel_table; 1070 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1071 ret = smu_v11_0_set_single_dpm_table(smu, 1072 SMU_PIXCLK, 1073 dpm_table); 1074 if (ret) 1075 return ret; 1076 dpm_table->is_fine_grained = 1077 !table_member[PPCLK_PIXCLK].SnapToDiscrete; 1078 } else { 1079 dpm_table->count = 1; 1080 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1081 dpm_table->dpm_levels[0].enabled = true; 1082 dpm_table->min = dpm_table->dpm_levels[0].value; 1083 dpm_table->max = dpm_table->dpm_levels[0].value; 1084 } 1085 1086 /* displayclk dpm table setup */ 1087 dpm_table = &dpm_context->dpm_tables.display_table; 1088 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1089 ret = smu_v11_0_set_single_dpm_table(smu, 1090 SMU_DISPCLK, 1091 dpm_table); 1092 if (ret) 1093 return ret; 1094 dpm_table->is_fine_grained = 1095 !table_member[PPCLK_DISPCLK].SnapToDiscrete; 1096 } else { 1097 dpm_table->count = 1; 1098 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1099 dpm_table->dpm_levels[0].enabled = true; 1100 dpm_table->min = dpm_table->dpm_levels[0].value; 1101 dpm_table->max = dpm_table->dpm_levels[0].value; 1102 } 1103 1104 /* phyclk dpm table setup */ 1105 dpm_table = &dpm_context->dpm_tables.phy_table; 1106 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1107 ret = smu_v11_0_set_single_dpm_table(smu, 1108 SMU_PHYCLK, 1109 dpm_table); 1110 if (ret) 1111 return ret; 1112 dpm_table->is_fine_grained = 1113 !table_member[PPCLK_PHYCLK].SnapToDiscrete; 1114 } else { 1115 dpm_table->count = 1; 1116 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1117 dpm_table->dpm_levels[0].enabled = true; 1118 dpm_table->min = dpm_table->dpm_levels[0].value; 1119 dpm_table->max = dpm_table->dpm_levels[0].value; 1120 } 1121 1122 return 0; 1123 } 1124 1125 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 1126 { 1127 struct amdgpu_device *adev = smu->adev; 1128 int i, ret = 0; 1129 1130 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1131 if (adev->vcn.harvest_config & (1 << i)) 1132 continue; 1133 /* vcn dpm on is a prerequisite for vcn power gate messages */ 1134 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 1135 ret = smu_cmn_send_smc_msg_with_param(smu, enable ? 1136 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn, 1137 0x10000 * i, NULL); 1138 if (ret) 1139 return ret; 1140 } 1141 } 1142 1143 return ret; 1144 } 1145 1146 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 1147 { 1148 int ret = 0; 1149 1150 if (enable) { 1151 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 1152 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); 1153 if (ret) 1154 return ret; 1155 } 1156 } else { 1157 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 1158 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); 1159 if (ret) 1160 return ret; 1161 } 1162 } 1163 1164 return ret; 1165 } 1166 1167 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu, 1168 enum smu_clk_type clk_type, 1169 uint32_t *value) 1170 { 1171 MetricsMember_t member_type; 1172 int clk_id = 0; 1173 1174 clk_id = smu_cmn_to_asic_specific_index(smu, 1175 CMN2ASIC_MAPPING_CLK, 1176 clk_type); 1177 if (clk_id < 0) 1178 return clk_id; 1179 1180 switch (clk_id) { 1181 case PPCLK_GFXCLK: 1182 member_type = METRICS_CURR_GFXCLK; 1183 break; 1184 case PPCLK_UCLK: 1185 member_type = METRICS_CURR_UCLK; 1186 break; 1187 case PPCLK_SOCCLK: 1188 member_type = METRICS_CURR_SOCCLK; 1189 break; 1190 case PPCLK_FCLK: 1191 member_type = METRICS_CURR_FCLK; 1192 break; 1193 case PPCLK_VCLK_0: 1194 member_type = METRICS_CURR_VCLK; 1195 break; 1196 case PPCLK_VCLK_1: 1197 member_type = METRICS_CURR_VCLK1; 1198 break; 1199 case PPCLK_DCLK_0: 1200 member_type = METRICS_CURR_DCLK; 1201 break; 1202 case PPCLK_DCLK_1: 1203 member_type = METRICS_CURR_DCLK1; 1204 break; 1205 case PPCLK_DCEFCLK: 1206 member_type = METRICS_CURR_DCEFCLK; 1207 break; 1208 default: 1209 return -EINVAL; 1210 } 1211 1212 return sienna_cichlid_get_smu_metrics_data(smu, 1213 member_type, 1214 value); 1215 1216 } 1217 1218 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) 1219 { 1220 DpmDescriptor_t *dpm_desc = NULL; 1221 DpmDescriptor_t *table_member; 1222 uint32_t clk_index = 0; 1223 1224 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member); 1225 clk_index = smu_cmn_to_asic_specific_index(smu, 1226 CMN2ASIC_MAPPING_CLK, 1227 clk_type); 1228 dpm_desc = &table_member[clk_index]; 1229 1230 /* 0 - Fine grained DPM, 1 - Discrete DPM */ 1231 return dpm_desc->SnapToDiscrete == 0; 1232 } 1233 1234 static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table, 1235 enum SMU_11_0_7_ODFEATURE_CAP cap) 1236 { 1237 return od_table->cap[cap]; 1238 } 1239 1240 static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table, 1241 enum SMU_11_0_7_ODSETTING_ID setting, 1242 uint32_t *min, uint32_t *max) 1243 { 1244 if (min) 1245 *min = od_table->min[setting]; 1246 if (max) 1247 *max = od_table->max[setting]; 1248 } 1249 1250 static int sienna_cichlid_print_clk_levels(struct smu_context *smu, 1251 enum smu_clk_type clk_type, char *buf) 1252 { 1253 struct amdgpu_device *adev = smu->adev; 1254 struct smu_table_context *table_context = &smu->smu_table; 1255 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1256 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1257 uint16_t *table_member; 1258 1259 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings; 1260 OverDriveTable_t *od_table = 1261 (OverDriveTable_t *)table_context->overdrive_table; 1262 int i, size = 0, ret = 0; 1263 uint32_t cur_value = 0, value = 0, count = 0; 1264 uint32_t freq_values[3] = {0}; 1265 uint32_t mark_index = 0; 1266 uint32_t gen_speed, lane_width; 1267 uint32_t min_value, max_value; 1268 uint32_t smu_version; 1269 1270 smu_cmn_get_sysfs_buf(&buf, &size); 1271 1272 switch (clk_type) { 1273 case SMU_GFXCLK: 1274 case SMU_SCLK: 1275 case SMU_SOCCLK: 1276 case SMU_MCLK: 1277 case SMU_UCLK: 1278 case SMU_FCLK: 1279 case SMU_VCLK: 1280 case SMU_VCLK1: 1281 case SMU_DCLK: 1282 case SMU_DCLK1: 1283 case SMU_DCEFCLK: 1284 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value); 1285 if (ret) 1286 goto print_clk_out; 1287 1288 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); 1289 if (ret) 1290 goto print_clk_out; 1291 1292 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) { 1293 for (i = 0; i < count; i++) { 1294 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); 1295 if (ret) 1296 goto print_clk_out; 1297 1298 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 1299 cur_value == value ? "*" : ""); 1300 } 1301 } else { 1302 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]); 1303 if (ret) 1304 goto print_clk_out; 1305 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]); 1306 if (ret) 1307 goto print_clk_out; 1308 1309 freq_values[1] = cur_value; 1310 mark_index = cur_value == freq_values[0] ? 0 : 1311 cur_value == freq_values[2] ? 2 : 1; 1312 1313 count = 3; 1314 if (mark_index != 1) { 1315 count = 2; 1316 freq_values[1] = freq_values[2]; 1317 } 1318 1319 for (i = 0; i < count; i++) { 1320 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i], 1321 cur_value == freq_values[i] ? "*" : ""); 1322 } 1323 1324 } 1325 break; 1326 case SMU_PCIE: 1327 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); 1328 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); 1329 GET_PPTABLE_MEMBER(LclkFreq, &table_member); 1330 for (i = 0; i < NUM_LINK_LEVELS; i++) 1331 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i, 1332 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," : 1333 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," : 1334 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," : 1335 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "", 1336 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" : 1337 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" : 1338 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" : 1339 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" : 1340 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" : 1341 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "", 1342 table_member[i], 1343 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && 1344 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? 1345 "*" : ""); 1346 break; 1347 case SMU_OD_SCLK: 1348 if (!smu->od_enabled || !od_table || !od_settings) 1349 break; 1350 1351 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) 1352 break; 1353 1354 size += sysfs_emit_at(buf, size, "OD_SCLK:\n"); 1355 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax); 1356 break; 1357 1358 case SMU_OD_MCLK: 1359 if (!smu->od_enabled || !od_table || !od_settings) 1360 break; 1361 1362 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) 1363 break; 1364 1365 size += sysfs_emit_at(buf, size, "OD_MCLK:\n"); 1366 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax); 1367 break; 1368 1369 case SMU_OD_VDDGFX_OFFSET: 1370 if (!smu->od_enabled || !od_table || !od_settings) 1371 break; 1372 1373 /* 1374 * OD GFX Voltage Offset functionality is supported only by 58.41.0 1375 * and onwards SMU firmwares. 1376 */ 1377 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1378 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 1379 (smu_version < 0x003a2900)) 1380 break; 1381 1382 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n"); 1383 size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset); 1384 break; 1385 1386 case SMU_OD_RANGE: 1387 if (!smu->od_enabled || !od_table || !od_settings) 1388 break; 1389 1390 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 1391 1392 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) { 1393 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN, 1394 &min_value, NULL); 1395 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX, 1396 NULL, &max_value); 1397 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 1398 min_value, max_value); 1399 } 1400 1401 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) { 1402 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN, 1403 &min_value, NULL); 1404 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX, 1405 NULL, &max_value); 1406 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n", 1407 min_value, max_value); 1408 } 1409 break; 1410 1411 default: 1412 break; 1413 } 1414 1415 print_clk_out: 1416 return size; 1417 } 1418 1419 static int sienna_cichlid_force_clk_levels(struct smu_context *smu, 1420 enum smu_clk_type clk_type, uint32_t mask) 1421 { 1422 int ret = 0; 1423 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; 1424 1425 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1426 soft_max_level = mask ? (fls(mask) - 1) : 0; 1427 1428 switch (clk_type) { 1429 case SMU_GFXCLK: 1430 case SMU_SCLK: 1431 case SMU_SOCCLK: 1432 case SMU_MCLK: 1433 case SMU_UCLK: 1434 case SMU_FCLK: 1435 /* There is only 2 levels for fine grained DPM */ 1436 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) { 1437 soft_max_level = (soft_max_level >= 1 ? 1 : 0); 1438 soft_min_level = (soft_min_level >= 1 ? 1 : 0); 1439 } 1440 1441 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); 1442 if (ret) 1443 goto forec_level_out; 1444 1445 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq); 1446 if (ret) 1447 goto forec_level_out; 1448 1449 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 1450 if (ret) 1451 goto forec_level_out; 1452 break; 1453 case SMU_DCEFCLK: 1454 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n"); 1455 break; 1456 default: 1457 break; 1458 } 1459 1460 forec_level_out: 1461 return 0; 1462 } 1463 1464 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu) 1465 { 1466 struct smu_11_0_dpm_context *dpm_context = 1467 smu->smu_dpm.dpm_context; 1468 struct smu_11_0_dpm_table *gfx_table = 1469 &dpm_context->dpm_tables.gfx_table; 1470 struct smu_11_0_dpm_table *mem_table = 1471 &dpm_context->dpm_tables.uclk_table; 1472 struct smu_11_0_dpm_table *soc_table = 1473 &dpm_context->dpm_tables.soc_table; 1474 struct smu_umd_pstate_table *pstate_table = 1475 &smu->pstate_table; 1476 struct amdgpu_device *adev = smu->adev; 1477 1478 pstate_table->gfxclk_pstate.min = gfx_table->min; 1479 pstate_table->gfxclk_pstate.peak = gfx_table->max; 1480 1481 pstate_table->uclk_pstate.min = mem_table->min; 1482 pstate_table->uclk_pstate.peak = mem_table->max; 1483 1484 pstate_table->socclk_pstate.min = soc_table->min; 1485 pstate_table->socclk_pstate.peak = soc_table->max; 1486 1487 switch (adev->ip_versions[MP1_HWIP][0]) { 1488 case IP_VERSION(11, 0, 7): 1489 case IP_VERSION(11, 0, 11): 1490 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK; 1491 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK; 1492 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK; 1493 break; 1494 case IP_VERSION(11, 0, 12): 1495 pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK; 1496 pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK; 1497 pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK; 1498 break; 1499 case IP_VERSION(11, 0, 13): 1500 pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK; 1501 pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK; 1502 pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK; 1503 break; 1504 default: 1505 break; 1506 } 1507 1508 return 0; 1509 } 1510 1511 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu) 1512 { 1513 int ret = 0; 1514 uint32_t max_freq = 0; 1515 1516 /* Sienna_Cichlid do not support to change display num currently */ 1517 return 0; 1518 #if 0 1519 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL); 1520 if (ret) 1521 return ret; 1522 #endif 1523 1524 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1525 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq); 1526 if (ret) 1527 return ret; 1528 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq); 1529 if (ret) 1530 return ret; 1531 } 1532 1533 return ret; 1534 } 1535 1536 static int sienna_cichlid_display_config_changed(struct smu_context *smu) 1537 { 1538 int ret = 0; 1539 1540 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1541 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) && 1542 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 1543 #if 0 1544 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 1545 smu->display_config->num_display, 1546 NULL); 1547 #endif 1548 if (ret) 1549 return ret; 1550 } 1551 1552 return ret; 1553 } 1554 1555 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu) 1556 { 1557 int ret = 0; 1558 uint64_t feature_enabled; 1559 1560 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 1561 if (ret) 1562 return false; 1563 1564 return !!(feature_enabled & SMC_DPM_FEATURE); 1565 } 1566 1567 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu, 1568 uint32_t *speed) 1569 { 1570 if (!speed) 1571 return -EINVAL; 1572 1573 /* 1574 * For Sienna_Cichlid and later, the fan speed(rpm) reported 1575 * by pmfw is always trustable(even when the fan control feature 1576 * disabled or 0 RPM kicked in). 1577 */ 1578 return sienna_cichlid_get_smu_metrics_data(smu, 1579 METRICS_CURR_FANSPEED, 1580 speed); 1581 } 1582 1583 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu) 1584 { 1585 uint16_t *table_member; 1586 1587 GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member); 1588 smu->fan_max_rpm = *table_member; 1589 1590 return 0; 1591 } 1592 1593 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf) 1594 { 1595 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 1596 DpmActivityMonitorCoeffInt_t *activity_monitor = 1597 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 1598 uint32_t i, size = 0; 1599 int16_t workload_type = 0; 1600 static const char *title[] = { 1601 "PROFILE_INDEX(NAME)", 1602 "CLOCK_TYPE(NAME)", 1603 "FPS", 1604 "MinFreqType", 1605 "MinActiveFreqType", 1606 "MinActiveFreq", 1607 "BoosterFreqType", 1608 "BoosterFreq", 1609 "PD_Data_limit_c", 1610 "PD_Data_error_coeff", 1611 "PD_Data_error_rate_coeff"}; 1612 int result = 0; 1613 1614 if (!buf) 1615 return -EINVAL; 1616 1617 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n", 1618 title[0], title[1], title[2], title[3], title[4], title[5], 1619 title[6], title[7], title[8], title[9], title[10]); 1620 1621 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1622 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1623 workload_type = smu_cmn_to_asic_specific_index(smu, 1624 CMN2ASIC_MAPPING_WORKLOAD, 1625 i); 1626 if (workload_type < 0) 1627 return -EINVAL; 1628 1629 result = smu_cmn_update_table(smu, 1630 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type, 1631 (void *)(&activity_monitor_external), false); 1632 if (result) { 1633 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1634 return result; 1635 } 1636 1637 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n", 1638 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1639 1640 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1641 " ", 1642 0, 1643 "GFXCLK", 1644 activity_monitor->Gfx_FPS, 1645 activity_monitor->Gfx_MinFreqStep, 1646 activity_monitor->Gfx_MinActiveFreqType, 1647 activity_monitor->Gfx_MinActiveFreq, 1648 activity_monitor->Gfx_BoosterFreqType, 1649 activity_monitor->Gfx_BoosterFreq, 1650 activity_monitor->Gfx_PD_Data_limit_c, 1651 activity_monitor->Gfx_PD_Data_error_coeff, 1652 activity_monitor->Gfx_PD_Data_error_rate_coeff); 1653 1654 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1655 " ", 1656 1, 1657 "SOCCLK", 1658 activity_monitor->Fclk_FPS, 1659 activity_monitor->Fclk_MinFreqStep, 1660 activity_monitor->Fclk_MinActiveFreqType, 1661 activity_monitor->Fclk_MinActiveFreq, 1662 activity_monitor->Fclk_BoosterFreqType, 1663 activity_monitor->Fclk_BoosterFreq, 1664 activity_monitor->Fclk_PD_Data_limit_c, 1665 activity_monitor->Fclk_PD_Data_error_coeff, 1666 activity_monitor->Fclk_PD_Data_error_rate_coeff); 1667 1668 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1669 " ", 1670 2, 1671 "MEMLK", 1672 activity_monitor->Mem_FPS, 1673 activity_monitor->Mem_MinFreqStep, 1674 activity_monitor->Mem_MinActiveFreqType, 1675 activity_monitor->Mem_MinActiveFreq, 1676 activity_monitor->Mem_BoosterFreqType, 1677 activity_monitor->Mem_BoosterFreq, 1678 activity_monitor->Mem_PD_Data_limit_c, 1679 activity_monitor->Mem_PD_Data_error_coeff, 1680 activity_monitor->Mem_PD_Data_error_rate_coeff); 1681 } 1682 1683 return size; 1684 } 1685 1686 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 1687 { 1688 1689 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 1690 DpmActivityMonitorCoeffInt_t *activity_monitor = 1691 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 1692 int workload_type, ret = 0; 1693 1694 smu->power_profile_mode = input[size]; 1695 1696 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 1697 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode); 1698 return -EINVAL; 1699 } 1700 1701 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 1702 1703 ret = smu_cmn_update_table(smu, 1704 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1705 (void *)(&activity_monitor_external), false); 1706 if (ret) { 1707 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1708 return ret; 1709 } 1710 1711 switch (input[0]) { 1712 case 0: /* Gfxclk */ 1713 activity_monitor->Gfx_FPS = input[1]; 1714 activity_monitor->Gfx_MinFreqStep = input[2]; 1715 activity_monitor->Gfx_MinActiveFreqType = input[3]; 1716 activity_monitor->Gfx_MinActiveFreq = input[4]; 1717 activity_monitor->Gfx_BoosterFreqType = input[5]; 1718 activity_monitor->Gfx_BoosterFreq = input[6]; 1719 activity_monitor->Gfx_PD_Data_limit_c = input[7]; 1720 activity_monitor->Gfx_PD_Data_error_coeff = input[8]; 1721 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9]; 1722 break; 1723 case 1: /* Socclk */ 1724 activity_monitor->Fclk_FPS = input[1]; 1725 activity_monitor->Fclk_MinFreqStep = input[2]; 1726 activity_monitor->Fclk_MinActiveFreqType = input[3]; 1727 activity_monitor->Fclk_MinActiveFreq = input[4]; 1728 activity_monitor->Fclk_BoosterFreqType = input[5]; 1729 activity_monitor->Fclk_BoosterFreq = input[6]; 1730 activity_monitor->Fclk_PD_Data_limit_c = input[7]; 1731 activity_monitor->Fclk_PD_Data_error_coeff = input[8]; 1732 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9]; 1733 break; 1734 case 2: /* Memlk */ 1735 activity_monitor->Mem_FPS = input[1]; 1736 activity_monitor->Mem_MinFreqStep = input[2]; 1737 activity_monitor->Mem_MinActiveFreqType = input[3]; 1738 activity_monitor->Mem_MinActiveFreq = input[4]; 1739 activity_monitor->Mem_BoosterFreqType = input[5]; 1740 activity_monitor->Mem_BoosterFreq = input[6]; 1741 activity_monitor->Mem_PD_Data_limit_c = input[7]; 1742 activity_monitor->Mem_PD_Data_error_coeff = input[8]; 1743 activity_monitor->Mem_PD_Data_error_rate_coeff = input[9]; 1744 break; 1745 } 1746 1747 ret = smu_cmn_update_table(smu, 1748 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1749 (void *)(&activity_monitor_external), true); 1750 if (ret) { 1751 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 1752 return ret; 1753 } 1754 } 1755 1756 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1757 workload_type = smu_cmn_to_asic_specific_index(smu, 1758 CMN2ASIC_MAPPING_WORKLOAD, 1759 smu->power_profile_mode); 1760 if (workload_type < 0) 1761 return -EINVAL; 1762 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 1763 1 << workload_type, NULL); 1764 1765 return ret; 1766 } 1767 1768 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu) 1769 { 1770 struct smu_clocks min_clocks = {0}; 1771 struct pp_display_clock_request clock_req; 1772 int ret = 0; 1773 1774 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; 1775 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; 1776 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; 1777 1778 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1779 clock_req.clock_type = amd_pp_dcef_clock; 1780 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; 1781 1782 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req); 1783 if (!ret) { 1784 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) { 1785 ret = smu_cmn_send_smc_msg_with_param(smu, 1786 SMU_MSG_SetMinDeepSleepDcefclk, 1787 min_clocks.dcef_clock_in_sr/100, 1788 NULL); 1789 if (ret) { 1790 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!"); 1791 return ret; 1792 } 1793 } 1794 } else { 1795 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!"); 1796 } 1797 } 1798 1799 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1800 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); 1801 if (ret) { 1802 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__); 1803 return ret; 1804 } 1805 } 1806 1807 return 0; 1808 } 1809 1810 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu, 1811 struct pp_smu_wm_range_sets *clock_ranges) 1812 { 1813 Watermarks_t *table = smu->smu_table.watermarks_table; 1814 int ret = 0; 1815 int i; 1816 1817 if (clock_ranges) { 1818 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 1819 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1820 return -EINVAL; 1821 1822 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1823 table->WatermarkRow[WM_DCEFCLK][i].MinClock = 1824 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1825 table->WatermarkRow[WM_DCEFCLK][i].MaxClock = 1826 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1827 table->WatermarkRow[WM_DCEFCLK][i].MinUclk = 1828 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1829 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk = 1830 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1831 1832 table->WatermarkRow[WM_DCEFCLK][i].WmSetting = 1833 clock_ranges->reader_wm_sets[i].wm_inst; 1834 } 1835 1836 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1837 table->WatermarkRow[WM_SOCCLK][i].MinClock = 1838 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1839 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1840 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1841 table->WatermarkRow[WM_SOCCLK][i].MinUclk = 1842 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1843 table->WatermarkRow[WM_SOCCLK][i].MaxUclk = 1844 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1845 1846 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1847 clock_ranges->writer_wm_sets[i].wm_inst; 1848 } 1849 1850 smu->watermarks_bitmap |= WATERMARKS_EXIST; 1851 } 1852 1853 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1854 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1855 ret = smu_cmn_write_watermarks_table(smu); 1856 if (ret) { 1857 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1858 return ret; 1859 } 1860 smu->watermarks_bitmap |= WATERMARKS_LOADED; 1861 } 1862 1863 return 0; 1864 } 1865 1866 static int sienna_cichlid_read_sensor(struct smu_context *smu, 1867 enum amd_pp_sensors sensor, 1868 void *data, uint32_t *size) 1869 { 1870 int ret = 0; 1871 uint16_t *temp; 1872 struct amdgpu_device *adev = smu->adev; 1873 1874 if(!data || !size) 1875 return -EINVAL; 1876 1877 switch (sensor) { 1878 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 1879 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp); 1880 *(uint16_t *)data = *temp; 1881 *size = 4; 1882 break; 1883 case AMDGPU_PP_SENSOR_MEM_LOAD: 1884 ret = sienna_cichlid_get_smu_metrics_data(smu, 1885 METRICS_AVERAGE_MEMACTIVITY, 1886 (uint32_t *)data); 1887 *size = 4; 1888 break; 1889 case AMDGPU_PP_SENSOR_GPU_LOAD: 1890 ret = sienna_cichlid_get_smu_metrics_data(smu, 1891 METRICS_AVERAGE_GFXACTIVITY, 1892 (uint32_t *)data); 1893 *size = 4; 1894 break; 1895 case AMDGPU_PP_SENSOR_GPU_POWER: 1896 ret = sienna_cichlid_get_smu_metrics_data(smu, 1897 METRICS_AVERAGE_SOCKETPOWER, 1898 (uint32_t *)data); 1899 *size = 4; 1900 break; 1901 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1902 ret = sienna_cichlid_get_smu_metrics_data(smu, 1903 METRICS_TEMPERATURE_HOTSPOT, 1904 (uint32_t *)data); 1905 *size = 4; 1906 break; 1907 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1908 ret = sienna_cichlid_get_smu_metrics_data(smu, 1909 METRICS_TEMPERATURE_EDGE, 1910 (uint32_t *)data); 1911 *size = 4; 1912 break; 1913 case AMDGPU_PP_SENSOR_MEM_TEMP: 1914 ret = sienna_cichlid_get_smu_metrics_data(smu, 1915 METRICS_TEMPERATURE_MEM, 1916 (uint32_t *)data); 1917 *size = 4; 1918 break; 1919 case AMDGPU_PP_SENSOR_GFX_MCLK: 1920 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 1921 *(uint32_t *)data *= 100; 1922 *size = 4; 1923 break; 1924 case AMDGPU_PP_SENSOR_GFX_SCLK: 1925 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); 1926 *(uint32_t *)data *= 100; 1927 *size = 4; 1928 break; 1929 case AMDGPU_PP_SENSOR_VDDGFX: 1930 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data); 1931 *size = 4; 1932 break; 1933 case AMDGPU_PP_SENSOR_SS_APU_SHARE: 1934 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) { 1935 ret = sienna_cichlid_get_smu_metrics_data(smu, 1936 METRICS_SS_APU_SHARE, (uint32_t *)data); 1937 *size = 4; 1938 } else { 1939 ret = -EOPNOTSUPP; 1940 } 1941 break; 1942 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE: 1943 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) { 1944 ret = sienna_cichlid_get_smu_metrics_data(smu, 1945 METRICS_SS_DGPU_SHARE, (uint32_t *)data); 1946 *size = 4; 1947 } else { 1948 ret = -EOPNOTSUPP; 1949 } 1950 break; 1951 default: 1952 ret = -EOPNOTSUPP; 1953 break; 1954 } 1955 1956 return ret; 1957 } 1958 1959 static void sienna_cichlid_get_unique_id(struct smu_context *smu) 1960 { 1961 struct amdgpu_device *adev = smu->adev; 1962 uint32_t upper32 = 0, lower32 = 0; 1963 1964 /* Only supported as of version 0.58.83.0 and only on Sienna Cichlid */ 1965 if (smu->smc_fw_version < 0x3A5300 || 1966 smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) 1967 return; 1968 1969 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32)) 1970 goto out; 1971 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32)) 1972 goto out; 1973 1974 out: 1975 1976 adev->unique_id = ((uint64_t)upper32 << 32) | lower32; 1977 if (adev->serial[0] == '\0') 1978 sprintf(adev->serial, "%016llx", adev->unique_id); 1979 } 1980 1981 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states) 1982 { 1983 uint32_t num_discrete_levels = 0; 1984 uint16_t *dpm_levels = NULL; 1985 uint16_t i = 0; 1986 struct smu_table_context *table_context = &smu->smu_table; 1987 DpmDescriptor_t *table_member1; 1988 uint16_t *table_member2; 1989 1990 if (!clocks_in_khz || !num_states || !table_context->driver_pptable) 1991 return -EINVAL; 1992 1993 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1); 1994 num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels; 1995 GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2); 1996 dpm_levels = table_member2; 1997 1998 if (num_discrete_levels == 0 || dpm_levels == NULL) 1999 return -EINVAL; 2000 2001 *num_states = num_discrete_levels; 2002 for (i = 0; i < num_discrete_levels; i++) { 2003 /* convert to khz */ 2004 *clocks_in_khz = (*dpm_levels) * 1000; 2005 clocks_in_khz++; 2006 dpm_levels++; 2007 } 2008 2009 return 0; 2010 } 2011 2012 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu, 2013 struct smu_temperature_range *range) 2014 { 2015 struct smu_table_context *table_context = &smu->smu_table; 2016 struct smu_11_0_7_powerplay_table *powerplay_table = 2017 table_context->power_play_table; 2018 uint16_t *table_member; 2019 uint16_t temp_edge, temp_hotspot, temp_mem; 2020 2021 if (!range) 2022 return -EINVAL; 2023 2024 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range)); 2025 2026 GET_PPTABLE_MEMBER(TemperatureLimit, &table_member); 2027 temp_edge = table_member[TEMP_EDGE]; 2028 temp_hotspot = table_member[TEMP_HOTSPOT]; 2029 temp_mem = table_member[TEMP_MEM]; 2030 2031 range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2032 range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) * 2033 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2034 range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2035 range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) * 2036 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2037 range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2038 range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)* 2039 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2040 2041 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 2042 2043 return 0; 2044 } 2045 2046 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu, 2047 bool disable_memory_clock_switch) 2048 { 2049 int ret = 0; 2050 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks = 2051 (struct smu_11_0_max_sustainable_clocks *) 2052 smu->smu_table.max_sustainable_clocks; 2053 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal; 2054 uint32_t max_memory_clock = max_sustainable_clocks->uclock; 2055 2056 if(smu->disable_uclk_switch == disable_memory_clock_switch) 2057 return 0; 2058 2059 if(disable_memory_clock_switch) 2060 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0); 2061 else 2062 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0); 2063 2064 if(!ret) 2065 smu->disable_uclk_switch = disable_memory_clock_switch; 2066 2067 return ret; 2068 } 2069 2070 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu, 2071 uint32_t pcie_gen_cap, 2072 uint32_t pcie_width_cap) 2073 { 2074 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 2075 2076 uint32_t smu_pcie_arg; 2077 uint8_t *table_member1, *table_member2; 2078 int ret, i; 2079 2080 GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1); 2081 GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2); 2082 2083 /* lclk dpm table setup */ 2084 for (i = 0; i < MAX_PCIE_CONF; i++) { 2085 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = table_member1[i]; 2086 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = table_member2[i]; 2087 } 2088 2089 for (i = 0; i < NUM_LINK_LEVELS; i++) { 2090 smu_pcie_arg = (i << 16) | 2091 ((table_member1[i] <= pcie_gen_cap) ? 2092 (table_member1[i] << 8) : 2093 (pcie_gen_cap << 8)) | 2094 ((table_member2[i] <= pcie_width_cap) ? 2095 table_member2[i] : 2096 pcie_width_cap); 2097 2098 ret = smu_cmn_send_smc_msg_with_param(smu, 2099 SMU_MSG_OverridePcieParameters, 2100 smu_pcie_arg, 2101 NULL); 2102 if (ret) 2103 return ret; 2104 2105 if (table_member1[i] > pcie_gen_cap) 2106 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap; 2107 if (table_member2[i] > pcie_width_cap) 2108 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap; 2109 } 2110 2111 return 0; 2112 } 2113 2114 static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu, 2115 enum smu_clk_type clk_type, 2116 uint32_t *min, uint32_t *max) 2117 { 2118 return smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max); 2119 } 2120 2121 static void sienna_cichlid_dump_od_table(struct smu_context *smu, 2122 OverDriveTable_t *od_table) 2123 { 2124 struct amdgpu_device *adev = smu->adev; 2125 uint32_t smu_version; 2126 2127 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, 2128 od_table->GfxclkFmax); 2129 dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin, 2130 od_table->UclkFmax); 2131 2132 smu_cmn_get_smc_version(smu, NULL, &smu_version); 2133 if (!((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 2134 (smu_version < 0x003a2900))) 2135 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset); 2136 } 2137 2138 static int sienna_cichlid_set_default_od_settings(struct smu_context *smu) 2139 { 2140 OverDriveTable_t *od_table = 2141 (OverDriveTable_t *)smu->smu_table.overdrive_table; 2142 OverDriveTable_t *boot_od_table = 2143 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table; 2144 OverDriveTable_t *user_od_table = 2145 (OverDriveTable_t *)smu->smu_table.user_overdrive_table; 2146 int ret = 0; 2147 2148 /* 2149 * For S3/S4/Runpm resume, no need to setup those overdrive tables again as 2150 * - either they already have the default OD settings got during cold bootup 2151 * - or they have some user customized OD settings which cannot be overwritten 2152 */ 2153 if (smu->adev->in_suspend) 2154 return 0; 2155 2156 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 2157 0, (void *)boot_od_table, false); 2158 if (ret) { 2159 dev_err(smu->adev->dev, "Failed to get overdrive table!\n"); 2160 return ret; 2161 } 2162 2163 sienna_cichlid_dump_od_table(smu, boot_od_table); 2164 2165 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t)); 2166 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t)); 2167 2168 return 0; 2169 } 2170 2171 static int sienna_cichlid_od_setting_check_range(struct smu_context *smu, 2172 struct smu_11_0_7_overdrive_table *od_table, 2173 enum SMU_11_0_7_ODSETTING_ID setting, 2174 uint32_t value) 2175 { 2176 if (value < od_table->min[setting]) { 2177 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", 2178 setting, value, od_table->min[setting]); 2179 return -EINVAL; 2180 } 2181 if (value > od_table->max[setting]) { 2182 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", 2183 setting, value, od_table->max[setting]); 2184 return -EINVAL; 2185 } 2186 2187 return 0; 2188 } 2189 2190 static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu, 2191 enum PP_OD_DPM_TABLE_COMMAND type, 2192 long input[], uint32_t size) 2193 { 2194 struct smu_table_context *table_context = &smu->smu_table; 2195 OverDriveTable_t *od_table = 2196 (OverDriveTable_t *)table_context->overdrive_table; 2197 struct smu_11_0_7_overdrive_table *od_settings = 2198 (struct smu_11_0_7_overdrive_table *)smu->od_settings; 2199 struct amdgpu_device *adev = smu->adev; 2200 enum SMU_11_0_7_ODSETTING_ID freq_setting; 2201 uint16_t *freq_ptr; 2202 int i, ret = 0; 2203 uint32_t smu_version; 2204 2205 if (!smu->od_enabled) { 2206 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n"); 2207 return -EINVAL; 2208 } 2209 2210 if (!smu->od_settings) { 2211 dev_err(smu->adev->dev, "OD board limits are not set!\n"); 2212 return -ENOENT; 2213 } 2214 2215 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) { 2216 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n"); 2217 return -EINVAL; 2218 } 2219 2220 switch (type) { 2221 case PP_OD_EDIT_SCLK_VDDC_TABLE: 2222 if (!sienna_cichlid_is_od_feature_supported(od_settings, 2223 SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) { 2224 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n"); 2225 return -ENOTSUPP; 2226 } 2227 2228 for (i = 0; i < size; i += 2) { 2229 if (i + 2 > size) { 2230 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size); 2231 return -EINVAL; 2232 } 2233 2234 switch (input[i]) { 2235 case 0: 2236 if (input[i + 1] > od_table->GfxclkFmax) { 2237 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n", 2238 input[i + 1], od_table->GfxclkFmax); 2239 return -EINVAL; 2240 } 2241 2242 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN; 2243 freq_ptr = &od_table->GfxclkFmin; 2244 break; 2245 2246 case 1: 2247 if (input[i + 1] < od_table->GfxclkFmin) { 2248 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n", 2249 input[i + 1], od_table->GfxclkFmin); 2250 return -EINVAL; 2251 } 2252 2253 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX; 2254 freq_ptr = &od_table->GfxclkFmax; 2255 break; 2256 2257 default: 2258 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]); 2259 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n"); 2260 return -EINVAL; 2261 } 2262 2263 ret = sienna_cichlid_od_setting_check_range(smu, od_settings, 2264 freq_setting, input[i + 1]); 2265 if (ret) 2266 return ret; 2267 2268 *freq_ptr = (uint16_t)input[i + 1]; 2269 } 2270 break; 2271 2272 case PP_OD_EDIT_MCLK_VDDC_TABLE: 2273 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) { 2274 dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n"); 2275 return -ENOTSUPP; 2276 } 2277 2278 for (i = 0; i < size; i += 2) { 2279 if (i + 2 > size) { 2280 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size); 2281 return -EINVAL; 2282 } 2283 2284 switch (input[i]) { 2285 case 0: 2286 if (input[i + 1] > od_table->UclkFmax) { 2287 dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n", 2288 input[i + 1], od_table->UclkFmax); 2289 return -EINVAL; 2290 } 2291 2292 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN; 2293 freq_ptr = &od_table->UclkFmin; 2294 break; 2295 2296 case 1: 2297 if (input[i + 1] < od_table->UclkFmin) { 2298 dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n", 2299 input[i + 1], od_table->UclkFmin); 2300 return -EINVAL; 2301 } 2302 2303 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX; 2304 freq_ptr = &od_table->UclkFmax; 2305 break; 2306 2307 default: 2308 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]); 2309 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n"); 2310 return -EINVAL; 2311 } 2312 2313 ret = sienna_cichlid_od_setting_check_range(smu, od_settings, 2314 freq_setting, input[i + 1]); 2315 if (ret) 2316 return ret; 2317 2318 *freq_ptr = (uint16_t)input[i + 1]; 2319 } 2320 break; 2321 2322 case PP_OD_RESTORE_DEFAULT_TABLE: 2323 memcpy(table_context->overdrive_table, 2324 table_context->boot_overdrive_table, 2325 sizeof(OverDriveTable_t)); 2326 fallthrough; 2327 2328 case PP_OD_COMMIT_DPM_TABLE: 2329 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) { 2330 sienna_cichlid_dump_od_table(smu, od_table); 2331 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true); 2332 if (ret) { 2333 dev_err(smu->adev->dev, "Failed to import overdrive table!\n"); 2334 return ret; 2335 } 2336 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t)); 2337 smu->user_dpm_profile.user_od = true; 2338 2339 if (!memcmp(table_context->user_overdrive_table, 2340 table_context->boot_overdrive_table, 2341 sizeof(OverDriveTable_t))) 2342 smu->user_dpm_profile.user_od = false; 2343 } 2344 break; 2345 2346 case PP_OD_EDIT_VDDGFX_OFFSET: 2347 if (size != 1) { 2348 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size); 2349 return -EINVAL; 2350 } 2351 2352 /* 2353 * OD GFX Voltage Offset functionality is supported only by 58.41.0 2354 * and onwards SMU firmwares. 2355 */ 2356 smu_cmn_get_smc_version(smu, NULL, &smu_version); 2357 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 2358 (smu_version < 0x003a2900)) { 2359 dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported " 2360 "only by 58.41.0 and onwards SMU firmwares!\n"); 2361 return -EOPNOTSUPP; 2362 } 2363 2364 od_table->VddGfxOffset = (int16_t)input[0]; 2365 2366 sienna_cichlid_dump_od_table(smu, od_table); 2367 break; 2368 2369 default: 2370 return -ENOSYS; 2371 } 2372 2373 return ret; 2374 } 2375 2376 static int sienna_cichlid_run_btc(struct smu_context *smu) 2377 { 2378 int res; 2379 2380 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); 2381 if (res) 2382 dev_err(smu->adev->dev, "RunDcBtc failed!\n"); 2383 2384 return res; 2385 } 2386 2387 static int sienna_cichlid_baco_enter(struct smu_context *smu) 2388 { 2389 struct amdgpu_device *adev = smu->adev; 2390 2391 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) 2392 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO); 2393 else 2394 return smu_v11_0_baco_enter(smu); 2395 } 2396 2397 static int sienna_cichlid_baco_exit(struct smu_context *smu) 2398 { 2399 struct amdgpu_device *adev = smu->adev; 2400 2401 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) { 2402 /* Wait for PMFW handling for the Dstate change */ 2403 msleep(10); 2404 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS); 2405 } else { 2406 return smu_v11_0_baco_exit(smu); 2407 } 2408 } 2409 2410 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu) 2411 { 2412 struct amdgpu_device *adev = smu->adev; 2413 uint32_t val; 2414 u32 smu_version; 2415 2416 /** 2417 * SRIOV env will not support SMU mode1 reset 2418 * PM FW support mode1 reset from 58.26 2419 */ 2420 smu_cmn_get_smc_version(smu, NULL, &smu_version); 2421 if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00)) 2422 return false; 2423 2424 /** 2425 * mode1 reset relies on PSP, so we should check if 2426 * PSP is alive. 2427 */ 2428 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 2429 return val != 0x0; 2430 } 2431 2432 static void beige_goby_dump_pptable(struct smu_context *smu) 2433 { 2434 struct smu_table_context *table_context = &smu->smu_table; 2435 PPTable_beige_goby_t *pptable = table_context->driver_pptable; 2436 int i; 2437 2438 dev_info(smu->adev->dev, "Dumped PPTable:\n"); 2439 2440 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version); 2441 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]); 2442 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]); 2443 2444 for (i = 0; i < PPT_THROTTLER_COUNT; i++) { 2445 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]); 2446 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]); 2447 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]); 2448 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]); 2449 } 2450 2451 for (i = 0; i < TDC_THROTTLER_COUNT; i++) { 2452 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]); 2453 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]); 2454 } 2455 2456 for (i = 0; i < TEMP_COUNT; i++) { 2457 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]); 2458 } 2459 2460 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit); 2461 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig); 2462 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]); 2463 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]); 2464 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]); 2465 2466 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit); 2467 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) { 2468 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]); 2469 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]); 2470 } 2471 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask); 2472 2473 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask); 2474 2475 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc); 2476 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx); 2477 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx); 2478 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc); 2479 2480 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin); 2481 2482 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold); 2483 2484 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx); 2485 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc); 2486 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx); 2487 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc); 2488 2489 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx); 2490 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc); 2491 2492 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin); 2493 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin); 2494 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp); 2495 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp); 2496 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp); 2497 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp); 2498 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis); 2499 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis); 2500 2501 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n" 2502 " .VoltageMode = 0x%02x\n" 2503 " .SnapToDiscrete = 0x%02x\n" 2504 " .NumDiscreteLevels = 0x%02x\n" 2505 " .padding = 0x%02x\n" 2506 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2507 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2508 " .SsFmin = 0x%04x\n" 2509 " .Padding_16 = 0x%04x\n", 2510 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode, 2511 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete, 2512 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels, 2513 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding, 2514 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m, 2515 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b, 2516 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a, 2517 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b, 2518 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c, 2519 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin, 2520 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16); 2521 2522 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n" 2523 " .VoltageMode = 0x%02x\n" 2524 " .SnapToDiscrete = 0x%02x\n" 2525 " .NumDiscreteLevels = 0x%02x\n" 2526 " .padding = 0x%02x\n" 2527 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2528 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2529 " .SsFmin = 0x%04x\n" 2530 " .Padding_16 = 0x%04x\n", 2531 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode, 2532 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete, 2533 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels, 2534 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding, 2535 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m, 2536 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b, 2537 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a, 2538 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b, 2539 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c, 2540 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin, 2541 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16); 2542 2543 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n" 2544 " .VoltageMode = 0x%02x\n" 2545 " .SnapToDiscrete = 0x%02x\n" 2546 " .NumDiscreteLevels = 0x%02x\n" 2547 " .padding = 0x%02x\n" 2548 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2549 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2550 " .SsFmin = 0x%04x\n" 2551 " .Padding_16 = 0x%04x\n", 2552 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode, 2553 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete, 2554 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels, 2555 pptable->DpmDescriptor[PPCLK_UCLK].Padding, 2556 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m, 2557 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b, 2558 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a, 2559 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b, 2560 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c, 2561 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin, 2562 pptable->DpmDescriptor[PPCLK_UCLK].Padding16); 2563 2564 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n" 2565 " .VoltageMode = 0x%02x\n" 2566 " .SnapToDiscrete = 0x%02x\n" 2567 " .NumDiscreteLevels = 0x%02x\n" 2568 " .padding = 0x%02x\n" 2569 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2570 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2571 " .SsFmin = 0x%04x\n" 2572 " .Padding_16 = 0x%04x\n", 2573 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode, 2574 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete, 2575 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels, 2576 pptable->DpmDescriptor[PPCLK_FCLK].Padding, 2577 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m, 2578 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b, 2579 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a, 2580 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b, 2581 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c, 2582 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin, 2583 pptable->DpmDescriptor[PPCLK_FCLK].Padding16); 2584 2585 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n" 2586 " .VoltageMode = 0x%02x\n" 2587 " .SnapToDiscrete = 0x%02x\n" 2588 " .NumDiscreteLevels = 0x%02x\n" 2589 " .padding = 0x%02x\n" 2590 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2591 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2592 " .SsFmin = 0x%04x\n" 2593 " .Padding_16 = 0x%04x\n", 2594 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode, 2595 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete, 2596 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels, 2597 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding, 2598 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m, 2599 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b, 2600 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a, 2601 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b, 2602 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c, 2603 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin, 2604 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16); 2605 2606 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n" 2607 " .VoltageMode = 0x%02x\n" 2608 " .SnapToDiscrete = 0x%02x\n" 2609 " .NumDiscreteLevels = 0x%02x\n" 2610 " .padding = 0x%02x\n" 2611 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2612 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2613 " .SsFmin = 0x%04x\n" 2614 " .Padding_16 = 0x%04x\n", 2615 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode, 2616 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete, 2617 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels, 2618 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding, 2619 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m, 2620 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b, 2621 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a, 2622 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b, 2623 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c, 2624 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin, 2625 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16); 2626 2627 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n" 2628 " .VoltageMode = 0x%02x\n" 2629 " .SnapToDiscrete = 0x%02x\n" 2630 " .NumDiscreteLevels = 0x%02x\n" 2631 " .padding = 0x%02x\n" 2632 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2633 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2634 " .SsFmin = 0x%04x\n" 2635 " .Padding_16 = 0x%04x\n", 2636 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode, 2637 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete, 2638 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels, 2639 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding, 2640 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m, 2641 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b, 2642 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a, 2643 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b, 2644 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c, 2645 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin, 2646 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16); 2647 2648 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n" 2649 " .VoltageMode = 0x%02x\n" 2650 " .SnapToDiscrete = 0x%02x\n" 2651 " .NumDiscreteLevels = 0x%02x\n" 2652 " .padding = 0x%02x\n" 2653 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2654 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2655 " .SsFmin = 0x%04x\n" 2656 " .Padding_16 = 0x%04x\n", 2657 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode, 2658 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete, 2659 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels, 2660 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding, 2661 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m, 2662 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b, 2663 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a, 2664 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b, 2665 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c, 2666 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin, 2667 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16); 2668 2669 dev_info(smu->adev->dev, "FreqTableGfx\n"); 2670 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) 2671 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]); 2672 2673 dev_info(smu->adev->dev, "FreqTableVclk\n"); 2674 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++) 2675 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]); 2676 2677 dev_info(smu->adev->dev, "FreqTableDclk\n"); 2678 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++) 2679 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]); 2680 2681 dev_info(smu->adev->dev, "FreqTableSocclk\n"); 2682 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) 2683 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]); 2684 2685 dev_info(smu->adev->dev, "FreqTableUclk\n"); 2686 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2687 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]); 2688 2689 dev_info(smu->adev->dev, "FreqTableFclk\n"); 2690 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) 2691 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]); 2692 2693 dev_info(smu->adev->dev, "DcModeMaxFreq\n"); 2694 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]); 2695 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]); 2696 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]); 2697 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]); 2698 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]); 2699 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]); 2700 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]); 2701 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]); 2702 2703 dev_info(smu->adev->dev, "FreqTableUclkDiv\n"); 2704 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2705 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]); 2706 2707 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq); 2708 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding); 2709 2710 dev_info(smu->adev->dev, "Mp0clkFreq\n"); 2711 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 2712 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]); 2713 2714 dev_info(smu->adev->dev, "Mp0DpmVoltage\n"); 2715 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 2716 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]); 2717 2718 dev_info(smu->adev->dev, "MemVddciVoltage\n"); 2719 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2720 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]); 2721 2722 dev_info(smu->adev->dev, "MemMvddVoltage\n"); 2723 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2724 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]); 2725 2726 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry); 2727 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit); 2728 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle); 2729 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource); 2730 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding); 2731 2732 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask); 2733 2734 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask); 2735 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask); 2736 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]); 2737 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow); 2738 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]); 2739 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]); 2740 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]); 2741 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]); 2742 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt); 2743 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt); 2744 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt); 2745 2746 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage); 2747 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime); 2748 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime); 2749 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum); 2750 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis); 2751 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout); 2752 2753 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]); 2754 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]); 2755 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]); 2756 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]); 2757 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]); 2758 2759 dev_info(smu->adev->dev, "FlopsPerByteTable\n"); 2760 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++) 2761 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]); 2762 2763 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv); 2764 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]); 2765 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]); 2766 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]); 2767 2768 dev_info(smu->adev->dev, "UclkDpmPstates\n"); 2769 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2770 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]); 2771 2772 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n"); 2773 dev_info(smu->adev->dev, " .Fmin = 0x%x\n", 2774 pptable->UclkDpmSrcFreqRange.Fmin); 2775 dev_info(smu->adev->dev, " .Fmax = 0x%x\n", 2776 pptable->UclkDpmSrcFreqRange.Fmax); 2777 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n"); 2778 dev_info(smu->adev->dev, " .Fmin = 0x%x\n", 2779 pptable->UclkDpmTargFreqRange.Fmin); 2780 dev_info(smu->adev->dev, " .Fmax = 0x%x\n", 2781 pptable->UclkDpmTargFreqRange.Fmax); 2782 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq); 2783 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding); 2784 2785 dev_info(smu->adev->dev, "PcieGenSpeed\n"); 2786 for (i = 0; i < NUM_LINK_LEVELS; i++) 2787 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]); 2788 2789 dev_info(smu->adev->dev, "PcieLaneCount\n"); 2790 for (i = 0; i < NUM_LINK_LEVELS; i++) 2791 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]); 2792 2793 dev_info(smu->adev->dev, "LclkFreq\n"); 2794 for (i = 0; i < NUM_LINK_LEVELS; i++) 2795 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]); 2796 2797 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp); 2798 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp); 2799 2800 dev_info(smu->adev->dev, "FanGain\n"); 2801 for (i = 0; i < TEMP_COUNT; i++) 2802 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]); 2803 2804 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin); 2805 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm); 2806 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm); 2807 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm); 2808 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm); 2809 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature); 2810 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk); 2811 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16); 2812 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect); 2813 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding); 2814 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable); 2815 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev); 2816 2817 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta); 2818 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta); 2819 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta); 2820 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved); 2821 2822 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]); 2823 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]); 2824 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect); 2825 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs); 2826 2827 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", 2828 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a, 2829 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b, 2830 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c); 2831 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", 2832 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a, 2833 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b, 2834 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c); 2835 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n", 2836 pptable->dBtcGbGfxPll.a, 2837 pptable->dBtcGbGfxPll.b, 2838 pptable->dBtcGbGfxPll.c); 2839 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n", 2840 pptable->dBtcGbGfxDfll.a, 2841 pptable->dBtcGbGfxDfll.b, 2842 pptable->dBtcGbGfxDfll.c); 2843 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n", 2844 pptable->dBtcGbSoc.a, 2845 pptable->dBtcGbSoc.b, 2846 pptable->dBtcGbSoc.c); 2847 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n", 2848 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m, 2849 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b); 2850 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n", 2851 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m, 2852 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b); 2853 2854 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n"); 2855 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) { 2856 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n", 2857 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]); 2858 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n", 2859 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]); 2860 } 2861 2862 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", 2863 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a, 2864 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b, 2865 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c); 2866 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", 2867 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a, 2868 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b, 2869 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c); 2870 2871 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]); 2872 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]); 2873 2874 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]); 2875 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]); 2876 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]); 2877 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]); 2878 2879 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]); 2880 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]); 2881 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]); 2882 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]); 2883 2884 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]); 2885 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]); 2886 2887 dev_info(smu->adev->dev, "XgmiDpmPstates\n"); 2888 for (i = 0; i < NUM_XGMI_LEVELS; i++) 2889 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]); 2890 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]); 2891 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]); 2892 2893 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides); 2894 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n", 2895 pptable->ReservedEquation0.a, 2896 pptable->ReservedEquation0.b, 2897 pptable->ReservedEquation0.c); 2898 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n", 2899 pptable->ReservedEquation1.a, 2900 pptable->ReservedEquation1.b, 2901 pptable->ReservedEquation1.c); 2902 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n", 2903 pptable->ReservedEquation2.a, 2904 pptable->ReservedEquation2.b, 2905 pptable->ReservedEquation2.c); 2906 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n", 2907 pptable->ReservedEquation3.a, 2908 pptable->ReservedEquation3.b, 2909 pptable->ReservedEquation3.c); 2910 2911 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]); 2912 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]); 2913 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]); 2914 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]); 2915 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]); 2916 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]); 2917 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]); 2918 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]); 2919 2920 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]); 2921 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]); 2922 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]); 2923 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]); 2924 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]); 2925 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]); 2926 2927 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) { 2928 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i); 2929 dev_info(smu->adev->dev, " .Enabled = 0x%x\n", 2930 pptable->I2cControllers[i].Enabled); 2931 dev_info(smu->adev->dev, " .Speed = 0x%x\n", 2932 pptable->I2cControllers[i].Speed); 2933 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n", 2934 pptable->I2cControllers[i].SlaveAddress); 2935 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n", 2936 pptable->I2cControllers[i].ControllerPort); 2937 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n", 2938 pptable->I2cControllers[i].ControllerName); 2939 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n", 2940 pptable->I2cControllers[i].ThermalThrotter); 2941 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n", 2942 pptable->I2cControllers[i].I2cProtocol); 2943 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n", 2944 pptable->I2cControllers[i].PaddingConfig); 2945 } 2946 2947 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl); 2948 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda); 2949 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr); 2950 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]); 2951 2952 dev_info(smu->adev->dev, "Board Parameters:\n"); 2953 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping); 2954 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping); 2955 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping); 2956 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping); 2957 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask); 2958 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask); 2959 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask); 2960 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask); 2961 2962 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent); 2963 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset); 2964 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx); 2965 2966 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent); 2967 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset); 2968 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc); 2969 2970 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent); 2971 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset); 2972 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0); 2973 2974 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent); 2975 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset); 2976 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1); 2977 2978 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio); 2979 2980 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio); 2981 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity); 2982 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio); 2983 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity); 2984 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio); 2985 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity); 2986 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio); 2987 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity); 2988 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0); 2989 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1); 2990 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2); 2991 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask); 2992 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie); 2993 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError); 2994 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]); 2995 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]); 2996 2997 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled); 2998 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent); 2999 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq); 3000 3001 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled); 3002 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent); 3003 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq); 3004 3005 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding); 3006 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq); 3007 3008 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled); 3009 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent); 3010 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq); 3011 3012 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled); 3013 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth); 3014 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]); 3015 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]); 3016 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]); 3017 3018 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower); 3019 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding); 3020 3021 dev_info(smu->adev->dev, "XgmiLinkSpeed\n"); 3022 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3023 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]); 3024 dev_info(smu->adev->dev, "XgmiLinkWidth\n"); 3025 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3026 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]); 3027 dev_info(smu->adev->dev, "XgmiFclkFreq\n"); 3028 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3029 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]); 3030 dev_info(smu->adev->dev, "XgmiSocVoltage\n"); 3031 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3032 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]); 3033 3034 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled); 3035 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled); 3036 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]); 3037 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]); 3038 3039 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]); 3040 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]); 3041 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]); 3042 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]); 3043 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]); 3044 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]); 3045 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]); 3046 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]); 3047 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]); 3048 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]); 3049 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]); 3050 3051 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]); 3052 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]); 3053 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]); 3054 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]); 3055 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]); 3056 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]); 3057 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]); 3058 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]); 3059 } 3060 3061 static void sienna_cichlid_dump_pptable(struct smu_context *smu) 3062 { 3063 struct smu_table_context *table_context = &smu->smu_table; 3064 PPTable_t *pptable = table_context->driver_pptable; 3065 int i; 3066 3067 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) { 3068 beige_goby_dump_pptable(smu); 3069 return; 3070 } 3071 3072 dev_info(smu->adev->dev, "Dumped PPTable:\n"); 3073 3074 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version); 3075 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]); 3076 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]); 3077 3078 for (i = 0; i < PPT_THROTTLER_COUNT; i++) { 3079 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]); 3080 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]); 3081 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]); 3082 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]); 3083 } 3084 3085 for (i = 0; i < TDC_THROTTLER_COUNT; i++) { 3086 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]); 3087 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]); 3088 } 3089 3090 for (i = 0; i < TEMP_COUNT; i++) { 3091 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]); 3092 } 3093 3094 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit); 3095 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig); 3096 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]); 3097 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]); 3098 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]); 3099 3100 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit); 3101 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) { 3102 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]); 3103 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]); 3104 } 3105 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask); 3106 3107 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask); 3108 3109 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc); 3110 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx); 3111 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx); 3112 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc); 3113 3114 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin); 3115 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin); 3116 3117 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold); 3118 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]); 3119 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]); 3120 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]); 3121 3122 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx); 3123 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc); 3124 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx); 3125 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc); 3126 3127 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx); 3128 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc); 3129 3130 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin); 3131 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin); 3132 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp); 3133 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp); 3134 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp); 3135 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp); 3136 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis); 3137 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis); 3138 3139 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n" 3140 " .VoltageMode = 0x%02x\n" 3141 " .SnapToDiscrete = 0x%02x\n" 3142 " .NumDiscreteLevels = 0x%02x\n" 3143 " .padding = 0x%02x\n" 3144 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3145 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3146 " .SsFmin = 0x%04x\n" 3147 " .Padding_16 = 0x%04x\n", 3148 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode, 3149 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete, 3150 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels, 3151 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding, 3152 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m, 3153 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b, 3154 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a, 3155 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b, 3156 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c, 3157 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin, 3158 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16); 3159 3160 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n" 3161 " .VoltageMode = 0x%02x\n" 3162 " .SnapToDiscrete = 0x%02x\n" 3163 " .NumDiscreteLevels = 0x%02x\n" 3164 " .padding = 0x%02x\n" 3165 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3166 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3167 " .SsFmin = 0x%04x\n" 3168 " .Padding_16 = 0x%04x\n", 3169 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode, 3170 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete, 3171 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels, 3172 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding, 3173 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m, 3174 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b, 3175 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a, 3176 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b, 3177 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c, 3178 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin, 3179 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16); 3180 3181 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n" 3182 " .VoltageMode = 0x%02x\n" 3183 " .SnapToDiscrete = 0x%02x\n" 3184 " .NumDiscreteLevels = 0x%02x\n" 3185 " .padding = 0x%02x\n" 3186 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3187 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3188 " .SsFmin = 0x%04x\n" 3189 " .Padding_16 = 0x%04x\n", 3190 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode, 3191 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete, 3192 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels, 3193 pptable->DpmDescriptor[PPCLK_UCLK].Padding, 3194 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m, 3195 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b, 3196 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a, 3197 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b, 3198 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c, 3199 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin, 3200 pptable->DpmDescriptor[PPCLK_UCLK].Padding16); 3201 3202 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n" 3203 " .VoltageMode = 0x%02x\n" 3204 " .SnapToDiscrete = 0x%02x\n" 3205 " .NumDiscreteLevels = 0x%02x\n" 3206 " .padding = 0x%02x\n" 3207 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3208 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3209 " .SsFmin = 0x%04x\n" 3210 " .Padding_16 = 0x%04x\n", 3211 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode, 3212 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete, 3213 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels, 3214 pptable->DpmDescriptor[PPCLK_FCLK].Padding, 3215 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m, 3216 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b, 3217 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a, 3218 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b, 3219 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c, 3220 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin, 3221 pptable->DpmDescriptor[PPCLK_FCLK].Padding16); 3222 3223 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n" 3224 " .VoltageMode = 0x%02x\n" 3225 " .SnapToDiscrete = 0x%02x\n" 3226 " .NumDiscreteLevels = 0x%02x\n" 3227 " .padding = 0x%02x\n" 3228 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3229 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3230 " .SsFmin = 0x%04x\n" 3231 " .Padding_16 = 0x%04x\n", 3232 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode, 3233 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete, 3234 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels, 3235 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding, 3236 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m, 3237 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b, 3238 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a, 3239 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b, 3240 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c, 3241 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin, 3242 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16); 3243 3244 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n" 3245 " .VoltageMode = 0x%02x\n" 3246 " .SnapToDiscrete = 0x%02x\n" 3247 " .NumDiscreteLevels = 0x%02x\n" 3248 " .padding = 0x%02x\n" 3249 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3250 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3251 " .SsFmin = 0x%04x\n" 3252 " .Padding_16 = 0x%04x\n", 3253 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode, 3254 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete, 3255 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels, 3256 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding, 3257 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m, 3258 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b, 3259 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a, 3260 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b, 3261 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c, 3262 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin, 3263 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16); 3264 3265 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n" 3266 " .VoltageMode = 0x%02x\n" 3267 " .SnapToDiscrete = 0x%02x\n" 3268 " .NumDiscreteLevels = 0x%02x\n" 3269 " .padding = 0x%02x\n" 3270 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3271 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3272 " .SsFmin = 0x%04x\n" 3273 " .Padding_16 = 0x%04x\n", 3274 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode, 3275 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete, 3276 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels, 3277 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding, 3278 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m, 3279 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b, 3280 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a, 3281 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b, 3282 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c, 3283 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin, 3284 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16); 3285 3286 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n" 3287 " .VoltageMode = 0x%02x\n" 3288 " .SnapToDiscrete = 0x%02x\n" 3289 " .NumDiscreteLevels = 0x%02x\n" 3290 " .padding = 0x%02x\n" 3291 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3292 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3293 " .SsFmin = 0x%04x\n" 3294 " .Padding_16 = 0x%04x\n", 3295 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode, 3296 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete, 3297 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels, 3298 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding, 3299 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m, 3300 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b, 3301 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a, 3302 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b, 3303 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c, 3304 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin, 3305 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16); 3306 3307 dev_info(smu->adev->dev, "FreqTableGfx\n"); 3308 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) 3309 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]); 3310 3311 dev_info(smu->adev->dev, "FreqTableVclk\n"); 3312 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++) 3313 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]); 3314 3315 dev_info(smu->adev->dev, "FreqTableDclk\n"); 3316 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++) 3317 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]); 3318 3319 dev_info(smu->adev->dev, "FreqTableSocclk\n"); 3320 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) 3321 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]); 3322 3323 dev_info(smu->adev->dev, "FreqTableUclk\n"); 3324 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 3325 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]); 3326 3327 dev_info(smu->adev->dev, "FreqTableFclk\n"); 3328 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) 3329 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]); 3330 3331 dev_info(smu->adev->dev, "DcModeMaxFreq\n"); 3332 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]); 3333 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]); 3334 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]); 3335 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]); 3336 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]); 3337 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]); 3338 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]); 3339 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]); 3340 3341 dev_info(smu->adev->dev, "FreqTableUclkDiv\n"); 3342 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 3343 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]); 3344 3345 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq); 3346 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding); 3347 3348 dev_info(smu->adev->dev, "Mp0clkFreq\n"); 3349 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 3350 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]); 3351 3352 dev_info(smu->adev->dev, "Mp0DpmVoltage\n"); 3353 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 3354 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]); 3355 3356 dev_info(smu->adev->dev, "MemVddciVoltage\n"); 3357 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 3358 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]); 3359 3360 dev_info(smu->adev->dev, "MemMvddVoltage\n"); 3361 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 3362 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]); 3363 3364 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry); 3365 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit); 3366 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle); 3367 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource); 3368 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding); 3369 3370 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask); 3371 3372 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask); 3373 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask); 3374 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]); 3375 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow); 3376 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]); 3377 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]); 3378 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]); 3379 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]); 3380 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt); 3381 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt); 3382 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt); 3383 3384 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage); 3385 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime); 3386 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime); 3387 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum); 3388 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis); 3389 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout); 3390 3391 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]); 3392 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]); 3393 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]); 3394 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]); 3395 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]); 3396 3397 dev_info(smu->adev->dev, "FlopsPerByteTable\n"); 3398 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++) 3399 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]); 3400 3401 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv); 3402 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]); 3403 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]); 3404 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]); 3405 3406 dev_info(smu->adev->dev, "UclkDpmPstates\n"); 3407 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 3408 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]); 3409 3410 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n"); 3411 dev_info(smu->adev->dev, " .Fmin = 0x%x\n", 3412 pptable->UclkDpmSrcFreqRange.Fmin); 3413 dev_info(smu->adev->dev, " .Fmax = 0x%x\n", 3414 pptable->UclkDpmSrcFreqRange.Fmax); 3415 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n"); 3416 dev_info(smu->adev->dev, " .Fmin = 0x%x\n", 3417 pptable->UclkDpmTargFreqRange.Fmin); 3418 dev_info(smu->adev->dev, " .Fmax = 0x%x\n", 3419 pptable->UclkDpmTargFreqRange.Fmax); 3420 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq); 3421 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding); 3422 3423 dev_info(smu->adev->dev, "PcieGenSpeed\n"); 3424 for (i = 0; i < NUM_LINK_LEVELS; i++) 3425 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]); 3426 3427 dev_info(smu->adev->dev, "PcieLaneCount\n"); 3428 for (i = 0; i < NUM_LINK_LEVELS; i++) 3429 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]); 3430 3431 dev_info(smu->adev->dev, "LclkFreq\n"); 3432 for (i = 0; i < NUM_LINK_LEVELS; i++) 3433 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]); 3434 3435 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp); 3436 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp); 3437 3438 dev_info(smu->adev->dev, "FanGain\n"); 3439 for (i = 0; i < TEMP_COUNT; i++) 3440 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]); 3441 3442 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin); 3443 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm); 3444 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm); 3445 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm); 3446 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm); 3447 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature); 3448 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk); 3449 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16); 3450 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect); 3451 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding); 3452 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable); 3453 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev); 3454 3455 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta); 3456 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta); 3457 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta); 3458 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved); 3459 3460 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]); 3461 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]); 3462 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect); 3463 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs); 3464 3465 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", 3466 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a, 3467 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b, 3468 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c); 3469 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", 3470 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a, 3471 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b, 3472 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c); 3473 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n", 3474 pptable->dBtcGbGfxPll.a, 3475 pptable->dBtcGbGfxPll.b, 3476 pptable->dBtcGbGfxPll.c); 3477 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n", 3478 pptable->dBtcGbGfxDfll.a, 3479 pptable->dBtcGbGfxDfll.b, 3480 pptable->dBtcGbGfxDfll.c); 3481 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n", 3482 pptable->dBtcGbSoc.a, 3483 pptable->dBtcGbSoc.b, 3484 pptable->dBtcGbSoc.c); 3485 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n", 3486 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m, 3487 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b); 3488 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n", 3489 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m, 3490 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b); 3491 3492 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n"); 3493 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) { 3494 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n", 3495 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]); 3496 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n", 3497 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]); 3498 } 3499 3500 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", 3501 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a, 3502 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b, 3503 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c); 3504 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", 3505 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a, 3506 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b, 3507 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c); 3508 3509 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]); 3510 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]); 3511 3512 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]); 3513 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]); 3514 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]); 3515 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]); 3516 3517 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]); 3518 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]); 3519 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]); 3520 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]); 3521 3522 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]); 3523 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]); 3524 3525 dev_info(smu->adev->dev, "XgmiDpmPstates\n"); 3526 for (i = 0; i < NUM_XGMI_LEVELS; i++) 3527 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]); 3528 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]); 3529 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]); 3530 3531 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides); 3532 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n", 3533 pptable->ReservedEquation0.a, 3534 pptable->ReservedEquation0.b, 3535 pptable->ReservedEquation0.c); 3536 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n", 3537 pptable->ReservedEquation1.a, 3538 pptable->ReservedEquation1.b, 3539 pptable->ReservedEquation1.c); 3540 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n", 3541 pptable->ReservedEquation2.a, 3542 pptable->ReservedEquation2.b, 3543 pptable->ReservedEquation2.c); 3544 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n", 3545 pptable->ReservedEquation3.a, 3546 pptable->ReservedEquation3.b, 3547 pptable->ReservedEquation3.c); 3548 3549 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]); 3550 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]); 3551 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]); 3552 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]); 3553 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]); 3554 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]); 3555 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]); 3556 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]); 3557 3558 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]); 3559 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]); 3560 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]); 3561 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]); 3562 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]); 3563 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]); 3564 3565 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) { 3566 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i); 3567 dev_info(smu->adev->dev, " .Enabled = 0x%x\n", 3568 pptable->I2cControllers[i].Enabled); 3569 dev_info(smu->adev->dev, " .Speed = 0x%x\n", 3570 pptable->I2cControllers[i].Speed); 3571 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n", 3572 pptable->I2cControllers[i].SlaveAddress); 3573 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n", 3574 pptable->I2cControllers[i].ControllerPort); 3575 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n", 3576 pptable->I2cControllers[i].ControllerName); 3577 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n", 3578 pptable->I2cControllers[i].ThermalThrotter); 3579 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n", 3580 pptable->I2cControllers[i].I2cProtocol); 3581 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n", 3582 pptable->I2cControllers[i].PaddingConfig); 3583 } 3584 3585 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl); 3586 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda); 3587 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr); 3588 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]); 3589 3590 dev_info(smu->adev->dev, "Board Parameters:\n"); 3591 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping); 3592 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping); 3593 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping); 3594 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping); 3595 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask); 3596 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask); 3597 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask); 3598 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask); 3599 3600 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent); 3601 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset); 3602 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx); 3603 3604 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent); 3605 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset); 3606 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc); 3607 3608 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent); 3609 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset); 3610 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0); 3611 3612 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent); 3613 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset); 3614 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1); 3615 3616 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio); 3617 3618 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio); 3619 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity); 3620 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio); 3621 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity); 3622 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio); 3623 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity); 3624 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio); 3625 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity); 3626 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0); 3627 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1); 3628 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2); 3629 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask); 3630 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie); 3631 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError); 3632 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]); 3633 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]); 3634 3635 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled); 3636 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent); 3637 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq); 3638 3639 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled); 3640 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent); 3641 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq); 3642 3643 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding); 3644 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq); 3645 3646 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled); 3647 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent); 3648 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq); 3649 3650 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled); 3651 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth); 3652 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]); 3653 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]); 3654 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]); 3655 3656 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower); 3657 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding); 3658 3659 dev_info(smu->adev->dev, "XgmiLinkSpeed\n"); 3660 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3661 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]); 3662 dev_info(smu->adev->dev, "XgmiLinkWidth\n"); 3663 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3664 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]); 3665 dev_info(smu->adev->dev, "XgmiFclkFreq\n"); 3666 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3667 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]); 3668 dev_info(smu->adev->dev, "XgmiSocVoltage\n"); 3669 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3670 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]); 3671 3672 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled); 3673 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled); 3674 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]); 3675 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]); 3676 3677 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]); 3678 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]); 3679 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]); 3680 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]); 3681 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]); 3682 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]); 3683 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]); 3684 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]); 3685 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]); 3686 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]); 3687 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]); 3688 3689 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]); 3690 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]); 3691 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]); 3692 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]); 3693 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]); 3694 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]); 3695 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]); 3696 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]); 3697 } 3698 3699 static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap, 3700 struct i2c_msg *msg, int num_msgs) 3701 { 3702 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap); 3703 struct amdgpu_device *adev = smu_i2c->adev; 3704 struct smu_context *smu = adev->powerplay.pp_handle; 3705 struct smu_table_context *smu_table = &smu->smu_table; 3706 struct smu_table *table = &smu_table->driver_table; 3707 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 3708 int i, j, r, c; 3709 u16 dir; 3710 3711 if (!adev->pm.dpm_enabled) 3712 return -EBUSY; 3713 3714 req = kzalloc(sizeof(*req), GFP_KERNEL); 3715 if (!req) 3716 return -ENOMEM; 3717 3718 req->I2CcontrollerPort = smu_i2c->port; 3719 req->I2CSpeed = I2C_SPEED_FAST_400K; 3720 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 3721 dir = msg[0].flags & I2C_M_RD; 3722 3723 for (c = i = 0; i < num_msgs; i++) { 3724 for (j = 0; j < msg[i].len; j++, c++) { 3725 SwI2cCmd_t *cmd = &req->SwI2cCmds[c]; 3726 3727 if (!(msg[i].flags & I2C_M_RD)) { 3728 /* write */ 3729 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK; 3730 cmd->ReadWriteData = msg[i].buf[j]; 3731 } 3732 3733 if ((dir ^ msg[i].flags) & I2C_M_RD) { 3734 /* The direction changes. 3735 */ 3736 dir = msg[i].flags & I2C_M_RD; 3737 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK; 3738 } 3739 3740 req->NumCmds++; 3741 3742 /* 3743 * Insert STOP if we are at the last byte of either last 3744 * message for the transaction or the client explicitly 3745 * requires a STOP at this particular message. 3746 */ 3747 if ((j == msg[i].len - 1) && 3748 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) { 3749 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK; 3750 cmd->CmdConfig |= CMDCONFIG_STOP_MASK; 3751 } 3752 } 3753 } 3754 mutex_lock(&adev->pm.mutex); 3755 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 3756 mutex_unlock(&adev->pm.mutex); 3757 if (r) 3758 goto fail; 3759 3760 for (c = i = 0; i < num_msgs; i++) { 3761 if (!(msg[i].flags & I2C_M_RD)) { 3762 c += msg[i].len; 3763 continue; 3764 } 3765 for (j = 0; j < msg[i].len; j++, c++) { 3766 SwI2cCmd_t *cmd = &res->SwI2cCmds[c]; 3767 3768 msg[i].buf[j] = cmd->ReadWriteData; 3769 } 3770 } 3771 r = num_msgs; 3772 fail: 3773 kfree(req); 3774 return r; 3775 } 3776 3777 static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap) 3778 { 3779 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 3780 } 3781 3782 3783 static const struct i2c_algorithm sienna_cichlid_i2c_algo = { 3784 .master_xfer = sienna_cichlid_i2c_xfer, 3785 .functionality = sienna_cichlid_i2c_func, 3786 }; 3787 3788 static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = { 3789 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN, 3790 .max_read_len = MAX_SW_I2C_COMMANDS, 3791 .max_write_len = MAX_SW_I2C_COMMANDS, 3792 .max_comb_1st_msg_len = 2, 3793 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 3794 }; 3795 3796 static int sienna_cichlid_i2c_control_init(struct smu_context *smu) 3797 { 3798 struct amdgpu_device *adev = smu->adev; 3799 int res, i; 3800 3801 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 3802 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 3803 struct i2c_adapter *control = &smu_i2c->adapter; 3804 3805 smu_i2c->adev = adev; 3806 smu_i2c->port = i; 3807 mutex_init(&smu_i2c->mutex); 3808 control->owner = THIS_MODULE; 3809 control->class = I2C_CLASS_HWMON; 3810 control->dev.parent = &adev->pdev->dev; 3811 control->algo = &sienna_cichlid_i2c_algo; 3812 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i); 3813 control->quirks = &sienna_cichlid_i2c_control_quirks; 3814 i2c_set_adapdata(control, smu_i2c); 3815 3816 res = i2c_add_adapter(control); 3817 if (res) { 3818 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 3819 goto Out_err; 3820 } 3821 } 3822 /* assign the buses used for the FRU EEPROM and RAS EEPROM */ 3823 /* XXX ideally this would be something in a vbios data table */ 3824 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter; 3825 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 3826 3827 return 0; 3828 Out_err: 3829 for ( ; i >= 0; i--) { 3830 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 3831 struct i2c_adapter *control = &smu_i2c->adapter; 3832 3833 i2c_del_adapter(control); 3834 } 3835 return res; 3836 } 3837 3838 static void sienna_cichlid_i2c_control_fini(struct smu_context *smu) 3839 { 3840 struct amdgpu_device *adev = smu->adev; 3841 int i; 3842 3843 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 3844 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 3845 struct i2c_adapter *control = &smu_i2c->adapter; 3846 3847 i2c_del_adapter(control); 3848 } 3849 adev->pm.ras_eeprom_i2c_bus = NULL; 3850 adev->pm.fru_eeprom_i2c_bus = NULL; 3851 } 3852 3853 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu, 3854 void **table) 3855 { 3856 struct smu_table_context *smu_table = &smu->smu_table; 3857 struct gpu_metrics_v1_3 *gpu_metrics = 3858 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 3859 SmuMetricsExternal_t metrics_external; 3860 SmuMetrics_t *metrics = 3861 &(metrics_external.SmuMetrics); 3862 SmuMetrics_V2_t *metrics_v2 = 3863 &(metrics_external.SmuMetrics_V2); 3864 SmuMetrics_V3_t *metrics_v3 = 3865 &(metrics_external.SmuMetrics_V3); 3866 struct amdgpu_device *adev = smu->adev; 3867 bool use_metrics_v2 = false; 3868 bool use_metrics_v3 = false; 3869 uint16_t average_gfx_activity; 3870 int ret = 0; 3871 3872 switch (smu->adev->ip_versions[MP1_HWIP][0]) { 3873 case IP_VERSION(11, 0, 7): 3874 if (smu->smc_fw_version >= 0x3A4900) 3875 use_metrics_v3 = true; 3876 else if (smu->smc_fw_version >= 0x3A4300) 3877 use_metrics_v2 = true; 3878 break; 3879 case IP_VERSION(11, 0, 11): 3880 if (smu->smc_fw_version >= 0x412D00) 3881 use_metrics_v2 = true; 3882 break; 3883 case IP_VERSION(11, 0, 12): 3884 if (smu->smc_fw_version >= 0x3B2300) 3885 use_metrics_v2 = true; 3886 break; 3887 case IP_VERSION(11, 0, 13): 3888 if (smu->smc_fw_version >= 0x491100) 3889 use_metrics_v2 = true; 3890 break; 3891 default: 3892 break; 3893 } 3894 3895 ret = smu_cmn_get_metrics_table(smu, 3896 &metrics_external, 3897 true); 3898 if (ret) 3899 return ret; 3900 3901 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 3902 3903 gpu_metrics->temperature_edge = use_metrics_v3 ? metrics_v3->TemperatureEdge : 3904 use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge; 3905 gpu_metrics->temperature_hotspot = use_metrics_v3 ? metrics_v3->TemperatureHotspot : 3906 use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot; 3907 gpu_metrics->temperature_mem = use_metrics_v3 ? metrics_v3->TemperatureMem : 3908 use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem; 3909 gpu_metrics->temperature_vrgfx = use_metrics_v3 ? metrics_v3->TemperatureVrGfx : 3910 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx; 3911 gpu_metrics->temperature_vrsoc = use_metrics_v3 ? metrics_v3->TemperatureVrSoc : 3912 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc; 3913 gpu_metrics->temperature_vrmem = use_metrics_v3 ? metrics_v3->TemperatureVrMem0 : 3914 use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0; 3915 3916 gpu_metrics->average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity : 3917 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity; 3918 gpu_metrics->average_umc_activity = use_metrics_v3 ? metrics_v3->AverageUclkActivity : 3919 use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity; 3920 gpu_metrics->average_mm_activity = use_metrics_v3 ? 3921 (metrics_v3->VcnUsagePercentage0 + metrics_v3->VcnUsagePercentage1) / 2 : 3922 use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage; 3923 3924 gpu_metrics->average_socket_power = use_metrics_v3 ? metrics_v3->AverageSocketPower : 3925 use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower; 3926 gpu_metrics->energy_accumulator = use_metrics_v3 ? metrics_v3->EnergyAccumulator : 3927 use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator; 3928 3929 if (metrics->CurrGfxVoltageOffset) 3930 gpu_metrics->voltage_gfx = 3931 (155000 - 625 * metrics->CurrGfxVoltageOffset) / 100; 3932 if (metrics->CurrMemVidOffset) 3933 gpu_metrics->voltage_mem = 3934 (155000 - 625 * metrics->CurrMemVidOffset) / 100; 3935 if (metrics->CurrSocVoltageOffset) 3936 gpu_metrics->voltage_soc = 3937 (155000 - 625 * metrics->CurrSocVoltageOffset) / 100; 3938 3939 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity : 3940 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity; 3941 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD) 3942 gpu_metrics->average_gfxclk_frequency = 3943 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs : 3944 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs : 3945 metrics->AverageGfxclkFrequencyPostDs; 3946 else 3947 gpu_metrics->average_gfxclk_frequency = 3948 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs : 3949 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs : 3950 metrics->AverageGfxclkFrequencyPreDs; 3951 3952 gpu_metrics->average_uclk_frequency = 3953 use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs : 3954 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs : 3955 metrics->AverageUclkFrequencyPostDs; 3956 gpu_metrics->average_vclk0_frequency = use_metrics_v3 ? metrics_v3->AverageVclk0Frequency : 3957 use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency; 3958 gpu_metrics->average_dclk0_frequency = use_metrics_v3 ? metrics_v3->AverageDclk0Frequency : 3959 use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency; 3960 gpu_metrics->average_vclk1_frequency = use_metrics_v3 ? metrics_v3->AverageVclk1Frequency : 3961 use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency; 3962 gpu_metrics->average_dclk1_frequency = use_metrics_v3 ? metrics_v3->AverageDclk1Frequency : 3963 use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency; 3964 3965 gpu_metrics->current_gfxclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] : 3966 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK]; 3967 gpu_metrics->current_socclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] : 3968 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK]; 3969 gpu_metrics->current_uclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] : 3970 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK]; 3971 gpu_metrics->current_vclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] : 3972 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0]; 3973 gpu_metrics->current_dclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] : 3974 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0]; 3975 gpu_metrics->current_vclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] : 3976 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1]; 3977 gpu_metrics->current_dclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] : 3978 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1]; 3979 3980 gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu); 3981 gpu_metrics->indep_throttle_status = 3982 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status, 3983 sienna_cichlid_throttler_map); 3984 3985 gpu_metrics->current_fan_speed = use_metrics_v3 ? metrics_v3->CurrFanSpeed : 3986 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed; 3987 3988 if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) || 3989 ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) { 3990 gpu_metrics->pcie_link_width = use_metrics_v3 ? metrics_v3->PcieWidth : 3991 use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth; 3992 gpu_metrics->pcie_link_speed = link_speed[use_metrics_v3 ? metrics_v3->PcieRate : 3993 use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate]; 3994 } else { 3995 gpu_metrics->pcie_link_width = 3996 smu_v11_0_get_current_pcie_link_width(smu); 3997 gpu_metrics->pcie_link_speed = 3998 smu_v11_0_get_current_pcie_link_speed(smu); 3999 } 4000 4001 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 4002 4003 *table = (void *)gpu_metrics; 4004 4005 return sizeof(struct gpu_metrics_v1_3); 4006 } 4007 4008 static int sienna_cichlid_check_ecc_table_support(struct smu_context *smu) 4009 { 4010 uint32_t if_version = 0xff, smu_version = 0xff; 4011 int ret = 0; 4012 4013 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 4014 if (ret) 4015 return -EOPNOTSUPP; 4016 4017 if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION) 4018 ret = -EOPNOTSUPP; 4019 4020 return ret; 4021 } 4022 4023 static ssize_t sienna_cichlid_get_ecc_info(struct smu_context *smu, 4024 void *table) 4025 { 4026 struct smu_table_context *smu_table = &smu->smu_table; 4027 EccInfoTable_t *ecc_table = NULL; 4028 struct ecc_info_per_ch *ecc_info_per_channel = NULL; 4029 int i, ret = 0; 4030 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table; 4031 4032 ret = sienna_cichlid_check_ecc_table_support(smu); 4033 if (ret) 4034 return ret; 4035 4036 ret = smu_cmn_update_table(smu, 4037 SMU_TABLE_ECCINFO, 4038 0, 4039 smu_table->ecc_table, 4040 false); 4041 if (ret) { 4042 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n"); 4043 return ret; 4044 } 4045 4046 ecc_table = (EccInfoTable_t *)smu_table->ecc_table; 4047 4048 for (i = 0; i < SIENNA_CICHLID_UMC_CHANNEL_NUM; i++) { 4049 ecc_info_per_channel = &(eccinfo->ecc[i]); 4050 ecc_info_per_channel->ce_count_lo_chip = 4051 ecc_table->EccInfo[i].ce_count_lo_chip; 4052 ecc_info_per_channel->ce_count_hi_chip = 4053 ecc_table->EccInfo[i].ce_count_hi_chip; 4054 ecc_info_per_channel->mca_umc_status = 4055 ecc_table->EccInfo[i].mca_umc_status; 4056 ecc_info_per_channel->mca_umc_addr = 4057 ecc_table->EccInfo[i].mca_umc_addr; 4058 } 4059 4060 return ret; 4061 } 4062 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu) 4063 { 4064 uint16_t *mgpu_fan_boost_limit_rpm; 4065 4066 GET_PPTABLE_MEMBER(MGpuFanBoostLimitRpm, &mgpu_fan_boost_limit_rpm); 4067 /* 4068 * Skip the MGpuFanBoost setting for those ASICs 4069 * which do not support it 4070 */ 4071 if (*mgpu_fan_boost_limit_rpm == 0) 4072 return 0; 4073 4074 return smu_cmn_send_smc_msg_with_param(smu, 4075 SMU_MSG_SetMGpuFanBoostLimitRpm, 4076 0, 4077 NULL); 4078 } 4079 4080 static int sienna_cichlid_gpo_control(struct smu_context *smu, 4081 bool enablement) 4082 { 4083 uint32_t smu_version; 4084 int ret = 0; 4085 4086 4087 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) { 4088 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 4089 if (ret) 4090 return ret; 4091 4092 if (enablement) { 4093 if (smu_version < 0x003a2500) { 4094 ret = smu_cmn_send_smc_msg_with_param(smu, 4095 SMU_MSG_SetGpoFeaturePMask, 4096 GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK, 4097 NULL); 4098 } else { 4099 ret = smu_cmn_send_smc_msg_with_param(smu, 4100 SMU_MSG_DisallowGpo, 4101 0, 4102 NULL); 4103 } 4104 } else { 4105 if (smu_version < 0x003a2500) { 4106 ret = smu_cmn_send_smc_msg_with_param(smu, 4107 SMU_MSG_SetGpoFeaturePMask, 4108 0, 4109 NULL); 4110 } else { 4111 ret = smu_cmn_send_smc_msg_with_param(smu, 4112 SMU_MSG_DisallowGpo, 4113 1, 4114 NULL); 4115 } 4116 } 4117 } 4118 4119 return ret; 4120 } 4121 4122 static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu) 4123 { 4124 uint32_t smu_version; 4125 int ret = 0; 4126 4127 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 4128 if (ret) 4129 return ret; 4130 4131 /* 4132 * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45 4133 * onwards PMFWs. 4134 */ 4135 if (smu_version < 0x003A2D00) 4136 return 0; 4137 4138 return smu_cmn_send_smc_msg_with_param(smu, 4139 SMU_MSG_Enable2ndUSB20Port, 4140 smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ? 4141 1 : 0, 4142 NULL); 4143 } 4144 4145 static int sienna_cichlid_system_features_control(struct smu_context *smu, 4146 bool en) 4147 { 4148 int ret = 0; 4149 4150 if (en) { 4151 ret = sienna_cichlid_notify_2nd_usb20_port(smu); 4152 if (ret) 4153 return ret; 4154 } 4155 4156 return smu_v11_0_system_features_control(smu, en); 4157 } 4158 4159 static int sienna_cichlid_set_mp1_state(struct smu_context *smu, 4160 enum pp_mp1_state mp1_state) 4161 { 4162 int ret; 4163 4164 switch (mp1_state) { 4165 case PP_MP1_STATE_UNLOAD: 4166 ret = smu_cmn_set_mp1_state(smu, mp1_state); 4167 break; 4168 default: 4169 /* Ignore others */ 4170 ret = 0; 4171 } 4172 4173 return ret; 4174 } 4175 4176 static void sienna_cichlid_stb_init(struct smu_context *smu) 4177 { 4178 struct amdgpu_device *adev = smu->adev; 4179 uint32_t reg; 4180 4181 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_START); 4182 smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE); 4183 4184 /* STB is disabled */ 4185 if (!smu->stb_context.enabled) 4186 return; 4187 4188 spin_lock_init(&smu->stb_context.lock); 4189 4190 /* STB buffer size in bytes as function of FIFO depth */ 4191 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_FIFO); 4192 smu->stb_context.stb_buf_size = 1 << REG_GET_FIELD(reg, MP1_PMI_3_FIFO, DEPTH); 4193 smu->stb_context.stb_buf_size *= SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES; 4194 4195 dev_info(smu->adev->dev, "STB initialized to %d entries", 4196 smu->stb_context.stb_buf_size / SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES); 4197 4198 } 4199 4200 static int sienna_cichlid_get_default_config_table_settings(struct smu_context *smu, 4201 struct config_table_setting *table) 4202 { 4203 struct amdgpu_device *adev = smu->adev; 4204 4205 if (!table) 4206 return -EINVAL; 4207 4208 table->gfxclk_average_tau = 10; 4209 table->socclk_average_tau = 10; 4210 table->fclk_average_tau = 10; 4211 table->uclk_average_tau = 10; 4212 table->gfx_activity_average_tau = 10; 4213 table->mem_activity_average_tau = 10; 4214 table->socket_power_average_tau = 100; 4215 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) 4216 table->apu_socket_power_average_tau = 100; 4217 4218 return 0; 4219 } 4220 4221 static int sienna_cichlid_set_config_table(struct smu_context *smu, 4222 struct config_table_setting *table) 4223 { 4224 DriverSmuConfigExternal_t driver_smu_config_table; 4225 4226 if (!table) 4227 return -EINVAL; 4228 4229 memset(&driver_smu_config_table, 4230 0, 4231 sizeof(driver_smu_config_table)); 4232 driver_smu_config_table.DriverSmuConfig.GfxclkAverageLpfTau = 4233 table->gfxclk_average_tau; 4234 driver_smu_config_table.DriverSmuConfig.FclkAverageLpfTau = 4235 table->fclk_average_tau; 4236 driver_smu_config_table.DriverSmuConfig.UclkAverageLpfTau = 4237 table->uclk_average_tau; 4238 driver_smu_config_table.DriverSmuConfig.GfxActivityLpfTau = 4239 table->gfx_activity_average_tau; 4240 driver_smu_config_table.DriverSmuConfig.UclkActivityLpfTau = 4241 table->mem_activity_average_tau; 4242 driver_smu_config_table.DriverSmuConfig.SocketPowerLpfTau = 4243 table->socket_power_average_tau; 4244 4245 return smu_cmn_update_table(smu, 4246 SMU_TABLE_DRIVER_SMU_CONFIG, 4247 0, 4248 (void *)&driver_smu_config_table, 4249 true); 4250 } 4251 4252 static int sienna_cichlid_stb_get_data_direct(struct smu_context *smu, 4253 void *buf, 4254 uint32_t size) 4255 { 4256 uint32_t *p = buf; 4257 struct amdgpu_device *adev = smu->adev; 4258 4259 /* No need to disable interrupts for now as we don't lock it yet from ISR */ 4260 spin_lock(&smu->stb_context.lock); 4261 4262 /* 4263 * Read the STB FIFO in units of 32bit since this is the accessor window 4264 * (register width) we have. 4265 */ 4266 buf = ((char *) buf) + size; 4267 while ((void *)p < buf) 4268 *p++ = cpu_to_le32(RREG32_PCIE(MP1_Public | smnMP1_PMI_3)); 4269 4270 spin_unlock(&smu->stb_context.lock); 4271 4272 return 0; 4273 } 4274 4275 static bool sienna_cichlid_is_mode2_reset_supported(struct smu_context *smu) 4276 { 4277 return true; 4278 } 4279 4280 static int sienna_cichlid_mode2_reset(struct smu_context *smu) 4281 { 4282 u32 smu_version; 4283 int ret = 0, index; 4284 struct amdgpu_device *adev = smu->adev; 4285 int timeout = 100; 4286 4287 smu_cmn_get_smc_version(smu, NULL, &smu_version); 4288 4289 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 4290 SMU_MSG_DriverMode2Reset); 4291 4292 mutex_lock(&smu->message_lock); 4293 4294 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, 4295 SMU_RESET_MODE_2); 4296 4297 ret = smu_cmn_wait_for_response(smu); 4298 while (ret != 0 && timeout) { 4299 ret = smu_cmn_wait_for_response(smu); 4300 /* Wait a bit more time for getting ACK */ 4301 if (ret != 0) { 4302 --timeout; 4303 usleep_range(500, 1000); 4304 continue; 4305 } else { 4306 break; 4307 } 4308 } 4309 4310 if (!timeout) { 4311 dev_err(adev->dev, 4312 "failed to send mode2 message \tparam: 0x%08x response %#x\n", 4313 SMU_RESET_MODE_2, ret); 4314 goto out; 4315 } 4316 4317 dev_info(smu->adev->dev, "restore config space...\n"); 4318 /* Restore the config space saved during init */ 4319 amdgpu_device_load_pci_state(adev->pdev); 4320 out: 4321 mutex_unlock(&smu->message_lock); 4322 4323 return ret; 4324 } 4325 4326 static const struct pptable_funcs sienna_cichlid_ppt_funcs = { 4327 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask, 4328 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table, 4329 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable, 4330 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable, 4331 .i2c_init = sienna_cichlid_i2c_control_init, 4332 .i2c_fini = sienna_cichlid_i2c_control_fini, 4333 .print_clk_levels = sienna_cichlid_print_clk_levels, 4334 .force_clk_levels = sienna_cichlid_force_clk_levels, 4335 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk, 4336 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed, 4337 .display_config_changed = sienna_cichlid_display_config_changed, 4338 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config, 4339 .is_dpm_running = sienna_cichlid_is_dpm_running, 4340 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm, 4341 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm, 4342 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode, 4343 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode, 4344 .set_watermarks_table = sienna_cichlid_set_watermarks_table, 4345 .read_sensor = sienna_cichlid_read_sensor, 4346 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states, 4347 .set_performance_level = smu_v11_0_set_performance_level, 4348 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range, 4349 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch, 4350 .get_power_limit = sienna_cichlid_get_power_limit, 4351 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters, 4352 .dump_pptable = sienna_cichlid_dump_pptable, 4353 .init_microcode = smu_v11_0_init_microcode, 4354 .load_microcode = smu_v11_0_load_microcode, 4355 .fini_microcode = smu_v11_0_fini_microcode, 4356 .init_smc_tables = sienna_cichlid_init_smc_tables, 4357 .fini_smc_tables = smu_v11_0_fini_smc_tables, 4358 .init_power = smu_v11_0_init_power, 4359 .fini_power = smu_v11_0_fini_power, 4360 .check_fw_status = smu_v11_0_check_fw_status, 4361 .setup_pptable = sienna_cichlid_setup_pptable, 4362 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, 4363 .check_fw_version = smu_v11_0_check_fw_version, 4364 .write_pptable = smu_cmn_write_pptable, 4365 .set_driver_table_location = smu_v11_0_set_driver_table_location, 4366 .set_tool_table_location = smu_v11_0_set_tool_table_location, 4367 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 4368 .system_features_control = sienna_cichlid_system_features_control, 4369 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 4370 .send_smc_msg = smu_cmn_send_smc_msg, 4371 .init_display_count = NULL, 4372 .set_allowed_mask = smu_v11_0_set_allowed_mask, 4373 .get_enabled_mask = smu_cmn_get_enabled_mask, 4374 .feature_is_enabled = smu_cmn_feature_is_enabled, 4375 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 4376 .notify_display_change = NULL, 4377 .set_power_limit = smu_v11_0_set_power_limit, 4378 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks, 4379 .enable_thermal_alert = smu_v11_0_enable_thermal_alert, 4380 .disable_thermal_alert = smu_v11_0_disable_thermal_alert, 4381 .set_min_dcef_deep_sleep = NULL, 4382 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request, 4383 .get_fan_control_mode = smu_v11_0_get_fan_control_mode, 4384 .set_fan_control_mode = smu_v11_0_set_fan_control_mode, 4385 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm, 4386 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm, 4387 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate, 4388 .gfx_off_control = smu_v11_0_gfx_off_control, 4389 .register_irq_handler = smu_v11_0_register_irq_handler, 4390 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme, 4391 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc, 4392 .baco_is_support = smu_v11_0_baco_is_support, 4393 .baco_get_state = smu_v11_0_baco_get_state, 4394 .baco_set_state = smu_v11_0_baco_set_state, 4395 .baco_enter = sienna_cichlid_baco_enter, 4396 .baco_exit = sienna_cichlid_baco_exit, 4397 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported, 4398 .mode1_reset = smu_v11_0_mode1_reset, 4399 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq, 4400 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, 4401 .set_default_od_settings = sienna_cichlid_set_default_od_settings, 4402 .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table, 4403 .restore_user_od_settings = smu_v11_0_restore_user_od_settings, 4404 .run_btc = sienna_cichlid_run_btc, 4405 .set_power_source = smu_v11_0_set_power_source, 4406 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 4407 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 4408 .get_gpu_metrics = sienna_cichlid_get_gpu_metrics, 4409 .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost, 4410 .gfx_ulv_control = smu_v11_0_gfx_ulv_control, 4411 .deep_sleep_control = smu_v11_0_deep_sleep_control, 4412 .get_fan_parameters = sienna_cichlid_get_fan_parameters, 4413 .interrupt_work = smu_v11_0_interrupt_work, 4414 .gpo_control = sienna_cichlid_gpo_control, 4415 .set_mp1_state = sienna_cichlid_set_mp1_state, 4416 .stb_collect_info = sienna_cichlid_stb_get_data_direct, 4417 .get_ecc_info = sienna_cichlid_get_ecc_info, 4418 .get_default_config_table_settings = sienna_cichlid_get_default_config_table_settings, 4419 .set_config_table = sienna_cichlid_set_config_table, 4420 .get_unique_id = sienna_cichlid_get_unique_id, 4421 .mode2_reset_is_support = sienna_cichlid_is_mode2_reset_supported, 4422 .mode2_reset = sienna_cichlid_mode2_reset, 4423 }; 4424 4425 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu) 4426 { 4427 smu->ppt_funcs = &sienna_cichlid_ppt_funcs; 4428 smu->message_map = sienna_cichlid_message_map; 4429 smu->clock_map = sienna_cichlid_clk_map; 4430 smu->feature_map = sienna_cichlid_feature_mask_map; 4431 smu->table_map = sienna_cichlid_table_map; 4432 smu->pwr_src_map = sienna_cichlid_pwr_src_map; 4433 smu->workload_map = sienna_cichlid_workload_map; 4434 smu_v11_0_set_smu_mailbox_registers(smu); 4435 } 4436