1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include <linux/pci.h> 28 #include <linux/i2c.h> 29 #include "amdgpu.h" 30 #include "amdgpu_dpm.h" 31 #include "amdgpu_smu.h" 32 #include "atomfirmware.h" 33 #include "amdgpu_atomfirmware.h" 34 #include "amdgpu_atombios.h" 35 #include "smu_v11_0.h" 36 #include "smu11_driver_if_sienna_cichlid.h" 37 #include "soc15_common.h" 38 #include "atom.h" 39 #include "sienna_cichlid_ppt.h" 40 #include "smu_v11_0_7_pptable.h" 41 #include "smu_v11_0_7_ppsmc.h" 42 #include "nbio/nbio_2_3_offset.h" 43 #include "nbio/nbio_2_3_sh_mask.h" 44 #include "thm/thm_11_0_2_offset.h" 45 #include "thm/thm_11_0_2_sh_mask.h" 46 #include "mp/mp_11_0_offset.h" 47 #include "mp/mp_11_0_sh_mask.h" 48 49 #include "asic_reg/mp/mp_11_0_sh_mask.h" 50 #include "amdgpu_ras.h" 51 #include "smu_cmn.h" 52 53 /* 54 * DO NOT use these for err/warn/info/debug messages. 55 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 56 * They are more MGPU friendly. 57 */ 58 #undef pr_err 59 #undef pr_warn 60 #undef pr_info 61 #undef pr_debug 62 63 #define FEATURE_MASK(feature) (1ULL << feature) 64 #define SMC_DPM_FEATURE ( \ 65 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \ 66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \ 72 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)) 73 74 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15 75 76 #define GET_PPTABLE_MEMBER(field, member) do {\ 77 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))\ 78 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\ 79 else\ 80 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\ 81 } while(0) 82 83 /* STB FIFO depth is in 64bit units */ 84 #define SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES 8 85 86 /* 87 * SMU support ECCTABLE since version 58.70.0, 88 * use this to check whether ECCTABLE feature is supported. 89 */ 90 #define SUPPORT_ECCTABLE_SMU_VERSION 0x003a4600 91 92 static int get_table_size(struct smu_context *smu) 93 { 94 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) 95 return sizeof(PPTable_beige_goby_t); 96 else 97 return sizeof(PPTable_t); 98 } 99 100 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = { 101 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 102 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 103 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 104 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0), 105 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), 106 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 107 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 108 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1), 109 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1), 110 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1), 111 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1), 112 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1), 113 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1), 114 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 115 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 116 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 117 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 118 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 119 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 120 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 121 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 122 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 123 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 124 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), 125 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1), 126 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), 127 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1), 128 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 129 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), 130 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), 131 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 132 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0), 133 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0), 134 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0), 135 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0), 136 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0), 137 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0), 138 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0), 139 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0), 140 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1), 141 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 142 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 143 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 144 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1), 145 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0), 146 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 147 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 148 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 149 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 150 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0), 151 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0), 152 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0), 153 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0), 154 MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0), 155 MSG_MAP(DisallowGpo, PPSMC_MSG_DisallowGpo, 0), 156 MSG_MAP(Enable2ndUSB20Port, PPSMC_MSG_Enable2ndUSB20Port, 0), 157 MSG_MAP(DriverMode2Reset, PPSMC_MSG_DriverMode2Reset, 0), 158 }; 159 160 static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = { 161 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 162 CLK_MAP(SCLK, PPCLK_GFXCLK), 163 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 164 CLK_MAP(FCLK, PPCLK_FCLK), 165 CLK_MAP(UCLK, PPCLK_UCLK), 166 CLK_MAP(MCLK, PPCLK_UCLK), 167 CLK_MAP(DCLK, PPCLK_DCLK_0), 168 CLK_MAP(DCLK1, PPCLK_DCLK_1), 169 CLK_MAP(VCLK, PPCLK_VCLK_0), 170 CLK_MAP(VCLK1, PPCLK_VCLK_1), 171 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK), 172 CLK_MAP(DISPCLK, PPCLK_DISPCLK), 173 CLK_MAP(PIXCLK, PPCLK_PIXCLK), 174 CLK_MAP(PHYCLK, PPCLK_PHYCLK), 175 }; 176 177 static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = { 178 FEA_MAP(DPM_PREFETCHER), 179 FEA_MAP(DPM_GFXCLK), 180 FEA_MAP(DPM_GFX_GPO), 181 FEA_MAP(DPM_UCLK), 182 FEA_MAP(DPM_FCLK), 183 FEA_MAP(DPM_SOCCLK), 184 FEA_MAP(DPM_MP0CLK), 185 FEA_MAP(DPM_LINK), 186 FEA_MAP(DPM_DCEFCLK), 187 FEA_MAP(DPM_XGMI), 188 FEA_MAP(MEM_VDDCI_SCALING), 189 FEA_MAP(MEM_MVDD_SCALING), 190 FEA_MAP(DS_GFXCLK), 191 FEA_MAP(DS_SOCCLK), 192 FEA_MAP(DS_FCLK), 193 FEA_MAP(DS_LCLK), 194 FEA_MAP(DS_DCEFCLK), 195 FEA_MAP(DS_UCLK), 196 FEA_MAP(GFX_ULV), 197 FEA_MAP(FW_DSTATE), 198 FEA_MAP(GFXOFF), 199 FEA_MAP(BACO), 200 FEA_MAP(MM_DPM_PG), 201 FEA_MAP(RSMU_SMN_CG), 202 FEA_MAP(PPT), 203 FEA_MAP(TDC), 204 FEA_MAP(APCC_PLUS), 205 FEA_MAP(GTHR), 206 FEA_MAP(ACDC), 207 FEA_MAP(VR0HOT), 208 FEA_MAP(VR1HOT), 209 FEA_MAP(FW_CTF), 210 FEA_MAP(FAN_CONTROL), 211 FEA_MAP(THERMAL), 212 FEA_MAP(GFX_DCS), 213 FEA_MAP(RM), 214 FEA_MAP(LED_DISPLAY), 215 FEA_MAP(GFX_SS), 216 FEA_MAP(OUT_OF_BAND_MONITOR), 217 FEA_MAP(TEMP_DEPENDENT_VMIN), 218 FEA_MAP(MMHUB_PG), 219 FEA_MAP(ATHUB_PG), 220 FEA_MAP(APCC_DFLL), 221 }; 222 223 static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = { 224 TAB_MAP(PPTABLE), 225 TAB_MAP(WATERMARKS), 226 TAB_MAP(AVFS_PSM_DEBUG), 227 TAB_MAP(AVFS_FUSE_OVERRIDE), 228 TAB_MAP(PMSTATUSLOG), 229 TAB_MAP(SMU_METRICS), 230 TAB_MAP(DRIVER_SMU_CONFIG), 231 TAB_MAP(ACTIVITY_MONITOR_COEFF), 232 TAB_MAP(OVERDRIVE), 233 TAB_MAP(I2C_COMMANDS), 234 TAB_MAP(PACE), 235 TAB_MAP(ECCINFO), 236 }; 237 238 static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { 239 PWR_MAP(AC), 240 PWR_MAP(DC), 241 }; 242 243 static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 244 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), 245 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 246 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 247 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 248 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 249 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 250 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 251 }; 252 253 static const uint8_t sienna_cichlid_throttler_map[] = { 254 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT), 255 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT), 256 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 257 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 258 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 259 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT), 260 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 261 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT), 262 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT), 263 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 264 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 265 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 266 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 267 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT), 268 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT), 269 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), 270 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT), 271 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT), 272 }; 273 274 static int 275 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, 276 uint32_t *feature_mask, uint32_t num) 277 { 278 struct amdgpu_device *adev = smu->adev; 279 280 if (num > 2) 281 return -EINVAL; 282 283 memset(feature_mask, 0, sizeof(uint32_t) * num); 284 285 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) 286 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT) 287 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) 288 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) 289 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) 290 | FEATURE_MASK(FEATURE_DS_FCLK_BIT) 291 | FEATURE_MASK(FEATURE_DS_UCLK_BIT) 292 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) 293 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT) 294 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) 295 | FEATURE_MASK(FEATURE_GFX_SS_BIT) 296 | FEATURE_MASK(FEATURE_VR0HOT_BIT) 297 | FEATURE_MASK(FEATURE_PPT_BIT) 298 | FEATURE_MASK(FEATURE_TDC_BIT) 299 | FEATURE_MASK(FEATURE_BACO_BIT) 300 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) 301 | FEATURE_MASK(FEATURE_FW_CTF_BIT) 302 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) 303 | FEATURE_MASK(FEATURE_THERMAL_BIT) 304 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT); 305 306 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { 307 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 308 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT); 309 } 310 311 if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) && 312 (adev->ip_versions[MP1_HWIP][0] > IP_VERSION(11, 0, 7)) && 313 !(adev->flags & AMD_IS_APU)) 314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT); 315 316 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) 317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) 318 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) 319 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); 320 321 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) 322 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); 323 324 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) 325 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); 326 327 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) 328 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 329 330 if (adev->pm.pp_feature & PP_ULV_MASK) 331 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); 332 333 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) 334 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 335 336 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 337 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); 338 339 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB) 340 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT); 341 342 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) 343 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); 344 345 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN || 346 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG) 347 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT); 348 349 if (smu->dc_controlled_by_gpio) 350 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT); 351 352 if (amdgpu_device_should_use_aspm(adev)) 353 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT); 354 355 return 0; 356 } 357 358 static void sienna_cichlid_check_bxco_support(struct smu_context *smu) 359 { 360 struct smu_table_context *table_context = &smu->smu_table; 361 struct smu_11_0_7_powerplay_table *powerplay_table = 362 table_context->power_play_table; 363 struct smu_baco_context *smu_baco = &smu->smu_baco; 364 struct amdgpu_device *adev = smu->adev; 365 uint32_t val; 366 367 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) { 368 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); 369 smu_baco->platform_support = 370 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : 371 false; 372 373 /* 374 * Disable BACO entry/exit completely on below SKUs to 375 * avoid hardware intermittent failures. 376 */ 377 if (((adev->pdev->device == 0x73A1) && 378 (adev->pdev->revision == 0x00)) || 379 ((adev->pdev->device == 0x73BF) && 380 (adev->pdev->revision == 0xCF)) || 381 ((adev->pdev->device == 0x7422) && 382 (adev->pdev->revision == 0x00))) 383 smu_baco->platform_support = false; 384 385 } 386 } 387 388 static void sienna_cichlid_check_fan_support(struct smu_context *smu) 389 { 390 struct smu_table_context *table_context = &smu->smu_table; 391 PPTable_t *pptable = table_context->driver_pptable; 392 uint64_t features = *(uint64_t *) pptable->FeaturesToRun; 393 394 /* Fan control is not possible if PPTable has it disabled */ 395 smu->adev->pm.no_fan = 396 !(features & (1ULL << FEATURE_FAN_CONTROL_BIT)); 397 if (smu->adev->pm.no_fan) 398 dev_info_once(smu->adev->dev, 399 "PMFW based fan control disabled"); 400 } 401 402 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu) 403 { 404 struct smu_table_context *table_context = &smu->smu_table; 405 struct smu_11_0_7_powerplay_table *powerplay_table = 406 table_context->power_play_table; 407 408 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC) 409 smu->dc_controlled_by_gpio = true; 410 411 sienna_cichlid_check_bxco_support(smu); 412 sienna_cichlid_check_fan_support(smu); 413 414 table_context->thermal_controller_type = 415 powerplay_table->thermal_controller_type; 416 417 /* 418 * Instead of having its own buffer space and get overdrive_table copied, 419 * smu->od_settings just points to the actual overdrive_table 420 */ 421 smu->od_settings = &powerplay_table->overdrive_table; 422 423 return 0; 424 } 425 426 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu) 427 { 428 struct atom_smc_dpm_info_v4_9 *smc_dpm_table; 429 int index, ret; 430 I2cControllerConfig_t *table_member; 431 432 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 433 smc_dpm_info); 434 435 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 436 (uint8_t **)&smc_dpm_table); 437 if (ret) 438 return ret; 439 GET_PPTABLE_MEMBER(I2cControllers, &table_member); 440 memcpy(table_member, smc_dpm_table->I2cControllers, 441 sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header)); 442 443 return 0; 444 } 445 446 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu) 447 { 448 struct smu_table_context *table_context = &smu->smu_table; 449 struct smu_11_0_7_powerplay_table *powerplay_table = 450 table_context->power_play_table; 451 int table_size; 452 453 table_size = get_table_size(smu); 454 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 455 table_size); 456 457 return 0; 458 } 459 460 static int sienna_cichlid_patch_pptable_quirk(struct smu_context *smu) 461 { 462 struct amdgpu_device *adev = smu->adev; 463 uint32_t *board_reserved; 464 uint16_t *freq_table_gfx; 465 uint32_t i; 466 467 /* Fix some OEM SKU specific stability issues */ 468 GET_PPTABLE_MEMBER(BoardReserved, &board_reserved); 469 if ((adev->pdev->device == 0x73DF) && 470 (adev->pdev->revision == 0XC3) && 471 (adev->pdev->subsystem_device == 0x16C2) && 472 (adev->pdev->subsystem_vendor == 0x1043)) 473 board_reserved[0] = 1387; 474 475 GET_PPTABLE_MEMBER(FreqTableGfx, &freq_table_gfx); 476 if ((adev->pdev->device == 0x73DF) && 477 (adev->pdev->revision == 0XC3) && 478 ((adev->pdev->subsystem_device == 0x16C2) || 479 (adev->pdev->subsystem_device == 0x133C)) && 480 (adev->pdev->subsystem_vendor == 0x1043)) { 481 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) { 482 if (freq_table_gfx[i] > 2500) 483 freq_table_gfx[i] = 2500; 484 } 485 } 486 487 return 0; 488 } 489 490 static int sienna_cichlid_setup_pptable(struct smu_context *smu) 491 { 492 int ret = 0; 493 494 ret = smu_v11_0_setup_pptable(smu); 495 if (ret) 496 return ret; 497 498 ret = sienna_cichlid_store_powerplay_table(smu); 499 if (ret) 500 return ret; 501 502 ret = sienna_cichlid_append_powerplay_table(smu); 503 if (ret) 504 return ret; 505 506 ret = sienna_cichlid_check_powerplay_table(smu); 507 if (ret) 508 return ret; 509 510 return sienna_cichlid_patch_pptable_quirk(smu); 511 } 512 513 static int sienna_cichlid_tables_init(struct smu_context *smu) 514 { 515 struct smu_table_context *smu_table = &smu->smu_table; 516 struct smu_table *tables = smu_table->tables; 517 int table_size; 518 519 table_size = get_table_size(smu); 520 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size, 521 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 522 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 523 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 524 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t), 525 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 526 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 527 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 528 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t), 529 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 530 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 531 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 532 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, 533 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE, 534 AMDGPU_GEM_DOMAIN_VRAM); 535 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t), 536 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 537 SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfigExternal_t), 538 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 539 540 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL); 541 if (!smu_table->metrics_table) 542 goto err0_out; 543 smu_table->metrics_time = 0; 544 545 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 546 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 547 if (!smu_table->gpu_metrics_table) 548 goto err1_out; 549 550 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 551 if (!smu_table->watermarks_table) 552 goto err2_out; 553 554 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL); 555 if (!smu_table->ecc_table) 556 goto err3_out; 557 558 smu_table->driver_smu_config_table = 559 kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL); 560 if (!smu_table->driver_smu_config_table) 561 goto err4_out; 562 563 return 0; 564 565 err4_out: 566 kfree(smu_table->ecc_table); 567 err3_out: 568 kfree(smu_table->watermarks_table); 569 err2_out: 570 kfree(smu_table->gpu_metrics_table); 571 err1_out: 572 kfree(smu_table->metrics_table); 573 err0_out: 574 return -ENOMEM; 575 } 576 577 static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu) 578 { 579 struct smu_table_context *smu_table= &smu->smu_table; 580 SmuMetricsExternal_t *metrics_ext = 581 (SmuMetricsExternal_t *)(smu_table->metrics_table); 582 uint32_t throttler_status = 0; 583 int i; 584 585 if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 586 (smu->smc_fw_version >= 0x3A4900)) { 587 for (i = 0; i < THROTTLER_COUNT; i++) 588 throttler_status |= 589 (metrics_ext->SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0); 590 } else if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 591 (smu->smc_fw_version >= 0x3A4300)) { 592 for (i = 0; i < THROTTLER_COUNT; i++) 593 throttler_status |= 594 (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0); 595 } else { 596 throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus; 597 } 598 599 return throttler_status; 600 } 601 602 static int sienna_cichlid_get_power_limit(struct smu_context *smu, 603 uint32_t *current_power_limit, 604 uint32_t *default_power_limit, 605 uint32_t *max_power_limit) 606 { 607 struct smu_11_0_7_powerplay_table *powerplay_table = 608 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table; 609 uint32_t power_limit, od_percent; 610 uint16_t *table_member; 611 612 GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member); 613 614 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) { 615 power_limit = 616 table_member[PPT_THROTTLER_PPT0]; 617 } 618 619 if (current_power_limit) 620 *current_power_limit = power_limit; 621 if (default_power_limit) 622 *default_power_limit = power_limit; 623 624 if (max_power_limit) { 625 if (smu->od_enabled) { 626 od_percent = 627 le32_to_cpu(powerplay_table->overdrive_table.max[ 628 SMU_11_0_7_ODSETTING_POWERPERCENTAGE]); 629 630 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", 631 od_percent, power_limit); 632 633 power_limit *= (100 + od_percent); 634 power_limit /= 100; 635 } 636 *max_power_limit = power_limit; 637 } 638 639 return 0; 640 } 641 642 static void sienna_cichlid_get_smartshift_power_percentage(struct smu_context *smu, 643 uint32_t *apu_percent, 644 uint32_t *dgpu_percent) 645 { 646 struct smu_table_context *smu_table = &smu->smu_table; 647 SmuMetrics_V4_t *metrics_v4 = 648 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V4); 649 uint16_t powerRatio = 0; 650 uint16_t apu_power_limit = 0; 651 uint16_t dgpu_power_limit = 0; 652 uint32_t apu_boost = 0; 653 uint32_t dgpu_boost = 0; 654 uint32_t cur_power_limit; 655 656 if (metrics_v4->ApuSTAPMSmartShiftLimit != 0) { 657 sienna_cichlid_get_power_limit(smu, &cur_power_limit, NULL, NULL); 658 apu_power_limit = metrics_v4->ApuSTAPMLimit; 659 dgpu_power_limit = cur_power_limit; 660 powerRatio = (((apu_power_limit + 661 dgpu_power_limit) * 100) / 662 metrics_v4->ApuSTAPMSmartShiftLimit); 663 if (powerRatio > 100) { 664 apu_power_limit = (apu_power_limit * 100) / 665 powerRatio; 666 dgpu_power_limit = (dgpu_power_limit * 100) / 667 powerRatio; 668 } 669 if (metrics_v4->AverageApuSocketPower > apu_power_limit && 670 apu_power_limit != 0) { 671 apu_boost = ((metrics_v4->AverageApuSocketPower - 672 apu_power_limit) * 100) / 673 apu_power_limit; 674 if (apu_boost > 100) 675 apu_boost = 100; 676 } 677 678 if (metrics_v4->AverageSocketPower > dgpu_power_limit && 679 dgpu_power_limit != 0) { 680 dgpu_boost = ((metrics_v4->AverageSocketPower - 681 dgpu_power_limit) * 100) / 682 dgpu_power_limit; 683 if (dgpu_boost > 100) 684 dgpu_boost = 100; 685 } 686 687 if (dgpu_boost >= apu_boost) 688 apu_boost = 0; 689 else 690 dgpu_boost = 0; 691 } 692 *apu_percent = apu_boost; 693 *dgpu_percent = dgpu_boost; 694 } 695 696 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu, 697 MetricsMember_t member, 698 uint32_t *value) 699 { 700 struct smu_table_context *smu_table= &smu->smu_table; 701 SmuMetrics_t *metrics = 702 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics); 703 SmuMetrics_V2_t *metrics_v2 = 704 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2); 705 SmuMetrics_V3_t *metrics_v3 = 706 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V3); 707 bool use_metrics_v2 = false; 708 bool use_metrics_v3 = false; 709 uint16_t average_gfx_activity; 710 int ret = 0; 711 uint32_t apu_percent = 0; 712 uint32_t dgpu_percent = 0; 713 714 switch (smu->adev->ip_versions[MP1_HWIP][0]) { 715 case IP_VERSION(11, 0, 7): 716 if (smu->smc_fw_version >= 0x3A4900) 717 use_metrics_v3 = true; 718 else if (smu->smc_fw_version >= 0x3A4300) 719 use_metrics_v2 = true; 720 break; 721 case IP_VERSION(11, 0, 11): 722 if (smu->smc_fw_version >= 0x412D00) 723 use_metrics_v2 = true; 724 break; 725 case IP_VERSION(11, 0, 12): 726 if (smu->smc_fw_version >= 0x3B2300) 727 use_metrics_v2 = true; 728 break; 729 case IP_VERSION(11, 0, 13): 730 if (smu->smc_fw_version >= 0x491100) 731 use_metrics_v2 = true; 732 break; 733 default: 734 break; 735 } 736 737 ret = smu_cmn_get_metrics_table(smu, 738 NULL, 739 false); 740 if (ret) 741 return ret; 742 743 switch (member) { 744 case METRICS_CURR_GFXCLK: 745 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] : 746 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : 747 metrics->CurrClock[PPCLK_GFXCLK]; 748 break; 749 case METRICS_CURR_SOCCLK: 750 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] : 751 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : 752 metrics->CurrClock[PPCLK_SOCCLK]; 753 break; 754 case METRICS_CURR_UCLK: 755 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] : 756 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : 757 metrics->CurrClock[PPCLK_UCLK]; 758 break; 759 case METRICS_CURR_VCLK: 760 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] : 761 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : 762 metrics->CurrClock[PPCLK_VCLK_0]; 763 break; 764 case METRICS_CURR_VCLK1: 765 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] : 766 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : 767 metrics->CurrClock[PPCLK_VCLK_1]; 768 break; 769 case METRICS_CURR_DCLK: 770 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] : 771 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : 772 metrics->CurrClock[PPCLK_DCLK_0]; 773 break; 774 case METRICS_CURR_DCLK1: 775 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] : 776 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : 777 metrics->CurrClock[PPCLK_DCLK_1]; 778 break; 779 case METRICS_CURR_DCEFCLK: 780 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCEFCLK] : 781 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] : 782 metrics->CurrClock[PPCLK_DCEFCLK]; 783 break; 784 case METRICS_CURR_FCLK: 785 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_FCLK] : 786 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] : 787 metrics->CurrClock[PPCLK_FCLK]; 788 break; 789 case METRICS_AVERAGE_GFXCLK: 790 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity : 791 use_metrics_v2 ? metrics_v2->AverageGfxActivity : 792 metrics->AverageGfxActivity; 793 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD) 794 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs : 795 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs : 796 metrics->AverageGfxclkFrequencyPostDs; 797 else 798 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs : 799 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs : 800 metrics->AverageGfxclkFrequencyPreDs; 801 break; 802 case METRICS_AVERAGE_FCLK: 803 *value = use_metrics_v3 ? metrics_v3->AverageFclkFrequencyPostDs : 804 use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs : 805 metrics->AverageFclkFrequencyPostDs; 806 break; 807 case METRICS_AVERAGE_UCLK: 808 *value = use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs : 809 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs : 810 metrics->AverageUclkFrequencyPostDs; 811 break; 812 case METRICS_AVERAGE_GFXACTIVITY: 813 *value = use_metrics_v3 ? metrics_v3->AverageGfxActivity : 814 use_metrics_v2 ? metrics_v2->AverageGfxActivity : 815 metrics->AverageGfxActivity; 816 break; 817 case METRICS_AVERAGE_MEMACTIVITY: 818 *value = use_metrics_v3 ? metrics_v3->AverageUclkActivity : 819 use_metrics_v2 ? metrics_v2->AverageUclkActivity : 820 metrics->AverageUclkActivity; 821 break; 822 case METRICS_AVERAGE_SOCKETPOWER: 823 *value = use_metrics_v3 ? metrics_v3->AverageSocketPower << 8 : 824 use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 : 825 metrics->AverageSocketPower << 8; 826 break; 827 case METRICS_TEMPERATURE_EDGE: 828 *value = (use_metrics_v3 ? metrics_v3->TemperatureEdge : 829 use_metrics_v2 ? metrics_v2->TemperatureEdge : 830 metrics->TemperatureEdge) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 831 break; 832 case METRICS_TEMPERATURE_HOTSPOT: 833 *value = (use_metrics_v3 ? metrics_v3->TemperatureHotspot : 834 use_metrics_v2 ? metrics_v2->TemperatureHotspot : 835 metrics->TemperatureHotspot) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 836 break; 837 case METRICS_TEMPERATURE_MEM: 838 *value = (use_metrics_v3 ? metrics_v3->TemperatureMem : 839 use_metrics_v2 ? metrics_v2->TemperatureMem : 840 metrics->TemperatureMem) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 841 break; 842 case METRICS_TEMPERATURE_VRGFX: 843 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrGfx : 844 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : 845 metrics->TemperatureVrGfx) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 846 break; 847 case METRICS_TEMPERATURE_VRSOC: 848 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrSoc : 849 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : 850 metrics->TemperatureVrSoc) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 851 break; 852 case METRICS_THROTTLER_STATUS: 853 *value = sienna_cichlid_get_throttler_status_locked(smu); 854 break; 855 case METRICS_CURR_FANSPEED: 856 *value = use_metrics_v3 ? metrics_v3->CurrFanSpeed : 857 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed; 858 break; 859 case METRICS_UNIQUE_ID_UPPER32: 860 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */ 861 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumUpper32 : 0; 862 break; 863 case METRICS_UNIQUE_ID_LOWER32: 864 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */ 865 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumLower32 : 0; 866 break; 867 case METRICS_SS_APU_SHARE: 868 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent); 869 *value = apu_percent; 870 break; 871 case METRICS_SS_DGPU_SHARE: 872 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent); 873 *value = dgpu_percent; 874 break; 875 876 default: 877 *value = UINT_MAX; 878 break; 879 } 880 881 return ret; 882 883 } 884 885 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu) 886 { 887 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 888 889 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 890 GFP_KERNEL); 891 if (!smu_dpm->dpm_context) 892 return -ENOMEM; 893 894 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 895 896 return 0; 897 } 898 899 static void sienna_cichlid_stb_init(struct smu_context *smu); 900 901 static int sienna_cichlid_init_smc_tables(struct smu_context *smu) 902 { 903 struct amdgpu_device *adev = smu->adev; 904 int ret = 0; 905 906 ret = sienna_cichlid_tables_init(smu); 907 if (ret) 908 return ret; 909 910 ret = sienna_cichlid_allocate_dpm_context(smu); 911 if (ret) 912 return ret; 913 914 if (!amdgpu_sriov_vf(adev)) 915 sienna_cichlid_stb_init(smu); 916 917 return smu_v11_0_init_smc_tables(smu); 918 } 919 920 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) 921 { 922 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 923 struct smu_11_0_dpm_table *dpm_table; 924 struct amdgpu_device *adev = smu->adev; 925 int i, ret = 0; 926 DpmDescriptor_t *table_member; 927 928 /* socclk dpm table setup */ 929 dpm_table = &dpm_context->dpm_tables.soc_table; 930 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member); 931 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 932 ret = smu_v11_0_set_single_dpm_table(smu, 933 SMU_SOCCLK, 934 dpm_table); 935 if (ret) 936 return ret; 937 dpm_table->is_fine_grained = 938 !table_member[PPCLK_SOCCLK].SnapToDiscrete; 939 } else { 940 dpm_table->count = 1; 941 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 942 dpm_table->dpm_levels[0].enabled = true; 943 dpm_table->min = dpm_table->dpm_levels[0].value; 944 dpm_table->max = dpm_table->dpm_levels[0].value; 945 } 946 947 /* gfxclk dpm table setup */ 948 dpm_table = &dpm_context->dpm_tables.gfx_table; 949 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 950 ret = smu_v11_0_set_single_dpm_table(smu, 951 SMU_GFXCLK, 952 dpm_table); 953 if (ret) 954 return ret; 955 dpm_table->is_fine_grained = 956 !table_member[PPCLK_GFXCLK].SnapToDiscrete; 957 } else { 958 dpm_table->count = 1; 959 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 960 dpm_table->dpm_levels[0].enabled = true; 961 dpm_table->min = dpm_table->dpm_levels[0].value; 962 dpm_table->max = dpm_table->dpm_levels[0].value; 963 } 964 965 /* uclk dpm table setup */ 966 dpm_table = &dpm_context->dpm_tables.uclk_table; 967 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 968 ret = smu_v11_0_set_single_dpm_table(smu, 969 SMU_UCLK, 970 dpm_table); 971 if (ret) 972 return ret; 973 dpm_table->is_fine_grained = 974 !table_member[PPCLK_UCLK].SnapToDiscrete; 975 } else { 976 dpm_table->count = 1; 977 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 978 dpm_table->dpm_levels[0].enabled = true; 979 dpm_table->min = dpm_table->dpm_levels[0].value; 980 dpm_table->max = dpm_table->dpm_levels[0].value; 981 } 982 983 /* fclk dpm table setup */ 984 dpm_table = &dpm_context->dpm_tables.fclk_table; 985 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 986 ret = smu_v11_0_set_single_dpm_table(smu, 987 SMU_FCLK, 988 dpm_table); 989 if (ret) 990 return ret; 991 dpm_table->is_fine_grained = 992 !table_member[PPCLK_FCLK].SnapToDiscrete; 993 } else { 994 dpm_table->count = 1; 995 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 996 dpm_table->dpm_levels[0].enabled = true; 997 dpm_table->min = dpm_table->dpm_levels[0].value; 998 dpm_table->max = dpm_table->dpm_levels[0].value; 999 } 1000 1001 /* vclk0/1 dpm table setup */ 1002 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1003 if (adev->vcn.harvest_config & (1 << i)) 1004 continue; 1005 1006 dpm_table = &dpm_context->dpm_tables.vclk_table; 1007 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 1008 ret = smu_v11_0_set_single_dpm_table(smu, 1009 i ? SMU_VCLK1 : SMU_VCLK, 1010 dpm_table); 1011 if (ret) 1012 return ret; 1013 dpm_table->is_fine_grained = 1014 !table_member[i ? PPCLK_VCLK_1 : PPCLK_VCLK_0].SnapToDiscrete; 1015 } else { 1016 dpm_table->count = 1; 1017 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; 1018 dpm_table->dpm_levels[0].enabled = true; 1019 dpm_table->min = dpm_table->dpm_levels[0].value; 1020 dpm_table->max = dpm_table->dpm_levels[0].value; 1021 } 1022 } 1023 1024 /* dclk0/1 dpm table setup */ 1025 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1026 if (adev->vcn.harvest_config & (1 << i)) 1027 continue; 1028 dpm_table = &dpm_context->dpm_tables.dclk_table; 1029 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 1030 ret = smu_v11_0_set_single_dpm_table(smu, 1031 i ? SMU_DCLK1 : SMU_DCLK, 1032 dpm_table); 1033 if (ret) 1034 return ret; 1035 dpm_table->is_fine_grained = 1036 !table_member[i ? PPCLK_DCLK_1 : PPCLK_DCLK_0].SnapToDiscrete; 1037 } else { 1038 dpm_table->count = 1; 1039 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; 1040 dpm_table->dpm_levels[0].enabled = true; 1041 dpm_table->min = dpm_table->dpm_levels[0].value; 1042 dpm_table->max = dpm_table->dpm_levels[0].value; 1043 } 1044 } 1045 1046 /* dcefclk dpm table setup */ 1047 dpm_table = &dpm_context->dpm_tables.dcef_table; 1048 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1049 ret = smu_v11_0_set_single_dpm_table(smu, 1050 SMU_DCEFCLK, 1051 dpm_table); 1052 if (ret) 1053 return ret; 1054 dpm_table->is_fine_grained = 1055 !table_member[PPCLK_DCEFCLK].SnapToDiscrete; 1056 } else { 1057 dpm_table->count = 1; 1058 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1059 dpm_table->dpm_levels[0].enabled = true; 1060 dpm_table->min = dpm_table->dpm_levels[0].value; 1061 dpm_table->max = dpm_table->dpm_levels[0].value; 1062 } 1063 1064 /* pixelclk dpm table setup */ 1065 dpm_table = &dpm_context->dpm_tables.pixel_table; 1066 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1067 ret = smu_v11_0_set_single_dpm_table(smu, 1068 SMU_PIXCLK, 1069 dpm_table); 1070 if (ret) 1071 return ret; 1072 dpm_table->is_fine_grained = 1073 !table_member[PPCLK_PIXCLK].SnapToDiscrete; 1074 } else { 1075 dpm_table->count = 1; 1076 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1077 dpm_table->dpm_levels[0].enabled = true; 1078 dpm_table->min = dpm_table->dpm_levels[0].value; 1079 dpm_table->max = dpm_table->dpm_levels[0].value; 1080 } 1081 1082 /* displayclk dpm table setup */ 1083 dpm_table = &dpm_context->dpm_tables.display_table; 1084 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1085 ret = smu_v11_0_set_single_dpm_table(smu, 1086 SMU_DISPCLK, 1087 dpm_table); 1088 if (ret) 1089 return ret; 1090 dpm_table->is_fine_grained = 1091 !table_member[PPCLK_DISPCLK].SnapToDiscrete; 1092 } else { 1093 dpm_table->count = 1; 1094 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1095 dpm_table->dpm_levels[0].enabled = true; 1096 dpm_table->min = dpm_table->dpm_levels[0].value; 1097 dpm_table->max = dpm_table->dpm_levels[0].value; 1098 } 1099 1100 /* phyclk dpm table setup */ 1101 dpm_table = &dpm_context->dpm_tables.phy_table; 1102 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1103 ret = smu_v11_0_set_single_dpm_table(smu, 1104 SMU_PHYCLK, 1105 dpm_table); 1106 if (ret) 1107 return ret; 1108 dpm_table->is_fine_grained = 1109 !table_member[PPCLK_PHYCLK].SnapToDiscrete; 1110 } else { 1111 dpm_table->count = 1; 1112 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1113 dpm_table->dpm_levels[0].enabled = true; 1114 dpm_table->min = dpm_table->dpm_levels[0].value; 1115 dpm_table->max = dpm_table->dpm_levels[0].value; 1116 } 1117 1118 return 0; 1119 } 1120 1121 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 1122 { 1123 struct amdgpu_device *adev = smu->adev; 1124 int i, ret = 0; 1125 1126 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1127 if (adev->vcn.harvest_config & (1 << i)) 1128 continue; 1129 /* vcn dpm on is a prerequisite for vcn power gate messages */ 1130 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 1131 ret = smu_cmn_send_smc_msg_with_param(smu, enable ? 1132 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn, 1133 0x10000 * i, NULL); 1134 if (ret) 1135 return ret; 1136 } 1137 } 1138 1139 return ret; 1140 } 1141 1142 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 1143 { 1144 int ret = 0; 1145 1146 if (enable) { 1147 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 1148 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); 1149 if (ret) 1150 return ret; 1151 } 1152 } else { 1153 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 1154 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); 1155 if (ret) 1156 return ret; 1157 } 1158 } 1159 1160 return ret; 1161 } 1162 1163 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu, 1164 enum smu_clk_type clk_type, 1165 uint32_t *value) 1166 { 1167 MetricsMember_t member_type; 1168 int clk_id = 0; 1169 1170 clk_id = smu_cmn_to_asic_specific_index(smu, 1171 CMN2ASIC_MAPPING_CLK, 1172 clk_type); 1173 if (clk_id < 0) 1174 return clk_id; 1175 1176 switch (clk_id) { 1177 case PPCLK_GFXCLK: 1178 member_type = METRICS_CURR_GFXCLK; 1179 break; 1180 case PPCLK_UCLK: 1181 member_type = METRICS_CURR_UCLK; 1182 break; 1183 case PPCLK_SOCCLK: 1184 member_type = METRICS_CURR_SOCCLK; 1185 break; 1186 case PPCLK_FCLK: 1187 member_type = METRICS_CURR_FCLK; 1188 break; 1189 case PPCLK_VCLK_0: 1190 member_type = METRICS_CURR_VCLK; 1191 break; 1192 case PPCLK_VCLK_1: 1193 member_type = METRICS_CURR_VCLK1; 1194 break; 1195 case PPCLK_DCLK_0: 1196 member_type = METRICS_CURR_DCLK; 1197 break; 1198 case PPCLK_DCLK_1: 1199 member_type = METRICS_CURR_DCLK1; 1200 break; 1201 case PPCLK_DCEFCLK: 1202 member_type = METRICS_CURR_DCEFCLK; 1203 break; 1204 default: 1205 return -EINVAL; 1206 } 1207 1208 return sienna_cichlid_get_smu_metrics_data(smu, 1209 member_type, 1210 value); 1211 1212 } 1213 1214 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) 1215 { 1216 DpmDescriptor_t *dpm_desc = NULL; 1217 DpmDescriptor_t *table_member; 1218 uint32_t clk_index = 0; 1219 1220 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member); 1221 clk_index = smu_cmn_to_asic_specific_index(smu, 1222 CMN2ASIC_MAPPING_CLK, 1223 clk_type); 1224 dpm_desc = &table_member[clk_index]; 1225 1226 /* 0 - Fine grained DPM, 1 - Discrete DPM */ 1227 return dpm_desc->SnapToDiscrete == 0; 1228 } 1229 1230 static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table, 1231 enum SMU_11_0_7_ODFEATURE_CAP cap) 1232 { 1233 return od_table->cap[cap]; 1234 } 1235 1236 static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table, 1237 enum SMU_11_0_7_ODSETTING_ID setting, 1238 uint32_t *min, uint32_t *max) 1239 { 1240 if (min) 1241 *min = od_table->min[setting]; 1242 if (max) 1243 *max = od_table->max[setting]; 1244 } 1245 1246 static int sienna_cichlid_print_clk_levels(struct smu_context *smu, 1247 enum smu_clk_type clk_type, char *buf) 1248 { 1249 struct amdgpu_device *adev = smu->adev; 1250 struct smu_table_context *table_context = &smu->smu_table; 1251 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1252 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1253 uint16_t *table_member; 1254 1255 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings; 1256 OverDriveTable_t *od_table = 1257 (OverDriveTable_t *)table_context->overdrive_table; 1258 int i, size = 0, ret = 0; 1259 uint32_t cur_value = 0, value = 0, count = 0; 1260 uint32_t freq_values[3] = {0}; 1261 uint32_t mark_index = 0; 1262 uint32_t gen_speed, lane_width; 1263 uint32_t min_value, max_value; 1264 uint32_t smu_version; 1265 1266 smu_cmn_get_sysfs_buf(&buf, &size); 1267 1268 switch (clk_type) { 1269 case SMU_GFXCLK: 1270 case SMU_SCLK: 1271 case SMU_SOCCLK: 1272 case SMU_MCLK: 1273 case SMU_UCLK: 1274 case SMU_FCLK: 1275 case SMU_VCLK: 1276 case SMU_VCLK1: 1277 case SMU_DCLK: 1278 case SMU_DCLK1: 1279 case SMU_DCEFCLK: 1280 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value); 1281 if (ret) 1282 goto print_clk_out; 1283 1284 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); 1285 if (ret) 1286 goto print_clk_out; 1287 1288 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) { 1289 for (i = 0; i < count; i++) { 1290 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); 1291 if (ret) 1292 goto print_clk_out; 1293 1294 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 1295 cur_value == value ? "*" : ""); 1296 } 1297 } else { 1298 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]); 1299 if (ret) 1300 goto print_clk_out; 1301 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]); 1302 if (ret) 1303 goto print_clk_out; 1304 1305 freq_values[1] = cur_value; 1306 mark_index = cur_value == freq_values[0] ? 0 : 1307 cur_value == freq_values[2] ? 2 : 1; 1308 1309 count = 3; 1310 if (mark_index != 1) { 1311 count = 2; 1312 freq_values[1] = freq_values[2]; 1313 } 1314 1315 for (i = 0; i < count; i++) { 1316 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i], 1317 cur_value == freq_values[i] ? "*" : ""); 1318 } 1319 1320 } 1321 break; 1322 case SMU_PCIE: 1323 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); 1324 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); 1325 GET_PPTABLE_MEMBER(LclkFreq, &table_member); 1326 for (i = 0; i < NUM_LINK_LEVELS; i++) 1327 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i, 1328 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," : 1329 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," : 1330 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," : 1331 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "", 1332 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" : 1333 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" : 1334 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" : 1335 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" : 1336 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" : 1337 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "", 1338 table_member[i], 1339 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && 1340 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? 1341 "*" : ""); 1342 break; 1343 case SMU_OD_SCLK: 1344 if (!smu->od_enabled || !od_table || !od_settings) 1345 break; 1346 1347 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) 1348 break; 1349 1350 size += sysfs_emit_at(buf, size, "OD_SCLK:\n"); 1351 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax); 1352 break; 1353 1354 case SMU_OD_MCLK: 1355 if (!smu->od_enabled || !od_table || !od_settings) 1356 break; 1357 1358 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) 1359 break; 1360 1361 size += sysfs_emit_at(buf, size, "OD_MCLK:\n"); 1362 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax); 1363 break; 1364 1365 case SMU_OD_VDDGFX_OFFSET: 1366 if (!smu->od_enabled || !od_table || !od_settings) 1367 break; 1368 1369 /* 1370 * OD GFX Voltage Offset functionality is supported only by 58.41.0 1371 * and onwards SMU firmwares. 1372 */ 1373 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1374 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 1375 (smu_version < 0x003a2900)) 1376 break; 1377 1378 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n"); 1379 size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset); 1380 break; 1381 1382 case SMU_OD_RANGE: 1383 if (!smu->od_enabled || !od_table || !od_settings) 1384 break; 1385 1386 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 1387 1388 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) { 1389 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN, 1390 &min_value, NULL); 1391 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX, 1392 NULL, &max_value); 1393 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 1394 min_value, max_value); 1395 } 1396 1397 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) { 1398 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN, 1399 &min_value, NULL); 1400 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX, 1401 NULL, &max_value); 1402 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n", 1403 min_value, max_value); 1404 } 1405 break; 1406 1407 default: 1408 break; 1409 } 1410 1411 print_clk_out: 1412 return size; 1413 } 1414 1415 static int sienna_cichlid_force_clk_levels(struct smu_context *smu, 1416 enum smu_clk_type clk_type, uint32_t mask) 1417 { 1418 int ret = 0; 1419 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; 1420 1421 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1422 soft_max_level = mask ? (fls(mask) - 1) : 0; 1423 1424 switch (clk_type) { 1425 case SMU_GFXCLK: 1426 case SMU_SCLK: 1427 case SMU_SOCCLK: 1428 case SMU_MCLK: 1429 case SMU_UCLK: 1430 case SMU_FCLK: 1431 /* There is only 2 levels for fine grained DPM */ 1432 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) { 1433 soft_max_level = (soft_max_level >= 1 ? 1 : 0); 1434 soft_min_level = (soft_min_level >= 1 ? 1 : 0); 1435 } 1436 1437 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); 1438 if (ret) 1439 goto forec_level_out; 1440 1441 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq); 1442 if (ret) 1443 goto forec_level_out; 1444 1445 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 1446 if (ret) 1447 goto forec_level_out; 1448 break; 1449 case SMU_DCEFCLK: 1450 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n"); 1451 break; 1452 default: 1453 break; 1454 } 1455 1456 forec_level_out: 1457 return 0; 1458 } 1459 1460 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu) 1461 { 1462 struct smu_11_0_dpm_context *dpm_context = 1463 smu->smu_dpm.dpm_context; 1464 struct smu_11_0_dpm_table *gfx_table = 1465 &dpm_context->dpm_tables.gfx_table; 1466 struct smu_11_0_dpm_table *mem_table = 1467 &dpm_context->dpm_tables.uclk_table; 1468 struct smu_11_0_dpm_table *soc_table = 1469 &dpm_context->dpm_tables.soc_table; 1470 struct smu_umd_pstate_table *pstate_table = 1471 &smu->pstate_table; 1472 struct amdgpu_device *adev = smu->adev; 1473 1474 pstate_table->gfxclk_pstate.min = gfx_table->min; 1475 pstate_table->gfxclk_pstate.peak = gfx_table->max; 1476 1477 pstate_table->uclk_pstate.min = mem_table->min; 1478 pstate_table->uclk_pstate.peak = mem_table->max; 1479 1480 pstate_table->socclk_pstate.min = soc_table->min; 1481 pstate_table->socclk_pstate.peak = soc_table->max; 1482 1483 switch (adev->ip_versions[MP1_HWIP][0]) { 1484 case IP_VERSION(11, 0, 7): 1485 case IP_VERSION(11, 0, 11): 1486 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK; 1487 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK; 1488 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK; 1489 break; 1490 case IP_VERSION(11, 0, 12): 1491 pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK; 1492 pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK; 1493 pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK; 1494 break; 1495 case IP_VERSION(11, 0, 13): 1496 pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK; 1497 pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK; 1498 pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK; 1499 break; 1500 default: 1501 break; 1502 } 1503 1504 return 0; 1505 } 1506 1507 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu) 1508 { 1509 int ret = 0; 1510 uint32_t max_freq = 0; 1511 1512 /* Sienna_Cichlid do not support to change display num currently */ 1513 return 0; 1514 #if 0 1515 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL); 1516 if (ret) 1517 return ret; 1518 #endif 1519 1520 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1521 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq); 1522 if (ret) 1523 return ret; 1524 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq); 1525 if (ret) 1526 return ret; 1527 } 1528 1529 return ret; 1530 } 1531 1532 static int sienna_cichlid_display_config_changed(struct smu_context *smu) 1533 { 1534 int ret = 0; 1535 1536 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1537 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) && 1538 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 1539 #if 0 1540 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 1541 smu->display_config->num_display, 1542 NULL); 1543 #endif 1544 if (ret) 1545 return ret; 1546 } 1547 1548 return ret; 1549 } 1550 1551 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu) 1552 { 1553 int ret = 0; 1554 uint64_t feature_enabled; 1555 1556 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 1557 if (ret) 1558 return false; 1559 1560 return !!(feature_enabled & SMC_DPM_FEATURE); 1561 } 1562 1563 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu, 1564 uint32_t *speed) 1565 { 1566 if (!speed) 1567 return -EINVAL; 1568 1569 /* 1570 * For Sienna_Cichlid and later, the fan speed(rpm) reported 1571 * by pmfw is always trustable(even when the fan control feature 1572 * disabled or 0 RPM kicked in). 1573 */ 1574 return sienna_cichlid_get_smu_metrics_data(smu, 1575 METRICS_CURR_FANSPEED, 1576 speed); 1577 } 1578 1579 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu) 1580 { 1581 uint16_t *table_member; 1582 1583 GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member); 1584 smu->fan_max_rpm = *table_member; 1585 1586 return 0; 1587 } 1588 1589 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf) 1590 { 1591 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 1592 DpmActivityMonitorCoeffInt_t *activity_monitor = 1593 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 1594 uint32_t i, size = 0; 1595 int16_t workload_type = 0; 1596 static const char *title[] = { 1597 "PROFILE_INDEX(NAME)", 1598 "CLOCK_TYPE(NAME)", 1599 "FPS", 1600 "MinFreqType", 1601 "MinActiveFreqType", 1602 "MinActiveFreq", 1603 "BoosterFreqType", 1604 "BoosterFreq", 1605 "PD_Data_limit_c", 1606 "PD_Data_error_coeff", 1607 "PD_Data_error_rate_coeff"}; 1608 int result = 0; 1609 1610 if (!buf) 1611 return -EINVAL; 1612 1613 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n", 1614 title[0], title[1], title[2], title[3], title[4], title[5], 1615 title[6], title[7], title[8], title[9], title[10]); 1616 1617 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1618 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1619 workload_type = smu_cmn_to_asic_specific_index(smu, 1620 CMN2ASIC_MAPPING_WORKLOAD, 1621 i); 1622 if (workload_type < 0) 1623 return -EINVAL; 1624 1625 result = smu_cmn_update_table(smu, 1626 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type, 1627 (void *)(&activity_monitor_external), false); 1628 if (result) { 1629 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1630 return result; 1631 } 1632 1633 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n", 1634 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1635 1636 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1637 " ", 1638 0, 1639 "GFXCLK", 1640 activity_monitor->Gfx_FPS, 1641 activity_monitor->Gfx_MinFreqStep, 1642 activity_monitor->Gfx_MinActiveFreqType, 1643 activity_monitor->Gfx_MinActiveFreq, 1644 activity_monitor->Gfx_BoosterFreqType, 1645 activity_monitor->Gfx_BoosterFreq, 1646 activity_monitor->Gfx_PD_Data_limit_c, 1647 activity_monitor->Gfx_PD_Data_error_coeff, 1648 activity_monitor->Gfx_PD_Data_error_rate_coeff); 1649 1650 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1651 " ", 1652 1, 1653 "SOCCLK", 1654 activity_monitor->Fclk_FPS, 1655 activity_monitor->Fclk_MinFreqStep, 1656 activity_monitor->Fclk_MinActiveFreqType, 1657 activity_monitor->Fclk_MinActiveFreq, 1658 activity_monitor->Fclk_BoosterFreqType, 1659 activity_monitor->Fclk_BoosterFreq, 1660 activity_monitor->Fclk_PD_Data_limit_c, 1661 activity_monitor->Fclk_PD_Data_error_coeff, 1662 activity_monitor->Fclk_PD_Data_error_rate_coeff); 1663 1664 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1665 " ", 1666 2, 1667 "MEMLK", 1668 activity_monitor->Mem_FPS, 1669 activity_monitor->Mem_MinFreqStep, 1670 activity_monitor->Mem_MinActiveFreqType, 1671 activity_monitor->Mem_MinActiveFreq, 1672 activity_monitor->Mem_BoosterFreqType, 1673 activity_monitor->Mem_BoosterFreq, 1674 activity_monitor->Mem_PD_Data_limit_c, 1675 activity_monitor->Mem_PD_Data_error_coeff, 1676 activity_monitor->Mem_PD_Data_error_rate_coeff); 1677 } 1678 1679 return size; 1680 } 1681 1682 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 1683 { 1684 1685 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 1686 DpmActivityMonitorCoeffInt_t *activity_monitor = 1687 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 1688 int workload_type, ret = 0; 1689 1690 smu->power_profile_mode = input[size]; 1691 1692 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 1693 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode); 1694 return -EINVAL; 1695 } 1696 1697 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 1698 1699 ret = smu_cmn_update_table(smu, 1700 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1701 (void *)(&activity_monitor_external), false); 1702 if (ret) { 1703 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1704 return ret; 1705 } 1706 1707 switch (input[0]) { 1708 case 0: /* Gfxclk */ 1709 activity_monitor->Gfx_FPS = input[1]; 1710 activity_monitor->Gfx_MinFreqStep = input[2]; 1711 activity_monitor->Gfx_MinActiveFreqType = input[3]; 1712 activity_monitor->Gfx_MinActiveFreq = input[4]; 1713 activity_monitor->Gfx_BoosterFreqType = input[5]; 1714 activity_monitor->Gfx_BoosterFreq = input[6]; 1715 activity_monitor->Gfx_PD_Data_limit_c = input[7]; 1716 activity_monitor->Gfx_PD_Data_error_coeff = input[8]; 1717 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9]; 1718 break; 1719 case 1: /* Socclk */ 1720 activity_monitor->Fclk_FPS = input[1]; 1721 activity_monitor->Fclk_MinFreqStep = input[2]; 1722 activity_monitor->Fclk_MinActiveFreqType = input[3]; 1723 activity_monitor->Fclk_MinActiveFreq = input[4]; 1724 activity_monitor->Fclk_BoosterFreqType = input[5]; 1725 activity_monitor->Fclk_BoosterFreq = input[6]; 1726 activity_monitor->Fclk_PD_Data_limit_c = input[7]; 1727 activity_monitor->Fclk_PD_Data_error_coeff = input[8]; 1728 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9]; 1729 break; 1730 case 2: /* Memlk */ 1731 activity_monitor->Mem_FPS = input[1]; 1732 activity_monitor->Mem_MinFreqStep = input[2]; 1733 activity_monitor->Mem_MinActiveFreqType = input[3]; 1734 activity_monitor->Mem_MinActiveFreq = input[4]; 1735 activity_monitor->Mem_BoosterFreqType = input[5]; 1736 activity_monitor->Mem_BoosterFreq = input[6]; 1737 activity_monitor->Mem_PD_Data_limit_c = input[7]; 1738 activity_monitor->Mem_PD_Data_error_coeff = input[8]; 1739 activity_monitor->Mem_PD_Data_error_rate_coeff = input[9]; 1740 break; 1741 } 1742 1743 ret = smu_cmn_update_table(smu, 1744 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1745 (void *)(&activity_monitor_external), true); 1746 if (ret) { 1747 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 1748 return ret; 1749 } 1750 } 1751 1752 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1753 workload_type = smu_cmn_to_asic_specific_index(smu, 1754 CMN2ASIC_MAPPING_WORKLOAD, 1755 smu->power_profile_mode); 1756 if (workload_type < 0) 1757 return -EINVAL; 1758 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 1759 1 << workload_type, NULL); 1760 1761 return ret; 1762 } 1763 1764 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu) 1765 { 1766 struct smu_clocks min_clocks = {0}; 1767 struct pp_display_clock_request clock_req; 1768 int ret = 0; 1769 1770 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; 1771 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; 1772 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; 1773 1774 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1775 clock_req.clock_type = amd_pp_dcef_clock; 1776 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; 1777 1778 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req); 1779 if (!ret) { 1780 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) { 1781 ret = smu_cmn_send_smc_msg_with_param(smu, 1782 SMU_MSG_SetMinDeepSleepDcefclk, 1783 min_clocks.dcef_clock_in_sr/100, 1784 NULL); 1785 if (ret) { 1786 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!"); 1787 return ret; 1788 } 1789 } 1790 } else { 1791 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!"); 1792 } 1793 } 1794 1795 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1796 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); 1797 if (ret) { 1798 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__); 1799 return ret; 1800 } 1801 } 1802 1803 return 0; 1804 } 1805 1806 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu, 1807 struct pp_smu_wm_range_sets *clock_ranges) 1808 { 1809 Watermarks_t *table = smu->smu_table.watermarks_table; 1810 int ret = 0; 1811 int i; 1812 1813 if (clock_ranges) { 1814 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 1815 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1816 return -EINVAL; 1817 1818 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1819 table->WatermarkRow[WM_DCEFCLK][i].MinClock = 1820 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1821 table->WatermarkRow[WM_DCEFCLK][i].MaxClock = 1822 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1823 table->WatermarkRow[WM_DCEFCLK][i].MinUclk = 1824 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1825 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk = 1826 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1827 1828 table->WatermarkRow[WM_DCEFCLK][i].WmSetting = 1829 clock_ranges->reader_wm_sets[i].wm_inst; 1830 } 1831 1832 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1833 table->WatermarkRow[WM_SOCCLK][i].MinClock = 1834 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1835 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1836 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1837 table->WatermarkRow[WM_SOCCLK][i].MinUclk = 1838 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1839 table->WatermarkRow[WM_SOCCLK][i].MaxUclk = 1840 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1841 1842 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1843 clock_ranges->writer_wm_sets[i].wm_inst; 1844 } 1845 1846 smu->watermarks_bitmap |= WATERMARKS_EXIST; 1847 } 1848 1849 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1850 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1851 ret = smu_cmn_write_watermarks_table(smu); 1852 if (ret) { 1853 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1854 return ret; 1855 } 1856 smu->watermarks_bitmap |= WATERMARKS_LOADED; 1857 } 1858 1859 return 0; 1860 } 1861 1862 static int sienna_cichlid_read_sensor(struct smu_context *smu, 1863 enum amd_pp_sensors sensor, 1864 void *data, uint32_t *size) 1865 { 1866 int ret = 0; 1867 uint16_t *temp; 1868 struct amdgpu_device *adev = smu->adev; 1869 1870 if(!data || !size) 1871 return -EINVAL; 1872 1873 switch (sensor) { 1874 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 1875 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp); 1876 *(uint16_t *)data = *temp; 1877 *size = 4; 1878 break; 1879 case AMDGPU_PP_SENSOR_MEM_LOAD: 1880 ret = sienna_cichlid_get_smu_metrics_data(smu, 1881 METRICS_AVERAGE_MEMACTIVITY, 1882 (uint32_t *)data); 1883 *size = 4; 1884 break; 1885 case AMDGPU_PP_SENSOR_GPU_LOAD: 1886 ret = sienna_cichlid_get_smu_metrics_data(smu, 1887 METRICS_AVERAGE_GFXACTIVITY, 1888 (uint32_t *)data); 1889 *size = 4; 1890 break; 1891 case AMDGPU_PP_SENSOR_GPU_POWER: 1892 ret = sienna_cichlid_get_smu_metrics_data(smu, 1893 METRICS_AVERAGE_SOCKETPOWER, 1894 (uint32_t *)data); 1895 *size = 4; 1896 break; 1897 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1898 ret = sienna_cichlid_get_smu_metrics_data(smu, 1899 METRICS_TEMPERATURE_HOTSPOT, 1900 (uint32_t *)data); 1901 *size = 4; 1902 break; 1903 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1904 ret = sienna_cichlid_get_smu_metrics_data(smu, 1905 METRICS_TEMPERATURE_EDGE, 1906 (uint32_t *)data); 1907 *size = 4; 1908 break; 1909 case AMDGPU_PP_SENSOR_MEM_TEMP: 1910 ret = sienna_cichlid_get_smu_metrics_data(smu, 1911 METRICS_TEMPERATURE_MEM, 1912 (uint32_t *)data); 1913 *size = 4; 1914 break; 1915 case AMDGPU_PP_SENSOR_GFX_MCLK: 1916 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 1917 *(uint32_t *)data *= 100; 1918 *size = 4; 1919 break; 1920 case AMDGPU_PP_SENSOR_GFX_SCLK: 1921 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); 1922 *(uint32_t *)data *= 100; 1923 *size = 4; 1924 break; 1925 case AMDGPU_PP_SENSOR_VDDGFX: 1926 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data); 1927 *size = 4; 1928 break; 1929 case AMDGPU_PP_SENSOR_SS_APU_SHARE: 1930 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) { 1931 ret = sienna_cichlid_get_smu_metrics_data(smu, 1932 METRICS_SS_APU_SHARE, (uint32_t *)data); 1933 *size = 4; 1934 } else { 1935 ret = -EOPNOTSUPP; 1936 } 1937 break; 1938 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE: 1939 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) { 1940 ret = sienna_cichlid_get_smu_metrics_data(smu, 1941 METRICS_SS_DGPU_SHARE, (uint32_t *)data); 1942 *size = 4; 1943 } else { 1944 ret = -EOPNOTSUPP; 1945 } 1946 break; 1947 default: 1948 ret = -EOPNOTSUPP; 1949 break; 1950 } 1951 1952 return ret; 1953 } 1954 1955 static void sienna_cichlid_get_unique_id(struct smu_context *smu) 1956 { 1957 struct amdgpu_device *adev = smu->adev; 1958 uint32_t upper32 = 0, lower32 = 0; 1959 1960 /* Only supported as of version 0.58.83.0 and only on Sienna Cichlid */ 1961 if (smu->smc_fw_version < 0x3A5300 || 1962 smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) 1963 return; 1964 1965 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32)) 1966 goto out; 1967 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32)) 1968 goto out; 1969 1970 out: 1971 1972 adev->unique_id = ((uint64_t)upper32 << 32) | lower32; 1973 if (adev->serial[0] == '\0') 1974 sprintf(adev->serial, "%016llx", adev->unique_id); 1975 } 1976 1977 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states) 1978 { 1979 uint32_t num_discrete_levels = 0; 1980 uint16_t *dpm_levels = NULL; 1981 uint16_t i = 0; 1982 struct smu_table_context *table_context = &smu->smu_table; 1983 DpmDescriptor_t *table_member1; 1984 uint16_t *table_member2; 1985 1986 if (!clocks_in_khz || !num_states || !table_context->driver_pptable) 1987 return -EINVAL; 1988 1989 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1); 1990 num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels; 1991 GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2); 1992 dpm_levels = table_member2; 1993 1994 if (num_discrete_levels == 0 || dpm_levels == NULL) 1995 return -EINVAL; 1996 1997 *num_states = num_discrete_levels; 1998 for (i = 0; i < num_discrete_levels; i++) { 1999 /* convert to khz */ 2000 *clocks_in_khz = (*dpm_levels) * 1000; 2001 clocks_in_khz++; 2002 dpm_levels++; 2003 } 2004 2005 return 0; 2006 } 2007 2008 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu, 2009 struct smu_temperature_range *range) 2010 { 2011 struct smu_table_context *table_context = &smu->smu_table; 2012 struct smu_11_0_7_powerplay_table *powerplay_table = 2013 table_context->power_play_table; 2014 uint16_t *table_member; 2015 uint16_t temp_edge, temp_hotspot, temp_mem; 2016 2017 if (!range) 2018 return -EINVAL; 2019 2020 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range)); 2021 2022 GET_PPTABLE_MEMBER(TemperatureLimit, &table_member); 2023 temp_edge = table_member[TEMP_EDGE]; 2024 temp_hotspot = table_member[TEMP_HOTSPOT]; 2025 temp_mem = table_member[TEMP_MEM]; 2026 2027 range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2028 range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) * 2029 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2030 range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2031 range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) * 2032 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2033 range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2034 range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)* 2035 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2036 2037 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 2038 2039 return 0; 2040 } 2041 2042 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu, 2043 bool disable_memory_clock_switch) 2044 { 2045 int ret = 0; 2046 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks = 2047 (struct smu_11_0_max_sustainable_clocks *) 2048 smu->smu_table.max_sustainable_clocks; 2049 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal; 2050 uint32_t max_memory_clock = max_sustainable_clocks->uclock; 2051 2052 if(smu->disable_uclk_switch == disable_memory_clock_switch) 2053 return 0; 2054 2055 if(disable_memory_clock_switch) 2056 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0); 2057 else 2058 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0); 2059 2060 if(!ret) 2061 smu->disable_uclk_switch = disable_memory_clock_switch; 2062 2063 return ret; 2064 } 2065 2066 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu, 2067 uint32_t pcie_gen_cap, 2068 uint32_t pcie_width_cap) 2069 { 2070 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 2071 2072 uint32_t smu_pcie_arg; 2073 uint8_t *table_member1, *table_member2; 2074 int ret, i; 2075 2076 GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1); 2077 GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2); 2078 2079 /* lclk dpm table setup */ 2080 for (i = 0; i < MAX_PCIE_CONF; i++) { 2081 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = table_member1[i]; 2082 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = table_member2[i]; 2083 } 2084 2085 for (i = 0; i < NUM_LINK_LEVELS; i++) { 2086 smu_pcie_arg = (i << 16) | 2087 ((table_member1[i] <= pcie_gen_cap) ? 2088 (table_member1[i] << 8) : 2089 (pcie_gen_cap << 8)) | 2090 ((table_member2[i] <= pcie_width_cap) ? 2091 table_member2[i] : 2092 pcie_width_cap); 2093 2094 ret = smu_cmn_send_smc_msg_with_param(smu, 2095 SMU_MSG_OverridePcieParameters, 2096 smu_pcie_arg, 2097 NULL); 2098 if (ret) 2099 return ret; 2100 2101 if (table_member1[i] > pcie_gen_cap) 2102 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap; 2103 if (table_member2[i] > pcie_width_cap) 2104 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap; 2105 } 2106 2107 return 0; 2108 } 2109 2110 static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu, 2111 enum smu_clk_type clk_type, 2112 uint32_t *min, uint32_t *max) 2113 { 2114 return smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max); 2115 } 2116 2117 static void sienna_cichlid_dump_od_table(struct smu_context *smu, 2118 OverDriveTable_t *od_table) 2119 { 2120 struct amdgpu_device *adev = smu->adev; 2121 uint32_t smu_version; 2122 2123 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, 2124 od_table->GfxclkFmax); 2125 dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin, 2126 od_table->UclkFmax); 2127 2128 smu_cmn_get_smc_version(smu, NULL, &smu_version); 2129 if (!((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 2130 (smu_version < 0x003a2900))) 2131 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset); 2132 } 2133 2134 static int sienna_cichlid_set_default_od_settings(struct smu_context *smu) 2135 { 2136 OverDriveTable_t *od_table = 2137 (OverDriveTable_t *)smu->smu_table.overdrive_table; 2138 OverDriveTable_t *boot_od_table = 2139 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table; 2140 OverDriveTable_t *user_od_table = 2141 (OverDriveTable_t *)smu->smu_table.user_overdrive_table; 2142 int ret = 0; 2143 2144 /* 2145 * For S3/S4/Runpm resume, no need to setup those overdrive tables again as 2146 * - either they already have the default OD settings got during cold bootup 2147 * - or they have some user customized OD settings which cannot be overwritten 2148 */ 2149 if (smu->adev->in_suspend) 2150 return 0; 2151 2152 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 2153 0, (void *)boot_od_table, false); 2154 if (ret) { 2155 dev_err(smu->adev->dev, "Failed to get overdrive table!\n"); 2156 return ret; 2157 } 2158 2159 sienna_cichlid_dump_od_table(smu, boot_od_table); 2160 2161 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t)); 2162 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t)); 2163 2164 return 0; 2165 } 2166 2167 static int sienna_cichlid_od_setting_check_range(struct smu_context *smu, 2168 struct smu_11_0_7_overdrive_table *od_table, 2169 enum SMU_11_0_7_ODSETTING_ID setting, 2170 uint32_t value) 2171 { 2172 if (value < od_table->min[setting]) { 2173 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", 2174 setting, value, od_table->min[setting]); 2175 return -EINVAL; 2176 } 2177 if (value > od_table->max[setting]) { 2178 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", 2179 setting, value, od_table->max[setting]); 2180 return -EINVAL; 2181 } 2182 2183 return 0; 2184 } 2185 2186 static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu, 2187 enum PP_OD_DPM_TABLE_COMMAND type, 2188 long input[], uint32_t size) 2189 { 2190 struct smu_table_context *table_context = &smu->smu_table; 2191 OverDriveTable_t *od_table = 2192 (OverDriveTable_t *)table_context->overdrive_table; 2193 struct smu_11_0_7_overdrive_table *od_settings = 2194 (struct smu_11_0_7_overdrive_table *)smu->od_settings; 2195 struct amdgpu_device *adev = smu->adev; 2196 enum SMU_11_0_7_ODSETTING_ID freq_setting; 2197 uint16_t *freq_ptr; 2198 int i, ret = 0; 2199 uint32_t smu_version; 2200 2201 if (!smu->od_enabled) { 2202 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n"); 2203 return -EINVAL; 2204 } 2205 2206 if (!smu->od_settings) { 2207 dev_err(smu->adev->dev, "OD board limits are not set!\n"); 2208 return -ENOENT; 2209 } 2210 2211 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) { 2212 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n"); 2213 return -EINVAL; 2214 } 2215 2216 switch (type) { 2217 case PP_OD_EDIT_SCLK_VDDC_TABLE: 2218 if (!sienna_cichlid_is_od_feature_supported(od_settings, 2219 SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) { 2220 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n"); 2221 return -ENOTSUPP; 2222 } 2223 2224 for (i = 0; i < size; i += 2) { 2225 if (i + 2 > size) { 2226 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size); 2227 return -EINVAL; 2228 } 2229 2230 switch (input[i]) { 2231 case 0: 2232 if (input[i + 1] > od_table->GfxclkFmax) { 2233 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n", 2234 input[i + 1], od_table->GfxclkFmax); 2235 return -EINVAL; 2236 } 2237 2238 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN; 2239 freq_ptr = &od_table->GfxclkFmin; 2240 break; 2241 2242 case 1: 2243 if (input[i + 1] < od_table->GfxclkFmin) { 2244 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n", 2245 input[i + 1], od_table->GfxclkFmin); 2246 return -EINVAL; 2247 } 2248 2249 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX; 2250 freq_ptr = &od_table->GfxclkFmax; 2251 break; 2252 2253 default: 2254 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]); 2255 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n"); 2256 return -EINVAL; 2257 } 2258 2259 ret = sienna_cichlid_od_setting_check_range(smu, od_settings, 2260 freq_setting, input[i + 1]); 2261 if (ret) 2262 return ret; 2263 2264 *freq_ptr = (uint16_t)input[i + 1]; 2265 } 2266 break; 2267 2268 case PP_OD_EDIT_MCLK_VDDC_TABLE: 2269 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) { 2270 dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n"); 2271 return -ENOTSUPP; 2272 } 2273 2274 for (i = 0; i < size; i += 2) { 2275 if (i + 2 > size) { 2276 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size); 2277 return -EINVAL; 2278 } 2279 2280 switch (input[i]) { 2281 case 0: 2282 if (input[i + 1] > od_table->UclkFmax) { 2283 dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n", 2284 input[i + 1], od_table->UclkFmax); 2285 return -EINVAL; 2286 } 2287 2288 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN; 2289 freq_ptr = &od_table->UclkFmin; 2290 break; 2291 2292 case 1: 2293 if (input[i + 1] < od_table->UclkFmin) { 2294 dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n", 2295 input[i + 1], od_table->UclkFmin); 2296 return -EINVAL; 2297 } 2298 2299 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX; 2300 freq_ptr = &od_table->UclkFmax; 2301 break; 2302 2303 default: 2304 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]); 2305 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n"); 2306 return -EINVAL; 2307 } 2308 2309 ret = sienna_cichlid_od_setting_check_range(smu, od_settings, 2310 freq_setting, input[i + 1]); 2311 if (ret) 2312 return ret; 2313 2314 *freq_ptr = (uint16_t)input[i + 1]; 2315 } 2316 break; 2317 2318 case PP_OD_RESTORE_DEFAULT_TABLE: 2319 memcpy(table_context->overdrive_table, 2320 table_context->boot_overdrive_table, 2321 sizeof(OverDriveTable_t)); 2322 fallthrough; 2323 2324 case PP_OD_COMMIT_DPM_TABLE: 2325 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) { 2326 sienna_cichlid_dump_od_table(smu, od_table); 2327 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true); 2328 if (ret) { 2329 dev_err(smu->adev->dev, "Failed to import overdrive table!\n"); 2330 return ret; 2331 } 2332 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t)); 2333 smu->user_dpm_profile.user_od = true; 2334 2335 if (!memcmp(table_context->user_overdrive_table, 2336 table_context->boot_overdrive_table, 2337 sizeof(OverDriveTable_t))) 2338 smu->user_dpm_profile.user_od = false; 2339 } 2340 break; 2341 2342 case PP_OD_EDIT_VDDGFX_OFFSET: 2343 if (size != 1) { 2344 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size); 2345 return -EINVAL; 2346 } 2347 2348 /* 2349 * OD GFX Voltage Offset functionality is supported only by 58.41.0 2350 * and onwards SMU firmwares. 2351 */ 2352 smu_cmn_get_smc_version(smu, NULL, &smu_version); 2353 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && 2354 (smu_version < 0x003a2900)) { 2355 dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported " 2356 "only by 58.41.0 and onwards SMU firmwares!\n"); 2357 return -EOPNOTSUPP; 2358 } 2359 2360 od_table->VddGfxOffset = (int16_t)input[0]; 2361 2362 sienna_cichlid_dump_od_table(smu, od_table); 2363 break; 2364 2365 default: 2366 return -ENOSYS; 2367 } 2368 2369 return ret; 2370 } 2371 2372 static int sienna_cichlid_run_btc(struct smu_context *smu) 2373 { 2374 int res; 2375 2376 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); 2377 if (res) 2378 dev_err(smu->adev->dev, "RunDcBtc failed!\n"); 2379 2380 return res; 2381 } 2382 2383 static int sienna_cichlid_baco_enter(struct smu_context *smu) 2384 { 2385 struct amdgpu_device *adev = smu->adev; 2386 2387 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) 2388 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO); 2389 else 2390 return smu_v11_0_baco_enter(smu); 2391 } 2392 2393 static int sienna_cichlid_baco_exit(struct smu_context *smu) 2394 { 2395 struct amdgpu_device *adev = smu->adev; 2396 2397 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) { 2398 /* Wait for PMFW handling for the Dstate change */ 2399 msleep(10); 2400 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS); 2401 } else { 2402 return smu_v11_0_baco_exit(smu); 2403 } 2404 } 2405 2406 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu) 2407 { 2408 struct amdgpu_device *adev = smu->adev; 2409 uint32_t val; 2410 u32 smu_version; 2411 2412 /** 2413 * SRIOV env will not support SMU mode1 reset 2414 * PM FW support mode1 reset from 58.26 2415 */ 2416 smu_cmn_get_smc_version(smu, NULL, &smu_version); 2417 if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00)) 2418 return false; 2419 2420 /** 2421 * mode1 reset relies on PSP, so we should check if 2422 * PSP is alive. 2423 */ 2424 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 2425 return val != 0x0; 2426 } 2427 2428 static void beige_goby_dump_pptable(struct smu_context *smu) 2429 { 2430 struct smu_table_context *table_context = &smu->smu_table; 2431 PPTable_beige_goby_t *pptable = table_context->driver_pptable; 2432 int i; 2433 2434 dev_info(smu->adev->dev, "Dumped PPTable:\n"); 2435 2436 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version); 2437 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]); 2438 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]); 2439 2440 for (i = 0; i < PPT_THROTTLER_COUNT; i++) { 2441 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]); 2442 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]); 2443 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]); 2444 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]); 2445 } 2446 2447 for (i = 0; i < TDC_THROTTLER_COUNT; i++) { 2448 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]); 2449 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]); 2450 } 2451 2452 for (i = 0; i < TEMP_COUNT; i++) { 2453 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]); 2454 } 2455 2456 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit); 2457 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig); 2458 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]); 2459 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]); 2460 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]); 2461 2462 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit); 2463 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) { 2464 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]); 2465 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]); 2466 } 2467 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask); 2468 2469 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask); 2470 2471 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc); 2472 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx); 2473 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx); 2474 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc); 2475 2476 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin); 2477 2478 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold); 2479 2480 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx); 2481 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc); 2482 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx); 2483 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc); 2484 2485 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx); 2486 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc); 2487 2488 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin); 2489 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin); 2490 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp); 2491 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp); 2492 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp); 2493 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp); 2494 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis); 2495 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis); 2496 2497 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n" 2498 " .VoltageMode = 0x%02x\n" 2499 " .SnapToDiscrete = 0x%02x\n" 2500 " .NumDiscreteLevels = 0x%02x\n" 2501 " .padding = 0x%02x\n" 2502 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2503 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2504 " .SsFmin = 0x%04x\n" 2505 " .Padding_16 = 0x%04x\n", 2506 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode, 2507 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete, 2508 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels, 2509 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding, 2510 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m, 2511 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b, 2512 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a, 2513 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b, 2514 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c, 2515 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin, 2516 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16); 2517 2518 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n" 2519 " .VoltageMode = 0x%02x\n" 2520 " .SnapToDiscrete = 0x%02x\n" 2521 " .NumDiscreteLevels = 0x%02x\n" 2522 " .padding = 0x%02x\n" 2523 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2524 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2525 " .SsFmin = 0x%04x\n" 2526 " .Padding_16 = 0x%04x\n", 2527 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode, 2528 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete, 2529 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels, 2530 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding, 2531 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m, 2532 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b, 2533 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a, 2534 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b, 2535 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c, 2536 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin, 2537 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16); 2538 2539 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n" 2540 " .VoltageMode = 0x%02x\n" 2541 " .SnapToDiscrete = 0x%02x\n" 2542 " .NumDiscreteLevels = 0x%02x\n" 2543 " .padding = 0x%02x\n" 2544 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2545 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2546 " .SsFmin = 0x%04x\n" 2547 " .Padding_16 = 0x%04x\n", 2548 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode, 2549 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete, 2550 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels, 2551 pptable->DpmDescriptor[PPCLK_UCLK].Padding, 2552 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m, 2553 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b, 2554 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a, 2555 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b, 2556 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c, 2557 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin, 2558 pptable->DpmDescriptor[PPCLK_UCLK].Padding16); 2559 2560 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n" 2561 " .VoltageMode = 0x%02x\n" 2562 " .SnapToDiscrete = 0x%02x\n" 2563 " .NumDiscreteLevels = 0x%02x\n" 2564 " .padding = 0x%02x\n" 2565 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2566 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2567 " .SsFmin = 0x%04x\n" 2568 " .Padding_16 = 0x%04x\n", 2569 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode, 2570 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete, 2571 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels, 2572 pptable->DpmDescriptor[PPCLK_FCLK].Padding, 2573 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m, 2574 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b, 2575 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a, 2576 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b, 2577 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c, 2578 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin, 2579 pptable->DpmDescriptor[PPCLK_FCLK].Padding16); 2580 2581 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n" 2582 " .VoltageMode = 0x%02x\n" 2583 " .SnapToDiscrete = 0x%02x\n" 2584 " .NumDiscreteLevels = 0x%02x\n" 2585 " .padding = 0x%02x\n" 2586 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2587 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2588 " .SsFmin = 0x%04x\n" 2589 " .Padding_16 = 0x%04x\n", 2590 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode, 2591 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete, 2592 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels, 2593 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding, 2594 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m, 2595 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b, 2596 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a, 2597 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b, 2598 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c, 2599 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin, 2600 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16); 2601 2602 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n" 2603 " .VoltageMode = 0x%02x\n" 2604 " .SnapToDiscrete = 0x%02x\n" 2605 " .NumDiscreteLevels = 0x%02x\n" 2606 " .padding = 0x%02x\n" 2607 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2608 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2609 " .SsFmin = 0x%04x\n" 2610 " .Padding_16 = 0x%04x\n", 2611 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode, 2612 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete, 2613 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels, 2614 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding, 2615 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m, 2616 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b, 2617 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a, 2618 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b, 2619 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c, 2620 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin, 2621 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16); 2622 2623 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n" 2624 " .VoltageMode = 0x%02x\n" 2625 " .SnapToDiscrete = 0x%02x\n" 2626 " .NumDiscreteLevels = 0x%02x\n" 2627 " .padding = 0x%02x\n" 2628 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2629 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2630 " .SsFmin = 0x%04x\n" 2631 " .Padding_16 = 0x%04x\n", 2632 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode, 2633 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete, 2634 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels, 2635 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding, 2636 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m, 2637 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b, 2638 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a, 2639 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b, 2640 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c, 2641 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin, 2642 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16); 2643 2644 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n" 2645 " .VoltageMode = 0x%02x\n" 2646 " .SnapToDiscrete = 0x%02x\n" 2647 " .NumDiscreteLevels = 0x%02x\n" 2648 " .padding = 0x%02x\n" 2649 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2650 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2651 " .SsFmin = 0x%04x\n" 2652 " .Padding_16 = 0x%04x\n", 2653 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode, 2654 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete, 2655 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels, 2656 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding, 2657 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m, 2658 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b, 2659 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a, 2660 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b, 2661 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c, 2662 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin, 2663 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16); 2664 2665 dev_info(smu->adev->dev, "FreqTableGfx\n"); 2666 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) 2667 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]); 2668 2669 dev_info(smu->adev->dev, "FreqTableVclk\n"); 2670 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++) 2671 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]); 2672 2673 dev_info(smu->adev->dev, "FreqTableDclk\n"); 2674 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++) 2675 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]); 2676 2677 dev_info(smu->adev->dev, "FreqTableSocclk\n"); 2678 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) 2679 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]); 2680 2681 dev_info(smu->adev->dev, "FreqTableUclk\n"); 2682 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2683 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]); 2684 2685 dev_info(smu->adev->dev, "FreqTableFclk\n"); 2686 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) 2687 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]); 2688 2689 dev_info(smu->adev->dev, "DcModeMaxFreq\n"); 2690 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]); 2691 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]); 2692 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]); 2693 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]); 2694 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]); 2695 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]); 2696 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]); 2697 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]); 2698 2699 dev_info(smu->adev->dev, "FreqTableUclkDiv\n"); 2700 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2701 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]); 2702 2703 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq); 2704 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding); 2705 2706 dev_info(smu->adev->dev, "Mp0clkFreq\n"); 2707 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 2708 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]); 2709 2710 dev_info(smu->adev->dev, "Mp0DpmVoltage\n"); 2711 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 2712 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]); 2713 2714 dev_info(smu->adev->dev, "MemVddciVoltage\n"); 2715 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2716 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]); 2717 2718 dev_info(smu->adev->dev, "MemMvddVoltage\n"); 2719 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2720 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]); 2721 2722 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry); 2723 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit); 2724 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle); 2725 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource); 2726 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding); 2727 2728 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask); 2729 2730 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask); 2731 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask); 2732 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]); 2733 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow); 2734 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]); 2735 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]); 2736 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]); 2737 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]); 2738 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt); 2739 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt); 2740 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt); 2741 2742 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage); 2743 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime); 2744 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime); 2745 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum); 2746 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis); 2747 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout); 2748 2749 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]); 2750 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]); 2751 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]); 2752 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]); 2753 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]); 2754 2755 dev_info(smu->adev->dev, "FlopsPerByteTable\n"); 2756 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++) 2757 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]); 2758 2759 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv); 2760 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]); 2761 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]); 2762 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]); 2763 2764 dev_info(smu->adev->dev, "UclkDpmPstates\n"); 2765 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2766 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]); 2767 2768 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n"); 2769 dev_info(smu->adev->dev, " .Fmin = 0x%x\n", 2770 pptable->UclkDpmSrcFreqRange.Fmin); 2771 dev_info(smu->adev->dev, " .Fmax = 0x%x\n", 2772 pptable->UclkDpmSrcFreqRange.Fmax); 2773 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n"); 2774 dev_info(smu->adev->dev, " .Fmin = 0x%x\n", 2775 pptable->UclkDpmTargFreqRange.Fmin); 2776 dev_info(smu->adev->dev, " .Fmax = 0x%x\n", 2777 pptable->UclkDpmTargFreqRange.Fmax); 2778 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq); 2779 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding); 2780 2781 dev_info(smu->adev->dev, "PcieGenSpeed\n"); 2782 for (i = 0; i < NUM_LINK_LEVELS; i++) 2783 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]); 2784 2785 dev_info(smu->adev->dev, "PcieLaneCount\n"); 2786 for (i = 0; i < NUM_LINK_LEVELS; i++) 2787 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]); 2788 2789 dev_info(smu->adev->dev, "LclkFreq\n"); 2790 for (i = 0; i < NUM_LINK_LEVELS; i++) 2791 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]); 2792 2793 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp); 2794 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp); 2795 2796 dev_info(smu->adev->dev, "FanGain\n"); 2797 for (i = 0; i < TEMP_COUNT; i++) 2798 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]); 2799 2800 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin); 2801 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm); 2802 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm); 2803 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm); 2804 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm); 2805 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature); 2806 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk); 2807 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16); 2808 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect); 2809 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding); 2810 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable); 2811 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev); 2812 2813 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta); 2814 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta); 2815 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta); 2816 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved); 2817 2818 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]); 2819 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]); 2820 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect); 2821 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs); 2822 2823 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", 2824 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a, 2825 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b, 2826 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c); 2827 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", 2828 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a, 2829 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b, 2830 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c); 2831 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n", 2832 pptable->dBtcGbGfxPll.a, 2833 pptable->dBtcGbGfxPll.b, 2834 pptable->dBtcGbGfxPll.c); 2835 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n", 2836 pptable->dBtcGbGfxDfll.a, 2837 pptable->dBtcGbGfxDfll.b, 2838 pptable->dBtcGbGfxDfll.c); 2839 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n", 2840 pptable->dBtcGbSoc.a, 2841 pptable->dBtcGbSoc.b, 2842 pptable->dBtcGbSoc.c); 2843 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n", 2844 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m, 2845 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b); 2846 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n", 2847 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m, 2848 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b); 2849 2850 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n"); 2851 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) { 2852 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n", 2853 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]); 2854 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n", 2855 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]); 2856 } 2857 2858 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", 2859 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a, 2860 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b, 2861 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c); 2862 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", 2863 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a, 2864 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b, 2865 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c); 2866 2867 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]); 2868 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]); 2869 2870 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]); 2871 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]); 2872 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]); 2873 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]); 2874 2875 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]); 2876 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]); 2877 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]); 2878 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]); 2879 2880 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]); 2881 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]); 2882 2883 dev_info(smu->adev->dev, "XgmiDpmPstates\n"); 2884 for (i = 0; i < NUM_XGMI_LEVELS; i++) 2885 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]); 2886 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]); 2887 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]); 2888 2889 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides); 2890 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n", 2891 pptable->ReservedEquation0.a, 2892 pptable->ReservedEquation0.b, 2893 pptable->ReservedEquation0.c); 2894 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n", 2895 pptable->ReservedEquation1.a, 2896 pptable->ReservedEquation1.b, 2897 pptable->ReservedEquation1.c); 2898 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n", 2899 pptable->ReservedEquation2.a, 2900 pptable->ReservedEquation2.b, 2901 pptable->ReservedEquation2.c); 2902 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n", 2903 pptable->ReservedEquation3.a, 2904 pptable->ReservedEquation3.b, 2905 pptable->ReservedEquation3.c); 2906 2907 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]); 2908 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]); 2909 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]); 2910 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]); 2911 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]); 2912 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]); 2913 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]); 2914 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]); 2915 2916 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]); 2917 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]); 2918 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]); 2919 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]); 2920 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]); 2921 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]); 2922 2923 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) { 2924 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i); 2925 dev_info(smu->adev->dev, " .Enabled = 0x%x\n", 2926 pptable->I2cControllers[i].Enabled); 2927 dev_info(smu->adev->dev, " .Speed = 0x%x\n", 2928 pptable->I2cControllers[i].Speed); 2929 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n", 2930 pptable->I2cControllers[i].SlaveAddress); 2931 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n", 2932 pptable->I2cControllers[i].ControllerPort); 2933 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n", 2934 pptable->I2cControllers[i].ControllerName); 2935 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n", 2936 pptable->I2cControllers[i].ThermalThrotter); 2937 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n", 2938 pptable->I2cControllers[i].I2cProtocol); 2939 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n", 2940 pptable->I2cControllers[i].PaddingConfig); 2941 } 2942 2943 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl); 2944 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda); 2945 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr); 2946 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]); 2947 2948 dev_info(smu->adev->dev, "Board Parameters:\n"); 2949 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping); 2950 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping); 2951 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping); 2952 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping); 2953 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask); 2954 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask); 2955 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask); 2956 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask); 2957 2958 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent); 2959 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset); 2960 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx); 2961 2962 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent); 2963 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset); 2964 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc); 2965 2966 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent); 2967 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset); 2968 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0); 2969 2970 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent); 2971 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset); 2972 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1); 2973 2974 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio); 2975 2976 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio); 2977 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity); 2978 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio); 2979 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity); 2980 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio); 2981 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity); 2982 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio); 2983 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity); 2984 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0); 2985 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1); 2986 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2); 2987 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask); 2988 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie); 2989 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError); 2990 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]); 2991 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]); 2992 2993 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled); 2994 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent); 2995 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq); 2996 2997 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled); 2998 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent); 2999 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq); 3000 3001 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding); 3002 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq); 3003 3004 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled); 3005 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent); 3006 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq); 3007 3008 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled); 3009 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth); 3010 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]); 3011 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]); 3012 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]); 3013 3014 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower); 3015 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding); 3016 3017 dev_info(smu->adev->dev, "XgmiLinkSpeed\n"); 3018 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3019 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]); 3020 dev_info(smu->adev->dev, "XgmiLinkWidth\n"); 3021 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3022 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]); 3023 dev_info(smu->adev->dev, "XgmiFclkFreq\n"); 3024 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3025 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]); 3026 dev_info(smu->adev->dev, "XgmiSocVoltage\n"); 3027 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3028 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]); 3029 3030 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled); 3031 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled); 3032 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]); 3033 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]); 3034 3035 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]); 3036 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]); 3037 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]); 3038 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]); 3039 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]); 3040 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]); 3041 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]); 3042 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]); 3043 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]); 3044 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]); 3045 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]); 3046 3047 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]); 3048 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]); 3049 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]); 3050 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]); 3051 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]); 3052 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]); 3053 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]); 3054 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]); 3055 } 3056 3057 static void sienna_cichlid_dump_pptable(struct smu_context *smu) 3058 { 3059 struct smu_table_context *table_context = &smu->smu_table; 3060 PPTable_t *pptable = table_context->driver_pptable; 3061 int i; 3062 3063 if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) { 3064 beige_goby_dump_pptable(smu); 3065 return; 3066 } 3067 3068 dev_info(smu->adev->dev, "Dumped PPTable:\n"); 3069 3070 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version); 3071 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]); 3072 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]); 3073 3074 for (i = 0; i < PPT_THROTTLER_COUNT; i++) { 3075 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]); 3076 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]); 3077 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]); 3078 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]); 3079 } 3080 3081 for (i = 0; i < TDC_THROTTLER_COUNT; i++) { 3082 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]); 3083 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]); 3084 } 3085 3086 for (i = 0; i < TEMP_COUNT; i++) { 3087 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]); 3088 } 3089 3090 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit); 3091 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig); 3092 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]); 3093 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]); 3094 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]); 3095 3096 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit); 3097 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) { 3098 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]); 3099 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]); 3100 } 3101 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask); 3102 3103 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask); 3104 3105 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc); 3106 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx); 3107 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx); 3108 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc); 3109 3110 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin); 3111 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin); 3112 3113 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold); 3114 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]); 3115 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]); 3116 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]); 3117 3118 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx); 3119 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc); 3120 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx); 3121 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc); 3122 3123 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx); 3124 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc); 3125 3126 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin); 3127 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin); 3128 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp); 3129 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp); 3130 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp); 3131 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp); 3132 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis); 3133 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis); 3134 3135 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n" 3136 " .VoltageMode = 0x%02x\n" 3137 " .SnapToDiscrete = 0x%02x\n" 3138 " .NumDiscreteLevels = 0x%02x\n" 3139 " .padding = 0x%02x\n" 3140 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3141 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3142 " .SsFmin = 0x%04x\n" 3143 " .Padding_16 = 0x%04x\n", 3144 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode, 3145 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete, 3146 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels, 3147 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding, 3148 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m, 3149 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b, 3150 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a, 3151 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b, 3152 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c, 3153 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin, 3154 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16); 3155 3156 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n" 3157 " .VoltageMode = 0x%02x\n" 3158 " .SnapToDiscrete = 0x%02x\n" 3159 " .NumDiscreteLevels = 0x%02x\n" 3160 " .padding = 0x%02x\n" 3161 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3162 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3163 " .SsFmin = 0x%04x\n" 3164 " .Padding_16 = 0x%04x\n", 3165 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode, 3166 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete, 3167 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels, 3168 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding, 3169 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m, 3170 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b, 3171 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a, 3172 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b, 3173 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c, 3174 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin, 3175 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16); 3176 3177 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n" 3178 " .VoltageMode = 0x%02x\n" 3179 " .SnapToDiscrete = 0x%02x\n" 3180 " .NumDiscreteLevels = 0x%02x\n" 3181 " .padding = 0x%02x\n" 3182 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3183 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3184 " .SsFmin = 0x%04x\n" 3185 " .Padding_16 = 0x%04x\n", 3186 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode, 3187 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete, 3188 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels, 3189 pptable->DpmDescriptor[PPCLK_UCLK].Padding, 3190 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m, 3191 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b, 3192 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a, 3193 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b, 3194 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c, 3195 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin, 3196 pptable->DpmDescriptor[PPCLK_UCLK].Padding16); 3197 3198 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n" 3199 " .VoltageMode = 0x%02x\n" 3200 " .SnapToDiscrete = 0x%02x\n" 3201 " .NumDiscreteLevels = 0x%02x\n" 3202 " .padding = 0x%02x\n" 3203 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3204 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3205 " .SsFmin = 0x%04x\n" 3206 " .Padding_16 = 0x%04x\n", 3207 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode, 3208 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete, 3209 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels, 3210 pptable->DpmDescriptor[PPCLK_FCLK].Padding, 3211 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m, 3212 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b, 3213 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a, 3214 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b, 3215 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c, 3216 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin, 3217 pptable->DpmDescriptor[PPCLK_FCLK].Padding16); 3218 3219 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n" 3220 " .VoltageMode = 0x%02x\n" 3221 " .SnapToDiscrete = 0x%02x\n" 3222 " .NumDiscreteLevels = 0x%02x\n" 3223 " .padding = 0x%02x\n" 3224 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3225 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3226 " .SsFmin = 0x%04x\n" 3227 " .Padding_16 = 0x%04x\n", 3228 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode, 3229 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete, 3230 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels, 3231 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding, 3232 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m, 3233 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b, 3234 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a, 3235 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b, 3236 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c, 3237 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin, 3238 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16); 3239 3240 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n" 3241 " .VoltageMode = 0x%02x\n" 3242 " .SnapToDiscrete = 0x%02x\n" 3243 " .NumDiscreteLevels = 0x%02x\n" 3244 " .padding = 0x%02x\n" 3245 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3246 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3247 " .SsFmin = 0x%04x\n" 3248 " .Padding_16 = 0x%04x\n", 3249 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode, 3250 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete, 3251 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels, 3252 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding, 3253 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m, 3254 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b, 3255 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a, 3256 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b, 3257 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c, 3258 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin, 3259 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16); 3260 3261 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n" 3262 " .VoltageMode = 0x%02x\n" 3263 " .SnapToDiscrete = 0x%02x\n" 3264 " .NumDiscreteLevels = 0x%02x\n" 3265 " .padding = 0x%02x\n" 3266 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3267 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3268 " .SsFmin = 0x%04x\n" 3269 " .Padding_16 = 0x%04x\n", 3270 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode, 3271 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete, 3272 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels, 3273 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding, 3274 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m, 3275 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b, 3276 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a, 3277 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b, 3278 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c, 3279 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin, 3280 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16); 3281 3282 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n" 3283 " .VoltageMode = 0x%02x\n" 3284 " .SnapToDiscrete = 0x%02x\n" 3285 " .NumDiscreteLevels = 0x%02x\n" 3286 " .padding = 0x%02x\n" 3287 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3288 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3289 " .SsFmin = 0x%04x\n" 3290 " .Padding_16 = 0x%04x\n", 3291 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode, 3292 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete, 3293 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels, 3294 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding, 3295 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m, 3296 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b, 3297 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a, 3298 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b, 3299 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c, 3300 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin, 3301 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16); 3302 3303 dev_info(smu->adev->dev, "FreqTableGfx\n"); 3304 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) 3305 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]); 3306 3307 dev_info(smu->adev->dev, "FreqTableVclk\n"); 3308 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++) 3309 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]); 3310 3311 dev_info(smu->adev->dev, "FreqTableDclk\n"); 3312 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++) 3313 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]); 3314 3315 dev_info(smu->adev->dev, "FreqTableSocclk\n"); 3316 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) 3317 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]); 3318 3319 dev_info(smu->adev->dev, "FreqTableUclk\n"); 3320 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 3321 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]); 3322 3323 dev_info(smu->adev->dev, "FreqTableFclk\n"); 3324 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) 3325 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]); 3326 3327 dev_info(smu->adev->dev, "DcModeMaxFreq\n"); 3328 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]); 3329 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]); 3330 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]); 3331 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]); 3332 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]); 3333 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]); 3334 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]); 3335 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]); 3336 3337 dev_info(smu->adev->dev, "FreqTableUclkDiv\n"); 3338 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 3339 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]); 3340 3341 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq); 3342 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding); 3343 3344 dev_info(smu->adev->dev, "Mp0clkFreq\n"); 3345 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 3346 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]); 3347 3348 dev_info(smu->adev->dev, "Mp0DpmVoltage\n"); 3349 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 3350 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]); 3351 3352 dev_info(smu->adev->dev, "MemVddciVoltage\n"); 3353 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 3354 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]); 3355 3356 dev_info(smu->adev->dev, "MemMvddVoltage\n"); 3357 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 3358 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]); 3359 3360 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry); 3361 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit); 3362 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle); 3363 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource); 3364 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding); 3365 3366 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask); 3367 3368 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask); 3369 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask); 3370 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]); 3371 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow); 3372 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]); 3373 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]); 3374 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]); 3375 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]); 3376 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt); 3377 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt); 3378 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt); 3379 3380 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage); 3381 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime); 3382 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime); 3383 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum); 3384 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis); 3385 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout); 3386 3387 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]); 3388 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]); 3389 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]); 3390 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]); 3391 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]); 3392 3393 dev_info(smu->adev->dev, "FlopsPerByteTable\n"); 3394 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++) 3395 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]); 3396 3397 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv); 3398 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]); 3399 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]); 3400 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]); 3401 3402 dev_info(smu->adev->dev, "UclkDpmPstates\n"); 3403 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 3404 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]); 3405 3406 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n"); 3407 dev_info(smu->adev->dev, " .Fmin = 0x%x\n", 3408 pptable->UclkDpmSrcFreqRange.Fmin); 3409 dev_info(smu->adev->dev, " .Fmax = 0x%x\n", 3410 pptable->UclkDpmSrcFreqRange.Fmax); 3411 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n"); 3412 dev_info(smu->adev->dev, " .Fmin = 0x%x\n", 3413 pptable->UclkDpmTargFreqRange.Fmin); 3414 dev_info(smu->adev->dev, " .Fmax = 0x%x\n", 3415 pptable->UclkDpmTargFreqRange.Fmax); 3416 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq); 3417 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding); 3418 3419 dev_info(smu->adev->dev, "PcieGenSpeed\n"); 3420 for (i = 0; i < NUM_LINK_LEVELS; i++) 3421 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]); 3422 3423 dev_info(smu->adev->dev, "PcieLaneCount\n"); 3424 for (i = 0; i < NUM_LINK_LEVELS; i++) 3425 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]); 3426 3427 dev_info(smu->adev->dev, "LclkFreq\n"); 3428 for (i = 0; i < NUM_LINK_LEVELS; i++) 3429 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]); 3430 3431 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp); 3432 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp); 3433 3434 dev_info(smu->adev->dev, "FanGain\n"); 3435 for (i = 0; i < TEMP_COUNT; i++) 3436 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]); 3437 3438 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin); 3439 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm); 3440 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm); 3441 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm); 3442 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm); 3443 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature); 3444 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk); 3445 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16); 3446 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect); 3447 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding); 3448 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable); 3449 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev); 3450 3451 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta); 3452 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta); 3453 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta); 3454 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved); 3455 3456 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]); 3457 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]); 3458 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect); 3459 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs); 3460 3461 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", 3462 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a, 3463 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b, 3464 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c); 3465 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", 3466 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a, 3467 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b, 3468 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c); 3469 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n", 3470 pptable->dBtcGbGfxPll.a, 3471 pptable->dBtcGbGfxPll.b, 3472 pptable->dBtcGbGfxPll.c); 3473 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n", 3474 pptable->dBtcGbGfxDfll.a, 3475 pptable->dBtcGbGfxDfll.b, 3476 pptable->dBtcGbGfxDfll.c); 3477 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n", 3478 pptable->dBtcGbSoc.a, 3479 pptable->dBtcGbSoc.b, 3480 pptable->dBtcGbSoc.c); 3481 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n", 3482 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m, 3483 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b); 3484 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n", 3485 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m, 3486 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b); 3487 3488 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n"); 3489 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) { 3490 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n", 3491 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]); 3492 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n", 3493 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]); 3494 } 3495 3496 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", 3497 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a, 3498 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b, 3499 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c); 3500 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", 3501 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a, 3502 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b, 3503 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c); 3504 3505 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]); 3506 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]); 3507 3508 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]); 3509 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]); 3510 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]); 3511 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]); 3512 3513 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]); 3514 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]); 3515 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]); 3516 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]); 3517 3518 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]); 3519 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]); 3520 3521 dev_info(smu->adev->dev, "XgmiDpmPstates\n"); 3522 for (i = 0; i < NUM_XGMI_LEVELS; i++) 3523 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]); 3524 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]); 3525 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]); 3526 3527 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides); 3528 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n", 3529 pptable->ReservedEquation0.a, 3530 pptable->ReservedEquation0.b, 3531 pptable->ReservedEquation0.c); 3532 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n", 3533 pptable->ReservedEquation1.a, 3534 pptable->ReservedEquation1.b, 3535 pptable->ReservedEquation1.c); 3536 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n", 3537 pptable->ReservedEquation2.a, 3538 pptable->ReservedEquation2.b, 3539 pptable->ReservedEquation2.c); 3540 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n", 3541 pptable->ReservedEquation3.a, 3542 pptable->ReservedEquation3.b, 3543 pptable->ReservedEquation3.c); 3544 3545 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]); 3546 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]); 3547 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]); 3548 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]); 3549 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]); 3550 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]); 3551 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]); 3552 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]); 3553 3554 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]); 3555 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]); 3556 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]); 3557 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]); 3558 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]); 3559 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]); 3560 3561 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) { 3562 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i); 3563 dev_info(smu->adev->dev, " .Enabled = 0x%x\n", 3564 pptable->I2cControllers[i].Enabled); 3565 dev_info(smu->adev->dev, " .Speed = 0x%x\n", 3566 pptable->I2cControllers[i].Speed); 3567 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n", 3568 pptable->I2cControllers[i].SlaveAddress); 3569 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n", 3570 pptable->I2cControllers[i].ControllerPort); 3571 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n", 3572 pptable->I2cControllers[i].ControllerName); 3573 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n", 3574 pptable->I2cControllers[i].ThermalThrotter); 3575 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n", 3576 pptable->I2cControllers[i].I2cProtocol); 3577 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n", 3578 pptable->I2cControllers[i].PaddingConfig); 3579 } 3580 3581 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl); 3582 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda); 3583 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr); 3584 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]); 3585 3586 dev_info(smu->adev->dev, "Board Parameters:\n"); 3587 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping); 3588 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping); 3589 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping); 3590 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping); 3591 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask); 3592 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask); 3593 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask); 3594 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask); 3595 3596 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent); 3597 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset); 3598 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx); 3599 3600 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent); 3601 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset); 3602 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc); 3603 3604 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent); 3605 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset); 3606 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0); 3607 3608 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent); 3609 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset); 3610 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1); 3611 3612 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio); 3613 3614 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio); 3615 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity); 3616 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio); 3617 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity); 3618 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio); 3619 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity); 3620 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio); 3621 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity); 3622 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0); 3623 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1); 3624 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2); 3625 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask); 3626 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie); 3627 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError); 3628 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]); 3629 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]); 3630 3631 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled); 3632 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent); 3633 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq); 3634 3635 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled); 3636 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent); 3637 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq); 3638 3639 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding); 3640 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq); 3641 3642 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled); 3643 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent); 3644 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq); 3645 3646 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled); 3647 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth); 3648 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]); 3649 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]); 3650 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]); 3651 3652 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower); 3653 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding); 3654 3655 dev_info(smu->adev->dev, "XgmiLinkSpeed\n"); 3656 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3657 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]); 3658 dev_info(smu->adev->dev, "XgmiLinkWidth\n"); 3659 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3660 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]); 3661 dev_info(smu->adev->dev, "XgmiFclkFreq\n"); 3662 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3663 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]); 3664 dev_info(smu->adev->dev, "XgmiSocVoltage\n"); 3665 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3666 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]); 3667 3668 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled); 3669 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled); 3670 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]); 3671 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]); 3672 3673 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]); 3674 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]); 3675 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]); 3676 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]); 3677 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]); 3678 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]); 3679 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]); 3680 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]); 3681 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]); 3682 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]); 3683 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]); 3684 3685 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]); 3686 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]); 3687 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]); 3688 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]); 3689 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]); 3690 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]); 3691 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]); 3692 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]); 3693 } 3694 3695 static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap, 3696 struct i2c_msg *msg, int num_msgs) 3697 { 3698 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap); 3699 struct amdgpu_device *adev = smu_i2c->adev; 3700 struct smu_context *smu = adev->powerplay.pp_handle; 3701 struct smu_table_context *smu_table = &smu->smu_table; 3702 struct smu_table *table = &smu_table->driver_table; 3703 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 3704 int i, j, r, c; 3705 u16 dir; 3706 3707 if (!adev->pm.dpm_enabled) 3708 return -EBUSY; 3709 3710 req = kzalloc(sizeof(*req), GFP_KERNEL); 3711 if (!req) 3712 return -ENOMEM; 3713 3714 req->I2CcontrollerPort = smu_i2c->port; 3715 req->I2CSpeed = I2C_SPEED_FAST_400K; 3716 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 3717 dir = msg[0].flags & I2C_M_RD; 3718 3719 for (c = i = 0; i < num_msgs; i++) { 3720 for (j = 0; j < msg[i].len; j++, c++) { 3721 SwI2cCmd_t *cmd = &req->SwI2cCmds[c]; 3722 3723 if (!(msg[i].flags & I2C_M_RD)) { 3724 /* write */ 3725 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK; 3726 cmd->ReadWriteData = msg[i].buf[j]; 3727 } 3728 3729 if ((dir ^ msg[i].flags) & I2C_M_RD) { 3730 /* The direction changes. 3731 */ 3732 dir = msg[i].flags & I2C_M_RD; 3733 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK; 3734 } 3735 3736 req->NumCmds++; 3737 3738 /* 3739 * Insert STOP if we are at the last byte of either last 3740 * message for the transaction or the client explicitly 3741 * requires a STOP at this particular message. 3742 */ 3743 if ((j == msg[i].len - 1) && 3744 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) { 3745 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK; 3746 cmd->CmdConfig |= CMDCONFIG_STOP_MASK; 3747 } 3748 } 3749 } 3750 mutex_lock(&adev->pm.mutex); 3751 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 3752 mutex_unlock(&adev->pm.mutex); 3753 if (r) 3754 goto fail; 3755 3756 for (c = i = 0; i < num_msgs; i++) { 3757 if (!(msg[i].flags & I2C_M_RD)) { 3758 c += msg[i].len; 3759 continue; 3760 } 3761 for (j = 0; j < msg[i].len; j++, c++) { 3762 SwI2cCmd_t *cmd = &res->SwI2cCmds[c]; 3763 3764 msg[i].buf[j] = cmd->ReadWriteData; 3765 } 3766 } 3767 r = num_msgs; 3768 fail: 3769 kfree(req); 3770 return r; 3771 } 3772 3773 static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap) 3774 { 3775 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 3776 } 3777 3778 3779 static const struct i2c_algorithm sienna_cichlid_i2c_algo = { 3780 .master_xfer = sienna_cichlid_i2c_xfer, 3781 .functionality = sienna_cichlid_i2c_func, 3782 }; 3783 3784 static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = { 3785 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN, 3786 .max_read_len = MAX_SW_I2C_COMMANDS, 3787 .max_write_len = MAX_SW_I2C_COMMANDS, 3788 .max_comb_1st_msg_len = 2, 3789 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 3790 }; 3791 3792 static int sienna_cichlid_i2c_control_init(struct smu_context *smu) 3793 { 3794 struct amdgpu_device *adev = smu->adev; 3795 int res, i; 3796 3797 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 3798 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 3799 struct i2c_adapter *control = &smu_i2c->adapter; 3800 3801 smu_i2c->adev = adev; 3802 smu_i2c->port = i; 3803 mutex_init(&smu_i2c->mutex); 3804 control->owner = THIS_MODULE; 3805 control->class = I2C_CLASS_HWMON; 3806 control->dev.parent = &adev->pdev->dev; 3807 control->algo = &sienna_cichlid_i2c_algo; 3808 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i); 3809 control->quirks = &sienna_cichlid_i2c_control_quirks; 3810 i2c_set_adapdata(control, smu_i2c); 3811 3812 res = i2c_add_adapter(control); 3813 if (res) { 3814 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 3815 goto Out_err; 3816 } 3817 } 3818 /* assign the buses used for the FRU EEPROM and RAS EEPROM */ 3819 /* XXX ideally this would be something in a vbios data table */ 3820 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter; 3821 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 3822 3823 return 0; 3824 Out_err: 3825 for ( ; i >= 0; i--) { 3826 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 3827 struct i2c_adapter *control = &smu_i2c->adapter; 3828 3829 i2c_del_adapter(control); 3830 } 3831 return res; 3832 } 3833 3834 static void sienna_cichlid_i2c_control_fini(struct smu_context *smu) 3835 { 3836 struct amdgpu_device *adev = smu->adev; 3837 int i; 3838 3839 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 3840 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 3841 struct i2c_adapter *control = &smu_i2c->adapter; 3842 3843 i2c_del_adapter(control); 3844 } 3845 adev->pm.ras_eeprom_i2c_bus = NULL; 3846 adev->pm.fru_eeprom_i2c_bus = NULL; 3847 } 3848 3849 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu, 3850 void **table) 3851 { 3852 struct smu_table_context *smu_table = &smu->smu_table; 3853 struct gpu_metrics_v1_3 *gpu_metrics = 3854 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 3855 SmuMetricsExternal_t metrics_external; 3856 SmuMetrics_t *metrics = 3857 &(metrics_external.SmuMetrics); 3858 SmuMetrics_V2_t *metrics_v2 = 3859 &(metrics_external.SmuMetrics_V2); 3860 SmuMetrics_V3_t *metrics_v3 = 3861 &(metrics_external.SmuMetrics_V3); 3862 struct amdgpu_device *adev = smu->adev; 3863 bool use_metrics_v2 = false; 3864 bool use_metrics_v3 = false; 3865 uint16_t average_gfx_activity; 3866 int ret = 0; 3867 3868 switch (smu->adev->ip_versions[MP1_HWIP][0]) { 3869 case IP_VERSION(11, 0, 7): 3870 if (smu->smc_fw_version >= 0x3A4900) 3871 use_metrics_v3 = true; 3872 else if (smu->smc_fw_version >= 0x3A4300) 3873 use_metrics_v2 = true; 3874 break; 3875 case IP_VERSION(11, 0, 11): 3876 if (smu->smc_fw_version >= 0x412D00) 3877 use_metrics_v2 = true; 3878 break; 3879 case IP_VERSION(11, 0, 12): 3880 if (smu->smc_fw_version >= 0x3B2300) 3881 use_metrics_v2 = true; 3882 break; 3883 case IP_VERSION(11, 0, 13): 3884 if (smu->smc_fw_version >= 0x491100) 3885 use_metrics_v2 = true; 3886 break; 3887 default: 3888 break; 3889 } 3890 3891 ret = smu_cmn_get_metrics_table(smu, 3892 &metrics_external, 3893 true); 3894 if (ret) 3895 return ret; 3896 3897 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 3898 3899 gpu_metrics->temperature_edge = use_metrics_v3 ? metrics_v3->TemperatureEdge : 3900 use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge; 3901 gpu_metrics->temperature_hotspot = use_metrics_v3 ? metrics_v3->TemperatureHotspot : 3902 use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot; 3903 gpu_metrics->temperature_mem = use_metrics_v3 ? metrics_v3->TemperatureMem : 3904 use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem; 3905 gpu_metrics->temperature_vrgfx = use_metrics_v3 ? metrics_v3->TemperatureVrGfx : 3906 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx; 3907 gpu_metrics->temperature_vrsoc = use_metrics_v3 ? metrics_v3->TemperatureVrSoc : 3908 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc; 3909 gpu_metrics->temperature_vrmem = use_metrics_v3 ? metrics_v3->TemperatureVrMem0 : 3910 use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0; 3911 3912 gpu_metrics->average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity : 3913 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity; 3914 gpu_metrics->average_umc_activity = use_metrics_v3 ? metrics_v3->AverageUclkActivity : 3915 use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity; 3916 gpu_metrics->average_mm_activity = use_metrics_v3 ? 3917 (metrics_v3->VcnUsagePercentage0 + metrics_v3->VcnUsagePercentage1) / 2 : 3918 use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage; 3919 3920 gpu_metrics->average_socket_power = use_metrics_v3 ? metrics_v3->AverageSocketPower : 3921 use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower; 3922 gpu_metrics->energy_accumulator = use_metrics_v3 ? metrics_v3->EnergyAccumulator : 3923 use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator; 3924 3925 if (metrics->CurrGfxVoltageOffset) 3926 gpu_metrics->voltage_gfx = 3927 (155000 - 625 * metrics->CurrGfxVoltageOffset) / 100; 3928 if (metrics->CurrMemVidOffset) 3929 gpu_metrics->voltage_mem = 3930 (155000 - 625 * metrics->CurrMemVidOffset) / 100; 3931 if (metrics->CurrSocVoltageOffset) 3932 gpu_metrics->voltage_soc = 3933 (155000 - 625 * metrics->CurrSocVoltageOffset) / 100; 3934 3935 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity : 3936 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity; 3937 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD) 3938 gpu_metrics->average_gfxclk_frequency = 3939 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs : 3940 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs : 3941 metrics->AverageGfxclkFrequencyPostDs; 3942 else 3943 gpu_metrics->average_gfxclk_frequency = 3944 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs : 3945 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs : 3946 metrics->AverageGfxclkFrequencyPreDs; 3947 3948 gpu_metrics->average_uclk_frequency = 3949 use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs : 3950 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs : 3951 metrics->AverageUclkFrequencyPostDs; 3952 gpu_metrics->average_vclk0_frequency = use_metrics_v3 ? metrics_v3->AverageVclk0Frequency : 3953 use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency; 3954 gpu_metrics->average_dclk0_frequency = use_metrics_v3 ? metrics_v3->AverageDclk0Frequency : 3955 use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency; 3956 gpu_metrics->average_vclk1_frequency = use_metrics_v3 ? metrics_v3->AverageVclk1Frequency : 3957 use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency; 3958 gpu_metrics->average_dclk1_frequency = use_metrics_v3 ? metrics_v3->AverageDclk1Frequency : 3959 use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency; 3960 3961 gpu_metrics->current_gfxclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] : 3962 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK]; 3963 gpu_metrics->current_socclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] : 3964 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK]; 3965 gpu_metrics->current_uclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] : 3966 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK]; 3967 gpu_metrics->current_vclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] : 3968 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0]; 3969 gpu_metrics->current_dclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] : 3970 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0]; 3971 gpu_metrics->current_vclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] : 3972 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1]; 3973 gpu_metrics->current_dclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] : 3974 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1]; 3975 3976 gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu); 3977 gpu_metrics->indep_throttle_status = 3978 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status, 3979 sienna_cichlid_throttler_map); 3980 3981 gpu_metrics->current_fan_speed = use_metrics_v3 ? metrics_v3->CurrFanSpeed : 3982 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed; 3983 3984 if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) || 3985 ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) { 3986 gpu_metrics->pcie_link_width = use_metrics_v3 ? metrics_v3->PcieWidth : 3987 use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth; 3988 gpu_metrics->pcie_link_speed = link_speed[use_metrics_v3 ? metrics_v3->PcieRate : 3989 use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate]; 3990 } else { 3991 gpu_metrics->pcie_link_width = 3992 smu_v11_0_get_current_pcie_link_width(smu); 3993 gpu_metrics->pcie_link_speed = 3994 smu_v11_0_get_current_pcie_link_speed(smu); 3995 } 3996 3997 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 3998 3999 *table = (void *)gpu_metrics; 4000 4001 return sizeof(struct gpu_metrics_v1_3); 4002 } 4003 4004 static int sienna_cichlid_check_ecc_table_support(struct smu_context *smu) 4005 { 4006 uint32_t if_version = 0xff, smu_version = 0xff; 4007 int ret = 0; 4008 4009 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); 4010 if (ret) 4011 return -EOPNOTSUPP; 4012 4013 if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION) 4014 ret = -EOPNOTSUPP; 4015 4016 return ret; 4017 } 4018 4019 static ssize_t sienna_cichlid_get_ecc_info(struct smu_context *smu, 4020 void *table) 4021 { 4022 struct smu_table_context *smu_table = &smu->smu_table; 4023 EccInfoTable_t *ecc_table = NULL; 4024 struct ecc_info_per_ch *ecc_info_per_channel = NULL; 4025 int i, ret = 0; 4026 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table; 4027 4028 ret = sienna_cichlid_check_ecc_table_support(smu); 4029 if (ret) 4030 return ret; 4031 4032 ret = smu_cmn_update_table(smu, 4033 SMU_TABLE_ECCINFO, 4034 0, 4035 smu_table->ecc_table, 4036 false); 4037 if (ret) { 4038 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n"); 4039 return ret; 4040 } 4041 4042 ecc_table = (EccInfoTable_t *)smu_table->ecc_table; 4043 4044 for (i = 0; i < SIENNA_CICHLID_UMC_CHANNEL_NUM; i++) { 4045 ecc_info_per_channel = &(eccinfo->ecc[i]); 4046 ecc_info_per_channel->ce_count_lo_chip = 4047 ecc_table->EccInfo[i].ce_count_lo_chip; 4048 ecc_info_per_channel->ce_count_hi_chip = 4049 ecc_table->EccInfo[i].ce_count_hi_chip; 4050 ecc_info_per_channel->mca_umc_status = 4051 ecc_table->EccInfo[i].mca_umc_status; 4052 ecc_info_per_channel->mca_umc_addr = 4053 ecc_table->EccInfo[i].mca_umc_addr; 4054 } 4055 4056 return ret; 4057 } 4058 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu) 4059 { 4060 uint16_t *mgpu_fan_boost_limit_rpm; 4061 4062 GET_PPTABLE_MEMBER(MGpuFanBoostLimitRpm, &mgpu_fan_boost_limit_rpm); 4063 /* 4064 * Skip the MGpuFanBoost setting for those ASICs 4065 * which do not support it 4066 */ 4067 if (*mgpu_fan_boost_limit_rpm == 0) 4068 return 0; 4069 4070 return smu_cmn_send_smc_msg_with_param(smu, 4071 SMU_MSG_SetMGpuFanBoostLimitRpm, 4072 0, 4073 NULL); 4074 } 4075 4076 static int sienna_cichlid_gpo_control(struct smu_context *smu, 4077 bool enablement) 4078 { 4079 uint32_t smu_version; 4080 int ret = 0; 4081 4082 4083 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) { 4084 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 4085 if (ret) 4086 return ret; 4087 4088 if (enablement) { 4089 if (smu_version < 0x003a2500) { 4090 ret = smu_cmn_send_smc_msg_with_param(smu, 4091 SMU_MSG_SetGpoFeaturePMask, 4092 GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK, 4093 NULL); 4094 } else { 4095 ret = smu_cmn_send_smc_msg_with_param(smu, 4096 SMU_MSG_DisallowGpo, 4097 0, 4098 NULL); 4099 } 4100 } else { 4101 if (smu_version < 0x003a2500) { 4102 ret = smu_cmn_send_smc_msg_with_param(smu, 4103 SMU_MSG_SetGpoFeaturePMask, 4104 0, 4105 NULL); 4106 } else { 4107 ret = smu_cmn_send_smc_msg_with_param(smu, 4108 SMU_MSG_DisallowGpo, 4109 1, 4110 NULL); 4111 } 4112 } 4113 } 4114 4115 return ret; 4116 } 4117 4118 static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu) 4119 { 4120 uint32_t smu_version; 4121 int ret = 0; 4122 4123 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 4124 if (ret) 4125 return ret; 4126 4127 /* 4128 * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45 4129 * onwards PMFWs. 4130 */ 4131 if (smu_version < 0x003A2D00) 4132 return 0; 4133 4134 return smu_cmn_send_smc_msg_with_param(smu, 4135 SMU_MSG_Enable2ndUSB20Port, 4136 smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ? 4137 1 : 0, 4138 NULL); 4139 } 4140 4141 static int sienna_cichlid_system_features_control(struct smu_context *smu, 4142 bool en) 4143 { 4144 int ret = 0; 4145 4146 if (en) { 4147 ret = sienna_cichlid_notify_2nd_usb20_port(smu); 4148 if (ret) 4149 return ret; 4150 } 4151 4152 return smu_v11_0_system_features_control(smu, en); 4153 } 4154 4155 static int sienna_cichlid_set_mp1_state(struct smu_context *smu, 4156 enum pp_mp1_state mp1_state) 4157 { 4158 int ret; 4159 4160 switch (mp1_state) { 4161 case PP_MP1_STATE_UNLOAD: 4162 ret = smu_cmn_set_mp1_state(smu, mp1_state); 4163 break; 4164 default: 4165 /* Ignore others */ 4166 ret = 0; 4167 } 4168 4169 return ret; 4170 } 4171 4172 static void sienna_cichlid_stb_init(struct smu_context *smu) 4173 { 4174 struct amdgpu_device *adev = smu->adev; 4175 uint32_t reg; 4176 4177 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_START); 4178 smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE); 4179 4180 /* STB is disabled */ 4181 if (!smu->stb_context.enabled) 4182 return; 4183 4184 spin_lock_init(&smu->stb_context.lock); 4185 4186 /* STB buffer size in bytes as function of FIFO depth */ 4187 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_FIFO); 4188 smu->stb_context.stb_buf_size = 1 << REG_GET_FIELD(reg, MP1_PMI_3_FIFO, DEPTH); 4189 smu->stb_context.stb_buf_size *= SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES; 4190 4191 dev_info(smu->adev->dev, "STB initialized to %d entries", 4192 smu->stb_context.stb_buf_size / SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES); 4193 4194 } 4195 4196 static int sienna_cichlid_get_default_config_table_settings(struct smu_context *smu, 4197 struct config_table_setting *table) 4198 { 4199 struct amdgpu_device *adev = smu->adev; 4200 4201 if (!table) 4202 return -EINVAL; 4203 4204 table->gfxclk_average_tau = 10; 4205 table->socclk_average_tau = 10; 4206 table->fclk_average_tau = 10; 4207 table->uclk_average_tau = 10; 4208 table->gfx_activity_average_tau = 10; 4209 table->mem_activity_average_tau = 10; 4210 table->socket_power_average_tau = 100; 4211 if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) 4212 table->apu_socket_power_average_tau = 100; 4213 4214 return 0; 4215 } 4216 4217 static int sienna_cichlid_set_config_table(struct smu_context *smu, 4218 struct config_table_setting *table) 4219 { 4220 DriverSmuConfigExternal_t driver_smu_config_table; 4221 4222 if (!table) 4223 return -EINVAL; 4224 4225 memset(&driver_smu_config_table, 4226 0, 4227 sizeof(driver_smu_config_table)); 4228 driver_smu_config_table.DriverSmuConfig.GfxclkAverageLpfTau = 4229 table->gfxclk_average_tau; 4230 driver_smu_config_table.DriverSmuConfig.FclkAverageLpfTau = 4231 table->fclk_average_tau; 4232 driver_smu_config_table.DriverSmuConfig.UclkAverageLpfTau = 4233 table->uclk_average_tau; 4234 driver_smu_config_table.DriverSmuConfig.GfxActivityLpfTau = 4235 table->gfx_activity_average_tau; 4236 driver_smu_config_table.DriverSmuConfig.UclkActivityLpfTau = 4237 table->mem_activity_average_tau; 4238 driver_smu_config_table.DriverSmuConfig.SocketPowerLpfTau = 4239 table->socket_power_average_tau; 4240 4241 return smu_cmn_update_table(smu, 4242 SMU_TABLE_DRIVER_SMU_CONFIG, 4243 0, 4244 (void *)&driver_smu_config_table, 4245 true); 4246 } 4247 4248 static int sienna_cichlid_stb_get_data_direct(struct smu_context *smu, 4249 void *buf, 4250 uint32_t size) 4251 { 4252 uint32_t *p = buf; 4253 struct amdgpu_device *adev = smu->adev; 4254 4255 /* No need to disable interrupts for now as we don't lock it yet from ISR */ 4256 spin_lock(&smu->stb_context.lock); 4257 4258 /* 4259 * Read the STB FIFO in units of 32bit since this is the accessor window 4260 * (register width) we have. 4261 */ 4262 buf = ((char *) buf) + size; 4263 while ((void *)p < buf) 4264 *p++ = cpu_to_le32(RREG32_PCIE(MP1_Public | smnMP1_PMI_3)); 4265 4266 spin_unlock(&smu->stb_context.lock); 4267 4268 return 0; 4269 } 4270 4271 static bool sienna_cichlid_is_mode2_reset_supported(struct smu_context *smu) 4272 { 4273 return true; 4274 } 4275 4276 static int sienna_cichlid_mode2_reset(struct smu_context *smu) 4277 { 4278 u32 smu_version; 4279 int ret = 0, index; 4280 struct amdgpu_device *adev = smu->adev; 4281 int timeout = 100; 4282 4283 smu_cmn_get_smc_version(smu, NULL, &smu_version); 4284 4285 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 4286 SMU_MSG_DriverMode2Reset); 4287 4288 mutex_lock(&smu->message_lock); 4289 4290 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, 4291 SMU_RESET_MODE_2); 4292 4293 ret = smu_cmn_wait_for_response(smu); 4294 while (ret != 0 && timeout) { 4295 ret = smu_cmn_wait_for_response(smu); 4296 /* Wait a bit more time for getting ACK */ 4297 if (ret != 0) { 4298 --timeout; 4299 usleep_range(500, 1000); 4300 continue; 4301 } else { 4302 break; 4303 } 4304 } 4305 4306 if (!timeout) { 4307 dev_err(adev->dev, 4308 "failed to send mode2 message \tparam: 0x%08x response %#x\n", 4309 SMU_RESET_MODE_2, ret); 4310 goto out; 4311 } 4312 4313 dev_info(smu->adev->dev, "restore config space...\n"); 4314 /* Restore the config space saved during init */ 4315 amdgpu_device_load_pci_state(adev->pdev); 4316 out: 4317 mutex_unlock(&smu->message_lock); 4318 4319 return ret; 4320 } 4321 4322 static const struct pptable_funcs sienna_cichlid_ppt_funcs = { 4323 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask, 4324 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table, 4325 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable, 4326 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable, 4327 .i2c_init = sienna_cichlid_i2c_control_init, 4328 .i2c_fini = sienna_cichlid_i2c_control_fini, 4329 .print_clk_levels = sienna_cichlid_print_clk_levels, 4330 .force_clk_levels = sienna_cichlid_force_clk_levels, 4331 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk, 4332 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed, 4333 .display_config_changed = sienna_cichlid_display_config_changed, 4334 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config, 4335 .is_dpm_running = sienna_cichlid_is_dpm_running, 4336 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm, 4337 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm, 4338 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode, 4339 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode, 4340 .set_watermarks_table = sienna_cichlid_set_watermarks_table, 4341 .read_sensor = sienna_cichlid_read_sensor, 4342 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states, 4343 .set_performance_level = smu_v11_0_set_performance_level, 4344 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range, 4345 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch, 4346 .get_power_limit = sienna_cichlid_get_power_limit, 4347 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters, 4348 .dump_pptable = sienna_cichlid_dump_pptable, 4349 .init_microcode = smu_v11_0_init_microcode, 4350 .load_microcode = smu_v11_0_load_microcode, 4351 .fini_microcode = smu_v11_0_fini_microcode, 4352 .init_smc_tables = sienna_cichlid_init_smc_tables, 4353 .fini_smc_tables = smu_v11_0_fini_smc_tables, 4354 .init_power = smu_v11_0_init_power, 4355 .fini_power = smu_v11_0_fini_power, 4356 .check_fw_status = smu_v11_0_check_fw_status, 4357 .setup_pptable = sienna_cichlid_setup_pptable, 4358 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, 4359 .check_fw_version = smu_v11_0_check_fw_version, 4360 .write_pptable = smu_cmn_write_pptable, 4361 .set_driver_table_location = smu_v11_0_set_driver_table_location, 4362 .set_tool_table_location = smu_v11_0_set_tool_table_location, 4363 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 4364 .system_features_control = sienna_cichlid_system_features_control, 4365 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 4366 .send_smc_msg = smu_cmn_send_smc_msg, 4367 .init_display_count = NULL, 4368 .set_allowed_mask = smu_v11_0_set_allowed_mask, 4369 .get_enabled_mask = smu_cmn_get_enabled_mask, 4370 .feature_is_enabled = smu_cmn_feature_is_enabled, 4371 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 4372 .notify_display_change = NULL, 4373 .set_power_limit = smu_v11_0_set_power_limit, 4374 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks, 4375 .enable_thermal_alert = smu_v11_0_enable_thermal_alert, 4376 .disable_thermal_alert = smu_v11_0_disable_thermal_alert, 4377 .set_min_dcef_deep_sleep = NULL, 4378 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request, 4379 .get_fan_control_mode = smu_v11_0_get_fan_control_mode, 4380 .set_fan_control_mode = smu_v11_0_set_fan_control_mode, 4381 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm, 4382 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm, 4383 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate, 4384 .gfx_off_control = smu_v11_0_gfx_off_control, 4385 .register_irq_handler = smu_v11_0_register_irq_handler, 4386 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme, 4387 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc, 4388 .baco_is_support = smu_v11_0_baco_is_support, 4389 .baco_get_state = smu_v11_0_baco_get_state, 4390 .baco_set_state = smu_v11_0_baco_set_state, 4391 .baco_enter = sienna_cichlid_baco_enter, 4392 .baco_exit = sienna_cichlid_baco_exit, 4393 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported, 4394 .mode1_reset = smu_v11_0_mode1_reset, 4395 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq, 4396 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, 4397 .set_default_od_settings = sienna_cichlid_set_default_od_settings, 4398 .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table, 4399 .restore_user_od_settings = smu_v11_0_restore_user_od_settings, 4400 .run_btc = sienna_cichlid_run_btc, 4401 .set_power_source = smu_v11_0_set_power_source, 4402 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 4403 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 4404 .get_gpu_metrics = sienna_cichlid_get_gpu_metrics, 4405 .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost, 4406 .gfx_ulv_control = smu_v11_0_gfx_ulv_control, 4407 .deep_sleep_control = smu_v11_0_deep_sleep_control, 4408 .get_fan_parameters = sienna_cichlid_get_fan_parameters, 4409 .interrupt_work = smu_v11_0_interrupt_work, 4410 .gpo_control = sienna_cichlid_gpo_control, 4411 .set_mp1_state = sienna_cichlid_set_mp1_state, 4412 .stb_collect_info = sienna_cichlid_stb_get_data_direct, 4413 .get_ecc_info = sienna_cichlid_get_ecc_info, 4414 .get_default_config_table_settings = sienna_cichlid_get_default_config_table_settings, 4415 .set_config_table = sienna_cichlid_set_config_table, 4416 .get_unique_id = sienna_cichlid_get_unique_id, 4417 .mode2_reset_is_support = sienna_cichlid_is_mode2_reset_supported, 4418 .mode2_reset = sienna_cichlid_mode2_reset, 4419 }; 4420 4421 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu) 4422 { 4423 smu->ppt_funcs = &sienna_cichlid_ppt_funcs; 4424 smu->message_map = sienna_cichlid_message_map; 4425 smu->clock_map = sienna_cichlid_clk_map; 4426 smu->feature_map = sienna_cichlid_feature_mask_map; 4427 smu->table_map = sienna_cichlid_table_map; 4428 smu->pwr_src_map = sienna_cichlid_pwr_src_map; 4429 smu->workload_map = sienna_cichlid_workload_map; 4430 smu_v11_0_set_smu_mailbox_registers(smu); 4431 } 4432