1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include <linux/pci.h> 28 #include <linux/i2c.h> 29 #include "amdgpu.h" 30 #include "amdgpu_smu.h" 31 #include "atomfirmware.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "amdgpu_atombios.h" 34 #include "smu_v11_0.h" 35 #include "smu11_driver_if_sienna_cichlid.h" 36 #include "soc15_common.h" 37 #include "atom.h" 38 #include "sienna_cichlid_ppt.h" 39 #include "smu_v11_0_7_pptable.h" 40 #include "smu_v11_0_7_ppsmc.h" 41 #include "nbio/nbio_2_3_offset.h" 42 #include "nbio/nbio_2_3_sh_mask.h" 43 #include "thm/thm_11_0_2_offset.h" 44 #include "thm/thm_11_0_2_sh_mask.h" 45 #include "mp/mp_11_0_offset.h" 46 #include "mp/mp_11_0_sh_mask.h" 47 48 #include "asic_reg/mp/mp_11_0_sh_mask.h" 49 #include "smu_cmn.h" 50 51 /* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56 #undef pr_err 57 #undef pr_warn 58 #undef pr_info 59 #undef pr_debug 60 61 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 62 63 #define FEATURE_MASK(feature) (1ULL << feature) 64 #define SMC_DPM_FEATURE ( \ 65 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \ 66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \ 72 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)) 73 74 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15 75 76 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = { 77 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 78 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 79 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 80 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0), 81 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), 82 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 83 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 84 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1), 85 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1), 86 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1), 87 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1), 88 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1), 89 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1), 90 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 91 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 92 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0), 93 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0), 94 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 95 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 96 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0), 97 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 98 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 99 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 100 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), 101 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0), 102 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0), 103 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1), 104 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 105 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), 106 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), 107 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 108 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0), 109 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0), 110 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0), 111 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0), 112 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0), 113 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0), 114 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0), 115 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0), 116 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1), 117 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 118 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 119 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 120 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1), 121 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0), 122 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 123 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 124 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 125 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 126 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0), 127 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0), 128 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0), 129 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0), 130 MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0), 131 MSG_MAP(DisallowGpo, PPSMC_MSG_DisallowGpo, 0), 132 MSG_MAP(Enable2ndUSB20Port, PPSMC_MSG_Enable2ndUSB20Port, 0), 133 }; 134 135 static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = { 136 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 137 CLK_MAP(SCLK, PPCLK_GFXCLK), 138 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 139 CLK_MAP(FCLK, PPCLK_FCLK), 140 CLK_MAP(UCLK, PPCLK_UCLK), 141 CLK_MAP(MCLK, PPCLK_UCLK), 142 CLK_MAP(DCLK, PPCLK_DCLK_0), 143 CLK_MAP(DCLK1, PPCLK_DCLK_1), 144 CLK_MAP(VCLK, PPCLK_VCLK_0), 145 CLK_MAP(VCLK1, PPCLK_VCLK_1), 146 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK), 147 CLK_MAP(DISPCLK, PPCLK_DISPCLK), 148 CLK_MAP(PIXCLK, PPCLK_PIXCLK), 149 CLK_MAP(PHYCLK, PPCLK_PHYCLK), 150 }; 151 152 static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = { 153 FEA_MAP(DPM_PREFETCHER), 154 FEA_MAP(DPM_GFXCLK), 155 FEA_MAP(DPM_GFX_GPO), 156 FEA_MAP(DPM_UCLK), 157 FEA_MAP(DPM_FCLK), 158 FEA_MAP(DPM_SOCCLK), 159 FEA_MAP(DPM_MP0CLK), 160 FEA_MAP(DPM_LINK), 161 FEA_MAP(DPM_DCEFCLK), 162 FEA_MAP(DPM_XGMI), 163 FEA_MAP(MEM_VDDCI_SCALING), 164 FEA_MAP(MEM_MVDD_SCALING), 165 FEA_MAP(DS_GFXCLK), 166 FEA_MAP(DS_SOCCLK), 167 FEA_MAP(DS_FCLK), 168 FEA_MAP(DS_LCLK), 169 FEA_MAP(DS_DCEFCLK), 170 FEA_MAP(DS_UCLK), 171 FEA_MAP(GFX_ULV), 172 FEA_MAP(FW_DSTATE), 173 FEA_MAP(GFXOFF), 174 FEA_MAP(BACO), 175 FEA_MAP(MM_DPM_PG), 176 FEA_MAP(RSMU_SMN_CG), 177 FEA_MAP(PPT), 178 FEA_MAP(TDC), 179 FEA_MAP(APCC_PLUS), 180 FEA_MAP(GTHR), 181 FEA_MAP(ACDC), 182 FEA_MAP(VR0HOT), 183 FEA_MAP(VR1HOT), 184 FEA_MAP(FW_CTF), 185 FEA_MAP(FAN_CONTROL), 186 FEA_MAP(THERMAL), 187 FEA_MAP(GFX_DCS), 188 FEA_MAP(RM), 189 FEA_MAP(LED_DISPLAY), 190 FEA_MAP(GFX_SS), 191 FEA_MAP(OUT_OF_BAND_MONITOR), 192 FEA_MAP(TEMP_DEPENDENT_VMIN), 193 FEA_MAP(MMHUB_PG), 194 FEA_MAP(ATHUB_PG), 195 FEA_MAP(APCC_DFLL), 196 }; 197 198 static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = { 199 TAB_MAP(PPTABLE), 200 TAB_MAP(WATERMARKS), 201 TAB_MAP(AVFS_PSM_DEBUG), 202 TAB_MAP(AVFS_FUSE_OVERRIDE), 203 TAB_MAP(PMSTATUSLOG), 204 TAB_MAP(SMU_METRICS), 205 TAB_MAP(DRIVER_SMU_CONFIG), 206 TAB_MAP(ACTIVITY_MONITOR_COEFF), 207 TAB_MAP(OVERDRIVE), 208 TAB_MAP(I2C_COMMANDS), 209 TAB_MAP(PACE), 210 }; 211 212 static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { 213 PWR_MAP(AC), 214 PWR_MAP(DC), 215 }; 216 217 static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 218 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), 219 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 220 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 221 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 222 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 223 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 224 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 225 }; 226 227 static int 228 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, 229 uint32_t *feature_mask, uint32_t num) 230 { 231 struct amdgpu_device *adev = smu->adev; 232 233 if (num > 2) 234 return -EINVAL; 235 236 memset(feature_mask, 0, sizeof(uint32_t) * num); 237 238 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) 239 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT) 240 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) 241 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) 242 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) 243 | FEATURE_MASK(FEATURE_DS_FCLK_BIT) 244 | FEATURE_MASK(FEATURE_DS_UCLK_BIT) 245 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) 246 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT) 247 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) 248 | FEATURE_MASK(FEATURE_GFX_SS_BIT) 249 | FEATURE_MASK(FEATURE_VR0HOT_BIT) 250 | FEATURE_MASK(FEATURE_PPT_BIT) 251 | FEATURE_MASK(FEATURE_TDC_BIT) 252 | FEATURE_MASK(FEATURE_BACO_BIT) 253 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) 254 | FEATURE_MASK(FEATURE_FW_CTF_BIT) 255 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) 256 | FEATURE_MASK(FEATURE_THERMAL_BIT) 257 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT); 258 259 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { 260 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 261 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT); 262 } 263 264 if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) && 265 (adev->asic_type > CHIP_SIENNA_CICHLID) && 266 !(adev->flags & AMD_IS_APU)) 267 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT); 268 269 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) 270 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) 271 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) 272 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); 273 274 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) 275 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); 276 277 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) 278 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); 279 280 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) 281 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 282 283 if (adev->pm.pp_feature & PP_ULV_MASK) 284 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); 285 286 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) 287 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 288 289 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 290 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); 291 292 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB) 293 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT); 294 295 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) 296 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); 297 298 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN || 299 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG) 300 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT); 301 302 if (smu->dc_controlled_by_gpio) 303 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT); 304 305 if (amdgpu_aspm == 1) 306 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT); 307 308 return 0; 309 } 310 311 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu) 312 { 313 struct smu_table_context *table_context = &smu->smu_table; 314 struct smu_11_0_7_powerplay_table *powerplay_table = 315 table_context->power_play_table; 316 struct smu_baco_context *smu_baco = &smu->smu_baco; 317 318 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC) 319 smu->dc_controlled_by_gpio = true; 320 321 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO || 322 powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO) 323 smu_baco->platform_support = true; 324 325 table_context->thermal_controller_type = 326 powerplay_table->thermal_controller_type; 327 328 /* 329 * Instead of having its own buffer space and get overdrive_table copied, 330 * smu->od_settings just points to the actual overdrive_table 331 */ 332 smu->od_settings = &powerplay_table->overdrive_table; 333 334 return 0; 335 } 336 337 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu) 338 { 339 struct smu_table_context *table_context = &smu->smu_table; 340 PPTable_t *smc_pptable = table_context->driver_pptable; 341 struct atom_smc_dpm_info_v4_9 *smc_dpm_table; 342 int index, ret; 343 344 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 345 smc_dpm_info); 346 347 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 348 (uint8_t **)&smc_dpm_table); 349 if (ret) 350 return ret; 351 352 memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers, 353 sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header)); 354 355 return 0; 356 } 357 358 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu) 359 { 360 struct smu_table_context *table_context = &smu->smu_table; 361 struct smu_11_0_7_powerplay_table *powerplay_table = 362 table_context->power_play_table; 363 364 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 365 sizeof(PPTable_t)); 366 367 return 0; 368 } 369 370 static int sienna_cichlid_setup_pptable(struct smu_context *smu) 371 { 372 int ret = 0; 373 374 ret = smu_v11_0_setup_pptable(smu); 375 if (ret) 376 return ret; 377 378 ret = sienna_cichlid_store_powerplay_table(smu); 379 if (ret) 380 return ret; 381 382 ret = sienna_cichlid_append_powerplay_table(smu); 383 if (ret) 384 return ret; 385 386 ret = sienna_cichlid_check_powerplay_table(smu); 387 if (ret) 388 return ret; 389 390 return ret; 391 } 392 393 static int sienna_cichlid_tables_init(struct smu_context *smu) 394 { 395 struct smu_table_context *smu_table = &smu->smu_table; 396 struct smu_table *tables = smu_table->tables; 397 398 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 399 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 400 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 401 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 402 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t), 403 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 404 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 405 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 406 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t), 407 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 408 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 409 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 410 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, 411 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE, 412 AMDGPU_GEM_DOMAIN_VRAM); 413 414 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL); 415 if (!smu_table->metrics_table) 416 goto err0_out; 417 smu_table->metrics_time = 0; 418 419 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_0); 420 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 421 if (!smu_table->gpu_metrics_table) 422 goto err1_out; 423 424 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 425 if (!smu_table->watermarks_table) 426 goto err2_out; 427 428 return 0; 429 430 err2_out: 431 kfree(smu_table->gpu_metrics_table); 432 err1_out: 433 kfree(smu_table->metrics_table); 434 err0_out: 435 return -ENOMEM; 436 } 437 438 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu, 439 MetricsMember_t member, 440 uint32_t *value) 441 { 442 struct smu_table_context *smu_table= &smu->smu_table; 443 SmuMetrics_t *metrics = 444 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics); 445 int ret = 0; 446 447 mutex_lock(&smu->metrics_lock); 448 449 ret = smu_cmn_get_metrics_table_locked(smu, 450 NULL, 451 false); 452 if (ret) { 453 mutex_unlock(&smu->metrics_lock); 454 return ret; 455 } 456 457 switch (member) { 458 case METRICS_CURR_GFXCLK: 459 *value = metrics->CurrClock[PPCLK_GFXCLK]; 460 break; 461 case METRICS_CURR_SOCCLK: 462 *value = metrics->CurrClock[PPCLK_SOCCLK]; 463 break; 464 case METRICS_CURR_UCLK: 465 *value = metrics->CurrClock[PPCLK_UCLK]; 466 break; 467 case METRICS_CURR_VCLK: 468 *value = metrics->CurrClock[PPCLK_VCLK_0]; 469 break; 470 case METRICS_CURR_VCLK1: 471 *value = metrics->CurrClock[PPCLK_VCLK_1]; 472 break; 473 case METRICS_CURR_DCLK: 474 *value = metrics->CurrClock[PPCLK_DCLK_0]; 475 break; 476 case METRICS_CURR_DCLK1: 477 *value = metrics->CurrClock[PPCLK_DCLK_1]; 478 break; 479 case METRICS_CURR_DCEFCLK: 480 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 481 break; 482 case METRICS_CURR_FCLK: 483 *value = metrics->CurrClock[PPCLK_FCLK]; 484 break; 485 case METRICS_AVERAGE_GFXCLK: 486 if (metrics->AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD) 487 *value = metrics->AverageGfxclkFrequencyPostDs; 488 else 489 *value = metrics->AverageGfxclkFrequencyPreDs; 490 break; 491 case METRICS_AVERAGE_FCLK: 492 *value = metrics->AverageFclkFrequencyPostDs; 493 break; 494 case METRICS_AVERAGE_UCLK: 495 *value = metrics->AverageUclkFrequencyPostDs; 496 break; 497 case METRICS_AVERAGE_GFXACTIVITY: 498 *value = metrics->AverageGfxActivity; 499 break; 500 case METRICS_AVERAGE_MEMACTIVITY: 501 *value = metrics->AverageUclkActivity; 502 break; 503 case METRICS_AVERAGE_SOCKETPOWER: 504 *value = metrics->AverageSocketPower << 8; 505 break; 506 case METRICS_TEMPERATURE_EDGE: 507 *value = metrics->TemperatureEdge * 508 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 509 break; 510 case METRICS_TEMPERATURE_HOTSPOT: 511 *value = metrics->TemperatureHotspot * 512 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 513 break; 514 case METRICS_TEMPERATURE_MEM: 515 *value = metrics->TemperatureMem * 516 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 517 break; 518 case METRICS_TEMPERATURE_VRGFX: 519 *value = metrics->TemperatureVrGfx * 520 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 521 break; 522 case METRICS_TEMPERATURE_VRSOC: 523 *value = metrics->TemperatureVrSoc * 524 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 525 break; 526 case METRICS_THROTTLER_STATUS: 527 *value = metrics->ThrottlerStatus; 528 break; 529 case METRICS_CURR_FANSPEED: 530 *value = metrics->CurrFanSpeed; 531 break; 532 default: 533 *value = UINT_MAX; 534 break; 535 } 536 537 mutex_unlock(&smu->metrics_lock); 538 539 return ret; 540 541 } 542 543 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu) 544 { 545 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 546 547 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 548 GFP_KERNEL); 549 if (!smu_dpm->dpm_context) 550 return -ENOMEM; 551 552 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 553 554 return 0; 555 } 556 557 static int sienna_cichlid_init_smc_tables(struct smu_context *smu) 558 { 559 int ret = 0; 560 561 ret = sienna_cichlid_tables_init(smu); 562 if (ret) 563 return ret; 564 565 ret = sienna_cichlid_allocate_dpm_context(smu); 566 if (ret) 567 return ret; 568 569 return smu_v11_0_init_smc_tables(smu); 570 } 571 572 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) 573 { 574 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 575 PPTable_t *driver_ppt = smu->smu_table.driver_pptable; 576 struct smu_11_0_dpm_table *dpm_table; 577 struct amdgpu_device *adev = smu->adev; 578 int ret = 0; 579 580 /* socclk dpm table setup */ 581 dpm_table = &dpm_context->dpm_tables.soc_table; 582 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 583 ret = smu_v11_0_set_single_dpm_table(smu, 584 SMU_SOCCLK, 585 dpm_table); 586 if (ret) 587 return ret; 588 dpm_table->is_fine_grained = 589 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete; 590 } else { 591 dpm_table->count = 1; 592 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 593 dpm_table->dpm_levels[0].enabled = true; 594 dpm_table->min = dpm_table->dpm_levels[0].value; 595 dpm_table->max = dpm_table->dpm_levels[0].value; 596 } 597 598 /* gfxclk dpm table setup */ 599 dpm_table = &dpm_context->dpm_tables.gfx_table; 600 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 601 ret = smu_v11_0_set_single_dpm_table(smu, 602 SMU_GFXCLK, 603 dpm_table); 604 if (ret) 605 return ret; 606 dpm_table->is_fine_grained = 607 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete; 608 } else { 609 dpm_table->count = 1; 610 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 611 dpm_table->dpm_levels[0].enabled = true; 612 dpm_table->min = dpm_table->dpm_levels[0].value; 613 dpm_table->max = dpm_table->dpm_levels[0].value; 614 } 615 616 /* uclk dpm table setup */ 617 dpm_table = &dpm_context->dpm_tables.uclk_table; 618 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 619 ret = smu_v11_0_set_single_dpm_table(smu, 620 SMU_UCLK, 621 dpm_table); 622 if (ret) 623 return ret; 624 dpm_table->is_fine_grained = 625 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete; 626 } else { 627 dpm_table->count = 1; 628 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 629 dpm_table->dpm_levels[0].enabled = true; 630 dpm_table->min = dpm_table->dpm_levels[0].value; 631 dpm_table->max = dpm_table->dpm_levels[0].value; 632 } 633 634 /* fclk dpm table setup */ 635 dpm_table = &dpm_context->dpm_tables.fclk_table; 636 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 637 ret = smu_v11_0_set_single_dpm_table(smu, 638 SMU_FCLK, 639 dpm_table); 640 if (ret) 641 return ret; 642 dpm_table->is_fine_grained = 643 !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete; 644 } else { 645 dpm_table->count = 1; 646 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 647 dpm_table->dpm_levels[0].enabled = true; 648 dpm_table->min = dpm_table->dpm_levels[0].value; 649 dpm_table->max = dpm_table->dpm_levels[0].value; 650 } 651 652 /* vclk0 dpm table setup */ 653 dpm_table = &dpm_context->dpm_tables.vclk_table; 654 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 655 ret = smu_v11_0_set_single_dpm_table(smu, 656 SMU_VCLK, 657 dpm_table); 658 if (ret) 659 return ret; 660 dpm_table->is_fine_grained = 661 !driver_ppt->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete; 662 } else { 663 dpm_table->count = 1; 664 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; 665 dpm_table->dpm_levels[0].enabled = true; 666 dpm_table->min = dpm_table->dpm_levels[0].value; 667 dpm_table->max = dpm_table->dpm_levels[0].value; 668 } 669 670 /* vclk1 dpm table setup */ 671 if (adev->vcn.num_vcn_inst > 1) { 672 dpm_table = &dpm_context->dpm_tables.vclk1_table; 673 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 674 ret = smu_v11_0_set_single_dpm_table(smu, 675 SMU_VCLK1, 676 dpm_table); 677 if (ret) 678 return ret; 679 dpm_table->is_fine_grained = 680 !driver_ppt->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete; 681 } else { 682 dpm_table->count = 1; 683 dpm_table->dpm_levels[0].value = 684 smu->smu_table.boot_values.vclk / 100; 685 dpm_table->dpm_levels[0].enabled = true; 686 dpm_table->min = dpm_table->dpm_levels[0].value; 687 dpm_table->max = dpm_table->dpm_levels[0].value; 688 } 689 } 690 691 /* dclk0 dpm table setup */ 692 dpm_table = &dpm_context->dpm_tables.dclk_table; 693 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 694 ret = smu_v11_0_set_single_dpm_table(smu, 695 SMU_DCLK, 696 dpm_table); 697 if (ret) 698 return ret; 699 dpm_table->is_fine_grained = 700 !driver_ppt->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete; 701 } else { 702 dpm_table->count = 1; 703 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; 704 dpm_table->dpm_levels[0].enabled = true; 705 dpm_table->min = dpm_table->dpm_levels[0].value; 706 dpm_table->max = dpm_table->dpm_levels[0].value; 707 } 708 709 /* dclk1 dpm table setup */ 710 if (adev->vcn.num_vcn_inst > 1) { 711 dpm_table = &dpm_context->dpm_tables.dclk1_table; 712 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 713 ret = smu_v11_0_set_single_dpm_table(smu, 714 SMU_DCLK1, 715 dpm_table); 716 if (ret) 717 return ret; 718 dpm_table->is_fine_grained = 719 !driver_ppt->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete; 720 } else { 721 dpm_table->count = 1; 722 dpm_table->dpm_levels[0].value = 723 smu->smu_table.boot_values.dclk / 100; 724 dpm_table->dpm_levels[0].enabled = true; 725 dpm_table->min = dpm_table->dpm_levels[0].value; 726 dpm_table->max = dpm_table->dpm_levels[0].value; 727 } 728 } 729 730 /* dcefclk dpm table setup */ 731 dpm_table = &dpm_context->dpm_tables.dcef_table; 732 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 733 ret = smu_v11_0_set_single_dpm_table(smu, 734 SMU_DCEFCLK, 735 dpm_table); 736 if (ret) 737 return ret; 738 dpm_table->is_fine_grained = 739 !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete; 740 } else { 741 dpm_table->count = 1; 742 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 743 dpm_table->dpm_levels[0].enabled = true; 744 dpm_table->min = dpm_table->dpm_levels[0].value; 745 dpm_table->max = dpm_table->dpm_levels[0].value; 746 } 747 748 /* pixelclk dpm table setup */ 749 dpm_table = &dpm_context->dpm_tables.pixel_table; 750 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 751 ret = smu_v11_0_set_single_dpm_table(smu, 752 SMU_PIXCLK, 753 dpm_table); 754 if (ret) 755 return ret; 756 dpm_table->is_fine_grained = 757 !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete; 758 } else { 759 dpm_table->count = 1; 760 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 761 dpm_table->dpm_levels[0].enabled = true; 762 dpm_table->min = dpm_table->dpm_levels[0].value; 763 dpm_table->max = dpm_table->dpm_levels[0].value; 764 } 765 766 /* displayclk dpm table setup */ 767 dpm_table = &dpm_context->dpm_tables.display_table; 768 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 769 ret = smu_v11_0_set_single_dpm_table(smu, 770 SMU_DISPCLK, 771 dpm_table); 772 if (ret) 773 return ret; 774 dpm_table->is_fine_grained = 775 !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete; 776 } else { 777 dpm_table->count = 1; 778 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 779 dpm_table->dpm_levels[0].enabled = true; 780 dpm_table->min = dpm_table->dpm_levels[0].value; 781 dpm_table->max = dpm_table->dpm_levels[0].value; 782 } 783 784 /* phyclk dpm table setup */ 785 dpm_table = &dpm_context->dpm_tables.phy_table; 786 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 787 ret = smu_v11_0_set_single_dpm_table(smu, 788 SMU_PHYCLK, 789 dpm_table); 790 if (ret) 791 return ret; 792 dpm_table->is_fine_grained = 793 !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete; 794 } else { 795 dpm_table->count = 1; 796 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 797 dpm_table->dpm_levels[0].enabled = true; 798 dpm_table->min = dpm_table->dpm_levels[0].value; 799 dpm_table->max = dpm_table->dpm_levels[0].value; 800 } 801 802 return 0; 803 } 804 805 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 806 { 807 struct amdgpu_device *adev = smu->adev; 808 int ret = 0; 809 810 if (enable) { 811 /* vcn dpm on is a prerequisite for vcn power gate messages */ 812 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 813 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL); 814 if (ret) 815 return ret; 816 if (adev->vcn.num_vcn_inst > 1) { 817 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 818 0x10000, NULL); 819 if (ret) 820 return ret; 821 } 822 } 823 } else { 824 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 825 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL); 826 if (ret) 827 return ret; 828 if (adev->vcn.num_vcn_inst > 1) { 829 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 830 0x10000, NULL); 831 if (ret) 832 return ret; 833 } 834 } 835 } 836 837 return ret; 838 } 839 840 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 841 { 842 int ret = 0; 843 844 if (enable) { 845 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 846 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); 847 if (ret) 848 return ret; 849 } 850 } else { 851 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 852 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); 853 if (ret) 854 return ret; 855 } 856 } 857 858 return ret; 859 } 860 861 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu, 862 enum smu_clk_type clk_type, 863 uint32_t *value) 864 { 865 MetricsMember_t member_type; 866 int clk_id = 0; 867 868 clk_id = smu_cmn_to_asic_specific_index(smu, 869 CMN2ASIC_MAPPING_CLK, 870 clk_type); 871 if (clk_id < 0) 872 return clk_id; 873 874 switch (clk_id) { 875 case PPCLK_GFXCLK: 876 member_type = METRICS_CURR_GFXCLK; 877 break; 878 case PPCLK_UCLK: 879 member_type = METRICS_CURR_UCLK; 880 break; 881 case PPCLK_SOCCLK: 882 member_type = METRICS_CURR_SOCCLK; 883 break; 884 case PPCLK_FCLK: 885 member_type = METRICS_CURR_FCLK; 886 break; 887 case PPCLK_VCLK_0: 888 member_type = METRICS_CURR_VCLK; 889 break; 890 case PPCLK_VCLK_1: 891 member_type = METRICS_CURR_VCLK1; 892 break; 893 case PPCLK_DCLK_0: 894 member_type = METRICS_CURR_DCLK; 895 break; 896 case PPCLK_DCLK_1: 897 member_type = METRICS_CURR_DCLK1; 898 break; 899 case PPCLK_DCEFCLK: 900 member_type = METRICS_CURR_DCEFCLK; 901 break; 902 default: 903 return -EINVAL; 904 } 905 906 return sienna_cichlid_get_smu_metrics_data(smu, 907 member_type, 908 value); 909 910 } 911 912 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) 913 { 914 PPTable_t *pptable = smu->smu_table.driver_pptable; 915 DpmDescriptor_t *dpm_desc = NULL; 916 uint32_t clk_index = 0; 917 918 clk_index = smu_cmn_to_asic_specific_index(smu, 919 CMN2ASIC_MAPPING_CLK, 920 clk_type); 921 dpm_desc = &pptable->DpmDescriptor[clk_index]; 922 923 /* 0 - Fine grained DPM, 1 - Discrete DPM */ 924 return dpm_desc->SnapToDiscrete == 0 ? true : false; 925 } 926 927 static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table, 928 enum SMU_11_0_7_ODFEATURE_CAP cap) 929 { 930 return od_table->cap[cap]; 931 } 932 933 static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table, 934 enum SMU_11_0_7_ODSETTING_ID setting, 935 uint32_t *min, uint32_t *max) 936 { 937 if (min) 938 *min = od_table->min[setting]; 939 if (max) 940 *max = od_table->max[setting]; 941 } 942 943 static int sienna_cichlid_print_clk_levels(struct smu_context *smu, 944 enum smu_clk_type clk_type, char *buf) 945 { 946 struct amdgpu_device *adev = smu->adev; 947 struct smu_table_context *table_context = &smu->smu_table; 948 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 949 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; 950 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable; 951 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings; 952 OverDriveTable_t *od_table = 953 (OverDriveTable_t *)table_context->overdrive_table; 954 int i, size = 0, ret = 0; 955 uint32_t cur_value = 0, value = 0, count = 0; 956 uint32_t freq_values[3] = {0}; 957 uint32_t mark_index = 0; 958 uint32_t gen_speed, lane_width; 959 uint32_t min_value, max_value; 960 uint32_t smu_version; 961 962 switch (clk_type) { 963 case SMU_GFXCLK: 964 case SMU_SCLK: 965 case SMU_SOCCLK: 966 case SMU_MCLK: 967 case SMU_UCLK: 968 case SMU_FCLK: 969 case SMU_DCEFCLK: 970 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value); 971 if (ret) 972 goto print_clk_out; 973 974 /* no need to disable gfxoff when retrieving the current gfxclk */ 975 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK)) 976 amdgpu_gfx_off_ctrl(adev, false); 977 978 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); 979 if (ret) 980 goto print_clk_out; 981 982 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) { 983 for (i = 0; i < count; i++) { 984 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); 985 if (ret) 986 goto print_clk_out; 987 988 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, 989 cur_value == value ? "*" : ""); 990 } 991 } else { 992 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]); 993 if (ret) 994 goto print_clk_out; 995 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]); 996 if (ret) 997 goto print_clk_out; 998 999 freq_values[1] = cur_value; 1000 mark_index = cur_value == freq_values[0] ? 0 : 1001 cur_value == freq_values[2] ? 2 : 1; 1002 1003 count = 3; 1004 if (mark_index != 1) { 1005 count = 2; 1006 freq_values[1] = freq_values[2]; 1007 } 1008 1009 for (i = 0; i < count; i++) { 1010 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i], 1011 cur_value == freq_values[i] ? "*" : ""); 1012 } 1013 1014 } 1015 break; 1016 case SMU_PCIE: 1017 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); 1018 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); 1019 for (i = 0; i < NUM_LINK_LEVELS; i++) 1020 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i, 1021 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," : 1022 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," : 1023 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," : 1024 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "", 1025 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" : 1026 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" : 1027 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" : 1028 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" : 1029 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" : 1030 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "", 1031 pptable->LclkFreq[i], 1032 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && 1033 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? 1034 "*" : ""); 1035 break; 1036 case SMU_OD_SCLK: 1037 if (!smu->od_enabled || !od_table || !od_settings) 1038 break; 1039 1040 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) 1041 break; 1042 1043 size += sprintf(buf + size, "OD_SCLK:\n"); 1044 size += sprintf(buf + size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax); 1045 break; 1046 1047 case SMU_OD_MCLK: 1048 if (!smu->od_enabled || !od_table || !od_settings) 1049 break; 1050 1051 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) 1052 break; 1053 1054 size += sprintf(buf + size, "OD_MCLK:\n"); 1055 size += sprintf(buf + size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax); 1056 break; 1057 1058 case SMU_OD_VDDGFX_OFFSET: 1059 if (!smu->od_enabled || !od_table || !od_settings) 1060 break; 1061 1062 /* 1063 * OD GFX Voltage Offset functionality is supported only by 58.41.0 1064 * and onwards SMU firmwares. 1065 */ 1066 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1067 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 1068 (smu_version < 0x003a2900)) 1069 break; 1070 1071 size += sprintf(buf + size, "OD_VDDGFX_OFFSET:\n"); 1072 size += sprintf(buf + size, "%dmV\n", od_table->VddGfxOffset); 1073 break; 1074 1075 case SMU_OD_RANGE: 1076 if (!smu->od_enabled || !od_table || !od_settings) 1077 break; 1078 1079 size = sprintf(buf, "%s:\n", "OD_RANGE"); 1080 1081 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) { 1082 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN, 1083 &min_value, NULL); 1084 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX, 1085 NULL, &max_value); 1086 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n", 1087 min_value, max_value); 1088 } 1089 1090 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) { 1091 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN, 1092 &min_value, NULL); 1093 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX, 1094 NULL, &max_value); 1095 size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n", 1096 min_value, max_value); 1097 } 1098 break; 1099 1100 default: 1101 break; 1102 } 1103 1104 print_clk_out: 1105 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK)) 1106 amdgpu_gfx_off_ctrl(adev, true); 1107 1108 return size; 1109 } 1110 1111 static int sienna_cichlid_force_clk_levels(struct smu_context *smu, 1112 enum smu_clk_type clk_type, uint32_t mask) 1113 { 1114 struct amdgpu_device *adev = smu->adev; 1115 int ret = 0, size = 0; 1116 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; 1117 1118 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1119 soft_max_level = mask ? (fls(mask) - 1) : 0; 1120 1121 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK)) 1122 amdgpu_gfx_off_ctrl(adev, false); 1123 1124 switch (clk_type) { 1125 case SMU_GFXCLK: 1126 case SMU_SCLK: 1127 case SMU_SOCCLK: 1128 case SMU_MCLK: 1129 case SMU_UCLK: 1130 case SMU_DCEFCLK: 1131 case SMU_FCLK: 1132 /* There is only 2 levels for fine grained DPM */ 1133 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) { 1134 soft_max_level = (soft_max_level >= 1 ? 1 : 0); 1135 soft_min_level = (soft_min_level >= 1 ? 1 : 0); 1136 } 1137 1138 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); 1139 if (ret) 1140 goto forec_level_out; 1141 1142 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq); 1143 if (ret) 1144 goto forec_level_out; 1145 1146 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 1147 if (ret) 1148 goto forec_level_out; 1149 break; 1150 default: 1151 break; 1152 } 1153 1154 forec_level_out: 1155 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK)) 1156 amdgpu_gfx_off_ctrl(adev, true); 1157 1158 return size; 1159 } 1160 1161 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu) 1162 { 1163 struct smu_11_0_dpm_context *dpm_context = 1164 smu->smu_dpm.dpm_context; 1165 struct smu_11_0_dpm_table *gfx_table = 1166 &dpm_context->dpm_tables.gfx_table; 1167 struct smu_11_0_dpm_table *mem_table = 1168 &dpm_context->dpm_tables.uclk_table; 1169 struct smu_11_0_dpm_table *soc_table = 1170 &dpm_context->dpm_tables.soc_table; 1171 struct smu_umd_pstate_table *pstate_table = 1172 &smu->pstate_table; 1173 1174 pstate_table->gfxclk_pstate.min = gfx_table->min; 1175 pstate_table->gfxclk_pstate.peak = gfx_table->max; 1176 if (gfx_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK) 1177 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK; 1178 1179 pstate_table->uclk_pstate.min = mem_table->min; 1180 pstate_table->uclk_pstate.peak = mem_table->max; 1181 if (mem_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK) 1182 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK; 1183 1184 pstate_table->socclk_pstate.min = soc_table->min; 1185 pstate_table->socclk_pstate.peak = soc_table->max; 1186 if (soc_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK) 1187 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK; 1188 1189 return 0; 1190 } 1191 1192 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu) 1193 { 1194 int ret = 0; 1195 uint32_t max_freq = 0; 1196 1197 /* Sienna_Cichlid do not support to change display num currently */ 1198 return 0; 1199 #if 0 1200 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL); 1201 if (ret) 1202 return ret; 1203 #endif 1204 1205 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1206 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq); 1207 if (ret) 1208 return ret; 1209 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq); 1210 if (ret) 1211 return ret; 1212 } 1213 1214 return ret; 1215 } 1216 1217 static int sienna_cichlid_display_config_changed(struct smu_context *smu) 1218 { 1219 int ret = 0; 1220 1221 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1222 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) && 1223 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 1224 #if 0 1225 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 1226 smu->display_config->num_display, 1227 NULL); 1228 #endif 1229 if (ret) 1230 return ret; 1231 } 1232 1233 return ret; 1234 } 1235 1236 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu) 1237 { 1238 int ret = 0; 1239 uint32_t feature_mask[2]; 1240 uint64_t feature_enabled; 1241 1242 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2); 1243 if (ret) 1244 return false; 1245 1246 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0]; 1247 1248 return !!(feature_enabled & SMC_DPM_FEATURE); 1249 } 1250 1251 static int sienna_cichlid_get_fan_speed_percent(struct smu_context *smu, 1252 uint32_t *speed) 1253 { 1254 int ret; 1255 u32 rpm; 1256 1257 if (!speed) 1258 return -EINVAL; 1259 1260 switch (smu_v11_0_get_fan_control_mode(smu)) { 1261 case AMD_FAN_CTRL_AUTO: 1262 ret = sienna_cichlid_get_smu_metrics_data(smu, 1263 METRICS_CURR_FANSPEED, 1264 &rpm); 1265 if (!ret && smu->fan_max_rpm) 1266 *speed = rpm * 100 / smu->fan_max_rpm; 1267 return ret; 1268 default: 1269 *speed = smu->user_dpm_profile.fan_speed_percent; 1270 return 0; 1271 } 1272 } 1273 1274 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu) 1275 { 1276 PPTable_t *pptable = smu->smu_table.driver_pptable; 1277 1278 smu->fan_max_rpm = pptable->FanMaximumRpm; 1279 1280 return 0; 1281 } 1282 1283 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf) 1284 { 1285 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 1286 DpmActivityMonitorCoeffInt_t *activity_monitor = 1287 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 1288 uint32_t i, size = 0; 1289 int16_t workload_type = 0; 1290 static const char *profile_name[] = { 1291 "BOOTUP_DEFAULT", 1292 "3D_FULL_SCREEN", 1293 "POWER_SAVING", 1294 "VIDEO", 1295 "VR", 1296 "COMPUTE", 1297 "CUSTOM"}; 1298 static const char *title[] = { 1299 "PROFILE_INDEX(NAME)", 1300 "CLOCK_TYPE(NAME)", 1301 "FPS", 1302 "MinFreqType", 1303 "MinActiveFreqType", 1304 "MinActiveFreq", 1305 "BoosterFreqType", 1306 "BoosterFreq", 1307 "PD_Data_limit_c", 1308 "PD_Data_error_coeff", 1309 "PD_Data_error_rate_coeff"}; 1310 int result = 0; 1311 1312 if (!buf) 1313 return -EINVAL; 1314 1315 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n", 1316 title[0], title[1], title[2], title[3], title[4], title[5], 1317 title[6], title[7], title[8], title[9], title[10]); 1318 1319 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1320 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1321 workload_type = smu_cmn_to_asic_specific_index(smu, 1322 CMN2ASIC_MAPPING_WORKLOAD, 1323 i); 1324 if (workload_type < 0) 1325 return -EINVAL; 1326 1327 result = smu_cmn_update_table(smu, 1328 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type, 1329 (void *)(&activity_monitor_external), false); 1330 if (result) { 1331 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1332 return result; 1333 } 1334 1335 size += sprintf(buf + size, "%2d %14s%s:\n", 1336 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1337 1338 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1339 " ", 1340 0, 1341 "GFXCLK", 1342 activity_monitor->Gfx_FPS, 1343 activity_monitor->Gfx_MinFreqStep, 1344 activity_monitor->Gfx_MinActiveFreqType, 1345 activity_monitor->Gfx_MinActiveFreq, 1346 activity_monitor->Gfx_BoosterFreqType, 1347 activity_monitor->Gfx_BoosterFreq, 1348 activity_monitor->Gfx_PD_Data_limit_c, 1349 activity_monitor->Gfx_PD_Data_error_coeff, 1350 activity_monitor->Gfx_PD_Data_error_rate_coeff); 1351 1352 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1353 " ", 1354 1, 1355 "SOCCLK", 1356 activity_monitor->Fclk_FPS, 1357 activity_monitor->Fclk_MinFreqStep, 1358 activity_monitor->Fclk_MinActiveFreqType, 1359 activity_monitor->Fclk_MinActiveFreq, 1360 activity_monitor->Fclk_BoosterFreqType, 1361 activity_monitor->Fclk_BoosterFreq, 1362 activity_monitor->Fclk_PD_Data_limit_c, 1363 activity_monitor->Fclk_PD_Data_error_coeff, 1364 activity_monitor->Fclk_PD_Data_error_rate_coeff); 1365 1366 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1367 " ", 1368 2, 1369 "MEMLK", 1370 activity_monitor->Mem_FPS, 1371 activity_monitor->Mem_MinFreqStep, 1372 activity_monitor->Mem_MinActiveFreqType, 1373 activity_monitor->Mem_MinActiveFreq, 1374 activity_monitor->Mem_BoosterFreqType, 1375 activity_monitor->Mem_BoosterFreq, 1376 activity_monitor->Mem_PD_Data_limit_c, 1377 activity_monitor->Mem_PD_Data_error_coeff, 1378 activity_monitor->Mem_PD_Data_error_rate_coeff); 1379 } 1380 1381 return size; 1382 } 1383 1384 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 1385 { 1386 1387 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 1388 DpmActivityMonitorCoeffInt_t *activity_monitor = 1389 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 1390 int workload_type, ret = 0; 1391 1392 smu->power_profile_mode = input[size]; 1393 1394 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 1395 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode); 1396 return -EINVAL; 1397 } 1398 1399 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 1400 1401 ret = smu_cmn_update_table(smu, 1402 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1403 (void *)(&activity_monitor_external), false); 1404 if (ret) { 1405 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1406 return ret; 1407 } 1408 1409 switch (input[0]) { 1410 case 0: /* Gfxclk */ 1411 activity_monitor->Gfx_FPS = input[1]; 1412 activity_monitor->Gfx_MinFreqStep = input[2]; 1413 activity_monitor->Gfx_MinActiveFreqType = input[3]; 1414 activity_monitor->Gfx_MinActiveFreq = input[4]; 1415 activity_monitor->Gfx_BoosterFreqType = input[5]; 1416 activity_monitor->Gfx_BoosterFreq = input[6]; 1417 activity_monitor->Gfx_PD_Data_limit_c = input[7]; 1418 activity_monitor->Gfx_PD_Data_error_coeff = input[8]; 1419 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9]; 1420 break; 1421 case 1: /* Socclk */ 1422 activity_monitor->Fclk_FPS = input[1]; 1423 activity_monitor->Fclk_MinFreqStep = input[2]; 1424 activity_monitor->Fclk_MinActiveFreqType = input[3]; 1425 activity_monitor->Fclk_MinActiveFreq = input[4]; 1426 activity_monitor->Fclk_BoosterFreqType = input[5]; 1427 activity_monitor->Fclk_BoosterFreq = input[6]; 1428 activity_monitor->Fclk_PD_Data_limit_c = input[7]; 1429 activity_monitor->Fclk_PD_Data_error_coeff = input[8]; 1430 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9]; 1431 break; 1432 case 2: /* Memlk */ 1433 activity_monitor->Mem_FPS = input[1]; 1434 activity_monitor->Mem_MinFreqStep = input[2]; 1435 activity_monitor->Mem_MinActiveFreqType = input[3]; 1436 activity_monitor->Mem_MinActiveFreq = input[4]; 1437 activity_monitor->Mem_BoosterFreqType = input[5]; 1438 activity_monitor->Mem_BoosterFreq = input[6]; 1439 activity_monitor->Mem_PD_Data_limit_c = input[7]; 1440 activity_monitor->Mem_PD_Data_error_coeff = input[8]; 1441 activity_monitor->Mem_PD_Data_error_rate_coeff = input[9]; 1442 break; 1443 } 1444 1445 ret = smu_cmn_update_table(smu, 1446 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1447 (void *)(&activity_monitor_external), true); 1448 if (ret) { 1449 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 1450 return ret; 1451 } 1452 } 1453 1454 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1455 workload_type = smu_cmn_to_asic_specific_index(smu, 1456 CMN2ASIC_MAPPING_WORKLOAD, 1457 smu->power_profile_mode); 1458 if (workload_type < 0) 1459 return -EINVAL; 1460 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 1461 1 << workload_type, NULL); 1462 1463 return ret; 1464 } 1465 1466 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu) 1467 { 1468 struct smu_clocks min_clocks = {0}; 1469 struct pp_display_clock_request clock_req; 1470 int ret = 0; 1471 1472 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; 1473 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; 1474 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; 1475 1476 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1477 clock_req.clock_type = amd_pp_dcef_clock; 1478 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; 1479 1480 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req); 1481 if (!ret) { 1482 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) { 1483 ret = smu_cmn_send_smc_msg_with_param(smu, 1484 SMU_MSG_SetMinDeepSleepDcefclk, 1485 min_clocks.dcef_clock_in_sr/100, 1486 NULL); 1487 if (ret) { 1488 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!"); 1489 return ret; 1490 } 1491 } 1492 } else { 1493 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!"); 1494 } 1495 } 1496 1497 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1498 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); 1499 if (ret) { 1500 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__); 1501 return ret; 1502 } 1503 } 1504 1505 return 0; 1506 } 1507 1508 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu, 1509 struct pp_smu_wm_range_sets *clock_ranges) 1510 { 1511 Watermarks_t *table = smu->smu_table.watermarks_table; 1512 int ret = 0; 1513 int i; 1514 1515 if (clock_ranges) { 1516 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 1517 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1518 return -EINVAL; 1519 1520 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1521 table->WatermarkRow[WM_DCEFCLK][i].MinClock = 1522 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1523 table->WatermarkRow[WM_DCEFCLK][i].MaxClock = 1524 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1525 table->WatermarkRow[WM_DCEFCLK][i].MinUclk = 1526 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1527 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk = 1528 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1529 1530 table->WatermarkRow[WM_DCEFCLK][i].WmSetting = 1531 clock_ranges->reader_wm_sets[i].wm_inst; 1532 } 1533 1534 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1535 table->WatermarkRow[WM_SOCCLK][i].MinClock = 1536 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1537 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1538 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1539 table->WatermarkRow[WM_SOCCLK][i].MinUclk = 1540 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1541 table->WatermarkRow[WM_SOCCLK][i].MaxUclk = 1542 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1543 1544 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1545 clock_ranges->writer_wm_sets[i].wm_inst; 1546 } 1547 1548 smu->watermarks_bitmap |= WATERMARKS_EXIST; 1549 } 1550 1551 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1552 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1553 ret = smu_cmn_write_watermarks_table(smu); 1554 if (ret) { 1555 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1556 return ret; 1557 } 1558 smu->watermarks_bitmap |= WATERMARKS_LOADED; 1559 } 1560 1561 return 0; 1562 } 1563 1564 static int sienna_cichlid_read_sensor(struct smu_context *smu, 1565 enum amd_pp_sensors sensor, 1566 void *data, uint32_t *size) 1567 { 1568 int ret = 0; 1569 struct smu_table_context *table_context = &smu->smu_table; 1570 PPTable_t *pptable = table_context->driver_pptable; 1571 1572 if(!data || !size) 1573 return -EINVAL; 1574 1575 mutex_lock(&smu->sensor_lock); 1576 switch (sensor) { 1577 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 1578 *(uint32_t *)data = pptable->FanMaximumRpm; 1579 *size = 4; 1580 break; 1581 case AMDGPU_PP_SENSOR_MEM_LOAD: 1582 ret = sienna_cichlid_get_smu_metrics_data(smu, 1583 METRICS_AVERAGE_MEMACTIVITY, 1584 (uint32_t *)data); 1585 *size = 4; 1586 break; 1587 case AMDGPU_PP_SENSOR_GPU_LOAD: 1588 ret = sienna_cichlid_get_smu_metrics_data(smu, 1589 METRICS_AVERAGE_GFXACTIVITY, 1590 (uint32_t *)data); 1591 *size = 4; 1592 break; 1593 case AMDGPU_PP_SENSOR_GPU_POWER: 1594 ret = sienna_cichlid_get_smu_metrics_data(smu, 1595 METRICS_AVERAGE_SOCKETPOWER, 1596 (uint32_t *)data); 1597 *size = 4; 1598 break; 1599 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1600 ret = sienna_cichlid_get_smu_metrics_data(smu, 1601 METRICS_TEMPERATURE_HOTSPOT, 1602 (uint32_t *)data); 1603 *size = 4; 1604 break; 1605 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1606 ret = sienna_cichlid_get_smu_metrics_data(smu, 1607 METRICS_TEMPERATURE_EDGE, 1608 (uint32_t *)data); 1609 *size = 4; 1610 break; 1611 case AMDGPU_PP_SENSOR_MEM_TEMP: 1612 ret = sienna_cichlid_get_smu_metrics_data(smu, 1613 METRICS_TEMPERATURE_MEM, 1614 (uint32_t *)data); 1615 *size = 4; 1616 break; 1617 case AMDGPU_PP_SENSOR_GFX_MCLK: 1618 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 1619 *(uint32_t *)data *= 100; 1620 *size = 4; 1621 break; 1622 case AMDGPU_PP_SENSOR_GFX_SCLK: 1623 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); 1624 *(uint32_t *)data *= 100; 1625 *size = 4; 1626 break; 1627 case AMDGPU_PP_SENSOR_VDDGFX: 1628 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data); 1629 *size = 4; 1630 break; 1631 default: 1632 ret = -EOPNOTSUPP; 1633 break; 1634 } 1635 mutex_unlock(&smu->sensor_lock); 1636 1637 return ret; 1638 } 1639 1640 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states) 1641 { 1642 uint32_t num_discrete_levels = 0; 1643 uint16_t *dpm_levels = NULL; 1644 uint16_t i = 0; 1645 struct smu_table_context *table_context = &smu->smu_table; 1646 PPTable_t *driver_ppt = NULL; 1647 1648 if (!clocks_in_khz || !num_states || !table_context->driver_pptable) 1649 return -EINVAL; 1650 1651 driver_ppt = table_context->driver_pptable; 1652 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels; 1653 dpm_levels = driver_ppt->FreqTableUclk; 1654 1655 if (num_discrete_levels == 0 || dpm_levels == NULL) 1656 return -EINVAL; 1657 1658 *num_states = num_discrete_levels; 1659 for (i = 0; i < num_discrete_levels; i++) { 1660 /* convert to khz */ 1661 *clocks_in_khz = (*dpm_levels) * 1000; 1662 clocks_in_khz++; 1663 dpm_levels++; 1664 } 1665 1666 return 0; 1667 } 1668 1669 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu, 1670 struct smu_temperature_range *range) 1671 { 1672 struct smu_table_context *table_context = &smu->smu_table; 1673 struct smu_11_0_7_powerplay_table *powerplay_table = 1674 table_context->power_play_table; 1675 PPTable_t *pptable = smu->smu_table.driver_pptable; 1676 1677 if (!range) 1678 return -EINVAL; 1679 1680 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range)); 1681 1682 range->max = pptable->TemperatureLimit[TEMP_EDGE] * 1683 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1684 range->edge_emergency_max = (pptable->TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) * 1685 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1686 range->hotspot_crit_max = pptable->TemperatureLimit[TEMP_HOTSPOT] * 1687 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1688 range->hotspot_emergency_max = (pptable->TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) * 1689 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1690 range->mem_crit_max = pptable->TemperatureLimit[TEMP_MEM] * 1691 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1692 range->mem_emergency_max = (pptable->TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)* 1693 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1694 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 1695 1696 return 0; 1697 } 1698 1699 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu, 1700 bool disable_memory_clock_switch) 1701 { 1702 int ret = 0; 1703 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks = 1704 (struct smu_11_0_max_sustainable_clocks *) 1705 smu->smu_table.max_sustainable_clocks; 1706 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal; 1707 uint32_t max_memory_clock = max_sustainable_clocks->uclock; 1708 1709 if(smu->disable_uclk_switch == disable_memory_clock_switch) 1710 return 0; 1711 1712 if(disable_memory_clock_switch) 1713 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0); 1714 else 1715 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0); 1716 1717 if(!ret) 1718 smu->disable_uclk_switch = disable_memory_clock_switch; 1719 1720 return ret; 1721 } 1722 1723 static int sienna_cichlid_get_power_limit(struct smu_context *smu) 1724 { 1725 struct smu_11_0_7_powerplay_table *powerplay_table = 1726 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table; 1727 PPTable_t *pptable = smu->smu_table.driver_pptable; 1728 uint32_t power_limit, od_percent; 1729 1730 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) { 1731 /* the last hope to figure out the ppt limit */ 1732 if (!pptable) { 1733 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!"); 1734 return -EINVAL; 1735 } 1736 power_limit = 1737 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0]; 1738 } 1739 smu->current_power_limit = power_limit; 1740 1741 if (smu->od_enabled) { 1742 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]); 1743 1744 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit); 1745 1746 power_limit *= (100 + od_percent); 1747 power_limit /= 100; 1748 } 1749 smu->max_power_limit = power_limit; 1750 1751 return 0; 1752 } 1753 1754 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu, 1755 uint32_t pcie_gen_cap, 1756 uint32_t pcie_width_cap) 1757 { 1758 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 1759 PPTable_t *pptable = smu->smu_table.driver_pptable; 1760 uint32_t smu_pcie_arg; 1761 int ret, i; 1762 1763 /* lclk dpm table setup */ 1764 for (i = 0; i < MAX_PCIE_CONF; i++) { 1765 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i]; 1766 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i]; 1767 } 1768 1769 for (i = 0; i < NUM_LINK_LEVELS; i++) { 1770 smu_pcie_arg = (i << 16) | 1771 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? 1772 (pptable->PcieGenSpeed[i] << 8) : 1773 (pcie_gen_cap << 8)) | 1774 ((pptable->PcieLaneCount[i] <= pcie_width_cap) ? 1775 pptable->PcieLaneCount[i] : 1776 pcie_width_cap); 1777 1778 ret = smu_cmn_send_smc_msg_with_param(smu, 1779 SMU_MSG_OverridePcieParameters, 1780 smu_pcie_arg, 1781 NULL); 1782 1783 if (ret) 1784 return ret; 1785 1786 if (pptable->PcieGenSpeed[i] > pcie_gen_cap) 1787 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap; 1788 if (pptable->PcieLaneCount[i] > pcie_width_cap) 1789 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap; 1790 } 1791 1792 return 0; 1793 } 1794 1795 static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu, 1796 enum smu_clk_type clk_type, 1797 uint32_t *min, uint32_t *max) 1798 { 1799 struct amdgpu_device *adev = smu->adev; 1800 int ret; 1801 1802 if (clk_type == SMU_GFXCLK) 1803 amdgpu_gfx_off_ctrl(adev, false); 1804 ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max); 1805 if (clk_type == SMU_GFXCLK) 1806 amdgpu_gfx_off_ctrl(adev, true); 1807 1808 return ret; 1809 } 1810 1811 static void sienna_cichlid_dump_od_table(struct smu_context *smu, 1812 OverDriveTable_t *od_table) 1813 { 1814 struct amdgpu_device *adev = smu->adev; 1815 uint32_t smu_version; 1816 1817 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, 1818 od_table->GfxclkFmax); 1819 dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin, 1820 od_table->UclkFmax); 1821 1822 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1823 if (!((adev->asic_type == CHIP_SIENNA_CICHLID) && 1824 (smu_version < 0x003a2900))) 1825 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset); 1826 } 1827 1828 static int sienna_cichlid_set_default_od_settings(struct smu_context *smu) 1829 { 1830 OverDriveTable_t *od_table = 1831 (OverDriveTable_t *)smu->smu_table.overdrive_table; 1832 OverDriveTable_t *boot_od_table = 1833 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table; 1834 int ret = 0; 1835 1836 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 1837 0, (void *)od_table, false); 1838 if (ret) { 1839 dev_err(smu->adev->dev, "Failed to get overdrive table!\n"); 1840 return ret; 1841 } 1842 1843 memcpy(boot_od_table, od_table, sizeof(OverDriveTable_t)); 1844 1845 sienna_cichlid_dump_od_table(smu, od_table); 1846 1847 return 0; 1848 } 1849 1850 static int sienna_cichlid_od_setting_check_range(struct smu_context *smu, 1851 struct smu_11_0_7_overdrive_table *od_table, 1852 enum SMU_11_0_7_ODSETTING_ID setting, 1853 uint32_t value) 1854 { 1855 if (value < od_table->min[setting]) { 1856 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", 1857 setting, value, od_table->min[setting]); 1858 return -EINVAL; 1859 } 1860 if (value > od_table->max[setting]) { 1861 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", 1862 setting, value, od_table->max[setting]); 1863 return -EINVAL; 1864 } 1865 1866 return 0; 1867 } 1868 1869 static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu, 1870 enum PP_OD_DPM_TABLE_COMMAND type, 1871 long input[], uint32_t size) 1872 { 1873 struct smu_table_context *table_context = &smu->smu_table; 1874 OverDriveTable_t *od_table = 1875 (OverDriveTable_t *)table_context->overdrive_table; 1876 struct smu_11_0_7_overdrive_table *od_settings = 1877 (struct smu_11_0_7_overdrive_table *)smu->od_settings; 1878 struct amdgpu_device *adev = smu->adev; 1879 enum SMU_11_0_7_ODSETTING_ID freq_setting; 1880 uint16_t *freq_ptr; 1881 int i, ret = 0; 1882 uint32_t smu_version; 1883 1884 if (!smu->od_enabled) { 1885 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n"); 1886 return -EINVAL; 1887 } 1888 1889 if (!smu->od_settings) { 1890 dev_err(smu->adev->dev, "OD board limits are not set!\n"); 1891 return -ENOENT; 1892 } 1893 1894 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) { 1895 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n"); 1896 return -EINVAL; 1897 } 1898 1899 switch (type) { 1900 case PP_OD_EDIT_SCLK_VDDC_TABLE: 1901 if (!sienna_cichlid_is_od_feature_supported(od_settings, 1902 SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) { 1903 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n"); 1904 return -ENOTSUPP; 1905 } 1906 1907 for (i = 0; i < size; i += 2) { 1908 if (i + 2 > size) { 1909 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size); 1910 return -EINVAL; 1911 } 1912 1913 switch (input[i]) { 1914 case 0: 1915 if (input[i + 1] > od_table->GfxclkFmax) { 1916 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n", 1917 input[i + 1], od_table->GfxclkFmax); 1918 return -EINVAL; 1919 } 1920 1921 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN; 1922 freq_ptr = &od_table->GfxclkFmin; 1923 break; 1924 1925 case 1: 1926 if (input[i + 1] < od_table->GfxclkFmin) { 1927 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n", 1928 input[i + 1], od_table->GfxclkFmin); 1929 return -EINVAL; 1930 } 1931 1932 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX; 1933 freq_ptr = &od_table->GfxclkFmax; 1934 break; 1935 1936 default: 1937 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]); 1938 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n"); 1939 return -EINVAL; 1940 } 1941 1942 ret = sienna_cichlid_od_setting_check_range(smu, od_settings, 1943 freq_setting, input[i + 1]); 1944 if (ret) 1945 return ret; 1946 1947 *freq_ptr = (uint16_t)input[i + 1]; 1948 } 1949 break; 1950 1951 case PP_OD_EDIT_MCLK_VDDC_TABLE: 1952 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) { 1953 dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n"); 1954 return -ENOTSUPP; 1955 } 1956 1957 for (i = 0; i < size; i += 2) { 1958 if (i + 2 > size) { 1959 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size); 1960 return -EINVAL; 1961 } 1962 1963 switch (input[i]) { 1964 case 0: 1965 if (input[i + 1] > od_table->UclkFmax) { 1966 dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n", 1967 input[i + 1], od_table->UclkFmax); 1968 return -EINVAL; 1969 } 1970 1971 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN; 1972 freq_ptr = &od_table->UclkFmin; 1973 break; 1974 1975 case 1: 1976 if (input[i + 1] < od_table->UclkFmin) { 1977 dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n", 1978 input[i + 1], od_table->UclkFmin); 1979 return -EINVAL; 1980 } 1981 1982 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX; 1983 freq_ptr = &od_table->UclkFmax; 1984 break; 1985 1986 default: 1987 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]); 1988 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n"); 1989 return -EINVAL; 1990 } 1991 1992 ret = sienna_cichlid_od_setting_check_range(smu, od_settings, 1993 freq_setting, input[i + 1]); 1994 if (ret) 1995 return ret; 1996 1997 *freq_ptr = (uint16_t)input[i + 1]; 1998 } 1999 break; 2000 2001 case PP_OD_RESTORE_DEFAULT_TABLE: 2002 memcpy(table_context->overdrive_table, 2003 table_context->boot_overdrive_table, 2004 sizeof(OverDriveTable_t)); 2005 fallthrough; 2006 2007 case PP_OD_COMMIT_DPM_TABLE: 2008 sienna_cichlid_dump_od_table(smu, od_table); 2009 2010 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 2011 0, (void *)od_table, true); 2012 if (ret) { 2013 dev_err(smu->adev->dev, "Failed to import overdrive table!\n"); 2014 return ret; 2015 } 2016 break; 2017 2018 case PP_OD_EDIT_VDDGFX_OFFSET: 2019 if (size != 1) { 2020 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size); 2021 return -EINVAL; 2022 } 2023 2024 /* 2025 * OD GFX Voltage Offset functionality is supported only by 58.41.0 2026 * and onwards SMU firmwares. 2027 */ 2028 smu_cmn_get_smc_version(smu, NULL, &smu_version); 2029 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 2030 (smu_version < 0x003a2900)) { 2031 dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported " 2032 "only by 58.41.0 and onwards SMU firmwares!\n"); 2033 return -EOPNOTSUPP; 2034 } 2035 2036 od_table->VddGfxOffset = (int16_t)input[0]; 2037 2038 sienna_cichlid_dump_od_table(smu, od_table); 2039 break; 2040 2041 default: 2042 return -ENOSYS; 2043 } 2044 2045 return ret; 2046 } 2047 2048 static int sienna_cichlid_run_btc(struct smu_context *smu) 2049 { 2050 return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); 2051 } 2052 2053 static bool sienna_cichlid_is_baco_supported(struct smu_context *smu) 2054 { 2055 struct amdgpu_device *adev = smu->adev; 2056 uint32_t val; 2057 2058 if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu))) 2059 return false; 2060 2061 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); 2062 return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false; 2063 } 2064 2065 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu) 2066 { 2067 struct amdgpu_device *adev = smu->adev; 2068 uint32_t val; 2069 u32 smu_version; 2070 2071 /** 2072 * SRIOV env will not support SMU mode1 reset 2073 * PM FW support mode1 reset from 58.26 2074 */ 2075 smu_cmn_get_smc_version(smu, NULL, &smu_version); 2076 if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00)) 2077 return false; 2078 2079 /** 2080 * mode1 reset relies on PSP, so we should check if 2081 * PSP is alive. 2082 */ 2083 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 2084 return val != 0x0; 2085 } 2086 2087 static void sienna_cichlid_dump_pptable(struct smu_context *smu) 2088 { 2089 struct smu_table_context *table_context = &smu->smu_table; 2090 PPTable_t *pptable = table_context->driver_pptable; 2091 int i; 2092 2093 dev_info(smu->adev->dev, "Dumped PPTable:\n"); 2094 2095 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version); 2096 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]); 2097 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]); 2098 2099 for (i = 0; i < PPT_THROTTLER_COUNT; i++) { 2100 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]); 2101 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]); 2102 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]); 2103 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]); 2104 } 2105 2106 for (i = 0; i < TDC_THROTTLER_COUNT; i++) { 2107 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]); 2108 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]); 2109 } 2110 2111 for (i = 0; i < TEMP_COUNT; i++) { 2112 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]); 2113 } 2114 2115 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit); 2116 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig); 2117 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]); 2118 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]); 2119 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]); 2120 2121 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit); 2122 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) { 2123 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]); 2124 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]); 2125 } 2126 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask); 2127 2128 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask); 2129 2130 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc); 2131 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx); 2132 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx); 2133 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc); 2134 2135 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin); 2136 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin); 2137 2138 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold); 2139 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]); 2140 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]); 2141 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]); 2142 2143 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx); 2144 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc); 2145 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx); 2146 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc); 2147 2148 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx); 2149 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc); 2150 2151 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin); 2152 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin); 2153 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp); 2154 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp); 2155 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp); 2156 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp); 2157 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis); 2158 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis); 2159 2160 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n" 2161 " .VoltageMode = 0x%02x\n" 2162 " .SnapToDiscrete = 0x%02x\n" 2163 " .NumDiscreteLevels = 0x%02x\n" 2164 " .padding = 0x%02x\n" 2165 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2166 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2167 " .SsFmin = 0x%04x\n" 2168 " .Padding_16 = 0x%04x\n", 2169 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode, 2170 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete, 2171 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels, 2172 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding, 2173 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m, 2174 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b, 2175 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a, 2176 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b, 2177 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c, 2178 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin, 2179 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16); 2180 2181 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n" 2182 " .VoltageMode = 0x%02x\n" 2183 " .SnapToDiscrete = 0x%02x\n" 2184 " .NumDiscreteLevels = 0x%02x\n" 2185 " .padding = 0x%02x\n" 2186 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2187 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2188 " .SsFmin = 0x%04x\n" 2189 " .Padding_16 = 0x%04x\n", 2190 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode, 2191 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete, 2192 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels, 2193 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding, 2194 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m, 2195 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b, 2196 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a, 2197 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b, 2198 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c, 2199 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin, 2200 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16); 2201 2202 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n" 2203 " .VoltageMode = 0x%02x\n" 2204 " .SnapToDiscrete = 0x%02x\n" 2205 " .NumDiscreteLevels = 0x%02x\n" 2206 " .padding = 0x%02x\n" 2207 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2208 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2209 " .SsFmin = 0x%04x\n" 2210 " .Padding_16 = 0x%04x\n", 2211 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode, 2212 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete, 2213 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels, 2214 pptable->DpmDescriptor[PPCLK_UCLK].Padding, 2215 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m, 2216 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b, 2217 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a, 2218 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b, 2219 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c, 2220 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin, 2221 pptable->DpmDescriptor[PPCLK_UCLK].Padding16); 2222 2223 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n" 2224 " .VoltageMode = 0x%02x\n" 2225 " .SnapToDiscrete = 0x%02x\n" 2226 " .NumDiscreteLevels = 0x%02x\n" 2227 " .padding = 0x%02x\n" 2228 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2229 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2230 " .SsFmin = 0x%04x\n" 2231 " .Padding_16 = 0x%04x\n", 2232 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode, 2233 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete, 2234 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels, 2235 pptable->DpmDescriptor[PPCLK_FCLK].Padding, 2236 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m, 2237 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b, 2238 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a, 2239 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b, 2240 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c, 2241 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin, 2242 pptable->DpmDescriptor[PPCLK_FCLK].Padding16); 2243 2244 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n" 2245 " .VoltageMode = 0x%02x\n" 2246 " .SnapToDiscrete = 0x%02x\n" 2247 " .NumDiscreteLevels = 0x%02x\n" 2248 " .padding = 0x%02x\n" 2249 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2250 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2251 " .SsFmin = 0x%04x\n" 2252 " .Padding_16 = 0x%04x\n", 2253 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode, 2254 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete, 2255 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels, 2256 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding, 2257 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m, 2258 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b, 2259 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a, 2260 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b, 2261 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c, 2262 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin, 2263 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16); 2264 2265 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n" 2266 " .VoltageMode = 0x%02x\n" 2267 " .SnapToDiscrete = 0x%02x\n" 2268 " .NumDiscreteLevels = 0x%02x\n" 2269 " .padding = 0x%02x\n" 2270 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2271 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2272 " .SsFmin = 0x%04x\n" 2273 " .Padding_16 = 0x%04x\n", 2274 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode, 2275 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete, 2276 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels, 2277 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding, 2278 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m, 2279 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b, 2280 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a, 2281 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b, 2282 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c, 2283 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin, 2284 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16); 2285 2286 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n" 2287 " .VoltageMode = 0x%02x\n" 2288 " .SnapToDiscrete = 0x%02x\n" 2289 " .NumDiscreteLevels = 0x%02x\n" 2290 " .padding = 0x%02x\n" 2291 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2292 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2293 " .SsFmin = 0x%04x\n" 2294 " .Padding_16 = 0x%04x\n", 2295 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode, 2296 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete, 2297 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels, 2298 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding, 2299 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m, 2300 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b, 2301 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a, 2302 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b, 2303 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c, 2304 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin, 2305 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16); 2306 2307 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n" 2308 " .VoltageMode = 0x%02x\n" 2309 " .SnapToDiscrete = 0x%02x\n" 2310 " .NumDiscreteLevels = 0x%02x\n" 2311 " .padding = 0x%02x\n" 2312 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2313 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2314 " .SsFmin = 0x%04x\n" 2315 " .Padding_16 = 0x%04x\n", 2316 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode, 2317 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete, 2318 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels, 2319 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding, 2320 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m, 2321 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b, 2322 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a, 2323 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b, 2324 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c, 2325 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin, 2326 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16); 2327 2328 dev_info(smu->adev->dev, "FreqTableGfx\n"); 2329 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) 2330 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]); 2331 2332 dev_info(smu->adev->dev, "FreqTableVclk\n"); 2333 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++) 2334 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]); 2335 2336 dev_info(smu->adev->dev, "FreqTableDclk\n"); 2337 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++) 2338 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]); 2339 2340 dev_info(smu->adev->dev, "FreqTableSocclk\n"); 2341 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) 2342 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]); 2343 2344 dev_info(smu->adev->dev, "FreqTableUclk\n"); 2345 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2346 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]); 2347 2348 dev_info(smu->adev->dev, "FreqTableFclk\n"); 2349 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) 2350 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]); 2351 2352 dev_info(smu->adev->dev, "DcModeMaxFreq\n"); 2353 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]); 2354 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]); 2355 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]); 2356 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]); 2357 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]); 2358 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]); 2359 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]); 2360 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]); 2361 2362 dev_info(smu->adev->dev, "FreqTableUclkDiv\n"); 2363 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2364 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]); 2365 2366 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq); 2367 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding); 2368 2369 dev_info(smu->adev->dev, "Mp0clkFreq\n"); 2370 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 2371 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]); 2372 2373 dev_info(smu->adev->dev, "Mp0DpmVoltage\n"); 2374 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 2375 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]); 2376 2377 dev_info(smu->adev->dev, "MemVddciVoltage\n"); 2378 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2379 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]); 2380 2381 dev_info(smu->adev->dev, "MemMvddVoltage\n"); 2382 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2383 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]); 2384 2385 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry); 2386 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit); 2387 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle); 2388 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource); 2389 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding); 2390 2391 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask); 2392 2393 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask); 2394 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask); 2395 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]); 2396 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow); 2397 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]); 2398 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]); 2399 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]); 2400 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]); 2401 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt); 2402 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt); 2403 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt); 2404 2405 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage); 2406 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime); 2407 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime); 2408 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum); 2409 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis); 2410 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout); 2411 2412 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]); 2413 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]); 2414 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]); 2415 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]); 2416 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]); 2417 2418 dev_info(smu->adev->dev, "FlopsPerByteTable\n"); 2419 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++) 2420 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]); 2421 2422 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv); 2423 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]); 2424 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]); 2425 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]); 2426 2427 dev_info(smu->adev->dev, "UclkDpmPstates\n"); 2428 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2429 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]); 2430 2431 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n"); 2432 dev_info(smu->adev->dev, " .Fmin = 0x%x\n", 2433 pptable->UclkDpmSrcFreqRange.Fmin); 2434 dev_info(smu->adev->dev, " .Fmax = 0x%x\n", 2435 pptable->UclkDpmSrcFreqRange.Fmax); 2436 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n"); 2437 dev_info(smu->adev->dev, " .Fmin = 0x%x\n", 2438 pptable->UclkDpmTargFreqRange.Fmin); 2439 dev_info(smu->adev->dev, " .Fmax = 0x%x\n", 2440 pptable->UclkDpmTargFreqRange.Fmax); 2441 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq); 2442 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding); 2443 2444 dev_info(smu->adev->dev, "PcieGenSpeed\n"); 2445 for (i = 0; i < NUM_LINK_LEVELS; i++) 2446 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]); 2447 2448 dev_info(smu->adev->dev, "PcieLaneCount\n"); 2449 for (i = 0; i < NUM_LINK_LEVELS; i++) 2450 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]); 2451 2452 dev_info(smu->adev->dev, "LclkFreq\n"); 2453 for (i = 0; i < NUM_LINK_LEVELS; i++) 2454 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]); 2455 2456 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp); 2457 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp); 2458 2459 dev_info(smu->adev->dev, "FanGain\n"); 2460 for (i = 0; i < TEMP_COUNT; i++) 2461 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]); 2462 2463 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin); 2464 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm); 2465 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm); 2466 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm); 2467 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm); 2468 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature); 2469 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk); 2470 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16); 2471 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect); 2472 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding); 2473 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable); 2474 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev); 2475 2476 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta); 2477 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta); 2478 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta); 2479 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved); 2480 2481 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]); 2482 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]); 2483 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect); 2484 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs); 2485 2486 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", 2487 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a, 2488 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b, 2489 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c); 2490 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", 2491 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a, 2492 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b, 2493 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c); 2494 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n", 2495 pptable->dBtcGbGfxPll.a, 2496 pptable->dBtcGbGfxPll.b, 2497 pptable->dBtcGbGfxPll.c); 2498 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n", 2499 pptable->dBtcGbGfxDfll.a, 2500 pptable->dBtcGbGfxDfll.b, 2501 pptable->dBtcGbGfxDfll.c); 2502 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n", 2503 pptable->dBtcGbSoc.a, 2504 pptable->dBtcGbSoc.b, 2505 pptable->dBtcGbSoc.c); 2506 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n", 2507 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m, 2508 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b); 2509 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n", 2510 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m, 2511 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b); 2512 2513 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n"); 2514 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) { 2515 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n", 2516 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]); 2517 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n", 2518 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]); 2519 } 2520 2521 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", 2522 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a, 2523 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b, 2524 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c); 2525 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", 2526 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a, 2527 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b, 2528 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c); 2529 2530 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]); 2531 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]); 2532 2533 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]); 2534 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]); 2535 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]); 2536 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]); 2537 2538 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]); 2539 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]); 2540 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]); 2541 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]); 2542 2543 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]); 2544 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]); 2545 2546 dev_info(smu->adev->dev, "XgmiDpmPstates\n"); 2547 for (i = 0; i < NUM_XGMI_LEVELS; i++) 2548 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]); 2549 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]); 2550 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]); 2551 2552 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides); 2553 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n", 2554 pptable->ReservedEquation0.a, 2555 pptable->ReservedEquation0.b, 2556 pptable->ReservedEquation0.c); 2557 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n", 2558 pptable->ReservedEquation1.a, 2559 pptable->ReservedEquation1.b, 2560 pptable->ReservedEquation1.c); 2561 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n", 2562 pptable->ReservedEquation2.a, 2563 pptable->ReservedEquation2.b, 2564 pptable->ReservedEquation2.c); 2565 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n", 2566 pptable->ReservedEquation3.a, 2567 pptable->ReservedEquation3.b, 2568 pptable->ReservedEquation3.c); 2569 2570 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]); 2571 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]); 2572 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]); 2573 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]); 2574 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]); 2575 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]); 2576 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]); 2577 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]); 2578 2579 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]); 2580 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]); 2581 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]); 2582 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]); 2583 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]); 2584 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]); 2585 2586 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) { 2587 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i); 2588 dev_info(smu->adev->dev, " .Enabled = 0x%x\n", 2589 pptable->I2cControllers[i].Enabled); 2590 dev_info(smu->adev->dev, " .Speed = 0x%x\n", 2591 pptable->I2cControllers[i].Speed); 2592 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n", 2593 pptable->I2cControllers[i].SlaveAddress); 2594 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n", 2595 pptable->I2cControllers[i].ControllerPort); 2596 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n", 2597 pptable->I2cControllers[i].ControllerName); 2598 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n", 2599 pptable->I2cControllers[i].ThermalThrotter); 2600 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n", 2601 pptable->I2cControllers[i].I2cProtocol); 2602 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n", 2603 pptable->I2cControllers[i].PaddingConfig); 2604 } 2605 2606 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl); 2607 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda); 2608 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr); 2609 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]); 2610 2611 dev_info(smu->adev->dev, "Board Parameters:\n"); 2612 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping); 2613 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping); 2614 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping); 2615 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping); 2616 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask); 2617 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask); 2618 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask); 2619 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask); 2620 2621 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent); 2622 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset); 2623 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx); 2624 2625 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent); 2626 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset); 2627 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc); 2628 2629 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent); 2630 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset); 2631 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0); 2632 2633 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent); 2634 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset); 2635 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1); 2636 2637 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio); 2638 2639 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio); 2640 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity); 2641 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio); 2642 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity); 2643 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio); 2644 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity); 2645 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio); 2646 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity); 2647 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0); 2648 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1); 2649 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2); 2650 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask); 2651 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie); 2652 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError); 2653 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]); 2654 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]); 2655 2656 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled); 2657 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent); 2658 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq); 2659 2660 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled); 2661 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent); 2662 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq); 2663 2664 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding); 2665 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq); 2666 2667 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled); 2668 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent); 2669 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq); 2670 2671 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled); 2672 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth); 2673 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]); 2674 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]); 2675 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]); 2676 2677 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower); 2678 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding); 2679 2680 dev_info(smu->adev->dev, "XgmiLinkSpeed\n"); 2681 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 2682 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]); 2683 dev_info(smu->adev->dev, "XgmiLinkWidth\n"); 2684 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 2685 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]); 2686 dev_info(smu->adev->dev, "XgmiFclkFreq\n"); 2687 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 2688 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]); 2689 dev_info(smu->adev->dev, "XgmiSocVoltage\n"); 2690 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 2691 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]); 2692 2693 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled); 2694 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled); 2695 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]); 2696 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]); 2697 2698 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]); 2699 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]); 2700 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]); 2701 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]); 2702 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]); 2703 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]); 2704 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]); 2705 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]); 2706 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]); 2707 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]); 2708 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]); 2709 2710 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]); 2711 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]); 2712 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]); 2713 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]); 2714 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]); 2715 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]); 2716 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]); 2717 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]); 2718 } 2719 2720 static void sienna_cichlid_fill_i2c_req(SwI2cRequest_t *req, bool write, 2721 uint8_t address, uint32_t numbytes, 2722 uint8_t *data) 2723 { 2724 int i; 2725 2726 req->I2CcontrollerPort = 1; 2727 req->I2CSpeed = 2; 2728 req->SlaveAddress = address; 2729 req->NumCmds = numbytes; 2730 2731 for (i = 0; i < numbytes; i++) { 2732 SwI2cCmd_t *cmd = &req->SwI2cCmds[i]; 2733 2734 /* First 2 bytes are always write for lower 2b EEPROM address */ 2735 if (i < 2) 2736 cmd->CmdConfig = CMDCONFIG_READWRITE_MASK; 2737 else 2738 cmd->CmdConfig = write ? CMDCONFIG_READWRITE_MASK : 0; 2739 2740 2741 /* Add RESTART for read after address filled */ 2742 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0; 2743 2744 /* Add STOP in the end */ 2745 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0; 2746 2747 /* Fill with data regardless if read or write to simplify code */ 2748 cmd->ReadWriteData = data[i]; 2749 } 2750 } 2751 2752 static int sienna_cichlid_i2c_read_data(struct i2c_adapter *control, 2753 uint8_t address, 2754 uint8_t *data, 2755 uint32_t numbytes) 2756 { 2757 uint32_t i, ret = 0; 2758 SwI2cRequest_t req; 2759 struct amdgpu_device *adev = to_amdgpu_device(control); 2760 struct smu_table_context *smu_table = &adev->smu.smu_table; 2761 struct smu_table *table = &smu_table->driver_table; 2762 2763 if (numbytes > MAX_SW_I2C_COMMANDS) { 2764 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n", 2765 numbytes, MAX_SW_I2C_COMMANDS); 2766 return -EINVAL; 2767 } 2768 2769 memset(&req, 0, sizeof(req)); 2770 sienna_cichlid_fill_i2c_req(&req, false, address, numbytes, data); 2771 2772 mutex_lock(&adev->smu.mutex); 2773 /* Now read data starting with that address */ 2774 ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, 2775 true); 2776 mutex_unlock(&adev->smu.mutex); 2777 2778 if (!ret) { 2779 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr; 2780 2781 /* Assume SMU fills res.SwI2cCmds[i].Data with read bytes */ 2782 for (i = 0; i < numbytes; i++) 2783 data[i] = res->SwI2cCmds[i].ReadWriteData; 2784 2785 dev_dbg(adev->dev, "sienna_cichlid_i2c_read_data, address = %x, bytes = %d, data :", 2786 (uint16_t)address, numbytes); 2787 2788 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE, 2789 8, 1, data, numbytes, false); 2790 } else 2791 dev_err(adev->dev, "sienna_cichlid_i2c_read_data - error occurred :%x", ret); 2792 2793 return ret; 2794 } 2795 2796 static int sienna_cichlid_i2c_write_data(struct i2c_adapter *control, 2797 uint8_t address, 2798 uint8_t *data, 2799 uint32_t numbytes) 2800 { 2801 uint32_t ret; 2802 SwI2cRequest_t req; 2803 struct amdgpu_device *adev = to_amdgpu_device(control); 2804 2805 if (numbytes > MAX_SW_I2C_COMMANDS) { 2806 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n", 2807 numbytes, MAX_SW_I2C_COMMANDS); 2808 return -EINVAL; 2809 } 2810 2811 memset(&req, 0, sizeof(req)); 2812 sienna_cichlid_fill_i2c_req(&req, true, address, numbytes, data); 2813 2814 mutex_lock(&adev->smu.mutex); 2815 ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true); 2816 mutex_unlock(&adev->smu.mutex); 2817 2818 if (!ret) { 2819 dev_dbg(adev->dev, "sienna_cichlid_i2c_write(), address = %x, bytes = %d , data: ", 2820 (uint16_t)address, numbytes); 2821 2822 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE, 2823 8, 1, data, numbytes, false); 2824 /* 2825 * According to EEPROM spec there is a MAX of 10 ms required for 2826 * EEPROM to flush internal RX buffer after STOP was issued at the 2827 * end of write transaction. During this time the EEPROM will not be 2828 * responsive to any more commands - so wait a bit more. 2829 */ 2830 msleep(10); 2831 2832 } else 2833 dev_err(adev->dev, "sienna_cichlid_i2c_write- error occurred :%x", ret); 2834 2835 return ret; 2836 } 2837 2838 static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap, 2839 struct i2c_msg *msgs, int num) 2840 { 2841 uint32_t i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0; 2842 uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 }; 2843 2844 for (i = 0; i < num; i++) { 2845 /* 2846 * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at 2847 * once and hence the data needs to be spliced into chunks and sent each 2848 * chunk separately 2849 */ 2850 data_size = msgs[i].len - 2; 2851 data_chunk_size = MAX_SW_I2C_COMMANDS - 2; 2852 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff); 2853 data_ptr = msgs[i].buf + 2; 2854 2855 for (j = 0; j < data_size / data_chunk_size; j++) { 2856 /* Insert the EEPROM dest addess, bits 0-15 */ 2857 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff); 2858 data_chunk[1] = (next_eeprom_addr & 0xff); 2859 2860 if (msgs[i].flags & I2C_M_RD) { 2861 ret = sienna_cichlid_i2c_read_data(i2c_adap, 2862 (uint8_t)msgs[i].addr, 2863 data_chunk, MAX_SW_I2C_COMMANDS); 2864 2865 memcpy(data_ptr, data_chunk + 2, data_chunk_size); 2866 } else { 2867 2868 memcpy(data_chunk + 2, data_ptr, data_chunk_size); 2869 2870 ret = sienna_cichlid_i2c_write_data(i2c_adap, 2871 (uint8_t)msgs[i].addr, 2872 data_chunk, MAX_SW_I2C_COMMANDS); 2873 } 2874 2875 if (ret) { 2876 num = -EIO; 2877 goto fail; 2878 } 2879 2880 next_eeprom_addr += data_chunk_size; 2881 data_ptr += data_chunk_size; 2882 } 2883 2884 if (data_size % data_chunk_size) { 2885 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff); 2886 data_chunk[1] = (next_eeprom_addr & 0xff); 2887 2888 if (msgs[i].flags & I2C_M_RD) { 2889 ret = sienna_cichlid_i2c_read_data(i2c_adap, 2890 (uint8_t)msgs[i].addr, 2891 data_chunk, (data_size % data_chunk_size) + 2); 2892 2893 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size); 2894 } else { 2895 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size); 2896 2897 ret = sienna_cichlid_i2c_write_data(i2c_adap, 2898 (uint8_t)msgs[i].addr, 2899 data_chunk, (data_size % data_chunk_size) + 2); 2900 } 2901 2902 if (ret) { 2903 num = -EIO; 2904 goto fail; 2905 } 2906 } 2907 } 2908 2909 fail: 2910 return num; 2911 } 2912 2913 static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap) 2914 { 2915 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 2916 } 2917 2918 2919 static const struct i2c_algorithm sienna_cichlid_i2c_algo = { 2920 .master_xfer = sienna_cichlid_i2c_xfer, 2921 .functionality = sienna_cichlid_i2c_func, 2922 }; 2923 2924 static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control) 2925 { 2926 struct amdgpu_device *adev = to_amdgpu_device(control); 2927 int res; 2928 2929 control->owner = THIS_MODULE; 2930 control->class = I2C_CLASS_SPD; 2931 control->dev.parent = &adev->pdev->dev; 2932 control->algo = &sienna_cichlid_i2c_algo; 2933 snprintf(control->name, sizeof(control->name), "AMDGPU SMU"); 2934 2935 res = i2c_add_adapter(control); 2936 if (res) 2937 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 2938 2939 return res; 2940 } 2941 2942 static void sienna_cichlid_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control) 2943 { 2944 i2c_del_adapter(control); 2945 } 2946 2947 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu, 2948 void **table) 2949 { 2950 struct smu_table_context *smu_table = &smu->smu_table; 2951 struct gpu_metrics_v1_0 *gpu_metrics = 2952 (struct gpu_metrics_v1_0 *)smu_table->gpu_metrics_table; 2953 SmuMetricsExternal_t metrics_external; 2954 SmuMetrics_t *metrics = 2955 &(metrics_external.SmuMetrics); 2956 int ret = 0; 2957 2958 ret = smu_cmn_get_metrics_table(smu, 2959 &metrics_external, 2960 true); 2961 if (ret) 2962 return ret; 2963 2964 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 0); 2965 2966 gpu_metrics->temperature_edge = metrics->TemperatureEdge; 2967 gpu_metrics->temperature_hotspot = metrics->TemperatureHotspot; 2968 gpu_metrics->temperature_mem = metrics->TemperatureMem; 2969 gpu_metrics->temperature_vrgfx = metrics->TemperatureVrGfx; 2970 gpu_metrics->temperature_vrsoc = metrics->TemperatureVrSoc; 2971 gpu_metrics->temperature_vrmem = metrics->TemperatureVrMem0; 2972 2973 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity; 2974 gpu_metrics->average_umc_activity = metrics->AverageUclkActivity; 2975 gpu_metrics->average_mm_activity = metrics->VcnActivityPercentage; 2976 2977 gpu_metrics->average_socket_power = metrics->AverageSocketPower; 2978 gpu_metrics->energy_accumulator = metrics->EnergyAccumulator; 2979 2980 if (metrics->AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD) 2981 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs; 2982 else 2983 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs; 2984 gpu_metrics->average_uclk_frequency = metrics->AverageUclkFrequencyPostDs; 2985 gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency; 2986 gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency; 2987 gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency; 2988 gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency; 2989 2990 gpu_metrics->current_gfxclk = metrics->CurrClock[PPCLK_GFXCLK]; 2991 gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK]; 2992 gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK]; 2993 gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0]; 2994 gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0]; 2995 gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1]; 2996 gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1]; 2997 2998 gpu_metrics->throttle_status = metrics->ThrottlerStatus; 2999 3000 gpu_metrics->current_fan_speed = metrics->CurrFanSpeed; 3001 3002 gpu_metrics->pcie_link_width = 3003 smu_v11_0_get_current_pcie_link_width(smu); 3004 gpu_metrics->pcie_link_speed = 3005 smu_v11_0_get_current_pcie_link_speed(smu); 3006 3007 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 3008 3009 *table = (void *)gpu_metrics; 3010 3011 return sizeof(struct gpu_metrics_v1_0); 3012 } 3013 3014 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu) 3015 { 3016 return smu_cmn_send_smc_msg_with_param(smu, 3017 SMU_MSG_SetMGpuFanBoostLimitRpm, 3018 0, 3019 NULL); 3020 } 3021 3022 static int sienna_cichlid_gpo_control(struct smu_context *smu, 3023 bool enablement) 3024 { 3025 uint32_t smu_version; 3026 int ret = 0; 3027 3028 3029 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) { 3030 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 3031 if (ret) 3032 return ret; 3033 3034 if (enablement) { 3035 if (smu_version < 0x003a2500) { 3036 ret = smu_cmn_send_smc_msg_with_param(smu, 3037 SMU_MSG_SetGpoFeaturePMask, 3038 GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK, 3039 NULL); 3040 } else { 3041 ret = smu_cmn_send_smc_msg_with_param(smu, 3042 SMU_MSG_DisallowGpo, 3043 0, 3044 NULL); 3045 } 3046 } else { 3047 if (smu_version < 0x003a2500) { 3048 ret = smu_cmn_send_smc_msg_with_param(smu, 3049 SMU_MSG_SetGpoFeaturePMask, 3050 0, 3051 NULL); 3052 } else { 3053 ret = smu_cmn_send_smc_msg_with_param(smu, 3054 SMU_MSG_DisallowGpo, 3055 1, 3056 NULL); 3057 } 3058 } 3059 } 3060 3061 return ret; 3062 } 3063 3064 static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu) 3065 { 3066 uint32_t smu_version; 3067 int ret = 0; 3068 3069 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 3070 if (ret) 3071 return ret; 3072 3073 /* 3074 * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45 3075 * onwards PMFWs. 3076 */ 3077 if (smu_version < 0x003A2D00) 3078 return 0; 3079 3080 return smu_cmn_send_smc_msg_with_param(smu, 3081 SMU_MSG_Enable2ndUSB20Port, 3082 smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ? 3083 1 : 0, 3084 NULL); 3085 } 3086 3087 static int sienna_cichlid_system_features_control(struct smu_context *smu, 3088 bool en) 3089 { 3090 int ret = 0; 3091 3092 if (en) { 3093 ret = sienna_cichlid_notify_2nd_usb20_port(smu); 3094 if (ret) 3095 return ret; 3096 } 3097 3098 return smu_v11_0_system_features_control(smu, en); 3099 } 3100 3101 static const struct pptable_funcs sienna_cichlid_ppt_funcs = { 3102 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask, 3103 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table, 3104 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable, 3105 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable, 3106 .i2c_init = sienna_cichlid_i2c_control_init, 3107 .i2c_fini = sienna_cichlid_i2c_control_fini, 3108 .print_clk_levels = sienna_cichlid_print_clk_levels, 3109 .force_clk_levels = sienna_cichlid_force_clk_levels, 3110 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk, 3111 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed, 3112 .display_config_changed = sienna_cichlid_display_config_changed, 3113 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config, 3114 .is_dpm_running = sienna_cichlid_is_dpm_running, 3115 .get_fan_speed_percent = sienna_cichlid_get_fan_speed_percent, 3116 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode, 3117 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode, 3118 .set_watermarks_table = sienna_cichlid_set_watermarks_table, 3119 .read_sensor = sienna_cichlid_read_sensor, 3120 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states, 3121 .set_performance_level = smu_v11_0_set_performance_level, 3122 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range, 3123 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch, 3124 .get_power_limit = sienna_cichlid_get_power_limit, 3125 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters, 3126 .dump_pptable = sienna_cichlid_dump_pptable, 3127 .init_microcode = smu_v11_0_init_microcode, 3128 .load_microcode = smu_v11_0_load_microcode, 3129 .init_smc_tables = sienna_cichlid_init_smc_tables, 3130 .fini_smc_tables = smu_v11_0_fini_smc_tables, 3131 .init_power = smu_v11_0_init_power, 3132 .fini_power = smu_v11_0_fini_power, 3133 .check_fw_status = smu_v11_0_check_fw_status, 3134 .setup_pptable = sienna_cichlid_setup_pptable, 3135 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, 3136 .check_fw_version = smu_v11_0_check_fw_version, 3137 .write_pptable = smu_cmn_write_pptable, 3138 .set_driver_table_location = smu_v11_0_set_driver_table_location, 3139 .set_tool_table_location = smu_v11_0_set_tool_table_location, 3140 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 3141 .system_features_control = sienna_cichlid_system_features_control, 3142 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 3143 .send_smc_msg = smu_cmn_send_smc_msg, 3144 .init_display_count = NULL, 3145 .set_allowed_mask = smu_v11_0_set_allowed_mask, 3146 .get_enabled_mask = smu_cmn_get_enabled_mask, 3147 .feature_is_enabled = smu_cmn_feature_is_enabled, 3148 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 3149 .notify_display_change = NULL, 3150 .set_power_limit = smu_v11_0_set_power_limit, 3151 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks, 3152 .enable_thermal_alert = smu_v11_0_enable_thermal_alert, 3153 .disable_thermal_alert = smu_v11_0_disable_thermal_alert, 3154 .set_min_dcef_deep_sleep = NULL, 3155 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request, 3156 .get_fan_control_mode = smu_v11_0_get_fan_control_mode, 3157 .set_fan_control_mode = smu_v11_0_set_fan_control_mode, 3158 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent, 3159 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate, 3160 .gfx_off_control = smu_v11_0_gfx_off_control, 3161 .register_irq_handler = smu_v11_0_register_irq_handler, 3162 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme, 3163 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc, 3164 .baco_is_support= sienna_cichlid_is_baco_supported, 3165 .baco_get_state = smu_v11_0_baco_get_state, 3166 .baco_set_state = smu_v11_0_baco_set_state, 3167 .baco_enter = smu_v11_0_baco_enter, 3168 .baco_exit = smu_v11_0_baco_exit, 3169 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported, 3170 .mode1_reset = smu_v11_0_mode1_reset, 3171 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq, 3172 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, 3173 .set_default_od_settings = sienna_cichlid_set_default_od_settings, 3174 .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table, 3175 .run_btc = sienna_cichlid_run_btc, 3176 .set_power_source = smu_v11_0_set_power_source, 3177 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 3178 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 3179 .get_gpu_metrics = sienna_cichlid_get_gpu_metrics, 3180 .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost, 3181 .gfx_ulv_control = smu_v11_0_gfx_ulv_control, 3182 .deep_sleep_control = smu_v11_0_deep_sleep_control, 3183 .get_fan_parameters = sienna_cichlid_get_fan_parameters, 3184 .interrupt_work = smu_v11_0_interrupt_work, 3185 .gpo_control = sienna_cichlid_gpo_control, 3186 }; 3187 3188 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu) 3189 { 3190 smu->ppt_funcs = &sienna_cichlid_ppt_funcs; 3191 smu->message_map = sienna_cichlid_message_map; 3192 smu->clock_map = sienna_cichlid_clk_map; 3193 smu->feature_map = sienna_cichlid_feature_mask_map; 3194 smu->table_map = sienna_cichlid_table_map; 3195 smu->pwr_src_map = sienna_cichlid_pwr_src_map; 3196 smu->workload_map = sienna_cichlid_workload_map; 3197 } 3198