1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include <linux/pci.h> 28 #include <linux/i2c.h> 29 #include "amdgpu.h" 30 #include "amdgpu_dpm.h" 31 #include "amdgpu_smu.h" 32 #include "atomfirmware.h" 33 #include "amdgpu_atomfirmware.h" 34 #include "amdgpu_atombios.h" 35 #include "soc15_common.h" 36 #include "smu_v11_0.h" 37 #include "smu11_driver_if_navi10.h" 38 #include "atom.h" 39 #include "navi10_ppt.h" 40 #include "smu_v11_0_pptable.h" 41 #include "smu_v11_0_ppsmc.h" 42 #include "nbio/nbio_2_3_offset.h" 43 #include "nbio/nbio_2_3_sh_mask.h" 44 #include "thm/thm_11_0_2_offset.h" 45 #include "thm/thm_11_0_2_sh_mask.h" 46 47 #include "asic_reg/mp/mp_11_0_sh_mask.h" 48 #include "smu_cmn.h" 49 #include "smu_11_0_cdr_table.h" 50 51 /* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56 #undef pr_err 57 #undef pr_warn 58 #undef pr_info 59 #undef pr_debug 60 61 #define FEATURE_MASK(feature) (1ULL << feature) 62 #define SMC_DPM_FEATURE ( \ 63 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \ 64 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 65 FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT) | \ 66 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 70 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)) 71 72 #define SMU_11_0_GFX_BUSY_THRESHOLD 15 73 74 static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = { 75 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 76 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 77 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 78 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0), 79 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), 80 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 81 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 82 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 0), 83 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 0), 84 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 0), 85 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 0), 86 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1), 87 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1), 88 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 0), 89 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 90 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 91 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 92 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 93 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 94 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 95 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 96 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 97 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable, 0), 98 MSG_MAP(RunBtc, PPSMC_MSG_RunBtc, 0), 99 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), 100 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1), 101 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), 102 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0), 103 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 104 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), 105 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), 106 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 107 MSG_MAP(SetMemoryChannelConfig, PPSMC_MSG_SetMemoryChannelConfig, 0), 108 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0), 109 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0), 110 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0), 111 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0), 112 MSG_MAP(SetMinDeepSleepDcefclk, PPSMC_MSG_SetMinDeepSleepDcefclk, 0), 113 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0), 114 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0), 115 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0), 116 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0), 117 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1), 118 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 119 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 120 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 121 MSG_MAP(ConfigureGfxDidt, PPSMC_MSG_ConfigureGfxDidt, 0), 122 MSG_MAP(NumOfDisplays, PPSMC_MSG_NumOfDisplays, 0), 123 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0), 124 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0), 125 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 126 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 127 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 128 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1), 129 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0), 130 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0), 131 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset, 0), 132 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown, 0), 133 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 134 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 135 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 136 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 137 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0), 138 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0), 139 MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE,PPSMC_MSG_DALDisableDummyPstateChange, 0), 140 MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALEnableDummyPstateChange, 0), 141 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0), 142 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0), 143 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0), 144 MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH, PPSMC_MSG_SetDriverDummyTableDramAddrHigh, 0), 145 MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW, PPSMC_MSG_SetDriverDummyTableDramAddrLow, 0), 146 MSG_MAP(GET_UMC_FW_WA, PPSMC_MSG_GetUMCFWWA, 0), 147 }; 148 149 static struct cmn2asic_mapping navi10_clk_map[SMU_CLK_COUNT] = { 150 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 151 CLK_MAP(SCLK, PPCLK_GFXCLK), 152 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 153 CLK_MAP(FCLK, PPCLK_SOCCLK), 154 CLK_MAP(UCLK, PPCLK_UCLK), 155 CLK_MAP(MCLK, PPCLK_UCLK), 156 CLK_MAP(DCLK, PPCLK_DCLK), 157 CLK_MAP(VCLK, PPCLK_VCLK), 158 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK), 159 CLK_MAP(DISPCLK, PPCLK_DISPCLK), 160 CLK_MAP(PIXCLK, PPCLK_PIXCLK), 161 CLK_MAP(PHYCLK, PPCLK_PHYCLK), 162 }; 163 164 static struct cmn2asic_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = { 165 FEA_MAP(DPM_PREFETCHER), 166 FEA_MAP(DPM_GFXCLK), 167 FEA_MAP(DPM_GFX_PACE), 168 FEA_MAP(DPM_UCLK), 169 FEA_MAP(DPM_SOCCLK), 170 FEA_MAP(DPM_MP0CLK), 171 FEA_MAP(DPM_LINK), 172 FEA_MAP(DPM_DCEFCLK), 173 FEA_MAP(MEM_VDDCI_SCALING), 174 FEA_MAP(MEM_MVDD_SCALING), 175 FEA_MAP(DS_GFXCLK), 176 FEA_MAP(DS_SOCCLK), 177 FEA_MAP(DS_LCLK), 178 FEA_MAP(DS_DCEFCLK), 179 FEA_MAP(DS_UCLK), 180 FEA_MAP(GFX_ULV), 181 FEA_MAP(FW_DSTATE), 182 FEA_MAP(GFXOFF), 183 FEA_MAP(BACO), 184 FEA_MAP(VCN_PG), 185 FEA_MAP(JPEG_PG), 186 FEA_MAP(USB_PG), 187 FEA_MAP(RSMU_SMN_CG), 188 FEA_MAP(PPT), 189 FEA_MAP(TDC), 190 FEA_MAP(GFX_EDC), 191 FEA_MAP(APCC_PLUS), 192 FEA_MAP(GTHR), 193 FEA_MAP(ACDC), 194 FEA_MAP(VR0HOT), 195 FEA_MAP(VR1HOT), 196 FEA_MAP(FW_CTF), 197 FEA_MAP(FAN_CONTROL), 198 FEA_MAP(THERMAL), 199 FEA_MAP(GFX_DCS), 200 FEA_MAP(RM), 201 FEA_MAP(LED_DISPLAY), 202 FEA_MAP(GFX_SS), 203 FEA_MAP(OUT_OF_BAND_MONITOR), 204 FEA_MAP(TEMP_DEPENDENT_VMIN), 205 FEA_MAP(MMHUB_PG), 206 FEA_MAP(ATHUB_PG), 207 FEA_MAP(APCC_DFLL), 208 }; 209 210 static struct cmn2asic_mapping navi10_table_map[SMU_TABLE_COUNT] = { 211 TAB_MAP(PPTABLE), 212 TAB_MAP(WATERMARKS), 213 TAB_MAP(AVFS), 214 TAB_MAP(AVFS_PSM_DEBUG), 215 TAB_MAP(AVFS_FUSE_OVERRIDE), 216 TAB_MAP(PMSTATUSLOG), 217 TAB_MAP(SMU_METRICS), 218 TAB_MAP(DRIVER_SMU_CONFIG), 219 TAB_MAP(ACTIVITY_MONITOR_COEFF), 220 TAB_MAP(OVERDRIVE), 221 TAB_MAP(I2C_COMMANDS), 222 TAB_MAP(PACE), 223 }; 224 225 static struct cmn2asic_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { 226 PWR_MAP(AC), 227 PWR_MAP(DC), 228 }; 229 230 static struct cmn2asic_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 231 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), 232 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 233 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 234 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 235 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 236 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 237 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 238 }; 239 240 static const uint8_t navi1x_throttler_map[] = { 241 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT), 242 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT), 243 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 244 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 245 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 246 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT), 247 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 248 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT), 249 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT), 250 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 251 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 252 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 253 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 254 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT), 255 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT), 256 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), 257 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT), 258 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT), 259 }; 260 261 262 static bool is_asic_secure(struct smu_context *smu) 263 { 264 struct amdgpu_device *adev = smu->adev; 265 bool is_secure = true; 266 uint32_t mp0_fw_intf; 267 268 mp0_fw_intf = RREG32_PCIE(MP0_Public | 269 (smnMP0_FW_INTF & 0xffffffff)); 270 271 if (!(mp0_fw_intf & (1 << 19))) 272 is_secure = false; 273 274 return is_secure; 275 } 276 277 static int 278 navi10_get_allowed_feature_mask(struct smu_context *smu, 279 uint32_t *feature_mask, uint32_t num) 280 { 281 struct amdgpu_device *adev = smu->adev; 282 283 if (num > 2) 284 return -EINVAL; 285 286 memset(feature_mask, 0, sizeof(uint32_t) * num); 287 288 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) 289 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) 290 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) 291 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) 292 | FEATURE_MASK(FEATURE_PPT_BIT) 293 | FEATURE_MASK(FEATURE_TDC_BIT) 294 | FEATURE_MASK(FEATURE_GFX_EDC_BIT) 295 | FEATURE_MASK(FEATURE_APCC_PLUS_BIT) 296 | FEATURE_MASK(FEATURE_VR0HOT_BIT) 297 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) 298 | FEATURE_MASK(FEATURE_THERMAL_BIT) 299 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT) 300 | FEATURE_MASK(FEATURE_DS_LCLK_BIT) 301 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) 302 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) 303 | FEATURE_MASK(FEATURE_BACO_BIT) 304 | FEATURE_MASK(FEATURE_GFX_SS_BIT) 305 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) 306 | FEATURE_MASK(FEATURE_FW_CTF_BIT) 307 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT); 308 309 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) 310 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 311 312 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) 313 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); 314 315 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) 316 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); 317 318 if (adev->pm.pp_feature & PP_ULV_MASK) 319 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); 320 321 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) 322 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 323 324 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 325 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); 326 327 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) 328 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); 329 330 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB) 331 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT); 332 333 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN) 334 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT); 335 336 if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG) 337 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT); 338 339 if (smu->dc_controlled_by_gpio) 340 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT); 341 342 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) 343 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 344 345 /* DPM UCLK enablement should be skipped for navi10 A0 secure board */ 346 if (!(is_asic_secure(smu) && 347 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && 348 (adev->rev_id == 0)) && 349 (adev->pm.pp_feature & PP_MCLK_DPM_MASK)) 350 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) 351 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) 352 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); 353 354 /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */ 355 if (is_asic_secure(smu) && 356 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && 357 (adev->rev_id == 0)) 358 *(uint64_t *)feature_mask &= 359 ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT); 360 361 return 0; 362 } 363 364 static void navi10_check_bxco_support(struct smu_context *smu) 365 { 366 struct smu_table_context *table_context = &smu->smu_table; 367 struct smu_11_0_powerplay_table *powerplay_table = 368 table_context->power_play_table; 369 struct smu_baco_context *smu_baco = &smu->smu_baco; 370 struct amdgpu_device *adev = smu->adev; 371 uint32_t val; 372 373 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO || 374 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) { 375 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); 376 smu_baco->platform_support = 377 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : 378 false; 379 } 380 } 381 382 static int navi10_check_powerplay_table(struct smu_context *smu) 383 { 384 struct smu_table_context *table_context = &smu->smu_table; 385 struct smu_11_0_powerplay_table *powerplay_table = 386 table_context->power_play_table; 387 388 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC) 389 smu->dc_controlled_by_gpio = true; 390 391 navi10_check_bxco_support(smu); 392 393 table_context->thermal_controller_type = 394 powerplay_table->thermal_controller_type; 395 396 /* 397 * Instead of having its own buffer space and get overdrive_table copied, 398 * smu->od_settings just points to the actual overdrive_table 399 */ 400 smu->od_settings = &powerplay_table->overdrive_table; 401 402 return 0; 403 } 404 405 static int navi10_append_powerplay_table(struct smu_context *smu) 406 { 407 struct amdgpu_device *adev = smu->adev; 408 struct smu_table_context *table_context = &smu->smu_table; 409 PPTable_t *smc_pptable = table_context->driver_pptable; 410 struct atom_smc_dpm_info_v4_5 *smc_dpm_table; 411 struct atom_smc_dpm_info_v4_7 *smc_dpm_table_v4_7; 412 int index, ret; 413 414 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 415 smc_dpm_info); 416 417 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL, 418 (uint8_t **)&smc_dpm_table); 419 if (ret) 420 return ret; 421 422 dev_info(adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n", 423 smc_dpm_table->table_header.format_revision, 424 smc_dpm_table->table_header.content_revision); 425 426 if (smc_dpm_table->table_header.format_revision != 4) { 427 dev_err(adev->dev, "smc_dpm_info table format revision is not 4!\n"); 428 return -EINVAL; 429 } 430 431 switch (smc_dpm_table->table_header.content_revision) { 432 case 5: /* nv10 and nv14 */ 433 smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved, 434 smc_dpm_table, I2cControllers); 435 break; 436 case 7: /* nv12 */ 437 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL, 438 (uint8_t **)&smc_dpm_table_v4_7); 439 if (ret) 440 return ret; 441 smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved, 442 smc_dpm_table_v4_7, I2cControllers); 443 break; 444 default: 445 dev_err(smu->adev->dev, "smc_dpm_info with unsupported content revision %d!\n", 446 smc_dpm_table->table_header.content_revision); 447 return -EINVAL; 448 } 449 450 if (adev->pm.pp_feature & PP_GFXOFF_MASK) { 451 /* TODO: remove it once SMU fw fix it */ 452 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN; 453 } 454 455 return 0; 456 } 457 458 static int navi10_store_powerplay_table(struct smu_context *smu) 459 { 460 struct smu_table_context *table_context = &smu->smu_table; 461 struct smu_11_0_powerplay_table *powerplay_table = 462 table_context->power_play_table; 463 464 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 465 sizeof(PPTable_t)); 466 467 return 0; 468 } 469 470 static int navi10_setup_pptable(struct smu_context *smu) 471 { 472 int ret = 0; 473 474 ret = smu_v11_0_setup_pptable(smu); 475 if (ret) 476 return ret; 477 478 ret = navi10_store_powerplay_table(smu); 479 if (ret) 480 return ret; 481 482 ret = navi10_append_powerplay_table(smu); 483 if (ret) 484 return ret; 485 486 ret = navi10_check_powerplay_table(smu); 487 if (ret) 488 return ret; 489 490 return ret; 491 } 492 493 static int navi10_tables_init(struct smu_context *smu) 494 { 495 struct smu_table_context *smu_table = &smu->smu_table; 496 struct smu_table *tables = smu_table->tables; 497 struct smu_table *dummy_read_1_table = 498 &smu_table->dummy_read_1_table; 499 500 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 501 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 502 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 503 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 504 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_NV1X_t), 505 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 506 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 507 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 508 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t), 509 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 510 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 511 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 512 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, 513 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE, 514 AMDGPU_GEM_DOMAIN_VRAM); 515 SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfig_t), 516 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 517 518 dummy_read_1_table->size = 0x40000; 519 dummy_read_1_table->align = PAGE_SIZE; 520 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 521 522 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_NV1X_t), 523 GFP_KERNEL); 524 if (!smu_table->metrics_table) 525 goto err0_out; 526 smu_table->metrics_time = 0; 527 528 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 529 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 530 if (!smu_table->gpu_metrics_table) 531 goto err1_out; 532 533 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 534 if (!smu_table->watermarks_table) 535 goto err2_out; 536 537 smu_table->driver_smu_config_table = 538 kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL); 539 if (!smu_table->driver_smu_config_table) 540 goto err3_out; 541 542 return 0; 543 544 err3_out: 545 kfree(smu_table->watermarks_table); 546 err2_out: 547 kfree(smu_table->gpu_metrics_table); 548 err1_out: 549 kfree(smu_table->metrics_table); 550 err0_out: 551 return -ENOMEM; 552 } 553 554 static int navi10_get_legacy_smu_metrics_data(struct smu_context *smu, 555 MetricsMember_t member, 556 uint32_t *value) 557 { 558 struct smu_table_context *smu_table= &smu->smu_table; 559 SmuMetrics_legacy_t *metrics = 560 (SmuMetrics_legacy_t *)smu_table->metrics_table; 561 int ret = 0; 562 563 ret = smu_cmn_get_metrics_table(smu, 564 NULL, 565 false); 566 if (ret) 567 return ret; 568 569 switch (member) { 570 case METRICS_CURR_GFXCLK: 571 *value = metrics->CurrClock[PPCLK_GFXCLK]; 572 break; 573 case METRICS_CURR_SOCCLK: 574 *value = metrics->CurrClock[PPCLK_SOCCLK]; 575 break; 576 case METRICS_CURR_UCLK: 577 *value = metrics->CurrClock[PPCLK_UCLK]; 578 break; 579 case METRICS_CURR_VCLK: 580 *value = metrics->CurrClock[PPCLK_VCLK]; 581 break; 582 case METRICS_CURR_DCLK: 583 *value = metrics->CurrClock[PPCLK_DCLK]; 584 break; 585 case METRICS_CURR_DCEFCLK: 586 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 587 break; 588 case METRICS_AVERAGE_GFXCLK: 589 *value = metrics->AverageGfxclkFrequency; 590 break; 591 case METRICS_AVERAGE_SOCCLK: 592 *value = metrics->AverageSocclkFrequency; 593 break; 594 case METRICS_AVERAGE_UCLK: 595 *value = metrics->AverageUclkFrequency; 596 break; 597 case METRICS_AVERAGE_GFXACTIVITY: 598 *value = metrics->AverageGfxActivity; 599 break; 600 case METRICS_AVERAGE_MEMACTIVITY: 601 *value = metrics->AverageUclkActivity; 602 break; 603 case METRICS_AVERAGE_SOCKETPOWER: 604 *value = metrics->AverageSocketPower << 8; 605 break; 606 case METRICS_TEMPERATURE_EDGE: 607 *value = metrics->TemperatureEdge * 608 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 609 break; 610 case METRICS_TEMPERATURE_HOTSPOT: 611 *value = metrics->TemperatureHotspot * 612 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 613 break; 614 case METRICS_TEMPERATURE_MEM: 615 *value = metrics->TemperatureMem * 616 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 617 break; 618 case METRICS_TEMPERATURE_VRGFX: 619 *value = metrics->TemperatureVrGfx * 620 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 621 break; 622 case METRICS_TEMPERATURE_VRSOC: 623 *value = metrics->TemperatureVrSoc * 624 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 625 break; 626 case METRICS_THROTTLER_STATUS: 627 *value = metrics->ThrottlerStatus; 628 break; 629 case METRICS_CURR_FANSPEED: 630 *value = metrics->CurrFanSpeed; 631 break; 632 default: 633 *value = UINT_MAX; 634 break; 635 } 636 637 return ret; 638 } 639 640 static int navi10_get_smu_metrics_data(struct smu_context *smu, 641 MetricsMember_t member, 642 uint32_t *value) 643 { 644 struct smu_table_context *smu_table= &smu->smu_table; 645 SmuMetrics_t *metrics = 646 (SmuMetrics_t *)smu_table->metrics_table; 647 int ret = 0; 648 649 ret = smu_cmn_get_metrics_table(smu, 650 NULL, 651 false); 652 if (ret) 653 return ret; 654 655 switch (member) { 656 case METRICS_CURR_GFXCLK: 657 *value = metrics->CurrClock[PPCLK_GFXCLK]; 658 break; 659 case METRICS_CURR_SOCCLK: 660 *value = metrics->CurrClock[PPCLK_SOCCLK]; 661 break; 662 case METRICS_CURR_UCLK: 663 *value = metrics->CurrClock[PPCLK_UCLK]; 664 break; 665 case METRICS_CURR_VCLK: 666 *value = metrics->CurrClock[PPCLK_VCLK]; 667 break; 668 case METRICS_CURR_DCLK: 669 *value = metrics->CurrClock[PPCLK_DCLK]; 670 break; 671 case METRICS_CURR_DCEFCLK: 672 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 673 break; 674 case METRICS_AVERAGE_GFXCLK: 675 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 676 *value = metrics->AverageGfxclkFrequencyPreDs; 677 else 678 *value = metrics->AverageGfxclkFrequencyPostDs; 679 break; 680 case METRICS_AVERAGE_SOCCLK: 681 *value = metrics->AverageSocclkFrequency; 682 break; 683 case METRICS_AVERAGE_UCLK: 684 *value = metrics->AverageUclkFrequencyPostDs; 685 break; 686 case METRICS_AVERAGE_GFXACTIVITY: 687 *value = metrics->AverageGfxActivity; 688 break; 689 case METRICS_AVERAGE_MEMACTIVITY: 690 *value = metrics->AverageUclkActivity; 691 break; 692 case METRICS_AVERAGE_SOCKETPOWER: 693 *value = metrics->AverageSocketPower << 8; 694 break; 695 case METRICS_TEMPERATURE_EDGE: 696 *value = metrics->TemperatureEdge * 697 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 698 break; 699 case METRICS_TEMPERATURE_HOTSPOT: 700 *value = metrics->TemperatureHotspot * 701 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 702 break; 703 case METRICS_TEMPERATURE_MEM: 704 *value = metrics->TemperatureMem * 705 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 706 break; 707 case METRICS_TEMPERATURE_VRGFX: 708 *value = metrics->TemperatureVrGfx * 709 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 710 break; 711 case METRICS_TEMPERATURE_VRSOC: 712 *value = metrics->TemperatureVrSoc * 713 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 714 break; 715 case METRICS_THROTTLER_STATUS: 716 *value = metrics->ThrottlerStatus; 717 break; 718 case METRICS_CURR_FANSPEED: 719 *value = metrics->CurrFanSpeed; 720 break; 721 default: 722 *value = UINT_MAX; 723 break; 724 } 725 726 return ret; 727 } 728 729 static int navi12_get_legacy_smu_metrics_data(struct smu_context *smu, 730 MetricsMember_t member, 731 uint32_t *value) 732 { 733 struct smu_table_context *smu_table= &smu->smu_table; 734 SmuMetrics_NV12_legacy_t *metrics = 735 (SmuMetrics_NV12_legacy_t *)smu_table->metrics_table; 736 int ret = 0; 737 738 ret = smu_cmn_get_metrics_table(smu, 739 NULL, 740 false); 741 if (ret) 742 return ret; 743 744 switch (member) { 745 case METRICS_CURR_GFXCLK: 746 *value = metrics->CurrClock[PPCLK_GFXCLK]; 747 break; 748 case METRICS_CURR_SOCCLK: 749 *value = metrics->CurrClock[PPCLK_SOCCLK]; 750 break; 751 case METRICS_CURR_UCLK: 752 *value = metrics->CurrClock[PPCLK_UCLK]; 753 break; 754 case METRICS_CURR_VCLK: 755 *value = metrics->CurrClock[PPCLK_VCLK]; 756 break; 757 case METRICS_CURR_DCLK: 758 *value = metrics->CurrClock[PPCLK_DCLK]; 759 break; 760 case METRICS_CURR_DCEFCLK: 761 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 762 break; 763 case METRICS_AVERAGE_GFXCLK: 764 *value = metrics->AverageGfxclkFrequency; 765 break; 766 case METRICS_AVERAGE_SOCCLK: 767 *value = metrics->AverageSocclkFrequency; 768 break; 769 case METRICS_AVERAGE_UCLK: 770 *value = metrics->AverageUclkFrequency; 771 break; 772 case METRICS_AVERAGE_GFXACTIVITY: 773 *value = metrics->AverageGfxActivity; 774 break; 775 case METRICS_AVERAGE_MEMACTIVITY: 776 *value = metrics->AverageUclkActivity; 777 break; 778 case METRICS_AVERAGE_SOCKETPOWER: 779 *value = metrics->AverageSocketPower << 8; 780 break; 781 case METRICS_TEMPERATURE_EDGE: 782 *value = metrics->TemperatureEdge * 783 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 784 break; 785 case METRICS_TEMPERATURE_HOTSPOT: 786 *value = metrics->TemperatureHotspot * 787 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 788 break; 789 case METRICS_TEMPERATURE_MEM: 790 *value = metrics->TemperatureMem * 791 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 792 break; 793 case METRICS_TEMPERATURE_VRGFX: 794 *value = metrics->TemperatureVrGfx * 795 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 796 break; 797 case METRICS_TEMPERATURE_VRSOC: 798 *value = metrics->TemperatureVrSoc * 799 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 800 break; 801 case METRICS_THROTTLER_STATUS: 802 *value = metrics->ThrottlerStatus; 803 break; 804 case METRICS_CURR_FANSPEED: 805 *value = metrics->CurrFanSpeed; 806 break; 807 default: 808 *value = UINT_MAX; 809 break; 810 } 811 812 return ret; 813 } 814 815 static int navi12_get_smu_metrics_data(struct smu_context *smu, 816 MetricsMember_t member, 817 uint32_t *value) 818 { 819 struct smu_table_context *smu_table= &smu->smu_table; 820 SmuMetrics_NV12_t *metrics = 821 (SmuMetrics_NV12_t *)smu_table->metrics_table; 822 int ret = 0; 823 824 ret = smu_cmn_get_metrics_table(smu, 825 NULL, 826 false); 827 if (ret) 828 return ret; 829 830 switch (member) { 831 case METRICS_CURR_GFXCLK: 832 *value = metrics->CurrClock[PPCLK_GFXCLK]; 833 break; 834 case METRICS_CURR_SOCCLK: 835 *value = metrics->CurrClock[PPCLK_SOCCLK]; 836 break; 837 case METRICS_CURR_UCLK: 838 *value = metrics->CurrClock[PPCLK_UCLK]; 839 break; 840 case METRICS_CURR_VCLK: 841 *value = metrics->CurrClock[PPCLK_VCLK]; 842 break; 843 case METRICS_CURR_DCLK: 844 *value = metrics->CurrClock[PPCLK_DCLK]; 845 break; 846 case METRICS_CURR_DCEFCLK: 847 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 848 break; 849 case METRICS_AVERAGE_GFXCLK: 850 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 851 *value = metrics->AverageGfxclkFrequencyPreDs; 852 else 853 *value = metrics->AverageGfxclkFrequencyPostDs; 854 break; 855 case METRICS_AVERAGE_SOCCLK: 856 *value = metrics->AverageSocclkFrequency; 857 break; 858 case METRICS_AVERAGE_UCLK: 859 *value = metrics->AverageUclkFrequencyPostDs; 860 break; 861 case METRICS_AVERAGE_GFXACTIVITY: 862 *value = metrics->AverageGfxActivity; 863 break; 864 case METRICS_AVERAGE_MEMACTIVITY: 865 *value = metrics->AverageUclkActivity; 866 break; 867 case METRICS_AVERAGE_SOCKETPOWER: 868 *value = metrics->AverageSocketPower << 8; 869 break; 870 case METRICS_TEMPERATURE_EDGE: 871 *value = metrics->TemperatureEdge * 872 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 873 break; 874 case METRICS_TEMPERATURE_HOTSPOT: 875 *value = metrics->TemperatureHotspot * 876 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 877 break; 878 case METRICS_TEMPERATURE_MEM: 879 *value = metrics->TemperatureMem * 880 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 881 break; 882 case METRICS_TEMPERATURE_VRGFX: 883 *value = metrics->TemperatureVrGfx * 884 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 885 break; 886 case METRICS_TEMPERATURE_VRSOC: 887 *value = metrics->TemperatureVrSoc * 888 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 889 break; 890 case METRICS_THROTTLER_STATUS: 891 *value = metrics->ThrottlerStatus; 892 break; 893 case METRICS_CURR_FANSPEED: 894 *value = metrics->CurrFanSpeed; 895 break; 896 default: 897 *value = UINT_MAX; 898 break; 899 } 900 901 return ret; 902 } 903 904 static int navi1x_get_smu_metrics_data(struct smu_context *smu, 905 MetricsMember_t member, 906 uint32_t *value) 907 { 908 struct amdgpu_device *adev = smu->adev; 909 uint32_t smu_version; 910 int ret = 0; 911 912 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 913 if (ret) { 914 dev_err(adev->dev, "Failed to get smu version!\n"); 915 return ret; 916 } 917 918 switch (adev->ip_versions[MP1_HWIP][0]) { 919 case IP_VERSION(11, 0, 9): 920 if (smu_version > 0x00341C00) 921 ret = navi12_get_smu_metrics_data(smu, member, value); 922 else 923 ret = navi12_get_legacy_smu_metrics_data(smu, member, value); 924 break; 925 case IP_VERSION(11, 0, 0): 926 case IP_VERSION(11, 0, 5): 927 default: 928 if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) || 929 ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00)) 930 ret = navi10_get_smu_metrics_data(smu, member, value); 931 else 932 ret = navi10_get_legacy_smu_metrics_data(smu, member, value); 933 break; 934 } 935 936 return ret; 937 } 938 939 static int navi10_allocate_dpm_context(struct smu_context *smu) 940 { 941 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 942 943 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 944 GFP_KERNEL); 945 if (!smu_dpm->dpm_context) 946 return -ENOMEM; 947 948 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 949 950 return 0; 951 } 952 953 static int navi10_init_smc_tables(struct smu_context *smu) 954 { 955 int ret = 0; 956 957 ret = navi10_tables_init(smu); 958 if (ret) 959 return ret; 960 961 ret = navi10_allocate_dpm_context(smu); 962 if (ret) 963 return ret; 964 965 return smu_v11_0_init_smc_tables(smu); 966 } 967 968 static int navi10_set_default_dpm_table(struct smu_context *smu) 969 { 970 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 971 PPTable_t *driver_ppt = smu->smu_table.driver_pptable; 972 struct smu_11_0_dpm_table *dpm_table; 973 int ret = 0; 974 975 /* socclk dpm table setup */ 976 dpm_table = &dpm_context->dpm_tables.soc_table; 977 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 978 ret = smu_v11_0_set_single_dpm_table(smu, 979 SMU_SOCCLK, 980 dpm_table); 981 if (ret) 982 return ret; 983 dpm_table->is_fine_grained = 984 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete; 985 } else { 986 dpm_table->count = 1; 987 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 988 dpm_table->dpm_levels[0].enabled = true; 989 dpm_table->min = dpm_table->dpm_levels[0].value; 990 dpm_table->max = dpm_table->dpm_levels[0].value; 991 } 992 993 /* gfxclk dpm table setup */ 994 dpm_table = &dpm_context->dpm_tables.gfx_table; 995 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 996 ret = smu_v11_0_set_single_dpm_table(smu, 997 SMU_GFXCLK, 998 dpm_table); 999 if (ret) 1000 return ret; 1001 dpm_table->is_fine_grained = 1002 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete; 1003 } else { 1004 dpm_table->count = 1; 1005 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 1006 dpm_table->dpm_levels[0].enabled = true; 1007 dpm_table->min = dpm_table->dpm_levels[0].value; 1008 dpm_table->max = dpm_table->dpm_levels[0].value; 1009 } 1010 1011 /* uclk dpm table setup */ 1012 dpm_table = &dpm_context->dpm_tables.uclk_table; 1013 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1014 ret = smu_v11_0_set_single_dpm_table(smu, 1015 SMU_UCLK, 1016 dpm_table); 1017 if (ret) 1018 return ret; 1019 dpm_table->is_fine_grained = 1020 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete; 1021 } else { 1022 dpm_table->count = 1; 1023 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 1024 dpm_table->dpm_levels[0].enabled = true; 1025 dpm_table->min = dpm_table->dpm_levels[0].value; 1026 dpm_table->max = dpm_table->dpm_levels[0].value; 1027 } 1028 1029 /* vclk dpm table setup */ 1030 dpm_table = &dpm_context->dpm_tables.vclk_table; 1031 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1032 ret = smu_v11_0_set_single_dpm_table(smu, 1033 SMU_VCLK, 1034 dpm_table); 1035 if (ret) 1036 return ret; 1037 dpm_table->is_fine_grained = 1038 !driver_ppt->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete; 1039 } else { 1040 dpm_table->count = 1; 1041 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; 1042 dpm_table->dpm_levels[0].enabled = true; 1043 dpm_table->min = dpm_table->dpm_levels[0].value; 1044 dpm_table->max = dpm_table->dpm_levels[0].value; 1045 } 1046 1047 /* dclk dpm table setup */ 1048 dpm_table = &dpm_context->dpm_tables.dclk_table; 1049 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1050 ret = smu_v11_0_set_single_dpm_table(smu, 1051 SMU_DCLK, 1052 dpm_table); 1053 if (ret) 1054 return ret; 1055 dpm_table->is_fine_grained = 1056 !driver_ppt->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete; 1057 } else { 1058 dpm_table->count = 1; 1059 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; 1060 dpm_table->dpm_levels[0].enabled = true; 1061 dpm_table->min = dpm_table->dpm_levels[0].value; 1062 dpm_table->max = dpm_table->dpm_levels[0].value; 1063 } 1064 1065 /* dcefclk dpm table setup */ 1066 dpm_table = &dpm_context->dpm_tables.dcef_table; 1067 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1068 ret = smu_v11_0_set_single_dpm_table(smu, 1069 SMU_DCEFCLK, 1070 dpm_table); 1071 if (ret) 1072 return ret; 1073 dpm_table->is_fine_grained = 1074 !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete; 1075 } else { 1076 dpm_table->count = 1; 1077 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1078 dpm_table->dpm_levels[0].enabled = true; 1079 dpm_table->min = dpm_table->dpm_levels[0].value; 1080 dpm_table->max = dpm_table->dpm_levels[0].value; 1081 } 1082 1083 /* pixelclk dpm table setup */ 1084 dpm_table = &dpm_context->dpm_tables.pixel_table; 1085 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1086 ret = smu_v11_0_set_single_dpm_table(smu, 1087 SMU_PIXCLK, 1088 dpm_table); 1089 if (ret) 1090 return ret; 1091 dpm_table->is_fine_grained = 1092 !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete; 1093 } else { 1094 dpm_table->count = 1; 1095 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1096 dpm_table->dpm_levels[0].enabled = true; 1097 dpm_table->min = dpm_table->dpm_levels[0].value; 1098 dpm_table->max = dpm_table->dpm_levels[0].value; 1099 } 1100 1101 /* displayclk dpm table setup */ 1102 dpm_table = &dpm_context->dpm_tables.display_table; 1103 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1104 ret = smu_v11_0_set_single_dpm_table(smu, 1105 SMU_DISPCLK, 1106 dpm_table); 1107 if (ret) 1108 return ret; 1109 dpm_table->is_fine_grained = 1110 !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete; 1111 } else { 1112 dpm_table->count = 1; 1113 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1114 dpm_table->dpm_levels[0].enabled = true; 1115 dpm_table->min = dpm_table->dpm_levels[0].value; 1116 dpm_table->max = dpm_table->dpm_levels[0].value; 1117 } 1118 1119 /* phyclk dpm table setup */ 1120 dpm_table = &dpm_context->dpm_tables.phy_table; 1121 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1122 ret = smu_v11_0_set_single_dpm_table(smu, 1123 SMU_PHYCLK, 1124 dpm_table); 1125 if (ret) 1126 return ret; 1127 dpm_table->is_fine_grained = 1128 !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete; 1129 } else { 1130 dpm_table->count = 1; 1131 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1132 dpm_table->dpm_levels[0].enabled = true; 1133 dpm_table->min = dpm_table->dpm_levels[0].value; 1134 dpm_table->max = dpm_table->dpm_levels[0].value; 1135 } 1136 1137 return 0; 1138 } 1139 1140 static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 1141 { 1142 int ret = 0; 1143 1144 if (enable) { 1145 /* vcn dpm on is a prerequisite for vcn power gate messages */ 1146 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1147 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL); 1148 if (ret) 1149 return ret; 1150 } 1151 } else { 1152 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1153 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL); 1154 if (ret) 1155 return ret; 1156 } 1157 } 1158 1159 return ret; 1160 } 1161 1162 static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 1163 { 1164 int ret = 0; 1165 1166 if (enable) { 1167 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 1168 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerUpJpeg, NULL); 1169 if (ret) 1170 return ret; 1171 } 1172 } else { 1173 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 1174 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL); 1175 if (ret) 1176 return ret; 1177 } 1178 } 1179 1180 return ret; 1181 } 1182 1183 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu, 1184 enum smu_clk_type clk_type, 1185 uint32_t *value) 1186 { 1187 MetricsMember_t member_type; 1188 int clk_id = 0; 1189 1190 clk_id = smu_cmn_to_asic_specific_index(smu, 1191 CMN2ASIC_MAPPING_CLK, 1192 clk_type); 1193 if (clk_id < 0) 1194 return clk_id; 1195 1196 switch (clk_id) { 1197 case PPCLK_GFXCLK: 1198 member_type = METRICS_CURR_GFXCLK; 1199 break; 1200 case PPCLK_UCLK: 1201 member_type = METRICS_CURR_UCLK; 1202 break; 1203 case PPCLK_SOCCLK: 1204 member_type = METRICS_CURR_SOCCLK; 1205 break; 1206 case PPCLK_VCLK: 1207 member_type = METRICS_CURR_VCLK; 1208 break; 1209 case PPCLK_DCLK: 1210 member_type = METRICS_CURR_DCLK; 1211 break; 1212 case PPCLK_DCEFCLK: 1213 member_type = METRICS_CURR_DCEFCLK; 1214 break; 1215 default: 1216 return -EINVAL; 1217 } 1218 1219 return navi1x_get_smu_metrics_data(smu, 1220 member_type, 1221 value); 1222 } 1223 1224 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) 1225 { 1226 PPTable_t *pptable = smu->smu_table.driver_pptable; 1227 DpmDescriptor_t *dpm_desc = NULL; 1228 uint32_t clk_index = 0; 1229 1230 clk_index = smu_cmn_to_asic_specific_index(smu, 1231 CMN2ASIC_MAPPING_CLK, 1232 clk_type); 1233 dpm_desc = &pptable->DpmDescriptor[clk_index]; 1234 1235 /* 0 - Fine grained DPM, 1 - Discrete DPM */ 1236 return dpm_desc->SnapToDiscrete == 0; 1237 } 1238 1239 static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap) 1240 { 1241 return od_table->cap[cap]; 1242 } 1243 1244 static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table, 1245 enum SMU_11_0_ODSETTING_ID setting, 1246 uint32_t *min, uint32_t *max) 1247 { 1248 if (min) 1249 *min = od_table->min[setting]; 1250 if (max) 1251 *max = od_table->max[setting]; 1252 } 1253 1254 static int navi10_emit_clk_levels(struct smu_context *smu, 1255 enum smu_clk_type clk_type, 1256 char *buf, 1257 int *offset) 1258 { 1259 uint16_t *curve_settings; 1260 int ret = 0; 1261 uint32_t cur_value = 0, value = 0; 1262 uint32_t freq_values[3] = {0}; 1263 uint32_t i, levels, mark_index = 0, count = 0; 1264 struct smu_table_context *table_context = &smu->smu_table; 1265 uint32_t gen_speed, lane_width; 1266 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1267 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1268 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable; 1269 OverDriveTable_t *od_table = 1270 (OverDriveTable_t *)table_context->overdrive_table; 1271 struct smu_11_0_overdrive_table *od_settings = smu->od_settings; 1272 uint32_t min_value, max_value; 1273 1274 switch (clk_type) { 1275 case SMU_GFXCLK: 1276 case SMU_SCLK: 1277 case SMU_SOCCLK: 1278 case SMU_MCLK: 1279 case SMU_UCLK: 1280 case SMU_FCLK: 1281 case SMU_VCLK: 1282 case SMU_DCLK: 1283 case SMU_DCEFCLK: 1284 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value); 1285 if (ret) 1286 return ret; 1287 1288 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); 1289 if (ret) 1290 return ret; 1291 1292 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) { 1293 for (i = 0; i < count; i++) { 1294 ret = smu_v11_0_get_dpm_freq_by_index(smu, 1295 clk_type, i, &value); 1296 if (ret) 1297 return ret; 1298 1299 *offset += sysfs_emit_at(buf, *offset, 1300 "%d: %uMhz %s\n", 1301 i, value, 1302 cur_value == value ? "*" : ""); 1303 } 1304 } else { 1305 ret = smu_v11_0_get_dpm_freq_by_index(smu, 1306 clk_type, 0, &freq_values[0]); 1307 if (ret) 1308 return ret; 1309 ret = smu_v11_0_get_dpm_freq_by_index(smu, 1310 clk_type, 1311 count - 1, 1312 &freq_values[2]); 1313 if (ret) 1314 return ret; 1315 1316 freq_values[1] = cur_value; 1317 mark_index = cur_value == freq_values[0] ? 0 : 1318 cur_value == freq_values[2] ? 2 : 1; 1319 1320 levels = 3; 1321 if (mark_index != 1) { 1322 levels = 2; 1323 freq_values[1] = freq_values[2]; 1324 } 1325 1326 for (i = 0; i < levels; i++) { 1327 *offset += sysfs_emit_at(buf, *offset, 1328 "%d: %uMhz %s\n", 1329 i, freq_values[i], 1330 i == mark_index ? "*" : ""); 1331 } 1332 } 1333 break; 1334 case SMU_PCIE: 1335 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); 1336 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); 1337 for (i = 0; i < NUM_LINK_LEVELS; i++) { 1338 *offset += sysfs_emit_at(buf, *offset, "%d: %s %s %dMhz %s\n", i, 1339 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," : 1340 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," : 1341 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," : 1342 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "", 1343 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" : 1344 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" : 1345 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" : 1346 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" : 1347 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" : 1348 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "", 1349 pptable->LclkFreq[i], 1350 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && 1351 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? 1352 "*" : ""); 1353 } 1354 break; 1355 case SMU_OD_SCLK: 1356 if (!smu->od_enabled || !od_table || !od_settings) 1357 return -EOPNOTSUPP; 1358 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) 1359 break; 1360 *offset += sysfs_emit_at(buf, *offset, "OD_SCLK:\n0: %uMhz\n1: %uMhz\n", 1361 od_table->GfxclkFmin, od_table->GfxclkFmax); 1362 break; 1363 case SMU_OD_MCLK: 1364 if (!smu->od_enabled || !od_table || !od_settings) 1365 return -EOPNOTSUPP; 1366 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) 1367 break; 1368 *offset += sysfs_emit_at(buf, *offset, "OD_MCLK:\n1: %uMHz\n", od_table->UclkFmax); 1369 break; 1370 case SMU_OD_VDDC_CURVE: 1371 if (!smu->od_enabled || !od_table || !od_settings) 1372 return -EOPNOTSUPP; 1373 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) 1374 break; 1375 *offset += sysfs_emit_at(buf, *offset, "OD_VDDC_CURVE:\n"); 1376 for (i = 0; i < 3; i++) { 1377 switch (i) { 1378 case 0: 1379 curve_settings = &od_table->GfxclkFreq1; 1380 break; 1381 case 1: 1382 curve_settings = &od_table->GfxclkFreq2; 1383 break; 1384 case 2: 1385 curve_settings = &od_table->GfxclkFreq3; 1386 break; 1387 default: 1388 break; 1389 } 1390 *offset += sysfs_emit_at(buf, *offset, "%d: %uMHz %umV\n", 1391 i, curve_settings[0], 1392 curve_settings[1] / NAVI10_VOLTAGE_SCALE); 1393 } 1394 break; 1395 case SMU_OD_RANGE: 1396 if (!smu->od_enabled || !od_table || !od_settings) 1397 return -EOPNOTSUPP; 1398 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_RANGE"); 1399 1400 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) { 1401 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN, 1402 &min_value, NULL); 1403 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX, 1404 NULL, &max_value); 1405 *offset += sysfs_emit_at(buf, *offset, "SCLK: %7uMhz %10uMhz\n", 1406 min_value, max_value); 1407 } 1408 1409 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) { 1410 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX, 1411 &min_value, &max_value); 1412 *offset += sysfs_emit_at(buf, *offset, "MCLK: %7uMhz %10uMhz\n", 1413 min_value, max_value); 1414 } 1415 1416 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) { 1417 navi10_od_setting_get_range(od_settings, 1418 SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1, 1419 &min_value, &max_value); 1420 *offset += sysfs_emit_at(buf, *offset, 1421 "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n", 1422 min_value, max_value); 1423 navi10_od_setting_get_range(od_settings, 1424 SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1, 1425 &min_value, &max_value); 1426 *offset += sysfs_emit_at(buf, *offset, 1427 "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n", 1428 min_value, max_value); 1429 navi10_od_setting_get_range(od_settings, 1430 SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2, 1431 &min_value, &max_value); 1432 *offset += sysfs_emit_at(buf, *offset, 1433 "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n", 1434 min_value, max_value); 1435 navi10_od_setting_get_range(od_settings, 1436 SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2, 1437 &min_value, &max_value); 1438 *offset += sysfs_emit_at(buf, *offset, 1439 "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n", 1440 min_value, max_value); 1441 navi10_od_setting_get_range(od_settings, 1442 SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3, 1443 &min_value, &max_value); 1444 *offset += sysfs_emit_at(buf, *offset, 1445 "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n", 1446 min_value, max_value); 1447 navi10_od_setting_get_range(od_settings, 1448 SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3, 1449 &min_value, &max_value); 1450 *offset += sysfs_emit_at(buf, *offset, 1451 "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n", 1452 min_value, max_value); 1453 } 1454 1455 break; 1456 default: 1457 break; 1458 } 1459 1460 return 0; 1461 } 1462 1463 static int navi10_print_clk_levels(struct smu_context *smu, 1464 enum smu_clk_type clk_type, char *buf) 1465 { 1466 uint16_t *curve_settings; 1467 int i, levels, size = 0, ret = 0; 1468 uint32_t cur_value = 0, value = 0, count = 0; 1469 uint32_t freq_values[3] = {0}; 1470 uint32_t mark_index = 0; 1471 struct smu_table_context *table_context = &smu->smu_table; 1472 uint32_t gen_speed, lane_width; 1473 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1474 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1475 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable; 1476 OverDriveTable_t *od_table = 1477 (OverDriveTable_t *)table_context->overdrive_table; 1478 struct smu_11_0_overdrive_table *od_settings = smu->od_settings; 1479 uint32_t min_value, max_value; 1480 1481 smu_cmn_get_sysfs_buf(&buf, &size); 1482 1483 switch (clk_type) { 1484 case SMU_GFXCLK: 1485 case SMU_SCLK: 1486 case SMU_SOCCLK: 1487 case SMU_MCLK: 1488 case SMU_UCLK: 1489 case SMU_FCLK: 1490 case SMU_VCLK: 1491 case SMU_DCLK: 1492 case SMU_DCEFCLK: 1493 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value); 1494 if (ret) 1495 return size; 1496 1497 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); 1498 if (ret) 1499 return size; 1500 1501 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) { 1502 for (i = 0; i < count; i++) { 1503 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); 1504 if (ret) 1505 return size; 1506 1507 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 1508 cur_value == value ? "*" : ""); 1509 } 1510 } else { 1511 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]); 1512 if (ret) 1513 return size; 1514 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]); 1515 if (ret) 1516 return size; 1517 1518 freq_values[1] = cur_value; 1519 mark_index = cur_value == freq_values[0] ? 0 : 1520 cur_value == freq_values[2] ? 2 : 1; 1521 1522 levels = 3; 1523 if (mark_index != 1) { 1524 levels = 2; 1525 freq_values[1] = freq_values[2]; 1526 } 1527 1528 for (i = 0; i < levels; i++) { 1529 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i], 1530 i == mark_index ? "*" : ""); 1531 } 1532 } 1533 break; 1534 case SMU_PCIE: 1535 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); 1536 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); 1537 for (i = 0; i < NUM_LINK_LEVELS; i++) 1538 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i, 1539 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," : 1540 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," : 1541 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," : 1542 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "", 1543 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" : 1544 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" : 1545 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" : 1546 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" : 1547 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" : 1548 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "", 1549 pptable->LclkFreq[i], 1550 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && 1551 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? 1552 "*" : ""); 1553 break; 1554 case SMU_OD_SCLK: 1555 if (!smu->od_enabled || !od_table || !od_settings) 1556 break; 1557 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) 1558 break; 1559 size += sysfs_emit_at(buf, size, "OD_SCLK:\n"); 1560 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", 1561 od_table->GfxclkFmin, od_table->GfxclkFmax); 1562 break; 1563 case SMU_OD_MCLK: 1564 if (!smu->od_enabled || !od_table || !od_settings) 1565 break; 1566 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) 1567 break; 1568 size += sysfs_emit_at(buf, size, "OD_MCLK:\n"); 1569 size += sysfs_emit_at(buf, size, "1: %uMHz\n", od_table->UclkFmax); 1570 break; 1571 case SMU_OD_VDDC_CURVE: 1572 if (!smu->od_enabled || !od_table || !od_settings) 1573 break; 1574 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) 1575 break; 1576 size += sysfs_emit_at(buf, size, "OD_VDDC_CURVE:\n"); 1577 for (i = 0; i < 3; i++) { 1578 switch (i) { 1579 case 0: 1580 curve_settings = &od_table->GfxclkFreq1; 1581 break; 1582 case 1: 1583 curve_settings = &od_table->GfxclkFreq2; 1584 break; 1585 case 2: 1586 curve_settings = &od_table->GfxclkFreq3; 1587 break; 1588 default: 1589 break; 1590 } 1591 size += sysfs_emit_at(buf, size, "%d: %uMHz %umV\n", 1592 i, curve_settings[0], 1593 curve_settings[1] / NAVI10_VOLTAGE_SCALE); 1594 } 1595 break; 1596 case SMU_OD_RANGE: 1597 if (!smu->od_enabled || !od_table || !od_settings) 1598 break; 1599 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 1600 1601 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) { 1602 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN, 1603 &min_value, NULL); 1604 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX, 1605 NULL, &max_value); 1606 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 1607 min_value, max_value); 1608 } 1609 1610 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) { 1611 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX, 1612 &min_value, &max_value); 1613 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n", 1614 min_value, max_value); 1615 } 1616 1617 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) { 1618 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1, 1619 &min_value, &max_value); 1620 size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n", 1621 min_value, max_value); 1622 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1, 1623 &min_value, &max_value); 1624 size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n", 1625 min_value, max_value); 1626 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2, 1627 &min_value, &max_value); 1628 size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n", 1629 min_value, max_value); 1630 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2, 1631 &min_value, &max_value); 1632 size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n", 1633 min_value, max_value); 1634 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3, 1635 &min_value, &max_value); 1636 size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n", 1637 min_value, max_value); 1638 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3, 1639 &min_value, &max_value); 1640 size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n", 1641 min_value, max_value); 1642 } 1643 1644 break; 1645 default: 1646 break; 1647 } 1648 1649 return size; 1650 } 1651 1652 static int navi10_force_clk_levels(struct smu_context *smu, 1653 enum smu_clk_type clk_type, uint32_t mask) 1654 { 1655 1656 int ret = 0, size = 0; 1657 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; 1658 1659 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1660 soft_max_level = mask ? (fls(mask) - 1) : 0; 1661 1662 switch (clk_type) { 1663 case SMU_GFXCLK: 1664 case SMU_SCLK: 1665 case SMU_SOCCLK: 1666 case SMU_MCLK: 1667 case SMU_UCLK: 1668 case SMU_FCLK: 1669 /* There is only 2 levels for fine grained DPM */ 1670 if (navi10_is_support_fine_grained_dpm(smu, clk_type)) { 1671 soft_max_level = (soft_max_level >= 1 ? 1 : 0); 1672 soft_min_level = (soft_min_level >= 1 ? 1 : 0); 1673 } 1674 1675 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); 1676 if (ret) 1677 return size; 1678 1679 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq); 1680 if (ret) 1681 return size; 1682 1683 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 1684 if (ret) 1685 return size; 1686 break; 1687 case SMU_DCEFCLK: 1688 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n"); 1689 break; 1690 1691 default: 1692 break; 1693 } 1694 1695 return size; 1696 } 1697 1698 static int navi10_populate_umd_state_clk(struct smu_context *smu) 1699 { 1700 struct smu_11_0_dpm_context *dpm_context = 1701 smu->smu_dpm.dpm_context; 1702 struct smu_11_0_dpm_table *gfx_table = 1703 &dpm_context->dpm_tables.gfx_table; 1704 struct smu_11_0_dpm_table *mem_table = 1705 &dpm_context->dpm_tables.uclk_table; 1706 struct smu_11_0_dpm_table *soc_table = 1707 &dpm_context->dpm_tables.soc_table; 1708 struct smu_umd_pstate_table *pstate_table = 1709 &smu->pstate_table; 1710 struct amdgpu_device *adev = smu->adev; 1711 uint32_t sclk_freq; 1712 1713 pstate_table->gfxclk_pstate.min = gfx_table->min; 1714 switch (adev->ip_versions[MP1_HWIP][0]) { 1715 case IP_VERSION(11, 0, 0): 1716 switch (adev->pdev->revision) { 1717 case 0xf0: /* XTX */ 1718 case 0xc0: 1719 sclk_freq = NAVI10_PEAK_SCLK_XTX; 1720 break; 1721 case 0xf1: /* XT */ 1722 case 0xc1: 1723 sclk_freq = NAVI10_PEAK_SCLK_XT; 1724 break; 1725 default: /* XL */ 1726 sclk_freq = NAVI10_PEAK_SCLK_XL; 1727 break; 1728 } 1729 break; 1730 case IP_VERSION(11, 0, 5): 1731 switch (adev->pdev->revision) { 1732 case 0xc7: /* XT */ 1733 case 0xf4: 1734 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK; 1735 break; 1736 case 0xc1: /* XTM */ 1737 case 0xf2: 1738 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK; 1739 break; 1740 case 0xc3: /* XLM */ 1741 case 0xf3: 1742 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK; 1743 break; 1744 case 0xc5: /* XTX */ 1745 case 0xf6: 1746 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK; 1747 break; 1748 default: /* XL */ 1749 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK; 1750 break; 1751 } 1752 break; 1753 case IP_VERSION(11, 0, 9): 1754 sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK; 1755 break; 1756 default: 1757 sclk_freq = gfx_table->dpm_levels[gfx_table->count - 1].value; 1758 break; 1759 } 1760 pstate_table->gfxclk_pstate.peak = sclk_freq; 1761 1762 pstate_table->uclk_pstate.min = mem_table->min; 1763 pstate_table->uclk_pstate.peak = mem_table->max; 1764 1765 pstate_table->socclk_pstate.min = soc_table->min; 1766 pstate_table->socclk_pstate.peak = soc_table->max; 1767 1768 if (gfx_table->max > NAVI10_UMD_PSTATE_PROFILING_GFXCLK && 1769 mem_table->max > NAVI10_UMD_PSTATE_PROFILING_MEMCLK && 1770 soc_table->max > NAVI10_UMD_PSTATE_PROFILING_SOCCLK) { 1771 pstate_table->gfxclk_pstate.standard = 1772 NAVI10_UMD_PSTATE_PROFILING_GFXCLK; 1773 pstate_table->uclk_pstate.standard = 1774 NAVI10_UMD_PSTATE_PROFILING_MEMCLK; 1775 pstate_table->socclk_pstate.standard = 1776 NAVI10_UMD_PSTATE_PROFILING_SOCCLK; 1777 } else { 1778 pstate_table->gfxclk_pstate.standard = 1779 pstate_table->gfxclk_pstate.min; 1780 pstate_table->uclk_pstate.standard = 1781 pstate_table->uclk_pstate.min; 1782 pstate_table->socclk_pstate.standard = 1783 pstate_table->socclk_pstate.min; 1784 } 1785 1786 return 0; 1787 } 1788 1789 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu, 1790 enum smu_clk_type clk_type, 1791 struct pp_clock_levels_with_latency *clocks) 1792 { 1793 int ret = 0, i = 0; 1794 uint32_t level_count = 0, freq = 0; 1795 1796 switch (clk_type) { 1797 case SMU_GFXCLK: 1798 case SMU_DCEFCLK: 1799 case SMU_SOCCLK: 1800 case SMU_MCLK: 1801 case SMU_UCLK: 1802 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &level_count); 1803 if (ret) 1804 return ret; 1805 1806 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS); 1807 clocks->num_levels = level_count; 1808 1809 for (i = 0; i < level_count; i++) { 1810 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &freq); 1811 if (ret) 1812 return ret; 1813 1814 clocks->data[i].clocks_in_khz = freq * 1000; 1815 clocks->data[i].latency_in_us = 0; 1816 } 1817 break; 1818 default: 1819 break; 1820 } 1821 1822 return ret; 1823 } 1824 1825 static int navi10_pre_display_config_changed(struct smu_context *smu) 1826 { 1827 int ret = 0; 1828 uint32_t max_freq = 0; 1829 1830 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL); 1831 if (ret) 1832 return ret; 1833 1834 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1835 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq); 1836 if (ret) 1837 return ret; 1838 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq); 1839 if (ret) 1840 return ret; 1841 } 1842 1843 return ret; 1844 } 1845 1846 static int navi10_display_config_changed(struct smu_context *smu) 1847 { 1848 int ret = 0; 1849 1850 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1851 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) && 1852 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 1853 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 1854 smu->display_config->num_display, 1855 NULL); 1856 if (ret) 1857 return ret; 1858 } 1859 1860 return ret; 1861 } 1862 1863 static bool navi10_is_dpm_running(struct smu_context *smu) 1864 { 1865 int ret = 0; 1866 uint64_t feature_enabled; 1867 1868 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 1869 if (ret) 1870 return false; 1871 1872 return !!(feature_enabled & SMC_DPM_FEATURE); 1873 } 1874 1875 static int navi10_get_fan_speed_rpm(struct smu_context *smu, 1876 uint32_t *speed) 1877 { 1878 int ret = 0; 1879 1880 if (!speed) 1881 return -EINVAL; 1882 1883 switch (smu_v11_0_get_fan_control_mode(smu)) { 1884 case AMD_FAN_CTRL_AUTO: 1885 ret = navi10_get_smu_metrics_data(smu, 1886 METRICS_CURR_FANSPEED, 1887 speed); 1888 break; 1889 default: 1890 ret = smu_v11_0_get_fan_speed_rpm(smu, 1891 speed); 1892 break; 1893 } 1894 1895 return ret; 1896 } 1897 1898 static int navi10_get_fan_parameters(struct smu_context *smu) 1899 { 1900 PPTable_t *pptable = smu->smu_table.driver_pptable; 1901 1902 smu->fan_max_rpm = pptable->FanMaximumRpm; 1903 1904 return 0; 1905 } 1906 1907 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf) 1908 { 1909 DpmActivityMonitorCoeffInt_t activity_monitor; 1910 uint32_t i, size = 0; 1911 int16_t workload_type = 0; 1912 static const char *title[] = { 1913 "PROFILE_INDEX(NAME)", 1914 "CLOCK_TYPE(NAME)", 1915 "FPS", 1916 "MinFreqType", 1917 "MinActiveFreqType", 1918 "MinActiveFreq", 1919 "BoosterFreqType", 1920 "BoosterFreq", 1921 "PD_Data_limit_c", 1922 "PD_Data_error_coeff", 1923 "PD_Data_error_rate_coeff"}; 1924 int result = 0; 1925 1926 if (!buf) 1927 return -EINVAL; 1928 1929 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n", 1930 title[0], title[1], title[2], title[3], title[4], title[5], 1931 title[6], title[7], title[8], title[9], title[10]); 1932 1933 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1934 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1935 workload_type = smu_cmn_to_asic_specific_index(smu, 1936 CMN2ASIC_MAPPING_WORKLOAD, 1937 i); 1938 if (workload_type < 0) 1939 return -EINVAL; 1940 1941 result = smu_cmn_update_table(smu, 1942 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type, 1943 (void *)(&activity_monitor), false); 1944 if (result) { 1945 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1946 return result; 1947 } 1948 1949 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n", 1950 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1951 1952 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1953 " ", 1954 0, 1955 "GFXCLK", 1956 activity_monitor.Gfx_FPS, 1957 activity_monitor.Gfx_MinFreqStep, 1958 activity_monitor.Gfx_MinActiveFreqType, 1959 activity_monitor.Gfx_MinActiveFreq, 1960 activity_monitor.Gfx_BoosterFreqType, 1961 activity_monitor.Gfx_BoosterFreq, 1962 activity_monitor.Gfx_PD_Data_limit_c, 1963 activity_monitor.Gfx_PD_Data_error_coeff, 1964 activity_monitor.Gfx_PD_Data_error_rate_coeff); 1965 1966 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1967 " ", 1968 1, 1969 "SOCCLK", 1970 activity_monitor.Soc_FPS, 1971 activity_monitor.Soc_MinFreqStep, 1972 activity_monitor.Soc_MinActiveFreqType, 1973 activity_monitor.Soc_MinActiveFreq, 1974 activity_monitor.Soc_BoosterFreqType, 1975 activity_monitor.Soc_BoosterFreq, 1976 activity_monitor.Soc_PD_Data_limit_c, 1977 activity_monitor.Soc_PD_Data_error_coeff, 1978 activity_monitor.Soc_PD_Data_error_rate_coeff); 1979 1980 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1981 " ", 1982 2, 1983 "MEMLK", 1984 activity_monitor.Mem_FPS, 1985 activity_monitor.Mem_MinFreqStep, 1986 activity_monitor.Mem_MinActiveFreqType, 1987 activity_monitor.Mem_MinActiveFreq, 1988 activity_monitor.Mem_BoosterFreqType, 1989 activity_monitor.Mem_BoosterFreq, 1990 activity_monitor.Mem_PD_Data_limit_c, 1991 activity_monitor.Mem_PD_Data_error_coeff, 1992 activity_monitor.Mem_PD_Data_error_rate_coeff); 1993 } 1994 1995 return size; 1996 } 1997 1998 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 1999 { 2000 DpmActivityMonitorCoeffInt_t activity_monitor; 2001 int workload_type, ret = 0; 2002 2003 smu->power_profile_mode = input[size]; 2004 2005 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 2006 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode); 2007 return -EINVAL; 2008 } 2009 2010 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 2011 2012 ret = smu_cmn_update_table(smu, 2013 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 2014 (void *)(&activity_monitor), false); 2015 if (ret) { 2016 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 2017 return ret; 2018 } 2019 2020 switch (input[0]) { 2021 case 0: /* Gfxclk */ 2022 activity_monitor.Gfx_FPS = input[1]; 2023 activity_monitor.Gfx_MinFreqStep = input[2]; 2024 activity_monitor.Gfx_MinActiveFreqType = input[3]; 2025 activity_monitor.Gfx_MinActiveFreq = input[4]; 2026 activity_monitor.Gfx_BoosterFreqType = input[5]; 2027 activity_monitor.Gfx_BoosterFreq = input[6]; 2028 activity_monitor.Gfx_PD_Data_limit_c = input[7]; 2029 activity_monitor.Gfx_PD_Data_error_coeff = input[8]; 2030 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9]; 2031 break; 2032 case 1: /* Socclk */ 2033 activity_monitor.Soc_FPS = input[1]; 2034 activity_monitor.Soc_MinFreqStep = input[2]; 2035 activity_monitor.Soc_MinActiveFreqType = input[3]; 2036 activity_monitor.Soc_MinActiveFreq = input[4]; 2037 activity_monitor.Soc_BoosterFreqType = input[5]; 2038 activity_monitor.Soc_BoosterFreq = input[6]; 2039 activity_monitor.Soc_PD_Data_limit_c = input[7]; 2040 activity_monitor.Soc_PD_Data_error_coeff = input[8]; 2041 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9]; 2042 break; 2043 case 2: /* Memlk */ 2044 activity_monitor.Mem_FPS = input[1]; 2045 activity_monitor.Mem_MinFreqStep = input[2]; 2046 activity_monitor.Mem_MinActiveFreqType = input[3]; 2047 activity_monitor.Mem_MinActiveFreq = input[4]; 2048 activity_monitor.Mem_BoosterFreqType = input[5]; 2049 activity_monitor.Mem_BoosterFreq = input[6]; 2050 activity_monitor.Mem_PD_Data_limit_c = input[7]; 2051 activity_monitor.Mem_PD_Data_error_coeff = input[8]; 2052 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9]; 2053 break; 2054 } 2055 2056 ret = smu_cmn_update_table(smu, 2057 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 2058 (void *)(&activity_monitor), true); 2059 if (ret) { 2060 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 2061 return ret; 2062 } 2063 } 2064 2065 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 2066 workload_type = smu_cmn_to_asic_specific_index(smu, 2067 CMN2ASIC_MAPPING_WORKLOAD, 2068 smu->power_profile_mode); 2069 if (workload_type < 0) 2070 return -EINVAL; 2071 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 2072 1 << workload_type, NULL); 2073 2074 return ret; 2075 } 2076 2077 static int navi10_notify_smc_display_config(struct smu_context *smu) 2078 { 2079 struct smu_clocks min_clocks = {0}; 2080 struct pp_display_clock_request clock_req; 2081 int ret = 0; 2082 2083 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; 2084 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; 2085 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; 2086 2087 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 2088 clock_req.clock_type = amd_pp_dcef_clock; 2089 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; 2090 2091 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req); 2092 if (!ret) { 2093 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) { 2094 ret = smu_cmn_send_smc_msg_with_param(smu, 2095 SMU_MSG_SetMinDeepSleepDcefclk, 2096 min_clocks.dcef_clock_in_sr/100, 2097 NULL); 2098 if (ret) { 2099 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!"); 2100 return ret; 2101 } 2102 } 2103 } else { 2104 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!"); 2105 } 2106 } 2107 2108 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 2109 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); 2110 if (ret) { 2111 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__); 2112 return ret; 2113 } 2114 } 2115 2116 return 0; 2117 } 2118 2119 static int navi10_set_watermarks_table(struct smu_context *smu, 2120 struct pp_smu_wm_range_sets *clock_ranges) 2121 { 2122 Watermarks_t *table = smu->smu_table.watermarks_table; 2123 int ret = 0; 2124 int i; 2125 2126 if (clock_ranges) { 2127 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 2128 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 2129 return -EINVAL; 2130 2131 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 2132 table->WatermarkRow[WM_DCEFCLK][i].MinClock = 2133 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 2134 table->WatermarkRow[WM_DCEFCLK][i].MaxClock = 2135 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 2136 table->WatermarkRow[WM_DCEFCLK][i].MinUclk = 2137 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 2138 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk = 2139 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 2140 2141 table->WatermarkRow[WM_DCEFCLK][i].WmSetting = 2142 clock_ranges->reader_wm_sets[i].wm_inst; 2143 } 2144 2145 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 2146 table->WatermarkRow[WM_SOCCLK][i].MinClock = 2147 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 2148 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 2149 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 2150 table->WatermarkRow[WM_SOCCLK][i].MinUclk = 2151 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 2152 table->WatermarkRow[WM_SOCCLK][i].MaxUclk = 2153 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 2154 2155 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 2156 clock_ranges->writer_wm_sets[i].wm_inst; 2157 } 2158 2159 smu->watermarks_bitmap |= WATERMARKS_EXIST; 2160 } 2161 2162 /* pass data to smu controller */ 2163 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 2164 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 2165 ret = smu_cmn_write_watermarks_table(smu); 2166 if (ret) { 2167 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 2168 return ret; 2169 } 2170 smu->watermarks_bitmap |= WATERMARKS_LOADED; 2171 } 2172 2173 return 0; 2174 } 2175 2176 static int navi10_read_sensor(struct smu_context *smu, 2177 enum amd_pp_sensors sensor, 2178 void *data, uint32_t *size) 2179 { 2180 int ret = 0; 2181 struct smu_table_context *table_context = &smu->smu_table; 2182 PPTable_t *pptable = table_context->driver_pptable; 2183 2184 if(!data || !size) 2185 return -EINVAL; 2186 2187 switch (sensor) { 2188 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 2189 *(uint32_t *)data = pptable->FanMaximumRpm; 2190 *size = 4; 2191 break; 2192 case AMDGPU_PP_SENSOR_MEM_LOAD: 2193 ret = navi1x_get_smu_metrics_data(smu, 2194 METRICS_AVERAGE_MEMACTIVITY, 2195 (uint32_t *)data); 2196 *size = 4; 2197 break; 2198 case AMDGPU_PP_SENSOR_GPU_LOAD: 2199 ret = navi1x_get_smu_metrics_data(smu, 2200 METRICS_AVERAGE_GFXACTIVITY, 2201 (uint32_t *)data); 2202 *size = 4; 2203 break; 2204 case AMDGPU_PP_SENSOR_GPU_POWER: 2205 ret = navi1x_get_smu_metrics_data(smu, 2206 METRICS_AVERAGE_SOCKETPOWER, 2207 (uint32_t *)data); 2208 *size = 4; 2209 break; 2210 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 2211 ret = navi1x_get_smu_metrics_data(smu, 2212 METRICS_TEMPERATURE_HOTSPOT, 2213 (uint32_t *)data); 2214 *size = 4; 2215 break; 2216 case AMDGPU_PP_SENSOR_EDGE_TEMP: 2217 ret = navi1x_get_smu_metrics_data(smu, 2218 METRICS_TEMPERATURE_EDGE, 2219 (uint32_t *)data); 2220 *size = 4; 2221 break; 2222 case AMDGPU_PP_SENSOR_MEM_TEMP: 2223 ret = navi1x_get_smu_metrics_data(smu, 2224 METRICS_TEMPERATURE_MEM, 2225 (uint32_t *)data); 2226 *size = 4; 2227 break; 2228 case AMDGPU_PP_SENSOR_GFX_MCLK: 2229 ret = navi10_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 2230 *(uint32_t *)data *= 100; 2231 *size = 4; 2232 break; 2233 case AMDGPU_PP_SENSOR_GFX_SCLK: 2234 ret = navi1x_get_smu_metrics_data(smu, METRICS_AVERAGE_GFXCLK, (uint32_t *)data); 2235 *(uint32_t *)data *= 100; 2236 *size = 4; 2237 break; 2238 case AMDGPU_PP_SENSOR_VDDGFX: 2239 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data); 2240 *size = 4; 2241 break; 2242 default: 2243 ret = -EOPNOTSUPP; 2244 break; 2245 } 2246 2247 return ret; 2248 } 2249 2250 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states) 2251 { 2252 uint32_t num_discrete_levels = 0; 2253 uint16_t *dpm_levels = NULL; 2254 uint16_t i = 0; 2255 struct smu_table_context *table_context = &smu->smu_table; 2256 PPTable_t *driver_ppt = NULL; 2257 2258 if (!clocks_in_khz || !num_states || !table_context->driver_pptable) 2259 return -EINVAL; 2260 2261 driver_ppt = table_context->driver_pptable; 2262 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels; 2263 dpm_levels = driver_ppt->FreqTableUclk; 2264 2265 if (num_discrete_levels == 0 || dpm_levels == NULL) 2266 return -EINVAL; 2267 2268 *num_states = num_discrete_levels; 2269 for (i = 0; i < num_discrete_levels; i++) { 2270 /* convert to khz */ 2271 *clocks_in_khz = (*dpm_levels) * 1000; 2272 clocks_in_khz++; 2273 dpm_levels++; 2274 } 2275 2276 return 0; 2277 } 2278 2279 static int navi10_get_thermal_temperature_range(struct smu_context *smu, 2280 struct smu_temperature_range *range) 2281 { 2282 struct smu_table_context *table_context = &smu->smu_table; 2283 struct smu_11_0_powerplay_table *powerplay_table = 2284 table_context->power_play_table; 2285 PPTable_t *pptable = smu->smu_table.driver_pptable; 2286 2287 if (!range) 2288 return -EINVAL; 2289 2290 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range)); 2291 2292 range->max = pptable->TedgeLimit * 2293 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2294 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) * 2295 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2296 range->hotspot_crit_max = pptable->ThotspotLimit * 2297 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2298 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 2299 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2300 range->mem_crit_max = pptable->TmemLimit * 2301 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2302 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)* 2303 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2304 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 2305 2306 return 0; 2307 } 2308 2309 static int navi10_display_disable_memory_clock_switch(struct smu_context *smu, 2310 bool disable_memory_clock_switch) 2311 { 2312 int ret = 0; 2313 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks = 2314 (struct smu_11_0_max_sustainable_clocks *) 2315 smu->smu_table.max_sustainable_clocks; 2316 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal; 2317 uint32_t max_memory_clock = max_sustainable_clocks->uclock; 2318 2319 if(smu->disable_uclk_switch == disable_memory_clock_switch) 2320 return 0; 2321 2322 if(disable_memory_clock_switch) 2323 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0); 2324 else 2325 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0); 2326 2327 if(!ret) 2328 smu->disable_uclk_switch = disable_memory_clock_switch; 2329 2330 return ret; 2331 } 2332 2333 static int navi10_get_power_limit(struct smu_context *smu, 2334 uint32_t *current_power_limit, 2335 uint32_t *default_power_limit, 2336 uint32_t *max_power_limit) 2337 { 2338 struct smu_11_0_powerplay_table *powerplay_table = 2339 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table; 2340 struct smu_11_0_overdrive_table *od_settings = smu->od_settings; 2341 PPTable_t *pptable = smu->smu_table.driver_pptable; 2342 uint32_t power_limit, od_percent; 2343 2344 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) { 2345 /* the last hope to figure out the ppt limit */ 2346 if (!pptable) { 2347 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!"); 2348 return -EINVAL; 2349 } 2350 power_limit = 2351 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0]; 2352 } 2353 2354 if (current_power_limit) 2355 *current_power_limit = power_limit; 2356 if (default_power_limit) 2357 *default_power_limit = power_limit; 2358 2359 if (max_power_limit) { 2360 if (smu->od_enabled && 2361 navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) { 2362 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]); 2363 2364 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit); 2365 2366 power_limit *= (100 + od_percent); 2367 power_limit /= 100; 2368 } 2369 2370 *max_power_limit = power_limit; 2371 } 2372 2373 return 0; 2374 } 2375 2376 static int navi10_update_pcie_parameters(struct smu_context *smu, 2377 uint32_t pcie_gen_cap, 2378 uint32_t pcie_width_cap) 2379 { 2380 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 2381 PPTable_t *pptable = smu->smu_table.driver_pptable; 2382 uint32_t smu_pcie_arg; 2383 int ret, i; 2384 2385 /* lclk dpm table setup */ 2386 for (i = 0; i < MAX_PCIE_CONF; i++) { 2387 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i]; 2388 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i]; 2389 } 2390 2391 for (i = 0; i < NUM_LINK_LEVELS; i++) { 2392 smu_pcie_arg = (i << 16) | 2393 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) : 2394 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ? 2395 pptable->PcieLaneCount[i] : pcie_width_cap); 2396 ret = smu_cmn_send_smc_msg_with_param(smu, 2397 SMU_MSG_OverridePcieParameters, 2398 smu_pcie_arg, 2399 NULL); 2400 2401 if (ret) 2402 return ret; 2403 2404 if (pptable->PcieGenSpeed[i] > pcie_gen_cap) 2405 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap; 2406 if (pptable->PcieLaneCount[i] > pcie_width_cap) 2407 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap; 2408 } 2409 2410 return 0; 2411 } 2412 2413 static inline void navi10_dump_od_table(struct smu_context *smu, 2414 OverDriveTable_t *od_table) 2415 { 2416 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax); 2417 dev_dbg(smu->adev->dev, "OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1); 2418 dev_dbg(smu->adev->dev, "OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2); 2419 dev_dbg(smu->adev->dev, "OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3); 2420 dev_dbg(smu->adev->dev, "OD: UclkFmax: %d\n", od_table->UclkFmax); 2421 dev_dbg(smu->adev->dev, "OD: OverDrivePct: %d\n", od_table->OverDrivePct); 2422 } 2423 2424 static int navi10_od_setting_check_range(struct smu_context *smu, 2425 struct smu_11_0_overdrive_table *od_table, 2426 enum SMU_11_0_ODSETTING_ID setting, 2427 uint32_t value) 2428 { 2429 if (value < od_table->min[setting]) { 2430 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]); 2431 return -EINVAL; 2432 } 2433 if (value > od_table->max[setting]) { 2434 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]); 2435 return -EINVAL; 2436 } 2437 return 0; 2438 } 2439 2440 static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu, 2441 uint16_t *voltage, 2442 uint32_t freq) 2443 { 2444 uint32_t param = (freq & 0xFFFF) | (PPCLK_GFXCLK << 16); 2445 uint32_t value = 0; 2446 int ret; 2447 2448 ret = smu_cmn_send_smc_msg_with_param(smu, 2449 SMU_MSG_GetVoltageByDpm, 2450 param, 2451 &value); 2452 if (ret) { 2453 dev_err(smu->adev->dev, "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!"); 2454 return ret; 2455 } 2456 2457 *voltage = (uint16_t)value; 2458 2459 return 0; 2460 } 2461 2462 static int navi10_baco_enter(struct smu_context *smu) 2463 { 2464 struct amdgpu_device *adev = smu->adev; 2465 2466 /* 2467 * This aims the case below: 2468 * amdgpu driver loaded -> runpm suspend kicked -> sound driver loaded 2469 * 2470 * For NAVI10 and later ASICs, we rely on PMFW to handle the runpm. To 2471 * make that possible, PMFW needs to acknowledge the dstate transition 2472 * process for both gfx(function 0) and audio(function 1) function of 2473 * the ASIC. 2474 * 2475 * The PCI device's initial runpm status is RUNPM_SUSPENDED. So as the 2476 * device representing the audio function of the ASIC. And that means 2477 * even if the sound driver(snd_hda_intel) was not loaded yet, it's still 2478 * possible runpm suspend kicked on the ASIC. However without the dstate 2479 * transition notification from audio function, pmfw cannot handle the 2480 * BACO in/exit correctly. And that will cause driver hang on runpm 2481 * resuming. 2482 * 2483 * To address this, we revert to legacy message way(driver masters the 2484 * timing for BACO in/exit) on sound driver missing. 2485 */ 2486 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) 2487 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO); 2488 else 2489 return smu_v11_0_baco_enter(smu); 2490 } 2491 2492 static int navi10_baco_exit(struct smu_context *smu) 2493 { 2494 struct amdgpu_device *adev = smu->adev; 2495 2496 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) { 2497 /* Wait for PMFW handling for the Dstate change */ 2498 msleep(10); 2499 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS); 2500 } else { 2501 return smu_v11_0_baco_exit(smu); 2502 } 2503 } 2504 2505 static int navi10_set_default_od_settings(struct smu_context *smu) 2506 { 2507 OverDriveTable_t *od_table = 2508 (OverDriveTable_t *)smu->smu_table.overdrive_table; 2509 OverDriveTable_t *boot_od_table = 2510 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table; 2511 OverDriveTable_t *user_od_table = 2512 (OverDriveTable_t *)smu->smu_table.user_overdrive_table; 2513 int ret = 0; 2514 2515 /* 2516 * For S3/S4/Runpm resume, no need to setup those overdrive tables again as 2517 * - either they already have the default OD settings got during cold bootup 2518 * - or they have some user customized OD settings which cannot be overwritten 2519 */ 2520 if (smu->adev->in_suspend) 2521 return 0; 2522 2523 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)boot_od_table, false); 2524 if (ret) { 2525 dev_err(smu->adev->dev, "Failed to get overdrive table!\n"); 2526 return ret; 2527 } 2528 2529 if (!boot_od_table->GfxclkVolt1) { 2530 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu, 2531 &boot_od_table->GfxclkVolt1, 2532 boot_od_table->GfxclkFreq1); 2533 if (ret) 2534 return ret; 2535 } 2536 2537 if (!boot_od_table->GfxclkVolt2) { 2538 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu, 2539 &boot_od_table->GfxclkVolt2, 2540 boot_od_table->GfxclkFreq2); 2541 if (ret) 2542 return ret; 2543 } 2544 2545 if (!boot_od_table->GfxclkVolt3) { 2546 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu, 2547 &boot_od_table->GfxclkVolt3, 2548 boot_od_table->GfxclkFreq3); 2549 if (ret) 2550 return ret; 2551 } 2552 2553 navi10_dump_od_table(smu, boot_od_table); 2554 2555 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t)); 2556 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t)); 2557 2558 return 0; 2559 } 2560 2561 static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) { 2562 int i; 2563 int ret = 0; 2564 struct smu_table_context *table_context = &smu->smu_table; 2565 OverDriveTable_t *od_table; 2566 struct smu_11_0_overdrive_table *od_settings; 2567 enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting; 2568 uint16_t *freq_ptr, *voltage_ptr; 2569 od_table = (OverDriveTable_t *)table_context->overdrive_table; 2570 2571 if (!smu->od_enabled) { 2572 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n"); 2573 return -EINVAL; 2574 } 2575 2576 if (!smu->od_settings) { 2577 dev_err(smu->adev->dev, "OD board limits are not set!\n"); 2578 return -ENOENT; 2579 } 2580 2581 od_settings = smu->od_settings; 2582 2583 switch (type) { 2584 case PP_OD_EDIT_SCLK_VDDC_TABLE: 2585 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) { 2586 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n"); 2587 return -ENOTSUPP; 2588 } 2589 if (!table_context->overdrive_table) { 2590 dev_err(smu->adev->dev, "Overdrive is not initialized\n"); 2591 return -EINVAL; 2592 } 2593 for (i = 0; i < size; i += 2) { 2594 if (i + 2 > size) { 2595 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size); 2596 return -EINVAL; 2597 } 2598 switch (input[i]) { 2599 case 0: 2600 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN; 2601 freq_ptr = &od_table->GfxclkFmin; 2602 if (input[i + 1] > od_table->GfxclkFmax) { 2603 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n", 2604 input[i + 1], 2605 od_table->GfxclkFmin); 2606 return -EINVAL; 2607 } 2608 break; 2609 case 1: 2610 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX; 2611 freq_ptr = &od_table->GfxclkFmax; 2612 if (input[i + 1] < od_table->GfxclkFmin) { 2613 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n", 2614 input[i + 1], 2615 od_table->GfxclkFmax); 2616 return -EINVAL; 2617 } 2618 break; 2619 default: 2620 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]); 2621 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n"); 2622 return -EINVAL; 2623 } 2624 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[i + 1]); 2625 if (ret) 2626 return ret; 2627 *freq_ptr = input[i + 1]; 2628 } 2629 break; 2630 case PP_OD_EDIT_MCLK_VDDC_TABLE: 2631 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) { 2632 dev_warn(smu->adev->dev, "UCLK_MAX not supported!\n"); 2633 return -ENOTSUPP; 2634 } 2635 if (size < 2) { 2636 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size); 2637 return -EINVAL; 2638 } 2639 if (input[0] != 1) { 2640 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]); 2641 dev_info(smu->adev->dev, "Supported indices: [1:max]\n"); 2642 return -EINVAL; 2643 } 2644 ret = navi10_od_setting_check_range(smu, od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]); 2645 if (ret) 2646 return ret; 2647 od_table->UclkFmax = input[1]; 2648 break; 2649 case PP_OD_RESTORE_DEFAULT_TABLE: 2650 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) { 2651 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n"); 2652 return -EINVAL; 2653 } 2654 memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t)); 2655 break; 2656 case PP_OD_COMMIT_DPM_TABLE: 2657 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) { 2658 navi10_dump_od_table(smu, od_table); 2659 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true); 2660 if (ret) { 2661 dev_err(smu->adev->dev, "Failed to import overdrive table!\n"); 2662 return ret; 2663 } 2664 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t)); 2665 smu->user_dpm_profile.user_od = true; 2666 2667 if (!memcmp(table_context->user_overdrive_table, 2668 table_context->boot_overdrive_table, 2669 sizeof(OverDriveTable_t))) 2670 smu->user_dpm_profile.user_od = false; 2671 } 2672 break; 2673 case PP_OD_EDIT_VDDC_CURVE: 2674 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) { 2675 dev_warn(smu->adev->dev, "GFXCLK_CURVE not supported!\n"); 2676 return -ENOTSUPP; 2677 } 2678 if (size < 3) { 2679 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size); 2680 return -EINVAL; 2681 } 2682 if (!od_table) { 2683 dev_info(smu->adev->dev, "Overdrive is not initialized\n"); 2684 return -EINVAL; 2685 } 2686 2687 switch (input[0]) { 2688 case 0: 2689 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1; 2690 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1; 2691 freq_ptr = &od_table->GfxclkFreq1; 2692 voltage_ptr = &od_table->GfxclkVolt1; 2693 break; 2694 case 1: 2695 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2; 2696 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2; 2697 freq_ptr = &od_table->GfxclkFreq2; 2698 voltage_ptr = &od_table->GfxclkVolt2; 2699 break; 2700 case 2: 2701 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3; 2702 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3; 2703 freq_ptr = &od_table->GfxclkFreq3; 2704 voltage_ptr = &od_table->GfxclkVolt3; 2705 break; 2706 default: 2707 dev_info(smu->adev->dev, "Invalid VDDC_CURVE index: %ld\n", input[0]); 2708 dev_info(smu->adev->dev, "Supported indices: [0, 1, 2]\n"); 2709 return -EINVAL; 2710 } 2711 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[1]); 2712 if (ret) 2713 return ret; 2714 // Allow setting zero to disable the OverDrive VDDC curve 2715 if (input[2] != 0) { 2716 ret = navi10_od_setting_check_range(smu, od_settings, voltage_setting, input[2]); 2717 if (ret) 2718 return ret; 2719 *freq_ptr = input[1]; 2720 *voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE; 2721 dev_dbg(smu->adev->dev, "OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr); 2722 } else { 2723 // If setting 0, disable all voltage curve settings 2724 od_table->GfxclkVolt1 = 0; 2725 od_table->GfxclkVolt2 = 0; 2726 od_table->GfxclkVolt3 = 0; 2727 } 2728 navi10_dump_od_table(smu, od_table); 2729 break; 2730 default: 2731 return -ENOSYS; 2732 } 2733 return ret; 2734 } 2735 2736 static int navi10_run_btc(struct smu_context *smu) 2737 { 2738 int ret = 0; 2739 2740 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunBtc, NULL); 2741 if (ret) 2742 dev_err(smu->adev->dev, "RunBtc failed!\n"); 2743 2744 return ret; 2745 } 2746 2747 static bool navi10_need_umc_cdr_workaround(struct smu_context *smu) 2748 { 2749 struct amdgpu_device *adev = smu->adev; 2750 2751 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 2752 return false; 2753 2754 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0) || 2755 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) 2756 return true; 2757 2758 return false; 2759 } 2760 2761 static int navi10_umc_hybrid_cdr_workaround(struct smu_context *smu) 2762 { 2763 uint32_t uclk_count, uclk_min, uclk_max; 2764 int ret = 0; 2765 2766 /* This workaround can be applied only with uclk dpm enabled */ 2767 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 2768 return 0; 2769 2770 ret = smu_v11_0_get_dpm_level_count(smu, SMU_UCLK, &uclk_count); 2771 if (ret) 2772 return ret; 2773 2774 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)(uclk_count - 1), &uclk_max); 2775 if (ret) 2776 return ret; 2777 2778 /* 2779 * The NAVI10_UMC_HYBRID_CDR_WORKAROUND_UCLK_THRESHOLD is 750Mhz. 2780 * This workaround is needed only when the max uclk frequency 2781 * not greater than that. 2782 */ 2783 if (uclk_max > 0x2EE) 2784 return 0; 2785 2786 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)0, &uclk_min); 2787 if (ret) 2788 return ret; 2789 2790 /* Force UCLK out of the highest DPM */ 2791 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_min); 2792 if (ret) 2793 return ret; 2794 2795 /* Revert the UCLK Hardmax */ 2796 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_max); 2797 if (ret) 2798 return ret; 2799 2800 /* 2801 * In this case, SMU already disabled dummy pstate during enablement 2802 * of UCLK DPM, we have to re-enabled it. 2803 */ 2804 return smu_cmn_send_smc_msg(smu, SMU_MSG_DAL_ENABLE_DUMMY_PSTATE_CHANGE, NULL); 2805 } 2806 2807 static int navi10_set_dummy_pstates_table_location(struct smu_context *smu) 2808 { 2809 struct smu_table_context *smu_table = &smu->smu_table; 2810 struct smu_table *dummy_read_table = 2811 &smu_table->dummy_read_1_table; 2812 char *dummy_table = dummy_read_table->cpu_addr; 2813 int ret = 0; 2814 uint32_t i; 2815 2816 for (i = 0; i < 0x40000; i += 0x1000 * 2) { 2817 memcpy(dummy_table, &NoDbiPrbs7[0], 0x1000); 2818 dummy_table += 0x1000; 2819 memcpy(dummy_table, &DbiPrbs7[0], 0x1000); 2820 dummy_table += 0x1000; 2821 } 2822 2823 amdgpu_asic_flush_hdp(smu->adev, NULL); 2824 2825 ret = smu_cmn_send_smc_msg_with_param(smu, 2826 SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH, 2827 upper_32_bits(dummy_read_table->mc_address), 2828 NULL); 2829 if (ret) 2830 return ret; 2831 2832 return smu_cmn_send_smc_msg_with_param(smu, 2833 SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW, 2834 lower_32_bits(dummy_read_table->mc_address), 2835 NULL); 2836 } 2837 2838 static int navi10_run_umc_cdr_workaround(struct smu_context *smu) 2839 { 2840 struct amdgpu_device *adev = smu->adev; 2841 uint8_t umc_fw_greater_than_v136 = false; 2842 uint8_t umc_fw_disable_cdr = false; 2843 uint32_t pmfw_version; 2844 uint32_t param; 2845 int ret = 0; 2846 2847 if (!navi10_need_umc_cdr_workaround(smu)) 2848 return 0; 2849 2850 ret = smu_cmn_get_smc_version(smu, NULL, &pmfw_version); 2851 if (ret) { 2852 dev_err(adev->dev, "Failed to get smu version!\n"); 2853 return ret; 2854 } 2855 2856 /* 2857 * The messages below are only supported by Navi10 42.53.0 and later 2858 * PMFWs and Navi14 53.29.0 and later PMFWs. 2859 * - PPSMC_MSG_SetDriverDummyTableDramAddrHigh 2860 * - PPSMC_MSG_SetDriverDummyTableDramAddrLow 2861 * - PPSMC_MSG_GetUMCFWWA 2862 */ 2863 if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && (pmfw_version >= 0x2a3500)) || 2864 ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && (pmfw_version >= 0x351D00))) { 2865 ret = smu_cmn_send_smc_msg_with_param(smu, 2866 SMU_MSG_GET_UMC_FW_WA, 2867 0, 2868 ¶m); 2869 if (ret) 2870 return ret; 2871 2872 /* First bit indicates if the UMC f/w is above v137 */ 2873 umc_fw_greater_than_v136 = param & 0x1; 2874 2875 /* Second bit indicates if hybrid-cdr is disabled */ 2876 umc_fw_disable_cdr = param & 0x2; 2877 2878 /* w/a only allowed if UMC f/w is <= 136 */ 2879 if (umc_fw_greater_than_v136) 2880 return 0; 2881 2882 if (umc_fw_disable_cdr) { 2883 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) 2884 return navi10_umc_hybrid_cdr_workaround(smu); 2885 } else { 2886 return navi10_set_dummy_pstates_table_location(smu); 2887 } 2888 } else { 2889 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) 2890 return navi10_umc_hybrid_cdr_workaround(smu); 2891 } 2892 2893 return 0; 2894 } 2895 2896 static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu, 2897 void **table) 2898 { 2899 struct smu_table_context *smu_table = &smu->smu_table; 2900 struct gpu_metrics_v1_3 *gpu_metrics = 2901 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 2902 SmuMetrics_legacy_t metrics; 2903 int ret = 0; 2904 2905 ret = smu_cmn_get_metrics_table(smu, 2906 NULL, 2907 true); 2908 if (ret) 2909 return ret; 2910 2911 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_legacy_t)); 2912 2913 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 2914 2915 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 2916 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 2917 gpu_metrics->temperature_mem = metrics.TemperatureMem; 2918 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 2919 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 2920 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 2921 2922 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 2923 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 2924 2925 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 2926 2927 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 2928 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 2929 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 2930 2931 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 2932 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 2933 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 2934 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 2935 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 2936 2937 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 2938 gpu_metrics->indep_throttle_status = 2939 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 2940 navi1x_throttler_map); 2941 2942 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 2943 2944 gpu_metrics->pcie_link_width = 2945 smu_v11_0_get_current_pcie_link_width(smu); 2946 gpu_metrics->pcie_link_speed = 2947 smu_v11_0_get_current_pcie_link_speed(smu); 2948 2949 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 2950 2951 if (metrics.CurrGfxVoltageOffset) 2952 gpu_metrics->voltage_gfx = 2953 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; 2954 if (metrics.CurrMemVidOffset) 2955 gpu_metrics->voltage_mem = 2956 (155000 - 625 * metrics.CurrMemVidOffset) / 100; 2957 if (metrics.CurrSocVoltageOffset) 2958 gpu_metrics->voltage_soc = 2959 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; 2960 2961 *table = (void *)gpu_metrics; 2962 2963 return sizeof(struct gpu_metrics_v1_3); 2964 } 2965 2966 static int navi10_i2c_xfer(struct i2c_adapter *i2c_adap, 2967 struct i2c_msg *msg, int num_msgs) 2968 { 2969 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap); 2970 struct amdgpu_device *adev = smu_i2c->adev; 2971 struct smu_context *smu = adev->powerplay.pp_handle; 2972 struct smu_table_context *smu_table = &smu->smu_table; 2973 struct smu_table *table = &smu_table->driver_table; 2974 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 2975 int i, j, r, c; 2976 u16 dir; 2977 2978 if (!adev->pm.dpm_enabled) 2979 return -EBUSY; 2980 2981 req = kzalloc(sizeof(*req), GFP_KERNEL); 2982 if (!req) 2983 return -ENOMEM; 2984 2985 req->I2CcontrollerPort = smu_i2c->port; 2986 req->I2CSpeed = I2C_SPEED_FAST_400K; 2987 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 2988 dir = msg[0].flags & I2C_M_RD; 2989 2990 for (c = i = 0; i < num_msgs; i++) { 2991 for (j = 0; j < msg[i].len; j++, c++) { 2992 SwI2cCmd_t *cmd = &req->SwI2cCmds[c]; 2993 2994 if (!(msg[i].flags & I2C_M_RD)) { 2995 /* write */ 2996 cmd->Cmd = I2C_CMD_WRITE; 2997 cmd->RegisterAddr = msg[i].buf[j]; 2998 } 2999 3000 if ((dir ^ msg[i].flags) & I2C_M_RD) { 3001 /* The direction changes. 3002 */ 3003 dir = msg[i].flags & I2C_M_RD; 3004 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK; 3005 } 3006 3007 req->NumCmds++; 3008 3009 /* 3010 * Insert STOP if we are at the last byte of either last 3011 * message for the transaction or the client explicitly 3012 * requires a STOP at this particular message. 3013 */ 3014 if ((j == msg[i].len - 1) && 3015 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) { 3016 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK; 3017 cmd->CmdConfig |= CMDCONFIG_STOP_MASK; 3018 } 3019 } 3020 } 3021 mutex_lock(&adev->pm.mutex); 3022 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 3023 mutex_unlock(&adev->pm.mutex); 3024 if (r) 3025 goto fail; 3026 3027 for (c = i = 0; i < num_msgs; i++) { 3028 if (!(msg[i].flags & I2C_M_RD)) { 3029 c += msg[i].len; 3030 continue; 3031 } 3032 for (j = 0; j < msg[i].len; j++, c++) { 3033 SwI2cCmd_t *cmd = &res->SwI2cCmds[c]; 3034 3035 msg[i].buf[j] = cmd->Data; 3036 } 3037 } 3038 r = num_msgs; 3039 fail: 3040 kfree(req); 3041 return r; 3042 } 3043 3044 static u32 navi10_i2c_func(struct i2c_adapter *adap) 3045 { 3046 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 3047 } 3048 3049 3050 static const struct i2c_algorithm navi10_i2c_algo = { 3051 .master_xfer = navi10_i2c_xfer, 3052 .functionality = navi10_i2c_func, 3053 }; 3054 3055 static const struct i2c_adapter_quirks navi10_i2c_control_quirks = { 3056 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN, 3057 .max_read_len = MAX_SW_I2C_COMMANDS, 3058 .max_write_len = MAX_SW_I2C_COMMANDS, 3059 .max_comb_1st_msg_len = 2, 3060 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 3061 }; 3062 3063 static int navi10_i2c_control_init(struct smu_context *smu) 3064 { 3065 struct amdgpu_device *adev = smu->adev; 3066 int res, i; 3067 3068 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 3069 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 3070 struct i2c_adapter *control = &smu_i2c->adapter; 3071 3072 smu_i2c->adev = adev; 3073 smu_i2c->port = i; 3074 mutex_init(&smu_i2c->mutex); 3075 control->owner = THIS_MODULE; 3076 control->class = I2C_CLASS_HWMON; 3077 control->dev.parent = &adev->pdev->dev; 3078 control->algo = &navi10_i2c_algo; 3079 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i); 3080 control->quirks = &navi10_i2c_control_quirks; 3081 i2c_set_adapdata(control, smu_i2c); 3082 3083 res = i2c_add_adapter(control); 3084 if (res) { 3085 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 3086 goto Out_err; 3087 } 3088 } 3089 3090 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 3091 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter; 3092 3093 return 0; 3094 Out_err: 3095 for ( ; i >= 0; i--) { 3096 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 3097 struct i2c_adapter *control = &smu_i2c->adapter; 3098 3099 i2c_del_adapter(control); 3100 } 3101 return res; 3102 } 3103 3104 static void navi10_i2c_control_fini(struct smu_context *smu) 3105 { 3106 struct amdgpu_device *adev = smu->adev; 3107 int i; 3108 3109 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 3110 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 3111 struct i2c_adapter *control = &smu_i2c->adapter; 3112 3113 i2c_del_adapter(control); 3114 } 3115 adev->pm.ras_eeprom_i2c_bus = NULL; 3116 adev->pm.fru_eeprom_i2c_bus = NULL; 3117 } 3118 3119 static ssize_t navi10_get_gpu_metrics(struct smu_context *smu, 3120 void **table) 3121 { 3122 struct smu_table_context *smu_table = &smu->smu_table; 3123 struct gpu_metrics_v1_3 *gpu_metrics = 3124 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 3125 SmuMetrics_t metrics; 3126 int ret = 0; 3127 3128 ret = smu_cmn_get_metrics_table(smu, 3129 NULL, 3130 true); 3131 if (ret) 3132 return ret; 3133 3134 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_t)); 3135 3136 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 3137 3138 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 3139 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 3140 gpu_metrics->temperature_mem = metrics.TemperatureMem; 3141 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 3142 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 3143 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 3144 3145 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 3146 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 3147 3148 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 3149 3150 if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 3151 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs; 3152 else 3153 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs; 3154 3155 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 3156 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs; 3157 3158 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 3159 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 3160 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 3161 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 3162 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 3163 3164 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 3165 gpu_metrics->indep_throttle_status = 3166 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 3167 navi1x_throttler_map); 3168 3169 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 3170 3171 gpu_metrics->pcie_link_width = metrics.PcieWidth; 3172 gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate]; 3173 3174 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 3175 3176 if (metrics.CurrGfxVoltageOffset) 3177 gpu_metrics->voltage_gfx = 3178 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; 3179 if (metrics.CurrMemVidOffset) 3180 gpu_metrics->voltage_mem = 3181 (155000 - 625 * metrics.CurrMemVidOffset) / 100; 3182 if (metrics.CurrSocVoltageOffset) 3183 gpu_metrics->voltage_soc = 3184 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; 3185 3186 *table = (void *)gpu_metrics; 3187 3188 return sizeof(struct gpu_metrics_v1_3); 3189 } 3190 3191 static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu, 3192 void **table) 3193 { 3194 struct smu_table_context *smu_table = &smu->smu_table; 3195 struct gpu_metrics_v1_3 *gpu_metrics = 3196 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 3197 SmuMetrics_NV12_legacy_t metrics; 3198 int ret = 0; 3199 3200 ret = smu_cmn_get_metrics_table(smu, 3201 NULL, 3202 true); 3203 if (ret) 3204 return ret; 3205 3206 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_legacy_t)); 3207 3208 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 3209 3210 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 3211 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 3212 gpu_metrics->temperature_mem = metrics.TemperatureMem; 3213 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 3214 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 3215 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 3216 3217 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 3218 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 3219 3220 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 3221 3222 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 3223 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 3224 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 3225 3226 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator; 3227 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency; 3228 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency; 3229 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage; 3230 3231 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 3232 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 3233 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 3234 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 3235 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 3236 3237 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 3238 gpu_metrics->indep_throttle_status = 3239 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 3240 navi1x_throttler_map); 3241 3242 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 3243 3244 gpu_metrics->pcie_link_width = 3245 smu_v11_0_get_current_pcie_link_width(smu); 3246 gpu_metrics->pcie_link_speed = 3247 smu_v11_0_get_current_pcie_link_speed(smu); 3248 3249 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 3250 3251 if (metrics.CurrGfxVoltageOffset) 3252 gpu_metrics->voltage_gfx = 3253 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; 3254 if (metrics.CurrMemVidOffset) 3255 gpu_metrics->voltage_mem = 3256 (155000 - 625 * metrics.CurrMemVidOffset) / 100; 3257 if (metrics.CurrSocVoltageOffset) 3258 gpu_metrics->voltage_soc = 3259 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; 3260 3261 *table = (void *)gpu_metrics; 3262 3263 return sizeof(struct gpu_metrics_v1_3); 3264 } 3265 3266 static ssize_t navi12_get_gpu_metrics(struct smu_context *smu, 3267 void **table) 3268 { 3269 struct smu_table_context *smu_table = &smu->smu_table; 3270 struct gpu_metrics_v1_3 *gpu_metrics = 3271 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 3272 SmuMetrics_NV12_t metrics; 3273 int ret = 0; 3274 3275 ret = smu_cmn_get_metrics_table(smu, 3276 NULL, 3277 true); 3278 if (ret) 3279 return ret; 3280 3281 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_t)); 3282 3283 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 3284 3285 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 3286 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 3287 gpu_metrics->temperature_mem = metrics.TemperatureMem; 3288 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 3289 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 3290 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 3291 3292 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 3293 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 3294 3295 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 3296 3297 if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 3298 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs; 3299 else 3300 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs; 3301 3302 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 3303 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs; 3304 3305 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator; 3306 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency; 3307 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency; 3308 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage; 3309 3310 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 3311 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 3312 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 3313 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 3314 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 3315 3316 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 3317 gpu_metrics->indep_throttle_status = 3318 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 3319 navi1x_throttler_map); 3320 3321 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 3322 3323 gpu_metrics->pcie_link_width = metrics.PcieWidth; 3324 gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate]; 3325 3326 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 3327 3328 if (metrics.CurrGfxVoltageOffset) 3329 gpu_metrics->voltage_gfx = 3330 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; 3331 if (metrics.CurrMemVidOffset) 3332 gpu_metrics->voltage_mem = 3333 (155000 - 625 * metrics.CurrMemVidOffset) / 100; 3334 if (metrics.CurrSocVoltageOffset) 3335 gpu_metrics->voltage_soc = 3336 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; 3337 3338 *table = (void *)gpu_metrics; 3339 3340 return sizeof(struct gpu_metrics_v1_3); 3341 } 3342 3343 static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu, 3344 void **table) 3345 { 3346 struct amdgpu_device *adev = smu->adev; 3347 uint32_t smu_version; 3348 int ret = 0; 3349 3350 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 3351 if (ret) { 3352 dev_err(adev->dev, "Failed to get smu version!\n"); 3353 return ret; 3354 } 3355 3356 switch (adev->ip_versions[MP1_HWIP][0]) { 3357 case IP_VERSION(11, 0, 9): 3358 if (smu_version > 0x00341C00) 3359 ret = navi12_get_gpu_metrics(smu, table); 3360 else 3361 ret = navi12_get_legacy_gpu_metrics(smu, table); 3362 break; 3363 case IP_VERSION(11, 0, 0): 3364 case IP_VERSION(11, 0, 5): 3365 default: 3366 if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) || 3367 ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00)) 3368 ret = navi10_get_gpu_metrics(smu, table); 3369 else 3370 ret =navi10_get_legacy_gpu_metrics(smu, table); 3371 break; 3372 } 3373 3374 return ret; 3375 } 3376 3377 static int navi10_enable_mgpu_fan_boost(struct smu_context *smu) 3378 { 3379 struct smu_table_context *table_context = &smu->smu_table; 3380 PPTable_t *smc_pptable = table_context->driver_pptable; 3381 struct amdgpu_device *adev = smu->adev; 3382 uint32_t param = 0; 3383 3384 /* Navi12 does not support this */ 3385 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9)) 3386 return 0; 3387 3388 /* 3389 * Skip the MGpuFanBoost setting for those ASICs 3390 * which do not support it 3391 */ 3392 if (!smc_pptable->MGpuFanBoostLimitRpm) 3393 return 0; 3394 3395 /* Workaround for WS SKU */ 3396 if (adev->pdev->device == 0x7312 && 3397 adev->pdev->revision == 0) 3398 param = 0xD188; 3399 3400 return smu_cmn_send_smc_msg_with_param(smu, 3401 SMU_MSG_SetMGpuFanBoostLimitRpm, 3402 param, 3403 NULL); 3404 } 3405 3406 static int navi10_post_smu_init(struct smu_context *smu) 3407 { 3408 struct amdgpu_device *adev = smu->adev; 3409 int ret = 0; 3410 3411 if (amdgpu_sriov_vf(adev)) 3412 return 0; 3413 3414 ret = navi10_run_umc_cdr_workaround(smu); 3415 if (ret) { 3416 dev_err(adev->dev, "Failed to apply umc cdr workaround!\n"); 3417 return ret; 3418 } 3419 3420 if (!smu->dc_controlled_by_gpio) { 3421 /* 3422 * For Navi1X, manually switch it to AC mode as PMFW 3423 * may boot it with DC mode. 3424 */ 3425 ret = smu_v11_0_set_power_source(smu, 3426 adev->pm.ac_power ? 3427 SMU_POWER_SOURCE_AC : 3428 SMU_POWER_SOURCE_DC); 3429 if (ret) { 3430 dev_err(adev->dev, "Failed to switch to %s mode!\n", 3431 adev->pm.ac_power ? "AC" : "DC"); 3432 return ret; 3433 } 3434 } 3435 3436 return ret; 3437 } 3438 3439 static int navi10_get_default_config_table_settings(struct smu_context *smu, 3440 struct config_table_setting *table) 3441 { 3442 if (!table) 3443 return -EINVAL; 3444 3445 table->gfxclk_average_tau = 10; 3446 table->socclk_average_tau = 10; 3447 table->uclk_average_tau = 10; 3448 table->gfx_activity_average_tau = 10; 3449 table->mem_activity_average_tau = 10; 3450 table->socket_power_average_tau = 10; 3451 3452 return 0; 3453 } 3454 3455 static int navi10_set_config_table(struct smu_context *smu, 3456 struct config_table_setting *table) 3457 { 3458 DriverSmuConfig_t driver_smu_config_table; 3459 3460 if (!table) 3461 return -EINVAL; 3462 3463 memset(&driver_smu_config_table, 3464 0, 3465 sizeof(driver_smu_config_table)); 3466 3467 driver_smu_config_table.GfxclkAverageLpfTau = 3468 table->gfxclk_average_tau; 3469 driver_smu_config_table.SocclkAverageLpfTau = 3470 table->socclk_average_tau; 3471 driver_smu_config_table.UclkAverageLpfTau = 3472 table->uclk_average_tau; 3473 driver_smu_config_table.GfxActivityLpfTau = 3474 table->gfx_activity_average_tau; 3475 driver_smu_config_table.UclkActivityLpfTau = 3476 table->mem_activity_average_tau; 3477 driver_smu_config_table.SocketPowerLpfTau = 3478 table->socket_power_average_tau; 3479 3480 return smu_cmn_update_table(smu, 3481 SMU_TABLE_DRIVER_SMU_CONFIG, 3482 0, 3483 (void *)&driver_smu_config_table, 3484 true); 3485 } 3486 3487 static const struct pptable_funcs navi10_ppt_funcs = { 3488 .get_allowed_feature_mask = navi10_get_allowed_feature_mask, 3489 .set_default_dpm_table = navi10_set_default_dpm_table, 3490 .dpm_set_vcn_enable = navi10_dpm_set_vcn_enable, 3491 .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable, 3492 .i2c_init = navi10_i2c_control_init, 3493 .i2c_fini = navi10_i2c_control_fini, 3494 .print_clk_levels = navi10_print_clk_levels, 3495 .emit_clk_levels = navi10_emit_clk_levels, 3496 .force_clk_levels = navi10_force_clk_levels, 3497 .populate_umd_state_clk = navi10_populate_umd_state_clk, 3498 .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency, 3499 .pre_display_config_changed = navi10_pre_display_config_changed, 3500 .display_config_changed = navi10_display_config_changed, 3501 .notify_smc_display_config = navi10_notify_smc_display_config, 3502 .is_dpm_running = navi10_is_dpm_running, 3503 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm, 3504 .get_fan_speed_rpm = navi10_get_fan_speed_rpm, 3505 .get_power_profile_mode = navi10_get_power_profile_mode, 3506 .set_power_profile_mode = navi10_set_power_profile_mode, 3507 .set_watermarks_table = navi10_set_watermarks_table, 3508 .read_sensor = navi10_read_sensor, 3509 .get_uclk_dpm_states = navi10_get_uclk_dpm_states, 3510 .set_performance_level = smu_v11_0_set_performance_level, 3511 .get_thermal_temperature_range = navi10_get_thermal_temperature_range, 3512 .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch, 3513 .get_power_limit = navi10_get_power_limit, 3514 .update_pcie_parameters = navi10_update_pcie_parameters, 3515 .init_microcode = smu_v11_0_init_microcode, 3516 .load_microcode = smu_v11_0_load_microcode, 3517 .fini_microcode = smu_v11_0_fini_microcode, 3518 .init_smc_tables = navi10_init_smc_tables, 3519 .fini_smc_tables = smu_v11_0_fini_smc_tables, 3520 .init_power = smu_v11_0_init_power, 3521 .fini_power = smu_v11_0_fini_power, 3522 .check_fw_status = smu_v11_0_check_fw_status, 3523 .setup_pptable = navi10_setup_pptable, 3524 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, 3525 .check_fw_version = smu_v11_0_check_fw_version, 3526 .write_pptable = smu_cmn_write_pptable, 3527 .set_driver_table_location = smu_v11_0_set_driver_table_location, 3528 .set_tool_table_location = smu_v11_0_set_tool_table_location, 3529 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 3530 .system_features_control = smu_v11_0_system_features_control, 3531 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 3532 .send_smc_msg = smu_cmn_send_smc_msg, 3533 .init_display_count = smu_v11_0_init_display_count, 3534 .set_allowed_mask = smu_v11_0_set_allowed_mask, 3535 .get_enabled_mask = smu_cmn_get_enabled_mask, 3536 .feature_is_enabled = smu_cmn_feature_is_enabled, 3537 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 3538 .notify_display_change = smu_v11_0_notify_display_change, 3539 .set_power_limit = smu_v11_0_set_power_limit, 3540 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks, 3541 .enable_thermal_alert = smu_v11_0_enable_thermal_alert, 3542 .disable_thermal_alert = smu_v11_0_disable_thermal_alert, 3543 .set_min_dcef_deep_sleep = smu_v11_0_set_min_deep_sleep_dcefclk, 3544 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request, 3545 .get_fan_control_mode = smu_v11_0_get_fan_control_mode, 3546 .set_fan_control_mode = smu_v11_0_set_fan_control_mode, 3547 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm, 3548 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm, 3549 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate, 3550 .gfx_off_control = smu_v11_0_gfx_off_control, 3551 .register_irq_handler = smu_v11_0_register_irq_handler, 3552 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme, 3553 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc, 3554 .baco_is_support = smu_v11_0_baco_is_support, 3555 .baco_get_state = smu_v11_0_baco_get_state, 3556 .baco_set_state = smu_v11_0_baco_set_state, 3557 .baco_enter = navi10_baco_enter, 3558 .baco_exit = navi10_baco_exit, 3559 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq, 3560 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, 3561 .set_default_od_settings = navi10_set_default_od_settings, 3562 .od_edit_dpm_table = navi10_od_edit_dpm_table, 3563 .restore_user_od_settings = smu_v11_0_restore_user_od_settings, 3564 .run_btc = navi10_run_btc, 3565 .set_power_source = smu_v11_0_set_power_source, 3566 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 3567 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 3568 .get_gpu_metrics = navi1x_get_gpu_metrics, 3569 .enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost, 3570 .gfx_ulv_control = smu_v11_0_gfx_ulv_control, 3571 .deep_sleep_control = smu_v11_0_deep_sleep_control, 3572 .get_fan_parameters = navi10_get_fan_parameters, 3573 .post_init = navi10_post_smu_init, 3574 .interrupt_work = smu_v11_0_interrupt_work, 3575 .set_mp1_state = smu_cmn_set_mp1_state, 3576 .get_default_config_table_settings = navi10_get_default_config_table_settings, 3577 .set_config_table = navi10_set_config_table, 3578 }; 3579 3580 void navi10_set_ppt_funcs(struct smu_context *smu) 3581 { 3582 smu->ppt_funcs = &navi10_ppt_funcs; 3583 smu->message_map = navi10_message_map; 3584 smu->clock_map = navi10_clk_map; 3585 smu->feature_map = navi10_feature_mask_map; 3586 smu->table_map = navi10_table_map; 3587 smu->pwr_src_map = navi10_pwr_src_map; 3588 smu->workload_map = navi10_workload_map; 3589 smu_v11_0_set_smu_mailbox_registers(smu); 3590 } 3591