1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #define SWSMU_CODE_LAYER_L2
25 
26 #include <linux/firmware.h>
27 #include <linux/pci.h>
28 #include <linux/i2c.h>
29 #include "amdgpu.h"
30 #include "amdgpu_smu.h"
31 #include "atomfirmware.h"
32 #include "amdgpu_atomfirmware.h"
33 #include "amdgpu_atombios.h"
34 #include "soc15_common.h"
35 #include "smu_v11_0.h"
36 #include "smu11_driver_if_navi10.h"
37 #include "atom.h"
38 #include "navi10_ppt.h"
39 #include "smu_v11_0_pptable.h"
40 #include "smu_v11_0_ppsmc.h"
41 #include "nbio/nbio_2_3_offset.h"
42 #include "nbio/nbio_2_3_sh_mask.h"
43 #include "thm/thm_11_0_2_offset.h"
44 #include "thm/thm_11_0_2_sh_mask.h"
45 
46 #include "asic_reg/mp/mp_11_0_sh_mask.h"
47 #include "smu_cmn.h"
48 #include "smu_11_0_cdr_table.h"
49 
50 /*
51  * DO NOT use these for err/warn/info/debug messages.
52  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53  * They are more MGPU friendly.
54  */
55 #undef pr_err
56 #undef pr_warn
57 #undef pr_info
58 #undef pr_debug
59 
60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
61 
62 #define FEATURE_MASK(feature) (1ULL << feature)
63 #define SMC_DPM_FEATURE ( \
64 	FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
65 	FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)	 | \
66 	FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT)	 | \
67 	FEATURE_MASK(FEATURE_DPM_UCLK_BIT)	 | \
68 	FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)	 | \
69 	FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)	 | \
70 	FEATURE_MASK(FEATURE_DPM_LINK_BIT)	 | \
71 	FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
72 
73 #define SMU_11_0_GFX_BUSY_THRESHOLD 15
74 
75 static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
76 	MSG_MAP(TestMessage,			PPSMC_MSG_TestMessage,			1),
77 	MSG_MAP(GetSmuVersion,			PPSMC_MSG_GetSmuVersion,		1),
78 	MSG_MAP(GetDriverIfVersion,		PPSMC_MSG_GetDriverIfVersion,		1),
79 	MSG_MAP(SetAllowedFeaturesMaskLow,	PPSMC_MSG_SetAllowedFeaturesMaskLow,	0),
80 	MSG_MAP(SetAllowedFeaturesMaskHigh,	PPSMC_MSG_SetAllowedFeaturesMaskHigh,	0),
81 	MSG_MAP(EnableAllSmuFeatures,		PPSMC_MSG_EnableAllSmuFeatures,		0),
82 	MSG_MAP(DisableAllSmuFeatures,		PPSMC_MSG_DisableAllSmuFeatures,	0),
83 	MSG_MAP(EnableSmuFeaturesLow,		PPSMC_MSG_EnableSmuFeaturesLow,		0),
84 	MSG_MAP(EnableSmuFeaturesHigh,		PPSMC_MSG_EnableSmuFeaturesHigh,	0),
85 	MSG_MAP(DisableSmuFeaturesLow,		PPSMC_MSG_DisableSmuFeaturesLow,	0),
86 	MSG_MAP(DisableSmuFeaturesHigh,		PPSMC_MSG_DisableSmuFeaturesHigh,	0),
87 	MSG_MAP(GetEnabledSmuFeaturesLow,	PPSMC_MSG_GetEnabledSmuFeaturesLow,	1),
88 	MSG_MAP(GetEnabledSmuFeaturesHigh,	PPSMC_MSG_GetEnabledSmuFeaturesHigh,	1),
89 	MSG_MAP(SetWorkloadMask,		PPSMC_MSG_SetWorkloadMask,		1),
90 	MSG_MAP(SetPptLimit,			PPSMC_MSG_SetPptLimit,			0),
91 	MSG_MAP(SetDriverDramAddrHigh,		PPSMC_MSG_SetDriverDramAddrHigh,	0),
92 	MSG_MAP(SetDriverDramAddrLow,		PPSMC_MSG_SetDriverDramAddrLow,		0),
93 	MSG_MAP(SetToolsDramAddrHigh,		PPSMC_MSG_SetToolsDramAddrHigh,		0),
94 	MSG_MAP(SetToolsDramAddrLow,		PPSMC_MSG_SetToolsDramAddrLow,		0),
95 	MSG_MAP(TransferTableSmu2Dram,		PPSMC_MSG_TransferTableSmu2Dram,	0),
96 	MSG_MAP(TransferTableDram2Smu,		PPSMC_MSG_TransferTableDram2Smu,	0),
97 	MSG_MAP(UseDefaultPPTable,		PPSMC_MSG_UseDefaultPPTable,		0),
98 	MSG_MAP(UseBackupPPTable,		PPSMC_MSG_UseBackupPPTable,		0),
99 	MSG_MAP(RunBtc,				PPSMC_MSG_RunBtc,			0),
100 	MSG_MAP(EnterBaco,			PPSMC_MSG_EnterBaco,			0),
101 	MSG_MAP(SetSoftMinByFreq,		PPSMC_MSG_SetSoftMinByFreq,		0),
102 	MSG_MAP(SetSoftMaxByFreq,		PPSMC_MSG_SetSoftMaxByFreq,		0),
103 	MSG_MAP(SetHardMinByFreq,		PPSMC_MSG_SetHardMinByFreq,		1),
104 	MSG_MAP(SetHardMaxByFreq,		PPSMC_MSG_SetHardMaxByFreq,		0),
105 	MSG_MAP(GetMinDpmFreq,			PPSMC_MSG_GetMinDpmFreq,		1),
106 	MSG_MAP(GetMaxDpmFreq,			PPSMC_MSG_GetMaxDpmFreq,		1),
107 	MSG_MAP(GetDpmFreqByIndex,		PPSMC_MSG_GetDpmFreqByIndex,		1),
108 	MSG_MAP(SetMemoryChannelConfig,		PPSMC_MSG_SetMemoryChannelConfig,	0),
109 	MSG_MAP(SetGeminiMode,			PPSMC_MSG_SetGeminiMode,		0),
110 	MSG_MAP(SetGeminiApertureHigh,		PPSMC_MSG_SetGeminiApertureHigh,	0),
111 	MSG_MAP(SetGeminiApertureLow,		PPSMC_MSG_SetGeminiApertureLow,		0),
112 	MSG_MAP(OverridePcieParameters,		PPSMC_MSG_OverridePcieParameters,	0),
113 	MSG_MAP(SetMinDeepSleepDcefclk,		PPSMC_MSG_SetMinDeepSleepDcefclk,	0),
114 	MSG_MAP(ReenableAcDcInterrupt,		PPSMC_MSG_ReenableAcDcInterrupt,	0),
115 	MSG_MAP(NotifyPowerSource,		PPSMC_MSG_NotifyPowerSource,		0),
116 	MSG_MAP(SetUclkFastSwitch,		PPSMC_MSG_SetUclkFastSwitch,		0),
117 	MSG_MAP(SetVideoFps,			PPSMC_MSG_SetVideoFps,			0),
118 	MSG_MAP(PrepareMp1ForUnload,		PPSMC_MSG_PrepareMp1ForUnload,		1),
119 	MSG_MAP(DramLogSetDramAddrHigh,		PPSMC_MSG_DramLogSetDramAddrHigh,	0),
120 	MSG_MAP(DramLogSetDramAddrLow,		PPSMC_MSG_DramLogSetDramAddrLow,	0),
121 	MSG_MAP(DramLogSetDramSize,		PPSMC_MSG_DramLogSetDramSize,		0),
122 	MSG_MAP(ConfigureGfxDidt,		PPSMC_MSG_ConfigureGfxDidt,		0),
123 	MSG_MAP(NumOfDisplays,			PPSMC_MSG_NumOfDisplays,		0),
124 	MSG_MAP(SetSystemVirtualDramAddrHigh,	PPSMC_MSG_SetSystemVirtualDramAddrHigh,	0),
125 	MSG_MAP(SetSystemVirtualDramAddrLow,	PPSMC_MSG_SetSystemVirtualDramAddrLow,	0),
126 	MSG_MAP(AllowGfxOff,			PPSMC_MSG_AllowGfxOff,			0),
127 	MSG_MAP(DisallowGfxOff,			PPSMC_MSG_DisallowGfxOff,		0),
128 	MSG_MAP(GetPptLimit,			PPSMC_MSG_GetPptLimit,			0),
129 	MSG_MAP(GetDcModeMaxDpmFreq,		PPSMC_MSG_GetDcModeMaxDpmFreq,		1),
130 	MSG_MAP(GetDebugData,			PPSMC_MSG_GetDebugData,			0),
131 	MSG_MAP(ExitBaco,			PPSMC_MSG_ExitBaco,			0),
132 	MSG_MAP(PrepareMp1ForReset,		PPSMC_MSG_PrepareMp1ForReset,		0),
133 	MSG_MAP(PrepareMp1ForShutdown,		PPSMC_MSG_PrepareMp1ForShutdown,	0),
134 	MSG_MAP(PowerUpVcn,			PPSMC_MSG_PowerUpVcn,			0),
135 	MSG_MAP(PowerDownVcn,			PPSMC_MSG_PowerDownVcn,			0),
136 	MSG_MAP(PowerUpJpeg,			PPSMC_MSG_PowerUpJpeg,			0),
137 	MSG_MAP(PowerDownJpeg,			PPSMC_MSG_PowerDownJpeg,		0),
138 	MSG_MAP(BacoAudioD3PME,			PPSMC_MSG_BacoAudioD3PME,		0),
139 	MSG_MAP(ArmD3,				PPSMC_MSG_ArmD3,			0),
140 	MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE,PPSMC_MSG_DALDisableDummyPstateChange,	0),
141 	MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE,	PPSMC_MSG_DALEnableDummyPstateChange,	0),
142 	MSG_MAP(GetVoltageByDpm,		PPSMC_MSG_GetVoltageByDpm,		0),
143 	MSG_MAP(GetVoltageByDpmOverdrive,	PPSMC_MSG_GetVoltageByDpmOverdrive,	0),
144 	MSG_MAP(SetMGpuFanBoostLimitRpm,	PPSMC_MSG_SetMGpuFanBoostLimitRpm,	0),
145 	MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH, PPSMC_MSG_SetDriverDummyTableDramAddrHigh, 0),
146 	MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW, PPSMC_MSG_SetDriverDummyTableDramAddrLow, 0),
147 	MSG_MAP(GET_UMC_FW_WA,			PPSMC_MSG_GetUMCFWWA,			0),
148 };
149 
150 static struct cmn2asic_mapping navi10_clk_map[SMU_CLK_COUNT] = {
151 	CLK_MAP(GFXCLK, PPCLK_GFXCLK),
152 	CLK_MAP(SCLK,	PPCLK_GFXCLK),
153 	CLK_MAP(SOCCLK, PPCLK_SOCCLK),
154 	CLK_MAP(FCLK, PPCLK_SOCCLK),
155 	CLK_MAP(UCLK, PPCLK_UCLK),
156 	CLK_MAP(MCLK, PPCLK_UCLK),
157 	CLK_MAP(DCLK, PPCLK_DCLK),
158 	CLK_MAP(VCLK, PPCLK_VCLK),
159 	CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
160 	CLK_MAP(DISPCLK, PPCLK_DISPCLK),
161 	CLK_MAP(PIXCLK, PPCLK_PIXCLK),
162 	CLK_MAP(PHYCLK, PPCLK_PHYCLK),
163 };
164 
165 static struct cmn2asic_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
166 	FEA_MAP(DPM_PREFETCHER),
167 	FEA_MAP(DPM_GFXCLK),
168 	FEA_MAP(DPM_GFX_PACE),
169 	FEA_MAP(DPM_UCLK),
170 	FEA_MAP(DPM_SOCCLK),
171 	FEA_MAP(DPM_MP0CLK),
172 	FEA_MAP(DPM_LINK),
173 	FEA_MAP(DPM_DCEFCLK),
174 	FEA_MAP(MEM_VDDCI_SCALING),
175 	FEA_MAP(MEM_MVDD_SCALING),
176 	FEA_MAP(DS_GFXCLK),
177 	FEA_MAP(DS_SOCCLK),
178 	FEA_MAP(DS_LCLK),
179 	FEA_MAP(DS_DCEFCLK),
180 	FEA_MAP(DS_UCLK),
181 	FEA_MAP(GFX_ULV),
182 	FEA_MAP(FW_DSTATE),
183 	FEA_MAP(GFXOFF),
184 	FEA_MAP(BACO),
185 	FEA_MAP(VCN_PG),
186 	FEA_MAP(JPEG_PG),
187 	FEA_MAP(USB_PG),
188 	FEA_MAP(RSMU_SMN_CG),
189 	FEA_MAP(PPT),
190 	FEA_MAP(TDC),
191 	FEA_MAP(GFX_EDC),
192 	FEA_MAP(APCC_PLUS),
193 	FEA_MAP(GTHR),
194 	FEA_MAP(ACDC),
195 	FEA_MAP(VR0HOT),
196 	FEA_MAP(VR1HOT),
197 	FEA_MAP(FW_CTF),
198 	FEA_MAP(FAN_CONTROL),
199 	FEA_MAP(THERMAL),
200 	FEA_MAP(GFX_DCS),
201 	FEA_MAP(RM),
202 	FEA_MAP(LED_DISPLAY),
203 	FEA_MAP(GFX_SS),
204 	FEA_MAP(OUT_OF_BAND_MONITOR),
205 	FEA_MAP(TEMP_DEPENDENT_VMIN),
206 	FEA_MAP(MMHUB_PG),
207 	FEA_MAP(ATHUB_PG),
208 	FEA_MAP(APCC_DFLL),
209 };
210 
211 static struct cmn2asic_mapping navi10_table_map[SMU_TABLE_COUNT] = {
212 	TAB_MAP(PPTABLE),
213 	TAB_MAP(WATERMARKS),
214 	TAB_MAP(AVFS),
215 	TAB_MAP(AVFS_PSM_DEBUG),
216 	TAB_MAP(AVFS_FUSE_OVERRIDE),
217 	TAB_MAP(PMSTATUSLOG),
218 	TAB_MAP(SMU_METRICS),
219 	TAB_MAP(DRIVER_SMU_CONFIG),
220 	TAB_MAP(ACTIVITY_MONITOR_COEFF),
221 	TAB_MAP(OVERDRIVE),
222 	TAB_MAP(I2C_COMMANDS),
223 	TAB_MAP(PACE),
224 };
225 
226 static struct cmn2asic_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
227 	PWR_MAP(AC),
228 	PWR_MAP(DC),
229 };
230 
231 static struct cmn2asic_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
232 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,	WORKLOAD_PPLIB_DEFAULT_BIT),
233 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,		WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
234 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,		WORKLOAD_PPLIB_POWER_SAVING_BIT),
235 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,		WORKLOAD_PPLIB_VIDEO_BIT),
236 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,			WORKLOAD_PPLIB_VR_BIT),
237 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,		WORKLOAD_PPLIB_COMPUTE_BIT),
238 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,		WORKLOAD_PPLIB_CUSTOM_BIT),
239 };
240 
241 static const uint8_t navi1x_throttler_map[] = {
242 	[THROTTLER_TEMP_EDGE_BIT]	= (SMU_THROTTLER_TEMP_EDGE_BIT),
243 	[THROTTLER_TEMP_HOTSPOT_BIT]	= (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
244 	[THROTTLER_TEMP_MEM_BIT]	= (SMU_THROTTLER_TEMP_MEM_BIT),
245 	[THROTTLER_TEMP_VR_GFX_BIT]	= (SMU_THROTTLER_TEMP_VR_GFX_BIT),
246 	[THROTTLER_TEMP_VR_MEM0_BIT]	= (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
247 	[THROTTLER_TEMP_VR_MEM1_BIT]	= (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
248 	[THROTTLER_TEMP_VR_SOC_BIT]	= (SMU_THROTTLER_TEMP_VR_SOC_BIT),
249 	[THROTTLER_TEMP_LIQUID0_BIT]	= (SMU_THROTTLER_TEMP_LIQUID0_BIT),
250 	[THROTTLER_TEMP_LIQUID1_BIT]	= (SMU_THROTTLER_TEMP_LIQUID1_BIT),
251 	[THROTTLER_TDC_GFX_BIT]		= (SMU_THROTTLER_TDC_GFX_BIT),
252 	[THROTTLER_TDC_SOC_BIT]		= (SMU_THROTTLER_TDC_SOC_BIT),
253 	[THROTTLER_PPT0_BIT]		= (SMU_THROTTLER_PPT0_BIT),
254 	[THROTTLER_PPT1_BIT]		= (SMU_THROTTLER_PPT1_BIT),
255 	[THROTTLER_PPT2_BIT]		= (SMU_THROTTLER_PPT2_BIT),
256 	[THROTTLER_PPT3_BIT]		= (SMU_THROTTLER_PPT3_BIT),
257 	[THROTTLER_FIT_BIT]		= (SMU_THROTTLER_FIT_BIT),
258 	[THROTTLER_PPM_BIT]		= (SMU_THROTTLER_PPM_BIT),
259 	[THROTTLER_APCC_BIT]		= (SMU_THROTTLER_APCC_BIT),
260 };
261 
262 
263 static bool is_asic_secure(struct smu_context *smu)
264 {
265 	struct amdgpu_device *adev = smu->adev;
266 	bool is_secure = true;
267 	uint32_t mp0_fw_intf;
268 
269 	mp0_fw_intf = RREG32_PCIE(MP0_Public |
270 				   (smnMP0_FW_INTF & 0xffffffff));
271 
272 	if (!(mp0_fw_intf & (1 << 19)))
273 		is_secure = false;
274 
275 	return is_secure;
276 }
277 
278 static int
279 navi10_get_allowed_feature_mask(struct smu_context *smu,
280 				  uint32_t *feature_mask, uint32_t num)
281 {
282 	struct amdgpu_device *adev = smu->adev;
283 
284 	if (num > 2)
285 		return -EINVAL;
286 
287 	memset(feature_mask, 0, sizeof(uint32_t) * num);
288 
289 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
290 				| FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
291 				| FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
292 				| FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
293 				| FEATURE_MASK(FEATURE_PPT_BIT)
294 				| FEATURE_MASK(FEATURE_TDC_BIT)
295 				| FEATURE_MASK(FEATURE_GFX_EDC_BIT)
296 				| FEATURE_MASK(FEATURE_APCC_PLUS_BIT)
297 				| FEATURE_MASK(FEATURE_VR0HOT_BIT)
298 				| FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
299 				| FEATURE_MASK(FEATURE_THERMAL_BIT)
300 				| FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
301 				| FEATURE_MASK(FEATURE_DS_LCLK_BIT)
302 				| FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
303 				| FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
304 				| FEATURE_MASK(FEATURE_BACO_BIT)
305 				| FEATURE_MASK(FEATURE_GFX_SS_BIT)
306 				| FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
307 				| FEATURE_MASK(FEATURE_FW_CTF_BIT)
308 				| FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
309 
310 	if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
311 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
312 
313 	if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
314 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
315 
316 	if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
317 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
318 
319 	if (adev->pm.pp_feature & PP_ULV_MASK)
320 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
321 
322 	if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
323 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
324 
325 	if (adev->pm.pp_feature & PP_GFXOFF_MASK)
326 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
327 
328 	if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
329 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
330 
331 	if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
332 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
333 
334 	if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
335 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
336 
337 	if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
338 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);
339 
340 	if (smu->dc_controlled_by_gpio)
341 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
342 
343 	if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
344 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
345 
346 	/* DPM UCLK enablement should be skipped for navi10 A0 secure board */
347 	if (!(is_asic_secure(smu) &&
348 	     (adev->asic_type == CHIP_NAVI10) &&
349 	     (adev->rev_id == 0)) &&
350 	    (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
351 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
352 				| FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
353 				| FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
354 
355 	/* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
356 	if (is_asic_secure(smu) &&
357 	    (adev->asic_type == CHIP_NAVI10) &&
358 	    (adev->rev_id == 0))
359 		*(uint64_t *)feature_mask &=
360 				~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
361 
362 	return 0;
363 }
364 
365 static void navi10_check_bxco_support(struct smu_context *smu)
366 {
367 	struct smu_table_context *table_context = &smu->smu_table;
368 	struct smu_11_0_powerplay_table *powerplay_table =
369 		table_context->power_play_table;
370 	struct smu_baco_context *smu_baco = &smu->smu_baco;
371 	struct amdgpu_device *adev = smu->adev;
372 	uint32_t val;
373 
374 	if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
375 	    powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) {
376 		val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
377 		smu_baco->platform_support =
378 			(val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
379 									false;
380 	}
381 }
382 
383 static int navi10_check_powerplay_table(struct smu_context *smu)
384 {
385 	struct smu_table_context *table_context = &smu->smu_table;
386 	struct smu_11_0_powerplay_table *powerplay_table =
387 		table_context->power_play_table;
388 
389 	if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC)
390 		smu->dc_controlled_by_gpio = true;
391 
392 	navi10_check_bxco_support(smu);
393 
394 	table_context->thermal_controller_type =
395 		powerplay_table->thermal_controller_type;
396 
397 	/*
398 	 * Instead of having its own buffer space and get overdrive_table copied,
399 	 * smu->od_settings just points to the actual overdrive_table
400 	 */
401 	smu->od_settings = &powerplay_table->overdrive_table;
402 
403 	return 0;
404 }
405 
406 static int navi10_append_powerplay_table(struct smu_context *smu)
407 {
408 	struct amdgpu_device *adev = smu->adev;
409 	struct smu_table_context *table_context = &smu->smu_table;
410 	PPTable_t *smc_pptable = table_context->driver_pptable;
411 	struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
412 	struct atom_smc_dpm_info_v4_7 *smc_dpm_table_v4_7;
413 	int index, ret;
414 
415 	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
416 					   smc_dpm_info);
417 
418 	ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL,
419 				      (uint8_t **)&smc_dpm_table);
420 	if (ret)
421 		return ret;
422 
423 	dev_info(adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
424 			smc_dpm_table->table_header.format_revision,
425 			smc_dpm_table->table_header.content_revision);
426 
427 	if (smc_dpm_table->table_header.format_revision != 4) {
428 		dev_err(adev->dev, "smc_dpm_info table format revision is not 4!\n");
429 		return -EINVAL;
430 	}
431 
432 	switch (smc_dpm_table->table_header.content_revision) {
433 	case 5: /* nv10 and nv14 */
434 		memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
435 			sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
436 		break;
437 	case 7: /* nv12 */
438 		ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL,
439 					      (uint8_t **)&smc_dpm_table_v4_7);
440 		if (ret)
441 			return ret;
442 		memcpy(smc_pptable->I2cControllers, smc_dpm_table_v4_7->I2cControllers,
443 			sizeof(*smc_dpm_table_v4_7) - sizeof(smc_dpm_table_v4_7->table_header));
444 		break;
445 	default:
446 		dev_err(smu->adev->dev, "smc_dpm_info with unsupported content revision %d!\n",
447 				smc_dpm_table->table_header.content_revision);
448 		return -EINVAL;
449 	}
450 
451 	if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
452 		/* TODO: remove it once SMU fw fix it */
453 		smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
454 	}
455 
456 	return 0;
457 }
458 
459 static int navi10_store_powerplay_table(struct smu_context *smu)
460 {
461 	struct smu_table_context *table_context = &smu->smu_table;
462 	struct smu_11_0_powerplay_table *powerplay_table =
463 		table_context->power_play_table;
464 
465 	memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
466 	       sizeof(PPTable_t));
467 
468 	return 0;
469 }
470 
471 static int navi10_setup_pptable(struct smu_context *smu)
472 {
473 	int ret = 0;
474 
475 	ret = smu_v11_0_setup_pptable(smu);
476 	if (ret)
477 		return ret;
478 
479 	ret = navi10_store_powerplay_table(smu);
480 	if (ret)
481 		return ret;
482 
483 	ret = navi10_append_powerplay_table(smu);
484 	if (ret)
485 		return ret;
486 
487 	ret = navi10_check_powerplay_table(smu);
488 	if (ret)
489 		return ret;
490 
491 	return ret;
492 }
493 
494 static int navi10_tables_init(struct smu_context *smu)
495 {
496 	struct smu_table_context *smu_table = &smu->smu_table;
497 	struct smu_table *tables = smu_table->tables;
498 
499 	SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
500 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
501 	SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
502 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
503 	SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_NV1X_t),
504 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
505 	SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
506 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
507 	SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
508 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
509 	SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
510 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
511 	SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
512 		       sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
513 		       AMDGPU_GEM_DOMAIN_VRAM);
514 
515 	smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_NV1X_t),
516 					   GFP_KERNEL);
517 	if (!smu_table->metrics_table)
518 		goto err0_out;
519 	smu_table->metrics_time = 0;
520 
521 	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
522 	smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
523 	if (!smu_table->gpu_metrics_table)
524 		goto err1_out;
525 
526 	smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
527 	if (!smu_table->watermarks_table)
528 		goto err2_out;
529 
530 	return 0;
531 
532 err2_out:
533 	kfree(smu_table->gpu_metrics_table);
534 err1_out:
535 	kfree(smu_table->metrics_table);
536 err0_out:
537 	return -ENOMEM;
538 }
539 
540 static int navi10_get_legacy_smu_metrics_data(struct smu_context *smu,
541 					      MetricsMember_t member,
542 					      uint32_t *value)
543 {
544 	struct smu_table_context *smu_table= &smu->smu_table;
545 	SmuMetrics_legacy_t *metrics =
546 		(SmuMetrics_legacy_t *)smu_table->metrics_table;
547 	int ret = 0;
548 
549 	mutex_lock(&smu->metrics_lock);
550 
551 	ret = smu_cmn_get_metrics_table_locked(smu,
552 					       NULL,
553 					       false);
554 	if (ret) {
555 		mutex_unlock(&smu->metrics_lock);
556 		return ret;
557 	}
558 
559 	switch (member) {
560 	case METRICS_CURR_GFXCLK:
561 		*value = metrics->CurrClock[PPCLK_GFXCLK];
562 		break;
563 	case METRICS_CURR_SOCCLK:
564 		*value = metrics->CurrClock[PPCLK_SOCCLK];
565 		break;
566 	case METRICS_CURR_UCLK:
567 		*value = metrics->CurrClock[PPCLK_UCLK];
568 		break;
569 	case METRICS_CURR_VCLK:
570 		*value = metrics->CurrClock[PPCLK_VCLK];
571 		break;
572 	case METRICS_CURR_DCLK:
573 		*value = metrics->CurrClock[PPCLK_DCLK];
574 		break;
575 	case METRICS_CURR_DCEFCLK:
576 		*value = metrics->CurrClock[PPCLK_DCEFCLK];
577 		break;
578 	case METRICS_AVERAGE_GFXCLK:
579 		*value = metrics->AverageGfxclkFrequency;
580 		break;
581 	case METRICS_AVERAGE_SOCCLK:
582 		*value = metrics->AverageSocclkFrequency;
583 		break;
584 	case METRICS_AVERAGE_UCLK:
585 		*value = metrics->AverageUclkFrequency;
586 		break;
587 	case METRICS_AVERAGE_GFXACTIVITY:
588 		*value = metrics->AverageGfxActivity;
589 		break;
590 	case METRICS_AVERAGE_MEMACTIVITY:
591 		*value = metrics->AverageUclkActivity;
592 		break;
593 	case METRICS_AVERAGE_SOCKETPOWER:
594 		*value = metrics->AverageSocketPower << 8;
595 		break;
596 	case METRICS_TEMPERATURE_EDGE:
597 		*value = metrics->TemperatureEdge *
598 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
599 		break;
600 	case METRICS_TEMPERATURE_HOTSPOT:
601 		*value = metrics->TemperatureHotspot *
602 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
603 		break;
604 	case METRICS_TEMPERATURE_MEM:
605 		*value = metrics->TemperatureMem *
606 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
607 		break;
608 	case METRICS_TEMPERATURE_VRGFX:
609 		*value = metrics->TemperatureVrGfx *
610 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
611 		break;
612 	case METRICS_TEMPERATURE_VRSOC:
613 		*value = metrics->TemperatureVrSoc *
614 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
615 		break;
616 	case METRICS_THROTTLER_STATUS:
617 		*value = metrics->ThrottlerStatus;
618 		break;
619 	case METRICS_CURR_FANSPEED:
620 		*value = metrics->CurrFanSpeed;
621 		break;
622 	default:
623 		*value = UINT_MAX;
624 		break;
625 	}
626 
627 	mutex_unlock(&smu->metrics_lock);
628 
629 	return ret;
630 }
631 
632 static int navi10_get_smu_metrics_data(struct smu_context *smu,
633 				       MetricsMember_t member,
634 				       uint32_t *value)
635 {
636 	struct smu_table_context *smu_table= &smu->smu_table;
637 	SmuMetrics_t *metrics =
638 		(SmuMetrics_t *)smu_table->metrics_table;
639 	int ret = 0;
640 
641 	mutex_lock(&smu->metrics_lock);
642 
643 	ret = smu_cmn_get_metrics_table_locked(smu,
644 					       NULL,
645 					       false);
646 	if (ret) {
647 		mutex_unlock(&smu->metrics_lock);
648 		return ret;
649 	}
650 
651 	switch (member) {
652 	case METRICS_CURR_GFXCLK:
653 		*value = metrics->CurrClock[PPCLK_GFXCLK];
654 		break;
655 	case METRICS_CURR_SOCCLK:
656 		*value = metrics->CurrClock[PPCLK_SOCCLK];
657 		break;
658 	case METRICS_CURR_UCLK:
659 		*value = metrics->CurrClock[PPCLK_UCLK];
660 		break;
661 	case METRICS_CURR_VCLK:
662 		*value = metrics->CurrClock[PPCLK_VCLK];
663 		break;
664 	case METRICS_CURR_DCLK:
665 		*value = metrics->CurrClock[PPCLK_DCLK];
666 		break;
667 	case METRICS_CURR_DCEFCLK:
668 		*value = metrics->CurrClock[PPCLK_DCEFCLK];
669 		break;
670 	case METRICS_AVERAGE_GFXCLK:
671 		if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
672 			*value = metrics->AverageGfxclkFrequencyPreDs;
673 		else
674 			*value = metrics->AverageGfxclkFrequencyPostDs;
675 		break;
676 	case METRICS_AVERAGE_SOCCLK:
677 		*value = metrics->AverageSocclkFrequency;
678 		break;
679 	case METRICS_AVERAGE_UCLK:
680 		*value = metrics->AverageUclkFrequencyPostDs;
681 		break;
682 	case METRICS_AVERAGE_GFXACTIVITY:
683 		*value = metrics->AverageGfxActivity;
684 		break;
685 	case METRICS_AVERAGE_MEMACTIVITY:
686 		*value = metrics->AverageUclkActivity;
687 		break;
688 	case METRICS_AVERAGE_SOCKETPOWER:
689 		*value = metrics->AverageSocketPower << 8;
690 		break;
691 	case METRICS_TEMPERATURE_EDGE:
692 		*value = metrics->TemperatureEdge *
693 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
694 		break;
695 	case METRICS_TEMPERATURE_HOTSPOT:
696 		*value = metrics->TemperatureHotspot *
697 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
698 		break;
699 	case METRICS_TEMPERATURE_MEM:
700 		*value = metrics->TemperatureMem *
701 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
702 		break;
703 	case METRICS_TEMPERATURE_VRGFX:
704 		*value = metrics->TemperatureVrGfx *
705 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
706 		break;
707 	case METRICS_TEMPERATURE_VRSOC:
708 		*value = metrics->TemperatureVrSoc *
709 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
710 		break;
711 	case METRICS_THROTTLER_STATUS:
712 		*value = metrics->ThrottlerStatus;
713 		break;
714 	case METRICS_CURR_FANSPEED:
715 		*value = metrics->CurrFanSpeed;
716 		break;
717 	default:
718 		*value = UINT_MAX;
719 		break;
720 	}
721 
722 	mutex_unlock(&smu->metrics_lock);
723 
724 	return ret;
725 }
726 
727 static int navi12_get_legacy_smu_metrics_data(struct smu_context *smu,
728 					      MetricsMember_t member,
729 					      uint32_t *value)
730 {
731 	struct smu_table_context *smu_table= &smu->smu_table;
732 	SmuMetrics_NV12_legacy_t *metrics =
733 		(SmuMetrics_NV12_legacy_t *)smu_table->metrics_table;
734 	int ret = 0;
735 
736 	mutex_lock(&smu->metrics_lock);
737 
738 	ret = smu_cmn_get_metrics_table_locked(smu,
739 					       NULL,
740 					       false);
741 	if (ret) {
742 		mutex_unlock(&smu->metrics_lock);
743 		return ret;
744 	}
745 
746 	switch (member) {
747 	case METRICS_CURR_GFXCLK:
748 		*value = metrics->CurrClock[PPCLK_GFXCLK];
749 		break;
750 	case METRICS_CURR_SOCCLK:
751 		*value = metrics->CurrClock[PPCLK_SOCCLK];
752 		break;
753 	case METRICS_CURR_UCLK:
754 		*value = metrics->CurrClock[PPCLK_UCLK];
755 		break;
756 	case METRICS_CURR_VCLK:
757 		*value = metrics->CurrClock[PPCLK_VCLK];
758 		break;
759 	case METRICS_CURR_DCLK:
760 		*value = metrics->CurrClock[PPCLK_DCLK];
761 		break;
762 	case METRICS_CURR_DCEFCLK:
763 		*value = metrics->CurrClock[PPCLK_DCEFCLK];
764 		break;
765 	case METRICS_AVERAGE_GFXCLK:
766 		*value = metrics->AverageGfxclkFrequency;
767 		break;
768 	case METRICS_AVERAGE_SOCCLK:
769 		*value = metrics->AverageSocclkFrequency;
770 		break;
771 	case METRICS_AVERAGE_UCLK:
772 		*value = metrics->AverageUclkFrequency;
773 		break;
774 	case METRICS_AVERAGE_GFXACTIVITY:
775 		*value = metrics->AverageGfxActivity;
776 		break;
777 	case METRICS_AVERAGE_MEMACTIVITY:
778 		*value = metrics->AverageUclkActivity;
779 		break;
780 	case METRICS_AVERAGE_SOCKETPOWER:
781 		*value = metrics->AverageSocketPower << 8;
782 		break;
783 	case METRICS_TEMPERATURE_EDGE:
784 		*value = metrics->TemperatureEdge *
785 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
786 		break;
787 	case METRICS_TEMPERATURE_HOTSPOT:
788 		*value = metrics->TemperatureHotspot *
789 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
790 		break;
791 	case METRICS_TEMPERATURE_MEM:
792 		*value = metrics->TemperatureMem *
793 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
794 		break;
795 	case METRICS_TEMPERATURE_VRGFX:
796 		*value = metrics->TemperatureVrGfx *
797 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
798 		break;
799 	case METRICS_TEMPERATURE_VRSOC:
800 		*value = metrics->TemperatureVrSoc *
801 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
802 		break;
803 	case METRICS_THROTTLER_STATUS:
804 		*value = metrics->ThrottlerStatus;
805 		break;
806 	case METRICS_CURR_FANSPEED:
807 		*value = metrics->CurrFanSpeed;
808 		break;
809 	default:
810 		*value = UINT_MAX;
811 		break;
812 	}
813 
814 	mutex_unlock(&smu->metrics_lock);
815 
816 	return ret;
817 }
818 
819 static int navi12_get_smu_metrics_data(struct smu_context *smu,
820 				       MetricsMember_t member,
821 				       uint32_t *value)
822 {
823 	struct smu_table_context *smu_table= &smu->smu_table;
824 	SmuMetrics_NV12_t *metrics =
825 		(SmuMetrics_NV12_t *)smu_table->metrics_table;
826 	int ret = 0;
827 
828 	mutex_lock(&smu->metrics_lock);
829 
830 	ret = smu_cmn_get_metrics_table_locked(smu,
831 					       NULL,
832 					       false);
833 	if (ret) {
834 		mutex_unlock(&smu->metrics_lock);
835 		return ret;
836 	}
837 
838 	switch (member) {
839 	case METRICS_CURR_GFXCLK:
840 		*value = metrics->CurrClock[PPCLK_GFXCLK];
841 		break;
842 	case METRICS_CURR_SOCCLK:
843 		*value = metrics->CurrClock[PPCLK_SOCCLK];
844 		break;
845 	case METRICS_CURR_UCLK:
846 		*value = metrics->CurrClock[PPCLK_UCLK];
847 		break;
848 	case METRICS_CURR_VCLK:
849 		*value = metrics->CurrClock[PPCLK_VCLK];
850 		break;
851 	case METRICS_CURR_DCLK:
852 		*value = metrics->CurrClock[PPCLK_DCLK];
853 		break;
854 	case METRICS_CURR_DCEFCLK:
855 		*value = metrics->CurrClock[PPCLK_DCEFCLK];
856 		break;
857 	case METRICS_AVERAGE_GFXCLK:
858 		if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
859 			*value = metrics->AverageGfxclkFrequencyPreDs;
860 		else
861 			*value = metrics->AverageGfxclkFrequencyPostDs;
862 		break;
863 	case METRICS_AVERAGE_SOCCLK:
864 		*value = metrics->AverageSocclkFrequency;
865 		break;
866 	case METRICS_AVERAGE_UCLK:
867 		*value = metrics->AverageUclkFrequencyPostDs;
868 		break;
869 	case METRICS_AVERAGE_GFXACTIVITY:
870 		*value = metrics->AverageGfxActivity;
871 		break;
872 	case METRICS_AVERAGE_MEMACTIVITY:
873 		*value = metrics->AverageUclkActivity;
874 		break;
875 	case METRICS_AVERAGE_SOCKETPOWER:
876 		*value = metrics->AverageSocketPower << 8;
877 		break;
878 	case METRICS_TEMPERATURE_EDGE:
879 		*value = metrics->TemperatureEdge *
880 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
881 		break;
882 	case METRICS_TEMPERATURE_HOTSPOT:
883 		*value = metrics->TemperatureHotspot *
884 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
885 		break;
886 	case METRICS_TEMPERATURE_MEM:
887 		*value = metrics->TemperatureMem *
888 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
889 		break;
890 	case METRICS_TEMPERATURE_VRGFX:
891 		*value = metrics->TemperatureVrGfx *
892 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
893 		break;
894 	case METRICS_TEMPERATURE_VRSOC:
895 		*value = metrics->TemperatureVrSoc *
896 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
897 		break;
898 	case METRICS_THROTTLER_STATUS:
899 		*value = metrics->ThrottlerStatus;
900 		break;
901 	case METRICS_CURR_FANSPEED:
902 		*value = metrics->CurrFanSpeed;
903 		break;
904 	default:
905 		*value = UINT_MAX;
906 		break;
907 	}
908 
909 	mutex_unlock(&smu->metrics_lock);
910 
911 	return ret;
912 }
913 
914 static int navi1x_get_smu_metrics_data(struct smu_context *smu,
915 				       MetricsMember_t member,
916 				       uint32_t *value)
917 {
918 	struct amdgpu_device *adev = smu->adev;
919 	uint32_t smu_version;
920 	int ret = 0;
921 
922 	ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
923 	if (ret) {
924 		dev_err(adev->dev, "Failed to get smu version!\n");
925 		return ret;
926 	}
927 
928 	switch (adev->asic_type) {
929 	case CHIP_NAVI12:
930 		if (smu_version > 0x00341C00)
931 			ret = navi12_get_smu_metrics_data(smu, member, value);
932 		else
933 			ret = navi12_get_legacy_smu_metrics_data(smu, member, value);
934 		break;
935 	case CHIP_NAVI10:
936 	case CHIP_NAVI14:
937 	default:
938 		if (((adev->asic_type == CHIP_NAVI14) && smu_version > 0x00351F00) ||
939 		      ((adev->asic_type == CHIP_NAVI10) && smu_version > 0x002A3B00))
940 			ret = navi10_get_smu_metrics_data(smu, member, value);
941 		else
942 			ret = navi10_get_legacy_smu_metrics_data(smu, member, value);
943 		break;
944 	}
945 
946 	return ret;
947 }
948 
949 static int navi10_allocate_dpm_context(struct smu_context *smu)
950 {
951 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
952 
953 	smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
954 				       GFP_KERNEL);
955 	if (!smu_dpm->dpm_context)
956 		return -ENOMEM;
957 
958 	smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
959 
960 	return 0;
961 }
962 
963 static int navi10_init_smc_tables(struct smu_context *smu)
964 {
965 	int ret = 0;
966 
967 	ret = navi10_tables_init(smu);
968 	if (ret)
969 		return ret;
970 
971 	ret = navi10_allocate_dpm_context(smu);
972 	if (ret)
973 		return ret;
974 
975 	return smu_v11_0_init_smc_tables(smu);
976 }
977 
978 static int navi10_set_default_dpm_table(struct smu_context *smu)
979 {
980 	struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
981 	PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
982 	struct smu_11_0_dpm_table *dpm_table;
983 	int ret = 0;
984 
985 	/* socclk dpm table setup */
986 	dpm_table = &dpm_context->dpm_tables.soc_table;
987 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
988 		ret = smu_v11_0_set_single_dpm_table(smu,
989 						     SMU_SOCCLK,
990 						     dpm_table);
991 		if (ret)
992 			return ret;
993 		dpm_table->is_fine_grained =
994 			!driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
995 	} else {
996 		dpm_table->count = 1;
997 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
998 		dpm_table->dpm_levels[0].enabled = true;
999 		dpm_table->min = dpm_table->dpm_levels[0].value;
1000 		dpm_table->max = dpm_table->dpm_levels[0].value;
1001 	}
1002 
1003 	/* gfxclk dpm table setup */
1004 	dpm_table = &dpm_context->dpm_tables.gfx_table;
1005 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
1006 		ret = smu_v11_0_set_single_dpm_table(smu,
1007 						     SMU_GFXCLK,
1008 						     dpm_table);
1009 		if (ret)
1010 			return ret;
1011 		dpm_table->is_fine_grained =
1012 			!driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
1013 	} else {
1014 		dpm_table->count = 1;
1015 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
1016 		dpm_table->dpm_levels[0].enabled = true;
1017 		dpm_table->min = dpm_table->dpm_levels[0].value;
1018 		dpm_table->max = dpm_table->dpm_levels[0].value;
1019 	}
1020 
1021 	/* uclk dpm table setup */
1022 	dpm_table = &dpm_context->dpm_tables.uclk_table;
1023 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1024 		ret = smu_v11_0_set_single_dpm_table(smu,
1025 						     SMU_UCLK,
1026 						     dpm_table);
1027 		if (ret)
1028 			return ret;
1029 		dpm_table->is_fine_grained =
1030 			!driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
1031 	} else {
1032 		dpm_table->count = 1;
1033 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
1034 		dpm_table->dpm_levels[0].enabled = true;
1035 		dpm_table->min = dpm_table->dpm_levels[0].value;
1036 		dpm_table->max = dpm_table->dpm_levels[0].value;
1037 	}
1038 
1039 	/* vclk dpm table setup */
1040 	dpm_table = &dpm_context->dpm_tables.vclk_table;
1041 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1042 		ret = smu_v11_0_set_single_dpm_table(smu,
1043 						     SMU_VCLK,
1044 						     dpm_table);
1045 		if (ret)
1046 			return ret;
1047 		dpm_table->is_fine_grained =
1048 			!driver_ppt->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete;
1049 	} else {
1050 		dpm_table->count = 1;
1051 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
1052 		dpm_table->dpm_levels[0].enabled = true;
1053 		dpm_table->min = dpm_table->dpm_levels[0].value;
1054 		dpm_table->max = dpm_table->dpm_levels[0].value;
1055 	}
1056 
1057 	/* dclk dpm table setup */
1058 	dpm_table = &dpm_context->dpm_tables.dclk_table;
1059 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1060 		ret = smu_v11_0_set_single_dpm_table(smu,
1061 						     SMU_DCLK,
1062 						     dpm_table);
1063 		if (ret)
1064 			return ret;
1065 		dpm_table->is_fine_grained =
1066 			!driver_ppt->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete;
1067 	} else {
1068 		dpm_table->count = 1;
1069 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
1070 		dpm_table->dpm_levels[0].enabled = true;
1071 		dpm_table->min = dpm_table->dpm_levels[0].value;
1072 		dpm_table->max = dpm_table->dpm_levels[0].value;
1073 	}
1074 
1075 	/* dcefclk dpm table setup */
1076 	dpm_table = &dpm_context->dpm_tables.dcef_table;
1077 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1078 		ret = smu_v11_0_set_single_dpm_table(smu,
1079 						     SMU_DCEFCLK,
1080 						     dpm_table);
1081 		if (ret)
1082 			return ret;
1083 		dpm_table->is_fine_grained =
1084 			!driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete;
1085 	} else {
1086 		dpm_table->count = 1;
1087 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1088 		dpm_table->dpm_levels[0].enabled = true;
1089 		dpm_table->min = dpm_table->dpm_levels[0].value;
1090 		dpm_table->max = dpm_table->dpm_levels[0].value;
1091 	}
1092 
1093 	/* pixelclk dpm table setup */
1094 	dpm_table = &dpm_context->dpm_tables.pixel_table;
1095 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1096 		ret = smu_v11_0_set_single_dpm_table(smu,
1097 						     SMU_PIXCLK,
1098 						     dpm_table);
1099 		if (ret)
1100 			return ret;
1101 		dpm_table->is_fine_grained =
1102 			!driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete;
1103 	} else {
1104 		dpm_table->count = 1;
1105 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1106 		dpm_table->dpm_levels[0].enabled = true;
1107 		dpm_table->min = dpm_table->dpm_levels[0].value;
1108 		dpm_table->max = dpm_table->dpm_levels[0].value;
1109 	}
1110 
1111 	/* displayclk dpm table setup */
1112 	dpm_table = &dpm_context->dpm_tables.display_table;
1113 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1114 		ret = smu_v11_0_set_single_dpm_table(smu,
1115 						     SMU_DISPCLK,
1116 						     dpm_table);
1117 		if (ret)
1118 			return ret;
1119 		dpm_table->is_fine_grained =
1120 			!driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete;
1121 	} else {
1122 		dpm_table->count = 1;
1123 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1124 		dpm_table->dpm_levels[0].enabled = true;
1125 		dpm_table->min = dpm_table->dpm_levels[0].value;
1126 		dpm_table->max = dpm_table->dpm_levels[0].value;
1127 	}
1128 
1129 	/* phyclk dpm table setup */
1130 	dpm_table = &dpm_context->dpm_tables.phy_table;
1131 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1132 		ret = smu_v11_0_set_single_dpm_table(smu,
1133 						     SMU_PHYCLK,
1134 						     dpm_table);
1135 		if (ret)
1136 			return ret;
1137 		dpm_table->is_fine_grained =
1138 			!driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete;
1139 	} else {
1140 		dpm_table->count = 1;
1141 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1142 		dpm_table->dpm_levels[0].enabled = true;
1143 		dpm_table->min = dpm_table->dpm_levels[0].value;
1144 		dpm_table->max = dpm_table->dpm_levels[0].value;
1145 	}
1146 
1147 	return 0;
1148 }
1149 
1150 static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1151 {
1152 	int ret = 0;
1153 
1154 	if (enable) {
1155 		/* vcn dpm on is a prerequisite for vcn power gate messages */
1156 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1157 			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL);
1158 			if (ret)
1159 				return ret;
1160 		}
1161 	} else {
1162 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1163 			ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
1164 			if (ret)
1165 				return ret;
1166 		}
1167 	}
1168 
1169 	return ret;
1170 }
1171 
1172 static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
1173 {
1174 	int ret = 0;
1175 
1176 	if (enable) {
1177 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
1178 			ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerUpJpeg, NULL);
1179 			if (ret)
1180 				return ret;
1181 		}
1182 	} else {
1183 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
1184 			ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL);
1185 			if (ret)
1186 				return ret;
1187 		}
1188 	}
1189 
1190 	return ret;
1191 }
1192 
1193 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
1194 				       enum smu_clk_type clk_type,
1195 				       uint32_t *value)
1196 {
1197 	MetricsMember_t member_type;
1198 	int clk_id = 0;
1199 
1200 	clk_id = smu_cmn_to_asic_specific_index(smu,
1201 						CMN2ASIC_MAPPING_CLK,
1202 						clk_type);
1203 	if (clk_id < 0)
1204 		return clk_id;
1205 
1206 	switch (clk_id) {
1207 	case PPCLK_GFXCLK:
1208 		member_type = METRICS_CURR_GFXCLK;
1209 		break;
1210 	case PPCLK_UCLK:
1211 		member_type = METRICS_CURR_UCLK;
1212 		break;
1213 	case PPCLK_SOCCLK:
1214 		member_type = METRICS_CURR_SOCCLK;
1215 		break;
1216 	case PPCLK_VCLK:
1217 		member_type = METRICS_CURR_VCLK;
1218 		break;
1219 	case PPCLK_DCLK:
1220 		member_type = METRICS_CURR_DCLK;
1221 		break;
1222 	case PPCLK_DCEFCLK:
1223 		member_type = METRICS_CURR_DCEFCLK;
1224 		break;
1225 	default:
1226 		return -EINVAL;
1227 	}
1228 
1229 	return navi1x_get_smu_metrics_data(smu,
1230 					   member_type,
1231 					   value);
1232 }
1233 
1234 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1235 {
1236 	PPTable_t *pptable = smu->smu_table.driver_pptable;
1237 	DpmDescriptor_t *dpm_desc = NULL;
1238 	uint32_t clk_index = 0;
1239 
1240 	clk_index = smu_cmn_to_asic_specific_index(smu,
1241 						   CMN2ASIC_MAPPING_CLK,
1242 						   clk_type);
1243 	dpm_desc = &pptable->DpmDescriptor[clk_index];
1244 
1245 	/* 0 - Fine grained DPM, 1 - Discrete DPM */
1246 	return dpm_desc->SnapToDiscrete == 0;
1247 }
1248 
1249 static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap)
1250 {
1251 	return od_table->cap[cap];
1252 }
1253 
1254 static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table,
1255 					enum SMU_11_0_ODSETTING_ID setting,
1256 					uint32_t *min, uint32_t *max)
1257 {
1258 	if (min)
1259 		*min = od_table->min[setting];
1260 	if (max)
1261 		*max = od_table->max[setting];
1262 }
1263 
1264 static int navi10_print_clk_levels(struct smu_context *smu,
1265 			enum smu_clk_type clk_type, char *buf)
1266 {
1267 	uint16_t *curve_settings;
1268 	int i, size = 0, ret = 0;
1269 	uint32_t cur_value = 0, value = 0, count = 0;
1270 	uint32_t freq_values[3] = {0};
1271 	uint32_t mark_index = 0;
1272 	struct smu_table_context *table_context = &smu->smu_table;
1273 	uint32_t gen_speed, lane_width;
1274 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1275 	struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1276 	PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
1277 	OverDriveTable_t *od_table =
1278 		(OverDriveTable_t *)table_context->overdrive_table;
1279 	struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
1280 	uint32_t min_value, max_value;
1281 
1282 	switch (clk_type) {
1283 	case SMU_GFXCLK:
1284 	case SMU_SCLK:
1285 	case SMU_SOCCLK:
1286 	case SMU_MCLK:
1287 	case SMU_UCLK:
1288 	case SMU_FCLK:
1289 	case SMU_VCLK:
1290 	case SMU_DCLK:
1291 	case SMU_DCEFCLK:
1292 		ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1293 		if (ret)
1294 			return size;
1295 
1296 		ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1297 		if (ret)
1298 			return size;
1299 
1300 		if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
1301 			for (i = 0; i < count; i++) {
1302 				ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
1303 				if (ret)
1304 					return size;
1305 
1306 				size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
1307 						cur_value == value ? "*" : "");
1308 			}
1309 		} else {
1310 			ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
1311 			if (ret)
1312 				return size;
1313 			ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
1314 			if (ret)
1315 				return size;
1316 
1317 			freq_values[1] = cur_value;
1318 			mark_index = cur_value == freq_values[0] ? 0 :
1319 				     cur_value == freq_values[2] ? 2 : 1;
1320 			if (mark_index != 1)
1321 				freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
1322 
1323 			for (i = 0; i < 3; i++) {
1324 				size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
1325 						i == mark_index ? "*" : "");
1326 			}
1327 
1328 		}
1329 		break;
1330 	case SMU_PCIE:
1331 		gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1332 		lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1333 		for (i = 0; i < NUM_LINK_LEVELS; i++)
1334 			size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
1335 					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1336 					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1337 					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1338 					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1339 					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1340 					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1341 					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1342 					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1343 					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1344 					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1345 					pptable->LclkFreq[i],
1346 					(gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1347 					(lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1348 					"*" : "");
1349 		break;
1350 	case SMU_OD_SCLK:
1351 		if (!smu->od_enabled || !od_table || !od_settings)
1352 			break;
1353 		if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS))
1354 			break;
1355 		size += sprintf(buf + size, "OD_SCLK:\n");
1356 		size += sprintf(buf + size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1357 		break;
1358 	case SMU_OD_MCLK:
1359 		if (!smu->od_enabled || !od_table || !od_settings)
1360 			break;
1361 		if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX))
1362 			break;
1363 		size += sprintf(buf + size, "OD_MCLK:\n");
1364 		size += sprintf(buf + size, "1: %uMHz\n", od_table->UclkFmax);
1365 		break;
1366 	case SMU_OD_VDDC_CURVE:
1367 		if (!smu->od_enabled || !od_table || !od_settings)
1368 			break;
1369 		if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE))
1370 			break;
1371 		size += sprintf(buf + size, "OD_VDDC_CURVE:\n");
1372 		for (i = 0; i < 3; i++) {
1373 			switch (i) {
1374 			case 0:
1375 				curve_settings = &od_table->GfxclkFreq1;
1376 				break;
1377 			case 1:
1378 				curve_settings = &od_table->GfxclkFreq2;
1379 				break;
1380 			case 2:
1381 				curve_settings = &od_table->GfxclkFreq3;
1382 				break;
1383 			default:
1384 				break;
1385 			}
1386 			size += sprintf(buf + size, "%d: %uMHz %umV\n", i, curve_settings[0], curve_settings[1] / NAVI10_VOLTAGE_SCALE);
1387 		}
1388 		break;
1389 	case SMU_OD_RANGE:
1390 		if (!smu->od_enabled || !od_table || !od_settings)
1391 			break;
1392 		size = sprintf(buf, "%s:\n", "OD_RANGE");
1393 
1394 		if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
1395 			navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN,
1396 						    &min_value, NULL);
1397 			navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX,
1398 						    NULL, &max_value);
1399 			size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
1400 					min_value, max_value);
1401 		}
1402 
1403 		if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
1404 			navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX,
1405 						    &min_value, &max_value);
1406 			size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
1407 					min_value, max_value);
1408 		}
1409 
1410 		if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
1411 			navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1,
1412 						    &min_value, &max_value);
1413 			size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
1414 					min_value, max_value);
1415 			navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1,
1416 						    &min_value, &max_value);
1417 			size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
1418 					min_value, max_value);
1419 			navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2,
1420 						    &min_value, &max_value);
1421 			size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
1422 					min_value, max_value);
1423 			navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2,
1424 						    &min_value, &max_value);
1425 			size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
1426 					min_value, max_value);
1427 			navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3,
1428 						    &min_value, &max_value);
1429 			size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
1430 					min_value, max_value);
1431 			navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3,
1432 						    &min_value, &max_value);
1433 			size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
1434 					min_value, max_value);
1435 		}
1436 
1437 		break;
1438 	default:
1439 		break;
1440 	}
1441 
1442 	return size;
1443 }
1444 
1445 static int navi10_force_clk_levels(struct smu_context *smu,
1446 				   enum smu_clk_type clk_type, uint32_t mask)
1447 {
1448 
1449 	int ret = 0, size = 0;
1450 	uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1451 
1452 	soft_min_level = mask ? (ffs(mask) - 1) : 0;
1453 	soft_max_level = mask ? (fls(mask) - 1) : 0;
1454 
1455 	switch (clk_type) {
1456 	case SMU_GFXCLK:
1457 	case SMU_SCLK:
1458 	case SMU_SOCCLK:
1459 	case SMU_MCLK:
1460 	case SMU_UCLK:
1461 	case SMU_FCLK:
1462 		/* There is only 2 levels for fine grained DPM */
1463 		if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
1464 			soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1465 			soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1466 		}
1467 
1468 		ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1469 		if (ret)
1470 			return size;
1471 
1472 		ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1473 		if (ret)
1474 			return size;
1475 
1476 		ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1477 		if (ret)
1478 			return size;
1479 		break;
1480 	case SMU_DCEFCLK:
1481 		dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1482 		break;
1483 
1484 	default:
1485 		break;
1486 	}
1487 
1488 	return size;
1489 }
1490 
1491 static int navi10_populate_umd_state_clk(struct smu_context *smu)
1492 {
1493 	struct smu_11_0_dpm_context *dpm_context =
1494 				smu->smu_dpm.dpm_context;
1495 	struct smu_11_0_dpm_table *gfx_table =
1496 				&dpm_context->dpm_tables.gfx_table;
1497 	struct smu_11_0_dpm_table *mem_table =
1498 				&dpm_context->dpm_tables.uclk_table;
1499 	struct smu_11_0_dpm_table *soc_table =
1500 				&dpm_context->dpm_tables.soc_table;
1501 	struct smu_umd_pstate_table *pstate_table =
1502 				&smu->pstate_table;
1503 	struct amdgpu_device *adev = smu->adev;
1504 	uint32_t sclk_freq;
1505 
1506 	pstate_table->gfxclk_pstate.min = gfx_table->min;
1507 	switch (adev->asic_type) {
1508 	case CHIP_NAVI10:
1509 		switch (adev->pdev->revision) {
1510 		case 0xf0: /* XTX */
1511 		case 0xc0:
1512 			sclk_freq = NAVI10_PEAK_SCLK_XTX;
1513 			break;
1514 		case 0xf1: /* XT */
1515 		case 0xc1:
1516 			sclk_freq = NAVI10_PEAK_SCLK_XT;
1517 			break;
1518 		default: /* XL */
1519 			sclk_freq = NAVI10_PEAK_SCLK_XL;
1520 			break;
1521 		}
1522 		break;
1523 	case CHIP_NAVI14:
1524 		switch (adev->pdev->revision) {
1525 		case 0xc7: /* XT */
1526 		case 0xf4:
1527 			sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;
1528 			break;
1529 		case 0xc1: /* XTM */
1530 		case 0xf2:
1531 			sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;
1532 			break;
1533 		case 0xc3: /* XLM */
1534 		case 0xf3:
1535 			sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1536 			break;
1537 		case 0xc5: /* XTX */
1538 		case 0xf6:
1539 			sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1540 			break;
1541 		default: /* XL */
1542 			sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;
1543 			break;
1544 		}
1545 		break;
1546 	case CHIP_NAVI12:
1547 		sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK;
1548 		break;
1549 	default:
1550 		sclk_freq = gfx_table->dpm_levels[gfx_table->count - 1].value;
1551 		break;
1552 	}
1553 	pstate_table->gfxclk_pstate.peak = sclk_freq;
1554 
1555 	pstate_table->uclk_pstate.min = mem_table->min;
1556 	pstate_table->uclk_pstate.peak = mem_table->max;
1557 
1558 	pstate_table->socclk_pstate.min = soc_table->min;
1559 	pstate_table->socclk_pstate.peak = soc_table->max;
1560 
1561 	if (gfx_table->max > NAVI10_UMD_PSTATE_PROFILING_GFXCLK &&
1562 	    mem_table->max > NAVI10_UMD_PSTATE_PROFILING_MEMCLK &&
1563 	    soc_table->max > NAVI10_UMD_PSTATE_PROFILING_SOCCLK) {
1564 		pstate_table->gfxclk_pstate.standard =
1565 			NAVI10_UMD_PSTATE_PROFILING_GFXCLK;
1566 		pstate_table->uclk_pstate.standard =
1567 			NAVI10_UMD_PSTATE_PROFILING_MEMCLK;
1568 		pstate_table->socclk_pstate.standard =
1569 			NAVI10_UMD_PSTATE_PROFILING_SOCCLK;
1570 	} else {
1571 		pstate_table->gfxclk_pstate.standard =
1572 			pstate_table->gfxclk_pstate.min;
1573 		pstate_table->uclk_pstate.standard =
1574 			pstate_table->uclk_pstate.min;
1575 		pstate_table->socclk_pstate.standard =
1576 			pstate_table->socclk_pstate.min;
1577 	}
1578 
1579 	return 0;
1580 }
1581 
1582 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
1583 						 enum smu_clk_type clk_type,
1584 						 struct pp_clock_levels_with_latency *clocks)
1585 {
1586 	int ret = 0, i = 0;
1587 	uint32_t level_count = 0, freq = 0;
1588 
1589 	switch (clk_type) {
1590 	case SMU_GFXCLK:
1591 	case SMU_DCEFCLK:
1592 	case SMU_SOCCLK:
1593 	case SMU_MCLK:
1594 	case SMU_UCLK:
1595 		ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &level_count);
1596 		if (ret)
1597 			return ret;
1598 
1599 		level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
1600 		clocks->num_levels = level_count;
1601 
1602 		for (i = 0; i < level_count; i++) {
1603 			ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &freq);
1604 			if (ret)
1605 				return ret;
1606 
1607 			clocks->data[i].clocks_in_khz = freq * 1000;
1608 			clocks->data[i].latency_in_us = 0;
1609 		}
1610 		break;
1611 	default:
1612 		break;
1613 	}
1614 
1615 	return ret;
1616 }
1617 
1618 static int navi10_pre_display_config_changed(struct smu_context *smu)
1619 {
1620 	int ret = 0;
1621 	uint32_t max_freq = 0;
1622 
1623 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1624 	if (ret)
1625 		return ret;
1626 
1627 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1628 		ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1629 		if (ret)
1630 			return ret;
1631 		ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1632 		if (ret)
1633 			return ret;
1634 	}
1635 
1636 	return ret;
1637 }
1638 
1639 static int navi10_display_config_changed(struct smu_context *smu)
1640 {
1641 	int ret = 0;
1642 
1643 	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1644 	    smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1645 	    smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1646 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1647 						  smu->display_config->num_display,
1648 						  NULL);
1649 		if (ret)
1650 			return ret;
1651 	}
1652 
1653 	return ret;
1654 }
1655 
1656 static bool navi10_is_dpm_running(struct smu_context *smu)
1657 {
1658 	int ret = 0;
1659 	uint32_t feature_mask[2];
1660 	uint64_t feature_enabled;
1661 
1662 	ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1663 	if (ret)
1664 		return false;
1665 
1666 	feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1667 
1668 	return !!(feature_enabled & SMC_DPM_FEATURE);
1669 }
1670 
1671 static int navi10_get_fan_speed_percent(struct smu_context *smu,
1672 					uint32_t *speed)
1673 {
1674 	int ret;
1675 	u32 rpm;
1676 
1677 	if (!speed)
1678 		return -EINVAL;
1679 
1680 	switch (smu_v11_0_get_fan_control_mode(smu)) {
1681 	case AMD_FAN_CTRL_AUTO:
1682 		ret = navi1x_get_smu_metrics_data(smu,
1683 						  METRICS_CURR_FANSPEED,
1684 						  &rpm);
1685 		if (!ret && smu->fan_max_rpm)
1686 			*speed = rpm * 100 / smu->fan_max_rpm;
1687 		return ret;
1688 	default:
1689 		*speed = smu->user_dpm_profile.fan_speed_percent;
1690 		return 0;
1691 	}
1692 }
1693 
1694 static int navi10_get_fan_parameters(struct smu_context *smu)
1695 {
1696 	PPTable_t *pptable = smu->smu_table.driver_pptable;
1697 
1698 	smu->fan_max_rpm = pptable->FanMaximumRpm;
1699 
1700 	return 0;
1701 }
1702 
1703 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
1704 {
1705 	DpmActivityMonitorCoeffInt_t activity_monitor;
1706 	uint32_t i, size = 0;
1707 	int16_t workload_type = 0;
1708 	static const char *profile_name[] = {
1709 					"BOOTUP_DEFAULT",
1710 					"3D_FULL_SCREEN",
1711 					"POWER_SAVING",
1712 					"VIDEO",
1713 					"VR",
1714 					"COMPUTE",
1715 					"CUSTOM"};
1716 	static const char *title[] = {
1717 			"PROFILE_INDEX(NAME)",
1718 			"CLOCK_TYPE(NAME)",
1719 			"FPS",
1720 			"MinFreqType",
1721 			"MinActiveFreqType",
1722 			"MinActiveFreq",
1723 			"BoosterFreqType",
1724 			"BoosterFreq",
1725 			"PD_Data_limit_c",
1726 			"PD_Data_error_coeff",
1727 			"PD_Data_error_rate_coeff"};
1728 	int result = 0;
1729 
1730 	if (!buf)
1731 		return -EINVAL;
1732 
1733 	size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1734 			title[0], title[1], title[2], title[3], title[4], title[5],
1735 			title[6], title[7], title[8], title[9], title[10]);
1736 
1737 	for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1738 		/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1739 		workload_type = smu_cmn_to_asic_specific_index(smu,
1740 							       CMN2ASIC_MAPPING_WORKLOAD,
1741 							       i);
1742 		if (workload_type < 0)
1743 			return -EINVAL;
1744 
1745 		result = smu_cmn_update_table(smu,
1746 					  SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1747 					  (void *)(&activity_monitor), false);
1748 		if (result) {
1749 			dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1750 			return result;
1751 		}
1752 
1753 		size += sprintf(buf + size, "%2d %14s%s:\n",
1754 			i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1755 
1756 		size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1757 			" ",
1758 			0,
1759 			"GFXCLK",
1760 			activity_monitor.Gfx_FPS,
1761 			activity_monitor.Gfx_MinFreqStep,
1762 			activity_monitor.Gfx_MinActiveFreqType,
1763 			activity_monitor.Gfx_MinActiveFreq,
1764 			activity_monitor.Gfx_BoosterFreqType,
1765 			activity_monitor.Gfx_BoosterFreq,
1766 			activity_monitor.Gfx_PD_Data_limit_c,
1767 			activity_monitor.Gfx_PD_Data_error_coeff,
1768 			activity_monitor.Gfx_PD_Data_error_rate_coeff);
1769 
1770 		size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1771 			" ",
1772 			1,
1773 			"SOCCLK",
1774 			activity_monitor.Soc_FPS,
1775 			activity_monitor.Soc_MinFreqStep,
1776 			activity_monitor.Soc_MinActiveFreqType,
1777 			activity_monitor.Soc_MinActiveFreq,
1778 			activity_monitor.Soc_BoosterFreqType,
1779 			activity_monitor.Soc_BoosterFreq,
1780 			activity_monitor.Soc_PD_Data_limit_c,
1781 			activity_monitor.Soc_PD_Data_error_coeff,
1782 			activity_monitor.Soc_PD_Data_error_rate_coeff);
1783 
1784 		size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1785 			" ",
1786 			2,
1787 			"MEMLK",
1788 			activity_monitor.Mem_FPS,
1789 			activity_monitor.Mem_MinFreqStep,
1790 			activity_monitor.Mem_MinActiveFreqType,
1791 			activity_monitor.Mem_MinActiveFreq,
1792 			activity_monitor.Mem_BoosterFreqType,
1793 			activity_monitor.Mem_BoosterFreq,
1794 			activity_monitor.Mem_PD_Data_limit_c,
1795 			activity_monitor.Mem_PD_Data_error_coeff,
1796 			activity_monitor.Mem_PD_Data_error_rate_coeff);
1797 	}
1798 
1799 	return size;
1800 }
1801 
1802 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1803 {
1804 	DpmActivityMonitorCoeffInt_t activity_monitor;
1805 	int workload_type, ret = 0;
1806 
1807 	smu->power_profile_mode = input[size];
1808 
1809 	if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1810 		dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1811 		return -EINVAL;
1812 	}
1813 
1814 	if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1815 
1816 		ret = smu_cmn_update_table(smu,
1817 				       SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1818 				       (void *)(&activity_monitor), false);
1819 		if (ret) {
1820 			dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1821 			return ret;
1822 		}
1823 
1824 		switch (input[0]) {
1825 		case 0: /* Gfxclk */
1826 			activity_monitor.Gfx_FPS = input[1];
1827 			activity_monitor.Gfx_MinFreqStep = input[2];
1828 			activity_monitor.Gfx_MinActiveFreqType = input[3];
1829 			activity_monitor.Gfx_MinActiveFreq = input[4];
1830 			activity_monitor.Gfx_BoosterFreqType = input[5];
1831 			activity_monitor.Gfx_BoosterFreq = input[6];
1832 			activity_monitor.Gfx_PD_Data_limit_c = input[7];
1833 			activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1834 			activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1835 			break;
1836 		case 1: /* Socclk */
1837 			activity_monitor.Soc_FPS = input[1];
1838 			activity_monitor.Soc_MinFreqStep = input[2];
1839 			activity_monitor.Soc_MinActiveFreqType = input[3];
1840 			activity_monitor.Soc_MinActiveFreq = input[4];
1841 			activity_monitor.Soc_BoosterFreqType = input[5];
1842 			activity_monitor.Soc_BoosterFreq = input[6];
1843 			activity_monitor.Soc_PD_Data_limit_c = input[7];
1844 			activity_monitor.Soc_PD_Data_error_coeff = input[8];
1845 			activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1846 			break;
1847 		case 2: /* Memlk */
1848 			activity_monitor.Mem_FPS = input[1];
1849 			activity_monitor.Mem_MinFreqStep = input[2];
1850 			activity_monitor.Mem_MinActiveFreqType = input[3];
1851 			activity_monitor.Mem_MinActiveFreq = input[4];
1852 			activity_monitor.Mem_BoosterFreqType = input[5];
1853 			activity_monitor.Mem_BoosterFreq = input[6];
1854 			activity_monitor.Mem_PD_Data_limit_c = input[7];
1855 			activity_monitor.Mem_PD_Data_error_coeff = input[8];
1856 			activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1857 			break;
1858 		}
1859 
1860 		ret = smu_cmn_update_table(smu,
1861 				       SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1862 				       (void *)(&activity_monitor), true);
1863 		if (ret) {
1864 			dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1865 			return ret;
1866 		}
1867 	}
1868 
1869 	/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1870 	workload_type = smu_cmn_to_asic_specific_index(smu,
1871 						       CMN2ASIC_MAPPING_WORKLOAD,
1872 						       smu->power_profile_mode);
1873 	if (workload_type < 0)
1874 		return -EINVAL;
1875 	smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1876 				    1 << workload_type, NULL);
1877 
1878 	return ret;
1879 }
1880 
1881 static int navi10_notify_smc_display_config(struct smu_context *smu)
1882 {
1883 	struct smu_clocks min_clocks = {0};
1884 	struct pp_display_clock_request clock_req;
1885 	int ret = 0;
1886 
1887 	min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1888 	min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1889 	min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1890 
1891 	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1892 		clock_req.clock_type = amd_pp_dcef_clock;
1893 		clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1894 
1895 		ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1896 		if (!ret) {
1897 			if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1898 				ret = smu_cmn_send_smc_msg_with_param(smu,
1899 								  SMU_MSG_SetMinDeepSleepDcefclk,
1900 								  min_clocks.dcef_clock_in_sr/100,
1901 								  NULL);
1902 				if (ret) {
1903 					dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1904 					return ret;
1905 				}
1906 			}
1907 		} else {
1908 			dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1909 		}
1910 	}
1911 
1912 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1913 		ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1914 		if (ret) {
1915 			dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1916 			return ret;
1917 		}
1918 	}
1919 
1920 	return 0;
1921 }
1922 
1923 static int navi10_set_watermarks_table(struct smu_context *smu,
1924 				       struct pp_smu_wm_range_sets *clock_ranges)
1925 {
1926 	Watermarks_t *table = smu->smu_table.watermarks_table;
1927 	int ret = 0;
1928 	int i;
1929 
1930 	if (clock_ranges) {
1931 		if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1932 		    clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1933 			return -EINVAL;
1934 
1935 		for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1936 			table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1937 				clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1938 			table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1939 				clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1940 			table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1941 				clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1942 			table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1943 				clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1944 
1945 			table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1946 				clock_ranges->reader_wm_sets[i].wm_inst;
1947 		}
1948 
1949 		for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1950 			table->WatermarkRow[WM_SOCCLK][i].MinClock =
1951 				clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1952 			table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1953 				clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1954 			table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1955 				clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1956 			table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1957 				clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1958 
1959 			table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1960 				clock_ranges->writer_wm_sets[i].wm_inst;
1961 		}
1962 
1963 		smu->watermarks_bitmap |= WATERMARKS_EXIST;
1964 	}
1965 
1966 	/* pass data to smu controller */
1967 	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1968 	     !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1969 		ret = smu_cmn_write_watermarks_table(smu);
1970 		if (ret) {
1971 			dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1972 			return ret;
1973 		}
1974 		smu->watermarks_bitmap |= WATERMARKS_LOADED;
1975 	}
1976 
1977 	return 0;
1978 }
1979 
1980 static int navi10_read_sensor(struct smu_context *smu,
1981 				 enum amd_pp_sensors sensor,
1982 				 void *data, uint32_t *size)
1983 {
1984 	int ret = 0;
1985 	struct smu_table_context *table_context = &smu->smu_table;
1986 	PPTable_t *pptable = table_context->driver_pptable;
1987 
1988 	if(!data || !size)
1989 		return -EINVAL;
1990 
1991 	mutex_lock(&smu->sensor_lock);
1992 	switch (sensor) {
1993 	case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1994 		*(uint32_t *)data = pptable->FanMaximumRpm;
1995 		*size = 4;
1996 		break;
1997 	case AMDGPU_PP_SENSOR_MEM_LOAD:
1998 		ret = navi1x_get_smu_metrics_data(smu,
1999 						  METRICS_AVERAGE_MEMACTIVITY,
2000 						  (uint32_t *)data);
2001 		*size = 4;
2002 		break;
2003 	case AMDGPU_PP_SENSOR_GPU_LOAD:
2004 		ret = navi1x_get_smu_metrics_data(smu,
2005 						  METRICS_AVERAGE_GFXACTIVITY,
2006 						  (uint32_t *)data);
2007 		*size = 4;
2008 		break;
2009 	case AMDGPU_PP_SENSOR_GPU_POWER:
2010 		ret = navi1x_get_smu_metrics_data(smu,
2011 						  METRICS_AVERAGE_SOCKETPOWER,
2012 						  (uint32_t *)data);
2013 		*size = 4;
2014 		break;
2015 	case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
2016 		ret = navi1x_get_smu_metrics_data(smu,
2017 						  METRICS_TEMPERATURE_HOTSPOT,
2018 						  (uint32_t *)data);
2019 		*size = 4;
2020 		break;
2021 	case AMDGPU_PP_SENSOR_EDGE_TEMP:
2022 		ret = navi1x_get_smu_metrics_data(smu,
2023 						  METRICS_TEMPERATURE_EDGE,
2024 						  (uint32_t *)data);
2025 		*size = 4;
2026 		break;
2027 	case AMDGPU_PP_SENSOR_MEM_TEMP:
2028 		ret = navi1x_get_smu_metrics_data(smu,
2029 						  METRICS_TEMPERATURE_MEM,
2030 						  (uint32_t *)data);
2031 		*size = 4;
2032 		break;
2033 	case AMDGPU_PP_SENSOR_GFX_MCLK:
2034 		ret = navi10_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
2035 		*(uint32_t *)data *= 100;
2036 		*size = 4;
2037 		break;
2038 	case AMDGPU_PP_SENSOR_GFX_SCLK:
2039 		ret = navi1x_get_smu_metrics_data(smu, METRICS_AVERAGE_GFXCLK, (uint32_t *)data);
2040 		*(uint32_t *)data *= 100;
2041 		*size = 4;
2042 		break;
2043 	case AMDGPU_PP_SENSOR_VDDGFX:
2044 		ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
2045 		*size = 4;
2046 		break;
2047 	default:
2048 		ret = -EOPNOTSUPP;
2049 		break;
2050 	}
2051 	mutex_unlock(&smu->sensor_lock);
2052 
2053 	return ret;
2054 }
2055 
2056 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
2057 {
2058 	uint32_t num_discrete_levels = 0;
2059 	uint16_t *dpm_levels = NULL;
2060 	uint16_t i = 0;
2061 	struct smu_table_context *table_context = &smu->smu_table;
2062 	PPTable_t *driver_ppt = NULL;
2063 
2064 	if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
2065 		return -EINVAL;
2066 
2067 	driver_ppt = table_context->driver_pptable;
2068 	num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
2069 	dpm_levels = driver_ppt->FreqTableUclk;
2070 
2071 	if (num_discrete_levels == 0 || dpm_levels == NULL)
2072 		return -EINVAL;
2073 
2074 	*num_states = num_discrete_levels;
2075 	for (i = 0; i < num_discrete_levels; i++) {
2076 		/* convert to khz */
2077 		*clocks_in_khz = (*dpm_levels) * 1000;
2078 		clocks_in_khz++;
2079 		dpm_levels++;
2080 	}
2081 
2082 	return 0;
2083 }
2084 
2085 static int navi10_get_thermal_temperature_range(struct smu_context *smu,
2086 						struct smu_temperature_range *range)
2087 {
2088 	struct smu_table_context *table_context = &smu->smu_table;
2089 	struct smu_11_0_powerplay_table *powerplay_table =
2090 				table_context->power_play_table;
2091 	PPTable_t *pptable = smu->smu_table.driver_pptable;
2092 
2093 	if (!range)
2094 		return -EINVAL;
2095 
2096 	memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
2097 
2098 	range->max = pptable->TedgeLimit *
2099 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2100 	range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
2101 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2102 	range->hotspot_crit_max = pptable->ThotspotLimit *
2103 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2104 	range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
2105 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2106 	range->mem_crit_max = pptable->TmemLimit *
2107 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2108 	range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
2109 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2110 	range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2111 
2112 	return 0;
2113 }
2114 
2115 static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
2116 						bool disable_memory_clock_switch)
2117 {
2118 	int ret = 0;
2119 	struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
2120 		(struct smu_11_0_max_sustainable_clocks *)
2121 			smu->smu_table.max_sustainable_clocks;
2122 	uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
2123 	uint32_t max_memory_clock = max_sustainable_clocks->uclock;
2124 
2125 	if(smu->disable_uclk_switch == disable_memory_clock_switch)
2126 		return 0;
2127 
2128 	if(disable_memory_clock_switch)
2129 		ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
2130 	else
2131 		ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
2132 
2133 	if(!ret)
2134 		smu->disable_uclk_switch = disable_memory_clock_switch;
2135 
2136 	return ret;
2137 }
2138 
2139 static int navi10_get_power_limit(struct smu_context *smu,
2140 				  uint32_t *current_power_limit,
2141 				  uint32_t *default_power_limit,
2142 				  uint32_t *max_power_limit)
2143 {
2144 	struct smu_11_0_powerplay_table *powerplay_table =
2145 		(struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
2146 	struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
2147 	PPTable_t *pptable = smu->smu_table.driver_pptable;
2148 	uint32_t power_limit, od_percent;
2149 
2150 	if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
2151 		/* the last hope to figure out the ppt limit */
2152 		if (!pptable) {
2153 			dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
2154 			return -EINVAL;
2155 		}
2156 		power_limit =
2157 			pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
2158 	}
2159 
2160 	if (current_power_limit)
2161 		*current_power_limit = power_limit;
2162 	if (default_power_limit)
2163 		*default_power_limit = power_limit;
2164 
2165 	if (max_power_limit) {
2166 		if (smu->od_enabled &&
2167 		    navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) {
2168 			od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
2169 
2170 			dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
2171 
2172 			power_limit *= (100 + od_percent);
2173 			power_limit /= 100;
2174 		}
2175 
2176 		*max_power_limit = power_limit;
2177 	}
2178 
2179 	return 0;
2180 }
2181 
2182 static int navi10_update_pcie_parameters(struct smu_context *smu,
2183 				     uint32_t pcie_gen_cap,
2184 				     uint32_t pcie_width_cap)
2185 {
2186 	struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2187 	PPTable_t *pptable = smu->smu_table.driver_pptable;
2188 	uint32_t smu_pcie_arg;
2189 	int ret, i;
2190 
2191 	/* lclk dpm table setup */
2192 	for (i = 0; i < MAX_PCIE_CONF; i++) {
2193 		dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i];
2194 		dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i];
2195 	}
2196 
2197 	for (i = 0; i < NUM_LINK_LEVELS; i++) {
2198 		smu_pcie_arg = (i << 16) |
2199 			((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
2200 				(pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
2201 					pptable->PcieLaneCount[i] : pcie_width_cap);
2202 		ret = smu_cmn_send_smc_msg_with_param(smu,
2203 					  SMU_MSG_OverridePcieParameters,
2204 					  smu_pcie_arg,
2205 					  NULL);
2206 
2207 		if (ret)
2208 			return ret;
2209 
2210 		if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
2211 			dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
2212 		if (pptable->PcieLaneCount[i] > pcie_width_cap)
2213 			dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
2214 	}
2215 
2216 	return 0;
2217 }
2218 
2219 static inline void navi10_dump_od_table(struct smu_context *smu,
2220 					OverDriveTable_t *od_table)
2221 {
2222 	dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
2223 	dev_dbg(smu->adev->dev, "OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1);
2224 	dev_dbg(smu->adev->dev, "OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2);
2225 	dev_dbg(smu->adev->dev, "OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3);
2226 	dev_dbg(smu->adev->dev, "OD: UclkFmax: %d\n", od_table->UclkFmax);
2227 	dev_dbg(smu->adev->dev, "OD: OverDrivePct: %d\n", od_table->OverDrivePct);
2228 }
2229 
2230 static int navi10_od_setting_check_range(struct smu_context *smu,
2231 					 struct smu_11_0_overdrive_table *od_table,
2232 					 enum SMU_11_0_ODSETTING_ID setting,
2233 					 uint32_t value)
2234 {
2235 	if (value < od_table->min[setting]) {
2236 		dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]);
2237 		return -EINVAL;
2238 	}
2239 	if (value > od_table->max[setting]) {
2240 		dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]);
2241 		return -EINVAL;
2242 	}
2243 	return 0;
2244 }
2245 
2246 static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
2247 						     uint16_t *voltage,
2248 						     uint32_t freq)
2249 {
2250 	uint32_t param = (freq & 0xFFFF) | (PPCLK_GFXCLK << 16);
2251 	uint32_t value = 0;
2252 	int ret;
2253 
2254 	ret = smu_cmn_send_smc_msg_with_param(smu,
2255 					  SMU_MSG_GetVoltageByDpm,
2256 					  param,
2257 					  &value);
2258 	if (ret) {
2259 		dev_err(smu->adev->dev, "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
2260 		return ret;
2261 	}
2262 
2263 	*voltage = (uint16_t)value;
2264 
2265 	return 0;
2266 }
2267 
2268 static int navi10_baco_enter(struct smu_context *smu)
2269 {
2270 	struct amdgpu_device *adev = smu->adev;
2271 
2272 	if (adev->in_runpm)
2273 		return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2274 	else
2275 		return smu_v11_0_baco_enter(smu);
2276 }
2277 
2278 static int navi10_baco_exit(struct smu_context *smu)
2279 {
2280 	struct amdgpu_device *adev = smu->adev;
2281 
2282 	if (adev->in_runpm) {
2283 		/* Wait for PMFW handling for the Dstate change */
2284 		msleep(10);
2285 		return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2286 	} else {
2287 		return smu_v11_0_baco_exit(smu);
2288 	}
2289 }
2290 
2291 static int navi10_set_default_od_settings(struct smu_context *smu)
2292 {
2293 	OverDriveTable_t *od_table =
2294 		(OverDriveTable_t *)smu->smu_table.overdrive_table;
2295 	OverDriveTable_t *boot_od_table =
2296 		(OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
2297 	int ret = 0;
2298 
2299 	ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, false);
2300 	if (ret) {
2301 		dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2302 		return ret;
2303 	}
2304 
2305 	if (!od_table->GfxclkVolt1) {
2306 		ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2307 								&od_table->GfxclkVolt1,
2308 								od_table->GfxclkFreq1);
2309 		if (ret)
2310 			return ret;
2311 	}
2312 
2313 	if (!od_table->GfxclkVolt2) {
2314 		ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2315 								&od_table->GfxclkVolt2,
2316 								od_table->GfxclkFreq2);
2317 		if (ret)
2318 			return ret;
2319 	}
2320 
2321 	if (!od_table->GfxclkVolt3) {
2322 		ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2323 								&od_table->GfxclkVolt3,
2324 								od_table->GfxclkFreq3);
2325 		if (ret)
2326 			return ret;
2327 	}
2328 
2329 	memcpy(boot_od_table, od_table, sizeof(OverDriveTable_t));
2330 
2331 	navi10_dump_od_table(smu, od_table);
2332 
2333 	return 0;
2334 }
2335 
2336 static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) {
2337 	int i;
2338 	int ret = 0;
2339 	struct smu_table_context *table_context = &smu->smu_table;
2340 	OverDriveTable_t *od_table;
2341 	struct smu_11_0_overdrive_table *od_settings;
2342 	enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting;
2343 	uint16_t *freq_ptr, *voltage_ptr;
2344 	od_table = (OverDriveTable_t *)table_context->overdrive_table;
2345 
2346 	if (!smu->od_enabled) {
2347 		dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2348 		return -EINVAL;
2349 	}
2350 
2351 	if (!smu->od_settings) {
2352 		dev_err(smu->adev->dev, "OD board limits are not set!\n");
2353 		return -ENOENT;
2354 	}
2355 
2356 	od_settings = smu->od_settings;
2357 
2358 	switch (type) {
2359 	case PP_OD_EDIT_SCLK_VDDC_TABLE:
2360 		if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
2361 			dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2362 			return -ENOTSUPP;
2363 		}
2364 		if (!table_context->overdrive_table) {
2365 			dev_err(smu->adev->dev, "Overdrive is not initialized\n");
2366 			return -EINVAL;
2367 		}
2368 		for (i = 0; i < size; i += 2) {
2369 			if (i + 2 > size) {
2370 				dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2371 				return -EINVAL;
2372 			}
2373 			switch (input[i]) {
2374 			case 0:
2375 				freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN;
2376 				freq_ptr = &od_table->GfxclkFmin;
2377 				if (input[i + 1] > od_table->GfxclkFmax) {
2378 					dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2379 						input[i + 1],
2380 						od_table->GfxclkFmin);
2381 					return -EINVAL;
2382 				}
2383 				break;
2384 			case 1:
2385 				freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX;
2386 				freq_ptr = &od_table->GfxclkFmax;
2387 				if (input[i + 1] < od_table->GfxclkFmin) {
2388 					dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2389 						input[i + 1],
2390 						od_table->GfxclkFmax);
2391 					return -EINVAL;
2392 				}
2393 				break;
2394 			default:
2395 				dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2396 				dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2397 				return -EINVAL;
2398 			}
2399 			ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[i + 1]);
2400 			if (ret)
2401 				return ret;
2402 			*freq_ptr = input[i + 1];
2403 		}
2404 		break;
2405 	case PP_OD_EDIT_MCLK_VDDC_TABLE:
2406 		if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
2407 			dev_warn(smu->adev->dev, "UCLK_MAX not supported!\n");
2408 			return -ENOTSUPP;
2409 		}
2410 		if (size < 2) {
2411 			dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2412 			return -EINVAL;
2413 		}
2414 		if (input[0] != 1) {
2415 			dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]);
2416 			dev_info(smu->adev->dev, "Supported indices: [1:max]\n");
2417 			return -EINVAL;
2418 		}
2419 		ret = navi10_od_setting_check_range(smu, od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]);
2420 		if (ret)
2421 			return ret;
2422 		od_table->UclkFmax = input[1];
2423 		break;
2424 	case PP_OD_RESTORE_DEFAULT_TABLE:
2425 		if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2426 			dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2427 			return -EINVAL;
2428 		}
2429 		memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t));
2430 		break;
2431 	case PP_OD_COMMIT_DPM_TABLE:
2432 		navi10_dump_od_table(smu, od_table);
2433 		ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2434 		if (ret) {
2435 			dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2436 			return ret;
2437 		}
2438 		break;
2439 	case PP_OD_EDIT_VDDC_CURVE:
2440 		if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
2441 			dev_warn(smu->adev->dev, "GFXCLK_CURVE not supported!\n");
2442 			return -ENOTSUPP;
2443 		}
2444 		if (size < 3) {
2445 			dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2446 			return -EINVAL;
2447 		}
2448 		if (!od_table) {
2449 			dev_info(smu->adev->dev, "Overdrive is not initialized\n");
2450 			return -EINVAL;
2451 		}
2452 
2453 		switch (input[0]) {
2454 		case 0:
2455 			freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1;
2456 			voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1;
2457 			freq_ptr = &od_table->GfxclkFreq1;
2458 			voltage_ptr = &od_table->GfxclkVolt1;
2459 			break;
2460 		case 1:
2461 			freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2;
2462 			voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2;
2463 			freq_ptr = &od_table->GfxclkFreq2;
2464 			voltage_ptr = &od_table->GfxclkVolt2;
2465 			break;
2466 		case 2:
2467 			freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3;
2468 			voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3;
2469 			freq_ptr = &od_table->GfxclkFreq3;
2470 			voltage_ptr = &od_table->GfxclkVolt3;
2471 			break;
2472 		default:
2473 			dev_info(smu->adev->dev, "Invalid VDDC_CURVE index: %ld\n", input[0]);
2474 			dev_info(smu->adev->dev, "Supported indices: [0, 1, 2]\n");
2475 			return -EINVAL;
2476 		}
2477 		ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[1]);
2478 		if (ret)
2479 			return ret;
2480 		// Allow setting zero to disable the OverDrive VDDC curve
2481 		if (input[2] != 0) {
2482 			ret = navi10_od_setting_check_range(smu, od_settings, voltage_setting, input[2]);
2483 			if (ret)
2484 				return ret;
2485 			*freq_ptr = input[1];
2486 			*voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE;
2487 			dev_dbg(smu->adev->dev, "OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr);
2488 		} else {
2489 			// If setting 0, disable all voltage curve settings
2490 			od_table->GfxclkVolt1 = 0;
2491 			od_table->GfxclkVolt2 = 0;
2492 			od_table->GfxclkVolt3 = 0;
2493 		}
2494 		navi10_dump_od_table(smu, od_table);
2495 		break;
2496 	default:
2497 		return -ENOSYS;
2498 	}
2499 	return ret;
2500 }
2501 
2502 static int navi10_run_btc(struct smu_context *smu)
2503 {
2504 	int ret = 0;
2505 
2506 	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunBtc, NULL);
2507 	if (ret)
2508 		dev_err(smu->adev->dev, "RunBtc failed!\n");
2509 
2510 	return ret;
2511 }
2512 
2513 static bool navi10_need_umc_cdr_workaround(struct smu_context *smu)
2514 {
2515 	struct amdgpu_device *adev = smu->adev;
2516 
2517 	if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
2518 		return false;
2519 
2520 	if (adev->asic_type == CHIP_NAVI10 ||
2521 	    adev->asic_type == CHIP_NAVI14)
2522 		return true;
2523 
2524 	return false;
2525 }
2526 
2527 static int navi10_umc_hybrid_cdr_workaround(struct smu_context *smu)
2528 {
2529 	uint32_t uclk_count, uclk_min, uclk_max;
2530 	int ret = 0;
2531 
2532 	/* This workaround can be applied only with uclk dpm enabled */
2533 	if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
2534 		return 0;
2535 
2536 	ret = smu_v11_0_get_dpm_level_count(smu, SMU_UCLK, &uclk_count);
2537 	if (ret)
2538 		return ret;
2539 
2540 	ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)(uclk_count - 1), &uclk_max);
2541 	if (ret)
2542 		return ret;
2543 
2544 	/*
2545 	 * The NAVI10_UMC_HYBRID_CDR_WORKAROUND_UCLK_THRESHOLD is 750Mhz.
2546 	 * This workaround is needed only when the max uclk frequency
2547 	 * not greater than that.
2548 	 */
2549 	if (uclk_max > 0x2EE)
2550 		return 0;
2551 
2552 	ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)0, &uclk_min);
2553 	if (ret)
2554 		return ret;
2555 
2556 	/* Force UCLK out of the highest DPM */
2557 	ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_min);
2558 	if (ret)
2559 		return ret;
2560 
2561 	/* Revert the UCLK Hardmax */
2562 	ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_max);
2563 	if (ret)
2564 		return ret;
2565 
2566 	/*
2567 	 * In this case, SMU already disabled dummy pstate during enablement
2568 	 * of UCLK DPM, we have to re-enabled it.
2569 	 */
2570 	return smu_cmn_send_smc_msg(smu, SMU_MSG_DAL_ENABLE_DUMMY_PSTATE_CHANGE, NULL);
2571 }
2572 
2573 static int navi10_set_dummy_pstates_table_location(struct smu_context *smu)
2574 {
2575 	struct smu_table_context *smu_table = &smu->smu_table;
2576 	struct smu_table *dummy_read_table =
2577 				&smu_table->dummy_read_1_table;
2578 	char *dummy_table = dummy_read_table->cpu_addr;
2579 	int ret = 0;
2580 	uint32_t i;
2581 
2582 	for (i = 0; i < 0x40000; i += 0x1000 * 2) {
2583 		memcpy(dummy_table, &NoDbiPrbs7[0], 0x1000);
2584 		dummy_table += 0x1000;
2585 		memcpy(dummy_table, &DbiPrbs7[0], 0x1000);
2586 		dummy_table += 0x1000;
2587 	}
2588 
2589 	amdgpu_asic_flush_hdp(smu->adev, NULL);
2590 
2591 	ret = smu_cmn_send_smc_msg_with_param(smu,
2592 					      SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH,
2593 					      upper_32_bits(dummy_read_table->mc_address),
2594 					      NULL);
2595 	if (ret)
2596 		return ret;
2597 
2598 	return smu_cmn_send_smc_msg_with_param(smu,
2599 					       SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW,
2600 					       lower_32_bits(dummy_read_table->mc_address),
2601 					       NULL);
2602 }
2603 
2604 static int navi10_run_umc_cdr_workaround(struct smu_context *smu)
2605 {
2606 	struct amdgpu_device *adev = smu->adev;
2607 	uint8_t umc_fw_greater_than_v136 = false;
2608 	uint8_t umc_fw_disable_cdr = false;
2609 	uint32_t pmfw_version;
2610 	uint32_t param;
2611 	int ret = 0;
2612 
2613 	if (!navi10_need_umc_cdr_workaround(smu))
2614 		return 0;
2615 
2616 	ret = smu_cmn_get_smc_version(smu, NULL, &pmfw_version);
2617 	if (ret) {
2618 		dev_err(adev->dev, "Failed to get smu version!\n");
2619 		return ret;
2620 	}
2621 
2622 	/*
2623 	 * The messages below are only supported by Navi10 42.53.0 and later
2624 	 * PMFWs and Navi14 53.29.0 and later PMFWs.
2625 	 * - PPSMC_MSG_SetDriverDummyTableDramAddrHigh
2626 	 * - PPSMC_MSG_SetDriverDummyTableDramAddrLow
2627 	 * - PPSMC_MSG_GetUMCFWWA
2628 	 */
2629 	if (((adev->asic_type == CHIP_NAVI10) && (pmfw_version >= 0x2a3500)) ||
2630 	    ((adev->asic_type == CHIP_NAVI14) && (pmfw_version >= 0x351D00))) {
2631 		ret = smu_cmn_send_smc_msg_with_param(smu,
2632 						      SMU_MSG_GET_UMC_FW_WA,
2633 						      0,
2634 						      &param);
2635 		if (ret)
2636 			return ret;
2637 
2638 		/* First bit indicates if the UMC f/w is above v137 */
2639 		umc_fw_greater_than_v136 = param & 0x1;
2640 
2641 		/* Second bit indicates if hybrid-cdr is disabled */
2642 		umc_fw_disable_cdr = param & 0x2;
2643 
2644 		/* w/a only allowed if UMC f/w is <= 136 */
2645 		if (umc_fw_greater_than_v136)
2646 			return 0;
2647 
2648 		if (umc_fw_disable_cdr) {
2649 			if (adev->asic_type == CHIP_NAVI10)
2650 				return navi10_umc_hybrid_cdr_workaround(smu);
2651 		} else {
2652 			return navi10_set_dummy_pstates_table_location(smu);
2653 		}
2654 	} else {
2655 		if (adev->asic_type == CHIP_NAVI10)
2656 			return navi10_umc_hybrid_cdr_workaround(smu);
2657 	}
2658 
2659 	return 0;
2660 }
2661 
2662 static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu,
2663 					     void **table)
2664 {
2665 	struct smu_table_context *smu_table = &smu->smu_table;
2666 	struct gpu_metrics_v1_3 *gpu_metrics =
2667 		(struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2668 	SmuMetrics_legacy_t metrics;
2669 	int ret = 0;
2670 
2671 	mutex_lock(&smu->metrics_lock);
2672 
2673 	ret = smu_cmn_get_metrics_table_locked(smu,
2674 					       NULL,
2675 					       true);
2676 	if (ret) {
2677 		mutex_unlock(&smu->metrics_lock);
2678 		return ret;
2679 	}
2680 
2681 	memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_legacy_t));
2682 
2683 	mutex_unlock(&smu->metrics_lock);
2684 
2685 	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2686 
2687 	gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2688 	gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2689 	gpu_metrics->temperature_mem = metrics.TemperatureMem;
2690 	gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2691 	gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2692 	gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2693 
2694 	gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2695 	gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2696 
2697 	gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2698 
2699 	gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2700 	gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2701 	gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2702 
2703 	gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2704 	gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2705 	gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2706 	gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2707 	gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2708 
2709 	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2710 	gpu_metrics->indep_throttle_status =
2711 			smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
2712 							   navi1x_throttler_map);
2713 
2714 	gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2715 
2716 	gpu_metrics->pcie_link_width =
2717 			smu_v11_0_get_current_pcie_link_width(smu);
2718 	gpu_metrics->pcie_link_speed =
2719 			smu_v11_0_get_current_pcie_link_speed(smu);
2720 
2721 	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2722 
2723 	if (metrics.CurrGfxVoltageOffset)
2724 		gpu_metrics->voltage_gfx =
2725 			(155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
2726 	if (metrics.CurrMemVidOffset)
2727 		gpu_metrics->voltage_mem =
2728 			(155000 - 625 * metrics.CurrMemVidOffset) / 100;
2729 	if (metrics.CurrSocVoltageOffset)
2730 		gpu_metrics->voltage_soc =
2731 			(155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
2732 
2733 	*table = (void *)gpu_metrics;
2734 
2735 	return sizeof(struct gpu_metrics_v1_3);
2736 }
2737 
2738 static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
2739 				      void **table)
2740 {
2741 	struct smu_table_context *smu_table = &smu->smu_table;
2742 	struct gpu_metrics_v1_3 *gpu_metrics =
2743 		(struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2744 	SmuMetrics_t metrics;
2745 	int ret = 0;
2746 
2747 	mutex_lock(&smu->metrics_lock);
2748 
2749 	ret = smu_cmn_get_metrics_table_locked(smu,
2750 					       NULL,
2751 					       true);
2752 	if (ret) {
2753 		mutex_unlock(&smu->metrics_lock);
2754 		return ret;
2755 	}
2756 
2757 	memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_t));
2758 
2759 	mutex_unlock(&smu->metrics_lock);
2760 
2761 	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2762 
2763 	gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2764 	gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2765 	gpu_metrics->temperature_mem = metrics.TemperatureMem;
2766 	gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2767 	gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2768 	gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2769 
2770 	gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2771 	gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2772 
2773 	gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2774 
2775 	if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
2776 		gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs;
2777 	else
2778 		gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs;
2779 
2780 	gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2781 	gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs;
2782 
2783 	gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2784 	gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2785 	gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2786 	gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2787 	gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2788 
2789 	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2790 	gpu_metrics->indep_throttle_status =
2791 			smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
2792 							   navi1x_throttler_map);
2793 
2794 	gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2795 
2796 	gpu_metrics->pcie_link_width = metrics.PcieWidth;
2797 	gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate];
2798 
2799 	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2800 
2801 	if (metrics.CurrGfxVoltageOffset)
2802 		gpu_metrics->voltage_gfx =
2803 			(155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
2804 	if (metrics.CurrMemVidOffset)
2805 		gpu_metrics->voltage_mem =
2806 			(155000 - 625 * metrics.CurrMemVidOffset) / 100;
2807 	if (metrics.CurrSocVoltageOffset)
2808 		gpu_metrics->voltage_soc =
2809 			(155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
2810 
2811 	*table = (void *)gpu_metrics;
2812 
2813 	return sizeof(struct gpu_metrics_v1_3);
2814 }
2815 
2816 static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu,
2817 					     void **table)
2818 {
2819 	struct smu_table_context *smu_table = &smu->smu_table;
2820 	struct gpu_metrics_v1_3 *gpu_metrics =
2821 		(struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2822 	SmuMetrics_NV12_legacy_t metrics;
2823 	int ret = 0;
2824 
2825 	mutex_lock(&smu->metrics_lock);
2826 
2827 	ret = smu_cmn_get_metrics_table_locked(smu,
2828 					       NULL,
2829 					       true);
2830 	if (ret) {
2831 		mutex_unlock(&smu->metrics_lock);
2832 		return ret;
2833 	}
2834 
2835 	memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_legacy_t));
2836 
2837 	mutex_unlock(&smu->metrics_lock);
2838 
2839 	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2840 
2841 	gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2842 	gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2843 	gpu_metrics->temperature_mem = metrics.TemperatureMem;
2844 	gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2845 	gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2846 	gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2847 
2848 	gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2849 	gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2850 
2851 	gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2852 
2853 	gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2854 	gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2855 	gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2856 
2857 	gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
2858 	gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
2859 	gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
2860 	gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
2861 
2862 	gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2863 	gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2864 	gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2865 	gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2866 	gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2867 
2868 	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2869 	gpu_metrics->indep_throttle_status =
2870 			smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
2871 							   navi1x_throttler_map);
2872 
2873 	gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2874 
2875 	gpu_metrics->pcie_link_width =
2876 			smu_v11_0_get_current_pcie_link_width(smu);
2877 	gpu_metrics->pcie_link_speed =
2878 			smu_v11_0_get_current_pcie_link_speed(smu);
2879 
2880 	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2881 
2882 	if (metrics.CurrGfxVoltageOffset)
2883 		gpu_metrics->voltage_gfx =
2884 			(155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
2885 	if (metrics.CurrMemVidOffset)
2886 		gpu_metrics->voltage_mem =
2887 			(155000 - 625 * metrics.CurrMemVidOffset) / 100;
2888 	if (metrics.CurrSocVoltageOffset)
2889 		gpu_metrics->voltage_soc =
2890 			(155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
2891 
2892 	*table = (void *)gpu_metrics;
2893 
2894 	return sizeof(struct gpu_metrics_v1_3);
2895 }
2896 
2897 static ssize_t navi12_get_gpu_metrics(struct smu_context *smu,
2898 				      void **table)
2899 {
2900 	struct smu_table_context *smu_table = &smu->smu_table;
2901 	struct gpu_metrics_v1_3 *gpu_metrics =
2902 		(struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2903 	SmuMetrics_NV12_t metrics;
2904 	int ret = 0;
2905 
2906 	mutex_lock(&smu->metrics_lock);
2907 
2908 	ret = smu_cmn_get_metrics_table_locked(smu,
2909 					       NULL,
2910 					       true);
2911 	if (ret) {
2912 		mutex_unlock(&smu->metrics_lock);
2913 		return ret;
2914 	}
2915 
2916 	memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_t));
2917 
2918 	mutex_unlock(&smu->metrics_lock);
2919 
2920 	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2921 
2922 	gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2923 	gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2924 	gpu_metrics->temperature_mem = metrics.TemperatureMem;
2925 	gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2926 	gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2927 	gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2928 
2929 	gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2930 	gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2931 
2932 	gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2933 
2934 	if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
2935 		gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs;
2936 	else
2937 		gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs;
2938 
2939 	gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2940 	gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs;
2941 
2942 	gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
2943 	gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
2944 	gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
2945 	gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
2946 
2947 	gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2948 	gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2949 	gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2950 	gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2951 	gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2952 
2953 	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2954 	gpu_metrics->indep_throttle_status =
2955 			smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
2956 							   navi1x_throttler_map);
2957 
2958 	gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2959 
2960 	gpu_metrics->pcie_link_width = metrics.PcieWidth;
2961 	gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate];
2962 
2963 	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2964 
2965 	if (metrics.CurrGfxVoltageOffset)
2966 		gpu_metrics->voltage_gfx =
2967 			(155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
2968 	if (metrics.CurrMemVidOffset)
2969 		gpu_metrics->voltage_mem =
2970 			(155000 - 625 * metrics.CurrMemVidOffset) / 100;
2971 	if (metrics.CurrSocVoltageOffset)
2972 		gpu_metrics->voltage_soc =
2973 			(155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
2974 
2975 	*table = (void *)gpu_metrics;
2976 
2977 	return sizeof(struct gpu_metrics_v1_3);
2978 }
2979 
2980 static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu,
2981 				      void **table)
2982 {
2983 	struct amdgpu_device *adev = smu->adev;
2984 	uint32_t smu_version;
2985 	int ret = 0;
2986 
2987 	ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2988 	if (ret) {
2989 		dev_err(adev->dev, "Failed to get smu version!\n");
2990 		return ret;
2991 	}
2992 
2993 	switch (adev->asic_type) {
2994 	case CHIP_NAVI12:
2995 		if (smu_version > 0x00341C00)
2996 			ret = navi12_get_gpu_metrics(smu, table);
2997 		else
2998 			ret = navi12_get_legacy_gpu_metrics(smu, table);
2999 		break;
3000 	case CHIP_NAVI10:
3001 	case CHIP_NAVI14:
3002 	default:
3003 		if (((adev->asic_type == CHIP_NAVI14) && smu_version > 0x00351F00) ||
3004 		      ((adev->asic_type == CHIP_NAVI10) && smu_version > 0x002A3B00))
3005 			ret = navi10_get_gpu_metrics(smu, table);
3006 		else
3007 			ret =navi10_get_legacy_gpu_metrics(smu, table);
3008 		break;
3009 	}
3010 
3011 	return ret;
3012 }
3013 
3014 static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
3015 {
3016 	struct smu_table_context *table_context = &smu->smu_table;
3017 	PPTable_t *smc_pptable = table_context->driver_pptable;
3018 	struct amdgpu_device *adev = smu->adev;
3019 	uint32_t param = 0;
3020 
3021 	/* Navi12 does not support this */
3022 	if (adev->asic_type == CHIP_NAVI12)
3023 		return 0;
3024 
3025 	/*
3026 	 * Skip the MGpuFanBoost setting for those ASICs
3027 	 * which do not support it
3028 	 */
3029 	if (!smc_pptable->MGpuFanBoostLimitRpm)
3030 		return 0;
3031 
3032 	/* Workaround for WS SKU */
3033 	if (adev->pdev->device == 0x7312 &&
3034 	    adev->pdev->revision == 0)
3035 		param = 0xD188;
3036 
3037 	return smu_cmn_send_smc_msg_with_param(smu,
3038 					       SMU_MSG_SetMGpuFanBoostLimitRpm,
3039 					       param,
3040 					       NULL);
3041 }
3042 
3043 static int navi10_post_smu_init(struct smu_context *smu)
3044 {
3045 	struct amdgpu_device *adev = smu->adev;
3046 	int ret = 0;
3047 
3048 	if (amdgpu_sriov_vf(adev))
3049 		return 0;
3050 
3051 	ret = navi10_run_umc_cdr_workaround(smu);
3052 	if (ret) {
3053 		dev_err(adev->dev, "Failed to apply umc cdr workaround!\n");
3054 		return ret;
3055 	}
3056 
3057 	if (!smu->dc_controlled_by_gpio) {
3058 		/*
3059 		 * For Navi1X, manually switch it to AC mode as PMFW
3060 		 * may boot it with DC mode.
3061 		 */
3062 		ret = smu_v11_0_set_power_source(smu,
3063 						 adev->pm.ac_power ?
3064 						 SMU_POWER_SOURCE_AC :
3065 						 SMU_POWER_SOURCE_DC);
3066 		if (ret) {
3067 			dev_err(adev->dev, "Failed to switch to %s mode!\n",
3068 					adev->pm.ac_power ? "AC" : "DC");
3069 			return ret;
3070 		}
3071 	}
3072 
3073 	return ret;
3074 }
3075 
3076 static const struct pptable_funcs navi10_ppt_funcs = {
3077 	.get_allowed_feature_mask = navi10_get_allowed_feature_mask,
3078 	.set_default_dpm_table = navi10_set_default_dpm_table,
3079 	.dpm_set_vcn_enable = navi10_dpm_set_vcn_enable,
3080 	.dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
3081 	.print_clk_levels = navi10_print_clk_levels,
3082 	.force_clk_levels = navi10_force_clk_levels,
3083 	.populate_umd_state_clk = navi10_populate_umd_state_clk,
3084 	.get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
3085 	.pre_display_config_changed = navi10_pre_display_config_changed,
3086 	.display_config_changed = navi10_display_config_changed,
3087 	.notify_smc_display_config = navi10_notify_smc_display_config,
3088 	.is_dpm_running = navi10_is_dpm_running,
3089 	.get_fan_speed_percent = navi10_get_fan_speed_percent,
3090 	.get_power_profile_mode = navi10_get_power_profile_mode,
3091 	.set_power_profile_mode = navi10_set_power_profile_mode,
3092 	.set_watermarks_table = navi10_set_watermarks_table,
3093 	.read_sensor = navi10_read_sensor,
3094 	.get_uclk_dpm_states = navi10_get_uclk_dpm_states,
3095 	.set_performance_level = smu_v11_0_set_performance_level,
3096 	.get_thermal_temperature_range = navi10_get_thermal_temperature_range,
3097 	.display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
3098 	.get_power_limit = navi10_get_power_limit,
3099 	.update_pcie_parameters = navi10_update_pcie_parameters,
3100 	.init_microcode = smu_v11_0_init_microcode,
3101 	.load_microcode = smu_v11_0_load_microcode,
3102 	.fini_microcode = smu_v11_0_fini_microcode,
3103 	.init_smc_tables = navi10_init_smc_tables,
3104 	.fini_smc_tables = smu_v11_0_fini_smc_tables,
3105 	.init_power = smu_v11_0_init_power,
3106 	.fini_power = smu_v11_0_fini_power,
3107 	.check_fw_status = smu_v11_0_check_fw_status,
3108 	.setup_pptable = navi10_setup_pptable,
3109 	.get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
3110 	.check_fw_version = smu_v11_0_check_fw_version,
3111 	.write_pptable = smu_cmn_write_pptable,
3112 	.set_driver_table_location = smu_v11_0_set_driver_table_location,
3113 	.set_tool_table_location = smu_v11_0_set_tool_table_location,
3114 	.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
3115 	.system_features_control = smu_v11_0_system_features_control,
3116 	.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
3117 	.send_smc_msg = smu_cmn_send_smc_msg,
3118 	.init_display_count = smu_v11_0_init_display_count,
3119 	.set_allowed_mask = smu_v11_0_set_allowed_mask,
3120 	.get_enabled_mask = smu_cmn_get_enabled_mask,
3121 	.feature_is_enabled = smu_cmn_feature_is_enabled,
3122 	.disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
3123 	.notify_display_change = smu_v11_0_notify_display_change,
3124 	.set_power_limit = smu_v11_0_set_power_limit,
3125 	.init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
3126 	.enable_thermal_alert = smu_v11_0_enable_thermal_alert,
3127 	.disable_thermal_alert = smu_v11_0_disable_thermal_alert,
3128 	.set_min_dcef_deep_sleep = smu_v11_0_set_min_deep_sleep_dcefclk,
3129 	.display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
3130 	.get_fan_control_mode = smu_v11_0_get_fan_control_mode,
3131 	.set_fan_control_mode = smu_v11_0_set_fan_control_mode,
3132 	.set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
3133 	.set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
3134 	.gfx_off_control = smu_v11_0_gfx_off_control,
3135 	.register_irq_handler = smu_v11_0_register_irq_handler,
3136 	.set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
3137 	.get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
3138 	.baco_is_support = smu_v11_0_baco_is_support,
3139 	.baco_get_state = smu_v11_0_baco_get_state,
3140 	.baco_set_state = smu_v11_0_baco_set_state,
3141 	.baco_enter = navi10_baco_enter,
3142 	.baco_exit = navi10_baco_exit,
3143 	.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
3144 	.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
3145 	.set_default_od_settings = navi10_set_default_od_settings,
3146 	.od_edit_dpm_table = navi10_od_edit_dpm_table,
3147 	.run_btc = navi10_run_btc,
3148 	.set_power_source = smu_v11_0_set_power_source,
3149 	.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3150 	.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
3151 	.get_gpu_metrics = navi1x_get_gpu_metrics,
3152 	.enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost,
3153 	.gfx_ulv_control = smu_v11_0_gfx_ulv_control,
3154 	.deep_sleep_control = smu_v11_0_deep_sleep_control,
3155 	.get_fan_parameters = navi10_get_fan_parameters,
3156 	.post_init = navi10_post_smu_init,
3157 	.interrupt_work = smu_v11_0_interrupt_work,
3158 	.set_mp1_state = smu_cmn_set_mp1_state,
3159 };
3160 
3161 void navi10_set_ppt_funcs(struct smu_context *smu)
3162 {
3163 	smu->ppt_funcs = &navi10_ppt_funcs;
3164 	smu->message_map = navi10_message_map;
3165 	smu->clock_map = navi10_clk_map;
3166 	smu->feature_map = navi10_feature_mask_map;
3167 	smu->table_map = navi10_table_map;
3168 	smu->pwr_src_map = navi10_pwr_src_map;
3169 	smu->workload_map = navi10_workload_map;
3170 }
3171