1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include <linux/pci.h> 28 #include <linux/i2c.h> 29 #include "amdgpu.h" 30 #include "amdgpu_dpm.h" 31 #include "amdgpu_smu.h" 32 #include "atomfirmware.h" 33 #include "amdgpu_atomfirmware.h" 34 #include "amdgpu_atombios.h" 35 #include "soc15_common.h" 36 #include "smu_v11_0.h" 37 #include "smu11_driver_if_navi10.h" 38 #include "atom.h" 39 #include "navi10_ppt.h" 40 #include "smu_v11_0_pptable.h" 41 #include "smu_v11_0_ppsmc.h" 42 #include "nbio/nbio_2_3_offset.h" 43 #include "nbio/nbio_2_3_sh_mask.h" 44 #include "thm/thm_11_0_2_offset.h" 45 #include "thm/thm_11_0_2_sh_mask.h" 46 47 #include "asic_reg/mp/mp_11_0_sh_mask.h" 48 #include "smu_cmn.h" 49 #include "smu_11_0_cdr_table.h" 50 51 /* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56 #undef pr_err 57 #undef pr_warn 58 #undef pr_info 59 #undef pr_debug 60 61 #define FEATURE_MASK(feature) (1ULL << feature) 62 #define SMC_DPM_FEATURE ( \ 63 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \ 64 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 65 FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT) | \ 66 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 70 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)) 71 72 #define SMU_11_0_GFX_BUSY_THRESHOLD 15 73 74 static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = { 75 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 76 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 77 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 78 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0), 79 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), 80 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 81 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 82 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 0), 83 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 0), 84 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 0), 85 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 0), 86 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1), 87 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1), 88 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 0), 89 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 90 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 91 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 92 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 93 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 94 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 95 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 96 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 97 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable, 0), 98 MSG_MAP(RunBtc, PPSMC_MSG_RunBtc, 0), 99 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), 100 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1), 101 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), 102 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0), 103 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 104 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), 105 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), 106 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 107 MSG_MAP(SetMemoryChannelConfig, PPSMC_MSG_SetMemoryChannelConfig, 0), 108 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0), 109 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0), 110 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0), 111 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0), 112 MSG_MAP(SetMinDeepSleepDcefclk, PPSMC_MSG_SetMinDeepSleepDcefclk, 0), 113 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0), 114 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0), 115 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0), 116 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0), 117 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1), 118 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 119 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 120 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 121 MSG_MAP(ConfigureGfxDidt, PPSMC_MSG_ConfigureGfxDidt, 0), 122 MSG_MAP(NumOfDisplays, PPSMC_MSG_NumOfDisplays, 0), 123 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0), 124 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0), 125 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 126 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 127 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 128 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1), 129 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0), 130 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0), 131 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset, 0), 132 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown, 0), 133 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 134 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 135 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 136 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 137 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0), 138 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0), 139 MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALDisableDummyPstateChange, 0), 140 MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALEnableDummyPstateChange, 0), 141 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0), 142 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0), 143 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0), 144 MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH, PPSMC_MSG_SetDriverDummyTableDramAddrHigh, 0), 145 MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW, PPSMC_MSG_SetDriverDummyTableDramAddrLow, 0), 146 MSG_MAP(GET_UMC_FW_WA, PPSMC_MSG_GetUMCFWWA, 0), 147 }; 148 149 static struct cmn2asic_mapping navi10_clk_map[SMU_CLK_COUNT] = { 150 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 151 CLK_MAP(SCLK, PPCLK_GFXCLK), 152 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 153 CLK_MAP(FCLK, PPCLK_SOCCLK), 154 CLK_MAP(UCLK, PPCLK_UCLK), 155 CLK_MAP(MCLK, PPCLK_UCLK), 156 CLK_MAP(DCLK, PPCLK_DCLK), 157 CLK_MAP(VCLK, PPCLK_VCLK), 158 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK), 159 CLK_MAP(DISPCLK, PPCLK_DISPCLK), 160 CLK_MAP(PIXCLK, PPCLK_PIXCLK), 161 CLK_MAP(PHYCLK, PPCLK_PHYCLK), 162 }; 163 164 static struct cmn2asic_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = { 165 FEA_MAP(DPM_PREFETCHER), 166 FEA_MAP(DPM_GFXCLK), 167 FEA_MAP(DPM_GFX_PACE), 168 FEA_MAP(DPM_UCLK), 169 FEA_MAP(DPM_SOCCLK), 170 FEA_MAP(DPM_MP0CLK), 171 FEA_MAP(DPM_LINK), 172 FEA_MAP(DPM_DCEFCLK), 173 FEA_MAP(MEM_VDDCI_SCALING), 174 FEA_MAP(MEM_MVDD_SCALING), 175 FEA_MAP(DS_GFXCLK), 176 FEA_MAP(DS_SOCCLK), 177 FEA_MAP(DS_LCLK), 178 FEA_MAP(DS_DCEFCLK), 179 FEA_MAP(DS_UCLK), 180 FEA_MAP(GFX_ULV), 181 FEA_MAP(FW_DSTATE), 182 FEA_MAP(GFXOFF), 183 FEA_MAP(BACO), 184 FEA_MAP(VCN_PG), 185 FEA_MAP(JPEG_PG), 186 FEA_MAP(USB_PG), 187 FEA_MAP(RSMU_SMN_CG), 188 FEA_MAP(PPT), 189 FEA_MAP(TDC), 190 FEA_MAP(GFX_EDC), 191 FEA_MAP(APCC_PLUS), 192 FEA_MAP(GTHR), 193 FEA_MAP(ACDC), 194 FEA_MAP(VR0HOT), 195 FEA_MAP(VR1HOT), 196 FEA_MAP(FW_CTF), 197 FEA_MAP(FAN_CONTROL), 198 FEA_MAP(THERMAL), 199 FEA_MAP(GFX_DCS), 200 FEA_MAP(RM), 201 FEA_MAP(LED_DISPLAY), 202 FEA_MAP(GFX_SS), 203 FEA_MAP(OUT_OF_BAND_MONITOR), 204 FEA_MAP(TEMP_DEPENDENT_VMIN), 205 FEA_MAP(MMHUB_PG), 206 FEA_MAP(ATHUB_PG), 207 FEA_MAP(APCC_DFLL), 208 }; 209 210 static struct cmn2asic_mapping navi10_table_map[SMU_TABLE_COUNT] = { 211 TAB_MAP(PPTABLE), 212 TAB_MAP(WATERMARKS), 213 TAB_MAP(AVFS), 214 TAB_MAP(AVFS_PSM_DEBUG), 215 TAB_MAP(AVFS_FUSE_OVERRIDE), 216 TAB_MAP(PMSTATUSLOG), 217 TAB_MAP(SMU_METRICS), 218 TAB_MAP(DRIVER_SMU_CONFIG), 219 TAB_MAP(ACTIVITY_MONITOR_COEFF), 220 TAB_MAP(OVERDRIVE), 221 TAB_MAP(I2C_COMMANDS), 222 TAB_MAP(PACE), 223 }; 224 225 static struct cmn2asic_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { 226 PWR_MAP(AC), 227 PWR_MAP(DC), 228 }; 229 230 static struct cmn2asic_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 231 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), 232 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 233 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 234 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 235 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 236 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 237 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 238 }; 239 240 static const uint8_t navi1x_throttler_map[] = { 241 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT), 242 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT), 243 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 244 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 245 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 246 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT), 247 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 248 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT), 249 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT), 250 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 251 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 252 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 253 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 254 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT), 255 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT), 256 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), 257 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT), 258 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT), 259 }; 260 261 262 static bool is_asic_secure(struct smu_context *smu) 263 { 264 struct amdgpu_device *adev = smu->adev; 265 bool is_secure = true; 266 uint32_t mp0_fw_intf; 267 268 mp0_fw_intf = RREG32_PCIE(MP0_Public | 269 (smnMP0_FW_INTF & 0xffffffff)); 270 271 if (!(mp0_fw_intf & (1 << 19))) 272 is_secure = false; 273 274 return is_secure; 275 } 276 277 static int 278 navi10_get_allowed_feature_mask(struct smu_context *smu, 279 uint32_t *feature_mask, uint32_t num) 280 { 281 struct amdgpu_device *adev = smu->adev; 282 283 if (num > 2) 284 return -EINVAL; 285 286 memset(feature_mask, 0, sizeof(uint32_t) * num); 287 288 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) 289 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) 290 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) 291 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) 292 | FEATURE_MASK(FEATURE_PPT_BIT) 293 | FEATURE_MASK(FEATURE_TDC_BIT) 294 | FEATURE_MASK(FEATURE_GFX_EDC_BIT) 295 | FEATURE_MASK(FEATURE_APCC_PLUS_BIT) 296 | FEATURE_MASK(FEATURE_VR0HOT_BIT) 297 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) 298 | FEATURE_MASK(FEATURE_THERMAL_BIT) 299 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT) 300 | FEATURE_MASK(FEATURE_DS_LCLK_BIT) 301 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) 302 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) 303 | FEATURE_MASK(FEATURE_BACO_BIT) 304 | FEATURE_MASK(FEATURE_GFX_SS_BIT) 305 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) 306 | FEATURE_MASK(FEATURE_FW_CTF_BIT) 307 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT) 308 | FEATURE_MASK(FEATURE_TEMP_DEPENDENT_VMIN_BIT); 309 310 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) 311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 312 313 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) 314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); 315 316 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) 317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); 318 319 if (adev->pm.pp_feature & PP_ULV_MASK) 320 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); 321 322 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) 323 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 324 325 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 326 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); 327 328 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) 329 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); 330 331 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB) 332 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT); 333 334 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN) 335 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT); 336 337 if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG) 338 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT); 339 340 if (smu->dc_controlled_by_gpio) 341 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT); 342 343 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) 344 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 345 346 /* DPM UCLK enablement should be skipped for navi10 A0 secure board */ 347 if (!(is_asic_secure(smu) && 348 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && 349 (adev->rev_id == 0)) && 350 (adev->pm.pp_feature & PP_MCLK_DPM_MASK)) 351 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) 352 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) 353 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); 354 355 /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */ 356 if (is_asic_secure(smu) && 357 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && 358 (adev->rev_id == 0)) 359 *(uint64_t *)feature_mask &= 360 ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT); 361 362 return 0; 363 } 364 365 static void navi10_check_bxco_support(struct smu_context *smu) 366 { 367 struct smu_table_context *table_context = &smu->smu_table; 368 struct smu_11_0_powerplay_table *powerplay_table = 369 table_context->power_play_table; 370 struct smu_baco_context *smu_baco = &smu->smu_baco; 371 struct amdgpu_device *adev = smu->adev; 372 uint32_t val; 373 374 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO || 375 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) { 376 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); 377 smu_baco->platform_support = 378 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : 379 false; 380 } 381 } 382 383 static int navi10_check_powerplay_table(struct smu_context *smu) 384 { 385 struct smu_table_context *table_context = &smu->smu_table; 386 struct smu_11_0_powerplay_table *powerplay_table = 387 table_context->power_play_table; 388 389 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC) 390 smu->dc_controlled_by_gpio = true; 391 392 navi10_check_bxco_support(smu); 393 394 table_context->thermal_controller_type = 395 powerplay_table->thermal_controller_type; 396 397 /* 398 * Instead of having its own buffer space and get overdrive_table copied, 399 * smu->od_settings just points to the actual overdrive_table 400 */ 401 smu->od_settings = &powerplay_table->overdrive_table; 402 403 return 0; 404 } 405 406 static int navi10_append_powerplay_table(struct smu_context *smu) 407 { 408 struct amdgpu_device *adev = smu->adev; 409 struct smu_table_context *table_context = &smu->smu_table; 410 PPTable_t *smc_pptable = table_context->driver_pptable; 411 struct atom_smc_dpm_info_v4_5 *smc_dpm_table; 412 struct atom_smc_dpm_info_v4_7 *smc_dpm_table_v4_7; 413 int index, ret; 414 415 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 416 smc_dpm_info); 417 418 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL, 419 (uint8_t **)&smc_dpm_table); 420 if (ret) 421 return ret; 422 423 dev_info(adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n", 424 smc_dpm_table->table_header.format_revision, 425 smc_dpm_table->table_header.content_revision); 426 427 if (smc_dpm_table->table_header.format_revision != 4) { 428 dev_err(adev->dev, "smc_dpm_info table format revision is not 4!\n"); 429 return -EINVAL; 430 } 431 432 switch (smc_dpm_table->table_header.content_revision) { 433 case 5: /* nv10 and nv14 */ 434 smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved, 435 smc_dpm_table, I2cControllers); 436 break; 437 case 7: /* nv12 */ 438 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL, 439 (uint8_t **)&smc_dpm_table_v4_7); 440 if (ret) 441 return ret; 442 smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved, 443 smc_dpm_table_v4_7, I2cControllers); 444 break; 445 default: 446 dev_err(smu->adev->dev, "smc_dpm_info with unsupported content revision %d!\n", 447 smc_dpm_table->table_header.content_revision); 448 return -EINVAL; 449 } 450 451 if (adev->pm.pp_feature & PP_GFXOFF_MASK) { 452 /* TODO: remove it once SMU fw fix it */ 453 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN; 454 } 455 456 return 0; 457 } 458 459 static int navi10_store_powerplay_table(struct smu_context *smu) 460 { 461 struct smu_table_context *table_context = &smu->smu_table; 462 struct smu_11_0_powerplay_table *powerplay_table = 463 table_context->power_play_table; 464 465 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 466 sizeof(PPTable_t)); 467 468 return 0; 469 } 470 471 static int navi10_setup_pptable(struct smu_context *smu) 472 { 473 int ret = 0; 474 475 ret = smu_v11_0_setup_pptable(smu); 476 if (ret) 477 return ret; 478 479 ret = navi10_store_powerplay_table(smu); 480 if (ret) 481 return ret; 482 483 ret = navi10_append_powerplay_table(smu); 484 if (ret) 485 return ret; 486 487 ret = navi10_check_powerplay_table(smu); 488 if (ret) 489 return ret; 490 491 return ret; 492 } 493 494 static int navi10_tables_init(struct smu_context *smu) 495 { 496 struct smu_table_context *smu_table = &smu->smu_table; 497 struct smu_table *tables = smu_table->tables; 498 struct smu_table *dummy_read_1_table = 499 &smu_table->dummy_read_1_table; 500 501 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 502 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 503 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 504 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 505 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_NV1X_t), 506 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 507 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 508 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 509 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t), 510 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 511 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 512 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 513 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, 514 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE, 515 AMDGPU_GEM_DOMAIN_VRAM); 516 SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfig_t), 517 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 518 519 dummy_read_1_table->size = 0x40000; 520 dummy_read_1_table->align = PAGE_SIZE; 521 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 522 523 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_NV1X_t), 524 GFP_KERNEL); 525 if (!smu_table->metrics_table) 526 goto err0_out; 527 smu_table->metrics_time = 0; 528 529 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 530 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 531 if (!smu_table->gpu_metrics_table) 532 goto err1_out; 533 534 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 535 if (!smu_table->watermarks_table) 536 goto err2_out; 537 538 smu_table->driver_smu_config_table = 539 kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL); 540 if (!smu_table->driver_smu_config_table) 541 goto err3_out; 542 543 return 0; 544 545 err3_out: 546 kfree(smu_table->watermarks_table); 547 err2_out: 548 kfree(smu_table->gpu_metrics_table); 549 err1_out: 550 kfree(smu_table->metrics_table); 551 err0_out: 552 return -ENOMEM; 553 } 554 555 static int navi10_get_legacy_smu_metrics_data(struct smu_context *smu, 556 MetricsMember_t member, 557 uint32_t *value) 558 { 559 struct smu_table_context *smu_table = &smu->smu_table; 560 SmuMetrics_legacy_t *metrics = 561 (SmuMetrics_legacy_t *)smu_table->metrics_table; 562 int ret = 0; 563 564 ret = smu_cmn_get_metrics_table(smu, 565 NULL, 566 false); 567 if (ret) 568 return ret; 569 570 switch (member) { 571 case METRICS_CURR_GFXCLK: 572 *value = metrics->CurrClock[PPCLK_GFXCLK]; 573 break; 574 case METRICS_CURR_SOCCLK: 575 *value = metrics->CurrClock[PPCLK_SOCCLK]; 576 break; 577 case METRICS_CURR_UCLK: 578 *value = metrics->CurrClock[PPCLK_UCLK]; 579 break; 580 case METRICS_CURR_VCLK: 581 *value = metrics->CurrClock[PPCLK_VCLK]; 582 break; 583 case METRICS_CURR_DCLK: 584 *value = metrics->CurrClock[PPCLK_DCLK]; 585 break; 586 case METRICS_CURR_DCEFCLK: 587 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 588 break; 589 case METRICS_AVERAGE_GFXCLK: 590 *value = metrics->AverageGfxclkFrequency; 591 break; 592 case METRICS_AVERAGE_SOCCLK: 593 *value = metrics->AverageSocclkFrequency; 594 break; 595 case METRICS_AVERAGE_UCLK: 596 *value = metrics->AverageUclkFrequency; 597 break; 598 case METRICS_AVERAGE_GFXACTIVITY: 599 *value = metrics->AverageGfxActivity; 600 break; 601 case METRICS_AVERAGE_MEMACTIVITY: 602 *value = metrics->AverageUclkActivity; 603 break; 604 case METRICS_AVERAGE_SOCKETPOWER: 605 *value = metrics->AverageSocketPower << 8; 606 break; 607 case METRICS_TEMPERATURE_EDGE: 608 *value = metrics->TemperatureEdge * 609 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 610 break; 611 case METRICS_TEMPERATURE_HOTSPOT: 612 *value = metrics->TemperatureHotspot * 613 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 614 break; 615 case METRICS_TEMPERATURE_MEM: 616 *value = metrics->TemperatureMem * 617 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 618 break; 619 case METRICS_TEMPERATURE_VRGFX: 620 *value = metrics->TemperatureVrGfx * 621 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 622 break; 623 case METRICS_TEMPERATURE_VRSOC: 624 *value = metrics->TemperatureVrSoc * 625 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 626 break; 627 case METRICS_THROTTLER_STATUS: 628 *value = metrics->ThrottlerStatus; 629 break; 630 case METRICS_CURR_FANSPEED: 631 *value = metrics->CurrFanSpeed; 632 break; 633 default: 634 *value = UINT_MAX; 635 break; 636 } 637 638 return ret; 639 } 640 641 static int navi10_get_smu_metrics_data(struct smu_context *smu, 642 MetricsMember_t member, 643 uint32_t *value) 644 { 645 struct smu_table_context *smu_table = &smu->smu_table; 646 SmuMetrics_t *metrics = 647 (SmuMetrics_t *)smu_table->metrics_table; 648 int ret = 0; 649 650 ret = smu_cmn_get_metrics_table(smu, 651 NULL, 652 false); 653 if (ret) 654 return ret; 655 656 switch (member) { 657 case METRICS_CURR_GFXCLK: 658 *value = metrics->CurrClock[PPCLK_GFXCLK]; 659 break; 660 case METRICS_CURR_SOCCLK: 661 *value = metrics->CurrClock[PPCLK_SOCCLK]; 662 break; 663 case METRICS_CURR_UCLK: 664 *value = metrics->CurrClock[PPCLK_UCLK]; 665 break; 666 case METRICS_CURR_VCLK: 667 *value = metrics->CurrClock[PPCLK_VCLK]; 668 break; 669 case METRICS_CURR_DCLK: 670 *value = metrics->CurrClock[PPCLK_DCLK]; 671 break; 672 case METRICS_CURR_DCEFCLK: 673 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 674 break; 675 case METRICS_AVERAGE_GFXCLK: 676 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 677 *value = metrics->AverageGfxclkFrequencyPreDs; 678 else 679 *value = metrics->AverageGfxclkFrequencyPostDs; 680 break; 681 case METRICS_AVERAGE_SOCCLK: 682 *value = metrics->AverageSocclkFrequency; 683 break; 684 case METRICS_AVERAGE_UCLK: 685 *value = metrics->AverageUclkFrequencyPostDs; 686 break; 687 case METRICS_AVERAGE_GFXACTIVITY: 688 *value = metrics->AverageGfxActivity; 689 break; 690 case METRICS_AVERAGE_MEMACTIVITY: 691 *value = metrics->AverageUclkActivity; 692 break; 693 case METRICS_AVERAGE_SOCKETPOWER: 694 *value = metrics->AverageSocketPower << 8; 695 break; 696 case METRICS_TEMPERATURE_EDGE: 697 *value = metrics->TemperatureEdge * 698 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 699 break; 700 case METRICS_TEMPERATURE_HOTSPOT: 701 *value = metrics->TemperatureHotspot * 702 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 703 break; 704 case METRICS_TEMPERATURE_MEM: 705 *value = metrics->TemperatureMem * 706 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 707 break; 708 case METRICS_TEMPERATURE_VRGFX: 709 *value = metrics->TemperatureVrGfx * 710 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 711 break; 712 case METRICS_TEMPERATURE_VRSOC: 713 *value = metrics->TemperatureVrSoc * 714 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 715 break; 716 case METRICS_THROTTLER_STATUS: 717 *value = metrics->ThrottlerStatus; 718 break; 719 case METRICS_CURR_FANSPEED: 720 *value = metrics->CurrFanSpeed; 721 break; 722 default: 723 *value = UINT_MAX; 724 break; 725 } 726 727 return ret; 728 } 729 730 static int navi12_get_legacy_smu_metrics_data(struct smu_context *smu, 731 MetricsMember_t member, 732 uint32_t *value) 733 { 734 struct smu_table_context *smu_table = &smu->smu_table; 735 SmuMetrics_NV12_legacy_t *metrics = 736 (SmuMetrics_NV12_legacy_t *)smu_table->metrics_table; 737 int ret = 0; 738 739 ret = smu_cmn_get_metrics_table(smu, 740 NULL, 741 false); 742 if (ret) 743 return ret; 744 745 switch (member) { 746 case METRICS_CURR_GFXCLK: 747 *value = metrics->CurrClock[PPCLK_GFXCLK]; 748 break; 749 case METRICS_CURR_SOCCLK: 750 *value = metrics->CurrClock[PPCLK_SOCCLK]; 751 break; 752 case METRICS_CURR_UCLK: 753 *value = metrics->CurrClock[PPCLK_UCLK]; 754 break; 755 case METRICS_CURR_VCLK: 756 *value = metrics->CurrClock[PPCLK_VCLK]; 757 break; 758 case METRICS_CURR_DCLK: 759 *value = metrics->CurrClock[PPCLK_DCLK]; 760 break; 761 case METRICS_CURR_DCEFCLK: 762 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 763 break; 764 case METRICS_AVERAGE_GFXCLK: 765 *value = metrics->AverageGfxclkFrequency; 766 break; 767 case METRICS_AVERAGE_SOCCLK: 768 *value = metrics->AverageSocclkFrequency; 769 break; 770 case METRICS_AVERAGE_UCLK: 771 *value = metrics->AverageUclkFrequency; 772 break; 773 case METRICS_AVERAGE_GFXACTIVITY: 774 *value = metrics->AverageGfxActivity; 775 break; 776 case METRICS_AVERAGE_MEMACTIVITY: 777 *value = metrics->AverageUclkActivity; 778 break; 779 case METRICS_AVERAGE_SOCKETPOWER: 780 *value = metrics->AverageSocketPower << 8; 781 break; 782 case METRICS_TEMPERATURE_EDGE: 783 *value = metrics->TemperatureEdge * 784 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 785 break; 786 case METRICS_TEMPERATURE_HOTSPOT: 787 *value = metrics->TemperatureHotspot * 788 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 789 break; 790 case METRICS_TEMPERATURE_MEM: 791 *value = metrics->TemperatureMem * 792 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 793 break; 794 case METRICS_TEMPERATURE_VRGFX: 795 *value = metrics->TemperatureVrGfx * 796 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 797 break; 798 case METRICS_TEMPERATURE_VRSOC: 799 *value = metrics->TemperatureVrSoc * 800 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 801 break; 802 case METRICS_THROTTLER_STATUS: 803 *value = metrics->ThrottlerStatus; 804 break; 805 case METRICS_CURR_FANSPEED: 806 *value = metrics->CurrFanSpeed; 807 break; 808 default: 809 *value = UINT_MAX; 810 break; 811 } 812 813 return ret; 814 } 815 816 static int navi12_get_smu_metrics_data(struct smu_context *smu, 817 MetricsMember_t member, 818 uint32_t *value) 819 { 820 struct smu_table_context *smu_table = &smu->smu_table; 821 SmuMetrics_NV12_t *metrics = 822 (SmuMetrics_NV12_t *)smu_table->metrics_table; 823 int ret = 0; 824 825 ret = smu_cmn_get_metrics_table(smu, 826 NULL, 827 false); 828 if (ret) 829 return ret; 830 831 switch (member) { 832 case METRICS_CURR_GFXCLK: 833 *value = metrics->CurrClock[PPCLK_GFXCLK]; 834 break; 835 case METRICS_CURR_SOCCLK: 836 *value = metrics->CurrClock[PPCLK_SOCCLK]; 837 break; 838 case METRICS_CURR_UCLK: 839 *value = metrics->CurrClock[PPCLK_UCLK]; 840 break; 841 case METRICS_CURR_VCLK: 842 *value = metrics->CurrClock[PPCLK_VCLK]; 843 break; 844 case METRICS_CURR_DCLK: 845 *value = metrics->CurrClock[PPCLK_DCLK]; 846 break; 847 case METRICS_CURR_DCEFCLK: 848 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 849 break; 850 case METRICS_AVERAGE_GFXCLK: 851 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 852 *value = metrics->AverageGfxclkFrequencyPreDs; 853 else 854 *value = metrics->AverageGfxclkFrequencyPostDs; 855 break; 856 case METRICS_AVERAGE_SOCCLK: 857 *value = metrics->AverageSocclkFrequency; 858 break; 859 case METRICS_AVERAGE_UCLK: 860 *value = metrics->AverageUclkFrequencyPostDs; 861 break; 862 case METRICS_AVERAGE_GFXACTIVITY: 863 *value = metrics->AverageGfxActivity; 864 break; 865 case METRICS_AVERAGE_MEMACTIVITY: 866 *value = metrics->AverageUclkActivity; 867 break; 868 case METRICS_AVERAGE_SOCKETPOWER: 869 *value = metrics->AverageSocketPower << 8; 870 break; 871 case METRICS_TEMPERATURE_EDGE: 872 *value = metrics->TemperatureEdge * 873 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 874 break; 875 case METRICS_TEMPERATURE_HOTSPOT: 876 *value = metrics->TemperatureHotspot * 877 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 878 break; 879 case METRICS_TEMPERATURE_MEM: 880 *value = metrics->TemperatureMem * 881 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 882 break; 883 case METRICS_TEMPERATURE_VRGFX: 884 *value = metrics->TemperatureVrGfx * 885 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 886 break; 887 case METRICS_TEMPERATURE_VRSOC: 888 *value = metrics->TemperatureVrSoc * 889 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 890 break; 891 case METRICS_THROTTLER_STATUS: 892 *value = metrics->ThrottlerStatus; 893 break; 894 case METRICS_CURR_FANSPEED: 895 *value = metrics->CurrFanSpeed; 896 break; 897 default: 898 *value = UINT_MAX; 899 break; 900 } 901 902 return ret; 903 } 904 905 static int navi1x_get_smu_metrics_data(struct smu_context *smu, 906 MetricsMember_t member, 907 uint32_t *value) 908 { 909 struct amdgpu_device *adev = smu->adev; 910 uint32_t smu_version; 911 int ret = 0; 912 913 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 914 if (ret) { 915 dev_err(adev->dev, "Failed to get smu version!\n"); 916 return ret; 917 } 918 919 switch (adev->ip_versions[MP1_HWIP][0]) { 920 case IP_VERSION(11, 0, 9): 921 if (smu_version > 0x00341C00) 922 ret = navi12_get_smu_metrics_data(smu, member, value); 923 else 924 ret = navi12_get_legacy_smu_metrics_data(smu, member, value); 925 break; 926 case IP_VERSION(11, 0, 0): 927 case IP_VERSION(11, 0, 5): 928 default: 929 if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) || 930 ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00)) 931 ret = navi10_get_smu_metrics_data(smu, member, value); 932 else 933 ret = navi10_get_legacy_smu_metrics_data(smu, member, value); 934 break; 935 } 936 937 return ret; 938 } 939 940 static int navi10_allocate_dpm_context(struct smu_context *smu) 941 { 942 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 943 944 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 945 GFP_KERNEL); 946 if (!smu_dpm->dpm_context) 947 return -ENOMEM; 948 949 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 950 951 return 0; 952 } 953 954 static int navi10_init_smc_tables(struct smu_context *smu) 955 { 956 int ret = 0; 957 958 ret = navi10_tables_init(smu); 959 if (ret) 960 return ret; 961 962 ret = navi10_allocate_dpm_context(smu); 963 if (ret) 964 return ret; 965 966 return smu_v11_0_init_smc_tables(smu); 967 } 968 969 static int navi10_set_default_dpm_table(struct smu_context *smu) 970 { 971 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 972 PPTable_t *driver_ppt = smu->smu_table.driver_pptable; 973 struct smu_11_0_dpm_table *dpm_table; 974 int ret = 0; 975 976 /* socclk dpm table setup */ 977 dpm_table = &dpm_context->dpm_tables.soc_table; 978 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 979 ret = smu_v11_0_set_single_dpm_table(smu, 980 SMU_SOCCLK, 981 dpm_table); 982 if (ret) 983 return ret; 984 dpm_table->is_fine_grained = 985 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete; 986 } else { 987 dpm_table->count = 1; 988 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 989 dpm_table->dpm_levels[0].enabled = true; 990 dpm_table->min = dpm_table->dpm_levels[0].value; 991 dpm_table->max = dpm_table->dpm_levels[0].value; 992 } 993 994 /* gfxclk dpm table setup */ 995 dpm_table = &dpm_context->dpm_tables.gfx_table; 996 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 997 ret = smu_v11_0_set_single_dpm_table(smu, 998 SMU_GFXCLK, 999 dpm_table); 1000 if (ret) 1001 return ret; 1002 dpm_table->is_fine_grained = 1003 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete; 1004 } else { 1005 dpm_table->count = 1; 1006 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 1007 dpm_table->dpm_levels[0].enabled = true; 1008 dpm_table->min = dpm_table->dpm_levels[0].value; 1009 dpm_table->max = dpm_table->dpm_levels[0].value; 1010 } 1011 1012 /* uclk dpm table setup */ 1013 dpm_table = &dpm_context->dpm_tables.uclk_table; 1014 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1015 ret = smu_v11_0_set_single_dpm_table(smu, 1016 SMU_UCLK, 1017 dpm_table); 1018 if (ret) 1019 return ret; 1020 dpm_table->is_fine_grained = 1021 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete; 1022 } else { 1023 dpm_table->count = 1; 1024 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 1025 dpm_table->dpm_levels[0].enabled = true; 1026 dpm_table->min = dpm_table->dpm_levels[0].value; 1027 dpm_table->max = dpm_table->dpm_levels[0].value; 1028 } 1029 1030 /* vclk dpm table setup */ 1031 dpm_table = &dpm_context->dpm_tables.vclk_table; 1032 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1033 ret = smu_v11_0_set_single_dpm_table(smu, 1034 SMU_VCLK, 1035 dpm_table); 1036 if (ret) 1037 return ret; 1038 dpm_table->is_fine_grained = 1039 !driver_ppt->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete; 1040 } else { 1041 dpm_table->count = 1; 1042 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; 1043 dpm_table->dpm_levels[0].enabled = true; 1044 dpm_table->min = dpm_table->dpm_levels[0].value; 1045 dpm_table->max = dpm_table->dpm_levels[0].value; 1046 } 1047 1048 /* dclk dpm table setup */ 1049 dpm_table = &dpm_context->dpm_tables.dclk_table; 1050 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1051 ret = smu_v11_0_set_single_dpm_table(smu, 1052 SMU_DCLK, 1053 dpm_table); 1054 if (ret) 1055 return ret; 1056 dpm_table->is_fine_grained = 1057 !driver_ppt->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete; 1058 } else { 1059 dpm_table->count = 1; 1060 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; 1061 dpm_table->dpm_levels[0].enabled = true; 1062 dpm_table->min = dpm_table->dpm_levels[0].value; 1063 dpm_table->max = dpm_table->dpm_levels[0].value; 1064 } 1065 1066 /* dcefclk dpm table setup */ 1067 dpm_table = &dpm_context->dpm_tables.dcef_table; 1068 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1069 ret = smu_v11_0_set_single_dpm_table(smu, 1070 SMU_DCEFCLK, 1071 dpm_table); 1072 if (ret) 1073 return ret; 1074 dpm_table->is_fine_grained = 1075 !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete; 1076 } else { 1077 dpm_table->count = 1; 1078 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1079 dpm_table->dpm_levels[0].enabled = true; 1080 dpm_table->min = dpm_table->dpm_levels[0].value; 1081 dpm_table->max = dpm_table->dpm_levels[0].value; 1082 } 1083 1084 /* pixelclk dpm table setup */ 1085 dpm_table = &dpm_context->dpm_tables.pixel_table; 1086 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1087 ret = smu_v11_0_set_single_dpm_table(smu, 1088 SMU_PIXCLK, 1089 dpm_table); 1090 if (ret) 1091 return ret; 1092 dpm_table->is_fine_grained = 1093 !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete; 1094 } else { 1095 dpm_table->count = 1; 1096 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1097 dpm_table->dpm_levels[0].enabled = true; 1098 dpm_table->min = dpm_table->dpm_levels[0].value; 1099 dpm_table->max = dpm_table->dpm_levels[0].value; 1100 } 1101 1102 /* displayclk dpm table setup */ 1103 dpm_table = &dpm_context->dpm_tables.display_table; 1104 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1105 ret = smu_v11_0_set_single_dpm_table(smu, 1106 SMU_DISPCLK, 1107 dpm_table); 1108 if (ret) 1109 return ret; 1110 dpm_table->is_fine_grained = 1111 !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete; 1112 } else { 1113 dpm_table->count = 1; 1114 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1115 dpm_table->dpm_levels[0].enabled = true; 1116 dpm_table->min = dpm_table->dpm_levels[0].value; 1117 dpm_table->max = dpm_table->dpm_levels[0].value; 1118 } 1119 1120 /* phyclk dpm table setup */ 1121 dpm_table = &dpm_context->dpm_tables.phy_table; 1122 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1123 ret = smu_v11_0_set_single_dpm_table(smu, 1124 SMU_PHYCLK, 1125 dpm_table); 1126 if (ret) 1127 return ret; 1128 dpm_table->is_fine_grained = 1129 !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete; 1130 } else { 1131 dpm_table->count = 1; 1132 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1133 dpm_table->dpm_levels[0].enabled = true; 1134 dpm_table->min = dpm_table->dpm_levels[0].value; 1135 dpm_table->max = dpm_table->dpm_levels[0].value; 1136 } 1137 1138 return 0; 1139 } 1140 1141 static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 1142 { 1143 int ret = 0; 1144 1145 if (enable) { 1146 /* vcn dpm on is a prerequisite for vcn power gate messages */ 1147 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1148 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL); 1149 if (ret) 1150 return ret; 1151 } 1152 } else { 1153 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1154 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL); 1155 if (ret) 1156 return ret; 1157 } 1158 } 1159 1160 return ret; 1161 } 1162 1163 static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 1164 { 1165 int ret = 0; 1166 1167 if (enable) { 1168 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 1169 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerUpJpeg, NULL); 1170 if (ret) 1171 return ret; 1172 } 1173 } else { 1174 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 1175 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL); 1176 if (ret) 1177 return ret; 1178 } 1179 } 1180 1181 return ret; 1182 } 1183 1184 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu, 1185 enum smu_clk_type clk_type, 1186 uint32_t *value) 1187 { 1188 MetricsMember_t member_type; 1189 int clk_id = 0; 1190 1191 clk_id = smu_cmn_to_asic_specific_index(smu, 1192 CMN2ASIC_MAPPING_CLK, 1193 clk_type); 1194 if (clk_id < 0) 1195 return clk_id; 1196 1197 switch (clk_id) { 1198 case PPCLK_GFXCLK: 1199 member_type = METRICS_CURR_GFXCLK; 1200 break; 1201 case PPCLK_UCLK: 1202 member_type = METRICS_CURR_UCLK; 1203 break; 1204 case PPCLK_SOCCLK: 1205 member_type = METRICS_CURR_SOCCLK; 1206 break; 1207 case PPCLK_VCLK: 1208 member_type = METRICS_CURR_VCLK; 1209 break; 1210 case PPCLK_DCLK: 1211 member_type = METRICS_CURR_DCLK; 1212 break; 1213 case PPCLK_DCEFCLK: 1214 member_type = METRICS_CURR_DCEFCLK; 1215 break; 1216 default: 1217 return -EINVAL; 1218 } 1219 1220 return navi1x_get_smu_metrics_data(smu, 1221 member_type, 1222 value); 1223 } 1224 1225 static int navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) 1226 { 1227 PPTable_t *pptable = smu->smu_table.driver_pptable; 1228 DpmDescriptor_t *dpm_desc = NULL; 1229 int clk_index = 0; 1230 1231 clk_index = smu_cmn_to_asic_specific_index(smu, 1232 CMN2ASIC_MAPPING_CLK, 1233 clk_type); 1234 if (clk_index < 0) 1235 return clk_index; 1236 1237 dpm_desc = &pptable->DpmDescriptor[clk_index]; 1238 1239 /* 0 - Fine grained DPM, 1 - Discrete DPM */ 1240 return dpm_desc->SnapToDiscrete == 0 ? 1 : 0; 1241 } 1242 1243 static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap) 1244 { 1245 return od_table->cap[cap]; 1246 } 1247 1248 static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table, 1249 enum SMU_11_0_ODSETTING_ID setting, 1250 uint32_t *min, uint32_t *max) 1251 { 1252 if (min) 1253 *min = od_table->min[setting]; 1254 if (max) 1255 *max = od_table->max[setting]; 1256 } 1257 1258 static int navi10_emit_clk_levels(struct smu_context *smu, 1259 enum smu_clk_type clk_type, 1260 char *buf, 1261 int *offset) 1262 { 1263 uint16_t *curve_settings; 1264 int ret = 0; 1265 uint32_t cur_value = 0, value = 0; 1266 uint32_t freq_values[3] = {0}; 1267 uint32_t i, levels, mark_index = 0, count = 0; 1268 struct smu_table_context *table_context = &smu->smu_table; 1269 uint32_t gen_speed, lane_width; 1270 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1271 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1272 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable; 1273 OverDriveTable_t *od_table = 1274 (OverDriveTable_t *)table_context->overdrive_table; 1275 struct smu_11_0_overdrive_table *od_settings = smu->od_settings; 1276 uint32_t min_value, max_value; 1277 1278 switch (clk_type) { 1279 case SMU_GFXCLK: 1280 case SMU_SCLK: 1281 case SMU_SOCCLK: 1282 case SMU_MCLK: 1283 case SMU_UCLK: 1284 case SMU_FCLK: 1285 case SMU_VCLK: 1286 case SMU_DCLK: 1287 case SMU_DCEFCLK: 1288 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value); 1289 if (ret) 1290 return ret; 1291 1292 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); 1293 if (ret) 1294 return ret; 1295 1296 ret = navi10_is_support_fine_grained_dpm(smu, clk_type); 1297 if (ret < 0) 1298 return ret; 1299 1300 if (!ret) { 1301 for (i = 0; i < count; i++) { 1302 ret = smu_v11_0_get_dpm_freq_by_index(smu, 1303 clk_type, i, &value); 1304 if (ret) 1305 return ret; 1306 1307 *offset += sysfs_emit_at(buf, *offset, 1308 "%d: %uMhz %s\n", 1309 i, value, 1310 cur_value == value ? "*" : ""); 1311 } 1312 } else { 1313 ret = smu_v11_0_get_dpm_freq_by_index(smu, 1314 clk_type, 0, &freq_values[0]); 1315 if (ret) 1316 return ret; 1317 ret = smu_v11_0_get_dpm_freq_by_index(smu, 1318 clk_type, 1319 count - 1, 1320 &freq_values[2]); 1321 if (ret) 1322 return ret; 1323 1324 freq_values[1] = cur_value; 1325 mark_index = cur_value == freq_values[0] ? 0 : 1326 cur_value == freq_values[2] ? 2 : 1; 1327 1328 levels = 3; 1329 if (mark_index != 1) { 1330 levels = 2; 1331 freq_values[1] = freq_values[2]; 1332 } 1333 1334 for (i = 0; i < levels; i++) { 1335 *offset += sysfs_emit_at(buf, *offset, 1336 "%d: %uMhz %s\n", 1337 i, freq_values[i], 1338 i == mark_index ? "*" : ""); 1339 } 1340 } 1341 break; 1342 case SMU_PCIE: 1343 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); 1344 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); 1345 for (i = 0; i < NUM_LINK_LEVELS; i++) { 1346 *offset += sysfs_emit_at(buf, *offset, "%d: %s %s %dMhz %s\n", i, 1347 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," : 1348 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," : 1349 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," : 1350 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "", 1351 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" : 1352 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" : 1353 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" : 1354 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" : 1355 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" : 1356 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "", 1357 pptable->LclkFreq[i], 1358 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && 1359 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? 1360 "*" : ""); 1361 } 1362 break; 1363 case SMU_OD_SCLK: 1364 if (!smu->od_enabled || !od_table || !od_settings) 1365 return -EOPNOTSUPP; 1366 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) 1367 break; 1368 *offset += sysfs_emit_at(buf, *offset, "OD_SCLK:\n0: %uMhz\n1: %uMhz\n", 1369 od_table->GfxclkFmin, od_table->GfxclkFmax); 1370 break; 1371 case SMU_OD_MCLK: 1372 if (!smu->od_enabled || !od_table || !od_settings) 1373 return -EOPNOTSUPP; 1374 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) 1375 break; 1376 *offset += sysfs_emit_at(buf, *offset, "OD_MCLK:\n1: %uMHz\n", od_table->UclkFmax); 1377 break; 1378 case SMU_OD_VDDC_CURVE: 1379 if (!smu->od_enabled || !od_table || !od_settings) 1380 return -EOPNOTSUPP; 1381 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) 1382 break; 1383 *offset += sysfs_emit_at(buf, *offset, "OD_VDDC_CURVE:\n"); 1384 for (i = 0; i < 3; i++) { 1385 switch (i) { 1386 case 0: 1387 curve_settings = &od_table->GfxclkFreq1; 1388 break; 1389 case 1: 1390 curve_settings = &od_table->GfxclkFreq2; 1391 break; 1392 case 2: 1393 curve_settings = &od_table->GfxclkFreq3; 1394 break; 1395 default: 1396 break; 1397 } 1398 *offset += sysfs_emit_at(buf, *offset, "%d: %uMHz %umV\n", 1399 i, curve_settings[0], 1400 curve_settings[1] / NAVI10_VOLTAGE_SCALE); 1401 } 1402 break; 1403 case SMU_OD_RANGE: 1404 if (!smu->od_enabled || !od_table || !od_settings) 1405 return -EOPNOTSUPP; 1406 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_RANGE"); 1407 1408 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) { 1409 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN, 1410 &min_value, NULL); 1411 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX, 1412 NULL, &max_value); 1413 *offset += sysfs_emit_at(buf, *offset, "SCLK: %7uMhz %10uMhz\n", 1414 min_value, max_value); 1415 } 1416 1417 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) { 1418 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX, 1419 &min_value, &max_value); 1420 *offset += sysfs_emit_at(buf, *offset, "MCLK: %7uMhz %10uMhz\n", 1421 min_value, max_value); 1422 } 1423 1424 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) { 1425 navi10_od_setting_get_range(od_settings, 1426 SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1, 1427 &min_value, &max_value); 1428 *offset += sysfs_emit_at(buf, *offset, 1429 "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n", 1430 min_value, max_value); 1431 navi10_od_setting_get_range(od_settings, 1432 SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1, 1433 &min_value, &max_value); 1434 *offset += sysfs_emit_at(buf, *offset, 1435 "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n", 1436 min_value, max_value); 1437 navi10_od_setting_get_range(od_settings, 1438 SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2, 1439 &min_value, &max_value); 1440 *offset += sysfs_emit_at(buf, *offset, 1441 "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n", 1442 min_value, max_value); 1443 navi10_od_setting_get_range(od_settings, 1444 SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2, 1445 &min_value, &max_value); 1446 *offset += sysfs_emit_at(buf, *offset, 1447 "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n", 1448 min_value, max_value); 1449 navi10_od_setting_get_range(od_settings, 1450 SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3, 1451 &min_value, &max_value); 1452 *offset += sysfs_emit_at(buf, *offset, 1453 "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n", 1454 min_value, max_value); 1455 navi10_od_setting_get_range(od_settings, 1456 SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3, 1457 &min_value, &max_value); 1458 *offset += sysfs_emit_at(buf, *offset, 1459 "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n", 1460 min_value, max_value); 1461 } 1462 1463 break; 1464 default: 1465 break; 1466 } 1467 1468 return 0; 1469 } 1470 1471 static int navi10_print_clk_levels(struct smu_context *smu, 1472 enum smu_clk_type clk_type, char *buf) 1473 { 1474 uint16_t *curve_settings; 1475 int i, levels, size = 0, ret = 0; 1476 uint32_t cur_value = 0, value = 0, count = 0; 1477 uint32_t freq_values[3] = {0}; 1478 uint32_t mark_index = 0; 1479 struct smu_table_context *table_context = &smu->smu_table; 1480 uint32_t gen_speed, lane_width; 1481 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1482 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1483 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable; 1484 OverDriveTable_t *od_table = 1485 (OverDriveTable_t *)table_context->overdrive_table; 1486 struct smu_11_0_overdrive_table *od_settings = smu->od_settings; 1487 uint32_t min_value, max_value; 1488 1489 smu_cmn_get_sysfs_buf(&buf, &size); 1490 1491 switch (clk_type) { 1492 case SMU_GFXCLK: 1493 case SMU_SCLK: 1494 case SMU_SOCCLK: 1495 case SMU_MCLK: 1496 case SMU_UCLK: 1497 case SMU_FCLK: 1498 case SMU_VCLK: 1499 case SMU_DCLK: 1500 case SMU_DCEFCLK: 1501 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value); 1502 if (ret) 1503 return size; 1504 1505 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); 1506 if (ret) 1507 return size; 1508 1509 ret = navi10_is_support_fine_grained_dpm(smu, clk_type); 1510 if (ret < 0) 1511 return ret; 1512 1513 if (!ret) { 1514 for (i = 0; i < count; i++) { 1515 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); 1516 if (ret) 1517 return size; 1518 1519 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 1520 cur_value == value ? "*" : ""); 1521 } 1522 } else { 1523 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]); 1524 if (ret) 1525 return size; 1526 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]); 1527 if (ret) 1528 return size; 1529 1530 freq_values[1] = cur_value; 1531 mark_index = cur_value == freq_values[0] ? 0 : 1532 cur_value == freq_values[2] ? 2 : 1; 1533 1534 levels = 3; 1535 if (mark_index != 1) { 1536 levels = 2; 1537 freq_values[1] = freq_values[2]; 1538 } 1539 1540 for (i = 0; i < levels; i++) { 1541 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i], 1542 i == mark_index ? "*" : ""); 1543 } 1544 } 1545 break; 1546 case SMU_PCIE: 1547 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); 1548 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); 1549 for (i = 0; i < NUM_LINK_LEVELS; i++) 1550 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i, 1551 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," : 1552 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," : 1553 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," : 1554 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "", 1555 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" : 1556 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" : 1557 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" : 1558 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" : 1559 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" : 1560 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "", 1561 pptable->LclkFreq[i], 1562 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && 1563 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? 1564 "*" : ""); 1565 break; 1566 case SMU_OD_SCLK: 1567 if (!smu->od_enabled || !od_table || !od_settings) 1568 break; 1569 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) 1570 break; 1571 size += sysfs_emit_at(buf, size, "OD_SCLK:\n"); 1572 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", 1573 od_table->GfxclkFmin, od_table->GfxclkFmax); 1574 break; 1575 case SMU_OD_MCLK: 1576 if (!smu->od_enabled || !od_table || !od_settings) 1577 break; 1578 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) 1579 break; 1580 size += sysfs_emit_at(buf, size, "OD_MCLK:\n"); 1581 size += sysfs_emit_at(buf, size, "1: %uMHz\n", od_table->UclkFmax); 1582 break; 1583 case SMU_OD_VDDC_CURVE: 1584 if (!smu->od_enabled || !od_table || !od_settings) 1585 break; 1586 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) 1587 break; 1588 size += sysfs_emit_at(buf, size, "OD_VDDC_CURVE:\n"); 1589 for (i = 0; i < 3; i++) { 1590 switch (i) { 1591 case 0: 1592 curve_settings = &od_table->GfxclkFreq1; 1593 break; 1594 case 1: 1595 curve_settings = &od_table->GfxclkFreq2; 1596 break; 1597 case 2: 1598 curve_settings = &od_table->GfxclkFreq3; 1599 break; 1600 default: 1601 break; 1602 } 1603 size += sysfs_emit_at(buf, size, "%d: %uMHz %umV\n", 1604 i, curve_settings[0], 1605 curve_settings[1] / NAVI10_VOLTAGE_SCALE); 1606 } 1607 break; 1608 case SMU_OD_RANGE: 1609 if (!smu->od_enabled || !od_table || !od_settings) 1610 break; 1611 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 1612 1613 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) { 1614 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN, 1615 &min_value, NULL); 1616 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX, 1617 NULL, &max_value); 1618 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 1619 min_value, max_value); 1620 } 1621 1622 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) { 1623 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX, 1624 &min_value, &max_value); 1625 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n", 1626 min_value, max_value); 1627 } 1628 1629 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) { 1630 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1, 1631 &min_value, &max_value); 1632 size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n", 1633 min_value, max_value); 1634 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1, 1635 &min_value, &max_value); 1636 size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n", 1637 min_value, max_value); 1638 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2, 1639 &min_value, &max_value); 1640 size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n", 1641 min_value, max_value); 1642 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2, 1643 &min_value, &max_value); 1644 size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n", 1645 min_value, max_value); 1646 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3, 1647 &min_value, &max_value); 1648 size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n", 1649 min_value, max_value); 1650 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3, 1651 &min_value, &max_value); 1652 size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n", 1653 min_value, max_value); 1654 } 1655 1656 break; 1657 default: 1658 break; 1659 } 1660 1661 return size; 1662 } 1663 1664 static int navi10_force_clk_levels(struct smu_context *smu, 1665 enum smu_clk_type clk_type, uint32_t mask) 1666 { 1667 1668 int ret = 0; 1669 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; 1670 1671 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1672 soft_max_level = mask ? (fls(mask) - 1) : 0; 1673 1674 switch (clk_type) { 1675 case SMU_GFXCLK: 1676 case SMU_SCLK: 1677 case SMU_SOCCLK: 1678 case SMU_MCLK: 1679 case SMU_UCLK: 1680 case SMU_FCLK: 1681 /* There is only 2 levels for fine grained DPM */ 1682 ret = navi10_is_support_fine_grained_dpm(smu, clk_type); 1683 if (ret < 0) 1684 return ret; 1685 1686 if (ret) { 1687 soft_max_level = (soft_max_level >= 1 ? 1 : 0); 1688 soft_min_level = (soft_min_level >= 1 ? 1 : 0); 1689 } 1690 1691 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); 1692 if (ret) 1693 return 0; 1694 1695 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq); 1696 if (ret) 1697 return 0; 1698 1699 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 1700 if (ret) 1701 return 0; 1702 break; 1703 case SMU_DCEFCLK: 1704 dev_info(smu->adev->dev, "Setting DCEFCLK min/max dpm level is not supported!\n"); 1705 break; 1706 1707 default: 1708 break; 1709 } 1710 1711 return 0; 1712 } 1713 1714 static int navi10_populate_umd_state_clk(struct smu_context *smu) 1715 { 1716 struct smu_11_0_dpm_context *dpm_context = 1717 smu->smu_dpm.dpm_context; 1718 struct smu_11_0_dpm_table *gfx_table = 1719 &dpm_context->dpm_tables.gfx_table; 1720 struct smu_11_0_dpm_table *mem_table = 1721 &dpm_context->dpm_tables.uclk_table; 1722 struct smu_11_0_dpm_table *soc_table = 1723 &dpm_context->dpm_tables.soc_table; 1724 struct smu_umd_pstate_table *pstate_table = 1725 &smu->pstate_table; 1726 struct amdgpu_device *adev = smu->adev; 1727 uint32_t sclk_freq; 1728 1729 pstate_table->gfxclk_pstate.min = gfx_table->min; 1730 switch (adev->ip_versions[MP1_HWIP][0]) { 1731 case IP_VERSION(11, 0, 0): 1732 switch (adev->pdev->revision) { 1733 case 0xf0: /* XTX */ 1734 case 0xc0: 1735 sclk_freq = NAVI10_PEAK_SCLK_XTX; 1736 break; 1737 case 0xf1: /* XT */ 1738 case 0xc1: 1739 sclk_freq = NAVI10_PEAK_SCLK_XT; 1740 break; 1741 default: /* XL */ 1742 sclk_freq = NAVI10_PEAK_SCLK_XL; 1743 break; 1744 } 1745 break; 1746 case IP_VERSION(11, 0, 5): 1747 switch (adev->pdev->revision) { 1748 case 0xc7: /* XT */ 1749 case 0xf4: 1750 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK; 1751 break; 1752 case 0xc1: /* XTM */ 1753 case 0xf2: 1754 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK; 1755 break; 1756 case 0xc3: /* XLM */ 1757 case 0xf3: 1758 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK; 1759 break; 1760 case 0xc5: /* XTX */ 1761 case 0xf6: 1762 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK; 1763 break; 1764 default: /* XL */ 1765 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK; 1766 break; 1767 } 1768 break; 1769 case IP_VERSION(11, 0, 9): 1770 sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK; 1771 break; 1772 default: 1773 sclk_freq = gfx_table->dpm_levels[gfx_table->count - 1].value; 1774 break; 1775 } 1776 pstate_table->gfxclk_pstate.peak = sclk_freq; 1777 1778 pstate_table->uclk_pstate.min = mem_table->min; 1779 pstate_table->uclk_pstate.peak = mem_table->max; 1780 1781 pstate_table->socclk_pstate.min = soc_table->min; 1782 pstate_table->socclk_pstate.peak = soc_table->max; 1783 1784 if (gfx_table->max > NAVI10_UMD_PSTATE_PROFILING_GFXCLK && 1785 mem_table->max > NAVI10_UMD_PSTATE_PROFILING_MEMCLK && 1786 soc_table->max > NAVI10_UMD_PSTATE_PROFILING_SOCCLK) { 1787 pstate_table->gfxclk_pstate.standard = 1788 NAVI10_UMD_PSTATE_PROFILING_GFXCLK; 1789 pstate_table->uclk_pstate.standard = 1790 NAVI10_UMD_PSTATE_PROFILING_MEMCLK; 1791 pstate_table->socclk_pstate.standard = 1792 NAVI10_UMD_PSTATE_PROFILING_SOCCLK; 1793 } else { 1794 pstate_table->gfxclk_pstate.standard = 1795 pstate_table->gfxclk_pstate.min; 1796 pstate_table->uclk_pstate.standard = 1797 pstate_table->uclk_pstate.min; 1798 pstate_table->socclk_pstate.standard = 1799 pstate_table->socclk_pstate.min; 1800 } 1801 1802 return 0; 1803 } 1804 1805 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu, 1806 enum smu_clk_type clk_type, 1807 struct pp_clock_levels_with_latency *clocks) 1808 { 1809 int ret = 0, i = 0; 1810 uint32_t level_count = 0, freq = 0; 1811 1812 switch (clk_type) { 1813 case SMU_GFXCLK: 1814 case SMU_DCEFCLK: 1815 case SMU_SOCCLK: 1816 case SMU_MCLK: 1817 case SMU_UCLK: 1818 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &level_count); 1819 if (ret) 1820 return ret; 1821 1822 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS); 1823 clocks->num_levels = level_count; 1824 1825 for (i = 0; i < level_count; i++) { 1826 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &freq); 1827 if (ret) 1828 return ret; 1829 1830 clocks->data[i].clocks_in_khz = freq * 1000; 1831 clocks->data[i].latency_in_us = 0; 1832 } 1833 break; 1834 default: 1835 break; 1836 } 1837 1838 return ret; 1839 } 1840 1841 static int navi10_pre_display_config_changed(struct smu_context *smu) 1842 { 1843 int ret = 0; 1844 uint32_t max_freq = 0; 1845 1846 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL); 1847 if (ret) 1848 return ret; 1849 1850 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1851 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq); 1852 if (ret) 1853 return ret; 1854 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq); 1855 if (ret) 1856 return ret; 1857 } 1858 1859 return ret; 1860 } 1861 1862 static int navi10_display_config_changed(struct smu_context *smu) 1863 { 1864 int ret = 0; 1865 1866 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1867 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) && 1868 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 1869 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 1870 smu->display_config->num_display, 1871 NULL); 1872 if (ret) 1873 return ret; 1874 } 1875 1876 return ret; 1877 } 1878 1879 static bool navi10_is_dpm_running(struct smu_context *smu) 1880 { 1881 int ret = 0; 1882 uint64_t feature_enabled; 1883 1884 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 1885 if (ret) 1886 return false; 1887 1888 return !!(feature_enabled & SMC_DPM_FEATURE); 1889 } 1890 1891 static int navi10_get_fan_speed_rpm(struct smu_context *smu, 1892 uint32_t *speed) 1893 { 1894 int ret = 0; 1895 1896 if (!speed) 1897 return -EINVAL; 1898 1899 switch (smu_v11_0_get_fan_control_mode(smu)) { 1900 case AMD_FAN_CTRL_AUTO: 1901 ret = navi10_get_smu_metrics_data(smu, 1902 METRICS_CURR_FANSPEED, 1903 speed); 1904 break; 1905 default: 1906 ret = smu_v11_0_get_fan_speed_rpm(smu, 1907 speed); 1908 break; 1909 } 1910 1911 return ret; 1912 } 1913 1914 static int navi10_get_fan_parameters(struct smu_context *smu) 1915 { 1916 PPTable_t *pptable = smu->smu_table.driver_pptable; 1917 1918 smu->fan_max_rpm = pptable->FanMaximumRpm; 1919 1920 return 0; 1921 } 1922 1923 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf) 1924 { 1925 DpmActivityMonitorCoeffInt_t activity_monitor; 1926 uint32_t i, size = 0; 1927 int16_t workload_type = 0; 1928 static const char *title[] = { 1929 "PROFILE_INDEX(NAME)", 1930 "CLOCK_TYPE(NAME)", 1931 "FPS", 1932 "MinFreqType", 1933 "MinActiveFreqType", 1934 "MinActiveFreq", 1935 "BoosterFreqType", 1936 "BoosterFreq", 1937 "PD_Data_limit_c", 1938 "PD_Data_error_coeff", 1939 "PD_Data_error_rate_coeff"}; 1940 int result = 0; 1941 1942 if (!buf) 1943 return -EINVAL; 1944 1945 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n", 1946 title[0], title[1], title[2], title[3], title[4], title[5], 1947 title[6], title[7], title[8], title[9], title[10]); 1948 1949 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1950 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1951 workload_type = smu_cmn_to_asic_specific_index(smu, 1952 CMN2ASIC_MAPPING_WORKLOAD, 1953 i); 1954 if (workload_type < 0) 1955 return -EINVAL; 1956 1957 result = smu_cmn_update_table(smu, 1958 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type, 1959 (void *)(&activity_monitor), false); 1960 if (result) { 1961 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1962 return result; 1963 } 1964 1965 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n", 1966 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1967 1968 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1969 " ", 1970 0, 1971 "GFXCLK", 1972 activity_monitor.Gfx_FPS, 1973 activity_monitor.Gfx_MinFreqStep, 1974 activity_monitor.Gfx_MinActiveFreqType, 1975 activity_monitor.Gfx_MinActiveFreq, 1976 activity_monitor.Gfx_BoosterFreqType, 1977 activity_monitor.Gfx_BoosterFreq, 1978 activity_monitor.Gfx_PD_Data_limit_c, 1979 activity_monitor.Gfx_PD_Data_error_coeff, 1980 activity_monitor.Gfx_PD_Data_error_rate_coeff); 1981 1982 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1983 " ", 1984 1, 1985 "SOCCLK", 1986 activity_monitor.Soc_FPS, 1987 activity_monitor.Soc_MinFreqStep, 1988 activity_monitor.Soc_MinActiveFreqType, 1989 activity_monitor.Soc_MinActiveFreq, 1990 activity_monitor.Soc_BoosterFreqType, 1991 activity_monitor.Soc_BoosterFreq, 1992 activity_monitor.Soc_PD_Data_limit_c, 1993 activity_monitor.Soc_PD_Data_error_coeff, 1994 activity_monitor.Soc_PD_Data_error_rate_coeff); 1995 1996 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1997 " ", 1998 2, 1999 "MEMLK", 2000 activity_monitor.Mem_FPS, 2001 activity_monitor.Mem_MinFreqStep, 2002 activity_monitor.Mem_MinActiveFreqType, 2003 activity_monitor.Mem_MinActiveFreq, 2004 activity_monitor.Mem_BoosterFreqType, 2005 activity_monitor.Mem_BoosterFreq, 2006 activity_monitor.Mem_PD_Data_limit_c, 2007 activity_monitor.Mem_PD_Data_error_coeff, 2008 activity_monitor.Mem_PD_Data_error_rate_coeff); 2009 } 2010 2011 return size; 2012 } 2013 2014 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 2015 { 2016 DpmActivityMonitorCoeffInt_t activity_monitor; 2017 int workload_type, ret = 0; 2018 2019 smu->power_profile_mode = input[size]; 2020 2021 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 2022 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode); 2023 return -EINVAL; 2024 } 2025 2026 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 2027 2028 ret = smu_cmn_update_table(smu, 2029 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 2030 (void *)(&activity_monitor), false); 2031 if (ret) { 2032 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 2033 return ret; 2034 } 2035 2036 switch (input[0]) { 2037 case 0: /* Gfxclk */ 2038 activity_monitor.Gfx_FPS = input[1]; 2039 activity_monitor.Gfx_MinFreqStep = input[2]; 2040 activity_monitor.Gfx_MinActiveFreqType = input[3]; 2041 activity_monitor.Gfx_MinActiveFreq = input[4]; 2042 activity_monitor.Gfx_BoosterFreqType = input[5]; 2043 activity_monitor.Gfx_BoosterFreq = input[6]; 2044 activity_monitor.Gfx_PD_Data_limit_c = input[7]; 2045 activity_monitor.Gfx_PD_Data_error_coeff = input[8]; 2046 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9]; 2047 break; 2048 case 1: /* Socclk */ 2049 activity_monitor.Soc_FPS = input[1]; 2050 activity_monitor.Soc_MinFreqStep = input[2]; 2051 activity_monitor.Soc_MinActiveFreqType = input[3]; 2052 activity_monitor.Soc_MinActiveFreq = input[4]; 2053 activity_monitor.Soc_BoosterFreqType = input[5]; 2054 activity_monitor.Soc_BoosterFreq = input[6]; 2055 activity_monitor.Soc_PD_Data_limit_c = input[7]; 2056 activity_monitor.Soc_PD_Data_error_coeff = input[8]; 2057 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9]; 2058 break; 2059 case 2: /* Memlk */ 2060 activity_monitor.Mem_FPS = input[1]; 2061 activity_monitor.Mem_MinFreqStep = input[2]; 2062 activity_monitor.Mem_MinActiveFreqType = input[3]; 2063 activity_monitor.Mem_MinActiveFreq = input[4]; 2064 activity_monitor.Mem_BoosterFreqType = input[5]; 2065 activity_monitor.Mem_BoosterFreq = input[6]; 2066 activity_monitor.Mem_PD_Data_limit_c = input[7]; 2067 activity_monitor.Mem_PD_Data_error_coeff = input[8]; 2068 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9]; 2069 break; 2070 } 2071 2072 ret = smu_cmn_update_table(smu, 2073 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 2074 (void *)(&activity_monitor), true); 2075 if (ret) { 2076 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 2077 return ret; 2078 } 2079 } 2080 2081 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 2082 workload_type = smu_cmn_to_asic_specific_index(smu, 2083 CMN2ASIC_MAPPING_WORKLOAD, 2084 smu->power_profile_mode); 2085 if (workload_type < 0) 2086 return -EINVAL; 2087 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 2088 1 << workload_type, NULL); 2089 2090 return ret; 2091 } 2092 2093 static int navi10_notify_smc_display_config(struct smu_context *smu) 2094 { 2095 struct smu_clocks min_clocks = {0}; 2096 struct pp_display_clock_request clock_req; 2097 int ret = 0; 2098 2099 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; 2100 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; 2101 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; 2102 2103 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 2104 clock_req.clock_type = amd_pp_dcef_clock; 2105 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; 2106 2107 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req); 2108 if (!ret) { 2109 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) { 2110 ret = smu_cmn_send_smc_msg_with_param(smu, 2111 SMU_MSG_SetMinDeepSleepDcefclk, 2112 min_clocks.dcef_clock_in_sr/100, 2113 NULL); 2114 if (ret) { 2115 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!"); 2116 return ret; 2117 } 2118 } 2119 } else { 2120 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!"); 2121 } 2122 } 2123 2124 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 2125 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); 2126 if (ret) { 2127 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__); 2128 return ret; 2129 } 2130 } 2131 2132 return 0; 2133 } 2134 2135 static int navi10_set_watermarks_table(struct smu_context *smu, 2136 struct pp_smu_wm_range_sets *clock_ranges) 2137 { 2138 Watermarks_t *table = smu->smu_table.watermarks_table; 2139 int ret = 0; 2140 int i; 2141 2142 if (clock_ranges) { 2143 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 2144 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 2145 return -EINVAL; 2146 2147 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 2148 table->WatermarkRow[WM_DCEFCLK][i].MinClock = 2149 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 2150 table->WatermarkRow[WM_DCEFCLK][i].MaxClock = 2151 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 2152 table->WatermarkRow[WM_DCEFCLK][i].MinUclk = 2153 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 2154 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk = 2155 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 2156 2157 table->WatermarkRow[WM_DCEFCLK][i].WmSetting = 2158 clock_ranges->reader_wm_sets[i].wm_inst; 2159 } 2160 2161 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 2162 table->WatermarkRow[WM_SOCCLK][i].MinClock = 2163 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 2164 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 2165 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 2166 table->WatermarkRow[WM_SOCCLK][i].MinUclk = 2167 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 2168 table->WatermarkRow[WM_SOCCLK][i].MaxUclk = 2169 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 2170 2171 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 2172 clock_ranges->writer_wm_sets[i].wm_inst; 2173 } 2174 2175 smu->watermarks_bitmap |= WATERMARKS_EXIST; 2176 } 2177 2178 /* pass data to smu controller */ 2179 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 2180 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 2181 ret = smu_cmn_write_watermarks_table(smu); 2182 if (ret) { 2183 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 2184 return ret; 2185 } 2186 smu->watermarks_bitmap |= WATERMARKS_LOADED; 2187 } 2188 2189 return 0; 2190 } 2191 2192 static int navi10_read_sensor(struct smu_context *smu, 2193 enum amd_pp_sensors sensor, 2194 void *data, uint32_t *size) 2195 { 2196 int ret = 0; 2197 struct smu_table_context *table_context = &smu->smu_table; 2198 PPTable_t *pptable = table_context->driver_pptable; 2199 2200 if (!data || !size) 2201 return -EINVAL; 2202 2203 switch (sensor) { 2204 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 2205 *(uint32_t *)data = pptable->FanMaximumRpm; 2206 *size = 4; 2207 break; 2208 case AMDGPU_PP_SENSOR_MEM_LOAD: 2209 ret = navi1x_get_smu_metrics_data(smu, 2210 METRICS_AVERAGE_MEMACTIVITY, 2211 (uint32_t *)data); 2212 *size = 4; 2213 break; 2214 case AMDGPU_PP_SENSOR_GPU_LOAD: 2215 ret = navi1x_get_smu_metrics_data(smu, 2216 METRICS_AVERAGE_GFXACTIVITY, 2217 (uint32_t *)data); 2218 *size = 4; 2219 break; 2220 case AMDGPU_PP_SENSOR_GPU_AVG_POWER: 2221 ret = navi1x_get_smu_metrics_data(smu, 2222 METRICS_AVERAGE_SOCKETPOWER, 2223 (uint32_t *)data); 2224 *size = 4; 2225 break; 2226 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 2227 ret = navi1x_get_smu_metrics_data(smu, 2228 METRICS_TEMPERATURE_HOTSPOT, 2229 (uint32_t *)data); 2230 *size = 4; 2231 break; 2232 case AMDGPU_PP_SENSOR_EDGE_TEMP: 2233 ret = navi1x_get_smu_metrics_data(smu, 2234 METRICS_TEMPERATURE_EDGE, 2235 (uint32_t *)data); 2236 *size = 4; 2237 break; 2238 case AMDGPU_PP_SENSOR_MEM_TEMP: 2239 ret = navi1x_get_smu_metrics_data(smu, 2240 METRICS_TEMPERATURE_MEM, 2241 (uint32_t *)data); 2242 *size = 4; 2243 break; 2244 case AMDGPU_PP_SENSOR_GFX_MCLK: 2245 ret = navi10_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 2246 *(uint32_t *)data *= 100; 2247 *size = 4; 2248 break; 2249 case AMDGPU_PP_SENSOR_GFX_SCLK: 2250 ret = navi1x_get_smu_metrics_data(smu, METRICS_AVERAGE_GFXCLK, (uint32_t *)data); 2251 *(uint32_t *)data *= 100; 2252 *size = 4; 2253 break; 2254 case AMDGPU_PP_SENSOR_VDDGFX: 2255 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data); 2256 *size = 4; 2257 break; 2258 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: 2259 default: 2260 ret = -EOPNOTSUPP; 2261 break; 2262 } 2263 2264 return ret; 2265 } 2266 2267 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states) 2268 { 2269 uint32_t num_discrete_levels = 0; 2270 uint16_t *dpm_levels = NULL; 2271 uint16_t i = 0; 2272 struct smu_table_context *table_context = &smu->smu_table; 2273 PPTable_t *driver_ppt = NULL; 2274 2275 if (!clocks_in_khz || !num_states || !table_context->driver_pptable) 2276 return -EINVAL; 2277 2278 driver_ppt = table_context->driver_pptable; 2279 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels; 2280 dpm_levels = driver_ppt->FreqTableUclk; 2281 2282 if (num_discrete_levels == 0 || dpm_levels == NULL) 2283 return -EINVAL; 2284 2285 *num_states = num_discrete_levels; 2286 for (i = 0; i < num_discrete_levels; i++) { 2287 /* convert to khz */ 2288 *clocks_in_khz = (*dpm_levels) * 1000; 2289 clocks_in_khz++; 2290 dpm_levels++; 2291 } 2292 2293 return 0; 2294 } 2295 2296 static int navi10_get_thermal_temperature_range(struct smu_context *smu, 2297 struct smu_temperature_range *range) 2298 { 2299 struct smu_table_context *table_context = &smu->smu_table; 2300 struct smu_11_0_powerplay_table *powerplay_table = 2301 table_context->power_play_table; 2302 PPTable_t *pptable = smu->smu_table.driver_pptable; 2303 2304 if (!range) 2305 return -EINVAL; 2306 2307 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range)); 2308 2309 range->max = pptable->TedgeLimit * 2310 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2311 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) * 2312 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2313 range->hotspot_crit_max = pptable->ThotspotLimit * 2314 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2315 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 2316 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2317 range->mem_crit_max = pptable->TmemLimit * 2318 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2319 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)* 2320 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2321 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 2322 2323 return 0; 2324 } 2325 2326 static int navi10_display_disable_memory_clock_switch(struct smu_context *smu, 2327 bool disable_memory_clock_switch) 2328 { 2329 int ret = 0; 2330 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks = 2331 (struct smu_11_0_max_sustainable_clocks *) 2332 smu->smu_table.max_sustainable_clocks; 2333 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal; 2334 uint32_t max_memory_clock = max_sustainable_clocks->uclock; 2335 2336 if (smu->disable_uclk_switch == disable_memory_clock_switch) 2337 return 0; 2338 2339 if (disable_memory_clock_switch) 2340 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0); 2341 else 2342 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0); 2343 2344 if (!ret) 2345 smu->disable_uclk_switch = disable_memory_clock_switch; 2346 2347 return ret; 2348 } 2349 2350 static int navi10_get_power_limit(struct smu_context *smu, 2351 uint32_t *current_power_limit, 2352 uint32_t *default_power_limit, 2353 uint32_t *max_power_limit) 2354 { 2355 struct smu_11_0_powerplay_table *powerplay_table = 2356 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table; 2357 struct smu_11_0_overdrive_table *od_settings = smu->od_settings; 2358 PPTable_t *pptable = smu->smu_table.driver_pptable; 2359 uint32_t power_limit, od_percent; 2360 2361 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) { 2362 /* the last hope to figure out the ppt limit */ 2363 if (!pptable) { 2364 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!"); 2365 return -EINVAL; 2366 } 2367 power_limit = 2368 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0]; 2369 } 2370 2371 if (current_power_limit) 2372 *current_power_limit = power_limit; 2373 if (default_power_limit) 2374 *default_power_limit = power_limit; 2375 2376 if (max_power_limit) { 2377 if (smu->od_enabled && 2378 navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) { 2379 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]); 2380 2381 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit); 2382 2383 power_limit *= (100 + od_percent); 2384 power_limit /= 100; 2385 } 2386 2387 *max_power_limit = power_limit; 2388 } 2389 2390 return 0; 2391 } 2392 2393 static int navi10_update_pcie_parameters(struct smu_context *smu, 2394 uint8_t pcie_gen_cap, 2395 uint8_t pcie_width_cap) 2396 { 2397 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 2398 PPTable_t *pptable = smu->smu_table.driver_pptable; 2399 uint32_t smu_pcie_arg; 2400 int ret, i; 2401 2402 /* lclk dpm table setup */ 2403 for (i = 0; i < MAX_PCIE_CONF; i++) { 2404 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i]; 2405 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i]; 2406 } 2407 2408 for (i = 0; i < NUM_LINK_LEVELS; i++) { 2409 smu_pcie_arg = (i << 16) | 2410 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) : 2411 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ? 2412 pptable->PcieLaneCount[i] : pcie_width_cap); 2413 ret = smu_cmn_send_smc_msg_with_param(smu, 2414 SMU_MSG_OverridePcieParameters, 2415 smu_pcie_arg, 2416 NULL); 2417 2418 if (ret) 2419 return ret; 2420 2421 if (pptable->PcieGenSpeed[i] > pcie_gen_cap) 2422 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap; 2423 if (pptable->PcieLaneCount[i] > pcie_width_cap) 2424 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap; 2425 } 2426 2427 return 0; 2428 } 2429 2430 static inline void navi10_dump_od_table(struct smu_context *smu, 2431 OverDriveTable_t *od_table) 2432 { 2433 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax); 2434 dev_dbg(smu->adev->dev, "OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1); 2435 dev_dbg(smu->adev->dev, "OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2); 2436 dev_dbg(smu->adev->dev, "OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3); 2437 dev_dbg(smu->adev->dev, "OD: UclkFmax: %d\n", od_table->UclkFmax); 2438 dev_dbg(smu->adev->dev, "OD: OverDrivePct: %d\n", od_table->OverDrivePct); 2439 } 2440 2441 static int navi10_od_setting_check_range(struct smu_context *smu, 2442 struct smu_11_0_overdrive_table *od_table, 2443 enum SMU_11_0_ODSETTING_ID setting, 2444 uint32_t value) 2445 { 2446 if (value < od_table->min[setting]) { 2447 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]); 2448 return -EINVAL; 2449 } 2450 if (value > od_table->max[setting]) { 2451 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]); 2452 return -EINVAL; 2453 } 2454 return 0; 2455 } 2456 2457 static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu, 2458 uint16_t *voltage, 2459 uint32_t freq) 2460 { 2461 uint32_t param = (freq & 0xFFFF) | (PPCLK_GFXCLK << 16); 2462 uint32_t value = 0; 2463 int ret; 2464 2465 ret = smu_cmn_send_smc_msg_with_param(smu, 2466 SMU_MSG_GetVoltageByDpm, 2467 param, 2468 &value); 2469 if (ret) { 2470 dev_err(smu->adev->dev, "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!"); 2471 return ret; 2472 } 2473 2474 *voltage = (uint16_t)value; 2475 2476 return 0; 2477 } 2478 2479 static int navi10_baco_enter(struct smu_context *smu) 2480 { 2481 struct amdgpu_device *adev = smu->adev; 2482 2483 /* 2484 * This aims the case below: 2485 * amdgpu driver loaded -> runpm suspend kicked -> sound driver loaded 2486 * 2487 * For NAVI10 and later ASICs, we rely on PMFW to handle the runpm. To 2488 * make that possible, PMFW needs to acknowledge the dstate transition 2489 * process for both gfx(function 0) and audio(function 1) function of 2490 * the ASIC. 2491 * 2492 * The PCI device's initial runpm status is RUNPM_SUSPENDED. So as the 2493 * device representing the audio function of the ASIC. And that means 2494 * even if the sound driver(snd_hda_intel) was not loaded yet, it's still 2495 * possible runpm suspend kicked on the ASIC. However without the dstate 2496 * transition notification from audio function, pmfw cannot handle the 2497 * BACO in/exit correctly. And that will cause driver hang on runpm 2498 * resuming. 2499 * 2500 * To address this, we revert to legacy message way(driver masters the 2501 * timing for BACO in/exit) on sound driver missing. 2502 */ 2503 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) 2504 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO); 2505 else 2506 return smu_v11_0_baco_enter(smu); 2507 } 2508 2509 static int navi10_baco_exit(struct smu_context *smu) 2510 { 2511 struct amdgpu_device *adev = smu->adev; 2512 2513 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) { 2514 /* Wait for PMFW handling for the Dstate change */ 2515 msleep(10); 2516 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS); 2517 } else { 2518 return smu_v11_0_baco_exit(smu); 2519 } 2520 } 2521 2522 static int navi10_set_default_od_settings(struct smu_context *smu) 2523 { 2524 OverDriveTable_t *od_table = 2525 (OverDriveTable_t *)smu->smu_table.overdrive_table; 2526 OverDriveTable_t *boot_od_table = 2527 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table; 2528 OverDriveTable_t *user_od_table = 2529 (OverDriveTable_t *)smu->smu_table.user_overdrive_table; 2530 int ret = 0; 2531 2532 /* 2533 * For S3/S4/Runpm resume, no need to setup those overdrive tables again as 2534 * - either they already have the default OD settings got during cold bootup 2535 * - or they have some user customized OD settings which cannot be overwritten 2536 */ 2537 if (smu->adev->in_suspend) 2538 return 0; 2539 2540 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)boot_od_table, false); 2541 if (ret) { 2542 dev_err(smu->adev->dev, "Failed to get overdrive table!\n"); 2543 return ret; 2544 } 2545 2546 if (!boot_od_table->GfxclkVolt1) { 2547 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu, 2548 &boot_od_table->GfxclkVolt1, 2549 boot_od_table->GfxclkFreq1); 2550 if (ret) 2551 return ret; 2552 } 2553 2554 if (!boot_od_table->GfxclkVolt2) { 2555 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu, 2556 &boot_od_table->GfxclkVolt2, 2557 boot_od_table->GfxclkFreq2); 2558 if (ret) 2559 return ret; 2560 } 2561 2562 if (!boot_od_table->GfxclkVolt3) { 2563 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu, 2564 &boot_od_table->GfxclkVolt3, 2565 boot_od_table->GfxclkFreq3); 2566 if (ret) 2567 return ret; 2568 } 2569 2570 navi10_dump_od_table(smu, boot_od_table); 2571 2572 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t)); 2573 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t)); 2574 2575 return 0; 2576 } 2577 2578 static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) 2579 { 2580 int i; 2581 int ret = 0; 2582 struct smu_table_context *table_context = &smu->smu_table; 2583 OverDriveTable_t *od_table; 2584 struct smu_11_0_overdrive_table *od_settings; 2585 enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting; 2586 uint16_t *freq_ptr, *voltage_ptr; 2587 od_table = (OverDriveTable_t *)table_context->overdrive_table; 2588 2589 if (!smu->od_enabled) { 2590 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n"); 2591 return -EINVAL; 2592 } 2593 2594 if (!smu->od_settings) { 2595 dev_err(smu->adev->dev, "OD board limits are not set!\n"); 2596 return -ENOENT; 2597 } 2598 2599 od_settings = smu->od_settings; 2600 2601 switch (type) { 2602 case PP_OD_EDIT_SCLK_VDDC_TABLE: 2603 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) { 2604 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n"); 2605 return -ENOTSUPP; 2606 } 2607 if (!table_context->overdrive_table) { 2608 dev_err(smu->adev->dev, "Overdrive is not initialized\n"); 2609 return -EINVAL; 2610 } 2611 for (i = 0; i < size; i += 2) { 2612 if (i + 2 > size) { 2613 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size); 2614 return -EINVAL; 2615 } 2616 switch (input[i]) { 2617 case 0: 2618 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN; 2619 freq_ptr = &od_table->GfxclkFmin; 2620 if (input[i + 1] > od_table->GfxclkFmax) { 2621 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n", 2622 input[i + 1], 2623 od_table->GfxclkFmin); 2624 return -EINVAL; 2625 } 2626 break; 2627 case 1: 2628 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX; 2629 freq_ptr = &od_table->GfxclkFmax; 2630 if (input[i + 1] < od_table->GfxclkFmin) { 2631 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n", 2632 input[i + 1], 2633 od_table->GfxclkFmax); 2634 return -EINVAL; 2635 } 2636 break; 2637 default: 2638 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]); 2639 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n"); 2640 return -EINVAL; 2641 } 2642 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[i + 1]); 2643 if (ret) 2644 return ret; 2645 *freq_ptr = input[i + 1]; 2646 } 2647 break; 2648 case PP_OD_EDIT_MCLK_VDDC_TABLE: 2649 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) { 2650 dev_warn(smu->adev->dev, "UCLK_MAX not supported!\n"); 2651 return -ENOTSUPP; 2652 } 2653 if (size < 2) { 2654 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size); 2655 return -EINVAL; 2656 } 2657 if (input[0] != 1) { 2658 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]); 2659 dev_info(smu->adev->dev, "Supported indices: [1:max]\n"); 2660 return -EINVAL; 2661 } 2662 ret = navi10_od_setting_check_range(smu, od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]); 2663 if (ret) 2664 return ret; 2665 od_table->UclkFmax = input[1]; 2666 break; 2667 case PP_OD_RESTORE_DEFAULT_TABLE: 2668 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) { 2669 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n"); 2670 return -EINVAL; 2671 } 2672 memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t)); 2673 break; 2674 case PP_OD_COMMIT_DPM_TABLE: 2675 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) { 2676 navi10_dump_od_table(smu, od_table); 2677 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true); 2678 if (ret) { 2679 dev_err(smu->adev->dev, "Failed to import overdrive table!\n"); 2680 return ret; 2681 } 2682 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t)); 2683 smu->user_dpm_profile.user_od = true; 2684 2685 if (!memcmp(table_context->user_overdrive_table, 2686 table_context->boot_overdrive_table, 2687 sizeof(OverDriveTable_t))) 2688 smu->user_dpm_profile.user_od = false; 2689 } 2690 break; 2691 case PP_OD_EDIT_VDDC_CURVE: 2692 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) { 2693 dev_warn(smu->adev->dev, "GFXCLK_CURVE not supported!\n"); 2694 return -ENOTSUPP; 2695 } 2696 if (size < 3) { 2697 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size); 2698 return -EINVAL; 2699 } 2700 if (!od_table) { 2701 dev_info(smu->adev->dev, "Overdrive is not initialized\n"); 2702 return -EINVAL; 2703 } 2704 2705 switch (input[0]) { 2706 case 0: 2707 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1; 2708 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1; 2709 freq_ptr = &od_table->GfxclkFreq1; 2710 voltage_ptr = &od_table->GfxclkVolt1; 2711 break; 2712 case 1: 2713 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2; 2714 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2; 2715 freq_ptr = &od_table->GfxclkFreq2; 2716 voltage_ptr = &od_table->GfxclkVolt2; 2717 break; 2718 case 2: 2719 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3; 2720 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3; 2721 freq_ptr = &od_table->GfxclkFreq3; 2722 voltage_ptr = &od_table->GfxclkVolt3; 2723 break; 2724 default: 2725 dev_info(smu->adev->dev, "Invalid VDDC_CURVE index: %ld\n", input[0]); 2726 dev_info(smu->adev->dev, "Supported indices: [0, 1, 2]\n"); 2727 return -EINVAL; 2728 } 2729 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[1]); 2730 if (ret) 2731 return ret; 2732 // Allow setting zero to disable the OverDrive VDDC curve 2733 if (input[2] != 0) { 2734 ret = navi10_od_setting_check_range(smu, od_settings, voltage_setting, input[2]); 2735 if (ret) 2736 return ret; 2737 *freq_ptr = input[1]; 2738 *voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE; 2739 dev_dbg(smu->adev->dev, "OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr); 2740 } else { 2741 // If setting 0, disable all voltage curve settings 2742 od_table->GfxclkVolt1 = 0; 2743 od_table->GfxclkVolt2 = 0; 2744 od_table->GfxclkVolt3 = 0; 2745 } 2746 navi10_dump_od_table(smu, od_table); 2747 break; 2748 default: 2749 return -ENOSYS; 2750 } 2751 return ret; 2752 } 2753 2754 static int navi10_run_btc(struct smu_context *smu) 2755 { 2756 int ret = 0; 2757 2758 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunBtc, NULL); 2759 if (ret) 2760 dev_err(smu->adev->dev, "RunBtc failed!\n"); 2761 2762 return ret; 2763 } 2764 2765 static bool navi10_need_umc_cdr_workaround(struct smu_context *smu) 2766 { 2767 struct amdgpu_device *adev = smu->adev; 2768 2769 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 2770 return false; 2771 2772 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0) || 2773 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) 2774 return true; 2775 2776 return false; 2777 } 2778 2779 static int navi10_umc_hybrid_cdr_workaround(struct smu_context *smu) 2780 { 2781 uint32_t uclk_count, uclk_min, uclk_max; 2782 int ret = 0; 2783 2784 /* This workaround can be applied only with uclk dpm enabled */ 2785 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 2786 return 0; 2787 2788 ret = smu_v11_0_get_dpm_level_count(smu, SMU_UCLK, &uclk_count); 2789 if (ret) 2790 return ret; 2791 2792 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)(uclk_count - 1), &uclk_max); 2793 if (ret) 2794 return ret; 2795 2796 /* 2797 * The NAVI10_UMC_HYBRID_CDR_WORKAROUND_UCLK_THRESHOLD is 750Mhz. 2798 * This workaround is needed only when the max uclk frequency 2799 * not greater than that. 2800 */ 2801 if (uclk_max > 0x2EE) 2802 return 0; 2803 2804 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)0, &uclk_min); 2805 if (ret) 2806 return ret; 2807 2808 /* Force UCLK out of the highest DPM */ 2809 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_min); 2810 if (ret) 2811 return ret; 2812 2813 /* Revert the UCLK Hardmax */ 2814 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_max); 2815 if (ret) 2816 return ret; 2817 2818 /* 2819 * In this case, SMU already disabled dummy pstate during enablement 2820 * of UCLK DPM, we have to re-enabled it. 2821 */ 2822 return smu_cmn_send_smc_msg(smu, SMU_MSG_DAL_ENABLE_DUMMY_PSTATE_CHANGE, NULL); 2823 } 2824 2825 static int navi10_set_dummy_pstates_table_location(struct smu_context *smu) 2826 { 2827 struct smu_table_context *smu_table = &smu->smu_table; 2828 struct smu_table *dummy_read_table = 2829 &smu_table->dummy_read_1_table; 2830 char *dummy_table = dummy_read_table->cpu_addr; 2831 int ret = 0; 2832 uint32_t i; 2833 2834 for (i = 0; i < 0x40000; i += 0x1000 * 2) { 2835 memcpy(dummy_table, &NoDbiPrbs7[0], 0x1000); 2836 dummy_table += 0x1000; 2837 memcpy(dummy_table, &DbiPrbs7[0], 0x1000); 2838 dummy_table += 0x1000; 2839 } 2840 2841 amdgpu_asic_flush_hdp(smu->adev, NULL); 2842 2843 ret = smu_cmn_send_smc_msg_with_param(smu, 2844 SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH, 2845 upper_32_bits(dummy_read_table->mc_address), 2846 NULL); 2847 if (ret) 2848 return ret; 2849 2850 return smu_cmn_send_smc_msg_with_param(smu, 2851 SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW, 2852 lower_32_bits(dummy_read_table->mc_address), 2853 NULL); 2854 } 2855 2856 static int navi10_run_umc_cdr_workaround(struct smu_context *smu) 2857 { 2858 struct amdgpu_device *adev = smu->adev; 2859 uint8_t umc_fw_greater_than_v136 = false; 2860 uint8_t umc_fw_disable_cdr = false; 2861 uint32_t pmfw_version; 2862 uint32_t param; 2863 int ret = 0; 2864 2865 if (!navi10_need_umc_cdr_workaround(smu)) 2866 return 0; 2867 2868 ret = smu_cmn_get_smc_version(smu, NULL, &pmfw_version); 2869 if (ret) { 2870 dev_err(adev->dev, "Failed to get smu version!\n"); 2871 return ret; 2872 } 2873 2874 /* 2875 * The messages below are only supported by Navi10 42.53.0 and later 2876 * PMFWs and Navi14 53.29.0 and later PMFWs. 2877 * - PPSMC_MSG_SetDriverDummyTableDramAddrHigh 2878 * - PPSMC_MSG_SetDriverDummyTableDramAddrLow 2879 * - PPSMC_MSG_GetUMCFWWA 2880 */ 2881 if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && (pmfw_version >= 0x2a3500)) || 2882 ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && (pmfw_version >= 0x351D00))) { 2883 ret = smu_cmn_send_smc_msg_with_param(smu, 2884 SMU_MSG_GET_UMC_FW_WA, 2885 0, 2886 ¶m); 2887 if (ret) 2888 return ret; 2889 2890 /* First bit indicates if the UMC f/w is above v137 */ 2891 umc_fw_greater_than_v136 = param & 0x1; 2892 2893 /* Second bit indicates if hybrid-cdr is disabled */ 2894 umc_fw_disable_cdr = param & 0x2; 2895 2896 /* w/a only allowed if UMC f/w is <= 136 */ 2897 if (umc_fw_greater_than_v136) 2898 return 0; 2899 2900 if (umc_fw_disable_cdr) { 2901 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) 2902 return navi10_umc_hybrid_cdr_workaround(smu); 2903 } else { 2904 return navi10_set_dummy_pstates_table_location(smu); 2905 } 2906 } else { 2907 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) 2908 return navi10_umc_hybrid_cdr_workaround(smu); 2909 } 2910 2911 return 0; 2912 } 2913 2914 static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu, 2915 void **table) 2916 { 2917 struct smu_table_context *smu_table = &smu->smu_table; 2918 struct gpu_metrics_v1_3 *gpu_metrics = 2919 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 2920 SmuMetrics_legacy_t metrics; 2921 int ret = 0; 2922 2923 ret = smu_cmn_get_metrics_table(smu, 2924 NULL, 2925 true); 2926 if (ret) 2927 return ret; 2928 2929 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_legacy_t)); 2930 2931 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 2932 2933 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 2934 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 2935 gpu_metrics->temperature_mem = metrics.TemperatureMem; 2936 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 2937 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 2938 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 2939 2940 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 2941 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 2942 2943 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 2944 2945 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 2946 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 2947 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 2948 2949 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 2950 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 2951 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 2952 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 2953 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 2954 2955 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 2956 gpu_metrics->indep_throttle_status = 2957 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 2958 navi1x_throttler_map); 2959 2960 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 2961 2962 gpu_metrics->pcie_link_width = 2963 smu_v11_0_get_current_pcie_link_width(smu); 2964 gpu_metrics->pcie_link_speed = 2965 smu_v11_0_get_current_pcie_link_speed(smu); 2966 2967 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 2968 2969 if (metrics.CurrGfxVoltageOffset) 2970 gpu_metrics->voltage_gfx = 2971 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; 2972 if (metrics.CurrMemVidOffset) 2973 gpu_metrics->voltage_mem = 2974 (155000 - 625 * metrics.CurrMemVidOffset) / 100; 2975 if (metrics.CurrSocVoltageOffset) 2976 gpu_metrics->voltage_soc = 2977 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; 2978 2979 *table = (void *)gpu_metrics; 2980 2981 return sizeof(struct gpu_metrics_v1_3); 2982 } 2983 2984 static int navi10_i2c_xfer(struct i2c_adapter *i2c_adap, 2985 struct i2c_msg *msg, int num_msgs) 2986 { 2987 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap); 2988 struct amdgpu_device *adev = smu_i2c->adev; 2989 struct smu_context *smu = adev->powerplay.pp_handle; 2990 struct smu_table_context *smu_table = &smu->smu_table; 2991 struct smu_table *table = &smu_table->driver_table; 2992 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 2993 int i, j, r, c; 2994 u16 dir; 2995 2996 if (!adev->pm.dpm_enabled) 2997 return -EBUSY; 2998 2999 req = kzalloc(sizeof(*req), GFP_KERNEL); 3000 if (!req) 3001 return -ENOMEM; 3002 3003 req->I2CcontrollerPort = smu_i2c->port; 3004 req->I2CSpeed = I2C_SPEED_FAST_400K; 3005 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 3006 dir = msg[0].flags & I2C_M_RD; 3007 3008 for (c = i = 0; i < num_msgs; i++) { 3009 for (j = 0; j < msg[i].len; j++, c++) { 3010 SwI2cCmd_t *cmd = &req->SwI2cCmds[c]; 3011 3012 if (!(msg[i].flags & I2C_M_RD)) { 3013 /* write */ 3014 cmd->Cmd = I2C_CMD_WRITE; 3015 cmd->RegisterAddr = msg[i].buf[j]; 3016 } 3017 3018 if ((dir ^ msg[i].flags) & I2C_M_RD) { 3019 /* The direction changes. 3020 */ 3021 dir = msg[i].flags & I2C_M_RD; 3022 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK; 3023 } 3024 3025 req->NumCmds++; 3026 3027 /* 3028 * Insert STOP if we are at the last byte of either last 3029 * message for the transaction or the client explicitly 3030 * requires a STOP at this particular message. 3031 */ 3032 if ((j == msg[i].len - 1) && 3033 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) { 3034 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK; 3035 cmd->CmdConfig |= CMDCONFIG_STOP_MASK; 3036 } 3037 } 3038 } 3039 mutex_lock(&adev->pm.mutex); 3040 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 3041 if (r) 3042 goto fail; 3043 3044 for (c = i = 0; i < num_msgs; i++) { 3045 if (!(msg[i].flags & I2C_M_RD)) { 3046 c += msg[i].len; 3047 continue; 3048 } 3049 for (j = 0; j < msg[i].len; j++, c++) { 3050 SwI2cCmd_t *cmd = &res->SwI2cCmds[c]; 3051 3052 msg[i].buf[j] = cmd->Data; 3053 } 3054 } 3055 r = num_msgs; 3056 fail: 3057 mutex_unlock(&adev->pm.mutex); 3058 kfree(req); 3059 return r; 3060 } 3061 3062 static u32 navi10_i2c_func(struct i2c_adapter *adap) 3063 { 3064 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 3065 } 3066 3067 3068 static const struct i2c_algorithm navi10_i2c_algo = { 3069 .master_xfer = navi10_i2c_xfer, 3070 .functionality = navi10_i2c_func, 3071 }; 3072 3073 static const struct i2c_adapter_quirks navi10_i2c_control_quirks = { 3074 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN, 3075 .max_read_len = MAX_SW_I2C_COMMANDS, 3076 .max_write_len = MAX_SW_I2C_COMMANDS, 3077 .max_comb_1st_msg_len = 2, 3078 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 3079 }; 3080 3081 static int navi10_i2c_control_init(struct smu_context *smu) 3082 { 3083 struct amdgpu_device *adev = smu->adev; 3084 int res, i; 3085 3086 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 3087 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 3088 struct i2c_adapter *control = &smu_i2c->adapter; 3089 3090 smu_i2c->adev = adev; 3091 smu_i2c->port = i; 3092 mutex_init(&smu_i2c->mutex); 3093 control->owner = THIS_MODULE; 3094 control->class = I2C_CLASS_HWMON; 3095 control->dev.parent = &adev->pdev->dev; 3096 control->algo = &navi10_i2c_algo; 3097 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i); 3098 control->quirks = &navi10_i2c_control_quirks; 3099 i2c_set_adapdata(control, smu_i2c); 3100 3101 res = i2c_add_adapter(control); 3102 if (res) { 3103 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 3104 goto Out_err; 3105 } 3106 } 3107 3108 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 3109 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter; 3110 3111 return 0; 3112 Out_err: 3113 for ( ; i >= 0; i--) { 3114 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 3115 struct i2c_adapter *control = &smu_i2c->adapter; 3116 3117 i2c_del_adapter(control); 3118 } 3119 return res; 3120 } 3121 3122 static void navi10_i2c_control_fini(struct smu_context *smu) 3123 { 3124 struct amdgpu_device *adev = smu->adev; 3125 int i; 3126 3127 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 3128 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 3129 struct i2c_adapter *control = &smu_i2c->adapter; 3130 3131 i2c_del_adapter(control); 3132 } 3133 adev->pm.ras_eeprom_i2c_bus = NULL; 3134 adev->pm.fru_eeprom_i2c_bus = NULL; 3135 } 3136 3137 static ssize_t navi10_get_gpu_metrics(struct smu_context *smu, 3138 void **table) 3139 { 3140 struct smu_table_context *smu_table = &smu->smu_table; 3141 struct gpu_metrics_v1_3 *gpu_metrics = 3142 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 3143 SmuMetrics_t metrics; 3144 int ret = 0; 3145 3146 ret = smu_cmn_get_metrics_table(smu, 3147 NULL, 3148 true); 3149 if (ret) 3150 return ret; 3151 3152 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_t)); 3153 3154 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 3155 3156 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 3157 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 3158 gpu_metrics->temperature_mem = metrics.TemperatureMem; 3159 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 3160 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 3161 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 3162 3163 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 3164 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 3165 3166 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 3167 3168 if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 3169 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs; 3170 else 3171 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs; 3172 3173 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 3174 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs; 3175 3176 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 3177 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 3178 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 3179 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 3180 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 3181 3182 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 3183 gpu_metrics->indep_throttle_status = 3184 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 3185 navi1x_throttler_map); 3186 3187 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 3188 3189 gpu_metrics->pcie_link_width = metrics.PcieWidth; 3190 gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate]; 3191 3192 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 3193 3194 if (metrics.CurrGfxVoltageOffset) 3195 gpu_metrics->voltage_gfx = 3196 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; 3197 if (metrics.CurrMemVidOffset) 3198 gpu_metrics->voltage_mem = 3199 (155000 - 625 * metrics.CurrMemVidOffset) / 100; 3200 if (metrics.CurrSocVoltageOffset) 3201 gpu_metrics->voltage_soc = 3202 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; 3203 3204 *table = (void *)gpu_metrics; 3205 3206 return sizeof(struct gpu_metrics_v1_3); 3207 } 3208 3209 static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu, 3210 void **table) 3211 { 3212 struct smu_table_context *smu_table = &smu->smu_table; 3213 struct gpu_metrics_v1_3 *gpu_metrics = 3214 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 3215 SmuMetrics_NV12_legacy_t metrics; 3216 int ret = 0; 3217 3218 ret = smu_cmn_get_metrics_table(smu, 3219 NULL, 3220 true); 3221 if (ret) 3222 return ret; 3223 3224 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_legacy_t)); 3225 3226 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 3227 3228 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 3229 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 3230 gpu_metrics->temperature_mem = metrics.TemperatureMem; 3231 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 3232 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 3233 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 3234 3235 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 3236 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 3237 3238 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 3239 3240 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 3241 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 3242 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 3243 3244 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator; 3245 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency; 3246 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency; 3247 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage; 3248 3249 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 3250 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 3251 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 3252 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 3253 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 3254 3255 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 3256 gpu_metrics->indep_throttle_status = 3257 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 3258 navi1x_throttler_map); 3259 3260 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 3261 3262 gpu_metrics->pcie_link_width = 3263 smu_v11_0_get_current_pcie_link_width(smu); 3264 gpu_metrics->pcie_link_speed = 3265 smu_v11_0_get_current_pcie_link_speed(smu); 3266 3267 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 3268 3269 if (metrics.CurrGfxVoltageOffset) 3270 gpu_metrics->voltage_gfx = 3271 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; 3272 if (metrics.CurrMemVidOffset) 3273 gpu_metrics->voltage_mem = 3274 (155000 - 625 * metrics.CurrMemVidOffset) / 100; 3275 if (metrics.CurrSocVoltageOffset) 3276 gpu_metrics->voltage_soc = 3277 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; 3278 3279 *table = (void *)gpu_metrics; 3280 3281 return sizeof(struct gpu_metrics_v1_3); 3282 } 3283 3284 static ssize_t navi12_get_gpu_metrics(struct smu_context *smu, 3285 void **table) 3286 { 3287 struct smu_table_context *smu_table = &smu->smu_table; 3288 struct gpu_metrics_v1_3 *gpu_metrics = 3289 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 3290 SmuMetrics_NV12_t metrics; 3291 int ret = 0; 3292 3293 ret = smu_cmn_get_metrics_table(smu, 3294 NULL, 3295 true); 3296 if (ret) 3297 return ret; 3298 3299 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_t)); 3300 3301 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 3302 3303 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 3304 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 3305 gpu_metrics->temperature_mem = metrics.TemperatureMem; 3306 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 3307 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 3308 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 3309 3310 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 3311 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 3312 3313 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 3314 3315 if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 3316 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs; 3317 else 3318 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs; 3319 3320 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 3321 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs; 3322 3323 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator; 3324 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency; 3325 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency; 3326 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage; 3327 3328 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 3329 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 3330 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 3331 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 3332 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 3333 3334 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 3335 gpu_metrics->indep_throttle_status = 3336 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 3337 navi1x_throttler_map); 3338 3339 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 3340 3341 gpu_metrics->pcie_link_width = metrics.PcieWidth; 3342 gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate]; 3343 3344 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 3345 3346 if (metrics.CurrGfxVoltageOffset) 3347 gpu_metrics->voltage_gfx = 3348 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; 3349 if (metrics.CurrMemVidOffset) 3350 gpu_metrics->voltage_mem = 3351 (155000 - 625 * metrics.CurrMemVidOffset) / 100; 3352 if (metrics.CurrSocVoltageOffset) 3353 gpu_metrics->voltage_soc = 3354 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; 3355 3356 *table = (void *)gpu_metrics; 3357 3358 return sizeof(struct gpu_metrics_v1_3); 3359 } 3360 3361 static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu, 3362 void **table) 3363 { 3364 struct amdgpu_device *adev = smu->adev; 3365 uint32_t smu_version; 3366 int ret = 0; 3367 3368 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 3369 if (ret) { 3370 dev_err(adev->dev, "Failed to get smu version!\n"); 3371 return ret; 3372 } 3373 3374 switch (adev->ip_versions[MP1_HWIP][0]) { 3375 case IP_VERSION(11, 0, 9): 3376 if (smu_version > 0x00341C00) 3377 ret = navi12_get_gpu_metrics(smu, table); 3378 else 3379 ret = navi12_get_legacy_gpu_metrics(smu, table); 3380 break; 3381 case IP_VERSION(11, 0, 0): 3382 case IP_VERSION(11, 0, 5): 3383 default: 3384 if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) || 3385 ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00)) 3386 ret = navi10_get_gpu_metrics(smu, table); 3387 else 3388 ret = navi10_get_legacy_gpu_metrics(smu, table); 3389 break; 3390 } 3391 3392 return ret; 3393 } 3394 3395 static int navi10_enable_mgpu_fan_boost(struct smu_context *smu) 3396 { 3397 struct smu_table_context *table_context = &smu->smu_table; 3398 PPTable_t *smc_pptable = table_context->driver_pptable; 3399 struct amdgpu_device *adev = smu->adev; 3400 uint32_t param = 0; 3401 3402 /* Navi12 does not support this */ 3403 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9)) 3404 return 0; 3405 3406 /* 3407 * Skip the MGpuFanBoost setting for those ASICs 3408 * which do not support it 3409 */ 3410 if (!smc_pptable->MGpuFanBoostLimitRpm) 3411 return 0; 3412 3413 /* Workaround for WS SKU */ 3414 if (adev->pdev->device == 0x7312 && 3415 adev->pdev->revision == 0) 3416 param = 0xD188; 3417 3418 return smu_cmn_send_smc_msg_with_param(smu, 3419 SMU_MSG_SetMGpuFanBoostLimitRpm, 3420 param, 3421 NULL); 3422 } 3423 3424 static int navi10_post_smu_init(struct smu_context *smu) 3425 { 3426 struct amdgpu_device *adev = smu->adev; 3427 int ret = 0; 3428 3429 if (amdgpu_sriov_vf(adev)) 3430 return 0; 3431 3432 ret = navi10_run_umc_cdr_workaround(smu); 3433 if (ret) 3434 dev_err(adev->dev, "Failed to apply umc cdr workaround!\n"); 3435 3436 return ret; 3437 } 3438 3439 static int navi10_get_default_config_table_settings(struct smu_context *smu, 3440 struct config_table_setting *table) 3441 { 3442 if (!table) 3443 return -EINVAL; 3444 3445 table->gfxclk_average_tau = 10; 3446 table->socclk_average_tau = 10; 3447 table->uclk_average_tau = 10; 3448 table->gfx_activity_average_tau = 10; 3449 table->mem_activity_average_tau = 10; 3450 table->socket_power_average_tau = 10; 3451 3452 return 0; 3453 } 3454 3455 static int navi10_set_config_table(struct smu_context *smu, 3456 struct config_table_setting *table) 3457 { 3458 DriverSmuConfig_t driver_smu_config_table; 3459 3460 if (!table) 3461 return -EINVAL; 3462 3463 memset(&driver_smu_config_table, 3464 0, 3465 sizeof(driver_smu_config_table)); 3466 3467 driver_smu_config_table.GfxclkAverageLpfTau = 3468 table->gfxclk_average_tau; 3469 driver_smu_config_table.SocclkAverageLpfTau = 3470 table->socclk_average_tau; 3471 driver_smu_config_table.UclkAverageLpfTau = 3472 table->uclk_average_tau; 3473 driver_smu_config_table.GfxActivityLpfTau = 3474 table->gfx_activity_average_tau; 3475 driver_smu_config_table.UclkActivityLpfTau = 3476 table->mem_activity_average_tau; 3477 driver_smu_config_table.SocketPowerLpfTau = 3478 table->socket_power_average_tau; 3479 3480 return smu_cmn_update_table(smu, 3481 SMU_TABLE_DRIVER_SMU_CONFIG, 3482 0, 3483 (void *)&driver_smu_config_table, 3484 true); 3485 } 3486 3487 static const struct pptable_funcs navi10_ppt_funcs = { 3488 .get_allowed_feature_mask = navi10_get_allowed_feature_mask, 3489 .set_default_dpm_table = navi10_set_default_dpm_table, 3490 .dpm_set_vcn_enable = navi10_dpm_set_vcn_enable, 3491 .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable, 3492 .i2c_init = navi10_i2c_control_init, 3493 .i2c_fini = navi10_i2c_control_fini, 3494 .print_clk_levels = navi10_print_clk_levels, 3495 .emit_clk_levels = navi10_emit_clk_levels, 3496 .force_clk_levels = navi10_force_clk_levels, 3497 .populate_umd_state_clk = navi10_populate_umd_state_clk, 3498 .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency, 3499 .pre_display_config_changed = navi10_pre_display_config_changed, 3500 .display_config_changed = navi10_display_config_changed, 3501 .notify_smc_display_config = navi10_notify_smc_display_config, 3502 .is_dpm_running = navi10_is_dpm_running, 3503 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm, 3504 .get_fan_speed_rpm = navi10_get_fan_speed_rpm, 3505 .get_power_profile_mode = navi10_get_power_profile_mode, 3506 .set_power_profile_mode = navi10_set_power_profile_mode, 3507 .set_watermarks_table = navi10_set_watermarks_table, 3508 .read_sensor = navi10_read_sensor, 3509 .get_uclk_dpm_states = navi10_get_uclk_dpm_states, 3510 .set_performance_level = smu_v11_0_set_performance_level, 3511 .get_thermal_temperature_range = navi10_get_thermal_temperature_range, 3512 .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch, 3513 .get_power_limit = navi10_get_power_limit, 3514 .update_pcie_parameters = navi10_update_pcie_parameters, 3515 .init_microcode = smu_v11_0_init_microcode, 3516 .load_microcode = smu_v11_0_load_microcode, 3517 .fini_microcode = smu_v11_0_fini_microcode, 3518 .init_smc_tables = navi10_init_smc_tables, 3519 .fini_smc_tables = smu_v11_0_fini_smc_tables, 3520 .init_power = smu_v11_0_init_power, 3521 .fini_power = smu_v11_0_fini_power, 3522 .check_fw_status = smu_v11_0_check_fw_status, 3523 .setup_pptable = navi10_setup_pptable, 3524 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, 3525 .check_fw_version = smu_v11_0_check_fw_version, 3526 .write_pptable = smu_cmn_write_pptable, 3527 .set_driver_table_location = smu_v11_0_set_driver_table_location, 3528 .set_tool_table_location = smu_v11_0_set_tool_table_location, 3529 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 3530 .system_features_control = smu_v11_0_system_features_control, 3531 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 3532 .send_smc_msg = smu_cmn_send_smc_msg, 3533 .init_display_count = smu_v11_0_init_display_count, 3534 .set_allowed_mask = smu_v11_0_set_allowed_mask, 3535 .get_enabled_mask = smu_cmn_get_enabled_mask, 3536 .feature_is_enabled = smu_cmn_feature_is_enabled, 3537 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 3538 .notify_display_change = smu_v11_0_notify_display_change, 3539 .set_power_limit = smu_v11_0_set_power_limit, 3540 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks, 3541 .enable_thermal_alert = smu_v11_0_enable_thermal_alert, 3542 .disable_thermal_alert = smu_v11_0_disable_thermal_alert, 3543 .set_min_dcef_deep_sleep = smu_v11_0_set_min_deep_sleep_dcefclk, 3544 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request, 3545 .get_fan_control_mode = smu_v11_0_get_fan_control_mode, 3546 .set_fan_control_mode = smu_v11_0_set_fan_control_mode, 3547 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm, 3548 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm, 3549 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate, 3550 .gfx_off_control = smu_v11_0_gfx_off_control, 3551 .register_irq_handler = smu_v11_0_register_irq_handler, 3552 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme, 3553 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc, 3554 .baco_is_support = smu_v11_0_baco_is_support, 3555 .baco_get_state = smu_v11_0_baco_get_state, 3556 .baco_set_state = smu_v11_0_baco_set_state, 3557 .baco_enter = navi10_baco_enter, 3558 .baco_exit = navi10_baco_exit, 3559 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq, 3560 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, 3561 .set_default_od_settings = navi10_set_default_od_settings, 3562 .od_edit_dpm_table = navi10_od_edit_dpm_table, 3563 .restore_user_od_settings = smu_v11_0_restore_user_od_settings, 3564 .run_btc = navi10_run_btc, 3565 .set_power_source = smu_v11_0_set_power_source, 3566 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 3567 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 3568 .get_gpu_metrics = navi1x_get_gpu_metrics, 3569 .enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost, 3570 .gfx_ulv_control = smu_v11_0_gfx_ulv_control, 3571 .deep_sleep_control = smu_v11_0_deep_sleep_control, 3572 .get_fan_parameters = navi10_get_fan_parameters, 3573 .post_init = navi10_post_smu_init, 3574 .interrupt_work = smu_v11_0_interrupt_work, 3575 .set_mp1_state = smu_cmn_set_mp1_state, 3576 .get_default_config_table_settings = navi10_get_default_config_table_settings, 3577 .set_config_table = navi10_set_config_table, 3578 }; 3579 3580 void navi10_set_ppt_funcs(struct smu_context *smu) 3581 { 3582 smu->ppt_funcs = &navi10_ppt_funcs; 3583 smu->message_map = navi10_message_map; 3584 smu->clock_map = navi10_clk_map; 3585 smu->feature_map = navi10_feature_mask_map; 3586 smu->table_map = navi10_table_map; 3587 smu->pwr_src_map = navi10_pwr_src_map; 3588 smu->workload_map = navi10_workload_map; 3589 smu_v11_0_set_smu_mailbox_registers(smu); 3590 } 3591