1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include <linux/pci.h> 28 #include <linux/i2c.h> 29 #include "amdgpu.h" 30 #include "amdgpu_dpm.h" 31 #include "amdgpu_smu.h" 32 #include "atomfirmware.h" 33 #include "amdgpu_atomfirmware.h" 34 #include "amdgpu_atombios.h" 35 #include "soc15_common.h" 36 #include "smu_v11_0.h" 37 #include "smu11_driver_if_navi10.h" 38 #include "atom.h" 39 #include "navi10_ppt.h" 40 #include "smu_v11_0_pptable.h" 41 #include "smu_v11_0_ppsmc.h" 42 #include "nbio/nbio_2_3_offset.h" 43 #include "nbio/nbio_2_3_sh_mask.h" 44 #include "thm/thm_11_0_2_offset.h" 45 #include "thm/thm_11_0_2_sh_mask.h" 46 47 #include "asic_reg/mp/mp_11_0_sh_mask.h" 48 #include "smu_cmn.h" 49 #include "smu_11_0_cdr_table.h" 50 51 /* 52 * DO NOT use these for err/warn/info/debug messages. 53 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 54 * They are more MGPU friendly. 55 */ 56 #undef pr_err 57 #undef pr_warn 58 #undef pr_info 59 #undef pr_debug 60 61 #define FEATURE_MASK(feature) (1ULL << feature) 62 #define SMC_DPM_FEATURE ( \ 63 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \ 64 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 65 FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT) | \ 66 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 70 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)) 71 72 #define SMU_11_0_GFX_BUSY_THRESHOLD 15 73 74 static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = { 75 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 76 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 77 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 78 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0), 79 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), 80 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 81 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 82 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 0), 83 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 0), 84 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 0), 85 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 0), 86 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1), 87 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1), 88 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 0), 89 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 90 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 91 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 92 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 93 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 94 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 95 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 96 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 97 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable, 0), 98 MSG_MAP(RunBtc, PPSMC_MSG_RunBtc, 0), 99 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), 100 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1), 101 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), 102 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0), 103 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 104 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), 105 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), 106 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 107 MSG_MAP(SetMemoryChannelConfig, PPSMC_MSG_SetMemoryChannelConfig, 0), 108 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0), 109 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0), 110 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0), 111 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0), 112 MSG_MAP(SetMinDeepSleepDcefclk, PPSMC_MSG_SetMinDeepSleepDcefclk, 0), 113 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0), 114 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0), 115 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0), 116 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0), 117 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1), 118 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 119 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 120 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 121 MSG_MAP(ConfigureGfxDidt, PPSMC_MSG_ConfigureGfxDidt, 0), 122 MSG_MAP(NumOfDisplays, PPSMC_MSG_NumOfDisplays, 0), 123 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0), 124 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0), 125 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 126 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 127 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 128 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1), 129 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0), 130 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0), 131 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset, 0), 132 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown, 0), 133 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 134 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 135 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 136 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 137 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0), 138 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0), 139 MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE,PPSMC_MSG_DALDisableDummyPstateChange, 0), 140 MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALEnableDummyPstateChange, 0), 141 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0), 142 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0), 143 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0), 144 MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH, PPSMC_MSG_SetDriverDummyTableDramAddrHigh, 0), 145 MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW, PPSMC_MSG_SetDriverDummyTableDramAddrLow, 0), 146 MSG_MAP(GET_UMC_FW_WA, PPSMC_MSG_GetUMCFWWA, 0), 147 }; 148 149 static struct cmn2asic_mapping navi10_clk_map[SMU_CLK_COUNT] = { 150 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 151 CLK_MAP(SCLK, PPCLK_GFXCLK), 152 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 153 CLK_MAP(FCLK, PPCLK_SOCCLK), 154 CLK_MAP(UCLK, PPCLK_UCLK), 155 CLK_MAP(MCLK, PPCLK_UCLK), 156 CLK_MAP(DCLK, PPCLK_DCLK), 157 CLK_MAP(VCLK, PPCLK_VCLK), 158 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK), 159 CLK_MAP(DISPCLK, PPCLK_DISPCLK), 160 CLK_MAP(PIXCLK, PPCLK_PIXCLK), 161 CLK_MAP(PHYCLK, PPCLK_PHYCLK), 162 }; 163 164 static struct cmn2asic_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = { 165 FEA_MAP(DPM_PREFETCHER), 166 FEA_MAP(DPM_GFXCLK), 167 FEA_MAP(DPM_GFX_PACE), 168 FEA_MAP(DPM_UCLK), 169 FEA_MAP(DPM_SOCCLK), 170 FEA_MAP(DPM_MP0CLK), 171 FEA_MAP(DPM_LINK), 172 FEA_MAP(DPM_DCEFCLK), 173 FEA_MAP(MEM_VDDCI_SCALING), 174 FEA_MAP(MEM_MVDD_SCALING), 175 FEA_MAP(DS_GFXCLK), 176 FEA_MAP(DS_SOCCLK), 177 FEA_MAP(DS_LCLK), 178 FEA_MAP(DS_DCEFCLK), 179 FEA_MAP(DS_UCLK), 180 FEA_MAP(GFX_ULV), 181 FEA_MAP(FW_DSTATE), 182 FEA_MAP(GFXOFF), 183 FEA_MAP(BACO), 184 FEA_MAP(VCN_PG), 185 FEA_MAP(JPEG_PG), 186 FEA_MAP(USB_PG), 187 FEA_MAP(RSMU_SMN_CG), 188 FEA_MAP(PPT), 189 FEA_MAP(TDC), 190 FEA_MAP(GFX_EDC), 191 FEA_MAP(APCC_PLUS), 192 FEA_MAP(GTHR), 193 FEA_MAP(ACDC), 194 FEA_MAP(VR0HOT), 195 FEA_MAP(VR1HOT), 196 FEA_MAP(FW_CTF), 197 FEA_MAP(FAN_CONTROL), 198 FEA_MAP(THERMAL), 199 FEA_MAP(GFX_DCS), 200 FEA_MAP(RM), 201 FEA_MAP(LED_DISPLAY), 202 FEA_MAP(GFX_SS), 203 FEA_MAP(OUT_OF_BAND_MONITOR), 204 FEA_MAP(TEMP_DEPENDENT_VMIN), 205 FEA_MAP(MMHUB_PG), 206 FEA_MAP(ATHUB_PG), 207 FEA_MAP(APCC_DFLL), 208 }; 209 210 static struct cmn2asic_mapping navi10_table_map[SMU_TABLE_COUNT] = { 211 TAB_MAP(PPTABLE), 212 TAB_MAP(WATERMARKS), 213 TAB_MAP(AVFS), 214 TAB_MAP(AVFS_PSM_DEBUG), 215 TAB_MAP(AVFS_FUSE_OVERRIDE), 216 TAB_MAP(PMSTATUSLOG), 217 TAB_MAP(SMU_METRICS), 218 TAB_MAP(DRIVER_SMU_CONFIG), 219 TAB_MAP(ACTIVITY_MONITOR_COEFF), 220 TAB_MAP(OVERDRIVE), 221 TAB_MAP(I2C_COMMANDS), 222 TAB_MAP(PACE), 223 }; 224 225 static struct cmn2asic_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { 226 PWR_MAP(AC), 227 PWR_MAP(DC), 228 }; 229 230 static struct cmn2asic_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 231 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), 232 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 233 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 234 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 235 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 236 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 237 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 238 }; 239 240 static const uint8_t navi1x_throttler_map[] = { 241 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT), 242 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT), 243 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 244 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 245 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 246 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT), 247 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 248 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT), 249 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT), 250 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 251 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 252 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 253 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 254 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT), 255 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT), 256 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), 257 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT), 258 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT), 259 }; 260 261 262 static bool is_asic_secure(struct smu_context *smu) 263 { 264 struct amdgpu_device *adev = smu->adev; 265 bool is_secure = true; 266 uint32_t mp0_fw_intf; 267 268 mp0_fw_intf = RREG32_PCIE(MP0_Public | 269 (smnMP0_FW_INTF & 0xffffffff)); 270 271 if (!(mp0_fw_intf & (1 << 19))) 272 is_secure = false; 273 274 return is_secure; 275 } 276 277 static int 278 navi10_get_allowed_feature_mask(struct smu_context *smu, 279 uint32_t *feature_mask, uint32_t num) 280 { 281 struct amdgpu_device *adev = smu->adev; 282 283 if (num > 2) 284 return -EINVAL; 285 286 memset(feature_mask, 0, sizeof(uint32_t) * num); 287 288 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) 289 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) 290 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) 291 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) 292 | FEATURE_MASK(FEATURE_PPT_BIT) 293 | FEATURE_MASK(FEATURE_TDC_BIT) 294 | FEATURE_MASK(FEATURE_GFX_EDC_BIT) 295 | FEATURE_MASK(FEATURE_APCC_PLUS_BIT) 296 | FEATURE_MASK(FEATURE_VR0HOT_BIT) 297 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) 298 | FEATURE_MASK(FEATURE_THERMAL_BIT) 299 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT) 300 | FEATURE_MASK(FEATURE_DS_LCLK_BIT) 301 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) 302 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) 303 | FEATURE_MASK(FEATURE_BACO_BIT) 304 | FEATURE_MASK(FEATURE_GFX_SS_BIT) 305 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) 306 | FEATURE_MASK(FEATURE_FW_CTF_BIT) 307 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT); 308 309 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) 310 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 311 312 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) 313 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); 314 315 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) 316 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); 317 318 if (adev->pm.pp_feature & PP_ULV_MASK) 319 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); 320 321 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) 322 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 323 324 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 325 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); 326 327 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) 328 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); 329 330 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB) 331 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT); 332 333 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN) 334 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT); 335 336 if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG) 337 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT); 338 339 if (smu->dc_controlled_by_gpio) 340 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT); 341 342 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) 343 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 344 345 /* DPM UCLK enablement should be skipped for navi10 A0 secure board */ 346 if (!(is_asic_secure(smu) && 347 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && 348 (adev->rev_id == 0)) && 349 (adev->pm.pp_feature & PP_MCLK_DPM_MASK)) 350 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) 351 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) 352 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); 353 354 /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */ 355 if (is_asic_secure(smu) && 356 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && 357 (adev->rev_id == 0)) 358 *(uint64_t *)feature_mask &= 359 ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT); 360 361 return 0; 362 } 363 364 static void navi10_check_bxco_support(struct smu_context *smu) 365 { 366 struct smu_table_context *table_context = &smu->smu_table; 367 struct smu_11_0_powerplay_table *powerplay_table = 368 table_context->power_play_table; 369 struct smu_baco_context *smu_baco = &smu->smu_baco; 370 struct amdgpu_device *adev = smu->adev; 371 uint32_t val; 372 373 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO || 374 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) { 375 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); 376 smu_baco->platform_support = 377 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : 378 false; 379 } 380 } 381 382 static int navi10_check_powerplay_table(struct smu_context *smu) 383 { 384 struct smu_table_context *table_context = &smu->smu_table; 385 struct smu_11_0_powerplay_table *powerplay_table = 386 table_context->power_play_table; 387 388 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC) 389 smu->dc_controlled_by_gpio = true; 390 391 navi10_check_bxco_support(smu); 392 393 table_context->thermal_controller_type = 394 powerplay_table->thermal_controller_type; 395 396 /* 397 * Instead of having its own buffer space and get overdrive_table copied, 398 * smu->od_settings just points to the actual overdrive_table 399 */ 400 smu->od_settings = &powerplay_table->overdrive_table; 401 402 return 0; 403 } 404 405 static int navi10_append_powerplay_table(struct smu_context *smu) 406 { 407 struct amdgpu_device *adev = smu->adev; 408 struct smu_table_context *table_context = &smu->smu_table; 409 PPTable_t *smc_pptable = table_context->driver_pptable; 410 struct atom_smc_dpm_info_v4_5 *smc_dpm_table; 411 struct atom_smc_dpm_info_v4_7 *smc_dpm_table_v4_7; 412 int index, ret; 413 414 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 415 smc_dpm_info); 416 417 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL, 418 (uint8_t **)&smc_dpm_table); 419 if (ret) 420 return ret; 421 422 dev_info(adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n", 423 smc_dpm_table->table_header.format_revision, 424 smc_dpm_table->table_header.content_revision); 425 426 if (smc_dpm_table->table_header.format_revision != 4) { 427 dev_err(adev->dev, "smc_dpm_info table format revision is not 4!\n"); 428 return -EINVAL; 429 } 430 431 switch (smc_dpm_table->table_header.content_revision) { 432 case 5: /* nv10 and nv14 */ 433 smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved, 434 smc_dpm_table, I2cControllers); 435 break; 436 case 7: /* nv12 */ 437 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL, 438 (uint8_t **)&smc_dpm_table_v4_7); 439 if (ret) 440 return ret; 441 smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved, 442 smc_dpm_table_v4_7, I2cControllers); 443 break; 444 default: 445 dev_err(smu->adev->dev, "smc_dpm_info with unsupported content revision %d!\n", 446 smc_dpm_table->table_header.content_revision); 447 return -EINVAL; 448 } 449 450 if (adev->pm.pp_feature & PP_GFXOFF_MASK) { 451 /* TODO: remove it once SMU fw fix it */ 452 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN; 453 } 454 455 return 0; 456 } 457 458 static int navi10_store_powerplay_table(struct smu_context *smu) 459 { 460 struct smu_table_context *table_context = &smu->smu_table; 461 struct smu_11_0_powerplay_table *powerplay_table = 462 table_context->power_play_table; 463 464 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 465 sizeof(PPTable_t)); 466 467 return 0; 468 } 469 470 static int navi10_setup_pptable(struct smu_context *smu) 471 { 472 int ret = 0; 473 474 ret = smu_v11_0_setup_pptable(smu); 475 if (ret) 476 return ret; 477 478 ret = navi10_store_powerplay_table(smu); 479 if (ret) 480 return ret; 481 482 ret = navi10_append_powerplay_table(smu); 483 if (ret) 484 return ret; 485 486 ret = navi10_check_powerplay_table(smu); 487 if (ret) 488 return ret; 489 490 return ret; 491 } 492 493 static int navi10_tables_init(struct smu_context *smu) 494 { 495 struct smu_table_context *smu_table = &smu->smu_table; 496 struct smu_table *tables = smu_table->tables; 497 498 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 499 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 500 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 501 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 502 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_NV1X_t), 503 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 504 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 505 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 506 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t), 507 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 508 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 509 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 510 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, 511 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE, 512 AMDGPU_GEM_DOMAIN_VRAM); 513 514 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_NV1X_t), 515 GFP_KERNEL); 516 if (!smu_table->metrics_table) 517 goto err0_out; 518 smu_table->metrics_time = 0; 519 520 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 521 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 522 if (!smu_table->gpu_metrics_table) 523 goto err1_out; 524 525 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 526 if (!smu_table->watermarks_table) 527 goto err2_out; 528 529 return 0; 530 531 err2_out: 532 kfree(smu_table->gpu_metrics_table); 533 err1_out: 534 kfree(smu_table->metrics_table); 535 err0_out: 536 return -ENOMEM; 537 } 538 539 static int navi10_get_legacy_smu_metrics_data(struct smu_context *smu, 540 MetricsMember_t member, 541 uint32_t *value) 542 { 543 struct smu_table_context *smu_table= &smu->smu_table; 544 SmuMetrics_legacy_t *metrics = 545 (SmuMetrics_legacy_t *)smu_table->metrics_table; 546 int ret = 0; 547 548 ret = smu_cmn_get_metrics_table(smu, 549 NULL, 550 false); 551 if (ret) 552 return ret; 553 554 switch (member) { 555 case METRICS_CURR_GFXCLK: 556 *value = metrics->CurrClock[PPCLK_GFXCLK]; 557 break; 558 case METRICS_CURR_SOCCLK: 559 *value = metrics->CurrClock[PPCLK_SOCCLK]; 560 break; 561 case METRICS_CURR_UCLK: 562 *value = metrics->CurrClock[PPCLK_UCLK]; 563 break; 564 case METRICS_CURR_VCLK: 565 *value = metrics->CurrClock[PPCLK_VCLK]; 566 break; 567 case METRICS_CURR_DCLK: 568 *value = metrics->CurrClock[PPCLK_DCLK]; 569 break; 570 case METRICS_CURR_DCEFCLK: 571 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 572 break; 573 case METRICS_AVERAGE_GFXCLK: 574 *value = metrics->AverageGfxclkFrequency; 575 break; 576 case METRICS_AVERAGE_SOCCLK: 577 *value = metrics->AverageSocclkFrequency; 578 break; 579 case METRICS_AVERAGE_UCLK: 580 *value = metrics->AverageUclkFrequency; 581 break; 582 case METRICS_AVERAGE_GFXACTIVITY: 583 *value = metrics->AverageGfxActivity; 584 break; 585 case METRICS_AVERAGE_MEMACTIVITY: 586 *value = metrics->AverageUclkActivity; 587 break; 588 case METRICS_AVERAGE_SOCKETPOWER: 589 *value = metrics->AverageSocketPower << 8; 590 break; 591 case METRICS_TEMPERATURE_EDGE: 592 *value = metrics->TemperatureEdge * 593 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 594 break; 595 case METRICS_TEMPERATURE_HOTSPOT: 596 *value = metrics->TemperatureHotspot * 597 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 598 break; 599 case METRICS_TEMPERATURE_MEM: 600 *value = metrics->TemperatureMem * 601 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 602 break; 603 case METRICS_TEMPERATURE_VRGFX: 604 *value = metrics->TemperatureVrGfx * 605 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 606 break; 607 case METRICS_TEMPERATURE_VRSOC: 608 *value = metrics->TemperatureVrSoc * 609 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 610 break; 611 case METRICS_THROTTLER_STATUS: 612 *value = metrics->ThrottlerStatus; 613 break; 614 case METRICS_CURR_FANSPEED: 615 *value = metrics->CurrFanSpeed; 616 break; 617 default: 618 *value = UINT_MAX; 619 break; 620 } 621 622 return ret; 623 } 624 625 static int navi10_get_smu_metrics_data(struct smu_context *smu, 626 MetricsMember_t member, 627 uint32_t *value) 628 { 629 struct smu_table_context *smu_table= &smu->smu_table; 630 SmuMetrics_t *metrics = 631 (SmuMetrics_t *)smu_table->metrics_table; 632 int ret = 0; 633 634 ret = smu_cmn_get_metrics_table(smu, 635 NULL, 636 false); 637 if (ret) 638 return ret; 639 640 switch (member) { 641 case METRICS_CURR_GFXCLK: 642 *value = metrics->CurrClock[PPCLK_GFXCLK]; 643 break; 644 case METRICS_CURR_SOCCLK: 645 *value = metrics->CurrClock[PPCLK_SOCCLK]; 646 break; 647 case METRICS_CURR_UCLK: 648 *value = metrics->CurrClock[PPCLK_UCLK]; 649 break; 650 case METRICS_CURR_VCLK: 651 *value = metrics->CurrClock[PPCLK_VCLK]; 652 break; 653 case METRICS_CURR_DCLK: 654 *value = metrics->CurrClock[PPCLK_DCLK]; 655 break; 656 case METRICS_CURR_DCEFCLK: 657 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 658 break; 659 case METRICS_AVERAGE_GFXCLK: 660 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 661 *value = metrics->AverageGfxclkFrequencyPreDs; 662 else 663 *value = metrics->AverageGfxclkFrequencyPostDs; 664 break; 665 case METRICS_AVERAGE_SOCCLK: 666 *value = metrics->AverageSocclkFrequency; 667 break; 668 case METRICS_AVERAGE_UCLK: 669 *value = metrics->AverageUclkFrequencyPostDs; 670 break; 671 case METRICS_AVERAGE_GFXACTIVITY: 672 *value = metrics->AverageGfxActivity; 673 break; 674 case METRICS_AVERAGE_MEMACTIVITY: 675 *value = metrics->AverageUclkActivity; 676 break; 677 case METRICS_AVERAGE_SOCKETPOWER: 678 *value = metrics->AverageSocketPower << 8; 679 break; 680 case METRICS_TEMPERATURE_EDGE: 681 *value = metrics->TemperatureEdge * 682 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 683 break; 684 case METRICS_TEMPERATURE_HOTSPOT: 685 *value = metrics->TemperatureHotspot * 686 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 687 break; 688 case METRICS_TEMPERATURE_MEM: 689 *value = metrics->TemperatureMem * 690 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 691 break; 692 case METRICS_TEMPERATURE_VRGFX: 693 *value = metrics->TemperatureVrGfx * 694 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 695 break; 696 case METRICS_TEMPERATURE_VRSOC: 697 *value = metrics->TemperatureVrSoc * 698 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 699 break; 700 case METRICS_THROTTLER_STATUS: 701 *value = metrics->ThrottlerStatus; 702 break; 703 case METRICS_CURR_FANSPEED: 704 *value = metrics->CurrFanSpeed; 705 break; 706 default: 707 *value = UINT_MAX; 708 break; 709 } 710 711 return ret; 712 } 713 714 static int navi12_get_legacy_smu_metrics_data(struct smu_context *smu, 715 MetricsMember_t member, 716 uint32_t *value) 717 { 718 struct smu_table_context *smu_table= &smu->smu_table; 719 SmuMetrics_NV12_legacy_t *metrics = 720 (SmuMetrics_NV12_legacy_t *)smu_table->metrics_table; 721 int ret = 0; 722 723 ret = smu_cmn_get_metrics_table(smu, 724 NULL, 725 false); 726 if (ret) 727 return ret; 728 729 switch (member) { 730 case METRICS_CURR_GFXCLK: 731 *value = metrics->CurrClock[PPCLK_GFXCLK]; 732 break; 733 case METRICS_CURR_SOCCLK: 734 *value = metrics->CurrClock[PPCLK_SOCCLK]; 735 break; 736 case METRICS_CURR_UCLK: 737 *value = metrics->CurrClock[PPCLK_UCLK]; 738 break; 739 case METRICS_CURR_VCLK: 740 *value = metrics->CurrClock[PPCLK_VCLK]; 741 break; 742 case METRICS_CURR_DCLK: 743 *value = metrics->CurrClock[PPCLK_DCLK]; 744 break; 745 case METRICS_CURR_DCEFCLK: 746 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 747 break; 748 case METRICS_AVERAGE_GFXCLK: 749 *value = metrics->AverageGfxclkFrequency; 750 break; 751 case METRICS_AVERAGE_SOCCLK: 752 *value = metrics->AverageSocclkFrequency; 753 break; 754 case METRICS_AVERAGE_UCLK: 755 *value = metrics->AverageUclkFrequency; 756 break; 757 case METRICS_AVERAGE_GFXACTIVITY: 758 *value = metrics->AverageGfxActivity; 759 break; 760 case METRICS_AVERAGE_MEMACTIVITY: 761 *value = metrics->AverageUclkActivity; 762 break; 763 case METRICS_AVERAGE_SOCKETPOWER: 764 *value = metrics->AverageSocketPower << 8; 765 break; 766 case METRICS_TEMPERATURE_EDGE: 767 *value = metrics->TemperatureEdge * 768 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 769 break; 770 case METRICS_TEMPERATURE_HOTSPOT: 771 *value = metrics->TemperatureHotspot * 772 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 773 break; 774 case METRICS_TEMPERATURE_MEM: 775 *value = metrics->TemperatureMem * 776 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 777 break; 778 case METRICS_TEMPERATURE_VRGFX: 779 *value = metrics->TemperatureVrGfx * 780 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 781 break; 782 case METRICS_TEMPERATURE_VRSOC: 783 *value = metrics->TemperatureVrSoc * 784 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 785 break; 786 case METRICS_THROTTLER_STATUS: 787 *value = metrics->ThrottlerStatus; 788 break; 789 case METRICS_CURR_FANSPEED: 790 *value = metrics->CurrFanSpeed; 791 break; 792 default: 793 *value = UINT_MAX; 794 break; 795 } 796 797 return ret; 798 } 799 800 static int navi12_get_smu_metrics_data(struct smu_context *smu, 801 MetricsMember_t member, 802 uint32_t *value) 803 { 804 struct smu_table_context *smu_table= &smu->smu_table; 805 SmuMetrics_NV12_t *metrics = 806 (SmuMetrics_NV12_t *)smu_table->metrics_table; 807 int ret = 0; 808 809 ret = smu_cmn_get_metrics_table(smu, 810 NULL, 811 false); 812 if (ret) 813 return ret; 814 815 switch (member) { 816 case METRICS_CURR_GFXCLK: 817 *value = metrics->CurrClock[PPCLK_GFXCLK]; 818 break; 819 case METRICS_CURR_SOCCLK: 820 *value = metrics->CurrClock[PPCLK_SOCCLK]; 821 break; 822 case METRICS_CURR_UCLK: 823 *value = metrics->CurrClock[PPCLK_UCLK]; 824 break; 825 case METRICS_CURR_VCLK: 826 *value = metrics->CurrClock[PPCLK_VCLK]; 827 break; 828 case METRICS_CURR_DCLK: 829 *value = metrics->CurrClock[PPCLK_DCLK]; 830 break; 831 case METRICS_CURR_DCEFCLK: 832 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 833 break; 834 case METRICS_AVERAGE_GFXCLK: 835 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 836 *value = metrics->AverageGfxclkFrequencyPreDs; 837 else 838 *value = metrics->AverageGfxclkFrequencyPostDs; 839 break; 840 case METRICS_AVERAGE_SOCCLK: 841 *value = metrics->AverageSocclkFrequency; 842 break; 843 case METRICS_AVERAGE_UCLK: 844 *value = metrics->AverageUclkFrequencyPostDs; 845 break; 846 case METRICS_AVERAGE_GFXACTIVITY: 847 *value = metrics->AverageGfxActivity; 848 break; 849 case METRICS_AVERAGE_MEMACTIVITY: 850 *value = metrics->AverageUclkActivity; 851 break; 852 case METRICS_AVERAGE_SOCKETPOWER: 853 *value = metrics->AverageSocketPower << 8; 854 break; 855 case METRICS_TEMPERATURE_EDGE: 856 *value = metrics->TemperatureEdge * 857 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 858 break; 859 case METRICS_TEMPERATURE_HOTSPOT: 860 *value = metrics->TemperatureHotspot * 861 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 862 break; 863 case METRICS_TEMPERATURE_MEM: 864 *value = metrics->TemperatureMem * 865 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 866 break; 867 case METRICS_TEMPERATURE_VRGFX: 868 *value = metrics->TemperatureVrGfx * 869 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 870 break; 871 case METRICS_TEMPERATURE_VRSOC: 872 *value = metrics->TemperatureVrSoc * 873 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 874 break; 875 case METRICS_THROTTLER_STATUS: 876 *value = metrics->ThrottlerStatus; 877 break; 878 case METRICS_CURR_FANSPEED: 879 *value = metrics->CurrFanSpeed; 880 break; 881 default: 882 *value = UINT_MAX; 883 break; 884 } 885 886 return ret; 887 } 888 889 static int navi1x_get_smu_metrics_data(struct smu_context *smu, 890 MetricsMember_t member, 891 uint32_t *value) 892 { 893 struct amdgpu_device *adev = smu->adev; 894 uint32_t smu_version; 895 int ret = 0; 896 897 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 898 if (ret) { 899 dev_err(adev->dev, "Failed to get smu version!\n"); 900 return ret; 901 } 902 903 switch (adev->ip_versions[MP1_HWIP][0]) { 904 case IP_VERSION(11, 0, 9): 905 if (smu_version > 0x00341C00) 906 ret = navi12_get_smu_metrics_data(smu, member, value); 907 else 908 ret = navi12_get_legacy_smu_metrics_data(smu, member, value); 909 break; 910 case IP_VERSION(11, 0, 0): 911 case IP_VERSION(11, 0, 5): 912 default: 913 if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) || 914 ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00)) 915 ret = navi10_get_smu_metrics_data(smu, member, value); 916 else 917 ret = navi10_get_legacy_smu_metrics_data(smu, member, value); 918 break; 919 } 920 921 return ret; 922 } 923 924 static int navi10_allocate_dpm_context(struct smu_context *smu) 925 { 926 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 927 928 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 929 GFP_KERNEL); 930 if (!smu_dpm->dpm_context) 931 return -ENOMEM; 932 933 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 934 935 return 0; 936 } 937 938 static int navi10_init_smc_tables(struct smu_context *smu) 939 { 940 int ret = 0; 941 942 ret = navi10_tables_init(smu); 943 if (ret) 944 return ret; 945 946 ret = navi10_allocate_dpm_context(smu); 947 if (ret) 948 return ret; 949 950 return smu_v11_0_init_smc_tables(smu); 951 } 952 953 static int navi10_set_default_dpm_table(struct smu_context *smu) 954 { 955 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 956 PPTable_t *driver_ppt = smu->smu_table.driver_pptable; 957 struct smu_11_0_dpm_table *dpm_table; 958 int ret = 0; 959 960 /* socclk dpm table setup */ 961 dpm_table = &dpm_context->dpm_tables.soc_table; 962 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 963 ret = smu_v11_0_set_single_dpm_table(smu, 964 SMU_SOCCLK, 965 dpm_table); 966 if (ret) 967 return ret; 968 dpm_table->is_fine_grained = 969 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete; 970 } else { 971 dpm_table->count = 1; 972 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 973 dpm_table->dpm_levels[0].enabled = true; 974 dpm_table->min = dpm_table->dpm_levels[0].value; 975 dpm_table->max = dpm_table->dpm_levels[0].value; 976 } 977 978 /* gfxclk dpm table setup */ 979 dpm_table = &dpm_context->dpm_tables.gfx_table; 980 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 981 ret = smu_v11_0_set_single_dpm_table(smu, 982 SMU_GFXCLK, 983 dpm_table); 984 if (ret) 985 return ret; 986 dpm_table->is_fine_grained = 987 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete; 988 } else { 989 dpm_table->count = 1; 990 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 991 dpm_table->dpm_levels[0].enabled = true; 992 dpm_table->min = dpm_table->dpm_levels[0].value; 993 dpm_table->max = dpm_table->dpm_levels[0].value; 994 } 995 996 /* uclk dpm table setup */ 997 dpm_table = &dpm_context->dpm_tables.uclk_table; 998 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 999 ret = smu_v11_0_set_single_dpm_table(smu, 1000 SMU_UCLK, 1001 dpm_table); 1002 if (ret) 1003 return ret; 1004 dpm_table->is_fine_grained = 1005 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete; 1006 } else { 1007 dpm_table->count = 1; 1008 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 1009 dpm_table->dpm_levels[0].enabled = true; 1010 dpm_table->min = dpm_table->dpm_levels[0].value; 1011 dpm_table->max = dpm_table->dpm_levels[0].value; 1012 } 1013 1014 /* vclk dpm table setup */ 1015 dpm_table = &dpm_context->dpm_tables.vclk_table; 1016 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1017 ret = smu_v11_0_set_single_dpm_table(smu, 1018 SMU_VCLK, 1019 dpm_table); 1020 if (ret) 1021 return ret; 1022 dpm_table->is_fine_grained = 1023 !driver_ppt->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete; 1024 } else { 1025 dpm_table->count = 1; 1026 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; 1027 dpm_table->dpm_levels[0].enabled = true; 1028 dpm_table->min = dpm_table->dpm_levels[0].value; 1029 dpm_table->max = dpm_table->dpm_levels[0].value; 1030 } 1031 1032 /* dclk dpm table setup */ 1033 dpm_table = &dpm_context->dpm_tables.dclk_table; 1034 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1035 ret = smu_v11_0_set_single_dpm_table(smu, 1036 SMU_DCLK, 1037 dpm_table); 1038 if (ret) 1039 return ret; 1040 dpm_table->is_fine_grained = 1041 !driver_ppt->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete; 1042 } else { 1043 dpm_table->count = 1; 1044 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; 1045 dpm_table->dpm_levels[0].enabled = true; 1046 dpm_table->min = dpm_table->dpm_levels[0].value; 1047 dpm_table->max = dpm_table->dpm_levels[0].value; 1048 } 1049 1050 /* dcefclk dpm table setup */ 1051 dpm_table = &dpm_context->dpm_tables.dcef_table; 1052 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1053 ret = smu_v11_0_set_single_dpm_table(smu, 1054 SMU_DCEFCLK, 1055 dpm_table); 1056 if (ret) 1057 return ret; 1058 dpm_table->is_fine_grained = 1059 !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete; 1060 } else { 1061 dpm_table->count = 1; 1062 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1063 dpm_table->dpm_levels[0].enabled = true; 1064 dpm_table->min = dpm_table->dpm_levels[0].value; 1065 dpm_table->max = dpm_table->dpm_levels[0].value; 1066 } 1067 1068 /* pixelclk dpm table setup */ 1069 dpm_table = &dpm_context->dpm_tables.pixel_table; 1070 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1071 ret = smu_v11_0_set_single_dpm_table(smu, 1072 SMU_PIXCLK, 1073 dpm_table); 1074 if (ret) 1075 return ret; 1076 dpm_table->is_fine_grained = 1077 !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete; 1078 } else { 1079 dpm_table->count = 1; 1080 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1081 dpm_table->dpm_levels[0].enabled = true; 1082 dpm_table->min = dpm_table->dpm_levels[0].value; 1083 dpm_table->max = dpm_table->dpm_levels[0].value; 1084 } 1085 1086 /* displayclk dpm table setup */ 1087 dpm_table = &dpm_context->dpm_tables.display_table; 1088 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1089 ret = smu_v11_0_set_single_dpm_table(smu, 1090 SMU_DISPCLK, 1091 dpm_table); 1092 if (ret) 1093 return ret; 1094 dpm_table->is_fine_grained = 1095 !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete; 1096 } else { 1097 dpm_table->count = 1; 1098 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1099 dpm_table->dpm_levels[0].enabled = true; 1100 dpm_table->min = dpm_table->dpm_levels[0].value; 1101 dpm_table->max = dpm_table->dpm_levels[0].value; 1102 } 1103 1104 /* phyclk dpm table setup */ 1105 dpm_table = &dpm_context->dpm_tables.phy_table; 1106 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1107 ret = smu_v11_0_set_single_dpm_table(smu, 1108 SMU_PHYCLK, 1109 dpm_table); 1110 if (ret) 1111 return ret; 1112 dpm_table->is_fine_grained = 1113 !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete; 1114 } else { 1115 dpm_table->count = 1; 1116 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1117 dpm_table->dpm_levels[0].enabled = true; 1118 dpm_table->min = dpm_table->dpm_levels[0].value; 1119 dpm_table->max = dpm_table->dpm_levels[0].value; 1120 } 1121 1122 return 0; 1123 } 1124 1125 static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 1126 { 1127 int ret = 0; 1128 1129 if (enable) { 1130 /* vcn dpm on is a prerequisite for vcn power gate messages */ 1131 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1132 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL); 1133 if (ret) 1134 return ret; 1135 } 1136 } else { 1137 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1138 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL); 1139 if (ret) 1140 return ret; 1141 } 1142 } 1143 1144 return ret; 1145 } 1146 1147 static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 1148 { 1149 int ret = 0; 1150 1151 if (enable) { 1152 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 1153 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerUpJpeg, NULL); 1154 if (ret) 1155 return ret; 1156 } 1157 } else { 1158 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 1159 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL); 1160 if (ret) 1161 return ret; 1162 } 1163 } 1164 1165 return ret; 1166 } 1167 1168 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu, 1169 enum smu_clk_type clk_type, 1170 uint32_t *value) 1171 { 1172 MetricsMember_t member_type; 1173 int clk_id = 0; 1174 1175 clk_id = smu_cmn_to_asic_specific_index(smu, 1176 CMN2ASIC_MAPPING_CLK, 1177 clk_type); 1178 if (clk_id < 0) 1179 return clk_id; 1180 1181 switch (clk_id) { 1182 case PPCLK_GFXCLK: 1183 member_type = METRICS_CURR_GFXCLK; 1184 break; 1185 case PPCLK_UCLK: 1186 member_type = METRICS_CURR_UCLK; 1187 break; 1188 case PPCLK_SOCCLK: 1189 member_type = METRICS_CURR_SOCCLK; 1190 break; 1191 case PPCLK_VCLK: 1192 member_type = METRICS_CURR_VCLK; 1193 break; 1194 case PPCLK_DCLK: 1195 member_type = METRICS_CURR_DCLK; 1196 break; 1197 case PPCLK_DCEFCLK: 1198 member_type = METRICS_CURR_DCEFCLK; 1199 break; 1200 default: 1201 return -EINVAL; 1202 } 1203 1204 return navi1x_get_smu_metrics_data(smu, 1205 member_type, 1206 value); 1207 } 1208 1209 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) 1210 { 1211 PPTable_t *pptable = smu->smu_table.driver_pptable; 1212 DpmDescriptor_t *dpm_desc = NULL; 1213 uint32_t clk_index = 0; 1214 1215 clk_index = smu_cmn_to_asic_specific_index(smu, 1216 CMN2ASIC_MAPPING_CLK, 1217 clk_type); 1218 dpm_desc = &pptable->DpmDescriptor[clk_index]; 1219 1220 /* 0 - Fine grained DPM, 1 - Discrete DPM */ 1221 return dpm_desc->SnapToDiscrete == 0; 1222 } 1223 1224 static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap) 1225 { 1226 return od_table->cap[cap]; 1227 } 1228 1229 static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table, 1230 enum SMU_11_0_ODSETTING_ID setting, 1231 uint32_t *min, uint32_t *max) 1232 { 1233 if (min) 1234 *min = od_table->min[setting]; 1235 if (max) 1236 *max = od_table->max[setting]; 1237 } 1238 1239 static int navi10_print_clk_levels(struct smu_context *smu, 1240 enum smu_clk_type clk_type, char *buf) 1241 { 1242 uint16_t *curve_settings; 1243 int i, levels, size = 0, ret = 0; 1244 uint32_t cur_value = 0, value = 0, count = 0; 1245 uint32_t freq_values[3] = {0}; 1246 uint32_t mark_index = 0; 1247 struct smu_table_context *table_context = &smu->smu_table; 1248 uint32_t gen_speed, lane_width; 1249 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1250 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1251 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable; 1252 OverDriveTable_t *od_table = 1253 (OverDriveTable_t *)table_context->overdrive_table; 1254 struct smu_11_0_overdrive_table *od_settings = smu->od_settings; 1255 uint32_t min_value, max_value; 1256 1257 smu_cmn_get_sysfs_buf(&buf, &size); 1258 1259 switch (clk_type) { 1260 case SMU_GFXCLK: 1261 case SMU_SCLK: 1262 case SMU_SOCCLK: 1263 case SMU_MCLK: 1264 case SMU_UCLK: 1265 case SMU_FCLK: 1266 case SMU_VCLK: 1267 case SMU_DCLK: 1268 case SMU_DCEFCLK: 1269 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value); 1270 if (ret) 1271 return size; 1272 1273 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); 1274 if (ret) 1275 return size; 1276 1277 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) { 1278 for (i = 0; i < count; i++) { 1279 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); 1280 if (ret) 1281 return size; 1282 1283 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 1284 cur_value == value ? "*" : ""); 1285 } 1286 } else { 1287 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]); 1288 if (ret) 1289 return size; 1290 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]); 1291 if (ret) 1292 return size; 1293 1294 freq_values[1] = cur_value; 1295 mark_index = cur_value == freq_values[0] ? 0 : 1296 cur_value == freq_values[2] ? 2 : 1; 1297 1298 levels = 3; 1299 if (mark_index != 1) { 1300 levels = 2; 1301 freq_values[1] = freq_values[2]; 1302 } 1303 1304 for (i = 0; i < levels; i++) { 1305 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i], 1306 i == mark_index ? "*" : ""); 1307 } 1308 } 1309 break; 1310 case SMU_PCIE: 1311 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); 1312 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); 1313 for (i = 0; i < NUM_LINK_LEVELS; i++) 1314 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i, 1315 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," : 1316 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," : 1317 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," : 1318 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "", 1319 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" : 1320 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" : 1321 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" : 1322 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" : 1323 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" : 1324 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "", 1325 pptable->LclkFreq[i], 1326 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && 1327 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? 1328 "*" : ""); 1329 break; 1330 case SMU_OD_SCLK: 1331 if (!smu->od_enabled || !od_table || !od_settings) 1332 break; 1333 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) 1334 break; 1335 size += sysfs_emit_at(buf, size, "OD_SCLK:\n"); 1336 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", 1337 od_table->GfxclkFmin, od_table->GfxclkFmax); 1338 break; 1339 case SMU_OD_MCLK: 1340 if (!smu->od_enabled || !od_table || !od_settings) 1341 break; 1342 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) 1343 break; 1344 size += sysfs_emit_at(buf, size, "OD_MCLK:\n"); 1345 size += sysfs_emit_at(buf, size, "1: %uMHz\n", od_table->UclkFmax); 1346 break; 1347 case SMU_OD_VDDC_CURVE: 1348 if (!smu->od_enabled || !od_table || !od_settings) 1349 break; 1350 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) 1351 break; 1352 size += sysfs_emit_at(buf, size, "OD_VDDC_CURVE:\n"); 1353 for (i = 0; i < 3; i++) { 1354 switch (i) { 1355 case 0: 1356 curve_settings = &od_table->GfxclkFreq1; 1357 break; 1358 case 1: 1359 curve_settings = &od_table->GfxclkFreq2; 1360 break; 1361 case 2: 1362 curve_settings = &od_table->GfxclkFreq3; 1363 break; 1364 default: 1365 break; 1366 } 1367 size += sysfs_emit_at(buf, size, "%d: %uMHz %umV\n", 1368 i, curve_settings[0], 1369 curve_settings[1] / NAVI10_VOLTAGE_SCALE); 1370 } 1371 break; 1372 case SMU_OD_RANGE: 1373 if (!smu->od_enabled || !od_table || !od_settings) 1374 break; 1375 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 1376 1377 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) { 1378 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN, 1379 &min_value, NULL); 1380 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX, 1381 NULL, &max_value); 1382 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 1383 min_value, max_value); 1384 } 1385 1386 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) { 1387 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX, 1388 &min_value, &max_value); 1389 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n", 1390 min_value, max_value); 1391 } 1392 1393 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) { 1394 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1, 1395 &min_value, &max_value); 1396 size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n", 1397 min_value, max_value); 1398 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1, 1399 &min_value, &max_value); 1400 size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n", 1401 min_value, max_value); 1402 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2, 1403 &min_value, &max_value); 1404 size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n", 1405 min_value, max_value); 1406 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2, 1407 &min_value, &max_value); 1408 size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n", 1409 min_value, max_value); 1410 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3, 1411 &min_value, &max_value); 1412 size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n", 1413 min_value, max_value); 1414 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3, 1415 &min_value, &max_value); 1416 size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n", 1417 min_value, max_value); 1418 } 1419 1420 break; 1421 default: 1422 break; 1423 } 1424 1425 return size; 1426 } 1427 1428 static int navi10_force_clk_levels(struct smu_context *smu, 1429 enum smu_clk_type clk_type, uint32_t mask) 1430 { 1431 1432 int ret = 0, size = 0; 1433 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; 1434 1435 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1436 soft_max_level = mask ? (fls(mask) - 1) : 0; 1437 1438 switch (clk_type) { 1439 case SMU_GFXCLK: 1440 case SMU_SCLK: 1441 case SMU_SOCCLK: 1442 case SMU_MCLK: 1443 case SMU_UCLK: 1444 case SMU_FCLK: 1445 /* There is only 2 levels for fine grained DPM */ 1446 if (navi10_is_support_fine_grained_dpm(smu, clk_type)) { 1447 soft_max_level = (soft_max_level >= 1 ? 1 : 0); 1448 soft_min_level = (soft_min_level >= 1 ? 1 : 0); 1449 } 1450 1451 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); 1452 if (ret) 1453 return size; 1454 1455 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq); 1456 if (ret) 1457 return size; 1458 1459 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 1460 if (ret) 1461 return size; 1462 break; 1463 case SMU_DCEFCLK: 1464 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n"); 1465 break; 1466 1467 default: 1468 break; 1469 } 1470 1471 return size; 1472 } 1473 1474 static int navi10_populate_umd_state_clk(struct smu_context *smu) 1475 { 1476 struct smu_11_0_dpm_context *dpm_context = 1477 smu->smu_dpm.dpm_context; 1478 struct smu_11_0_dpm_table *gfx_table = 1479 &dpm_context->dpm_tables.gfx_table; 1480 struct smu_11_0_dpm_table *mem_table = 1481 &dpm_context->dpm_tables.uclk_table; 1482 struct smu_11_0_dpm_table *soc_table = 1483 &dpm_context->dpm_tables.soc_table; 1484 struct smu_umd_pstate_table *pstate_table = 1485 &smu->pstate_table; 1486 struct amdgpu_device *adev = smu->adev; 1487 uint32_t sclk_freq; 1488 1489 pstate_table->gfxclk_pstate.min = gfx_table->min; 1490 switch (adev->ip_versions[MP1_HWIP][0]) { 1491 case IP_VERSION(11, 0, 0): 1492 switch (adev->pdev->revision) { 1493 case 0xf0: /* XTX */ 1494 case 0xc0: 1495 sclk_freq = NAVI10_PEAK_SCLK_XTX; 1496 break; 1497 case 0xf1: /* XT */ 1498 case 0xc1: 1499 sclk_freq = NAVI10_PEAK_SCLK_XT; 1500 break; 1501 default: /* XL */ 1502 sclk_freq = NAVI10_PEAK_SCLK_XL; 1503 break; 1504 } 1505 break; 1506 case IP_VERSION(11, 0, 5): 1507 switch (adev->pdev->revision) { 1508 case 0xc7: /* XT */ 1509 case 0xf4: 1510 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK; 1511 break; 1512 case 0xc1: /* XTM */ 1513 case 0xf2: 1514 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK; 1515 break; 1516 case 0xc3: /* XLM */ 1517 case 0xf3: 1518 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK; 1519 break; 1520 case 0xc5: /* XTX */ 1521 case 0xf6: 1522 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK; 1523 break; 1524 default: /* XL */ 1525 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK; 1526 break; 1527 } 1528 break; 1529 case IP_VERSION(11, 0, 9): 1530 sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK; 1531 break; 1532 default: 1533 sclk_freq = gfx_table->dpm_levels[gfx_table->count - 1].value; 1534 break; 1535 } 1536 pstate_table->gfxclk_pstate.peak = sclk_freq; 1537 1538 pstate_table->uclk_pstate.min = mem_table->min; 1539 pstate_table->uclk_pstate.peak = mem_table->max; 1540 1541 pstate_table->socclk_pstate.min = soc_table->min; 1542 pstate_table->socclk_pstate.peak = soc_table->max; 1543 1544 if (gfx_table->max > NAVI10_UMD_PSTATE_PROFILING_GFXCLK && 1545 mem_table->max > NAVI10_UMD_PSTATE_PROFILING_MEMCLK && 1546 soc_table->max > NAVI10_UMD_PSTATE_PROFILING_SOCCLK) { 1547 pstate_table->gfxclk_pstate.standard = 1548 NAVI10_UMD_PSTATE_PROFILING_GFXCLK; 1549 pstate_table->uclk_pstate.standard = 1550 NAVI10_UMD_PSTATE_PROFILING_MEMCLK; 1551 pstate_table->socclk_pstate.standard = 1552 NAVI10_UMD_PSTATE_PROFILING_SOCCLK; 1553 } else { 1554 pstate_table->gfxclk_pstate.standard = 1555 pstate_table->gfxclk_pstate.min; 1556 pstate_table->uclk_pstate.standard = 1557 pstate_table->uclk_pstate.min; 1558 pstate_table->socclk_pstate.standard = 1559 pstate_table->socclk_pstate.min; 1560 } 1561 1562 return 0; 1563 } 1564 1565 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu, 1566 enum smu_clk_type clk_type, 1567 struct pp_clock_levels_with_latency *clocks) 1568 { 1569 int ret = 0, i = 0; 1570 uint32_t level_count = 0, freq = 0; 1571 1572 switch (clk_type) { 1573 case SMU_GFXCLK: 1574 case SMU_DCEFCLK: 1575 case SMU_SOCCLK: 1576 case SMU_MCLK: 1577 case SMU_UCLK: 1578 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &level_count); 1579 if (ret) 1580 return ret; 1581 1582 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS); 1583 clocks->num_levels = level_count; 1584 1585 for (i = 0; i < level_count; i++) { 1586 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &freq); 1587 if (ret) 1588 return ret; 1589 1590 clocks->data[i].clocks_in_khz = freq * 1000; 1591 clocks->data[i].latency_in_us = 0; 1592 } 1593 break; 1594 default: 1595 break; 1596 } 1597 1598 return ret; 1599 } 1600 1601 static int navi10_pre_display_config_changed(struct smu_context *smu) 1602 { 1603 int ret = 0; 1604 uint32_t max_freq = 0; 1605 1606 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL); 1607 if (ret) 1608 return ret; 1609 1610 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1611 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq); 1612 if (ret) 1613 return ret; 1614 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq); 1615 if (ret) 1616 return ret; 1617 } 1618 1619 return ret; 1620 } 1621 1622 static int navi10_display_config_changed(struct smu_context *smu) 1623 { 1624 int ret = 0; 1625 1626 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1627 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) && 1628 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 1629 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 1630 smu->display_config->num_display, 1631 NULL); 1632 if (ret) 1633 return ret; 1634 } 1635 1636 return ret; 1637 } 1638 1639 static bool navi10_is_dpm_running(struct smu_context *smu) 1640 { 1641 int ret = 0; 1642 uint32_t feature_mask[2]; 1643 uint64_t feature_enabled; 1644 1645 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2); 1646 if (ret) 1647 return false; 1648 1649 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0]; 1650 1651 return !!(feature_enabled & SMC_DPM_FEATURE); 1652 } 1653 1654 static int navi10_get_fan_speed_rpm(struct smu_context *smu, 1655 uint32_t *speed) 1656 { 1657 int ret = 0; 1658 1659 if (!speed) 1660 return -EINVAL; 1661 1662 switch (smu_v11_0_get_fan_control_mode(smu)) { 1663 case AMD_FAN_CTRL_AUTO: 1664 ret = navi10_get_smu_metrics_data(smu, 1665 METRICS_CURR_FANSPEED, 1666 speed); 1667 break; 1668 default: 1669 ret = smu_v11_0_get_fan_speed_rpm(smu, 1670 speed); 1671 break; 1672 } 1673 1674 return ret; 1675 } 1676 1677 static int navi10_get_fan_parameters(struct smu_context *smu) 1678 { 1679 PPTable_t *pptable = smu->smu_table.driver_pptable; 1680 1681 smu->fan_max_rpm = pptable->FanMaximumRpm; 1682 1683 return 0; 1684 } 1685 1686 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf) 1687 { 1688 DpmActivityMonitorCoeffInt_t activity_monitor; 1689 uint32_t i, size = 0; 1690 int16_t workload_type = 0; 1691 static const char *title[] = { 1692 "PROFILE_INDEX(NAME)", 1693 "CLOCK_TYPE(NAME)", 1694 "FPS", 1695 "MinFreqType", 1696 "MinActiveFreqType", 1697 "MinActiveFreq", 1698 "BoosterFreqType", 1699 "BoosterFreq", 1700 "PD_Data_limit_c", 1701 "PD_Data_error_coeff", 1702 "PD_Data_error_rate_coeff"}; 1703 int result = 0; 1704 1705 if (!buf) 1706 return -EINVAL; 1707 1708 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n", 1709 title[0], title[1], title[2], title[3], title[4], title[5], 1710 title[6], title[7], title[8], title[9], title[10]); 1711 1712 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1713 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1714 workload_type = smu_cmn_to_asic_specific_index(smu, 1715 CMN2ASIC_MAPPING_WORKLOAD, 1716 i); 1717 if (workload_type < 0) 1718 return -EINVAL; 1719 1720 result = smu_cmn_update_table(smu, 1721 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type, 1722 (void *)(&activity_monitor), false); 1723 if (result) { 1724 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1725 return result; 1726 } 1727 1728 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n", 1729 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1730 1731 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1732 " ", 1733 0, 1734 "GFXCLK", 1735 activity_monitor.Gfx_FPS, 1736 activity_monitor.Gfx_MinFreqStep, 1737 activity_monitor.Gfx_MinActiveFreqType, 1738 activity_monitor.Gfx_MinActiveFreq, 1739 activity_monitor.Gfx_BoosterFreqType, 1740 activity_monitor.Gfx_BoosterFreq, 1741 activity_monitor.Gfx_PD_Data_limit_c, 1742 activity_monitor.Gfx_PD_Data_error_coeff, 1743 activity_monitor.Gfx_PD_Data_error_rate_coeff); 1744 1745 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1746 " ", 1747 1, 1748 "SOCCLK", 1749 activity_monitor.Soc_FPS, 1750 activity_monitor.Soc_MinFreqStep, 1751 activity_monitor.Soc_MinActiveFreqType, 1752 activity_monitor.Soc_MinActiveFreq, 1753 activity_monitor.Soc_BoosterFreqType, 1754 activity_monitor.Soc_BoosterFreq, 1755 activity_monitor.Soc_PD_Data_limit_c, 1756 activity_monitor.Soc_PD_Data_error_coeff, 1757 activity_monitor.Soc_PD_Data_error_rate_coeff); 1758 1759 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1760 " ", 1761 2, 1762 "MEMLK", 1763 activity_monitor.Mem_FPS, 1764 activity_monitor.Mem_MinFreqStep, 1765 activity_monitor.Mem_MinActiveFreqType, 1766 activity_monitor.Mem_MinActiveFreq, 1767 activity_monitor.Mem_BoosterFreqType, 1768 activity_monitor.Mem_BoosterFreq, 1769 activity_monitor.Mem_PD_Data_limit_c, 1770 activity_monitor.Mem_PD_Data_error_coeff, 1771 activity_monitor.Mem_PD_Data_error_rate_coeff); 1772 } 1773 1774 return size; 1775 } 1776 1777 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 1778 { 1779 DpmActivityMonitorCoeffInt_t activity_monitor; 1780 int workload_type, ret = 0; 1781 1782 smu->power_profile_mode = input[size]; 1783 1784 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 1785 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode); 1786 return -EINVAL; 1787 } 1788 1789 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 1790 1791 ret = smu_cmn_update_table(smu, 1792 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1793 (void *)(&activity_monitor), false); 1794 if (ret) { 1795 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1796 return ret; 1797 } 1798 1799 switch (input[0]) { 1800 case 0: /* Gfxclk */ 1801 activity_monitor.Gfx_FPS = input[1]; 1802 activity_monitor.Gfx_MinFreqStep = input[2]; 1803 activity_monitor.Gfx_MinActiveFreqType = input[3]; 1804 activity_monitor.Gfx_MinActiveFreq = input[4]; 1805 activity_monitor.Gfx_BoosterFreqType = input[5]; 1806 activity_monitor.Gfx_BoosterFreq = input[6]; 1807 activity_monitor.Gfx_PD_Data_limit_c = input[7]; 1808 activity_monitor.Gfx_PD_Data_error_coeff = input[8]; 1809 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9]; 1810 break; 1811 case 1: /* Socclk */ 1812 activity_monitor.Soc_FPS = input[1]; 1813 activity_monitor.Soc_MinFreqStep = input[2]; 1814 activity_monitor.Soc_MinActiveFreqType = input[3]; 1815 activity_monitor.Soc_MinActiveFreq = input[4]; 1816 activity_monitor.Soc_BoosterFreqType = input[5]; 1817 activity_monitor.Soc_BoosterFreq = input[6]; 1818 activity_monitor.Soc_PD_Data_limit_c = input[7]; 1819 activity_monitor.Soc_PD_Data_error_coeff = input[8]; 1820 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9]; 1821 break; 1822 case 2: /* Memlk */ 1823 activity_monitor.Mem_FPS = input[1]; 1824 activity_monitor.Mem_MinFreqStep = input[2]; 1825 activity_monitor.Mem_MinActiveFreqType = input[3]; 1826 activity_monitor.Mem_MinActiveFreq = input[4]; 1827 activity_monitor.Mem_BoosterFreqType = input[5]; 1828 activity_monitor.Mem_BoosterFreq = input[6]; 1829 activity_monitor.Mem_PD_Data_limit_c = input[7]; 1830 activity_monitor.Mem_PD_Data_error_coeff = input[8]; 1831 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9]; 1832 break; 1833 } 1834 1835 ret = smu_cmn_update_table(smu, 1836 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1837 (void *)(&activity_monitor), true); 1838 if (ret) { 1839 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 1840 return ret; 1841 } 1842 } 1843 1844 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1845 workload_type = smu_cmn_to_asic_specific_index(smu, 1846 CMN2ASIC_MAPPING_WORKLOAD, 1847 smu->power_profile_mode); 1848 if (workload_type < 0) 1849 return -EINVAL; 1850 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 1851 1 << workload_type, NULL); 1852 1853 return ret; 1854 } 1855 1856 static int navi10_notify_smc_display_config(struct smu_context *smu) 1857 { 1858 struct smu_clocks min_clocks = {0}; 1859 struct pp_display_clock_request clock_req; 1860 int ret = 0; 1861 1862 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; 1863 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; 1864 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; 1865 1866 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1867 clock_req.clock_type = amd_pp_dcef_clock; 1868 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; 1869 1870 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req); 1871 if (!ret) { 1872 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) { 1873 ret = smu_cmn_send_smc_msg_with_param(smu, 1874 SMU_MSG_SetMinDeepSleepDcefclk, 1875 min_clocks.dcef_clock_in_sr/100, 1876 NULL); 1877 if (ret) { 1878 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!"); 1879 return ret; 1880 } 1881 } 1882 } else { 1883 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!"); 1884 } 1885 } 1886 1887 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1888 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); 1889 if (ret) { 1890 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__); 1891 return ret; 1892 } 1893 } 1894 1895 return 0; 1896 } 1897 1898 static int navi10_set_watermarks_table(struct smu_context *smu, 1899 struct pp_smu_wm_range_sets *clock_ranges) 1900 { 1901 Watermarks_t *table = smu->smu_table.watermarks_table; 1902 int ret = 0; 1903 int i; 1904 1905 if (clock_ranges) { 1906 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 1907 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1908 return -EINVAL; 1909 1910 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1911 table->WatermarkRow[WM_DCEFCLK][i].MinClock = 1912 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1913 table->WatermarkRow[WM_DCEFCLK][i].MaxClock = 1914 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1915 table->WatermarkRow[WM_DCEFCLK][i].MinUclk = 1916 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1917 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk = 1918 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1919 1920 table->WatermarkRow[WM_DCEFCLK][i].WmSetting = 1921 clock_ranges->reader_wm_sets[i].wm_inst; 1922 } 1923 1924 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1925 table->WatermarkRow[WM_SOCCLK][i].MinClock = 1926 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1927 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1928 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1929 table->WatermarkRow[WM_SOCCLK][i].MinUclk = 1930 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1931 table->WatermarkRow[WM_SOCCLK][i].MaxUclk = 1932 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1933 1934 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1935 clock_ranges->writer_wm_sets[i].wm_inst; 1936 } 1937 1938 smu->watermarks_bitmap |= WATERMARKS_EXIST; 1939 } 1940 1941 /* pass data to smu controller */ 1942 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1943 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1944 ret = smu_cmn_write_watermarks_table(smu); 1945 if (ret) { 1946 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1947 return ret; 1948 } 1949 smu->watermarks_bitmap |= WATERMARKS_LOADED; 1950 } 1951 1952 return 0; 1953 } 1954 1955 static int navi10_read_sensor(struct smu_context *smu, 1956 enum amd_pp_sensors sensor, 1957 void *data, uint32_t *size) 1958 { 1959 int ret = 0; 1960 struct smu_table_context *table_context = &smu->smu_table; 1961 PPTable_t *pptable = table_context->driver_pptable; 1962 1963 if(!data || !size) 1964 return -EINVAL; 1965 1966 switch (sensor) { 1967 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 1968 *(uint32_t *)data = pptable->FanMaximumRpm; 1969 *size = 4; 1970 break; 1971 case AMDGPU_PP_SENSOR_MEM_LOAD: 1972 ret = navi1x_get_smu_metrics_data(smu, 1973 METRICS_AVERAGE_MEMACTIVITY, 1974 (uint32_t *)data); 1975 *size = 4; 1976 break; 1977 case AMDGPU_PP_SENSOR_GPU_LOAD: 1978 ret = navi1x_get_smu_metrics_data(smu, 1979 METRICS_AVERAGE_GFXACTIVITY, 1980 (uint32_t *)data); 1981 *size = 4; 1982 break; 1983 case AMDGPU_PP_SENSOR_GPU_POWER: 1984 ret = navi1x_get_smu_metrics_data(smu, 1985 METRICS_AVERAGE_SOCKETPOWER, 1986 (uint32_t *)data); 1987 *size = 4; 1988 break; 1989 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1990 ret = navi1x_get_smu_metrics_data(smu, 1991 METRICS_TEMPERATURE_HOTSPOT, 1992 (uint32_t *)data); 1993 *size = 4; 1994 break; 1995 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1996 ret = navi1x_get_smu_metrics_data(smu, 1997 METRICS_TEMPERATURE_EDGE, 1998 (uint32_t *)data); 1999 *size = 4; 2000 break; 2001 case AMDGPU_PP_SENSOR_MEM_TEMP: 2002 ret = navi1x_get_smu_metrics_data(smu, 2003 METRICS_TEMPERATURE_MEM, 2004 (uint32_t *)data); 2005 *size = 4; 2006 break; 2007 case AMDGPU_PP_SENSOR_GFX_MCLK: 2008 ret = navi10_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 2009 *(uint32_t *)data *= 100; 2010 *size = 4; 2011 break; 2012 case AMDGPU_PP_SENSOR_GFX_SCLK: 2013 ret = navi1x_get_smu_metrics_data(smu, METRICS_AVERAGE_GFXCLK, (uint32_t *)data); 2014 *(uint32_t *)data *= 100; 2015 *size = 4; 2016 break; 2017 case AMDGPU_PP_SENSOR_VDDGFX: 2018 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data); 2019 *size = 4; 2020 break; 2021 default: 2022 ret = -EOPNOTSUPP; 2023 break; 2024 } 2025 2026 return ret; 2027 } 2028 2029 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states) 2030 { 2031 uint32_t num_discrete_levels = 0; 2032 uint16_t *dpm_levels = NULL; 2033 uint16_t i = 0; 2034 struct smu_table_context *table_context = &smu->smu_table; 2035 PPTable_t *driver_ppt = NULL; 2036 2037 if (!clocks_in_khz || !num_states || !table_context->driver_pptable) 2038 return -EINVAL; 2039 2040 driver_ppt = table_context->driver_pptable; 2041 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels; 2042 dpm_levels = driver_ppt->FreqTableUclk; 2043 2044 if (num_discrete_levels == 0 || dpm_levels == NULL) 2045 return -EINVAL; 2046 2047 *num_states = num_discrete_levels; 2048 for (i = 0; i < num_discrete_levels; i++) { 2049 /* convert to khz */ 2050 *clocks_in_khz = (*dpm_levels) * 1000; 2051 clocks_in_khz++; 2052 dpm_levels++; 2053 } 2054 2055 return 0; 2056 } 2057 2058 static int navi10_get_thermal_temperature_range(struct smu_context *smu, 2059 struct smu_temperature_range *range) 2060 { 2061 struct smu_table_context *table_context = &smu->smu_table; 2062 struct smu_11_0_powerplay_table *powerplay_table = 2063 table_context->power_play_table; 2064 PPTable_t *pptable = smu->smu_table.driver_pptable; 2065 2066 if (!range) 2067 return -EINVAL; 2068 2069 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range)); 2070 2071 range->max = pptable->TedgeLimit * 2072 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2073 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) * 2074 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2075 range->hotspot_crit_max = pptable->ThotspotLimit * 2076 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2077 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 2078 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2079 range->mem_crit_max = pptable->TmemLimit * 2080 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2081 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)* 2082 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2083 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 2084 2085 return 0; 2086 } 2087 2088 static int navi10_display_disable_memory_clock_switch(struct smu_context *smu, 2089 bool disable_memory_clock_switch) 2090 { 2091 int ret = 0; 2092 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks = 2093 (struct smu_11_0_max_sustainable_clocks *) 2094 smu->smu_table.max_sustainable_clocks; 2095 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal; 2096 uint32_t max_memory_clock = max_sustainable_clocks->uclock; 2097 2098 if(smu->disable_uclk_switch == disable_memory_clock_switch) 2099 return 0; 2100 2101 if(disable_memory_clock_switch) 2102 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0); 2103 else 2104 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0); 2105 2106 if(!ret) 2107 smu->disable_uclk_switch = disable_memory_clock_switch; 2108 2109 return ret; 2110 } 2111 2112 static int navi10_get_power_limit(struct smu_context *smu, 2113 uint32_t *current_power_limit, 2114 uint32_t *default_power_limit, 2115 uint32_t *max_power_limit) 2116 { 2117 struct smu_11_0_powerplay_table *powerplay_table = 2118 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table; 2119 struct smu_11_0_overdrive_table *od_settings = smu->od_settings; 2120 PPTable_t *pptable = smu->smu_table.driver_pptable; 2121 uint32_t power_limit, od_percent; 2122 2123 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) { 2124 /* the last hope to figure out the ppt limit */ 2125 if (!pptable) { 2126 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!"); 2127 return -EINVAL; 2128 } 2129 power_limit = 2130 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0]; 2131 } 2132 2133 if (current_power_limit) 2134 *current_power_limit = power_limit; 2135 if (default_power_limit) 2136 *default_power_limit = power_limit; 2137 2138 if (max_power_limit) { 2139 if (smu->od_enabled && 2140 navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) { 2141 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]); 2142 2143 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit); 2144 2145 power_limit *= (100 + od_percent); 2146 power_limit /= 100; 2147 } 2148 2149 *max_power_limit = power_limit; 2150 } 2151 2152 return 0; 2153 } 2154 2155 static int navi10_update_pcie_parameters(struct smu_context *smu, 2156 uint32_t pcie_gen_cap, 2157 uint32_t pcie_width_cap) 2158 { 2159 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 2160 PPTable_t *pptable = smu->smu_table.driver_pptable; 2161 uint32_t smu_pcie_arg; 2162 int ret, i; 2163 2164 /* lclk dpm table setup */ 2165 for (i = 0; i < MAX_PCIE_CONF; i++) { 2166 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i]; 2167 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i]; 2168 } 2169 2170 for (i = 0; i < NUM_LINK_LEVELS; i++) { 2171 smu_pcie_arg = (i << 16) | 2172 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) : 2173 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ? 2174 pptable->PcieLaneCount[i] : pcie_width_cap); 2175 ret = smu_cmn_send_smc_msg_with_param(smu, 2176 SMU_MSG_OverridePcieParameters, 2177 smu_pcie_arg, 2178 NULL); 2179 2180 if (ret) 2181 return ret; 2182 2183 if (pptable->PcieGenSpeed[i] > pcie_gen_cap) 2184 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap; 2185 if (pptable->PcieLaneCount[i] > pcie_width_cap) 2186 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap; 2187 } 2188 2189 return 0; 2190 } 2191 2192 static inline void navi10_dump_od_table(struct smu_context *smu, 2193 OverDriveTable_t *od_table) 2194 { 2195 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax); 2196 dev_dbg(smu->adev->dev, "OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1); 2197 dev_dbg(smu->adev->dev, "OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2); 2198 dev_dbg(smu->adev->dev, "OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3); 2199 dev_dbg(smu->adev->dev, "OD: UclkFmax: %d\n", od_table->UclkFmax); 2200 dev_dbg(smu->adev->dev, "OD: OverDrivePct: %d\n", od_table->OverDrivePct); 2201 } 2202 2203 static int navi10_od_setting_check_range(struct smu_context *smu, 2204 struct smu_11_0_overdrive_table *od_table, 2205 enum SMU_11_0_ODSETTING_ID setting, 2206 uint32_t value) 2207 { 2208 if (value < od_table->min[setting]) { 2209 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]); 2210 return -EINVAL; 2211 } 2212 if (value > od_table->max[setting]) { 2213 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]); 2214 return -EINVAL; 2215 } 2216 return 0; 2217 } 2218 2219 static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu, 2220 uint16_t *voltage, 2221 uint32_t freq) 2222 { 2223 uint32_t param = (freq & 0xFFFF) | (PPCLK_GFXCLK << 16); 2224 uint32_t value = 0; 2225 int ret; 2226 2227 ret = smu_cmn_send_smc_msg_with_param(smu, 2228 SMU_MSG_GetVoltageByDpm, 2229 param, 2230 &value); 2231 if (ret) { 2232 dev_err(smu->adev->dev, "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!"); 2233 return ret; 2234 } 2235 2236 *voltage = (uint16_t)value; 2237 2238 return 0; 2239 } 2240 2241 static int navi10_baco_enter(struct smu_context *smu) 2242 { 2243 struct amdgpu_device *adev = smu->adev; 2244 2245 /* 2246 * This aims the case below: 2247 * amdgpu driver loaded -> runpm suspend kicked -> sound driver loaded 2248 * 2249 * For NAVI10 and later ASICs, we rely on PMFW to handle the runpm. To 2250 * make that possible, PMFW needs to acknowledge the dstate transition 2251 * process for both gfx(function 0) and audio(function 1) function of 2252 * the ASIC. 2253 * 2254 * The PCI device's initial runpm status is RUNPM_SUSPENDED. So as the 2255 * device representing the audio function of the ASIC. And that means 2256 * even if the sound driver(snd_hda_intel) was not loaded yet, it's still 2257 * possible runpm suspend kicked on the ASIC. However without the dstate 2258 * transition notification from audio function, pmfw cannot handle the 2259 * BACO in/exit correctly. And that will cause driver hang on runpm 2260 * resuming. 2261 * 2262 * To address this, we revert to legacy message way(driver masters the 2263 * timing for BACO in/exit) on sound driver missing. 2264 */ 2265 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) 2266 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO); 2267 else 2268 return smu_v11_0_baco_enter(smu); 2269 } 2270 2271 static int navi10_baco_exit(struct smu_context *smu) 2272 { 2273 struct amdgpu_device *adev = smu->adev; 2274 2275 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) { 2276 /* Wait for PMFW handling for the Dstate change */ 2277 msleep(10); 2278 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS); 2279 } else { 2280 return smu_v11_0_baco_exit(smu); 2281 } 2282 } 2283 2284 static int navi10_set_default_od_settings(struct smu_context *smu) 2285 { 2286 OverDriveTable_t *od_table = 2287 (OverDriveTable_t *)smu->smu_table.overdrive_table; 2288 OverDriveTable_t *boot_od_table = 2289 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table; 2290 OverDriveTable_t *user_od_table = 2291 (OverDriveTable_t *)smu->smu_table.user_overdrive_table; 2292 int ret = 0; 2293 2294 /* 2295 * For S3/S4/Runpm resume, no need to setup those overdrive tables again as 2296 * - either they already have the default OD settings got during cold bootup 2297 * - or they have some user customized OD settings which cannot be overwritten 2298 */ 2299 if (smu->adev->in_suspend) 2300 return 0; 2301 2302 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)boot_od_table, false); 2303 if (ret) { 2304 dev_err(smu->adev->dev, "Failed to get overdrive table!\n"); 2305 return ret; 2306 } 2307 2308 if (!boot_od_table->GfxclkVolt1) { 2309 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu, 2310 &boot_od_table->GfxclkVolt1, 2311 boot_od_table->GfxclkFreq1); 2312 if (ret) 2313 return ret; 2314 } 2315 2316 if (!boot_od_table->GfxclkVolt2) { 2317 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu, 2318 &boot_od_table->GfxclkVolt2, 2319 boot_od_table->GfxclkFreq2); 2320 if (ret) 2321 return ret; 2322 } 2323 2324 if (!boot_od_table->GfxclkVolt3) { 2325 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu, 2326 &boot_od_table->GfxclkVolt3, 2327 boot_od_table->GfxclkFreq3); 2328 if (ret) 2329 return ret; 2330 } 2331 2332 navi10_dump_od_table(smu, boot_od_table); 2333 2334 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t)); 2335 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t)); 2336 2337 return 0; 2338 } 2339 2340 static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) { 2341 int i; 2342 int ret = 0; 2343 struct smu_table_context *table_context = &smu->smu_table; 2344 OverDriveTable_t *od_table; 2345 struct smu_11_0_overdrive_table *od_settings; 2346 enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting; 2347 uint16_t *freq_ptr, *voltage_ptr; 2348 od_table = (OverDriveTable_t *)table_context->overdrive_table; 2349 2350 if (!smu->od_enabled) { 2351 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n"); 2352 return -EINVAL; 2353 } 2354 2355 if (!smu->od_settings) { 2356 dev_err(smu->adev->dev, "OD board limits are not set!\n"); 2357 return -ENOENT; 2358 } 2359 2360 od_settings = smu->od_settings; 2361 2362 switch (type) { 2363 case PP_OD_EDIT_SCLK_VDDC_TABLE: 2364 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) { 2365 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n"); 2366 return -ENOTSUPP; 2367 } 2368 if (!table_context->overdrive_table) { 2369 dev_err(smu->adev->dev, "Overdrive is not initialized\n"); 2370 return -EINVAL; 2371 } 2372 for (i = 0; i < size; i += 2) { 2373 if (i + 2 > size) { 2374 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size); 2375 return -EINVAL; 2376 } 2377 switch (input[i]) { 2378 case 0: 2379 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN; 2380 freq_ptr = &od_table->GfxclkFmin; 2381 if (input[i + 1] > od_table->GfxclkFmax) { 2382 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n", 2383 input[i + 1], 2384 od_table->GfxclkFmin); 2385 return -EINVAL; 2386 } 2387 break; 2388 case 1: 2389 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX; 2390 freq_ptr = &od_table->GfxclkFmax; 2391 if (input[i + 1] < od_table->GfxclkFmin) { 2392 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n", 2393 input[i + 1], 2394 od_table->GfxclkFmax); 2395 return -EINVAL; 2396 } 2397 break; 2398 default: 2399 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]); 2400 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n"); 2401 return -EINVAL; 2402 } 2403 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[i + 1]); 2404 if (ret) 2405 return ret; 2406 *freq_ptr = input[i + 1]; 2407 } 2408 break; 2409 case PP_OD_EDIT_MCLK_VDDC_TABLE: 2410 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) { 2411 dev_warn(smu->adev->dev, "UCLK_MAX not supported!\n"); 2412 return -ENOTSUPP; 2413 } 2414 if (size < 2) { 2415 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size); 2416 return -EINVAL; 2417 } 2418 if (input[0] != 1) { 2419 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]); 2420 dev_info(smu->adev->dev, "Supported indices: [1:max]\n"); 2421 return -EINVAL; 2422 } 2423 ret = navi10_od_setting_check_range(smu, od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]); 2424 if (ret) 2425 return ret; 2426 od_table->UclkFmax = input[1]; 2427 break; 2428 case PP_OD_RESTORE_DEFAULT_TABLE: 2429 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) { 2430 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n"); 2431 return -EINVAL; 2432 } 2433 memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t)); 2434 break; 2435 case PP_OD_COMMIT_DPM_TABLE: 2436 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) { 2437 navi10_dump_od_table(smu, od_table); 2438 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true); 2439 if (ret) { 2440 dev_err(smu->adev->dev, "Failed to import overdrive table!\n"); 2441 return ret; 2442 } 2443 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t)); 2444 smu->user_dpm_profile.user_od = true; 2445 2446 if (!memcmp(table_context->user_overdrive_table, 2447 table_context->boot_overdrive_table, 2448 sizeof(OverDriveTable_t))) 2449 smu->user_dpm_profile.user_od = false; 2450 } 2451 break; 2452 case PP_OD_EDIT_VDDC_CURVE: 2453 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) { 2454 dev_warn(smu->adev->dev, "GFXCLK_CURVE not supported!\n"); 2455 return -ENOTSUPP; 2456 } 2457 if (size < 3) { 2458 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size); 2459 return -EINVAL; 2460 } 2461 if (!od_table) { 2462 dev_info(smu->adev->dev, "Overdrive is not initialized\n"); 2463 return -EINVAL; 2464 } 2465 2466 switch (input[0]) { 2467 case 0: 2468 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1; 2469 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1; 2470 freq_ptr = &od_table->GfxclkFreq1; 2471 voltage_ptr = &od_table->GfxclkVolt1; 2472 break; 2473 case 1: 2474 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2; 2475 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2; 2476 freq_ptr = &od_table->GfxclkFreq2; 2477 voltage_ptr = &od_table->GfxclkVolt2; 2478 break; 2479 case 2: 2480 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3; 2481 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3; 2482 freq_ptr = &od_table->GfxclkFreq3; 2483 voltage_ptr = &od_table->GfxclkVolt3; 2484 break; 2485 default: 2486 dev_info(smu->adev->dev, "Invalid VDDC_CURVE index: %ld\n", input[0]); 2487 dev_info(smu->adev->dev, "Supported indices: [0, 1, 2]\n"); 2488 return -EINVAL; 2489 } 2490 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[1]); 2491 if (ret) 2492 return ret; 2493 // Allow setting zero to disable the OverDrive VDDC curve 2494 if (input[2] != 0) { 2495 ret = navi10_od_setting_check_range(smu, od_settings, voltage_setting, input[2]); 2496 if (ret) 2497 return ret; 2498 *freq_ptr = input[1]; 2499 *voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE; 2500 dev_dbg(smu->adev->dev, "OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr); 2501 } else { 2502 // If setting 0, disable all voltage curve settings 2503 od_table->GfxclkVolt1 = 0; 2504 od_table->GfxclkVolt2 = 0; 2505 od_table->GfxclkVolt3 = 0; 2506 } 2507 navi10_dump_od_table(smu, od_table); 2508 break; 2509 default: 2510 return -ENOSYS; 2511 } 2512 return ret; 2513 } 2514 2515 static int navi10_run_btc(struct smu_context *smu) 2516 { 2517 int ret = 0; 2518 2519 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunBtc, NULL); 2520 if (ret) 2521 dev_err(smu->adev->dev, "RunBtc failed!\n"); 2522 2523 return ret; 2524 } 2525 2526 static bool navi10_need_umc_cdr_workaround(struct smu_context *smu) 2527 { 2528 struct amdgpu_device *adev = smu->adev; 2529 2530 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 2531 return false; 2532 2533 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0) || 2534 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) 2535 return true; 2536 2537 return false; 2538 } 2539 2540 static int navi10_umc_hybrid_cdr_workaround(struct smu_context *smu) 2541 { 2542 uint32_t uclk_count, uclk_min, uclk_max; 2543 int ret = 0; 2544 2545 /* This workaround can be applied only with uclk dpm enabled */ 2546 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 2547 return 0; 2548 2549 ret = smu_v11_0_get_dpm_level_count(smu, SMU_UCLK, &uclk_count); 2550 if (ret) 2551 return ret; 2552 2553 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)(uclk_count - 1), &uclk_max); 2554 if (ret) 2555 return ret; 2556 2557 /* 2558 * The NAVI10_UMC_HYBRID_CDR_WORKAROUND_UCLK_THRESHOLD is 750Mhz. 2559 * This workaround is needed only when the max uclk frequency 2560 * not greater than that. 2561 */ 2562 if (uclk_max > 0x2EE) 2563 return 0; 2564 2565 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)0, &uclk_min); 2566 if (ret) 2567 return ret; 2568 2569 /* Force UCLK out of the highest DPM */ 2570 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_min); 2571 if (ret) 2572 return ret; 2573 2574 /* Revert the UCLK Hardmax */ 2575 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_max); 2576 if (ret) 2577 return ret; 2578 2579 /* 2580 * In this case, SMU already disabled dummy pstate during enablement 2581 * of UCLK DPM, we have to re-enabled it. 2582 */ 2583 return smu_cmn_send_smc_msg(smu, SMU_MSG_DAL_ENABLE_DUMMY_PSTATE_CHANGE, NULL); 2584 } 2585 2586 static int navi10_set_dummy_pstates_table_location(struct smu_context *smu) 2587 { 2588 struct smu_table_context *smu_table = &smu->smu_table; 2589 struct smu_table *dummy_read_table = 2590 &smu_table->dummy_read_1_table; 2591 char *dummy_table = dummy_read_table->cpu_addr; 2592 int ret = 0; 2593 uint32_t i; 2594 2595 for (i = 0; i < 0x40000; i += 0x1000 * 2) { 2596 memcpy(dummy_table, &NoDbiPrbs7[0], 0x1000); 2597 dummy_table += 0x1000; 2598 memcpy(dummy_table, &DbiPrbs7[0], 0x1000); 2599 dummy_table += 0x1000; 2600 } 2601 2602 amdgpu_asic_flush_hdp(smu->adev, NULL); 2603 2604 ret = smu_cmn_send_smc_msg_with_param(smu, 2605 SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH, 2606 upper_32_bits(dummy_read_table->mc_address), 2607 NULL); 2608 if (ret) 2609 return ret; 2610 2611 return smu_cmn_send_smc_msg_with_param(smu, 2612 SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW, 2613 lower_32_bits(dummy_read_table->mc_address), 2614 NULL); 2615 } 2616 2617 static int navi10_run_umc_cdr_workaround(struct smu_context *smu) 2618 { 2619 struct amdgpu_device *adev = smu->adev; 2620 uint8_t umc_fw_greater_than_v136 = false; 2621 uint8_t umc_fw_disable_cdr = false; 2622 uint32_t pmfw_version; 2623 uint32_t param; 2624 int ret = 0; 2625 2626 if (!navi10_need_umc_cdr_workaround(smu)) 2627 return 0; 2628 2629 ret = smu_cmn_get_smc_version(smu, NULL, &pmfw_version); 2630 if (ret) { 2631 dev_err(adev->dev, "Failed to get smu version!\n"); 2632 return ret; 2633 } 2634 2635 /* 2636 * The messages below are only supported by Navi10 42.53.0 and later 2637 * PMFWs and Navi14 53.29.0 and later PMFWs. 2638 * - PPSMC_MSG_SetDriverDummyTableDramAddrHigh 2639 * - PPSMC_MSG_SetDriverDummyTableDramAddrLow 2640 * - PPSMC_MSG_GetUMCFWWA 2641 */ 2642 if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && (pmfw_version >= 0x2a3500)) || 2643 ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && (pmfw_version >= 0x351D00))) { 2644 ret = smu_cmn_send_smc_msg_with_param(smu, 2645 SMU_MSG_GET_UMC_FW_WA, 2646 0, 2647 ¶m); 2648 if (ret) 2649 return ret; 2650 2651 /* First bit indicates if the UMC f/w is above v137 */ 2652 umc_fw_greater_than_v136 = param & 0x1; 2653 2654 /* Second bit indicates if hybrid-cdr is disabled */ 2655 umc_fw_disable_cdr = param & 0x2; 2656 2657 /* w/a only allowed if UMC f/w is <= 136 */ 2658 if (umc_fw_greater_than_v136) 2659 return 0; 2660 2661 if (umc_fw_disable_cdr) { 2662 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) 2663 return navi10_umc_hybrid_cdr_workaround(smu); 2664 } else { 2665 return navi10_set_dummy_pstates_table_location(smu); 2666 } 2667 } else { 2668 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) 2669 return navi10_umc_hybrid_cdr_workaround(smu); 2670 } 2671 2672 return 0; 2673 } 2674 2675 static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu, 2676 void **table) 2677 { 2678 struct smu_table_context *smu_table = &smu->smu_table; 2679 struct gpu_metrics_v1_3 *gpu_metrics = 2680 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 2681 SmuMetrics_legacy_t metrics; 2682 int ret = 0; 2683 2684 ret = smu_cmn_get_metrics_table(smu, 2685 NULL, 2686 true); 2687 if (ret) 2688 return ret; 2689 2690 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_legacy_t)); 2691 2692 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 2693 2694 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 2695 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 2696 gpu_metrics->temperature_mem = metrics.TemperatureMem; 2697 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 2698 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 2699 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 2700 2701 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 2702 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 2703 2704 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 2705 2706 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 2707 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 2708 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 2709 2710 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 2711 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 2712 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 2713 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 2714 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 2715 2716 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 2717 gpu_metrics->indep_throttle_status = 2718 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 2719 navi1x_throttler_map); 2720 2721 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 2722 2723 gpu_metrics->pcie_link_width = 2724 smu_v11_0_get_current_pcie_link_width(smu); 2725 gpu_metrics->pcie_link_speed = 2726 smu_v11_0_get_current_pcie_link_speed(smu); 2727 2728 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 2729 2730 if (metrics.CurrGfxVoltageOffset) 2731 gpu_metrics->voltage_gfx = 2732 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; 2733 if (metrics.CurrMemVidOffset) 2734 gpu_metrics->voltage_mem = 2735 (155000 - 625 * metrics.CurrMemVidOffset) / 100; 2736 if (metrics.CurrSocVoltageOffset) 2737 gpu_metrics->voltage_soc = 2738 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; 2739 2740 *table = (void *)gpu_metrics; 2741 2742 return sizeof(struct gpu_metrics_v1_3); 2743 } 2744 2745 static int navi10_i2c_xfer(struct i2c_adapter *i2c_adap, 2746 struct i2c_msg *msg, int num_msgs) 2747 { 2748 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap); 2749 struct amdgpu_device *adev = smu_i2c->adev; 2750 struct smu_context *smu = adev->powerplay.pp_handle; 2751 struct smu_table_context *smu_table = &smu->smu_table; 2752 struct smu_table *table = &smu_table->driver_table; 2753 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 2754 int i, j, r, c; 2755 u16 dir; 2756 2757 if (!adev->pm.dpm_enabled) 2758 return -EBUSY; 2759 2760 req = kzalloc(sizeof(*req), GFP_KERNEL); 2761 if (!req) 2762 return -ENOMEM; 2763 2764 req->I2CcontrollerPort = smu_i2c->port; 2765 req->I2CSpeed = I2C_SPEED_FAST_400K; 2766 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 2767 dir = msg[0].flags & I2C_M_RD; 2768 2769 for (c = i = 0; i < num_msgs; i++) { 2770 for (j = 0; j < msg[i].len; j++, c++) { 2771 SwI2cCmd_t *cmd = &req->SwI2cCmds[c]; 2772 2773 if (!(msg[i].flags & I2C_M_RD)) { 2774 /* write */ 2775 cmd->Cmd = I2C_CMD_WRITE; 2776 cmd->RegisterAddr = msg[i].buf[j]; 2777 } 2778 2779 if ((dir ^ msg[i].flags) & I2C_M_RD) { 2780 /* The direction changes. 2781 */ 2782 dir = msg[i].flags & I2C_M_RD; 2783 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK; 2784 } 2785 2786 req->NumCmds++; 2787 2788 /* 2789 * Insert STOP if we are at the last byte of either last 2790 * message for the transaction or the client explicitly 2791 * requires a STOP at this particular message. 2792 */ 2793 if ((j == msg[i].len - 1) && 2794 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) { 2795 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK; 2796 cmd->CmdConfig |= CMDCONFIG_STOP_MASK; 2797 } 2798 } 2799 } 2800 mutex_lock(&adev->pm.mutex); 2801 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 2802 mutex_unlock(&adev->pm.mutex); 2803 if (r) 2804 goto fail; 2805 2806 for (c = i = 0; i < num_msgs; i++) { 2807 if (!(msg[i].flags & I2C_M_RD)) { 2808 c += msg[i].len; 2809 continue; 2810 } 2811 for (j = 0; j < msg[i].len; j++, c++) { 2812 SwI2cCmd_t *cmd = &res->SwI2cCmds[c]; 2813 2814 msg[i].buf[j] = cmd->Data; 2815 } 2816 } 2817 r = num_msgs; 2818 fail: 2819 kfree(req); 2820 return r; 2821 } 2822 2823 static u32 navi10_i2c_func(struct i2c_adapter *adap) 2824 { 2825 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 2826 } 2827 2828 2829 static const struct i2c_algorithm navi10_i2c_algo = { 2830 .master_xfer = navi10_i2c_xfer, 2831 .functionality = navi10_i2c_func, 2832 }; 2833 2834 static const struct i2c_adapter_quirks navi10_i2c_control_quirks = { 2835 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN, 2836 .max_read_len = MAX_SW_I2C_COMMANDS, 2837 .max_write_len = MAX_SW_I2C_COMMANDS, 2838 .max_comb_1st_msg_len = 2, 2839 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 2840 }; 2841 2842 static int navi10_i2c_control_init(struct smu_context *smu) 2843 { 2844 struct amdgpu_device *adev = smu->adev; 2845 int res, i; 2846 2847 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 2848 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 2849 struct i2c_adapter *control = &smu_i2c->adapter; 2850 2851 smu_i2c->adev = adev; 2852 smu_i2c->port = i; 2853 mutex_init(&smu_i2c->mutex); 2854 control->owner = THIS_MODULE; 2855 control->class = I2C_CLASS_HWMON; 2856 control->dev.parent = &adev->pdev->dev; 2857 control->algo = &navi10_i2c_algo; 2858 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i); 2859 control->quirks = &navi10_i2c_control_quirks; 2860 i2c_set_adapdata(control, smu_i2c); 2861 2862 res = i2c_add_adapter(control); 2863 if (res) { 2864 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 2865 goto Out_err; 2866 } 2867 } 2868 2869 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 2870 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter; 2871 2872 return 0; 2873 Out_err: 2874 for ( ; i >= 0; i--) { 2875 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 2876 struct i2c_adapter *control = &smu_i2c->adapter; 2877 2878 i2c_del_adapter(control); 2879 } 2880 return res; 2881 } 2882 2883 static void navi10_i2c_control_fini(struct smu_context *smu) 2884 { 2885 struct amdgpu_device *adev = smu->adev; 2886 int i; 2887 2888 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 2889 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 2890 struct i2c_adapter *control = &smu_i2c->adapter; 2891 2892 i2c_del_adapter(control); 2893 } 2894 adev->pm.ras_eeprom_i2c_bus = NULL; 2895 adev->pm.fru_eeprom_i2c_bus = NULL; 2896 } 2897 2898 static ssize_t navi10_get_gpu_metrics(struct smu_context *smu, 2899 void **table) 2900 { 2901 struct smu_table_context *smu_table = &smu->smu_table; 2902 struct gpu_metrics_v1_3 *gpu_metrics = 2903 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 2904 SmuMetrics_t metrics; 2905 int ret = 0; 2906 2907 ret = smu_cmn_get_metrics_table(smu, 2908 NULL, 2909 true); 2910 if (ret) 2911 return ret; 2912 2913 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_t)); 2914 2915 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 2916 2917 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 2918 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 2919 gpu_metrics->temperature_mem = metrics.TemperatureMem; 2920 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 2921 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 2922 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 2923 2924 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 2925 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 2926 2927 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 2928 2929 if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 2930 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs; 2931 else 2932 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs; 2933 2934 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 2935 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs; 2936 2937 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 2938 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 2939 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 2940 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 2941 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 2942 2943 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 2944 gpu_metrics->indep_throttle_status = 2945 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 2946 navi1x_throttler_map); 2947 2948 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 2949 2950 gpu_metrics->pcie_link_width = metrics.PcieWidth; 2951 gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate]; 2952 2953 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 2954 2955 if (metrics.CurrGfxVoltageOffset) 2956 gpu_metrics->voltage_gfx = 2957 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; 2958 if (metrics.CurrMemVidOffset) 2959 gpu_metrics->voltage_mem = 2960 (155000 - 625 * metrics.CurrMemVidOffset) / 100; 2961 if (metrics.CurrSocVoltageOffset) 2962 gpu_metrics->voltage_soc = 2963 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; 2964 2965 *table = (void *)gpu_metrics; 2966 2967 return sizeof(struct gpu_metrics_v1_3); 2968 } 2969 2970 static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu, 2971 void **table) 2972 { 2973 struct smu_table_context *smu_table = &smu->smu_table; 2974 struct gpu_metrics_v1_3 *gpu_metrics = 2975 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 2976 SmuMetrics_NV12_legacy_t metrics; 2977 int ret = 0; 2978 2979 ret = smu_cmn_get_metrics_table(smu, 2980 NULL, 2981 true); 2982 if (ret) 2983 return ret; 2984 2985 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_legacy_t)); 2986 2987 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 2988 2989 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 2990 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 2991 gpu_metrics->temperature_mem = metrics.TemperatureMem; 2992 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 2993 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 2994 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 2995 2996 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 2997 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 2998 2999 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 3000 3001 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 3002 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 3003 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 3004 3005 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator; 3006 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency; 3007 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency; 3008 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage; 3009 3010 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 3011 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 3012 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 3013 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 3014 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 3015 3016 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 3017 gpu_metrics->indep_throttle_status = 3018 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 3019 navi1x_throttler_map); 3020 3021 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 3022 3023 gpu_metrics->pcie_link_width = 3024 smu_v11_0_get_current_pcie_link_width(smu); 3025 gpu_metrics->pcie_link_speed = 3026 smu_v11_0_get_current_pcie_link_speed(smu); 3027 3028 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 3029 3030 if (metrics.CurrGfxVoltageOffset) 3031 gpu_metrics->voltage_gfx = 3032 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; 3033 if (metrics.CurrMemVidOffset) 3034 gpu_metrics->voltage_mem = 3035 (155000 - 625 * metrics.CurrMemVidOffset) / 100; 3036 if (metrics.CurrSocVoltageOffset) 3037 gpu_metrics->voltage_soc = 3038 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; 3039 3040 *table = (void *)gpu_metrics; 3041 3042 return sizeof(struct gpu_metrics_v1_3); 3043 } 3044 3045 static ssize_t navi12_get_gpu_metrics(struct smu_context *smu, 3046 void **table) 3047 { 3048 struct smu_table_context *smu_table = &smu->smu_table; 3049 struct gpu_metrics_v1_3 *gpu_metrics = 3050 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 3051 SmuMetrics_NV12_t metrics; 3052 int ret = 0; 3053 3054 ret = smu_cmn_get_metrics_table(smu, 3055 NULL, 3056 true); 3057 if (ret) 3058 return ret; 3059 3060 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_t)); 3061 3062 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 3063 3064 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 3065 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 3066 gpu_metrics->temperature_mem = metrics.TemperatureMem; 3067 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 3068 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 3069 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 3070 3071 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 3072 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 3073 3074 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 3075 3076 if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 3077 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs; 3078 else 3079 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs; 3080 3081 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 3082 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs; 3083 3084 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator; 3085 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency; 3086 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency; 3087 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage; 3088 3089 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 3090 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 3091 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 3092 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 3093 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 3094 3095 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 3096 gpu_metrics->indep_throttle_status = 3097 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 3098 navi1x_throttler_map); 3099 3100 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 3101 3102 gpu_metrics->pcie_link_width = metrics.PcieWidth; 3103 gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate]; 3104 3105 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 3106 3107 if (metrics.CurrGfxVoltageOffset) 3108 gpu_metrics->voltage_gfx = 3109 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100; 3110 if (metrics.CurrMemVidOffset) 3111 gpu_metrics->voltage_mem = 3112 (155000 - 625 * metrics.CurrMemVidOffset) / 100; 3113 if (metrics.CurrSocVoltageOffset) 3114 gpu_metrics->voltage_soc = 3115 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100; 3116 3117 *table = (void *)gpu_metrics; 3118 3119 return sizeof(struct gpu_metrics_v1_3); 3120 } 3121 3122 static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu, 3123 void **table) 3124 { 3125 struct amdgpu_device *adev = smu->adev; 3126 uint32_t smu_version; 3127 int ret = 0; 3128 3129 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 3130 if (ret) { 3131 dev_err(adev->dev, "Failed to get smu version!\n"); 3132 return ret; 3133 } 3134 3135 switch (adev->ip_versions[MP1_HWIP][0]) { 3136 case IP_VERSION(11, 0, 9): 3137 if (smu_version > 0x00341C00) 3138 ret = navi12_get_gpu_metrics(smu, table); 3139 else 3140 ret = navi12_get_legacy_gpu_metrics(smu, table); 3141 break; 3142 case IP_VERSION(11, 0, 0): 3143 case IP_VERSION(11, 0, 5): 3144 default: 3145 if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) || 3146 ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00)) 3147 ret = navi10_get_gpu_metrics(smu, table); 3148 else 3149 ret =navi10_get_legacy_gpu_metrics(smu, table); 3150 break; 3151 } 3152 3153 return ret; 3154 } 3155 3156 static int navi10_enable_mgpu_fan_boost(struct smu_context *smu) 3157 { 3158 struct smu_table_context *table_context = &smu->smu_table; 3159 PPTable_t *smc_pptable = table_context->driver_pptable; 3160 struct amdgpu_device *adev = smu->adev; 3161 uint32_t param = 0; 3162 3163 /* Navi12 does not support this */ 3164 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9)) 3165 return 0; 3166 3167 /* 3168 * Skip the MGpuFanBoost setting for those ASICs 3169 * which do not support it 3170 */ 3171 if (!smc_pptable->MGpuFanBoostLimitRpm) 3172 return 0; 3173 3174 /* Workaround for WS SKU */ 3175 if (adev->pdev->device == 0x7312 && 3176 adev->pdev->revision == 0) 3177 param = 0xD188; 3178 3179 return smu_cmn_send_smc_msg_with_param(smu, 3180 SMU_MSG_SetMGpuFanBoostLimitRpm, 3181 param, 3182 NULL); 3183 } 3184 3185 static int navi10_post_smu_init(struct smu_context *smu) 3186 { 3187 struct amdgpu_device *adev = smu->adev; 3188 int ret = 0; 3189 3190 if (amdgpu_sriov_vf(adev)) 3191 return 0; 3192 3193 ret = navi10_run_umc_cdr_workaround(smu); 3194 if (ret) { 3195 dev_err(adev->dev, "Failed to apply umc cdr workaround!\n"); 3196 return ret; 3197 } 3198 3199 if (!smu->dc_controlled_by_gpio) { 3200 /* 3201 * For Navi1X, manually switch it to AC mode as PMFW 3202 * may boot it with DC mode. 3203 */ 3204 ret = smu_v11_0_set_power_source(smu, 3205 adev->pm.ac_power ? 3206 SMU_POWER_SOURCE_AC : 3207 SMU_POWER_SOURCE_DC); 3208 if (ret) { 3209 dev_err(adev->dev, "Failed to switch to %s mode!\n", 3210 adev->pm.ac_power ? "AC" : "DC"); 3211 return ret; 3212 } 3213 } 3214 3215 return ret; 3216 } 3217 3218 static const struct pptable_funcs navi10_ppt_funcs = { 3219 .get_allowed_feature_mask = navi10_get_allowed_feature_mask, 3220 .set_default_dpm_table = navi10_set_default_dpm_table, 3221 .dpm_set_vcn_enable = navi10_dpm_set_vcn_enable, 3222 .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable, 3223 .i2c_init = navi10_i2c_control_init, 3224 .i2c_fini = navi10_i2c_control_fini, 3225 .print_clk_levels = navi10_print_clk_levels, 3226 .force_clk_levels = navi10_force_clk_levels, 3227 .populate_umd_state_clk = navi10_populate_umd_state_clk, 3228 .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency, 3229 .pre_display_config_changed = navi10_pre_display_config_changed, 3230 .display_config_changed = navi10_display_config_changed, 3231 .notify_smc_display_config = navi10_notify_smc_display_config, 3232 .is_dpm_running = navi10_is_dpm_running, 3233 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm, 3234 .get_fan_speed_rpm = navi10_get_fan_speed_rpm, 3235 .get_power_profile_mode = navi10_get_power_profile_mode, 3236 .set_power_profile_mode = navi10_set_power_profile_mode, 3237 .set_watermarks_table = navi10_set_watermarks_table, 3238 .read_sensor = navi10_read_sensor, 3239 .get_uclk_dpm_states = navi10_get_uclk_dpm_states, 3240 .set_performance_level = smu_v11_0_set_performance_level, 3241 .get_thermal_temperature_range = navi10_get_thermal_temperature_range, 3242 .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch, 3243 .get_power_limit = navi10_get_power_limit, 3244 .update_pcie_parameters = navi10_update_pcie_parameters, 3245 .init_microcode = smu_v11_0_init_microcode, 3246 .load_microcode = smu_v11_0_load_microcode, 3247 .fini_microcode = smu_v11_0_fini_microcode, 3248 .init_smc_tables = navi10_init_smc_tables, 3249 .fini_smc_tables = smu_v11_0_fini_smc_tables, 3250 .init_power = smu_v11_0_init_power, 3251 .fini_power = smu_v11_0_fini_power, 3252 .check_fw_status = smu_v11_0_check_fw_status, 3253 .setup_pptable = navi10_setup_pptable, 3254 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, 3255 .check_fw_version = smu_v11_0_check_fw_version, 3256 .write_pptable = smu_cmn_write_pptable, 3257 .set_driver_table_location = smu_v11_0_set_driver_table_location, 3258 .set_tool_table_location = smu_v11_0_set_tool_table_location, 3259 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 3260 .system_features_control = smu_v11_0_system_features_control, 3261 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 3262 .send_smc_msg = smu_cmn_send_smc_msg, 3263 .init_display_count = smu_v11_0_init_display_count, 3264 .set_allowed_mask = smu_v11_0_set_allowed_mask, 3265 .get_enabled_mask = smu_cmn_get_enabled_mask, 3266 .feature_is_enabled = smu_cmn_feature_is_enabled, 3267 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 3268 .notify_display_change = smu_v11_0_notify_display_change, 3269 .set_power_limit = smu_v11_0_set_power_limit, 3270 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks, 3271 .enable_thermal_alert = smu_v11_0_enable_thermal_alert, 3272 .disable_thermal_alert = smu_v11_0_disable_thermal_alert, 3273 .set_min_dcef_deep_sleep = smu_v11_0_set_min_deep_sleep_dcefclk, 3274 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request, 3275 .get_fan_control_mode = smu_v11_0_get_fan_control_mode, 3276 .set_fan_control_mode = smu_v11_0_set_fan_control_mode, 3277 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm, 3278 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm, 3279 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate, 3280 .gfx_off_control = smu_v11_0_gfx_off_control, 3281 .register_irq_handler = smu_v11_0_register_irq_handler, 3282 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme, 3283 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc, 3284 .baco_is_support = smu_v11_0_baco_is_support, 3285 .baco_get_state = smu_v11_0_baco_get_state, 3286 .baco_set_state = smu_v11_0_baco_set_state, 3287 .baco_enter = navi10_baco_enter, 3288 .baco_exit = navi10_baco_exit, 3289 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq, 3290 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, 3291 .set_default_od_settings = navi10_set_default_od_settings, 3292 .od_edit_dpm_table = navi10_od_edit_dpm_table, 3293 .restore_user_od_settings = smu_v11_0_restore_user_od_settings, 3294 .run_btc = navi10_run_btc, 3295 .set_power_source = smu_v11_0_set_power_source, 3296 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 3297 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 3298 .get_gpu_metrics = navi1x_get_gpu_metrics, 3299 .enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost, 3300 .gfx_ulv_control = smu_v11_0_gfx_ulv_control, 3301 .deep_sleep_control = smu_v11_0_deep_sleep_control, 3302 .get_fan_parameters = navi10_get_fan_parameters, 3303 .post_init = navi10_post_smu_init, 3304 .interrupt_work = smu_v11_0_interrupt_work, 3305 .set_mp1_state = smu_cmn_set_mp1_state, 3306 }; 3307 3308 void navi10_set_ppt_funcs(struct smu_context *smu) 3309 { 3310 smu->ppt_funcs = &navi10_ppt_funcs; 3311 smu->message_map = navi10_message_map; 3312 smu->clock_map = navi10_clk_map; 3313 smu->feature_map = navi10_feature_mask_map; 3314 smu->table_map = navi10_table_map; 3315 smu->pwr_src_map = navi10_pwr_src_map; 3316 smu->workload_map = navi10_workload_map; 3317 } 3318