1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include <linux/pci.h> 28 #include <linux/i2c.h> 29 #include "amdgpu.h" 30 #include "amdgpu_smu.h" 31 #include "atomfirmware.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "amdgpu_atombios.h" 34 #include "soc15_common.h" 35 #include "smu_v11_0.h" 36 #include "smu11_driver_if_navi10.h" 37 #include "atom.h" 38 #include "navi10_ppt.h" 39 #include "smu_v11_0_pptable.h" 40 #include "smu_v11_0_ppsmc.h" 41 #include "nbio/nbio_2_3_offset.h" 42 #include "nbio/nbio_2_3_sh_mask.h" 43 #include "thm/thm_11_0_2_offset.h" 44 #include "thm/thm_11_0_2_sh_mask.h" 45 46 #include "asic_reg/mp/mp_11_0_sh_mask.h" 47 #include "smu_cmn.h" 48 #include "smu_11_0_cdr_table.h" 49 50 /* 51 * DO NOT use these for err/warn/info/debug messages. 52 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 53 * They are more MGPU friendly. 54 */ 55 #undef pr_err 56 #undef pr_warn 57 #undef pr_info 58 #undef pr_debug 59 60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 61 62 #define FEATURE_MASK(feature) (1ULL << feature) 63 #define SMC_DPM_FEATURE ( \ 64 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \ 65 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 66 FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) | \ 70 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)) 72 73 #define SMU_11_0_GFX_BUSY_THRESHOLD 15 74 75 static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = { 76 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 77 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 78 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 79 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0), 80 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), 81 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 82 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 83 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1), 84 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1), 85 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1), 86 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1), 87 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1), 88 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1), 89 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 90 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 91 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0), 92 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0), 93 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 94 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 95 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0), 96 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 97 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 98 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable, 0), 99 MSG_MAP(RunBtc, PPSMC_MSG_RunBtc, 0), 100 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), 101 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0), 102 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0), 103 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1), 104 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 105 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), 106 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), 107 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 108 MSG_MAP(SetMemoryChannelConfig, PPSMC_MSG_SetMemoryChannelConfig, 0), 109 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0), 110 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0), 111 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0), 112 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0), 113 MSG_MAP(SetMinDeepSleepDcefclk, PPSMC_MSG_SetMinDeepSleepDcefclk, 0), 114 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0), 115 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0), 116 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0), 117 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0), 118 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1), 119 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 120 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 121 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 122 MSG_MAP(ConfigureGfxDidt, PPSMC_MSG_ConfigureGfxDidt, 0), 123 MSG_MAP(NumOfDisplays, PPSMC_MSG_NumOfDisplays, 0), 124 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0), 125 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0), 126 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 127 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 128 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 129 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1), 130 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0), 131 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0), 132 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset, 0), 133 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown, 0), 134 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 135 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 136 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 137 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 138 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0), 139 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0), 140 MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE,PPSMC_MSG_DALDisableDummyPstateChange, 0), 141 MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALEnableDummyPstateChange, 0), 142 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0), 143 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0), 144 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0), 145 MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH, PPSMC_MSG_SetDriverDummyTableDramAddrHigh, 0), 146 MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW, PPSMC_MSG_SetDriverDummyTableDramAddrLow, 0), 147 MSG_MAP(GET_UMC_FW_WA, PPSMC_MSG_GetUMCFWWA, 0), 148 }; 149 150 static struct cmn2asic_mapping navi10_clk_map[SMU_CLK_COUNT] = { 151 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 152 CLK_MAP(SCLK, PPCLK_GFXCLK), 153 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 154 CLK_MAP(FCLK, PPCLK_SOCCLK), 155 CLK_MAP(UCLK, PPCLK_UCLK), 156 CLK_MAP(MCLK, PPCLK_UCLK), 157 CLK_MAP(DCLK, PPCLK_DCLK), 158 CLK_MAP(VCLK, PPCLK_VCLK), 159 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK), 160 CLK_MAP(DISPCLK, PPCLK_DISPCLK), 161 CLK_MAP(PIXCLK, PPCLK_PIXCLK), 162 CLK_MAP(PHYCLK, PPCLK_PHYCLK), 163 }; 164 165 static struct cmn2asic_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = { 166 FEA_MAP(DPM_PREFETCHER), 167 FEA_MAP(DPM_GFXCLK), 168 FEA_MAP(DPM_GFX_PACE), 169 FEA_MAP(DPM_UCLK), 170 FEA_MAP(DPM_SOCCLK), 171 FEA_MAP(DPM_MP0CLK), 172 FEA_MAP(DPM_LINK), 173 FEA_MAP(DPM_DCEFCLK), 174 FEA_MAP(MEM_VDDCI_SCALING), 175 FEA_MAP(MEM_MVDD_SCALING), 176 FEA_MAP(DS_GFXCLK), 177 FEA_MAP(DS_SOCCLK), 178 FEA_MAP(DS_LCLK), 179 FEA_MAP(DS_DCEFCLK), 180 FEA_MAP(DS_UCLK), 181 FEA_MAP(GFX_ULV), 182 FEA_MAP(FW_DSTATE), 183 FEA_MAP(GFXOFF), 184 FEA_MAP(BACO), 185 FEA_MAP(VCN_PG), 186 FEA_MAP(JPEG_PG), 187 FEA_MAP(USB_PG), 188 FEA_MAP(RSMU_SMN_CG), 189 FEA_MAP(PPT), 190 FEA_MAP(TDC), 191 FEA_MAP(GFX_EDC), 192 FEA_MAP(APCC_PLUS), 193 FEA_MAP(GTHR), 194 FEA_MAP(ACDC), 195 FEA_MAP(VR0HOT), 196 FEA_MAP(VR1HOT), 197 FEA_MAP(FW_CTF), 198 FEA_MAP(FAN_CONTROL), 199 FEA_MAP(THERMAL), 200 FEA_MAP(GFX_DCS), 201 FEA_MAP(RM), 202 FEA_MAP(LED_DISPLAY), 203 FEA_MAP(GFX_SS), 204 FEA_MAP(OUT_OF_BAND_MONITOR), 205 FEA_MAP(TEMP_DEPENDENT_VMIN), 206 FEA_MAP(MMHUB_PG), 207 FEA_MAP(ATHUB_PG), 208 FEA_MAP(APCC_DFLL), 209 }; 210 211 static struct cmn2asic_mapping navi10_table_map[SMU_TABLE_COUNT] = { 212 TAB_MAP(PPTABLE), 213 TAB_MAP(WATERMARKS), 214 TAB_MAP(AVFS), 215 TAB_MAP(AVFS_PSM_DEBUG), 216 TAB_MAP(AVFS_FUSE_OVERRIDE), 217 TAB_MAP(PMSTATUSLOG), 218 TAB_MAP(SMU_METRICS), 219 TAB_MAP(DRIVER_SMU_CONFIG), 220 TAB_MAP(ACTIVITY_MONITOR_COEFF), 221 TAB_MAP(OVERDRIVE), 222 TAB_MAP(I2C_COMMANDS), 223 TAB_MAP(PACE), 224 }; 225 226 static struct cmn2asic_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { 227 PWR_MAP(AC), 228 PWR_MAP(DC), 229 }; 230 231 static struct cmn2asic_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 232 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), 233 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 234 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 235 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 236 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 237 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 238 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 239 }; 240 241 static bool is_asic_secure(struct smu_context *smu) 242 { 243 struct amdgpu_device *adev = smu->adev; 244 bool is_secure = true; 245 uint32_t mp0_fw_intf; 246 247 mp0_fw_intf = RREG32_PCIE(MP0_Public | 248 (smnMP0_FW_INTF & 0xffffffff)); 249 250 if (!(mp0_fw_intf & (1 << 19))) 251 is_secure = false; 252 253 return is_secure; 254 } 255 256 static int 257 navi10_get_allowed_feature_mask(struct smu_context *smu, 258 uint32_t *feature_mask, uint32_t num) 259 { 260 struct amdgpu_device *adev = smu->adev; 261 262 if (num > 2) 263 return -EINVAL; 264 265 memset(feature_mask, 0, sizeof(uint32_t) * num); 266 267 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) 268 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) 269 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) 270 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) 271 | FEATURE_MASK(FEATURE_PPT_BIT) 272 | FEATURE_MASK(FEATURE_TDC_BIT) 273 | FEATURE_MASK(FEATURE_GFX_EDC_BIT) 274 | FEATURE_MASK(FEATURE_APCC_PLUS_BIT) 275 | FEATURE_MASK(FEATURE_VR0HOT_BIT) 276 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) 277 | FEATURE_MASK(FEATURE_THERMAL_BIT) 278 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT) 279 | FEATURE_MASK(FEATURE_DS_LCLK_BIT) 280 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) 281 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) 282 | FEATURE_MASK(FEATURE_BACO_BIT) 283 | FEATURE_MASK(FEATURE_GFX_SS_BIT) 284 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) 285 | FEATURE_MASK(FEATURE_FW_CTF_BIT) 286 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT); 287 288 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) 289 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 290 291 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) 292 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); 293 294 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) 295 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); 296 297 if (adev->pm.pp_feature & PP_ULV_MASK) 298 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); 299 300 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) 301 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 302 303 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 304 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); 305 306 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) 307 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); 308 309 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB) 310 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT); 311 312 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN) 313 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT); 314 315 if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG) 316 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT); 317 318 if (smu->dc_controlled_by_gpio) 319 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT); 320 321 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) 322 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 323 324 /* DPM UCLK enablement should be skipped for navi10 A0 secure board */ 325 if (!(is_asic_secure(smu) && 326 (adev->asic_type == CHIP_NAVI10) && 327 (adev->rev_id == 0)) && 328 (adev->pm.pp_feature & PP_MCLK_DPM_MASK)) 329 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) 330 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) 331 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); 332 333 /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */ 334 if (is_asic_secure(smu) && 335 (adev->asic_type == CHIP_NAVI10) && 336 (adev->rev_id == 0)) 337 *(uint64_t *)feature_mask &= 338 ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT); 339 340 return 0; 341 } 342 343 static int navi10_check_powerplay_table(struct smu_context *smu) 344 { 345 struct smu_table_context *table_context = &smu->smu_table; 346 struct smu_11_0_powerplay_table *powerplay_table = 347 table_context->power_play_table; 348 struct smu_baco_context *smu_baco = &smu->smu_baco; 349 350 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC) 351 smu->dc_controlled_by_gpio = true; 352 353 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO || 354 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) 355 smu_baco->platform_support = true; 356 357 table_context->thermal_controller_type = 358 powerplay_table->thermal_controller_type; 359 360 /* 361 * Instead of having its own buffer space and get overdrive_table copied, 362 * smu->od_settings just points to the actual overdrive_table 363 */ 364 smu->od_settings = &powerplay_table->overdrive_table; 365 366 return 0; 367 } 368 369 static int navi10_append_powerplay_table(struct smu_context *smu) 370 { 371 struct amdgpu_device *adev = smu->adev; 372 struct smu_table_context *table_context = &smu->smu_table; 373 PPTable_t *smc_pptable = table_context->driver_pptable; 374 struct atom_smc_dpm_info_v4_5 *smc_dpm_table; 375 struct atom_smc_dpm_info_v4_7 *smc_dpm_table_v4_7; 376 int index, ret; 377 378 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 379 smc_dpm_info); 380 381 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL, 382 (uint8_t **)&smc_dpm_table); 383 if (ret) 384 return ret; 385 386 dev_info(adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n", 387 smc_dpm_table->table_header.format_revision, 388 smc_dpm_table->table_header.content_revision); 389 390 if (smc_dpm_table->table_header.format_revision != 4) { 391 dev_err(adev->dev, "smc_dpm_info table format revision is not 4!\n"); 392 return -EINVAL; 393 } 394 395 switch (smc_dpm_table->table_header.content_revision) { 396 case 5: /* nv10 and nv14 */ 397 memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers, 398 sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header)); 399 break; 400 case 7: /* nv12 */ 401 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL, 402 (uint8_t **)&smc_dpm_table_v4_7); 403 if (ret) 404 return ret; 405 memcpy(smc_pptable->I2cControllers, smc_dpm_table_v4_7->I2cControllers, 406 sizeof(*smc_dpm_table_v4_7) - sizeof(smc_dpm_table_v4_7->table_header)); 407 break; 408 default: 409 dev_err(smu->adev->dev, "smc_dpm_info with unsupported content revision %d!\n", 410 smc_dpm_table->table_header.content_revision); 411 return -EINVAL; 412 } 413 414 if (adev->pm.pp_feature & PP_GFXOFF_MASK) { 415 /* TODO: remove it once SMU fw fix it */ 416 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN; 417 } 418 419 return 0; 420 } 421 422 static int navi10_store_powerplay_table(struct smu_context *smu) 423 { 424 struct smu_table_context *table_context = &smu->smu_table; 425 struct smu_11_0_powerplay_table *powerplay_table = 426 table_context->power_play_table; 427 428 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 429 sizeof(PPTable_t)); 430 431 return 0; 432 } 433 434 static int navi10_set_mp1_state(struct smu_context *smu, 435 enum pp_mp1_state mp1_state) 436 { 437 struct amdgpu_device *adev = smu->adev; 438 uint32_t mp1_fw_flags; 439 int ret = 0; 440 441 ret = smu_cmn_set_mp1_state(smu, mp1_state); 442 if (ret) 443 return ret; 444 445 if (mp1_state == PP_MP1_STATE_UNLOAD) { 446 mp1_fw_flags = RREG32_PCIE(MP1_Public | 447 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); 448 449 mp1_fw_flags &= ~MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK; 450 451 WREG32_PCIE(MP1_Public | 452 (smnMP1_FIRMWARE_FLAGS & 0xffffffff), mp1_fw_flags); 453 } 454 455 return 0; 456 } 457 458 static int navi10_setup_pptable(struct smu_context *smu) 459 { 460 int ret = 0; 461 462 ret = smu_v11_0_setup_pptable(smu); 463 if (ret) 464 return ret; 465 466 ret = navi10_store_powerplay_table(smu); 467 if (ret) 468 return ret; 469 470 ret = navi10_append_powerplay_table(smu); 471 if (ret) 472 return ret; 473 474 ret = navi10_check_powerplay_table(smu); 475 if (ret) 476 return ret; 477 478 return ret; 479 } 480 481 static int navi10_tables_init(struct smu_context *smu) 482 { 483 struct smu_table_context *smu_table = &smu->smu_table; 484 struct smu_table *tables = smu_table->tables; 485 486 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 487 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 488 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 489 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 490 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_NV1X_t), 491 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 492 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 493 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 494 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t), 495 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 496 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 497 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 498 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, 499 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE, 500 AMDGPU_GEM_DOMAIN_VRAM); 501 502 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_NV1X_t), 503 GFP_KERNEL); 504 if (!smu_table->metrics_table) 505 goto err0_out; 506 smu_table->metrics_time = 0; 507 508 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1); 509 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 510 if (!smu_table->gpu_metrics_table) 511 goto err1_out; 512 513 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 514 if (!smu_table->watermarks_table) 515 goto err2_out; 516 517 return 0; 518 519 err2_out: 520 kfree(smu_table->gpu_metrics_table); 521 err1_out: 522 kfree(smu_table->metrics_table); 523 err0_out: 524 return -ENOMEM; 525 } 526 527 static int navi10_get_legacy_smu_metrics_data(struct smu_context *smu, 528 MetricsMember_t member, 529 uint32_t *value) 530 { 531 struct smu_table_context *smu_table= &smu->smu_table; 532 SmuMetrics_legacy_t *metrics = 533 (SmuMetrics_legacy_t *)smu_table->metrics_table; 534 int ret = 0; 535 536 mutex_lock(&smu->metrics_lock); 537 538 ret = smu_cmn_get_metrics_table_locked(smu, 539 NULL, 540 false); 541 if (ret) { 542 mutex_unlock(&smu->metrics_lock); 543 return ret; 544 } 545 546 switch (member) { 547 case METRICS_CURR_GFXCLK: 548 *value = metrics->CurrClock[PPCLK_GFXCLK]; 549 break; 550 case METRICS_CURR_SOCCLK: 551 *value = metrics->CurrClock[PPCLK_SOCCLK]; 552 break; 553 case METRICS_CURR_UCLK: 554 *value = metrics->CurrClock[PPCLK_UCLK]; 555 break; 556 case METRICS_CURR_VCLK: 557 *value = metrics->CurrClock[PPCLK_VCLK]; 558 break; 559 case METRICS_CURR_DCLK: 560 *value = metrics->CurrClock[PPCLK_DCLK]; 561 break; 562 case METRICS_CURR_DCEFCLK: 563 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 564 break; 565 case METRICS_AVERAGE_GFXCLK: 566 *value = metrics->AverageGfxclkFrequency; 567 break; 568 case METRICS_AVERAGE_SOCCLK: 569 *value = metrics->AverageSocclkFrequency; 570 break; 571 case METRICS_AVERAGE_UCLK: 572 *value = metrics->AverageUclkFrequency; 573 break; 574 case METRICS_AVERAGE_GFXACTIVITY: 575 *value = metrics->AverageGfxActivity; 576 break; 577 case METRICS_AVERAGE_MEMACTIVITY: 578 *value = metrics->AverageUclkActivity; 579 break; 580 case METRICS_AVERAGE_SOCKETPOWER: 581 *value = metrics->AverageSocketPower << 8; 582 break; 583 case METRICS_TEMPERATURE_EDGE: 584 *value = metrics->TemperatureEdge * 585 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 586 break; 587 case METRICS_TEMPERATURE_HOTSPOT: 588 *value = metrics->TemperatureHotspot * 589 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 590 break; 591 case METRICS_TEMPERATURE_MEM: 592 *value = metrics->TemperatureMem * 593 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 594 break; 595 case METRICS_TEMPERATURE_VRGFX: 596 *value = metrics->TemperatureVrGfx * 597 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 598 break; 599 case METRICS_TEMPERATURE_VRSOC: 600 *value = metrics->TemperatureVrSoc * 601 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 602 break; 603 case METRICS_THROTTLER_STATUS: 604 *value = metrics->ThrottlerStatus; 605 break; 606 case METRICS_CURR_FANSPEED: 607 *value = metrics->CurrFanSpeed; 608 break; 609 default: 610 *value = UINT_MAX; 611 break; 612 } 613 614 mutex_unlock(&smu->metrics_lock); 615 616 return ret; 617 } 618 619 static int navi10_get_smu_metrics_data(struct smu_context *smu, 620 MetricsMember_t member, 621 uint32_t *value) 622 { 623 struct smu_table_context *smu_table= &smu->smu_table; 624 SmuMetrics_t *metrics = 625 (SmuMetrics_t *)smu_table->metrics_table; 626 int ret = 0; 627 628 mutex_lock(&smu->metrics_lock); 629 630 ret = smu_cmn_get_metrics_table_locked(smu, 631 NULL, 632 false); 633 if (ret) { 634 mutex_unlock(&smu->metrics_lock); 635 return ret; 636 } 637 638 switch (member) { 639 case METRICS_CURR_GFXCLK: 640 *value = metrics->CurrClock[PPCLK_GFXCLK]; 641 break; 642 case METRICS_CURR_SOCCLK: 643 *value = metrics->CurrClock[PPCLK_SOCCLK]; 644 break; 645 case METRICS_CURR_UCLK: 646 *value = metrics->CurrClock[PPCLK_UCLK]; 647 break; 648 case METRICS_CURR_VCLK: 649 *value = metrics->CurrClock[PPCLK_VCLK]; 650 break; 651 case METRICS_CURR_DCLK: 652 *value = metrics->CurrClock[PPCLK_DCLK]; 653 break; 654 case METRICS_CURR_DCEFCLK: 655 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 656 break; 657 case METRICS_AVERAGE_GFXCLK: 658 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 659 *value = metrics->AverageGfxclkFrequencyPreDs; 660 else 661 *value = metrics->AverageGfxclkFrequencyPostDs; 662 break; 663 case METRICS_AVERAGE_SOCCLK: 664 *value = metrics->AverageSocclkFrequency; 665 break; 666 case METRICS_AVERAGE_UCLK: 667 *value = metrics->AverageUclkFrequencyPostDs; 668 break; 669 case METRICS_AVERAGE_GFXACTIVITY: 670 *value = metrics->AverageGfxActivity; 671 break; 672 case METRICS_AVERAGE_MEMACTIVITY: 673 *value = metrics->AverageUclkActivity; 674 break; 675 case METRICS_AVERAGE_SOCKETPOWER: 676 *value = metrics->AverageSocketPower << 8; 677 break; 678 case METRICS_TEMPERATURE_EDGE: 679 *value = metrics->TemperatureEdge * 680 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 681 break; 682 case METRICS_TEMPERATURE_HOTSPOT: 683 *value = metrics->TemperatureHotspot * 684 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 685 break; 686 case METRICS_TEMPERATURE_MEM: 687 *value = metrics->TemperatureMem * 688 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 689 break; 690 case METRICS_TEMPERATURE_VRGFX: 691 *value = metrics->TemperatureVrGfx * 692 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 693 break; 694 case METRICS_TEMPERATURE_VRSOC: 695 *value = metrics->TemperatureVrSoc * 696 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 697 break; 698 case METRICS_THROTTLER_STATUS: 699 *value = metrics->ThrottlerStatus; 700 break; 701 case METRICS_CURR_FANSPEED: 702 *value = metrics->CurrFanSpeed; 703 break; 704 default: 705 *value = UINT_MAX; 706 break; 707 } 708 709 mutex_unlock(&smu->metrics_lock); 710 711 return ret; 712 } 713 714 static int navi12_get_legacy_smu_metrics_data(struct smu_context *smu, 715 MetricsMember_t member, 716 uint32_t *value) 717 { 718 struct smu_table_context *smu_table= &smu->smu_table; 719 SmuMetrics_NV12_legacy_t *metrics = 720 (SmuMetrics_NV12_legacy_t *)smu_table->metrics_table; 721 int ret = 0; 722 723 mutex_lock(&smu->metrics_lock); 724 725 ret = smu_cmn_get_metrics_table_locked(smu, 726 NULL, 727 false); 728 if (ret) { 729 mutex_unlock(&smu->metrics_lock); 730 return ret; 731 } 732 733 switch (member) { 734 case METRICS_CURR_GFXCLK: 735 *value = metrics->CurrClock[PPCLK_GFXCLK]; 736 break; 737 case METRICS_CURR_SOCCLK: 738 *value = metrics->CurrClock[PPCLK_SOCCLK]; 739 break; 740 case METRICS_CURR_UCLK: 741 *value = metrics->CurrClock[PPCLK_UCLK]; 742 break; 743 case METRICS_CURR_VCLK: 744 *value = metrics->CurrClock[PPCLK_VCLK]; 745 break; 746 case METRICS_CURR_DCLK: 747 *value = metrics->CurrClock[PPCLK_DCLK]; 748 break; 749 case METRICS_CURR_DCEFCLK: 750 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 751 break; 752 case METRICS_AVERAGE_GFXCLK: 753 *value = metrics->AverageGfxclkFrequency; 754 break; 755 case METRICS_AVERAGE_SOCCLK: 756 *value = metrics->AverageSocclkFrequency; 757 break; 758 case METRICS_AVERAGE_UCLK: 759 *value = metrics->AverageUclkFrequency; 760 break; 761 case METRICS_AVERAGE_GFXACTIVITY: 762 *value = metrics->AverageGfxActivity; 763 break; 764 case METRICS_AVERAGE_MEMACTIVITY: 765 *value = metrics->AverageUclkActivity; 766 break; 767 case METRICS_AVERAGE_SOCKETPOWER: 768 *value = metrics->AverageSocketPower << 8; 769 break; 770 case METRICS_TEMPERATURE_EDGE: 771 *value = metrics->TemperatureEdge * 772 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 773 break; 774 case METRICS_TEMPERATURE_HOTSPOT: 775 *value = metrics->TemperatureHotspot * 776 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 777 break; 778 case METRICS_TEMPERATURE_MEM: 779 *value = metrics->TemperatureMem * 780 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 781 break; 782 case METRICS_TEMPERATURE_VRGFX: 783 *value = metrics->TemperatureVrGfx * 784 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 785 break; 786 case METRICS_TEMPERATURE_VRSOC: 787 *value = metrics->TemperatureVrSoc * 788 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 789 break; 790 case METRICS_THROTTLER_STATUS: 791 *value = metrics->ThrottlerStatus; 792 break; 793 case METRICS_CURR_FANSPEED: 794 *value = metrics->CurrFanSpeed; 795 break; 796 default: 797 *value = UINT_MAX; 798 break; 799 } 800 801 mutex_unlock(&smu->metrics_lock); 802 803 return ret; 804 } 805 806 static int navi12_get_smu_metrics_data(struct smu_context *smu, 807 MetricsMember_t member, 808 uint32_t *value) 809 { 810 struct smu_table_context *smu_table= &smu->smu_table; 811 SmuMetrics_NV12_t *metrics = 812 (SmuMetrics_NV12_t *)smu_table->metrics_table; 813 int ret = 0; 814 815 mutex_lock(&smu->metrics_lock); 816 817 ret = smu_cmn_get_metrics_table_locked(smu, 818 NULL, 819 false); 820 if (ret) { 821 mutex_unlock(&smu->metrics_lock); 822 return ret; 823 } 824 825 switch (member) { 826 case METRICS_CURR_GFXCLK: 827 *value = metrics->CurrClock[PPCLK_GFXCLK]; 828 break; 829 case METRICS_CURR_SOCCLK: 830 *value = metrics->CurrClock[PPCLK_SOCCLK]; 831 break; 832 case METRICS_CURR_UCLK: 833 *value = metrics->CurrClock[PPCLK_UCLK]; 834 break; 835 case METRICS_CURR_VCLK: 836 *value = metrics->CurrClock[PPCLK_VCLK]; 837 break; 838 case METRICS_CURR_DCLK: 839 *value = metrics->CurrClock[PPCLK_DCLK]; 840 break; 841 case METRICS_CURR_DCEFCLK: 842 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 843 break; 844 case METRICS_AVERAGE_GFXCLK: 845 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 846 *value = metrics->AverageGfxclkFrequencyPreDs; 847 else 848 *value = metrics->AverageGfxclkFrequencyPostDs; 849 break; 850 case METRICS_AVERAGE_SOCCLK: 851 *value = metrics->AverageSocclkFrequency; 852 break; 853 case METRICS_AVERAGE_UCLK: 854 *value = metrics->AverageUclkFrequencyPostDs; 855 break; 856 case METRICS_AVERAGE_GFXACTIVITY: 857 *value = metrics->AverageGfxActivity; 858 break; 859 case METRICS_AVERAGE_MEMACTIVITY: 860 *value = metrics->AverageUclkActivity; 861 break; 862 case METRICS_AVERAGE_SOCKETPOWER: 863 *value = metrics->AverageSocketPower << 8; 864 break; 865 case METRICS_TEMPERATURE_EDGE: 866 *value = metrics->TemperatureEdge * 867 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 868 break; 869 case METRICS_TEMPERATURE_HOTSPOT: 870 *value = metrics->TemperatureHotspot * 871 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 872 break; 873 case METRICS_TEMPERATURE_MEM: 874 *value = metrics->TemperatureMem * 875 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 876 break; 877 case METRICS_TEMPERATURE_VRGFX: 878 *value = metrics->TemperatureVrGfx * 879 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 880 break; 881 case METRICS_TEMPERATURE_VRSOC: 882 *value = metrics->TemperatureVrSoc * 883 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 884 break; 885 case METRICS_THROTTLER_STATUS: 886 *value = metrics->ThrottlerStatus; 887 break; 888 case METRICS_CURR_FANSPEED: 889 *value = metrics->CurrFanSpeed; 890 break; 891 default: 892 *value = UINT_MAX; 893 break; 894 } 895 896 mutex_unlock(&smu->metrics_lock); 897 898 return ret; 899 } 900 901 static int navi1x_get_smu_metrics_data(struct smu_context *smu, 902 MetricsMember_t member, 903 uint32_t *value) 904 { 905 struct amdgpu_device *adev = smu->adev; 906 uint32_t smu_version; 907 int ret = 0; 908 909 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 910 if (ret) { 911 dev_err(adev->dev, "Failed to get smu version!\n"); 912 return ret; 913 } 914 915 switch (adev->asic_type) { 916 case CHIP_NAVI12: 917 if (smu_version > 0x00341C00) 918 ret = navi12_get_smu_metrics_data(smu, member, value); 919 else 920 ret = navi12_get_legacy_smu_metrics_data(smu, member, value); 921 break; 922 case CHIP_NAVI10: 923 case CHIP_NAVI14: 924 default: 925 if (((adev->asic_type == CHIP_NAVI14) && smu_version > 0x00351F00) || 926 ((adev->asic_type == CHIP_NAVI10) && smu_version > 0x002A3B00)) 927 ret = navi10_get_smu_metrics_data(smu, member, value); 928 else 929 ret = navi10_get_legacy_smu_metrics_data(smu, member, value); 930 break; 931 } 932 933 return ret; 934 } 935 936 static int navi10_allocate_dpm_context(struct smu_context *smu) 937 { 938 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 939 940 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 941 GFP_KERNEL); 942 if (!smu_dpm->dpm_context) 943 return -ENOMEM; 944 945 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 946 947 return 0; 948 } 949 950 static int navi10_init_smc_tables(struct smu_context *smu) 951 { 952 int ret = 0; 953 954 ret = navi10_tables_init(smu); 955 if (ret) 956 return ret; 957 958 ret = navi10_allocate_dpm_context(smu); 959 if (ret) 960 return ret; 961 962 return smu_v11_0_init_smc_tables(smu); 963 } 964 965 static int navi10_set_default_dpm_table(struct smu_context *smu) 966 { 967 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 968 PPTable_t *driver_ppt = smu->smu_table.driver_pptable; 969 struct smu_11_0_dpm_table *dpm_table; 970 int ret = 0; 971 972 /* socclk dpm table setup */ 973 dpm_table = &dpm_context->dpm_tables.soc_table; 974 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 975 ret = smu_v11_0_set_single_dpm_table(smu, 976 SMU_SOCCLK, 977 dpm_table); 978 if (ret) 979 return ret; 980 dpm_table->is_fine_grained = 981 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete; 982 } else { 983 dpm_table->count = 1; 984 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 985 dpm_table->dpm_levels[0].enabled = true; 986 dpm_table->min = dpm_table->dpm_levels[0].value; 987 dpm_table->max = dpm_table->dpm_levels[0].value; 988 } 989 990 /* gfxclk dpm table setup */ 991 dpm_table = &dpm_context->dpm_tables.gfx_table; 992 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 993 ret = smu_v11_0_set_single_dpm_table(smu, 994 SMU_GFXCLK, 995 dpm_table); 996 if (ret) 997 return ret; 998 dpm_table->is_fine_grained = 999 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete; 1000 } else { 1001 dpm_table->count = 1; 1002 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 1003 dpm_table->dpm_levels[0].enabled = true; 1004 dpm_table->min = dpm_table->dpm_levels[0].value; 1005 dpm_table->max = dpm_table->dpm_levels[0].value; 1006 } 1007 1008 /* uclk dpm table setup */ 1009 dpm_table = &dpm_context->dpm_tables.uclk_table; 1010 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1011 ret = smu_v11_0_set_single_dpm_table(smu, 1012 SMU_UCLK, 1013 dpm_table); 1014 if (ret) 1015 return ret; 1016 dpm_table->is_fine_grained = 1017 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete; 1018 } else { 1019 dpm_table->count = 1; 1020 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 1021 dpm_table->dpm_levels[0].enabled = true; 1022 dpm_table->min = dpm_table->dpm_levels[0].value; 1023 dpm_table->max = dpm_table->dpm_levels[0].value; 1024 } 1025 1026 /* vclk dpm table setup */ 1027 dpm_table = &dpm_context->dpm_tables.vclk_table; 1028 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1029 ret = smu_v11_0_set_single_dpm_table(smu, 1030 SMU_VCLK, 1031 dpm_table); 1032 if (ret) 1033 return ret; 1034 dpm_table->is_fine_grained = 1035 !driver_ppt->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete; 1036 } else { 1037 dpm_table->count = 1; 1038 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; 1039 dpm_table->dpm_levels[0].enabled = true; 1040 dpm_table->min = dpm_table->dpm_levels[0].value; 1041 dpm_table->max = dpm_table->dpm_levels[0].value; 1042 } 1043 1044 /* dclk dpm table setup */ 1045 dpm_table = &dpm_context->dpm_tables.dclk_table; 1046 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1047 ret = smu_v11_0_set_single_dpm_table(smu, 1048 SMU_DCLK, 1049 dpm_table); 1050 if (ret) 1051 return ret; 1052 dpm_table->is_fine_grained = 1053 !driver_ppt->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete; 1054 } else { 1055 dpm_table->count = 1; 1056 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; 1057 dpm_table->dpm_levels[0].enabled = true; 1058 dpm_table->min = dpm_table->dpm_levels[0].value; 1059 dpm_table->max = dpm_table->dpm_levels[0].value; 1060 } 1061 1062 /* dcefclk dpm table setup */ 1063 dpm_table = &dpm_context->dpm_tables.dcef_table; 1064 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1065 ret = smu_v11_0_set_single_dpm_table(smu, 1066 SMU_DCEFCLK, 1067 dpm_table); 1068 if (ret) 1069 return ret; 1070 dpm_table->is_fine_grained = 1071 !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete; 1072 } else { 1073 dpm_table->count = 1; 1074 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1075 dpm_table->dpm_levels[0].enabled = true; 1076 dpm_table->min = dpm_table->dpm_levels[0].value; 1077 dpm_table->max = dpm_table->dpm_levels[0].value; 1078 } 1079 1080 /* pixelclk dpm table setup */ 1081 dpm_table = &dpm_context->dpm_tables.pixel_table; 1082 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1083 ret = smu_v11_0_set_single_dpm_table(smu, 1084 SMU_PIXCLK, 1085 dpm_table); 1086 if (ret) 1087 return ret; 1088 dpm_table->is_fine_grained = 1089 !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete; 1090 } else { 1091 dpm_table->count = 1; 1092 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1093 dpm_table->dpm_levels[0].enabled = true; 1094 dpm_table->min = dpm_table->dpm_levels[0].value; 1095 dpm_table->max = dpm_table->dpm_levels[0].value; 1096 } 1097 1098 /* displayclk dpm table setup */ 1099 dpm_table = &dpm_context->dpm_tables.display_table; 1100 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1101 ret = smu_v11_0_set_single_dpm_table(smu, 1102 SMU_DISPCLK, 1103 dpm_table); 1104 if (ret) 1105 return ret; 1106 dpm_table->is_fine_grained = 1107 !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete; 1108 } else { 1109 dpm_table->count = 1; 1110 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1111 dpm_table->dpm_levels[0].enabled = true; 1112 dpm_table->min = dpm_table->dpm_levels[0].value; 1113 dpm_table->max = dpm_table->dpm_levels[0].value; 1114 } 1115 1116 /* phyclk dpm table setup */ 1117 dpm_table = &dpm_context->dpm_tables.phy_table; 1118 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1119 ret = smu_v11_0_set_single_dpm_table(smu, 1120 SMU_PHYCLK, 1121 dpm_table); 1122 if (ret) 1123 return ret; 1124 dpm_table->is_fine_grained = 1125 !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete; 1126 } else { 1127 dpm_table->count = 1; 1128 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1129 dpm_table->dpm_levels[0].enabled = true; 1130 dpm_table->min = dpm_table->dpm_levels[0].value; 1131 dpm_table->max = dpm_table->dpm_levels[0].value; 1132 } 1133 1134 return 0; 1135 } 1136 1137 static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 1138 { 1139 int ret = 0; 1140 1141 if (enable) { 1142 /* vcn dpm on is a prerequisite for vcn power gate messages */ 1143 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1144 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL); 1145 if (ret) 1146 return ret; 1147 } 1148 } else { 1149 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1150 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL); 1151 if (ret) 1152 return ret; 1153 } 1154 } 1155 1156 return ret; 1157 } 1158 1159 static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 1160 { 1161 int ret = 0; 1162 1163 if (enable) { 1164 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 1165 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerUpJpeg, NULL); 1166 if (ret) 1167 return ret; 1168 } 1169 } else { 1170 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 1171 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL); 1172 if (ret) 1173 return ret; 1174 } 1175 } 1176 1177 return ret; 1178 } 1179 1180 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu, 1181 enum smu_clk_type clk_type, 1182 uint32_t *value) 1183 { 1184 MetricsMember_t member_type; 1185 int clk_id = 0; 1186 1187 clk_id = smu_cmn_to_asic_specific_index(smu, 1188 CMN2ASIC_MAPPING_CLK, 1189 clk_type); 1190 if (clk_id < 0) 1191 return clk_id; 1192 1193 switch (clk_id) { 1194 case PPCLK_GFXCLK: 1195 member_type = METRICS_CURR_GFXCLK; 1196 break; 1197 case PPCLK_UCLK: 1198 member_type = METRICS_CURR_UCLK; 1199 break; 1200 case PPCLK_SOCCLK: 1201 member_type = METRICS_CURR_SOCCLK; 1202 break; 1203 case PPCLK_VCLK: 1204 member_type = METRICS_CURR_VCLK; 1205 break; 1206 case PPCLK_DCLK: 1207 member_type = METRICS_CURR_DCLK; 1208 break; 1209 case PPCLK_DCEFCLK: 1210 member_type = METRICS_CURR_DCEFCLK; 1211 break; 1212 default: 1213 return -EINVAL; 1214 } 1215 1216 return navi1x_get_smu_metrics_data(smu, 1217 member_type, 1218 value); 1219 } 1220 1221 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) 1222 { 1223 PPTable_t *pptable = smu->smu_table.driver_pptable; 1224 DpmDescriptor_t *dpm_desc = NULL; 1225 uint32_t clk_index = 0; 1226 1227 clk_index = smu_cmn_to_asic_specific_index(smu, 1228 CMN2ASIC_MAPPING_CLK, 1229 clk_type); 1230 dpm_desc = &pptable->DpmDescriptor[clk_index]; 1231 1232 /* 0 - Fine grained DPM, 1 - Discrete DPM */ 1233 return dpm_desc->SnapToDiscrete == 0; 1234 } 1235 1236 static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap) 1237 { 1238 return od_table->cap[cap]; 1239 } 1240 1241 static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table, 1242 enum SMU_11_0_ODSETTING_ID setting, 1243 uint32_t *min, uint32_t *max) 1244 { 1245 if (min) 1246 *min = od_table->min[setting]; 1247 if (max) 1248 *max = od_table->max[setting]; 1249 } 1250 1251 static int navi10_print_clk_levels(struct smu_context *smu, 1252 enum smu_clk_type clk_type, char *buf) 1253 { 1254 uint16_t *curve_settings; 1255 int i, size = 0, ret = 0; 1256 uint32_t cur_value = 0, value = 0, count = 0; 1257 uint32_t freq_values[3] = {0}; 1258 uint32_t mark_index = 0; 1259 struct smu_table_context *table_context = &smu->smu_table; 1260 uint32_t gen_speed, lane_width; 1261 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1262 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1263 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable; 1264 OverDriveTable_t *od_table = 1265 (OverDriveTable_t *)table_context->overdrive_table; 1266 struct smu_11_0_overdrive_table *od_settings = smu->od_settings; 1267 uint32_t min_value, max_value; 1268 1269 switch (clk_type) { 1270 case SMU_GFXCLK: 1271 case SMU_SCLK: 1272 case SMU_SOCCLK: 1273 case SMU_MCLK: 1274 case SMU_UCLK: 1275 case SMU_FCLK: 1276 case SMU_DCEFCLK: 1277 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value); 1278 if (ret) 1279 return size; 1280 1281 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); 1282 if (ret) 1283 return size; 1284 1285 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) { 1286 for (i = 0; i < count; i++) { 1287 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); 1288 if (ret) 1289 return size; 1290 1291 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, 1292 cur_value == value ? "*" : ""); 1293 } 1294 } else { 1295 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]); 1296 if (ret) 1297 return size; 1298 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]); 1299 if (ret) 1300 return size; 1301 1302 freq_values[1] = cur_value; 1303 mark_index = cur_value == freq_values[0] ? 0 : 1304 cur_value == freq_values[2] ? 2 : 1; 1305 if (mark_index != 1) 1306 freq_values[1] = (freq_values[0] + freq_values[2]) / 2; 1307 1308 for (i = 0; i < 3; i++) { 1309 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i], 1310 i == mark_index ? "*" : ""); 1311 } 1312 1313 } 1314 break; 1315 case SMU_PCIE: 1316 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); 1317 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); 1318 for (i = 0; i < NUM_LINK_LEVELS; i++) 1319 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i, 1320 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," : 1321 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," : 1322 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," : 1323 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "", 1324 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" : 1325 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" : 1326 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" : 1327 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" : 1328 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" : 1329 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "", 1330 pptable->LclkFreq[i], 1331 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && 1332 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? 1333 "*" : ""); 1334 break; 1335 case SMU_OD_SCLK: 1336 if (!smu->od_enabled || !od_table || !od_settings) 1337 break; 1338 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) 1339 break; 1340 size += sprintf(buf + size, "OD_SCLK:\n"); 1341 size += sprintf(buf + size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax); 1342 break; 1343 case SMU_OD_MCLK: 1344 if (!smu->od_enabled || !od_table || !od_settings) 1345 break; 1346 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) 1347 break; 1348 size += sprintf(buf + size, "OD_MCLK:\n"); 1349 size += sprintf(buf + size, "1: %uMHz\n", od_table->UclkFmax); 1350 break; 1351 case SMU_OD_VDDC_CURVE: 1352 if (!smu->od_enabled || !od_table || !od_settings) 1353 break; 1354 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) 1355 break; 1356 size += sprintf(buf + size, "OD_VDDC_CURVE:\n"); 1357 for (i = 0; i < 3; i++) { 1358 switch (i) { 1359 case 0: 1360 curve_settings = &od_table->GfxclkFreq1; 1361 break; 1362 case 1: 1363 curve_settings = &od_table->GfxclkFreq2; 1364 break; 1365 case 2: 1366 curve_settings = &od_table->GfxclkFreq3; 1367 break; 1368 default: 1369 break; 1370 } 1371 size += sprintf(buf + size, "%d: %uMHz %umV\n", i, curve_settings[0], curve_settings[1] / NAVI10_VOLTAGE_SCALE); 1372 } 1373 break; 1374 case SMU_OD_RANGE: 1375 if (!smu->od_enabled || !od_table || !od_settings) 1376 break; 1377 size = sprintf(buf, "%s:\n", "OD_RANGE"); 1378 1379 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) { 1380 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN, 1381 &min_value, NULL); 1382 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX, 1383 NULL, &max_value); 1384 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n", 1385 min_value, max_value); 1386 } 1387 1388 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) { 1389 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX, 1390 &min_value, &max_value); 1391 size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n", 1392 min_value, max_value); 1393 } 1394 1395 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) { 1396 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1, 1397 &min_value, &max_value); 1398 size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n", 1399 min_value, max_value); 1400 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1, 1401 &min_value, &max_value); 1402 size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n", 1403 min_value, max_value); 1404 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2, 1405 &min_value, &max_value); 1406 size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n", 1407 min_value, max_value); 1408 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2, 1409 &min_value, &max_value); 1410 size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n", 1411 min_value, max_value); 1412 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3, 1413 &min_value, &max_value); 1414 size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n", 1415 min_value, max_value); 1416 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3, 1417 &min_value, &max_value); 1418 size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n", 1419 min_value, max_value); 1420 } 1421 1422 break; 1423 default: 1424 break; 1425 } 1426 1427 return size; 1428 } 1429 1430 static int navi10_force_clk_levels(struct smu_context *smu, 1431 enum smu_clk_type clk_type, uint32_t mask) 1432 { 1433 1434 int ret = 0, size = 0; 1435 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; 1436 1437 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1438 soft_max_level = mask ? (fls(mask) - 1) : 0; 1439 1440 switch (clk_type) { 1441 case SMU_GFXCLK: 1442 case SMU_SCLK: 1443 case SMU_SOCCLK: 1444 case SMU_MCLK: 1445 case SMU_UCLK: 1446 case SMU_DCEFCLK: 1447 case SMU_FCLK: 1448 /* There is only 2 levels for fine grained DPM */ 1449 if (navi10_is_support_fine_grained_dpm(smu, clk_type)) { 1450 soft_max_level = (soft_max_level >= 1 ? 1 : 0); 1451 soft_min_level = (soft_min_level >= 1 ? 1 : 0); 1452 } 1453 1454 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); 1455 if (ret) 1456 return size; 1457 1458 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq); 1459 if (ret) 1460 return size; 1461 1462 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 1463 if (ret) 1464 return size; 1465 break; 1466 default: 1467 break; 1468 } 1469 1470 return size; 1471 } 1472 1473 static int navi10_populate_umd_state_clk(struct smu_context *smu) 1474 { 1475 struct smu_11_0_dpm_context *dpm_context = 1476 smu->smu_dpm.dpm_context; 1477 struct smu_11_0_dpm_table *gfx_table = 1478 &dpm_context->dpm_tables.gfx_table; 1479 struct smu_11_0_dpm_table *mem_table = 1480 &dpm_context->dpm_tables.uclk_table; 1481 struct smu_11_0_dpm_table *soc_table = 1482 &dpm_context->dpm_tables.soc_table; 1483 struct smu_umd_pstate_table *pstate_table = 1484 &smu->pstate_table; 1485 struct amdgpu_device *adev = smu->adev; 1486 uint32_t sclk_freq; 1487 1488 pstate_table->gfxclk_pstate.min = gfx_table->min; 1489 switch (adev->asic_type) { 1490 case CHIP_NAVI10: 1491 switch (adev->pdev->revision) { 1492 case 0xf0: /* XTX */ 1493 case 0xc0: 1494 sclk_freq = NAVI10_PEAK_SCLK_XTX; 1495 break; 1496 case 0xf1: /* XT */ 1497 case 0xc1: 1498 sclk_freq = NAVI10_PEAK_SCLK_XT; 1499 break; 1500 default: /* XL */ 1501 sclk_freq = NAVI10_PEAK_SCLK_XL; 1502 break; 1503 } 1504 break; 1505 case CHIP_NAVI14: 1506 switch (adev->pdev->revision) { 1507 case 0xc7: /* XT */ 1508 case 0xf4: 1509 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK; 1510 break; 1511 case 0xc1: /* XTM */ 1512 case 0xf2: 1513 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK; 1514 break; 1515 case 0xc3: /* XLM */ 1516 case 0xf3: 1517 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK; 1518 break; 1519 case 0xc5: /* XTX */ 1520 case 0xf6: 1521 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK; 1522 break; 1523 default: /* XL */ 1524 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK; 1525 break; 1526 } 1527 break; 1528 case CHIP_NAVI12: 1529 sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK; 1530 break; 1531 default: 1532 sclk_freq = gfx_table->dpm_levels[gfx_table->count - 1].value; 1533 break; 1534 } 1535 pstate_table->gfxclk_pstate.peak = sclk_freq; 1536 1537 pstate_table->uclk_pstate.min = mem_table->min; 1538 pstate_table->uclk_pstate.peak = mem_table->max; 1539 1540 pstate_table->socclk_pstate.min = soc_table->min; 1541 pstate_table->socclk_pstate.peak = soc_table->max; 1542 1543 if (gfx_table->max > NAVI10_UMD_PSTATE_PROFILING_GFXCLK && 1544 mem_table->max > NAVI10_UMD_PSTATE_PROFILING_MEMCLK && 1545 soc_table->max > NAVI10_UMD_PSTATE_PROFILING_SOCCLK) { 1546 pstate_table->gfxclk_pstate.standard = 1547 NAVI10_UMD_PSTATE_PROFILING_GFXCLK; 1548 pstate_table->uclk_pstate.standard = 1549 NAVI10_UMD_PSTATE_PROFILING_MEMCLK; 1550 pstate_table->socclk_pstate.standard = 1551 NAVI10_UMD_PSTATE_PROFILING_SOCCLK; 1552 } else { 1553 pstate_table->gfxclk_pstate.standard = 1554 pstate_table->gfxclk_pstate.min; 1555 pstate_table->uclk_pstate.standard = 1556 pstate_table->uclk_pstate.min; 1557 pstate_table->socclk_pstate.standard = 1558 pstate_table->socclk_pstate.min; 1559 } 1560 1561 return 0; 1562 } 1563 1564 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu, 1565 enum smu_clk_type clk_type, 1566 struct pp_clock_levels_with_latency *clocks) 1567 { 1568 int ret = 0, i = 0; 1569 uint32_t level_count = 0, freq = 0; 1570 1571 switch (clk_type) { 1572 case SMU_GFXCLK: 1573 case SMU_DCEFCLK: 1574 case SMU_SOCCLK: 1575 case SMU_MCLK: 1576 case SMU_UCLK: 1577 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &level_count); 1578 if (ret) 1579 return ret; 1580 1581 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS); 1582 clocks->num_levels = level_count; 1583 1584 for (i = 0; i < level_count; i++) { 1585 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &freq); 1586 if (ret) 1587 return ret; 1588 1589 clocks->data[i].clocks_in_khz = freq * 1000; 1590 clocks->data[i].latency_in_us = 0; 1591 } 1592 break; 1593 default: 1594 break; 1595 } 1596 1597 return ret; 1598 } 1599 1600 static int navi10_pre_display_config_changed(struct smu_context *smu) 1601 { 1602 int ret = 0; 1603 uint32_t max_freq = 0; 1604 1605 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL); 1606 if (ret) 1607 return ret; 1608 1609 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1610 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq); 1611 if (ret) 1612 return ret; 1613 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq); 1614 if (ret) 1615 return ret; 1616 } 1617 1618 return ret; 1619 } 1620 1621 static int navi10_display_config_changed(struct smu_context *smu) 1622 { 1623 int ret = 0; 1624 1625 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1626 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) && 1627 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 1628 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 1629 smu->display_config->num_display, 1630 NULL); 1631 if (ret) 1632 return ret; 1633 } 1634 1635 return ret; 1636 } 1637 1638 static bool navi10_is_dpm_running(struct smu_context *smu) 1639 { 1640 int ret = 0; 1641 uint32_t feature_mask[2]; 1642 uint64_t feature_enabled; 1643 1644 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2); 1645 if (ret) 1646 return false; 1647 1648 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0]; 1649 1650 return !!(feature_enabled & SMC_DPM_FEATURE); 1651 } 1652 1653 static int navi10_get_fan_speed_percent(struct smu_context *smu, 1654 uint32_t *speed) 1655 { 1656 int ret; 1657 u32 rpm; 1658 1659 if (!speed) 1660 return -EINVAL; 1661 1662 switch (smu_v11_0_get_fan_control_mode(smu)) { 1663 case AMD_FAN_CTRL_AUTO: 1664 ret = navi1x_get_smu_metrics_data(smu, 1665 METRICS_CURR_FANSPEED, 1666 &rpm); 1667 if (!ret && smu->fan_max_rpm) 1668 *speed = rpm * 100 / smu->fan_max_rpm; 1669 return ret; 1670 default: 1671 *speed = smu->user_dpm_profile.fan_speed_percent; 1672 return 0; 1673 } 1674 } 1675 1676 static int navi10_get_fan_parameters(struct smu_context *smu) 1677 { 1678 PPTable_t *pptable = smu->smu_table.driver_pptable; 1679 1680 smu->fan_max_rpm = pptable->FanMaximumRpm; 1681 1682 return 0; 1683 } 1684 1685 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf) 1686 { 1687 DpmActivityMonitorCoeffInt_t activity_monitor; 1688 uint32_t i, size = 0; 1689 int16_t workload_type = 0; 1690 static const char *profile_name[] = { 1691 "BOOTUP_DEFAULT", 1692 "3D_FULL_SCREEN", 1693 "POWER_SAVING", 1694 "VIDEO", 1695 "VR", 1696 "COMPUTE", 1697 "CUSTOM"}; 1698 static const char *title[] = { 1699 "PROFILE_INDEX(NAME)", 1700 "CLOCK_TYPE(NAME)", 1701 "FPS", 1702 "MinFreqType", 1703 "MinActiveFreqType", 1704 "MinActiveFreq", 1705 "BoosterFreqType", 1706 "BoosterFreq", 1707 "PD_Data_limit_c", 1708 "PD_Data_error_coeff", 1709 "PD_Data_error_rate_coeff"}; 1710 int result = 0; 1711 1712 if (!buf) 1713 return -EINVAL; 1714 1715 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n", 1716 title[0], title[1], title[2], title[3], title[4], title[5], 1717 title[6], title[7], title[8], title[9], title[10]); 1718 1719 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1720 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1721 workload_type = smu_cmn_to_asic_specific_index(smu, 1722 CMN2ASIC_MAPPING_WORKLOAD, 1723 i); 1724 if (workload_type < 0) 1725 return -EINVAL; 1726 1727 result = smu_cmn_update_table(smu, 1728 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type, 1729 (void *)(&activity_monitor), false); 1730 if (result) { 1731 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1732 return result; 1733 } 1734 1735 size += sprintf(buf + size, "%2d %14s%s:\n", 1736 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1737 1738 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1739 " ", 1740 0, 1741 "GFXCLK", 1742 activity_monitor.Gfx_FPS, 1743 activity_monitor.Gfx_MinFreqStep, 1744 activity_monitor.Gfx_MinActiveFreqType, 1745 activity_monitor.Gfx_MinActiveFreq, 1746 activity_monitor.Gfx_BoosterFreqType, 1747 activity_monitor.Gfx_BoosterFreq, 1748 activity_monitor.Gfx_PD_Data_limit_c, 1749 activity_monitor.Gfx_PD_Data_error_coeff, 1750 activity_monitor.Gfx_PD_Data_error_rate_coeff); 1751 1752 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1753 " ", 1754 1, 1755 "SOCCLK", 1756 activity_monitor.Soc_FPS, 1757 activity_monitor.Soc_MinFreqStep, 1758 activity_monitor.Soc_MinActiveFreqType, 1759 activity_monitor.Soc_MinActiveFreq, 1760 activity_monitor.Soc_BoosterFreqType, 1761 activity_monitor.Soc_BoosterFreq, 1762 activity_monitor.Soc_PD_Data_limit_c, 1763 activity_monitor.Soc_PD_Data_error_coeff, 1764 activity_monitor.Soc_PD_Data_error_rate_coeff); 1765 1766 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1767 " ", 1768 2, 1769 "MEMLK", 1770 activity_monitor.Mem_FPS, 1771 activity_monitor.Mem_MinFreqStep, 1772 activity_monitor.Mem_MinActiveFreqType, 1773 activity_monitor.Mem_MinActiveFreq, 1774 activity_monitor.Mem_BoosterFreqType, 1775 activity_monitor.Mem_BoosterFreq, 1776 activity_monitor.Mem_PD_Data_limit_c, 1777 activity_monitor.Mem_PD_Data_error_coeff, 1778 activity_monitor.Mem_PD_Data_error_rate_coeff); 1779 } 1780 1781 return size; 1782 } 1783 1784 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 1785 { 1786 DpmActivityMonitorCoeffInt_t activity_monitor; 1787 int workload_type, ret = 0; 1788 1789 smu->power_profile_mode = input[size]; 1790 1791 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 1792 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode); 1793 return -EINVAL; 1794 } 1795 1796 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 1797 1798 ret = smu_cmn_update_table(smu, 1799 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1800 (void *)(&activity_monitor), false); 1801 if (ret) { 1802 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1803 return ret; 1804 } 1805 1806 switch (input[0]) { 1807 case 0: /* Gfxclk */ 1808 activity_monitor.Gfx_FPS = input[1]; 1809 activity_monitor.Gfx_MinFreqStep = input[2]; 1810 activity_monitor.Gfx_MinActiveFreqType = input[3]; 1811 activity_monitor.Gfx_MinActiveFreq = input[4]; 1812 activity_monitor.Gfx_BoosterFreqType = input[5]; 1813 activity_monitor.Gfx_BoosterFreq = input[6]; 1814 activity_monitor.Gfx_PD_Data_limit_c = input[7]; 1815 activity_monitor.Gfx_PD_Data_error_coeff = input[8]; 1816 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9]; 1817 break; 1818 case 1: /* Socclk */ 1819 activity_monitor.Soc_FPS = input[1]; 1820 activity_monitor.Soc_MinFreqStep = input[2]; 1821 activity_monitor.Soc_MinActiveFreqType = input[3]; 1822 activity_monitor.Soc_MinActiveFreq = input[4]; 1823 activity_monitor.Soc_BoosterFreqType = input[5]; 1824 activity_monitor.Soc_BoosterFreq = input[6]; 1825 activity_monitor.Soc_PD_Data_limit_c = input[7]; 1826 activity_monitor.Soc_PD_Data_error_coeff = input[8]; 1827 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9]; 1828 break; 1829 case 2: /* Memlk */ 1830 activity_monitor.Mem_FPS = input[1]; 1831 activity_monitor.Mem_MinFreqStep = input[2]; 1832 activity_monitor.Mem_MinActiveFreqType = input[3]; 1833 activity_monitor.Mem_MinActiveFreq = input[4]; 1834 activity_monitor.Mem_BoosterFreqType = input[5]; 1835 activity_monitor.Mem_BoosterFreq = input[6]; 1836 activity_monitor.Mem_PD_Data_limit_c = input[7]; 1837 activity_monitor.Mem_PD_Data_error_coeff = input[8]; 1838 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9]; 1839 break; 1840 } 1841 1842 ret = smu_cmn_update_table(smu, 1843 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1844 (void *)(&activity_monitor), true); 1845 if (ret) { 1846 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 1847 return ret; 1848 } 1849 } 1850 1851 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1852 workload_type = smu_cmn_to_asic_specific_index(smu, 1853 CMN2ASIC_MAPPING_WORKLOAD, 1854 smu->power_profile_mode); 1855 if (workload_type < 0) 1856 return -EINVAL; 1857 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 1858 1 << workload_type, NULL); 1859 1860 return ret; 1861 } 1862 1863 static int navi10_notify_smc_display_config(struct smu_context *smu) 1864 { 1865 struct smu_clocks min_clocks = {0}; 1866 struct pp_display_clock_request clock_req; 1867 int ret = 0; 1868 1869 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; 1870 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; 1871 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; 1872 1873 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1874 clock_req.clock_type = amd_pp_dcef_clock; 1875 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; 1876 1877 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req); 1878 if (!ret) { 1879 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) { 1880 ret = smu_cmn_send_smc_msg_with_param(smu, 1881 SMU_MSG_SetMinDeepSleepDcefclk, 1882 min_clocks.dcef_clock_in_sr/100, 1883 NULL); 1884 if (ret) { 1885 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!"); 1886 return ret; 1887 } 1888 } 1889 } else { 1890 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!"); 1891 } 1892 } 1893 1894 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1895 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); 1896 if (ret) { 1897 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__); 1898 return ret; 1899 } 1900 } 1901 1902 return 0; 1903 } 1904 1905 static int navi10_set_watermarks_table(struct smu_context *smu, 1906 struct pp_smu_wm_range_sets *clock_ranges) 1907 { 1908 Watermarks_t *table = smu->smu_table.watermarks_table; 1909 int ret = 0; 1910 int i; 1911 1912 if (clock_ranges) { 1913 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 1914 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1915 return -EINVAL; 1916 1917 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1918 table->WatermarkRow[WM_DCEFCLK][i].MinClock = 1919 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1920 table->WatermarkRow[WM_DCEFCLK][i].MaxClock = 1921 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1922 table->WatermarkRow[WM_DCEFCLK][i].MinUclk = 1923 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1924 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk = 1925 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1926 1927 table->WatermarkRow[WM_DCEFCLK][i].WmSetting = 1928 clock_ranges->reader_wm_sets[i].wm_inst; 1929 } 1930 1931 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1932 table->WatermarkRow[WM_SOCCLK][i].MinClock = 1933 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1934 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1935 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1936 table->WatermarkRow[WM_SOCCLK][i].MinUclk = 1937 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1938 table->WatermarkRow[WM_SOCCLK][i].MaxUclk = 1939 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1940 1941 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1942 clock_ranges->writer_wm_sets[i].wm_inst; 1943 } 1944 1945 smu->watermarks_bitmap |= WATERMARKS_EXIST; 1946 } 1947 1948 /* pass data to smu controller */ 1949 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1950 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1951 ret = smu_cmn_write_watermarks_table(smu); 1952 if (ret) { 1953 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1954 return ret; 1955 } 1956 smu->watermarks_bitmap |= WATERMARKS_LOADED; 1957 } 1958 1959 return 0; 1960 } 1961 1962 static int navi10_read_sensor(struct smu_context *smu, 1963 enum amd_pp_sensors sensor, 1964 void *data, uint32_t *size) 1965 { 1966 int ret = 0; 1967 struct smu_table_context *table_context = &smu->smu_table; 1968 PPTable_t *pptable = table_context->driver_pptable; 1969 1970 if(!data || !size) 1971 return -EINVAL; 1972 1973 mutex_lock(&smu->sensor_lock); 1974 switch (sensor) { 1975 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 1976 *(uint32_t *)data = pptable->FanMaximumRpm; 1977 *size = 4; 1978 break; 1979 case AMDGPU_PP_SENSOR_MEM_LOAD: 1980 ret = navi1x_get_smu_metrics_data(smu, 1981 METRICS_AVERAGE_MEMACTIVITY, 1982 (uint32_t *)data); 1983 *size = 4; 1984 break; 1985 case AMDGPU_PP_SENSOR_GPU_LOAD: 1986 ret = navi1x_get_smu_metrics_data(smu, 1987 METRICS_AVERAGE_GFXACTIVITY, 1988 (uint32_t *)data); 1989 *size = 4; 1990 break; 1991 case AMDGPU_PP_SENSOR_GPU_POWER: 1992 ret = navi1x_get_smu_metrics_data(smu, 1993 METRICS_AVERAGE_SOCKETPOWER, 1994 (uint32_t *)data); 1995 *size = 4; 1996 break; 1997 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1998 ret = navi1x_get_smu_metrics_data(smu, 1999 METRICS_TEMPERATURE_HOTSPOT, 2000 (uint32_t *)data); 2001 *size = 4; 2002 break; 2003 case AMDGPU_PP_SENSOR_EDGE_TEMP: 2004 ret = navi1x_get_smu_metrics_data(smu, 2005 METRICS_TEMPERATURE_EDGE, 2006 (uint32_t *)data); 2007 *size = 4; 2008 break; 2009 case AMDGPU_PP_SENSOR_MEM_TEMP: 2010 ret = navi1x_get_smu_metrics_data(smu, 2011 METRICS_TEMPERATURE_MEM, 2012 (uint32_t *)data); 2013 *size = 4; 2014 break; 2015 case AMDGPU_PP_SENSOR_GFX_MCLK: 2016 ret = navi10_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 2017 *(uint32_t *)data *= 100; 2018 *size = 4; 2019 break; 2020 case AMDGPU_PP_SENSOR_GFX_SCLK: 2021 ret = navi1x_get_smu_metrics_data(smu, METRICS_AVERAGE_GFXCLK, (uint32_t *)data); 2022 *(uint32_t *)data *= 100; 2023 *size = 4; 2024 break; 2025 case AMDGPU_PP_SENSOR_VDDGFX: 2026 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data); 2027 *size = 4; 2028 break; 2029 default: 2030 ret = -EOPNOTSUPP; 2031 break; 2032 } 2033 mutex_unlock(&smu->sensor_lock); 2034 2035 return ret; 2036 } 2037 2038 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states) 2039 { 2040 uint32_t num_discrete_levels = 0; 2041 uint16_t *dpm_levels = NULL; 2042 uint16_t i = 0; 2043 struct smu_table_context *table_context = &smu->smu_table; 2044 PPTable_t *driver_ppt = NULL; 2045 2046 if (!clocks_in_khz || !num_states || !table_context->driver_pptable) 2047 return -EINVAL; 2048 2049 driver_ppt = table_context->driver_pptable; 2050 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels; 2051 dpm_levels = driver_ppt->FreqTableUclk; 2052 2053 if (num_discrete_levels == 0 || dpm_levels == NULL) 2054 return -EINVAL; 2055 2056 *num_states = num_discrete_levels; 2057 for (i = 0; i < num_discrete_levels; i++) { 2058 /* convert to khz */ 2059 *clocks_in_khz = (*dpm_levels) * 1000; 2060 clocks_in_khz++; 2061 dpm_levels++; 2062 } 2063 2064 return 0; 2065 } 2066 2067 static int navi10_get_thermal_temperature_range(struct smu_context *smu, 2068 struct smu_temperature_range *range) 2069 { 2070 struct smu_table_context *table_context = &smu->smu_table; 2071 struct smu_11_0_powerplay_table *powerplay_table = 2072 table_context->power_play_table; 2073 PPTable_t *pptable = smu->smu_table.driver_pptable; 2074 2075 if (!range) 2076 return -EINVAL; 2077 2078 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range)); 2079 2080 range->max = pptable->TedgeLimit * 2081 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2082 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) * 2083 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2084 range->hotspot_crit_max = pptable->ThotspotLimit * 2085 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2086 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 2087 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2088 range->mem_crit_max = pptable->TmemLimit * 2089 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2090 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)* 2091 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2092 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 2093 2094 return 0; 2095 } 2096 2097 static int navi10_display_disable_memory_clock_switch(struct smu_context *smu, 2098 bool disable_memory_clock_switch) 2099 { 2100 int ret = 0; 2101 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks = 2102 (struct smu_11_0_max_sustainable_clocks *) 2103 smu->smu_table.max_sustainable_clocks; 2104 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal; 2105 uint32_t max_memory_clock = max_sustainable_clocks->uclock; 2106 2107 if(smu->disable_uclk_switch == disable_memory_clock_switch) 2108 return 0; 2109 2110 if(disable_memory_clock_switch) 2111 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0); 2112 else 2113 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0); 2114 2115 if(!ret) 2116 smu->disable_uclk_switch = disable_memory_clock_switch; 2117 2118 return ret; 2119 } 2120 2121 static int navi10_get_power_limit(struct smu_context *smu) 2122 { 2123 struct smu_11_0_powerplay_table *powerplay_table = 2124 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table; 2125 struct smu_11_0_overdrive_table *od_settings = smu->od_settings; 2126 PPTable_t *pptable = smu->smu_table.driver_pptable; 2127 uint32_t power_limit, od_percent; 2128 2129 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) { 2130 /* the last hope to figure out the ppt limit */ 2131 if (!pptable) { 2132 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!"); 2133 return -EINVAL; 2134 } 2135 power_limit = 2136 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0]; 2137 } 2138 smu->current_power_limit = smu->default_power_limit = power_limit; 2139 2140 if (smu->od_enabled && 2141 navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) { 2142 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]); 2143 2144 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit); 2145 2146 power_limit *= (100 + od_percent); 2147 power_limit /= 100; 2148 } 2149 smu->max_power_limit = power_limit; 2150 2151 return 0; 2152 } 2153 2154 static int navi10_update_pcie_parameters(struct smu_context *smu, 2155 uint32_t pcie_gen_cap, 2156 uint32_t pcie_width_cap) 2157 { 2158 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 2159 PPTable_t *pptable = smu->smu_table.driver_pptable; 2160 uint32_t smu_pcie_arg; 2161 int ret, i; 2162 2163 /* lclk dpm table setup */ 2164 for (i = 0; i < MAX_PCIE_CONF; i++) { 2165 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i]; 2166 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i]; 2167 } 2168 2169 for (i = 0; i < NUM_LINK_LEVELS; i++) { 2170 smu_pcie_arg = (i << 16) | 2171 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) : 2172 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ? 2173 pptable->PcieLaneCount[i] : pcie_width_cap); 2174 ret = smu_cmn_send_smc_msg_with_param(smu, 2175 SMU_MSG_OverridePcieParameters, 2176 smu_pcie_arg, 2177 NULL); 2178 2179 if (ret) 2180 return ret; 2181 2182 if (pptable->PcieGenSpeed[i] > pcie_gen_cap) 2183 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap; 2184 if (pptable->PcieLaneCount[i] > pcie_width_cap) 2185 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap; 2186 } 2187 2188 return 0; 2189 } 2190 2191 static inline void navi10_dump_od_table(struct smu_context *smu, 2192 OverDriveTable_t *od_table) 2193 { 2194 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax); 2195 dev_dbg(smu->adev->dev, "OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1); 2196 dev_dbg(smu->adev->dev, "OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2); 2197 dev_dbg(smu->adev->dev, "OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3); 2198 dev_dbg(smu->adev->dev, "OD: UclkFmax: %d\n", od_table->UclkFmax); 2199 dev_dbg(smu->adev->dev, "OD: OverDrivePct: %d\n", od_table->OverDrivePct); 2200 } 2201 2202 static int navi10_od_setting_check_range(struct smu_context *smu, 2203 struct smu_11_0_overdrive_table *od_table, 2204 enum SMU_11_0_ODSETTING_ID setting, 2205 uint32_t value) 2206 { 2207 if (value < od_table->min[setting]) { 2208 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]); 2209 return -EINVAL; 2210 } 2211 if (value > od_table->max[setting]) { 2212 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]); 2213 return -EINVAL; 2214 } 2215 return 0; 2216 } 2217 2218 static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu, 2219 uint16_t *voltage, 2220 uint32_t freq) 2221 { 2222 uint32_t param = (freq & 0xFFFF) | (PPCLK_GFXCLK << 16); 2223 uint32_t value = 0; 2224 int ret; 2225 2226 ret = smu_cmn_send_smc_msg_with_param(smu, 2227 SMU_MSG_GetVoltageByDpm, 2228 param, 2229 &value); 2230 if (ret) { 2231 dev_err(smu->adev->dev, "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!"); 2232 return ret; 2233 } 2234 2235 *voltage = (uint16_t)value; 2236 2237 return 0; 2238 } 2239 2240 static bool navi10_is_baco_supported(struct smu_context *smu) 2241 { 2242 struct amdgpu_device *adev = smu->adev; 2243 uint32_t val; 2244 2245 if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu))) 2246 return false; 2247 2248 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); 2249 return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false; 2250 } 2251 2252 static int navi10_set_default_od_settings(struct smu_context *smu) 2253 { 2254 OverDriveTable_t *od_table = 2255 (OverDriveTable_t *)smu->smu_table.overdrive_table; 2256 OverDriveTable_t *boot_od_table = 2257 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table; 2258 int ret = 0; 2259 2260 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, false); 2261 if (ret) { 2262 dev_err(smu->adev->dev, "Failed to get overdrive table!\n"); 2263 return ret; 2264 } 2265 2266 if (!od_table->GfxclkVolt1) { 2267 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu, 2268 &od_table->GfxclkVolt1, 2269 od_table->GfxclkFreq1); 2270 if (ret) 2271 return ret; 2272 } 2273 2274 if (!od_table->GfxclkVolt2) { 2275 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu, 2276 &od_table->GfxclkVolt2, 2277 od_table->GfxclkFreq2); 2278 if (ret) 2279 return ret; 2280 } 2281 2282 if (!od_table->GfxclkVolt3) { 2283 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu, 2284 &od_table->GfxclkVolt3, 2285 od_table->GfxclkFreq3); 2286 if (ret) 2287 return ret; 2288 } 2289 2290 memcpy(boot_od_table, od_table, sizeof(OverDriveTable_t)); 2291 2292 navi10_dump_od_table(smu, od_table); 2293 2294 return 0; 2295 } 2296 2297 static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) { 2298 int i; 2299 int ret = 0; 2300 struct smu_table_context *table_context = &smu->smu_table; 2301 OverDriveTable_t *od_table; 2302 struct smu_11_0_overdrive_table *od_settings; 2303 enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting; 2304 uint16_t *freq_ptr, *voltage_ptr; 2305 od_table = (OverDriveTable_t *)table_context->overdrive_table; 2306 2307 if (!smu->od_enabled) { 2308 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n"); 2309 return -EINVAL; 2310 } 2311 2312 if (!smu->od_settings) { 2313 dev_err(smu->adev->dev, "OD board limits are not set!\n"); 2314 return -ENOENT; 2315 } 2316 2317 od_settings = smu->od_settings; 2318 2319 switch (type) { 2320 case PP_OD_EDIT_SCLK_VDDC_TABLE: 2321 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) { 2322 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n"); 2323 return -ENOTSUPP; 2324 } 2325 if (!table_context->overdrive_table) { 2326 dev_err(smu->adev->dev, "Overdrive is not initialized\n"); 2327 return -EINVAL; 2328 } 2329 for (i = 0; i < size; i += 2) { 2330 if (i + 2 > size) { 2331 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size); 2332 return -EINVAL; 2333 } 2334 switch (input[i]) { 2335 case 0: 2336 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN; 2337 freq_ptr = &od_table->GfxclkFmin; 2338 if (input[i + 1] > od_table->GfxclkFmax) { 2339 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n", 2340 input[i + 1], 2341 od_table->GfxclkFmin); 2342 return -EINVAL; 2343 } 2344 break; 2345 case 1: 2346 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX; 2347 freq_ptr = &od_table->GfxclkFmax; 2348 if (input[i + 1] < od_table->GfxclkFmin) { 2349 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n", 2350 input[i + 1], 2351 od_table->GfxclkFmax); 2352 return -EINVAL; 2353 } 2354 break; 2355 default: 2356 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]); 2357 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n"); 2358 return -EINVAL; 2359 } 2360 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[i + 1]); 2361 if (ret) 2362 return ret; 2363 *freq_ptr = input[i + 1]; 2364 } 2365 break; 2366 case PP_OD_EDIT_MCLK_VDDC_TABLE: 2367 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) { 2368 dev_warn(smu->adev->dev, "UCLK_MAX not supported!\n"); 2369 return -ENOTSUPP; 2370 } 2371 if (size < 2) { 2372 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size); 2373 return -EINVAL; 2374 } 2375 if (input[0] != 1) { 2376 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]); 2377 dev_info(smu->adev->dev, "Supported indices: [1:max]\n"); 2378 return -EINVAL; 2379 } 2380 ret = navi10_od_setting_check_range(smu, od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]); 2381 if (ret) 2382 return ret; 2383 od_table->UclkFmax = input[1]; 2384 break; 2385 case PP_OD_RESTORE_DEFAULT_TABLE: 2386 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) { 2387 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n"); 2388 return -EINVAL; 2389 } 2390 memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t)); 2391 break; 2392 case PP_OD_COMMIT_DPM_TABLE: 2393 navi10_dump_od_table(smu, od_table); 2394 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true); 2395 if (ret) { 2396 dev_err(smu->adev->dev, "Failed to import overdrive table!\n"); 2397 return ret; 2398 } 2399 break; 2400 case PP_OD_EDIT_VDDC_CURVE: 2401 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) { 2402 dev_warn(smu->adev->dev, "GFXCLK_CURVE not supported!\n"); 2403 return -ENOTSUPP; 2404 } 2405 if (size < 3) { 2406 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size); 2407 return -EINVAL; 2408 } 2409 if (!od_table) { 2410 dev_info(smu->adev->dev, "Overdrive is not initialized\n"); 2411 return -EINVAL; 2412 } 2413 2414 switch (input[0]) { 2415 case 0: 2416 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1; 2417 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1; 2418 freq_ptr = &od_table->GfxclkFreq1; 2419 voltage_ptr = &od_table->GfxclkVolt1; 2420 break; 2421 case 1: 2422 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2; 2423 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2; 2424 freq_ptr = &od_table->GfxclkFreq2; 2425 voltage_ptr = &od_table->GfxclkVolt2; 2426 break; 2427 case 2: 2428 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3; 2429 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3; 2430 freq_ptr = &od_table->GfxclkFreq3; 2431 voltage_ptr = &od_table->GfxclkVolt3; 2432 break; 2433 default: 2434 dev_info(smu->adev->dev, "Invalid VDDC_CURVE index: %ld\n", input[0]); 2435 dev_info(smu->adev->dev, "Supported indices: [0, 1, 2]\n"); 2436 return -EINVAL; 2437 } 2438 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[1]); 2439 if (ret) 2440 return ret; 2441 // Allow setting zero to disable the OverDrive VDDC curve 2442 if (input[2] != 0) { 2443 ret = navi10_od_setting_check_range(smu, od_settings, voltage_setting, input[2]); 2444 if (ret) 2445 return ret; 2446 *freq_ptr = input[1]; 2447 *voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE; 2448 dev_dbg(smu->adev->dev, "OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr); 2449 } else { 2450 // If setting 0, disable all voltage curve settings 2451 od_table->GfxclkVolt1 = 0; 2452 od_table->GfxclkVolt2 = 0; 2453 od_table->GfxclkVolt3 = 0; 2454 } 2455 navi10_dump_od_table(smu, od_table); 2456 break; 2457 default: 2458 return -ENOSYS; 2459 } 2460 return ret; 2461 } 2462 2463 static int navi10_run_btc(struct smu_context *smu) 2464 { 2465 int ret = 0; 2466 2467 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunBtc, NULL); 2468 if (ret) 2469 dev_err(smu->adev->dev, "RunBtc failed!\n"); 2470 2471 return ret; 2472 } 2473 2474 static bool navi10_need_umc_cdr_workaround(struct smu_context *smu) 2475 { 2476 struct amdgpu_device *adev = smu->adev; 2477 2478 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 2479 return false; 2480 2481 if (adev->asic_type == CHIP_NAVI10 || 2482 adev->asic_type == CHIP_NAVI14) 2483 return true; 2484 2485 return false; 2486 } 2487 2488 static int navi10_umc_hybrid_cdr_workaround(struct smu_context *smu) 2489 { 2490 uint32_t uclk_count, uclk_min, uclk_max; 2491 int ret = 0; 2492 2493 /* This workaround can be applied only with uclk dpm enabled */ 2494 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 2495 return 0; 2496 2497 ret = smu_v11_0_get_dpm_level_count(smu, SMU_UCLK, &uclk_count); 2498 if (ret) 2499 return ret; 2500 2501 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)(uclk_count - 1), &uclk_max); 2502 if (ret) 2503 return ret; 2504 2505 /* 2506 * The NAVI10_UMC_HYBRID_CDR_WORKAROUND_UCLK_THRESHOLD is 750Mhz. 2507 * This workaround is needed only when the max uclk frequency 2508 * not greater than that. 2509 */ 2510 if (uclk_max > 0x2EE) 2511 return 0; 2512 2513 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)0, &uclk_min); 2514 if (ret) 2515 return ret; 2516 2517 /* Force UCLK out of the highest DPM */ 2518 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_min); 2519 if (ret) 2520 return ret; 2521 2522 /* Revert the UCLK Hardmax */ 2523 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_max); 2524 if (ret) 2525 return ret; 2526 2527 /* 2528 * In this case, SMU already disabled dummy pstate during enablement 2529 * of UCLK DPM, we have to re-enabled it. 2530 */ 2531 return smu_cmn_send_smc_msg(smu, SMU_MSG_DAL_ENABLE_DUMMY_PSTATE_CHANGE, NULL); 2532 } 2533 2534 static int navi10_set_dummy_pstates_table_location(struct smu_context *smu) 2535 { 2536 struct smu_table_context *smu_table = &smu->smu_table; 2537 struct smu_table *dummy_read_table = 2538 &smu_table->dummy_read_1_table; 2539 char *dummy_table = dummy_read_table->cpu_addr; 2540 int ret = 0; 2541 uint32_t i; 2542 2543 for (i = 0; i < 0x40000; i += 0x1000 * 2) { 2544 memcpy(dummy_table, &NoDbiPrbs7[0], 0x1000); 2545 dummy_table += 0x1000; 2546 memcpy(dummy_table, &DbiPrbs7[0], 0x1000); 2547 dummy_table += 0x1000; 2548 } 2549 2550 amdgpu_asic_flush_hdp(smu->adev, NULL); 2551 2552 ret = smu_cmn_send_smc_msg_with_param(smu, 2553 SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH, 2554 upper_32_bits(dummy_read_table->mc_address), 2555 NULL); 2556 if (ret) 2557 return ret; 2558 2559 return smu_cmn_send_smc_msg_with_param(smu, 2560 SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW, 2561 lower_32_bits(dummy_read_table->mc_address), 2562 NULL); 2563 } 2564 2565 static int navi10_run_umc_cdr_workaround(struct smu_context *smu) 2566 { 2567 struct amdgpu_device *adev = smu->adev; 2568 uint8_t umc_fw_greater_than_v136 = false; 2569 uint8_t umc_fw_disable_cdr = false; 2570 uint32_t pmfw_version; 2571 uint32_t param; 2572 int ret = 0; 2573 2574 if (!navi10_need_umc_cdr_workaround(smu)) 2575 return 0; 2576 2577 ret = smu_cmn_get_smc_version(smu, NULL, &pmfw_version); 2578 if (ret) { 2579 dev_err(adev->dev, "Failed to get smu version!\n"); 2580 return ret; 2581 } 2582 2583 /* 2584 * The messages below are only supported by Navi10 42.53.0 and later 2585 * PMFWs and Navi14 53.29.0 and later PMFWs. 2586 * - PPSMC_MSG_SetDriverDummyTableDramAddrHigh 2587 * - PPSMC_MSG_SetDriverDummyTableDramAddrLow 2588 * - PPSMC_MSG_GetUMCFWWA 2589 */ 2590 if (((adev->asic_type == CHIP_NAVI10) && (pmfw_version >= 0x2a3500)) || 2591 ((adev->asic_type == CHIP_NAVI14) && (pmfw_version >= 0x351D00))) { 2592 ret = smu_cmn_send_smc_msg_with_param(smu, 2593 SMU_MSG_GET_UMC_FW_WA, 2594 0, 2595 ¶m); 2596 if (ret) 2597 return ret; 2598 2599 /* First bit indicates if the UMC f/w is above v137 */ 2600 umc_fw_greater_than_v136 = param & 0x1; 2601 2602 /* Second bit indicates if hybrid-cdr is disabled */ 2603 umc_fw_disable_cdr = param & 0x2; 2604 2605 /* w/a only allowed if UMC f/w is <= 136 */ 2606 if (umc_fw_greater_than_v136) 2607 return 0; 2608 2609 if (umc_fw_disable_cdr) { 2610 if (adev->asic_type == CHIP_NAVI10) 2611 return navi10_umc_hybrid_cdr_workaround(smu); 2612 } else { 2613 return navi10_set_dummy_pstates_table_location(smu); 2614 } 2615 } else { 2616 if (adev->asic_type == CHIP_NAVI10) 2617 return navi10_umc_hybrid_cdr_workaround(smu); 2618 } 2619 2620 return 0; 2621 } 2622 2623 static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu, 2624 void **table) 2625 { 2626 struct smu_table_context *smu_table = &smu->smu_table; 2627 struct gpu_metrics_v1_1 *gpu_metrics = 2628 (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table; 2629 SmuMetrics_legacy_t metrics; 2630 int ret = 0; 2631 2632 mutex_lock(&smu->metrics_lock); 2633 2634 ret = smu_cmn_get_metrics_table_locked(smu, 2635 NULL, 2636 true); 2637 if (ret) { 2638 mutex_unlock(&smu->metrics_lock); 2639 return ret; 2640 } 2641 2642 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_legacy_t)); 2643 2644 mutex_unlock(&smu->metrics_lock); 2645 2646 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1); 2647 2648 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 2649 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 2650 gpu_metrics->temperature_mem = metrics.TemperatureMem; 2651 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 2652 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 2653 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 2654 2655 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 2656 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 2657 2658 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 2659 2660 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 2661 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 2662 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 2663 2664 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 2665 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 2666 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 2667 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 2668 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 2669 2670 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 2671 2672 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 2673 2674 gpu_metrics->pcie_link_width = 2675 smu_v11_0_get_current_pcie_link_width(smu); 2676 gpu_metrics->pcie_link_speed = 2677 smu_v11_0_get_current_pcie_link_speed(smu); 2678 2679 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 2680 2681 *table = (void *)gpu_metrics; 2682 2683 return sizeof(struct gpu_metrics_v1_1); 2684 } 2685 2686 static ssize_t navi10_get_gpu_metrics(struct smu_context *smu, 2687 void **table) 2688 { 2689 struct smu_table_context *smu_table = &smu->smu_table; 2690 struct gpu_metrics_v1_1 *gpu_metrics = 2691 (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table; 2692 SmuMetrics_t metrics; 2693 int ret = 0; 2694 2695 mutex_lock(&smu->metrics_lock); 2696 2697 ret = smu_cmn_get_metrics_table_locked(smu, 2698 NULL, 2699 true); 2700 if (ret) { 2701 mutex_unlock(&smu->metrics_lock); 2702 return ret; 2703 } 2704 2705 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_t)); 2706 2707 mutex_unlock(&smu->metrics_lock); 2708 2709 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1); 2710 2711 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 2712 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 2713 gpu_metrics->temperature_mem = metrics.TemperatureMem; 2714 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 2715 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 2716 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 2717 2718 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 2719 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 2720 2721 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 2722 2723 if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 2724 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs; 2725 else 2726 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs; 2727 2728 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 2729 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs; 2730 2731 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 2732 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 2733 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 2734 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 2735 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 2736 2737 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 2738 2739 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 2740 2741 gpu_metrics->pcie_link_width = metrics.PcieWidth; 2742 gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate]; 2743 2744 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 2745 2746 *table = (void *)gpu_metrics; 2747 2748 return sizeof(struct gpu_metrics_v1_1); 2749 } 2750 2751 static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu, 2752 void **table) 2753 { 2754 struct smu_table_context *smu_table = &smu->smu_table; 2755 struct gpu_metrics_v1_1 *gpu_metrics = 2756 (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table; 2757 SmuMetrics_NV12_legacy_t metrics; 2758 int ret = 0; 2759 2760 mutex_lock(&smu->metrics_lock); 2761 2762 ret = smu_cmn_get_metrics_table_locked(smu, 2763 NULL, 2764 true); 2765 if (ret) { 2766 mutex_unlock(&smu->metrics_lock); 2767 return ret; 2768 } 2769 2770 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_legacy_t)); 2771 2772 mutex_unlock(&smu->metrics_lock); 2773 2774 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1); 2775 2776 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 2777 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 2778 gpu_metrics->temperature_mem = metrics.TemperatureMem; 2779 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 2780 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 2781 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 2782 2783 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 2784 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 2785 2786 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 2787 2788 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 2789 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 2790 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 2791 2792 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator; 2793 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency; 2794 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency; 2795 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage; 2796 2797 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 2798 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 2799 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 2800 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 2801 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 2802 2803 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 2804 2805 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 2806 2807 gpu_metrics->pcie_link_width = 2808 smu_v11_0_get_current_pcie_link_width(smu); 2809 gpu_metrics->pcie_link_speed = 2810 smu_v11_0_get_current_pcie_link_speed(smu); 2811 2812 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 2813 2814 *table = (void *)gpu_metrics; 2815 2816 return sizeof(struct gpu_metrics_v1_1); 2817 } 2818 2819 static ssize_t navi12_get_gpu_metrics(struct smu_context *smu, 2820 void **table) 2821 { 2822 struct smu_table_context *smu_table = &smu->smu_table; 2823 struct gpu_metrics_v1_1 *gpu_metrics = 2824 (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table; 2825 SmuMetrics_NV12_t metrics; 2826 int ret = 0; 2827 2828 mutex_lock(&smu->metrics_lock); 2829 2830 ret = smu_cmn_get_metrics_table_locked(smu, 2831 NULL, 2832 true); 2833 if (ret) { 2834 mutex_unlock(&smu->metrics_lock); 2835 return ret; 2836 } 2837 2838 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_t)); 2839 2840 mutex_unlock(&smu->metrics_lock); 2841 2842 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1); 2843 2844 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 2845 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 2846 gpu_metrics->temperature_mem = metrics.TemperatureMem; 2847 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 2848 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 2849 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 2850 2851 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 2852 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 2853 2854 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 2855 2856 if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD) 2857 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs; 2858 else 2859 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs; 2860 2861 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 2862 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs; 2863 2864 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator; 2865 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency; 2866 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency; 2867 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage; 2868 2869 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 2870 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 2871 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 2872 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 2873 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 2874 2875 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 2876 2877 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 2878 2879 gpu_metrics->pcie_link_width = metrics.PcieWidth; 2880 gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate]; 2881 2882 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 2883 2884 *table = (void *)gpu_metrics; 2885 2886 return sizeof(struct gpu_metrics_v1_1); 2887 } 2888 2889 static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu, 2890 void **table) 2891 { 2892 struct amdgpu_device *adev = smu->adev; 2893 uint32_t smu_version; 2894 int ret = 0; 2895 2896 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 2897 if (ret) { 2898 dev_err(adev->dev, "Failed to get smu version!\n"); 2899 return ret; 2900 } 2901 2902 switch (adev->asic_type) { 2903 case CHIP_NAVI12: 2904 if (smu_version > 0x00341C00) 2905 ret = navi12_get_gpu_metrics(smu, table); 2906 else 2907 ret = navi12_get_legacy_gpu_metrics(smu, table); 2908 break; 2909 case CHIP_NAVI10: 2910 case CHIP_NAVI14: 2911 default: 2912 if (((adev->asic_type == CHIP_NAVI14) && smu_version > 0x00351F00) || 2913 ((adev->asic_type == CHIP_NAVI10) && smu_version > 0x002A3B00)) 2914 ret = navi10_get_gpu_metrics(smu, table); 2915 else 2916 ret =navi10_get_legacy_gpu_metrics(smu, table); 2917 break; 2918 } 2919 2920 return ret; 2921 } 2922 2923 static int navi10_enable_mgpu_fan_boost(struct smu_context *smu) 2924 { 2925 struct amdgpu_device *adev = smu->adev; 2926 uint32_t param = 0; 2927 2928 /* Navi12 does not support this */ 2929 if (adev->asic_type == CHIP_NAVI12) 2930 return 0; 2931 2932 /* Workaround for WS SKU */ 2933 if (adev->pdev->device == 0x7312 && 2934 adev->pdev->revision == 0) 2935 param = 0xD188; 2936 2937 return smu_cmn_send_smc_msg_with_param(smu, 2938 SMU_MSG_SetMGpuFanBoostLimitRpm, 2939 param, 2940 NULL); 2941 } 2942 2943 static int navi10_post_smu_init(struct smu_context *smu) 2944 { 2945 struct amdgpu_device *adev = smu->adev; 2946 int ret = 0; 2947 2948 if (amdgpu_sriov_vf(adev)) 2949 return 0; 2950 2951 ret = navi10_run_umc_cdr_workaround(smu); 2952 if (ret) { 2953 dev_err(adev->dev, "Failed to apply umc cdr workaround!\n"); 2954 return ret; 2955 } 2956 2957 if (!smu->dc_controlled_by_gpio) { 2958 /* 2959 * For Navi1X, manually switch it to AC mode as PMFW 2960 * may boot it with DC mode. 2961 */ 2962 ret = smu_v11_0_set_power_source(smu, 2963 adev->pm.ac_power ? 2964 SMU_POWER_SOURCE_AC : 2965 SMU_POWER_SOURCE_DC); 2966 if (ret) { 2967 dev_err(adev->dev, "Failed to switch to %s mode!\n", 2968 adev->pm.ac_power ? "AC" : "DC"); 2969 return ret; 2970 } 2971 } 2972 2973 return ret; 2974 } 2975 2976 static const struct pptable_funcs navi10_ppt_funcs = { 2977 .get_allowed_feature_mask = navi10_get_allowed_feature_mask, 2978 .set_default_dpm_table = navi10_set_default_dpm_table, 2979 .dpm_set_vcn_enable = navi10_dpm_set_vcn_enable, 2980 .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable, 2981 .print_clk_levels = navi10_print_clk_levels, 2982 .force_clk_levels = navi10_force_clk_levels, 2983 .populate_umd_state_clk = navi10_populate_umd_state_clk, 2984 .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency, 2985 .pre_display_config_changed = navi10_pre_display_config_changed, 2986 .display_config_changed = navi10_display_config_changed, 2987 .notify_smc_display_config = navi10_notify_smc_display_config, 2988 .is_dpm_running = navi10_is_dpm_running, 2989 .get_fan_speed_percent = navi10_get_fan_speed_percent, 2990 .get_power_profile_mode = navi10_get_power_profile_mode, 2991 .set_power_profile_mode = navi10_set_power_profile_mode, 2992 .set_watermarks_table = navi10_set_watermarks_table, 2993 .read_sensor = navi10_read_sensor, 2994 .get_uclk_dpm_states = navi10_get_uclk_dpm_states, 2995 .set_performance_level = smu_v11_0_set_performance_level, 2996 .get_thermal_temperature_range = navi10_get_thermal_temperature_range, 2997 .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch, 2998 .get_power_limit = navi10_get_power_limit, 2999 .update_pcie_parameters = navi10_update_pcie_parameters, 3000 .init_microcode = smu_v11_0_init_microcode, 3001 .load_microcode = smu_v11_0_load_microcode, 3002 .fini_microcode = smu_v11_0_fini_microcode, 3003 .init_smc_tables = navi10_init_smc_tables, 3004 .fini_smc_tables = smu_v11_0_fini_smc_tables, 3005 .init_power = smu_v11_0_init_power, 3006 .fini_power = smu_v11_0_fini_power, 3007 .check_fw_status = smu_v11_0_check_fw_status, 3008 .setup_pptable = navi10_setup_pptable, 3009 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, 3010 .check_fw_version = smu_v11_0_check_fw_version, 3011 .write_pptable = smu_cmn_write_pptable, 3012 .set_driver_table_location = smu_v11_0_set_driver_table_location, 3013 .set_tool_table_location = smu_v11_0_set_tool_table_location, 3014 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 3015 .system_features_control = smu_v11_0_system_features_control, 3016 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 3017 .send_smc_msg = smu_cmn_send_smc_msg, 3018 .init_display_count = smu_v11_0_init_display_count, 3019 .set_allowed_mask = smu_v11_0_set_allowed_mask, 3020 .get_enabled_mask = smu_cmn_get_enabled_mask, 3021 .feature_is_enabled = smu_cmn_feature_is_enabled, 3022 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 3023 .notify_display_change = smu_v11_0_notify_display_change, 3024 .set_power_limit = smu_v11_0_set_power_limit, 3025 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks, 3026 .enable_thermal_alert = smu_v11_0_enable_thermal_alert, 3027 .disable_thermal_alert = smu_v11_0_disable_thermal_alert, 3028 .set_min_dcef_deep_sleep = smu_v11_0_set_min_deep_sleep_dcefclk, 3029 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request, 3030 .get_fan_control_mode = smu_v11_0_get_fan_control_mode, 3031 .set_fan_control_mode = smu_v11_0_set_fan_control_mode, 3032 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent, 3033 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate, 3034 .gfx_off_control = smu_v11_0_gfx_off_control, 3035 .register_irq_handler = smu_v11_0_register_irq_handler, 3036 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme, 3037 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc, 3038 .baco_is_support= navi10_is_baco_supported, 3039 .baco_get_state = smu_v11_0_baco_get_state, 3040 .baco_set_state = smu_v11_0_baco_set_state, 3041 .baco_enter = smu_v11_0_baco_enter, 3042 .baco_exit = smu_v11_0_baco_exit, 3043 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq, 3044 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, 3045 .set_default_od_settings = navi10_set_default_od_settings, 3046 .od_edit_dpm_table = navi10_od_edit_dpm_table, 3047 .run_btc = navi10_run_btc, 3048 .set_power_source = smu_v11_0_set_power_source, 3049 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 3050 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 3051 .get_gpu_metrics = navi1x_get_gpu_metrics, 3052 .enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost, 3053 .gfx_ulv_control = smu_v11_0_gfx_ulv_control, 3054 .deep_sleep_control = smu_v11_0_deep_sleep_control, 3055 .get_fan_parameters = navi10_get_fan_parameters, 3056 .post_init = navi10_post_smu_init, 3057 .interrupt_work = smu_v11_0_interrupt_work, 3058 .set_mp1_state = navi10_set_mp1_state, 3059 }; 3060 3061 void navi10_set_ppt_funcs(struct smu_context *smu) 3062 { 3063 smu->ppt_funcs = &navi10_ppt_funcs; 3064 smu->message_map = navi10_message_map; 3065 smu->clock_map = navi10_clk_map; 3066 smu->feature_map = navi10_feature_mask_map; 3067 smu->table_map = navi10_table_map; 3068 smu->pwr_src_map = navi10_pwr_src_map; 3069 smu->workload_map = navi10_workload_map; 3070 } 3071