1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include <linux/pci.h> 28 #include <linux/i2c.h> 29 #include "amdgpu.h" 30 #include "amdgpu_smu.h" 31 #include "atomfirmware.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "amdgpu_atombios.h" 34 #include "soc15_common.h" 35 #include "smu_v11_0.h" 36 #include "smu11_driver_if_navi10.h" 37 #include "atom.h" 38 #include "navi10_ppt.h" 39 #include "smu_v11_0_pptable.h" 40 #include "smu_v11_0_ppsmc.h" 41 #include "nbio/nbio_2_3_offset.h" 42 #include "nbio/nbio_2_3_sh_mask.h" 43 #include "thm/thm_11_0_2_offset.h" 44 #include "thm/thm_11_0_2_sh_mask.h" 45 46 #include "asic_reg/mp/mp_11_0_sh_mask.h" 47 #include "smu_cmn.h" 48 #include "smu_11_0_cdr_table.h" 49 50 /* 51 * DO NOT use these for err/warn/info/debug messages. 52 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 53 * They are more MGPU friendly. 54 */ 55 #undef pr_err 56 #undef pr_warn 57 #undef pr_info 58 #undef pr_debug 59 60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 61 62 #define FEATURE_MASK(feature) (1ULL << feature) 63 #define SMC_DPM_FEATURE ( \ 64 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \ 65 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 66 FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) | \ 70 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)) 72 73 static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = { 74 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 75 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 76 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 77 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0), 78 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), 79 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 80 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 81 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1), 82 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1), 83 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1), 84 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1), 85 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1), 86 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1), 87 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 88 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 89 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0), 90 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0), 91 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 92 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 93 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0), 94 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 95 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 96 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable, 0), 97 MSG_MAP(RunBtc, PPSMC_MSG_RunBtc, 0), 98 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), 99 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0), 100 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0), 101 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1), 102 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 103 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), 104 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), 105 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 106 MSG_MAP(SetMemoryChannelConfig, PPSMC_MSG_SetMemoryChannelConfig, 0), 107 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0), 108 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0), 109 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0), 110 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0), 111 MSG_MAP(SetMinDeepSleepDcefclk, PPSMC_MSG_SetMinDeepSleepDcefclk, 0), 112 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0), 113 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0), 114 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0), 115 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0), 116 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1), 117 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 118 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 119 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 120 MSG_MAP(ConfigureGfxDidt, PPSMC_MSG_ConfigureGfxDidt, 0), 121 MSG_MAP(NumOfDisplays, PPSMC_MSG_NumOfDisplays, 0), 122 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0), 123 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0), 124 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 125 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 126 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 127 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1), 128 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0), 129 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0), 130 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset, 0), 131 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown, 0), 132 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 133 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 134 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 135 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 136 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0), 137 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0), 138 MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE,PPSMC_MSG_DALDisableDummyPstateChange, 0), 139 MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALEnableDummyPstateChange, 0), 140 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0), 141 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0), 142 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0), 143 MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH, PPSMC_MSG_SetDriverDummyTableDramAddrHigh, 0), 144 MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW, PPSMC_MSG_SetDriverDummyTableDramAddrLow, 0), 145 MSG_MAP(GET_UMC_FW_WA, PPSMC_MSG_GetUMCFWWA, 0), 146 }; 147 148 static struct cmn2asic_mapping navi10_clk_map[SMU_CLK_COUNT] = { 149 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 150 CLK_MAP(SCLK, PPCLK_GFXCLK), 151 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 152 CLK_MAP(FCLK, PPCLK_SOCCLK), 153 CLK_MAP(UCLK, PPCLK_UCLK), 154 CLK_MAP(MCLK, PPCLK_UCLK), 155 CLK_MAP(DCLK, PPCLK_DCLK), 156 CLK_MAP(VCLK, PPCLK_VCLK), 157 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK), 158 CLK_MAP(DISPCLK, PPCLK_DISPCLK), 159 CLK_MAP(PIXCLK, PPCLK_PIXCLK), 160 CLK_MAP(PHYCLK, PPCLK_PHYCLK), 161 }; 162 163 static struct cmn2asic_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = { 164 FEA_MAP(DPM_PREFETCHER), 165 FEA_MAP(DPM_GFXCLK), 166 FEA_MAP(DPM_GFX_PACE), 167 FEA_MAP(DPM_UCLK), 168 FEA_MAP(DPM_SOCCLK), 169 FEA_MAP(DPM_MP0CLK), 170 FEA_MAP(DPM_LINK), 171 FEA_MAP(DPM_DCEFCLK), 172 FEA_MAP(MEM_VDDCI_SCALING), 173 FEA_MAP(MEM_MVDD_SCALING), 174 FEA_MAP(DS_GFXCLK), 175 FEA_MAP(DS_SOCCLK), 176 FEA_MAP(DS_LCLK), 177 FEA_MAP(DS_DCEFCLK), 178 FEA_MAP(DS_UCLK), 179 FEA_MAP(GFX_ULV), 180 FEA_MAP(FW_DSTATE), 181 FEA_MAP(GFXOFF), 182 FEA_MAP(BACO), 183 FEA_MAP(VCN_PG), 184 FEA_MAP(JPEG_PG), 185 FEA_MAP(USB_PG), 186 FEA_MAP(RSMU_SMN_CG), 187 FEA_MAP(PPT), 188 FEA_MAP(TDC), 189 FEA_MAP(GFX_EDC), 190 FEA_MAP(APCC_PLUS), 191 FEA_MAP(GTHR), 192 FEA_MAP(ACDC), 193 FEA_MAP(VR0HOT), 194 FEA_MAP(VR1HOT), 195 FEA_MAP(FW_CTF), 196 FEA_MAP(FAN_CONTROL), 197 FEA_MAP(THERMAL), 198 FEA_MAP(GFX_DCS), 199 FEA_MAP(RM), 200 FEA_MAP(LED_DISPLAY), 201 FEA_MAP(GFX_SS), 202 FEA_MAP(OUT_OF_BAND_MONITOR), 203 FEA_MAP(TEMP_DEPENDENT_VMIN), 204 FEA_MAP(MMHUB_PG), 205 FEA_MAP(ATHUB_PG), 206 FEA_MAP(APCC_DFLL), 207 }; 208 209 static struct cmn2asic_mapping navi10_table_map[SMU_TABLE_COUNT] = { 210 TAB_MAP(PPTABLE), 211 TAB_MAP(WATERMARKS), 212 TAB_MAP(AVFS), 213 TAB_MAP(AVFS_PSM_DEBUG), 214 TAB_MAP(AVFS_FUSE_OVERRIDE), 215 TAB_MAP(PMSTATUSLOG), 216 TAB_MAP(SMU_METRICS), 217 TAB_MAP(DRIVER_SMU_CONFIG), 218 TAB_MAP(ACTIVITY_MONITOR_COEFF), 219 TAB_MAP(OVERDRIVE), 220 TAB_MAP(I2C_COMMANDS), 221 TAB_MAP(PACE), 222 }; 223 224 static struct cmn2asic_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { 225 PWR_MAP(AC), 226 PWR_MAP(DC), 227 }; 228 229 static struct cmn2asic_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 230 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), 231 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 232 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 233 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 234 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 235 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 236 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 237 }; 238 239 static bool is_asic_secure(struct smu_context *smu) 240 { 241 struct amdgpu_device *adev = smu->adev; 242 bool is_secure = true; 243 uint32_t mp0_fw_intf; 244 245 mp0_fw_intf = RREG32_PCIE(MP0_Public | 246 (smnMP0_FW_INTF & 0xffffffff)); 247 248 if (!(mp0_fw_intf & (1 << 19))) 249 is_secure = false; 250 251 return is_secure; 252 } 253 254 static int 255 navi10_get_allowed_feature_mask(struct smu_context *smu, 256 uint32_t *feature_mask, uint32_t num) 257 { 258 struct amdgpu_device *adev = smu->adev; 259 260 if (num > 2) 261 return -EINVAL; 262 263 memset(feature_mask, 0, sizeof(uint32_t) * num); 264 265 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) 266 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) 267 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) 268 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) 269 | FEATURE_MASK(FEATURE_PPT_BIT) 270 | FEATURE_MASK(FEATURE_TDC_BIT) 271 | FEATURE_MASK(FEATURE_GFX_EDC_BIT) 272 | FEATURE_MASK(FEATURE_APCC_PLUS_BIT) 273 | FEATURE_MASK(FEATURE_VR0HOT_BIT) 274 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) 275 | FEATURE_MASK(FEATURE_THERMAL_BIT) 276 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT) 277 | FEATURE_MASK(FEATURE_DS_LCLK_BIT) 278 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) 279 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) 280 | FEATURE_MASK(FEATURE_BACO_BIT) 281 | FEATURE_MASK(FEATURE_GFX_SS_BIT) 282 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) 283 | FEATURE_MASK(FEATURE_FW_CTF_BIT) 284 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT); 285 286 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) 287 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 288 289 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) 290 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); 291 292 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) 293 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); 294 295 if (adev->pm.pp_feature & PP_ULV_MASK) 296 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); 297 298 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) 299 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 300 301 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 302 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); 303 304 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) 305 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); 306 307 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB) 308 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT); 309 310 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN) 311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT); 312 313 if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG) 314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT); 315 316 if (smu->dc_controlled_by_gpio) 317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT); 318 319 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) 320 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 321 322 /* DPM UCLK enablement should be skipped for navi10 A0 secure board */ 323 if (!(is_asic_secure(smu) && 324 (adev->asic_type == CHIP_NAVI10) && 325 (adev->rev_id == 0)) && 326 (adev->pm.pp_feature & PP_MCLK_DPM_MASK)) 327 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) 328 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) 329 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); 330 331 /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */ 332 if (is_asic_secure(smu) && 333 (adev->asic_type == CHIP_NAVI10) && 334 (adev->rev_id == 0)) 335 *(uint64_t *)feature_mask &= 336 ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT); 337 338 return 0; 339 } 340 341 static int navi10_check_powerplay_table(struct smu_context *smu) 342 { 343 struct smu_table_context *table_context = &smu->smu_table; 344 struct smu_11_0_powerplay_table *powerplay_table = 345 table_context->power_play_table; 346 struct smu_baco_context *smu_baco = &smu->smu_baco; 347 348 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC) 349 smu->dc_controlled_by_gpio = true; 350 351 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO || 352 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) 353 smu_baco->platform_support = true; 354 355 table_context->thermal_controller_type = 356 powerplay_table->thermal_controller_type; 357 358 /* 359 * Instead of having its own buffer space and get overdrive_table copied, 360 * smu->od_settings just points to the actual overdrive_table 361 */ 362 smu->od_settings = &powerplay_table->overdrive_table; 363 364 return 0; 365 } 366 367 static int navi10_append_powerplay_table(struct smu_context *smu) 368 { 369 struct amdgpu_device *adev = smu->adev; 370 struct smu_table_context *table_context = &smu->smu_table; 371 PPTable_t *smc_pptable = table_context->driver_pptable; 372 struct atom_smc_dpm_info_v4_5 *smc_dpm_table; 373 struct atom_smc_dpm_info_v4_7 *smc_dpm_table_v4_7; 374 int index, ret; 375 376 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 377 smc_dpm_info); 378 379 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL, 380 (uint8_t **)&smc_dpm_table); 381 if (ret) 382 return ret; 383 384 dev_info(adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n", 385 smc_dpm_table->table_header.format_revision, 386 smc_dpm_table->table_header.content_revision); 387 388 if (smc_dpm_table->table_header.format_revision != 4) { 389 dev_err(adev->dev, "smc_dpm_info table format revision is not 4!\n"); 390 return -EINVAL; 391 } 392 393 switch (smc_dpm_table->table_header.content_revision) { 394 case 5: /* nv10 and nv14 */ 395 memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers, 396 sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header)); 397 break; 398 case 7: /* nv12 */ 399 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL, 400 (uint8_t **)&smc_dpm_table_v4_7); 401 if (ret) 402 return ret; 403 memcpy(smc_pptable->I2cControllers, smc_dpm_table_v4_7->I2cControllers, 404 sizeof(*smc_dpm_table_v4_7) - sizeof(smc_dpm_table_v4_7->table_header)); 405 break; 406 default: 407 dev_err(smu->adev->dev, "smc_dpm_info with unsupported content revision %d!\n", 408 smc_dpm_table->table_header.content_revision); 409 return -EINVAL; 410 } 411 412 if (adev->pm.pp_feature & PP_GFXOFF_MASK) { 413 /* TODO: remove it once SMU fw fix it */ 414 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN; 415 } 416 417 return 0; 418 } 419 420 static int navi10_store_powerplay_table(struct smu_context *smu) 421 { 422 struct smu_table_context *table_context = &smu->smu_table; 423 struct smu_11_0_powerplay_table *powerplay_table = 424 table_context->power_play_table; 425 426 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 427 sizeof(PPTable_t)); 428 429 return 0; 430 } 431 432 static int navi10_setup_pptable(struct smu_context *smu) 433 { 434 int ret = 0; 435 436 ret = smu_v11_0_setup_pptable(smu); 437 if (ret) 438 return ret; 439 440 ret = navi10_store_powerplay_table(smu); 441 if (ret) 442 return ret; 443 444 ret = navi10_append_powerplay_table(smu); 445 if (ret) 446 return ret; 447 448 ret = navi10_check_powerplay_table(smu); 449 if (ret) 450 return ret; 451 452 return ret; 453 } 454 455 static int navi10_tables_init(struct smu_context *smu) 456 { 457 struct smu_table_context *smu_table = &smu->smu_table; 458 struct smu_table *tables = smu_table->tables; 459 struct amdgpu_device *adev = smu->adev; 460 461 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 462 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 463 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 464 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 465 if (adev->asic_type == CHIP_NAVI12) 466 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_NV12_t), 467 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 468 else 469 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 470 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 471 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 472 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 473 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t), 474 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 475 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 476 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 477 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, 478 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE, 479 AMDGPU_GEM_DOMAIN_VRAM); 480 481 smu_table->metrics_table = kzalloc(adev->asic_type == CHIP_NAVI12 ? 482 sizeof(SmuMetrics_NV12_t) : 483 sizeof(SmuMetrics_t), GFP_KERNEL); 484 if (!smu_table->metrics_table) 485 goto err0_out; 486 smu_table->metrics_time = 0; 487 488 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_0); 489 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 490 if (!smu_table->gpu_metrics_table) 491 goto err1_out; 492 493 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 494 if (!smu_table->watermarks_table) 495 goto err2_out; 496 497 return 0; 498 499 err2_out: 500 kfree(smu_table->gpu_metrics_table); 501 err1_out: 502 kfree(smu_table->metrics_table); 503 err0_out: 504 return -ENOMEM; 505 } 506 507 static int navi10_get_smu_metrics_data(struct smu_context *smu, 508 MetricsMember_t member, 509 uint32_t *value) 510 { 511 struct smu_table_context *smu_table= &smu->smu_table; 512 /* 513 * This works for NV12 also. As although NV12 uses a different 514 * SmuMetrics structure from other NV1X ASICs, they share the 515 * same offsets for the heading parts(those members used here). 516 */ 517 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 518 int ret = 0; 519 520 mutex_lock(&smu->metrics_lock); 521 522 ret = smu_cmn_get_metrics_table_locked(smu, 523 NULL, 524 false); 525 if (ret) { 526 mutex_unlock(&smu->metrics_lock); 527 return ret; 528 } 529 530 switch (member) { 531 case METRICS_CURR_GFXCLK: 532 *value = metrics->CurrClock[PPCLK_GFXCLK]; 533 break; 534 case METRICS_CURR_SOCCLK: 535 *value = metrics->CurrClock[PPCLK_SOCCLK]; 536 break; 537 case METRICS_CURR_UCLK: 538 *value = metrics->CurrClock[PPCLK_UCLK]; 539 break; 540 case METRICS_CURR_VCLK: 541 *value = metrics->CurrClock[PPCLK_VCLK]; 542 break; 543 case METRICS_CURR_DCLK: 544 *value = metrics->CurrClock[PPCLK_DCLK]; 545 break; 546 case METRICS_CURR_DCEFCLK: 547 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 548 break; 549 case METRICS_AVERAGE_GFXCLK: 550 *value = metrics->AverageGfxclkFrequency; 551 break; 552 case METRICS_AVERAGE_SOCCLK: 553 *value = metrics->AverageSocclkFrequency; 554 break; 555 case METRICS_AVERAGE_UCLK: 556 *value = metrics->AverageUclkFrequency; 557 break; 558 case METRICS_AVERAGE_GFXACTIVITY: 559 *value = metrics->AverageGfxActivity; 560 break; 561 case METRICS_AVERAGE_MEMACTIVITY: 562 *value = metrics->AverageUclkActivity; 563 break; 564 case METRICS_AVERAGE_SOCKETPOWER: 565 *value = metrics->AverageSocketPower << 8; 566 break; 567 case METRICS_TEMPERATURE_EDGE: 568 *value = metrics->TemperatureEdge * 569 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 570 break; 571 case METRICS_TEMPERATURE_HOTSPOT: 572 *value = metrics->TemperatureHotspot * 573 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 574 break; 575 case METRICS_TEMPERATURE_MEM: 576 *value = metrics->TemperatureMem * 577 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 578 break; 579 case METRICS_TEMPERATURE_VRGFX: 580 *value = metrics->TemperatureVrGfx * 581 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 582 break; 583 case METRICS_TEMPERATURE_VRSOC: 584 *value = metrics->TemperatureVrSoc * 585 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 586 break; 587 case METRICS_THROTTLER_STATUS: 588 *value = metrics->ThrottlerStatus; 589 break; 590 case METRICS_CURR_FANSPEED: 591 *value = metrics->CurrFanSpeed; 592 break; 593 default: 594 *value = UINT_MAX; 595 break; 596 } 597 598 mutex_unlock(&smu->metrics_lock); 599 600 return ret; 601 } 602 603 static int navi10_allocate_dpm_context(struct smu_context *smu) 604 { 605 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 606 607 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 608 GFP_KERNEL); 609 if (!smu_dpm->dpm_context) 610 return -ENOMEM; 611 612 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 613 614 return 0; 615 } 616 617 static int navi10_init_smc_tables(struct smu_context *smu) 618 { 619 int ret = 0; 620 621 ret = navi10_tables_init(smu); 622 if (ret) 623 return ret; 624 625 ret = navi10_allocate_dpm_context(smu); 626 if (ret) 627 return ret; 628 629 return smu_v11_0_init_smc_tables(smu); 630 } 631 632 static int navi10_set_default_dpm_table(struct smu_context *smu) 633 { 634 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 635 PPTable_t *driver_ppt = smu->smu_table.driver_pptable; 636 struct smu_11_0_dpm_table *dpm_table; 637 int ret = 0; 638 639 /* socclk dpm table setup */ 640 dpm_table = &dpm_context->dpm_tables.soc_table; 641 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 642 ret = smu_v11_0_set_single_dpm_table(smu, 643 SMU_SOCCLK, 644 dpm_table); 645 if (ret) 646 return ret; 647 dpm_table->is_fine_grained = 648 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete; 649 } else { 650 dpm_table->count = 1; 651 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 652 dpm_table->dpm_levels[0].enabled = true; 653 dpm_table->min = dpm_table->dpm_levels[0].value; 654 dpm_table->max = dpm_table->dpm_levels[0].value; 655 } 656 657 /* gfxclk dpm table setup */ 658 dpm_table = &dpm_context->dpm_tables.gfx_table; 659 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 660 ret = smu_v11_0_set_single_dpm_table(smu, 661 SMU_GFXCLK, 662 dpm_table); 663 if (ret) 664 return ret; 665 dpm_table->is_fine_grained = 666 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete; 667 } else { 668 dpm_table->count = 1; 669 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 670 dpm_table->dpm_levels[0].enabled = true; 671 dpm_table->min = dpm_table->dpm_levels[0].value; 672 dpm_table->max = dpm_table->dpm_levels[0].value; 673 } 674 675 /* uclk dpm table setup */ 676 dpm_table = &dpm_context->dpm_tables.uclk_table; 677 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 678 ret = smu_v11_0_set_single_dpm_table(smu, 679 SMU_UCLK, 680 dpm_table); 681 if (ret) 682 return ret; 683 dpm_table->is_fine_grained = 684 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete; 685 } else { 686 dpm_table->count = 1; 687 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 688 dpm_table->dpm_levels[0].enabled = true; 689 dpm_table->min = dpm_table->dpm_levels[0].value; 690 dpm_table->max = dpm_table->dpm_levels[0].value; 691 } 692 693 /* vclk dpm table setup */ 694 dpm_table = &dpm_context->dpm_tables.vclk_table; 695 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 696 ret = smu_v11_0_set_single_dpm_table(smu, 697 SMU_VCLK, 698 dpm_table); 699 if (ret) 700 return ret; 701 dpm_table->is_fine_grained = 702 !driver_ppt->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete; 703 } else { 704 dpm_table->count = 1; 705 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; 706 dpm_table->dpm_levels[0].enabled = true; 707 dpm_table->min = dpm_table->dpm_levels[0].value; 708 dpm_table->max = dpm_table->dpm_levels[0].value; 709 } 710 711 /* dclk dpm table setup */ 712 dpm_table = &dpm_context->dpm_tables.dclk_table; 713 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 714 ret = smu_v11_0_set_single_dpm_table(smu, 715 SMU_DCLK, 716 dpm_table); 717 if (ret) 718 return ret; 719 dpm_table->is_fine_grained = 720 !driver_ppt->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete; 721 } else { 722 dpm_table->count = 1; 723 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; 724 dpm_table->dpm_levels[0].enabled = true; 725 dpm_table->min = dpm_table->dpm_levels[0].value; 726 dpm_table->max = dpm_table->dpm_levels[0].value; 727 } 728 729 /* dcefclk dpm table setup */ 730 dpm_table = &dpm_context->dpm_tables.dcef_table; 731 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 732 ret = smu_v11_0_set_single_dpm_table(smu, 733 SMU_DCEFCLK, 734 dpm_table); 735 if (ret) 736 return ret; 737 dpm_table->is_fine_grained = 738 !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete; 739 } else { 740 dpm_table->count = 1; 741 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 742 dpm_table->dpm_levels[0].enabled = true; 743 dpm_table->min = dpm_table->dpm_levels[0].value; 744 dpm_table->max = dpm_table->dpm_levels[0].value; 745 } 746 747 /* pixelclk dpm table setup */ 748 dpm_table = &dpm_context->dpm_tables.pixel_table; 749 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 750 ret = smu_v11_0_set_single_dpm_table(smu, 751 SMU_PIXCLK, 752 dpm_table); 753 if (ret) 754 return ret; 755 dpm_table->is_fine_grained = 756 !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete; 757 } else { 758 dpm_table->count = 1; 759 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 760 dpm_table->dpm_levels[0].enabled = true; 761 dpm_table->min = dpm_table->dpm_levels[0].value; 762 dpm_table->max = dpm_table->dpm_levels[0].value; 763 } 764 765 /* displayclk dpm table setup */ 766 dpm_table = &dpm_context->dpm_tables.display_table; 767 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 768 ret = smu_v11_0_set_single_dpm_table(smu, 769 SMU_DISPCLK, 770 dpm_table); 771 if (ret) 772 return ret; 773 dpm_table->is_fine_grained = 774 !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete; 775 } else { 776 dpm_table->count = 1; 777 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 778 dpm_table->dpm_levels[0].enabled = true; 779 dpm_table->min = dpm_table->dpm_levels[0].value; 780 dpm_table->max = dpm_table->dpm_levels[0].value; 781 } 782 783 /* phyclk dpm table setup */ 784 dpm_table = &dpm_context->dpm_tables.phy_table; 785 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 786 ret = smu_v11_0_set_single_dpm_table(smu, 787 SMU_PHYCLK, 788 dpm_table); 789 if (ret) 790 return ret; 791 dpm_table->is_fine_grained = 792 !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete; 793 } else { 794 dpm_table->count = 1; 795 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 796 dpm_table->dpm_levels[0].enabled = true; 797 dpm_table->min = dpm_table->dpm_levels[0].value; 798 dpm_table->max = dpm_table->dpm_levels[0].value; 799 } 800 801 return 0; 802 } 803 804 static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 805 { 806 int ret = 0; 807 808 if (enable) { 809 /* vcn dpm on is a prerequisite for vcn power gate messages */ 810 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 811 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL); 812 if (ret) 813 return ret; 814 } 815 } else { 816 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 817 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL); 818 if (ret) 819 return ret; 820 } 821 } 822 823 return ret; 824 } 825 826 static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 827 { 828 int ret = 0; 829 830 if (enable) { 831 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 832 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerUpJpeg, NULL); 833 if (ret) 834 return ret; 835 } 836 } else { 837 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { 838 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL); 839 if (ret) 840 return ret; 841 } 842 } 843 844 return ret; 845 } 846 847 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu, 848 enum smu_clk_type clk_type, 849 uint32_t *value) 850 { 851 MetricsMember_t member_type; 852 int clk_id = 0; 853 854 clk_id = smu_cmn_to_asic_specific_index(smu, 855 CMN2ASIC_MAPPING_CLK, 856 clk_type); 857 if (clk_id < 0) 858 return clk_id; 859 860 switch (clk_id) { 861 case PPCLK_GFXCLK: 862 member_type = METRICS_CURR_GFXCLK; 863 break; 864 case PPCLK_UCLK: 865 member_type = METRICS_CURR_UCLK; 866 break; 867 case PPCLK_SOCCLK: 868 member_type = METRICS_CURR_SOCCLK; 869 break; 870 case PPCLK_VCLK: 871 member_type = METRICS_CURR_VCLK; 872 break; 873 case PPCLK_DCLK: 874 member_type = METRICS_CURR_DCLK; 875 break; 876 case PPCLK_DCEFCLK: 877 member_type = METRICS_CURR_DCEFCLK; 878 break; 879 default: 880 return -EINVAL; 881 } 882 883 return navi10_get_smu_metrics_data(smu, 884 member_type, 885 value); 886 } 887 888 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) 889 { 890 PPTable_t *pptable = smu->smu_table.driver_pptable; 891 DpmDescriptor_t *dpm_desc = NULL; 892 uint32_t clk_index = 0; 893 894 clk_index = smu_cmn_to_asic_specific_index(smu, 895 CMN2ASIC_MAPPING_CLK, 896 clk_type); 897 dpm_desc = &pptable->DpmDescriptor[clk_index]; 898 899 /* 0 - Fine grained DPM, 1 - Discrete DPM */ 900 return dpm_desc->SnapToDiscrete == 0 ? true : false; 901 } 902 903 static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap) 904 { 905 return od_table->cap[cap]; 906 } 907 908 static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table, 909 enum SMU_11_0_ODSETTING_ID setting, 910 uint32_t *min, uint32_t *max) 911 { 912 if (min) 913 *min = od_table->min[setting]; 914 if (max) 915 *max = od_table->max[setting]; 916 } 917 918 static int navi10_print_clk_levels(struct smu_context *smu, 919 enum smu_clk_type clk_type, char *buf) 920 { 921 uint16_t *curve_settings; 922 int i, size = 0, ret = 0; 923 uint32_t cur_value = 0, value = 0, count = 0; 924 uint32_t freq_values[3] = {0}; 925 uint32_t mark_index = 0; 926 struct smu_table_context *table_context = &smu->smu_table; 927 uint32_t gen_speed, lane_width; 928 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 929 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; 930 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable; 931 OverDriveTable_t *od_table = 932 (OverDriveTable_t *)table_context->overdrive_table; 933 struct smu_11_0_overdrive_table *od_settings = smu->od_settings; 934 uint32_t min_value, max_value; 935 936 switch (clk_type) { 937 case SMU_GFXCLK: 938 case SMU_SCLK: 939 case SMU_SOCCLK: 940 case SMU_MCLK: 941 case SMU_UCLK: 942 case SMU_FCLK: 943 case SMU_DCEFCLK: 944 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value); 945 if (ret) 946 return size; 947 948 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); 949 if (ret) 950 return size; 951 952 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) { 953 for (i = 0; i < count; i++) { 954 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); 955 if (ret) 956 return size; 957 958 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, 959 cur_value == value ? "*" : ""); 960 } 961 } else { 962 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]); 963 if (ret) 964 return size; 965 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]); 966 if (ret) 967 return size; 968 969 freq_values[1] = cur_value; 970 mark_index = cur_value == freq_values[0] ? 0 : 971 cur_value == freq_values[2] ? 2 : 1; 972 if (mark_index != 1) 973 freq_values[1] = (freq_values[0] + freq_values[2]) / 2; 974 975 for (i = 0; i < 3; i++) { 976 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i], 977 i == mark_index ? "*" : ""); 978 } 979 980 } 981 break; 982 case SMU_PCIE: 983 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); 984 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); 985 for (i = 0; i < NUM_LINK_LEVELS; i++) 986 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i, 987 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," : 988 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," : 989 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," : 990 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "", 991 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" : 992 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" : 993 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" : 994 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" : 995 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" : 996 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "", 997 pptable->LclkFreq[i], 998 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && 999 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? 1000 "*" : ""); 1001 break; 1002 case SMU_OD_SCLK: 1003 if (!smu->od_enabled || !od_table || !od_settings) 1004 break; 1005 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) 1006 break; 1007 size += sprintf(buf + size, "OD_SCLK:\n"); 1008 size += sprintf(buf + size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax); 1009 break; 1010 case SMU_OD_MCLK: 1011 if (!smu->od_enabled || !od_table || !od_settings) 1012 break; 1013 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) 1014 break; 1015 size += sprintf(buf + size, "OD_MCLK:\n"); 1016 size += sprintf(buf + size, "1: %uMHz\n", od_table->UclkFmax); 1017 break; 1018 case SMU_OD_VDDC_CURVE: 1019 if (!smu->od_enabled || !od_table || !od_settings) 1020 break; 1021 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) 1022 break; 1023 size += sprintf(buf + size, "OD_VDDC_CURVE:\n"); 1024 for (i = 0; i < 3; i++) { 1025 switch (i) { 1026 case 0: 1027 curve_settings = &od_table->GfxclkFreq1; 1028 break; 1029 case 1: 1030 curve_settings = &od_table->GfxclkFreq2; 1031 break; 1032 case 2: 1033 curve_settings = &od_table->GfxclkFreq3; 1034 break; 1035 default: 1036 break; 1037 } 1038 size += sprintf(buf + size, "%d: %uMHz %umV\n", i, curve_settings[0], curve_settings[1] / NAVI10_VOLTAGE_SCALE); 1039 } 1040 break; 1041 case SMU_OD_RANGE: 1042 if (!smu->od_enabled || !od_table || !od_settings) 1043 break; 1044 size = sprintf(buf, "%s:\n", "OD_RANGE"); 1045 1046 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) { 1047 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN, 1048 &min_value, NULL); 1049 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX, 1050 NULL, &max_value); 1051 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n", 1052 min_value, max_value); 1053 } 1054 1055 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) { 1056 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX, 1057 &min_value, &max_value); 1058 size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n", 1059 min_value, max_value); 1060 } 1061 1062 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) { 1063 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1, 1064 &min_value, &max_value); 1065 size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n", 1066 min_value, max_value); 1067 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1, 1068 &min_value, &max_value); 1069 size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n", 1070 min_value, max_value); 1071 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2, 1072 &min_value, &max_value); 1073 size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n", 1074 min_value, max_value); 1075 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2, 1076 &min_value, &max_value); 1077 size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n", 1078 min_value, max_value); 1079 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3, 1080 &min_value, &max_value); 1081 size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n", 1082 min_value, max_value); 1083 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3, 1084 &min_value, &max_value); 1085 size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n", 1086 min_value, max_value); 1087 } 1088 1089 break; 1090 default: 1091 break; 1092 } 1093 1094 return size; 1095 } 1096 1097 static int navi10_force_clk_levels(struct smu_context *smu, 1098 enum smu_clk_type clk_type, uint32_t mask) 1099 { 1100 1101 int ret = 0, size = 0; 1102 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; 1103 1104 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1105 soft_max_level = mask ? (fls(mask) - 1) : 0; 1106 1107 switch (clk_type) { 1108 case SMU_GFXCLK: 1109 case SMU_SCLK: 1110 case SMU_SOCCLK: 1111 case SMU_MCLK: 1112 case SMU_UCLK: 1113 case SMU_DCEFCLK: 1114 case SMU_FCLK: 1115 /* There is only 2 levels for fine grained DPM */ 1116 if (navi10_is_support_fine_grained_dpm(smu, clk_type)) { 1117 soft_max_level = (soft_max_level >= 1 ? 1 : 0); 1118 soft_min_level = (soft_min_level >= 1 ? 1 : 0); 1119 } 1120 1121 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); 1122 if (ret) 1123 return size; 1124 1125 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq); 1126 if (ret) 1127 return size; 1128 1129 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 1130 if (ret) 1131 return size; 1132 break; 1133 default: 1134 break; 1135 } 1136 1137 return size; 1138 } 1139 1140 static int navi10_populate_umd_state_clk(struct smu_context *smu) 1141 { 1142 struct smu_11_0_dpm_context *dpm_context = 1143 smu->smu_dpm.dpm_context; 1144 struct smu_11_0_dpm_table *gfx_table = 1145 &dpm_context->dpm_tables.gfx_table; 1146 struct smu_11_0_dpm_table *mem_table = 1147 &dpm_context->dpm_tables.uclk_table; 1148 struct smu_11_0_dpm_table *soc_table = 1149 &dpm_context->dpm_tables.soc_table; 1150 struct smu_umd_pstate_table *pstate_table = 1151 &smu->pstate_table; 1152 struct amdgpu_device *adev = smu->adev; 1153 uint32_t sclk_freq; 1154 1155 pstate_table->gfxclk_pstate.min = gfx_table->min; 1156 switch (adev->asic_type) { 1157 case CHIP_NAVI10: 1158 switch (adev->pdev->revision) { 1159 case 0xf0: /* XTX */ 1160 case 0xc0: 1161 sclk_freq = NAVI10_PEAK_SCLK_XTX; 1162 break; 1163 case 0xf1: /* XT */ 1164 case 0xc1: 1165 sclk_freq = NAVI10_PEAK_SCLK_XT; 1166 break; 1167 default: /* XL */ 1168 sclk_freq = NAVI10_PEAK_SCLK_XL; 1169 break; 1170 } 1171 break; 1172 case CHIP_NAVI14: 1173 switch (adev->pdev->revision) { 1174 case 0xc7: /* XT */ 1175 case 0xf4: 1176 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK; 1177 break; 1178 case 0xc1: /* XTM */ 1179 case 0xf2: 1180 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK; 1181 break; 1182 case 0xc3: /* XLM */ 1183 case 0xf3: 1184 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK; 1185 break; 1186 case 0xc5: /* XTX */ 1187 case 0xf6: 1188 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK; 1189 break; 1190 default: /* XL */ 1191 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK; 1192 break; 1193 } 1194 break; 1195 case CHIP_NAVI12: 1196 sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK; 1197 break; 1198 default: 1199 sclk_freq = gfx_table->dpm_levels[gfx_table->count - 1].value; 1200 break; 1201 } 1202 pstate_table->gfxclk_pstate.peak = sclk_freq; 1203 1204 pstate_table->uclk_pstate.min = mem_table->min; 1205 pstate_table->uclk_pstate.peak = mem_table->max; 1206 1207 pstate_table->socclk_pstate.min = soc_table->min; 1208 pstate_table->socclk_pstate.peak = soc_table->max; 1209 1210 if (gfx_table->max > NAVI10_UMD_PSTATE_PROFILING_GFXCLK && 1211 mem_table->max > NAVI10_UMD_PSTATE_PROFILING_MEMCLK && 1212 soc_table->max > NAVI10_UMD_PSTATE_PROFILING_SOCCLK) { 1213 pstate_table->gfxclk_pstate.standard = 1214 NAVI10_UMD_PSTATE_PROFILING_GFXCLK; 1215 pstate_table->uclk_pstate.standard = 1216 NAVI10_UMD_PSTATE_PROFILING_MEMCLK; 1217 pstate_table->socclk_pstate.standard = 1218 NAVI10_UMD_PSTATE_PROFILING_SOCCLK; 1219 } else { 1220 pstate_table->gfxclk_pstate.standard = 1221 pstate_table->gfxclk_pstate.min; 1222 pstate_table->uclk_pstate.standard = 1223 pstate_table->uclk_pstate.min; 1224 pstate_table->socclk_pstate.standard = 1225 pstate_table->socclk_pstate.min; 1226 } 1227 1228 return 0; 1229 } 1230 1231 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu, 1232 enum smu_clk_type clk_type, 1233 struct pp_clock_levels_with_latency *clocks) 1234 { 1235 int ret = 0, i = 0; 1236 uint32_t level_count = 0, freq = 0; 1237 1238 switch (clk_type) { 1239 case SMU_GFXCLK: 1240 case SMU_DCEFCLK: 1241 case SMU_SOCCLK: 1242 case SMU_MCLK: 1243 case SMU_UCLK: 1244 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &level_count); 1245 if (ret) 1246 return ret; 1247 1248 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS); 1249 clocks->num_levels = level_count; 1250 1251 for (i = 0; i < level_count; i++) { 1252 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &freq); 1253 if (ret) 1254 return ret; 1255 1256 clocks->data[i].clocks_in_khz = freq * 1000; 1257 clocks->data[i].latency_in_us = 0; 1258 } 1259 break; 1260 default: 1261 break; 1262 } 1263 1264 return ret; 1265 } 1266 1267 static int navi10_pre_display_config_changed(struct smu_context *smu) 1268 { 1269 int ret = 0; 1270 uint32_t max_freq = 0; 1271 1272 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL); 1273 if (ret) 1274 return ret; 1275 1276 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1277 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq); 1278 if (ret) 1279 return ret; 1280 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq); 1281 if (ret) 1282 return ret; 1283 } 1284 1285 return ret; 1286 } 1287 1288 static int navi10_display_config_changed(struct smu_context *smu) 1289 { 1290 int ret = 0; 1291 1292 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1293 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) && 1294 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 1295 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 1296 smu->display_config->num_display, 1297 NULL); 1298 if (ret) 1299 return ret; 1300 } 1301 1302 return ret; 1303 } 1304 1305 static bool navi10_is_dpm_running(struct smu_context *smu) 1306 { 1307 int ret = 0; 1308 uint32_t feature_mask[2]; 1309 uint64_t feature_enabled; 1310 1311 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2); 1312 if (ret) 1313 return false; 1314 1315 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0]; 1316 1317 return !!(feature_enabled & SMC_DPM_FEATURE); 1318 } 1319 1320 static int navi10_get_fan_speed_percent(struct smu_context *smu, 1321 uint32_t *speed) 1322 { 1323 int ret; 1324 u32 rpm; 1325 1326 if (!speed) 1327 return -EINVAL; 1328 1329 switch (smu_v11_0_get_fan_control_mode(smu)) { 1330 case AMD_FAN_CTRL_AUTO: 1331 ret = navi10_get_smu_metrics_data(smu, 1332 METRICS_CURR_FANSPEED, 1333 &rpm); 1334 if (!ret && smu->fan_max_rpm) 1335 *speed = rpm * 100 / smu->fan_max_rpm; 1336 return ret; 1337 default: 1338 *speed = smu->user_dpm_profile.fan_speed_percent; 1339 return 0; 1340 } 1341 } 1342 1343 static int navi10_get_fan_parameters(struct smu_context *smu) 1344 { 1345 PPTable_t *pptable = smu->smu_table.driver_pptable; 1346 1347 smu->fan_max_rpm = pptable->FanMaximumRpm; 1348 1349 return 0; 1350 } 1351 1352 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf) 1353 { 1354 DpmActivityMonitorCoeffInt_t activity_monitor; 1355 uint32_t i, size = 0; 1356 int16_t workload_type = 0; 1357 static const char *profile_name[] = { 1358 "BOOTUP_DEFAULT", 1359 "3D_FULL_SCREEN", 1360 "POWER_SAVING", 1361 "VIDEO", 1362 "VR", 1363 "COMPUTE", 1364 "CUSTOM"}; 1365 static const char *title[] = { 1366 "PROFILE_INDEX(NAME)", 1367 "CLOCK_TYPE(NAME)", 1368 "FPS", 1369 "MinFreqType", 1370 "MinActiveFreqType", 1371 "MinActiveFreq", 1372 "BoosterFreqType", 1373 "BoosterFreq", 1374 "PD_Data_limit_c", 1375 "PD_Data_error_coeff", 1376 "PD_Data_error_rate_coeff"}; 1377 int result = 0; 1378 1379 if (!buf) 1380 return -EINVAL; 1381 1382 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n", 1383 title[0], title[1], title[2], title[3], title[4], title[5], 1384 title[6], title[7], title[8], title[9], title[10]); 1385 1386 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1387 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1388 workload_type = smu_cmn_to_asic_specific_index(smu, 1389 CMN2ASIC_MAPPING_WORKLOAD, 1390 i); 1391 if (workload_type < 0) 1392 return -EINVAL; 1393 1394 result = smu_cmn_update_table(smu, 1395 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type, 1396 (void *)(&activity_monitor), false); 1397 if (result) { 1398 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1399 return result; 1400 } 1401 1402 size += sprintf(buf + size, "%2d %14s%s:\n", 1403 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1404 1405 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1406 " ", 1407 0, 1408 "GFXCLK", 1409 activity_monitor.Gfx_FPS, 1410 activity_monitor.Gfx_MinFreqStep, 1411 activity_monitor.Gfx_MinActiveFreqType, 1412 activity_monitor.Gfx_MinActiveFreq, 1413 activity_monitor.Gfx_BoosterFreqType, 1414 activity_monitor.Gfx_BoosterFreq, 1415 activity_monitor.Gfx_PD_Data_limit_c, 1416 activity_monitor.Gfx_PD_Data_error_coeff, 1417 activity_monitor.Gfx_PD_Data_error_rate_coeff); 1418 1419 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1420 " ", 1421 1, 1422 "SOCCLK", 1423 activity_monitor.Soc_FPS, 1424 activity_monitor.Soc_MinFreqStep, 1425 activity_monitor.Soc_MinActiveFreqType, 1426 activity_monitor.Soc_MinActiveFreq, 1427 activity_monitor.Soc_BoosterFreqType, 1428 activity_monitor.Soc_BoosterFreq, 1429 activity_monitor.Soc_PD_Data_limit_c, 1430 activity_monitor.Soc_PD_Data_error_coeff, 1431 activity_monitor.Soc_PD_Data_error_rate_coeff); 1432 1433 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1434 " ", 1435 2, 1436 "MEMLK", 1437 activity_monitor.Mem_FPS, 1438 activity_monitor.Mem_MinFreqStep, 1439 activity_monitor.Mem_MinActiveFreqType, 1440 activity_monitor.Mem_MinActiveFreq, 1441 activity_monitor.Mem_BoosterFreqType, 1442 activity_monitor.Mem_BoosterFreq, 1443 activity_monitor.Mem_PD_Data_limit_c, 1444 activity_monitor.Mem_PD_Data_error_coeff, 1445 activity_monitor.Mem_PD_Data_error_rate_coeff); 1446 } 1447 1448 return size; 1449 } 1450 1451 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 1452 { 1453 DpmActivityMonitorCoeffInt_t activity_monitor; 1454 int workload_type, ret = 0; 1455 1456 smu->power_profile_mode = input[size]; 1457 1458 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 1459 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode); 1460 return -EINVAL; 1461 } 1462 1463 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 1464 1465 ret = smu_cmn_update_table(smu, 1466 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1467 (void *)(&activity_monitor), false); 1468 if (ret) { 1469 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1470 return ret; 1471 } 1472 1473 switch (input[0]) { 1474 case 0: /* Gfxclk */ 1475 activity_monitor.Gfx_FPS = input[1]; 1476 activity_monitor.Gfx_MinFreqStep = input[2]; 1477 activity_monitor.Gfx_MinActiveFreqType = input[3]; 1478 activity_monitor.Gfx_MinActiveFreq = input[4]; 1479 activity_monitor.Gfx_BoosterFreqType = input[5]; 1480 activity_monitor.Gfx_BoosterFreq = input[6]; 1481 activity_monitor.Gfx_PD_Data_limit_c = input[7]; 1482 activity_monitor.Gfx_PD_Data_error_coeff = input[8]; 1483 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9]; 1484 break; 1485 case 1: /* Socclk */ 1486 activity_monitor.Soc_FPS = input[1]; 1487 activity_monitor.Soc_MinFreqStep = input[2]; 1488 activity_monitor.Soc_MinActiveFreqType = input[3]; 1489 activity_monitor.Soc_MinActiveFreq = input[4]; 1490 activity_monitor.Soc_BoosterFreqType = input[5]; 1491 activity_monitor.Soc_BoosterFreq = input[6]; 1492 activity_monitor.Soc_PD_Data_limit_c = input[7]; 1493 activity_monitor.Soc_PD_Data_error_coeff = input[8]; 1494 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9]; 1495 break; 1496 case 2: /* Memlk */ 1497 activity_monitor.Mem_FPS = input[1]; 1498 activity_monitor.Mem_MinFreqStep = input[2]; 1499 activity_monitor.Mem_MinActiveFreqType = input[3]; 1500 activity_monitor.Mem_MinActiveFreq = input[4]; 1501 activity_monitor.Mem_BoosterFreqType = input[5]; 1502 activity_monitor.Mem_BoosterFreq = input[6]; 1503 activity_monitor.Mem_PD_Data_limit_c = input[7]; 1504 activity_monitor.Mem_PD_Data_error_coeff = input[8]; 1505 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9]; 1506 break; 1507 } 1508 1509 ret = smu_cmn_update_table(smu, 1510 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1511 (void *)(&activity_monitor), true); 1512 if (ret) { 1513 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 1514 return ret; 1515 } 1516 } 1517 1518 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1519 workload_type = smu_cmn_to_asic_specific_index(smu, 1520 CMN2ASIC_MAPPING_WORKLOAD, 1521 smu->power_profile_mode); 1522 if (workload_type < 0) 1523 return -EINVAL; 1524 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 1525 1 << workload_type, NULL); 1526 1527 return ret; 1528 } 1529 1530 static int navi10_notify_smc_display_config(struct smu_context *smu) 1531 { 1532 struct smu_clocks min_clocks = {0}; 1533 struct pp_display_clock_request clock_req; 1534 int ret = 0; 1535 1536 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; 1537 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; 1538 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; 1539 1540 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1541 clock_req.clock_type = amd_pp_dcef_clock; 1542 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; 1543 1544 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req); 1545 if (!ret) { 1546 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) { 1547 ret = smu_cmn_send_smc_msg_with_param(smu, 1548 SMU_MSG_SetMinDeepSleepDcefclk, 1549 min_clocks.dcef_clock_in_sr/100, 1550 NULL); 1551 if (ret) { 1552 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!"); 1553 return ret; 1554 } 1555 } 1556 } else { 1557 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!"); 1558 } 1559 } 1560 1561 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1562 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); 1563 if (ret) { 1564 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__); 1565 return ret; 1566 } 1567 } 1568 1569 return 0; 1570 } 1571 1572 static int navi10_set_watermarks_table(struct smu_context *smu, 1573 struct pp_smu_wm_range_sets *clock_ranges) 1574 { 1575 Watermarks_t *table = smu->smu_table.watermarks_table; 1576 int ret = 0; 1577 int i; 1578 1579 if (clock_ranges) { 1580 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 1581 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1582 return -EINVAL; 1583 1584 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1585 table->WatermarkRow[WM_DCEFCLK][i].MinClock = 1586 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1587 table->WatermarkRow[WM_DCEFCLK][i].MaxClock = 1588 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1589 table->WatermarkRow[WM_DCEFCLK][i].MinUclk = 1590 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1591 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk = 1592 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1593 1594 table->WatermarkRow[WM_DCEFCLK][i].WmSetting = 1595 clock_ranges->reader_wm_sets[i].wm_inst; 1596 } 1597 1598 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1599 table->WatermarkRow[WM_SOCCLK][i].MinClock = 1600 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1601 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1602 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1603 table->WatermarkRow[WM_SOCCLK][i].MinUclk = 1604 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1605 table->WatermarkRow[WM_SOCCLK][i].MaxUclk = 1606 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1607 1608 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1609 clock_ranges->writer_wm_sets[i].wm_inst; 1610 } 1611 1612 smu->watermarks_bitmap |= WATERMARKS_EXIST; 1613 } 1614 1615 /* pass data to smu controller */ 1616 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1617 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1618 ret = smu_cmn_write_watermarks_table(smu); 1619 if (ret) { 1620 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1621 return ret; 1622 } 1623 smu->watermarks_bitmap |= WATERMARKS_LOADED; 1624 } 1625 1626 return 0; 1627 } 1628 1629 static int navi10_read_sensor(struct smu_context *smu, 1630 enum amd_pp_sensors sensor, 1631 void *data, uint32_t *size) 1632 { 1633 int ret = 0; 1634 struct smu_table_context *table_context = &smu->smu_table; 1635 PPTable_t *pptable = table_context->driver_pptable; 1636 1637 if(!data || !size) 1638 return -EINVAL; 1639 1640 mutex_lock(&smu->sensor_lock); 1641 switch (sensor) { 1642 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 1643 *(uint32_t *)data = pptable->FanMaximumRpm; 1644 *size = 4; 1645 break; 1646 case AMDGPU_PP_SENSOR_MEM_LOAD: 1647 ret = navi10_get_smu_metrics_data(smu, 1648 METRICS_AVERAGE_MEMACTIVITY, 1649 (uint32_t *)data); 1650 *size = 4; 1651 break; 1652 case AMDGPU_PP_SENSOR_GPU_LOAD: 1653 ret = navi10_get_smu_metrics_data(smu, 1654 METRICS_AVERAGE_GFXACTIVITY, 1655 (uint32_t *)data); 1656 *size = 4; 1657 break; 1658 case AMDGPU_PP_SENSOR_GPU_POWER: 1659 ret = navi10_get_smu_metrics_data(smu, 1660 METRICS_AVERAGE_SOCKETPOWER, 1661 (uint32_t *)data); 1662 *size = 4; 1663 break; 1664 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1665 ret = navi10_get_smu_metrics_data(smu, 1666 METRICS_TEMPERATURE_HOTSPOT, 1667 (uint32_t *)data); 1668 *size = 4; 1669 break; 1670 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1671 ret = navi10_get_smu_metrics_data(smu, 1672 METRICS_TEMPERATURE_EDGE, 1673 (uint32_t *)data); 1674 *size = 4; 1675 break; 1676 case AMDGPU_PP_SENSOR_MEM_TEMP: 1677 ret = navi10_get_smu_metrics_data(smu, 1678 METRICS_TEMPERATURE_MEM, 1679 (uint32_t *)data); 1680 *size = 4; 1681 break; 1682 case AMDGPU_PP_SENSOR_GFX_MCLK: 1683 ret = navi10_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 1684 *(uint32_t *)data *= 100; 1685 *size = 4; 1686 break; 1687 case AMDGPU_PP_SENSOR_GFX_SCLK: 1688 ret = navi10_get_smu_metrics_data(smu, METRICS_AVERAGE_GFXCLK, (uint32_t *)data); 1689 *(uint32_t *)data *= 100; 1690 *size = 4; 1691 break; 1692 case AMDGPU_PP_SENSOR_VDDGFX: 1693 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data); 1694 *size = 4; 1695 break; 1696 default: 1697 ret = -EOPNOTSUPP; 1698 break; 1699 } 1700 mutex_unlock(&smu->sensor_lock); 1701 1702 return ret; 1703 } 1704 1705 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states) 1706 { 1707 uint32_t num_discrete_levels = 0; 1708 uint16_t *dpm_levels = NULL; 1709 uint16_t i = 0; 1710 struct smu_table_context *table_context = &smu->smu_table; 1711 PPTable_t *driver_ppt = NULL; 1712 1713 if (!clocks_in_khz || !num_states || !table_context->driver_pptable) 1714 return -EINVAL; 1715 1716 driver_ppt = table_context->driver_pptable; 1717 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels; 1718 dpm_levels = driver_ppt->FreqTableUclk; 1719 1720 if (num_discrete_levels == 0 || dpm_levels == NULL) 1721 return -EINVAL; 1722 1723 *num_states = num_discrete_levels; 1724 for (i = 0; i < num_discrete_levels; i++) { 1725 /* convert to khz */ 1726 *clocks_in_khz = (*dpm_levels) * 1000; 1727 clocks_in_khz++; 1728 dpm_levels++; 1729 } 1730 1731 return 0; 1732 } 1733 1734 static int navi10_get_thermal_temperature_range(struct smu_context *smu, 1735 struct smu_temperature_range *range) 1736 { 1737 struct smu_table_context *table_context = &smu->smu_table; 1738 struct smu_11_0_powerplay_table *powerplay_table = 1739 table_context->power_play_table; 1740 PPTable_t *pptable = smu->smu_table.driver_pptable; 1741 1742 if (!range) 1743 return -EINVAL; 1744 1745 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range)); 1746 1747 range->max = pptable->TedgeLimit * 1748 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1749 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) * 1750 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1751 range->hotspot_crit_max = pptable->ThotspotLimit * 1752 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1753 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 1754 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1755 range->mem_crit_max = pptable->TmemLimit * 1756 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1757 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)* 1758 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1759 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 1760 1761 return 0; 1762 } 1763 1764 static int navi10_display_disable_memory_clock_switch(struct smu_context *smu, 1765 bool disable_memory_clock_switch) 1766 { 1767 int ret = 0; 1768 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks = 1769 (struct smu_11_0_max_sustainable_clocks *) 1770 smu->smu_table.max_sustainable_clocks; 1771 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal; 1772 uint32_t max_memory_clock = max_sustainable_clocks->uclock; 1773 1774 if(smu->disable_uclk_switch == disable_memory_clock_switch) 1775 return 0; 1776 1777 if(disable_memory_clock_switch) 1778 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0); 1779 else 1780 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0); 1781 1782 if(!ret) 1783 smu->disable_uclk_switch = disable_memory_clock_switch; 1784 1785 return ret; 1786 } 1787 1788 static int navi10_get_power_limit(struct smu_context *smu) 1789 { 1790 struct smu_11_0_powerplay_table *powerplay_table = 1791 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table; 1792 struct smu_11_0_overdrive_table *od_settings = smu->od_settings; 1793 PPTable_t *pptable = smu->smu_table.driver_pptable; 1794 uint32_t power_limit, od_percent; 1795 1796 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) { 1797 /* the last hope to figure out the ppt limit */ 1798 if (!pptable) { 1799 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!"); 1800 return -EINVAL; 1801 } 1802 power_limit = 1803 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0]; 1804 } 1805 smu->current_power_limit = power_limit; 1806 1807 if (smu->od_enabled && 1808 navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) { 1809 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]); 1810 1811 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit); 1812 1813 power_limit *= (100 + od_percent); 1814 power_limit /= 100; 1815 } 1816 smu->max_power_limit = power_limit; 1817 1818 return 0; 1819 } 1820 1821 static int navi10_update_pcie_parameters(struct smu_context *smu, 1822 uint32_t pcie_gen_cap, 1823 uint32_t pcie_width_cap) 1824 { 1825 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 1826 PPTable_t *pptable = smu->smu_table.driver_pptable; 1827 uint32_t smu_pcie_arg; 1828 int ret, i; 1829 1830 /* lclk dpm table setup */ 1831 for (i = 0; i < MAX_PCIE_CONF; i++) { 1832 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i]; 1833 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i]; 1834 } 1835 1836 for (i = 0; i < NUM_LINK_LEVELS; i++) { 1837 smu_pcie_arg = (i << 16) | 1838 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) : 1839 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ? 1840 pptable->PcieLaneCount[i] : pcie_width_cap); 1841 ret = smu_cmn_send_smc_msg_with_param(smu, 1842 SMU_MSG_OverridePcieParameters, 1843 smu_pcie_arg, 1844 NULL); 1845 1846 if (ret) 1847 return ret; 1848 1849 if (pptable->PcieGenSpeed[i] > pcie_gen_cap) 1850 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap; 1851 if (pptable->PcieLaneCount[i] > pcie_width_cap) 1852 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap; 1853 } 1854 1855 return 0; 1856 } 1857 1858 static inline void navi10_dump_od_table(struct smu_context *smu, 1859 OverDriveTable_t *od_table) 1860 { 1861 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax); 1862 dev_dbg(smu->adev->dev, "OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1); 1863 dev_dbg(smu->adev->dev, "OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2); 1864 dev_dbg(smu->adev->dev, "OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3); 1865 dev_dbg(smu->adev->dev, "OD: UclkFmax: %d\n", od_table->UclkFmax); 1866 dev_dbg(smu->adev->dev, "OD: OverDrivePct: %d\n", od_table->OverDrivePct); 1867 } 1868 1869 static int navi10_od_setting_check_range(struct smu_context *smu, 1870 struct smu_11_0_overdrive_table *od_table, 1871 enum SMU_11_0_ODSETTING_ID setting, 1872 uint32_t value) 1873 { 1874 if (value < od_table->min[setting]) { 1875 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]); 1876 return -EINVAL; 1877 } 1878 if (value > od_table->max[setting]) { 1879 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]); 1880 return -EINVAL; 1881 } 1882 return 0; 1883 } 1884 1885 static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu, 1886 uint16_t *voltage, 1887 uint32_t freq) 1888 { 1889 uint32_t param = (freq & 0xFFFF) | (PPCLK_GFXCLK << 16); 1890 uint32_t value = 0; 1891 int ret; 1892 1893 ret = smu_cmn_send_smc_msg_with_param(smu, 1894 SMU_MSG_GetVoltageByDpm, 1895 param, 1896 &value); 1897 if (ret) { 1898 dev_err(smu->adev->dev, "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!"); 1899 return ret; 1900 } 1901 1902 *voltage = (uint16_t)value; 1903 1904 return 0; 1905 } 1906 1907 static bool navi10_is_baco_supported(struct smu_context *smu) 1908 { 1909 struct amdgpu_device *adev = smu->adev; 1910 uint32_t val; 1911 1912 if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu))) 1913 return false; 1914 1915 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); 1916 return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false; 1917 } 1918 1919 static int navi10_set_default_od_settings(struct smu_context *smu) 1920 { 1921 OverDriveTable_t *od_table = 1922 (OverDriveTable_t *)smu->smu_table.overdrive_table; 1923 OverDriveTable_t *boot_od_table = 1924 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table; 1925 int ret = 0; 1926 1927 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, false); 1928 if (ret) { 1929 dev_err(smu->adev->dev, "Failed to get overdrive table!\n"); 1930 return ret; 1931 } 1932 1933 if (!od_table->GfxclkVolt1) { 1934 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu, 1935 &od_table->GfxclkVolt1, 1936 od_table->GfxclkFreq1); 1937 if (ret) 1938 return ret; 1939 } 1940 1941 if (!od_table->GfxclkVolt2) { 1942 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu, 1943 &od_table->GfxclkVolt2, 1944 od_table->GfxclkFreq2); 1945 if (ret) 1946 return ret; 1947 } 1948 1949 if (!od_table->GfxclkVolt3) { 1950 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu, 1951 &od_table->GfxclkVolt3, 1952 od_table->GfxclkFreq3); 1953 if (ret) 1954 return ret; 1955 } 1956 1957 memcpy(boot_od_table, od_table, sizeof(OverDriveTable_t)); 1958 1959 navi10_dump_od_table(smu, od_table); 1960 1961 return 0; 1962 } 1963 1964 static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) { 1965 int i; 1966 int ret = 0; 1967 struct smu_table_context *table_context = &smu->smu_table; 1968 OverDriveTable_t *od_table; 1969 struct smu_11_0_overdrive_table *od_settings; 1970 enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting; 1971 uint16_t *freq_ptr, *voltage_ptr; 1972 od_table = (OverDriveTable_t *)table_context->overdrive_table; 1973 1974 if (!smu->od_enabled) { 1975 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n"); 1976 return -EINVAL; 1977 } 1978 1979 if (!smu->od_settings) { 1980 dev_err(smu->adev->dev, "OD board limits are not set!\n"); 1981 return -ENOENT; 1982 } 1983 1984 od_settings = smu->od_settings; 1985 1986 switch (type) { 1987 case PP_OD_EDIT_SCLK_VDDC_TABLE: 1988 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) { 1989 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n"); 1990 return -ENOTSUPP; 1991 } 1992 if (!table_context->overdrive_table) { 1993 dev_err(smu->adev->dev, "Overdrive is not initialized\n"); 1994 return -EINVAL; 1995 } 1996 for (i = 0; i < size; i += 2) { 1997 if (i + 2 > size) { 1998 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size); 1999 return -EINVAL; 2000 } 2001 switch (input[i]) { 2002 case 0: 2003 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN; 2004 freq_ptr = &od_table->GfxclkFmin; 2005 if (input[i + 1] > od_table->GfxclkFmax) { 2006 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n", 2007 input[i + 1], 2008 od_table->GfxclkFmin); 2009 return -EINVAL; 2010 } 2011 break; 2012 case 1: 2013 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX; 2014 freq_ptr = &od_table->GfxclkFmax; 2015 if (input[i + 1] < od_table->GfxclkFmin) { 2016 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n", 2017 input[i + 1], 2018 od_table->GfxclkFmax); 2019 return -EINVAL; 2020 } 2021 break; 2022 default: 2023 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]); 2024 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n"); 2025 return -EINVAL; 2026 } 2027 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[i + 1]); 2028 if (ret) 2029 return ret; 2030 *freq_ptr = input[i + 1]; 2031 } 2032 break; 2033 case PP_OD_EDIT_MCLK_VDDC_TABLE: 2034 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) { 2035 dev_warn(smu->adev->dev, "UCLK_MAX not supported!\n"); 2036 return -ENOTSUPP; 2037 } 2038 if (size < 2) { 2039 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size); 2040 return -EINVAL; 2041 } 2042 if (input[0] != 1) { 2043 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]); 2044 dev_info(smu->adev->dev, "Supported indices: [1:max]\n"); 2045 return -EINVAL; 2046 } 2047 ret = navi10_od_setting_check_range(smu, od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]); 2048 if (ret) 2049 return ret; 2050 od_table->UclkFmax = input[1]; 2051 break; 2052 case PP_OD_RESTORE_DEFAULT_TABLE: 2053 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) { 2054 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n"); 2055 return -EINVAL; 2056 } 2057 memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t)); 2058 break; 2059 case PP_OD_COMMIT_DPM_TABLE: 2060 navi10_dump_od_table(smu, od_table); 2061 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true); 2062 if (ret) { 2063 dev_err(smu->adev->dev, "Failed to import overdrive table!\n"); 2064 return ret; 2065 } 2066 break; 2067 case PP_OD_EDIT_VDDC_CURVE: 2068 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) { 2069 dev_warn(smu->adev->dev, "GFXCLK_CURVE not supported!\n"); 2070 return -ENOTSUPP; 2071 } 2072 if (size < 3) { 2073 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size); 2074 return -EINVAL; 2075 } 2076 if (!od_table) { 2077 dev_info(smu->adev->dev, "Overdrive is not initialized\n"); 2078 return -EINVAL; 2079 } 2080 2081 switch (input[0]) { 2082 case 0: 2083 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1; 2084 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1; 2085 freq_ptr = &od_table->GfxclkFreq1; 2086 voltage_ptr = &od_table->GfxclkVolt1; 2087 break; 2088 case 1: 2089 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2; 2090 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2; 2091 freq_ptr = &od_table->GfxclkFreq2; 2092 voltage_ptr = &od_table->GfxclkVolt2; 2093 break; 2094 case 2: 2095 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3; 2096 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3; 2097 freq_ptr = &od_table->GfxclkFreq3; 2098 voltage_ptr = &od_table->GfxclkVolt3; 2099 break; 2100 default: 2101 dev_info(smu->adev->dev, "Invalid VDDC_CURVE index: %ld\n", input[0]); 2102 dev_info(smu->adev->dev, "Supported indices: [0, 1, 2]\n"); 2103 return -EINVAL; 2104 } 2105 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[1]); 2106 if (ret) 2107 return ret; 2108 // Allow setting zero to disable the OverDrive VDDC curve 2109 if (input[2] != 0) { 2110 ret = navi10_od_setting_check_range(smu, od_settings, voltage_setting, input[2]); 2111 if (ret) 2112 return ret; 2113 *freq_ptr = input[1]; 2114 *voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE; 2115 dev_dbg(smu->adev->dev, "OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr); 2116 } else { 2117 // If setting 0, disable all voltage curve settings 2118 od_table->GfxclkVolt1 = 0; 2119 od_table->GfxclkVolt2 = 0; 2120 od_table->GfxclkVolt3 = 0; 2121 } 2122 navi10_dump_od_table(smu, od_table); 2123 break; 2124 default: 2125 return -ENOSYS; 2126 } 2127 return ret; 2128 } 2129 2130 static int navi10_run_btc(struct smu_context *smu) 2131 { 2132 int ret = 0; 2133 2134 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunBtc, NULL); 2135 if (ret) 2136 dev_err(smu->adev->dev, "RunBtc failed!\n"); 2137 2138 return ret; 2139 } 2140 2141 static bool navi10_need_umc_cdr_workaround(struct smu_context *smu) 2142 { 2143 struct amdgpu_device *adev = smu->adev; 2144 2145 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 2146 return false; 2147 2148 if (adev->asic_type == CHIP_NAVI10 || 2149 adev->asic_type == CHIP_NAVI14) 2150 return true; 2151 2152 return false; 2153 } 2154 2155 static int navi10_umc_hybrid_cdr_workaround(struct smu_context *smu) 2156 { 2157 uint32_t uclk_count, uclk_min, uclk_max; 2158 int ret = 0; 2159 2160 /* This workaround can be applied only with uclk dpm enabled */ 2161 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 2162 return 0; 2163 2164 ret = smu_v11_0_get_dpm_level_count(smu, SMU_UCLK, &uclk_count); 2165 if (ret) 2166 return ret; 2167 2168 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)(uclk_count - 1), &uclk_max); 2169 if (ret) 2170 return ret; 2171 2172 /* 2173 * The NAVI10_UMC_HYBRID_CDR_WORKAROUND_UCLK_THRESHOLD is 750Mhz. 2174 * This workaround is needed only when the max uclk frequency 2175 * not greater than that. 2176 */ 2177 if (uclk_max > 0x2EE) 2178 return 0; 2179 2180 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)0, &uclk_min); 2181 if (ret) 2182 return ret; 2183 2184 /* Force UCLK out of the highest DPM */ 2185 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_min); 2186 if (ret) 2187 return ret; 2188 2189 /* Revert the UCLK Hardmax */ 2190 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_max); 2191 if (ret) 2192 return ret; 2193 2194 /* 2195 * In this case, SMU already disabled dummy pstate during enablement 2196 * of UCLK DPM, we have to re-enabled it. 2197 */ 2198 return smu_cmn_send_smc_msg(smu, SMU_MSG_DAL_ENABLE_DUMMY_PSTATE_CHANGE, NULL); 2199 } 2200 2201 static int navi10_set_dummy_pstates_table_location(struct smu_context *smu) 2202 { 2203 struct smu_table_context *smu_table = &smu->smu_table; 2204 struct smu_table *dummy_read_table = 2205 &smu_table->dummy_read_1_table; 2206 char *dummy_table = dummy_read_table->cpu_addr; 2207 int ret = 0; 2208 uint32_t i; 2209 2210 for (i = 0; i < 0x40000; i += 0x1000 * 2) { 2211 memcpy(dummy_table, &NoDbiPrbs7[0], 0x1000); 2212 dummy_table += 0x1000; 2213 memcpy(dummy_table, &DbiPrbs7[0], 0x1000); 2214 dummy_table += 0x1000; 2215 } 2216 2217 amdgpu_asic_flush_hdp(smu->adev, NULL); 2218 2219 ret = smu_cmn_send_smc_msg_with_param(smu, 2220 SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH, 2221 upper_32_bits(dummy_read_table->mc_address), 2222 NULL); 2223 if (ret) 2224 return ret; 2225 2226 return smu_cmn_send_smc_msg_with_param(smu, 2227 SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW, 2228 lower_32_bits(dummy_read_table->mc_address), 2229 NULL); 2230 } 2231 2232 static int navi10_run_umc_cdr_workaround(struct smu_context *smu) 2233 { 2234 struct amdgpu_device *adev = smu->adev; 2235 uint8_t umc_fw_greater_than_v136 = false; 2236 uint8_t umc_fw_disable_cdr = false; 2237 uint32_t pmfw_version; 2238 uint32_t param; 2239 int ret = 0; 2240 2241 if (!navi10_need_umc_cdr_workaround(smu)) 2242 return 0; 2243 2244 ret = smu_cmn_get_smc_version(smu, NULL, &pmfw_version); 2245 if (ret) { 2246 dev_err(adev->dev, "Failed to get smu version!\n"); 2247 return ret; 2248 } 2249 2250 /* 2251 * The messages below are only supported by Navi10 42.53.0 and later 2252 * PMFWs and Navi14 53.29.0 and later PMFWs. 2253 * - PPSMC_MSG_SetDriverDummyTableDramAddrHigh 2254 * - PPSMC_MSG_SetDriverDummyTableDramAddrLow 2255 * - PPSMC_MSG_GetUMCFWWA 2256 */ 2257 if (((adev->asic_type == CHIP_NAVI10) && (pmfw_version >= 0x2a3500)) || 2258 ((adev->asic_type == CHIP_NAVI14) && (pmfw_version >= 0x351D00))) { 2259 ret = smu_cmn_send_smc_msg_with_param(smu, 2260 SMU_MSG_GET_UMC_FW_WA, 2261 0, 2262 ¶m); 2263 if (ret) 2264 return ret; 2265 2266 /* First bit indicates if the UMC f/w is above v137 */ 2267 umc_fw_greater_than_v136 = param & 0x1; 2268 2269 /* Second bit indicates if hybrid-cdr is disabled */ 2270 umc_fw_disable_cdr = param & 0x2; 2271 2272 /* w/a only allowed if UMC f/w is <= 136 */ 2273 if (umc_fw_greater_than_v136) 2274 return 0; 2275 2276 if (umc_fw_disable_cdr) { 2277 if (adev->asic_type == CHIP_NAVI10) 2278 return navi10_umc_hybrid_cdr_workaround(smu); 2279 } else { 2280 return navi10_set_dummy_pstates_table_location(smu); 2281 } 2282 } else { 2283 if (adev->asic_type == CHIP_NAVI10) 2284 return navi10_umc_hybrid_cdr_workaround(smu); 2285 } 2286 2287 return 0; 2288 } 2289 2290 static ssize_t navi10_get_gpu_metrics(struct smu_context *smu, 2291 void **table) 2292 { 2293 struct smu_table_context *smu_table = &smu->smu_table; 2294 struct gpu_metrics_v1_0 *gpu_metrics = 2295 (struct gpu_metrics_v1_0 *)smu_table->gpu_metrics_table; 2296 struct amdgpu_device *adev = smu->adev; 2297 SmuMetrics_NV12_t nv12_metrics = { 0 }; 2298 SmuMetrics_t metrics; 2299 int ret = 0; 2300 2301 mutex_lock(&smu->metrics_lock); 2302 2303 ret = smu_cmn_get_metrics_table_locked(smu, 2304 NULL, 2305 true); 2306 if (ret) { 2307 mutex_unlock(&smu->metrics_lock); 2308 return ret; 2309 } 2310 2311 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_t)); 2312 if (adev->asic_type == CHIP_NAVI12) 2313 memcpy(&nv12_metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_t)); 2314 2315 mutex_unlock(&smu->metrics_lock); 2316 2317 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 0); 2318 2319 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 2320 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 2321 gpu_metrics->temperature_mem = metrics.TemperatureMem; 2322 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 2323 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 2324 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 2325 2326 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 2327 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 2328 2329 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 2330 2331 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 2332 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 2333 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 2334 2335 if (adev->asic_type == CHIP_NAVI12) { 2336 gpu_metrics->energy_accumulator = nv12_metrics.EnergyAccumulator; 2337 gpu_metrics->average_vclk0_frequency = nv12_metrics.AverageVclkFrequency; 2338 gpu_metrics->average_dclk0_frequency = nv12_metrics.AverageDclkFrequency; 2339 gpu_metrics->average_mm_activity = nv12_metrics.VcnActivityPercentage; 2340 } 2341 2342 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 2343 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 2344 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 2345 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 2346 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 2347 2348 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 2349 2350 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 2351 2352 gpu_metrics->pcie_link_width = 2353 smu_v11_0_get_current_pcie_link_width(smu); 2354 gpu_metrics->pcie_link_speed = 2355 smu_v11_0_get_current_pcie_link_speed(smu); 2356 2357 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 2358 2359 *table = (void *)gpu_metrics; 2360 2361 return sizeof(struct gpu_metrics_v1_0); 2362 } 2363 2364 static int navi10_enable_mgpu_fan_boost(struct smu_context *smu) 2365 { 2366 struct amdgpu_device *adev = smu->adev; 2367 uint32_t param = 0; 2368 2369 /* Navi12 does not support this */ 2370 if (adev->asic_type == CHIP_NAVI12) 2371 return 0; 2372 2373 /* Workaround for WS SKU */ 2374 if (adev->pdev->device == 0x7312 && 2375 adev->pdev->revision == 0) 2376 param = 0xD188; 2377 2378 return smu_cmn_send_smc_msg_with_param(smu, 2379 SMU_MSG_SetMGpuFanBoostLimitRpm, 2380 param, 2381 NULL); 2382 } 2383 2384 static int navi10_post_smu_init(struct smu_context *smu) 2385 { 2386 struct amdgpu_device *adev = smu->adev; 2387 int ret = 0; 2388 2389 if (amdgpu_sriov_vf(adev)) 2390 return 0; 2391 2392 ret = navi10_run_umc_cdr_workaround(smu); 2393 if (ret) { 2394 dev_err(adev->dev, "Failed to apply umc cdr workaround!\n"); 2395 return ret; 2396 } 2397 2398 if (!smu->dc_controlled_by_gpio) { 2399 /* 2400 * For Navi1X, manually switch it to AC mode as PMFW 2401 * may boot it with DC mode. 2402 */ 2403 ret = smu_v11_0_set_power_source(smu, 2404 adev->pm.ac_power ? 2405 SMU_POWER_SOURCE_AC : 2406 SMU_POWER_SOURCE_DC); 2407 if (ret) { 2408 dev_err(adev->dev, "Failed to switch to %s mode!\n", 2409 adev->pm.ac_power ? "AC" : "DC"); 2410 return ret; 2411 } 2412 } 2413 2414 return ret; 2415 } 2416 2417 static const struct pptable_funcs navi10_ppt_funcs = { 2418 .get_allowed_feature_mask = navi10_get_allowed_feature_mask, 2419 .set_default_dpm_table = navi10_set_default_dpm_table, 2420 .dpm_set_vcn_enable = navi10_dpm_set_vcn_enable, 2421 .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable, 2422 .print_clk_levels = navi10_print_clk_levels, 2423 .force_clk_levels = navi10_force_clk_levels, 2424 .populate_umd_state_clk = navi10_populate_umd_state_clk, 2425 .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency, 2426 .pre_display_config_changed = navi10_pre_display_config_changed, 2427 .display_config_changed = navi10_display_config_changed, 2428 .notify_smc_display_config = navi10_notify_smc_display_config, 2429 .is_dpm_running = navi10_is_dpm_running, 2430 .get_fan_speed_percent = navi10_get_fan_speed_percent, 2431 .get_power_profile_mode = navi10_get_power_profile_mode, 2432 .set_power_profile_mode = navi10_set_power_profile_mode, 2433 .set_watermarks_table = navi10_set_watermarks_table, 2434 .read_sensor = navi10_read_sensor, 2435 .get_uclk_dpm_states = navi10_get_uclk_dpm_states, 2436 .set_performance_level = smu_v11_0_set_performance_level, 2437 .get_thermal_temperature_range = navi10_get_thermal_temperature_range, 2438 .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch, 2439 .get_power_limit = navi10_get_power_limit, 2440 .update_pcie_parameters = navi10_update_pcie_parameters, 2441 .init_microcode = smu_v11_0_init_microcode, 2442 .load_microcode = smu_v11_0_load_microcode, 2443 .fini_microcode = smu_v11_0_fini_microcode, 2444 .init_smc_tables = navi10_init_smc_tables, 2445 .fini_smc_tables = smu_v11_0_fini_smc_tables, 2446 .init_power = smu_v11_0_init_power, 2447 .fini_power = smu_v11_0_fini_power, 2448 .check_fw_status = smu_v11_0_check_fw_status, 2449 .setup_pptable = navi10_setup_pptable, 2450 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, 2451 .check_fw_version = smu_v11_0_check_fw_version, 2452 .write_pptable = smu_cmn_write_pptable, 2453 .set_driver_table_location = smu_v11_0_set_driver_table_location, 2454 .set_tool_table_location = smu_v11_0_set_tool_table_location, 2455 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 2456 .system_features_control = smu_v11_0_system_features_control, 2457 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 2458 .send_smc_msg = smu_cmn_send_smc_msg, 2459 .init_display_count = smu_v11_0_init_display_count, 2460 .set_allowed_mask = smu_v11_0_set_allowed_mask, 2461 .get_enabled_mask = smu_cmn_get_enabled_mask, 2462 .feature_is_enabled = smu_cmn_feature_is_enabled, 2463 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 2464 .notify_display_change = smu_v11_0_notify_display_change, 2465 .set_power_limit = smu_v11_0_set_power_limit, 2466 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks, 2467 .enable_thermal_alert = smu_v11_0_enable_thermal_alert, 2468 .disable_thermal_alert = smu_v11_0_disable_thermal_alert, 2469 .set_min_dcef_deep_sleep = smu_v11_0_set_min_deep_sleep_dcefclk, 2470 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request, 2471 .get_fan_control_mode = smu_v11_0_get_fan_control_mode, 2472 .set_fan_control_mode = smu_v11_0_set_fan_control_mode, 2473 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent, 2474 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate, 2475 .gfx_off_control = smu_v11_0_gfx_off_control, 2476 .register_irq_handler = smu_v11_0_register_irq_handler, 2477 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme, 2478 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc, 2479 .baco_is_support= navi10_is_baco_supported, 2480 .baco_get_state = smu_v11_0_baco_get_state, 2481 .baco_set_state = smu_v11_0_baco_set_state, 2482 .baco_enter = smu_v11_0_baco_enter, 2483 .baco_exit = smu_v11_0_baco_exit, 2484 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq, 2485 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, 2486 .set_default_od_settings = navi10_set_default_od_settings, 2487 .od_edit_dpm_table = navi10_od_edit_dpm_table, 2488 .run_btc = navi10_run_btc, 2489 .set_power_source = smu_v11_0_set_power_source, 2490 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 2491 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 2492 .get_gpu_metrics = navi10_get_gpu_metrics, 2493 .enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost, 2494 .gfx_ulv_control = smu_v11_0_gfx_ulv_control, 2495 .deep_sleep_control = smu_v11_0_deep_sleep_control, 2496 .get_fan_parameters = navi10_get_fan_parameters, 2497 .post_init = navi10_post_smu_init, 2498 .interrupt_work = smu_v11_0_interrupt_work, 2499 }; 2500 2501 void navi10_set_ppt_funcs(struct smu_context *smu) 2502 { 2503 smu->ppt_funcs = &navi10_ppt_funcs; 2504 smu->message_map = navi10_message_map; 2505 smu->clock_map = navi10_clk_map; 2506 smu->feature_map = navi10_feature_mask_map; 2507 smu->table_map = navi10_table_map; 2508 smu->pwr_src_map = navi10_pwr_src_map; 2509 smu->workload_map = navi10_workload_map; 2510 } 2511