1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __SMU_V13_0_H__ 24 #define __SMU_V13_0_H__ 25 26 #include "amdgpu_smu.h" 27 28 #define SMU13_DRIVER_IF_VERSION_INV 0xFFFFFFFF 29 #define SMU13_DRIVER_IF_VERSION_YELLOW_CARP 0x04 30 #define SMU13_DRIVER_IF_VERSION_ALDE 0x08 31 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_0 0x37 32 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_4 0x08 33 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_5 0x04 34 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_10 0x32 35 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x37 36 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_10 0x1D 37 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_6 0x0 38 39 #define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms 40 41 /* MP Apertures */ 42 #define MP0_Public 0x03800000 43 #define MP0_SRAM 0x03900000 44 #define MP1_Public 0x03b00000 45 #define MP1_SRAM 0x03c00004 46 47 /* address block */ 48 #define smnMP1_FIRMWARE_FLAGS 0x3010024 49 #define smnMP1_V13_0_4_FIRMWARE_FLAGS 0x3010028 50 #define smnMP0_FW_INTF 0x30101c0 51 #define smnMP1_PUB_CTRL 0x3010b14 52 53 #define TEMP_RANGE_MIN (0) 54 #define TEMP_RANGE_MAX (80 * 1000) 55 56 #define SMU13_TOOL_SIZE 0x19000 57 58 #define MAX_DPM_LEVELS 16 59 #define MAX_PCIE_CONF 3 60 61 #define CTF_OFFSET_EDGE 5 62 #define CTF_OFFSET_HOTSPOT 5 63 #define CTF_OFFSET_MEM 5 64 65 extern const int pmfw_decoded_link_speed[5]; 66 extern const int pmfw_decoded_link_width[7]; 67 68 #define DECODE_GEN_SPEED(gen_speed_idx) (pmfw_decoded_link_speed[gen_speed_idx]) 69 #define DECODE_LANE_WIDTH(lane_width_idx) (pmfw_decoded_link_width[lane_width_idx]) 70 71 struct smu_13_0_max_sustainable_clocks { 72 uint32_t display_clock; 73 uint32_t phy_clock; 74 uint32_t pixel_clock; 75 uint32_t uclock; 76 uint32_t dcef_clock; 77 uint32_t soc_clock; 78 }; 79 80 struct smu_13_0_dpm_clk_level { 81 bool enabled; 82 uint32_t value; 83 }; 84 85 struct smu_13_0_dpm_table { 86 uint32_t min; /* MHz */ 87 uint32_t max; /* MHz */ 88 uint32_t count; 89 bool is_fine_grained; 90 struct smu_13_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS]; 91 }; 92 93 struct smu_13_0_pcie_table { 94 uint8_t pcie_gen[MAX_PCIE_CONF]; 95 uint8_t pcie_lane[MAX_PCIE_CONF]; 96 uint16_t clk_freq[MAX_PCIE_CONF]; 97 uint32_t num_of_link_levels; 98 }; 99 100 struct smu_13_0_dpm_tables { 101 struct smu_13_0_dpm_table soc_table; 102 struct smu_13_0_dpm_table gfx_table; 103 struct smu_13_0_dpm_table uclk_table; 104 struct smu_13_0_dpm_table eclk_table; 105 struct smu_13_0_dpm_table vclk_table; 106 struct smu_13_0_dpm_table dclk_table; 107 struct smu_13_0_dpm_table dcef_table; 108 struct smu_13_0_dpm_table pixel_table; 109 struct smu_13_0_dpm_table display_table; 110 struct smu_13_0_dpm_table phy_table; 111 struct smu_13_0_dpm_table fclk_table; 112 struct smu_13_0_pcie_table pcie_table; 113 }; 114 115 struct smu_13_0_dpm_context { 116 struct smu_13_0_dpm_tables dpm_tables; 117 uint32_t workload_policy_mask; 118 uint32_t dcef_min_ds_clk; 119 }; 120 121 enum smu_13_0_power_state { 122 SMU_13_0_POWER_STATE__D0 = 0, 123 SMU_13_0_POWER_STATE__D1, 124 SMU_13_0_POWER_STATE__D3, /* Sleep*/ 125 SMU_13_0_POWER_STATE__D4, /* Hibernate*/ 126 SMU_13_0_POWER_STATE__D5, /* Power off*/ 127 }; 128 129 struct smu_13_0_power_context { 130 uint32_t power_source; 131 uint8_t in_power_limit_boost_mode; 132 enum smu_13_0_power_state power_state; 133 }; 134 135 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) 136 137 int smu_v13_0_init_microcode(struct smu_context *smu); 138 139 void smu_v13_0_fini_microcode(struct smu_context *smu); 140 141 int smu_v13_0_load_microcode(struct smu_context *smu); 142 143 int smu_v13_0_init_smc_tables(struct smu_context *smu); 144 145 int smu_v13_0_fini_smc_tables(struct smu_context *smu); 146 147 int smu_v13_0_init_power(struct smu_context *smu); 148 149 int smu_v13_0_fini_power(struct smu_context *smu); 150 151 int smu_v13_0_check_fw_status(struct smu_context *smu); 152 153 int smu_v13_0_setup_pptable(struct smu_context *smu); 154 155 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu); 156 157 int smu_v13_0_check_fw_version(struct smu_context *smu); 158 159 int smu_v13_0_set_driver_table_location(struct smu_context *smu); 160 161 int smu_v13_0_set_tool_table_location(struct smu_context *smu); 162 163 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu); 164 165 int smu_v13_0_system_features_control(struct smu_context *smu, 166 bool en); 167 168 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count); 169 170 int smu_v13_0_set_allowed_mask(struct smu_context *smu); 171 172 int smu_v13_0_notify_display_change(struct smu_context *smu); 173 174 int smu_v13_0_get_current_power_limit(struct smu_context *smu, 175 uint32_t *power_limit); 176 177 int smu_v13_0_set_power_limit(struct smu_context *smu, 178 enum smu_ppt_limit_type limit_type, 179 uint32_t limit); 180 181 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu); 182 183 int smu_v13_0_enable_thermal_alert(struct smu_context *smu); 184 185 int smu_v13_0_disable_thermal_alert(struct smu_context *smu); 186 187 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value); 188 189 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk); 190 191 int 192 smu_v13_0_display_clock_voltage_request(struct smu_context *smu, 193 struct pp_display_clock_request 194 *clock_req); 195 196 uint32_t 197 smu_v13_0_get_fan_control_mode(struct smu_context *smu); 198 199 int 200 smu_v13_0_set_fan_control_mode(struct smu_context *smu, 201 uint32_t mode); 202 203 int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu, 204 uint32_t speed); 205 206 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu, 207 uint32_t speed); 208 209 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu, 210 uint32_t pstate); 211 212 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable); 213 214 int smu_v13_0_register_irq_handler(struct smu_context *smu); 215 216 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu); 217 218 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu, 219 struct pp_smu_nv_clock_table *max_clocks); 220 221 int smu_v13_0_baco_set_armd3_sequence(struct smu_context *smu, 222 enum smu_baco_seq baco_seq); 223 224 bool smu_v13_0_baco_is_support(struct smu_context *smu); 225 226 enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu); 227 228 int smu_v13_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state); 229 230 int smu_v13_0_baco_enter(struct smu_context *smu); 231 int smu_v13_0_baco_exit(struct smu_context *smu); 232 233 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 234 uint32_t *min, uint32_t *max); 235 236 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, 237 uint32_t min, uint32_t max); 238 239 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu, 240 enum smu_clk_type clk_type, 241 uint32_t min, 242 uint32_t max); 243 244 int smu_v13_0_set_performance_level(struct smu_context *smu, 245 enum amd_dpm_forced_level level); 246 247 int smu_v13_0_set_power_source(struct smu_context *smu, 248 enum smu_power_src_type power_src); 249 250 int smu_v13_0_set_single_dpm_table(struct smu_context *smu, 251 enum smu_clk_type clk_type, 252 struct smu_13_0_dpm_table *single_dpm_table); 253 254 int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu, 255 enum smu_clk_type clk_type, uint16_t level, 256 uint32_t *value); 257 258 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu); 259 260 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu); 261 262 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu); 263 264 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu); 265 266 int smu_v13_0_gfx_ulv_control(struct smu_context *smu, 267 bool enablement); 268 269 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event, 270 uint64_t event_arg); 271 272 int smu_v13_0_set_vcn_enable(struct smu_context *smu, 273 bool enable); 274 275 int smu_v13_0_set_jpeg_enable(struct smu_context *smu, 276 bool enable); 277 278 int smu_v13_0_init_pptable_microcode(struct smu_context *smu); 279 280 int smu_v13_0_run_btc(struct smu_context *smu); 281 282 int smu_v13_0_gpo_control(struct smu_context *smu, 283 bool enablement); 284 285 int smu_v13_0_deep_sleep_control(struct smu_context *smu, 286 bool enablement); 287 288 int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu); 289 290 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu, 291 enum PP_OD_DPM_TABLE_COMMAND type, 292 long input[], 293 uint32_t size); 294 295 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu); 296 297 void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu); 298 299 int smu_v13_0_mode1_reset(struct smu_context *smu); 300 301 int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu, 302 void **table, 303 uint32_t *size, 304 uint32_t pptable_id); 305 306 #endif 307 #endif 308