1 /*
2  * Copyright 2020 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #ifndef __SMU_V13_0_H__
24 #define __SMU_V13_0_H__
25 
26 #include "amdgpu_smu.h"
27 
28 #define SMU13_DRIVER_IF_VERSION_INV 0xFFFFFFFF
29 #define SMU13_DRIVER_IF_VERSION_YELLOW_CARP 0x04
30 #define SMU13_DRIVER_IF_VERSION_ALDE 0x08
31 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_0 0x34
32 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_4 0x07
33 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_5 0x04
34 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_10 0x32
35 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x35
36 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_10 0x1D
37 
38 #define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500  //500ms
39 
40 /* MP Apertures */
41 #define MP0_Public			0x03800000
42 #define MP0_SRAM			0x03900000
43 #define MP1_Public			0x03b00000
44 #define MP1_SRAM			0x03c00004
45 
46 /* address block */
47 #define smnMP1_FIRMWARE_FLAGS		0x3010024
48 #define smnMP1_V13_0_4_FIRMWARE_FLAGS	0x3010028
49 #define smnMP0_FW_INTF			0x30101c0
50 #define smnMP1_PUB_CTRL			0x3010b14
51 
52 #define TEMP_RANGE_MIN			(0)
53 #define TEMP_RANGE_MAX			(80 * 1000)
54 
55 #define SMU13_TOOL_SIZE			0x19000
56 
57 #define MAX_DPM_LEVELS 16
58 #define MAX_PCIE_CONF 3
59 
60 #define CTF_OFFSET_EDGE			5
61 #define CTF_OFFSET_HOTSPOT		5
62 #define CTF_OFFSET_MEM			5
63 
64 struct smu_13_0_max_sustainable_clocks {
65 	uint32_t display_clock;
66 	uint32_t phy_clock;
67 	uint32_t pixel_clock;
68 	uint32_t uclock;
69 	uint32_t dcef_clock;
70 	uint32_t soc_clock;
71 };
72 
73 struct smu_13_0_dpm_clk_level {
74 	bool				enabled;
75 	uint32_t			value;
76 };
77 
78 struct smu_13_0_dpm_table {
79 	uint32_t			min;        /* MHz */
80 	uint32_t			max;        /* MHz */
81 	uint32_t			count;
82 	bool				is_fine_grained;
83 	struct smu_13_0_dpm_clk_level	dpm_levels[MAX_DPM_LEVELS];
84 };
85 
86 struct smu_13_0_pcie_table {
87 	uint8_t  pcie_gen[MAX_PCIE_CONF];
88 	uint8_t  pcie_lane[MAX_PCIE_CONF];
89 	uint16_t clk_freq[MAX_PCIE_CONF];
90 	uint32_t num_of_link_levels;
91 };
92 
93 struct smu_13_0_dpm_tables {
94 	struct smu_13_0_dpm_table        soc_table;
95 	struct smu_13_0_dpm_table        gfx_table;
96 	struct smu_13_0_dpm_table        uclk_table;
97 	struct smu_13_0_dpm_table        eclk_table;
98 	struct smu_13_0_dpm_table        vclk_table;
99 	struct smu_13_0_dpm_table        dclk_table;
100 	struct smu_13_0_dpm_table        dcef_table;
101 	struct smu_13_0_dpm_table        pixel_table;
102 	struct smu_13_0_dpm_table        display_table;
103 	struct smu_13_0_dpm_table        phy_table;
104 	struct smu_13_0_dpm_table        fclk_table;
105 	struct smu_13_0_pcie_table       pcie_table;
106 };
107 
108 struct smu_13_0_dpm_context {
109 	struct smu_13_0_dpm_tables  dpm_tables;
110 	uint32_t                    workload_policy_mask;
111 	uint32_t                    dcef_min_ds_clk;
112 };
113 
114 enum smu_13_0_power_state {
115 	SMU_13_0_POWER_STATE__D0 = 0,
116 	SMU_13_0_POWER_STATE__D1,
117 	SMU_13_0_POWER_STATE__D3, /* Sleep*/
118 	SMU_13_0_POWER_STATE__D4, /* Hibernate*/
119 	SMU_13_0_POWER_STATE__D5, /* Power off*/
120 };
121 
122 struct smu_13_0_power_context {
123 	uint32_t	power_source;
124 	uint8_t		in_power_limit_boost_mode;
125 	enum smu_13_0_power_state power_state;
126 };
127 
128 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
129 
130 int smu_v13_0_init_microcode(struct smu_context *smu);
131 
132 void smu_v13_0_fini_microcode(struct smu_context *smu);
133 
134 int smu_v13_0_load_microcode(struct smu_context *smu);
135 
136 int smu_v13_0_init_smc_tables(struct smu_context *smu);
137 
138 int smu_v13_0_fini_smc_tables(struct smu_context *smu);
139 
140 int smu_v13_0_init_power(struct smu_context *smu);
141 
142 int smu_v13_0_fini_power(struct smu_context *smu);
143 
144 int smu_v13_0_check_fw_status(struct smu_context *smu);
145 
146 int smu_v13_0_setup_pptable(struct smu_context *smu);
147 
148 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu);
149 
150 int smu_v13_0_check_fw_version(struct smu_context *smu);
151 
152 int smu_v13_0_set_driver_table_location(struct smu_context *smu);
153 
154 int smu_v13_0_set_tool_table_location(struct smu_context *smu);
155 
156 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu);
157 
158 int smu_v13_0_system_features_control(struct smu_context *smu,
159 				      bool en);
160 
161 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count);
162 
163 int smu_v13_0_set_allowed_mask(struct smu_context *smu);
164 
165 int smu_v13_0_notify_display_change(struct smu_context *smu);
166 
167 int smu_v13_0_get_current_power_limit(struct smu_context *smu,
168 				      uint32_t *power_limit);
169 
170 int smu_v13_0_set_power_limit(struct smu_context *smu,
171 			      enum smu_ppt_limit_type limit_type,
172 			      uint32_t limit);
173 
174 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu);
175 
176 int smu_v13_0_enable_thermal_alert(struct smu_context *smu);
177 
178 int smu_v13_0_disable_thermal_alert(struct smu_context *smu);
179 
180 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value);
181 
182 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk);
183 
184 int
185 smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
186 					struct pp_display_clock_request
187 					*clock_req);
188 
189 uint32_t
190 smu_v13_0_get_fan_control_mode(struct smu_context *smu);
191 
192 int
193 smu_v13_0_set_fan_control_mode(struct smu_context *smu,
194 			       uint32_t mode);
195 
196 int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu,
197 				uint32_t speed);
198 
199 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
200 				uint32_t speed);
201 
202 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
203 			      uint32_t pstate);
204 
205 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable);
206 
207 int smu_v13_0_register_irq_handler(struct smu_context *smu);
208 
209 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu);
210 
211 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
212 					       struct pp_smu_nv_clock_table *max_clocks);
213 
214 int smu_v13_0_baco_set_armd3_sequence(struct smu_context *smu,
215 				      enum smu_baco_seq baco_seq);
216 
217 bool smu_v13_0_baco_is_support(struct smu_context *smu);
218 
219 enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu);
220 
221 int smu_v13_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);
222 
223 int smu_v13_0_baco_enter(struct smu_context *smu);
224 int smu_v13_0_baco_exit(struct smu_context *smu);
225 
226 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
227 				    uint32_t *min, uint32_t *max);
228 
229 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
230 					  uint32_t min, uint32_t max);
231 
232 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
233 					  enum smu_clk_type clk_type,
234 					  uint32_t min,
235 					  uint32_t max);
236 
237 int smu_v13_0_set_performance_level(struct smu_context *smu,
238 				    enum amd_dpm_forced_level level);
239 
240 int smu_v13_0_set_power_source(struct smu_context *smu,
241 			       enum smu_power_src_type power_src);
242 
243 int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
244 				   enum smu_clk_type clk_type,
245 				   struct smu_13_0_dpm_table *single_dpm_table);
246 
247 int smu_v13_0_get_dpm_level_range(struct smu_context *smu,
248 				  enum smu_clk_type clk_type,
249 				  uint32_t *min_value,
250 				  uint32_t *max_value);
251 
252 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu);
253 
254 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu);
255 
256 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu);
257 
258 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu);
259 
260 int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
261 			      bool enablement);
262 
263 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
264 			     uint64_t event_arg);
265 
266 int smu_v13_0_set_vcn_enable(struct smu_context *smu,
267 			     bool enable);
268 
269 int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
270 			      bool enable);
271 
272 int smu_v13_0_init_pptable_microcode(struct smu_context *smu);
273 
274 int smu_v13_0_run_btc(struct smu_context *smu);
275 
276 int smu_v13_0_gpo_control(struct smu_context *smu,
277 			  bool enablement);
278 
279 int smu_v13_0_deep_sleep_control(struct smu_context *smu,
280 				 bool enablement);
281 
282 int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu);
283 
284 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
285 				enum PP_OD_DPM_TABLE_COMMAND type,
286 				long input[],
287 				uint32_t size);
288 
289 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu);
290 
291 void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu);
292 
293 int smu_v13_0_mode1_reset(struct smu_context *smu);
294 
295 int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu,
296 					void **table,
297 					uint32_t *size,
298 					uint32_t pptable_id);
299 
300 #endif
301 #endif
302