1837d542aSEvan Quan /* 2837d542aSEvan Quan * Copyright 2020 Advanced Micro Devices, Inc. 3837d542aSEvan Quan * 4837d542aSEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5837d542aSEvan Quan * copy of this software and associated documentation files (the "Software"), 6837d542aSEvan Quan * to deal in the Software without restriction, including without limitation 7837d542aSEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8837d542aSEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9837d542aSEvan Quan * Software is furnished to do so, subject to the following conditions: 10837d542aSEvan Quan * 11837d542aSEvan Quan * The above copyright notice and this permission notice shall be included in 12837d542aSEvan Quan * all copies or substantial portions of the Software. 13837d542aSEvan Quan * 14837d542aSEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15837d542aSEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16837d542aSEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17837d542aSEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18837d542aSEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19837d542aSEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20837d542aSEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21837d542aSEvan Quan * 22837d542aSEvan Quan */ 23837d542aSEvan Quan #ifndef __SMU_V13_0_H__ 24837d542aSEvan Quan #define __SMU_V13_0_H__ 25837d542aSEvan Quan 26837d542aSEvan Quan #include "amdgpu_smu.h" 27837d542aSEvan Quan 28837d542aSEvan Quan #define SMU13_DRIVER_IF_VERSION_INV 0xFFFFFFFF 29837d542aSEvan Quan #define SMU13_DRIVER_IF_VERSION_YELLOW_CARP 0x04 30837d542aSEvan Quan #define SMU13_DRIVER_IF_VERSION_ALDE 0x08 31a0219175STim Huang #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_4 0x04 32276c03a0SEvan Quan #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_5 0x04 33*66f54992SEvan Quan #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0 0x29 34113cc31dSChengming Gui #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x28 35837d542aSEvan Quan 36837d542aSEvan Quan #define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms 37837d542aSEvan Quan 38837d542aSEvan Quan /* MP Apertures */ 39837d542aSEvan Quan #define MP0_Public 0x03800000 40837d542aSEvan Quan #define MP0_SRAM 0x03900000 41837d542aSEvan Quan #define MP1_Public 0x03b00000 42837d542aSEvan Quan #define MP1_SRAM 0x03c00004 43837d542aSEvan Quan 44837d542aSEvan Quan /* address block */ 45837d542aSEvan Quan #define smnMP1_FIRMWARE_FLAGS 0x3010024 46837d542aSEvan Quan #define smnMP0_FW_INTF 0x30101c0 47837d542aSEvan Quan #define smnMP1_PUB_CTRL 0x3010b14 48837d542aSEvan Quan 49837d542aSEvan Quan #define TEMP_RANGE_MIN (0) 50837d542aSEvan Quan #define TEMP_RANGE_MAX (80 * 1000) 51837d542aSEvan Quan 52837d542aSEvan Quan #define SMU13_TOOL_SIZE 0x19000 53837d542aSEvan Quan 54837d542aSEvan Quan #define MAX_DPM_LEVELS 16 55276c03a0SEvan Quan #define MAX_PCIE_CONF 3 56837d542aSEvan Quan 57837d542aSEvan Quan #define CTF_OFFSET_EDGE 5 58837d542aSEvan Quan #define CTF_OFFSET_HOTSPOT 5 59837d542aSEvan Quan #define CTF_OFFSET_MEM 5 60837d542aSEvan Quan 61837d542aSEvan Quan struct smu_13_0_max_sustainable_clocks { 62837d542aSEvan Quan uint32_t display_clock; 63837d542aSEvan Quan uint32_t phy_clock; 64837d542aSEvan Quan uint32_t pixel_clock; 65837d542aSEvan Quan uint32_t uclock; 66837d542aSEvan Quan uint32_t dcef_clock; 67837d542aSEvan Quan uint32_t soc_clock; 68837d542aSEvan Quan }; 69837d542aSEvan Quan 70837d542aSEvan Quan struct smu_13_0_dpm_clk_level { 71837d542aSEvan Quan bool enabled; 72837d542aSEvan Quan uint32_t value; 73837d542aSEvan Quan }; 74837d542aSEvan Quan 75837d542aSEvan Quan struct smu_13_0_dpm_table { 76837d542aSEvan Quan uint32_t min; /* MHz */ 77837d542aSEvan Quan uint32_t max; /* MHz */ 78837d542aSEvan Quan uint32_t count; 79276c03a0SEvan Quan bool is_fine_grained; 80837d542aSEvan Quan struct smu_13_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS]; 81837d542aSEvan Quan }; 82837d542aSEvan Quan 83837d542aSEvan Quan struct smu_13_0_pcie_table { 84837d542aSEvan Quan uint8_t pcie_gen[MAX_PCIE_CONF]; 85837d542aSEvan Quan uint8_t pcie_lane[MAX_PCIE_CONF]; 86276c03a0SEvan Quan uint16_t clk_freq[MAX_PCIE_CONF]; 87276c03a0SEvan Quan uint32_t num_of_link_levels; 88837d542aSEvan Quan }; 89837d542aSEvan Quan 90837d542aSEvan Quan struct smu_13_0_dpm_tables { 91837d542aSEvan Quan struct smu_13_0_dpm_table soc_table; 92837d542aSEvan Quan struct smu_13_0_dpm_table gfx_table; 93837d542aSEvan Quan struct smu_13_0_dpm_table uclk_table; 94837d542aSEvan Quan struct smu_13_0_dpm_table eclk_table; 95837d542aSEvan Quan struct smu_13_0_dpm_table vclk_table; 96837d542aSEvan Quan struct smu_13_0_dpm_table dclk_table; 97837d542aSEvan Quan struct smu_13_0_dpm_table dcef_table; 98837d542aSEvan Quan struct smu_13_0_dpm_table pixel_table; 99837d542aSEvan Quan struct smu_13_0_dpm_table display_table; 100837d542aSEvan Quan struct smu_13_0_dpm_table phy_table; 101837d542aSEvan Quan struct smu_13_0_dpm_table fclk_table; 102837d542aSEvan Quan struct smu_13_0_pcie_table pcie_table; 103837d542aSEvan Quan }; 104837d542aSEvan Quan 105837d542aSEvan Quan struct smu_13_0_dpm_context { 106837d542aSEvan Quan struct smu_13_0_dpm_tables dpm_tables; 107837d542aSEvan Quan uint32_t workload_policy_mask; 108837d542aSEvan Quan uint32_t dcef_min_ds_clk; 109837d542aSEvan Quan }; 110837d542aSEvan Quan 111837d542aSEvan Quan enum smu_13_0_power_state { 112837d542aSEvan Quan SMU_13_0_POWER_STATE__D0 = 0, 113837d542aSEvan Quan SMU_13_0_POWER_STATE__D1, 114837d542aSEvan Quan SMU_13_0_POWER_STATE__D3, /* Sleep*/ 115837d542aSEvan Quan SMU_13_0_POWER_STATE__D4, /* Hibernate*/ 116837d542aSEvan Quan SMU_13_0_POWER_STATE__D5, /* Power off*/ 117837d542aSEvan Quan }; 118837d542aSEvan Quan 119837d542aSEvan Quan struct smu_13_0_power_context { 120837d542aSEvan Quan uint32_t power_source; 121837d542aSEvan Quan uint8_t in_power_limit_boost_mode; 122837d542aSEvan Quan enum smu_13_0_power_state power_state; 123837d542aSEvan Quan }; 124837d542aSEvan Quan 125837d542aSEvan Quan enum smu_v13_0_baco_seq { 126837d542aSEvan Quan BACO_SEQ_BACO = 0, 127837d542aSEvan Quan BACO_SEQ_MSR, 128837d542aSEvan Quan BACO_SEQ_BAMACO, 129837d542aSEvan Quan BACO_SEQ_ULPS, 130837d542aSEvan Quan BACO_SEQ_COUNT, 131837d542aSEvan Quan }; 132837d542aSEvan Quan 133837d542aSEvan Quan #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) 134837d542aSEvan Quan 135837d542aSEvan Quan int smu_v13_0_init_microcode(struct smu_context *smu); 136837d542aSEvan Quan 137837d542aSEvan Quan void smu_v13_0_fini_microcode(struct smu_context *smu); 138837d542aSEvan Quan 139837d542aSEvan Quan int smu_v13_0_load_microcode(struct smu_context *smu); 140837d542aSEvan Quan 141837d542aSEvan Quan int smu_v13_0_init_smc_tables(struct smu_context *smu); 142837d542aSEvan Quan 143837d542aSEvan Quan int smu_v13_0_fini_smc_tables(struct smu_context *smu); 144837d542aSEvan Quan 145837d542aSEvan Quan int smu_v13_0_init_power(struct smu_context *smu); 146837d542aSEvan Quan 147837d542aSEvan Quan int smu_v13_0_fini_power(struct smu_context *smu); 148837d542aSEvan Quan 149837d542aSEvan Quan int smu_v13_0_check_fw_status(struct smu_context *smu); 150837d542aSEvan Quan 151837d542aSEvan Quan int smu_v13_0_setup_pptable(struct smu_context *smu); 152837d542aSEvan Quan 153837d542aSEvan Quan int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu); 154837d542aSEvan Quan 155837d542aSEvan Quan int smu_v13_0_check_fw_version(struct smu_context *smu); 156837d542aSEvan Quan 157837d542aSEvan Quan int smu_v13_0_set_driver_table_location(struct smu_context *smu); 158837d542aSEvan Quan 159837d542aSEvan Quan int smu_v13_0_set_tool_table_location(struct smu_context *smu); 160837d542aSEvan Quan 161837d542aSEvan Quan int smu_v13_0_notify_memory_pool_location(struct smu_context *smu); 162837d542aSEvan Quan 163837d542aSEvan Quan int smu_v13_0_system_features_control(struct smu_context *smu, 164837d542aSEvan Quan bool en); 165837d542aSEvan Quan 166837d542aSEvan Quan int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count); 167837d542aSEvan Quan 168837d542aSEvan Quan int smu_v13_0_set_allowed_mask(struct smu_context *smu); 169837d542aSEvan Quan 170837d542aSEvan Quan int smu_v13_0_notify_display_change(struct smu_context *smu); 171837d542aSEvan Quan 172837d542aSEvan Quan int smu_v13_0_get_current_power_limit(struct smu_context *smu, 173837d542aSEvan Quan uint32_t *power_limit); 174837d542aSEvan Quan 175837d542aSEvan Quan int smu_v13_0_set_power_limit(struct smu_context *smu, 176837d542aSEvan Quan enum smu_ppt_limit_type limit_type, 177837d542aSEvan Quan uint32_t limit); 178837d542aSEvan Quan 179837d542aSEvan Quan int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu); 180837d542aSEvan Quan 181837d542aSEvan Quan int smu_v13_0_enable_thermal_alert(struct smu_context *smu); 182837d542aSEvan Quan 183837d542aSEvan Quan int smu_v13_0_disable_thermal_alert(struct smu_context *smu); 184837d542aSEvan Quan 185837d542aSEvan Quan int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value); 186837d542aSEvan Quan 187837d542aSEvan Quan int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk); 188837d542aSEvan Quan 189837d542aSEvan Quan int 190837d542aSEvan Quan smu_v13_0_display_clock_voltage_request(struct smu_context *smu, 191837d542aSEvan Quan struct pp_display_clock_request 192837d542aSEvan Quan *clock_req); 193837d542aSEvan Quan 194837d542aSEvan Quan uint32_t 195837d542aSEvan Quan smu_v13_0_get_fan_control_mode(struct smu_context *smu); 196837d542aSEvan Quan 197837d542aSEvan Quan int 198837d542aSEvan Quan smu_v13_0_set_fan_control_mode(struct smu_context *smu, 199837d542aSEvan Quan uint32_t mode); 200837d542aSEvan Quan 201276c03a0SEvan Quan int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu, 202276c03a0SEvan Quan uint32_t speed); 203837d542aSEvan Quan 204837d542aSEvan Quan int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu, 205837d542aSEvan Quan uint32_t speed); 206837d542aSEvan Quan 207837d542aSEvan Quan int smu_v13_0_set_xgmi_pstate(struct smu_context *smu, 208837d542aSEvan Quan uint32_t pstate); 209837d542aSEvan Quan 210837d542aSEvan Quan int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable); 211837d542aSEvan Quan 212837d542aSEvan Quan int smu_v13_0_register_irq_handler(struct smu_context *smu); 213837d542aSEvan Quan 214837d542aSEvan Quan int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu); 215837d542aSEvan Quan 216837d542aSEvan Quan int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu, 217837d542aSEvan Quan struct pp_smu_nv_clock_table *max_clocks); 218837d542aSEvan Quan 219837d542aSEvan Quan bool smu_v13_0_baco_is_support(struct smu_context *smu); 220837d542aSEvan Quan 221837d542aSEvan Quan enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu); 222837d542aSEvan Quan 223837d542aSEvan Quan int smu_v13_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state); 224837d542aSEvan Quan 225837d542aSEvan Quan int smu_v13_0_baco_enter(struct smu_context *smu); 226837d542aSEvan Quan int smu_v13_0_baco_exit(struct smu_context *smu); 227837d542aSEvan Quan 228837d542aSEvan Quan int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 229837d542aSEvan Quan uint32_t *min, uint32_t *max); 230837d542aSEvan Quan 231837d542aSEvan Quan int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, 232837d542aSEvan Quan uint32_t min, uint32_t max); 233837d542aSEvan Quan 234837d542aSEvan Quan int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu, 235837d542aSEvan Quan enum smu_clk_type clk_type, 236837d542aSEvan Quan uint32_t min, 237837d542aSEvan Quan uint32_t max); 238837d542aSEvan Quan 239837d542aSEvan Quan int smu_v13_0_set_performance_level(struct smu_context *smu, 240837d542aSEvan Quan enum amd_dpm_forced_level level); 241837d542aSEvan Quan 242837d542aSEvan Quan int smu_v13_0_set_power_source(struct smu_context *smu, 243837d542aSEvan Quan enum smu_power_src_type power_src); 244837d542aSEvan Quan 245837d542aSEvan Quan int smu_v13_0_set_single_dpm_table(struct smu_context *smu, 246837d542aSEvan Quan enum smu_clk_type clk_type, 247837d542aSEvan Quan struct smu_13_0_dpm_table *single_dpm_table); 248837d542aSEvan Quan 249837d542aSEvan Quan int smu_v13_0_get_dpm_level_range(struct smu_context *smu, 250837d542aSEvan Quan enum smu_clk_type clk_type, 251837d542aSEvan Quan uint32_t *min_value, 252837d542aSEvan Quan uint32_t *max_value); 253837d542aSEvan Quan 254837d542aSEvan Quan int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu); 255837d542aSEvan Quan 256837d542aSEvan Quan int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu); 257837d542aSEvan Quan 258837d542aSEvan Quan int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu); 259837d542aSEvan Quan 260837d542aSEvan Quan int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu); 261837d542aSEvan Quan 262837d542aSEvan Quan int smu_v13_0_gfx_ulv_control(struct smu_context *smu, 263837d542aSEvan Quan bool enablement); 264837d542aSEvan Quan 265837d542aSEvan Quan int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event, 266837d542aSEvan Quan uint64_t event_arg); 267837d542aSEvan Quan 268276c03a0SEvan Quan int smu_v13_0_set_vcn_enable(struct smu_context *smu, 269276c03a0SEvan Quan bool enable); 270276c03a0SEvan Quan 271276c03a0SEvan Quan int smu_v13_0_set_jpeg_enable(struct smu_context *smu, 272276c03a0SEvan Quan bool enable); 273276c03a0SEvan Quan 274276c03a0SEvan Quan int smu_v13_0_init_pptable_microcode(struct smu_context *smu); 275276c03a0SEvan Quan 27693661c1dSEvan Quan int smu_v13_0_run_btc(struct smu_context *smu); 27793661c1dSEvan Quan 278a5ffbfa0SEvan Quan int smu_v13_0_deep_sleep_control(struct smu_context *smu, 279a5ffbfa0SEvan Quan bool enablement); 280a5ffbfa0SEvan Quan 281914b3087SEvan Quan int smu_v13_0_gfx_ulv_control(struct smu_context *smu, 282914b3087SEvan Quan bool enablement); 283914b3087SEvan Quan 2847c1fa0bfSEvan Quan bool smu_v13_0_baco_is_support(struct smu_context *smu); 2857c1fa0bfSEvan Quan 2867c1fa0bfSEvan Quan enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu); 2877c1fa0bfSEvan Quan 2887c1fa0bfSEvan Quan int smu_v13_0_baco_set_state(struct smu_context *smu, 2897c1fa0bfSEvan Quan enum smu_baco_state state); 2907c1fa0bfSEvan Quan 2917c1fa0bfSEvan Quan int smu_v13_0_baco_enter(struct smu_context *smu); 2927c1fa0bfSEvan Quan 2937c1fa0bfSEvan Quan int smu_v13_0_baco_exit(struct smu_context *smu); 2947c1fa0bfSEvan Quan 295a0219175STim Huang int smu_v13_0_od_edit_dpm_table(struct smu_context *smu, 296a0219175STim Huang enum PP_OD_DPM_TABLE_COMMAND type, 297a0219175STim Huang long input[], 298a0219175STim Huang uint32_t size); 299a0219175STim Huang 300a0219175STim Huang int smu_v13_0_set_default_dpm_tables(struct smu_context *smu); 301837d542aSEvan Quan #endif 302837d542aSEvan Quan #endif 303