1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef SMU_13_0_1_PPSMC_H 25 #define SMU_13_0_1_PPSMC_H 26 27 /** @def PPS_PMFW_IF_VER 28 * PPS (PPLib) to PMFW IF version 1.0 29 */ 30 #define PPS_PMFW_IF_VER "1.0" ///< Major.Minor 31 32 /** @defgroup ResponseCodes PMFW Response Codes: 33 * @{ 34 */ 35 #define PPSMC_Result_OK 0x1 ///< Message Response OK 36 #define PPSMC_Result_Failed 0xFF ///< Message Response Failed 37 #define PPSMC_Result_UnknownCmd 0xFE ///< Message Response Unknown Command 38 #define PPSMC_Result_CmdRejectedPrereq 0xFD ///< Message Response Command Failed Prerequisite 39 #define PPSMC_Result_CmdRejectedBusy 0xFC ///< Message Response Command Rejected due to PMFW is busy. Sender should retry sending this message 40 /** @}*/ 41 42 /** @defgroup definitions Message definitions 43 * @{ 44 */ 45 #define PPSMC_MSG_TestMessage 0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team 46 #define PPSMC_MSG_GetSmuVersion 0x02 ///< Get PMFW version 47 #define PPSMC_MSG_GetDriverIfVersion 0x03 ///< Get PMFW_DRIVER_IF version 48 #define PPSMC_MSG_EnableGfxOff 0x04 ///< Enable GFXOFF 49 #define PPSMC_MSG_DisableGfxOff 0x05 ///< Disable GFXOFF 50 #define PPSMC_MSG_PowerDownVcn 0x06 ///< Power down VCN 51 #define PPSMC_MSG_PowerUpVcn 0x07 ///< Power up VCN; VCN is power gated by default 52 #define PPSMC_MSG_SetHardMinVcn 0x08 ///< For wireless display 53 #define PPSMC_MSG_SetSoftMinGfxclk 0x09 ///< Set SoftMin for GFXCLK, argument is frequency in MHz 54 #define PPSMC_MSG_ActiveProcessNotify 0x0A ///< Deprecated (Not to be used) 55 #define PPSMC_MSG_ForcePowerDownGfx 0x0B ///< Force power down GFX, i.e. enter GFXOFF 56 #define PPSMC_MSG_PrepareMp1ForUnload 0x0C ///< Prepare PMFW for GFX driver unload 57 #define PPSMC_MSG_SetDriverDramAddrHigh 0x0D ///< Set high 32 bits of DRAM address for Driver table transfer 58 #define PPSMC_MSG_SetDriverDramAddrLow 0x0E ///< Set low 32 bits of DRAM address for Driver table transfer 59 #define PPSMC_MSG_TransferTableSmu2Dram 0x0F ///< Transfer driver interface table from PMFW SRAM to DRAM 60 #define PPSMC_MSG_TransferTableDram2Smu 0x10 ///< Transfer driver interface table from DRAM to PMFW SRAM 61 #define PPSMC_MSG_GfxDeviceDriverReset 0x11 ///< Request GFX mode 2 reset 62 #define PPSMC_MSG_GetEnabledSmuFeatures 0x12 ///< Get enabled features in PMFW 63 #define PPSMC_MSG_SetHardMinSocclkByFreq 0x13 ///< Set hard min for SOC CLK 64 #define PPSMC_MSG_SetSoftMinFclk 0x14 ///< Set hard min for FCLK 65 #define PPSMC_MSG_SetSoftMinVcn 0x15 ///< Set soft min for VCN clocks (VCLK and DCLK) 66 #define PPSMC_MSG_SPARE 0x16 ///< Spare 67 #define PPSMC_MSG_GetGfxclkFrequency 0x17 ///< Get GFX clock frequency 68 #define PPSMC_MSG_GetFclkFrequency 0x18 ///< Get FCLK frequency 69 #define PPSMC_MSG_AllowGfxOff 0x19 ///< Inform PMFW of allowing GFXOFF entry 70 #define PPSMC_MSG_DisallowGfxOff 0x1A ///< Inform PMFW of disallowing GFXOFF entry 71 #define PPSMC_MSG_SetSoftMaxGfxClk 0x1B ///< Set soft max for GFX CLK 72 #define PPSMC_MSG_SetHardMinGfxClk 0x1C ///< Set hard min for GFX CLK 73 #define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x1D ///< Set soft max for SOC CLK 74 #define PPSMC_MSG_SetSoftMaxFclkByFreq 0x1E ///< Set soft max for FCLK 75 #define PPSMC_MSG_SetSoftMaxVcn 0x1F ///< Set soft max for VCN clocks (VCLK and DCLK) 76 #define PPSMC_MSG_SetPowerLimitPercentage 0x20 ///< Set power limit percentage 77 #define PPSMC_MSG_PowerDownJpeg 0x21 ///< Power down Jpeg 78 #define PPSMC_MSG_PowerUpJpeg 0x22 ///< Power up Jpeg; VCN is power gated by default 79 #define PPSMC_MSG_SetHardMinFclkByFreq 0x23 ///< Set hard min for FCLK 80 #define PPSMC_MSG_SetSoftMinSocclkByFreq 0x24 ///< Set soft min for SOC CLK 81 #define PPSMC_MSG_AllowZstates 0x25 ///< Inform PMFM of allowing Zstate entry, i.e. no Miracast activity 82 #define PPSMC_MSG_DisallowZstates 0x26 ///< Inform PMFW of disallowing Zstate entry, i.e. there is Miracast activity 83 #define PPSMC_MSG_RequestActiveWgp 0x27 ///< Request GFX active WGP number 84 #define PPSMC_MSG_QueryActiveWgp 0x28 ///< Query the anumber of active WGP number 85 #define PPSMC_Message_Count 0x29 ///< Total number of PPS messages 86 /** @}*/ 87 88 /** @enum Mode_Reset_e 89 * Mode reset type, argument for PPSMC_MSG_GfxDeviceDriverReset 90 */ 91 typedef enum { 92 MODE1_RESET = 1, ///< Mode reset type 1 93 MODE2_RESET = 2 ///< Mode reset type 2 94 } Mode_Reset_e; 95 /** @}*/ 96 97 #endif 98