1 /*
2  * Copyright 2020 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #ifndef __SMU13_DRIVER_IF_YELLOW_CARP_H__
24 #define __SMU13_DRIVER_IF_YELLOW_CARP_H__
25 
26 // *** IMPORTANT ***
27 // SMU TEAM: Always increment the interface version if
28 // any structure is changed in this file
29 #define SMU13_DRIVER_IF_VERSION 4
30 
31 typedef struct {
32   int32_t value;
33   uint32_t numFractionalBits;
34 } FloatInIntFormat_t;
35 
36 typedef enum {
37   DSPCLK_DCFCLK = 0,
38   DSPCLK_DISPCLK,
39   DSPCLK_PIXCLK,
40   DSPCLK_PHYCLK,
41   DSPCLK_COUNT,
42 } DSPCLK_e;
43 
44 typedef struct {
45   uint16_t Freq; // in MHz
46   uint16_t Vid;  // min voltage in SVI3 VID
47 } DisplayClockTable_t;
48 
49 typedef struct {
50   uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
51   uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
52   uint16_t MinMclk;
53   uint16_t MaxMclk;
54 
55   uint8_t  WmSetting;
56   uint8_t  WmType;  // Used for normal pstate change or memory retraining
57   uint8_t  Padding[2];
58 } WatermarkRowGeneric_t;
59 
60 #define NUM_WM_RANGES 4
61 #define WM_PSTATE_CHG 0
62 #define WM_RETRAINING 1
63 
64 typedef enum {
65   WM_SOCCLK = 0,
66   WM_DCFCLK,
67   WM_COUNT,
68 } WM_CLOCK_e;
69 
70 typedef struct {
71   // Watermarks
72   WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
73 
74   uint32_t MmHubPadding[7]; // SMU internal use
75 } Watermarks_t;
76 
77 typedef enum {
78   CUSTOM_DPM_SETTING_GFXCLK,
79   CUSTOM_DPM_SETTING_CCLK,
80   CUSTOM_DPM_SETTING_FCLK_CCX,
81   CUSTOM_DPM_SETTING_FCLK_GFX,
82   CUSTOM_DPM_SETTING_FCLK_STALLS,
83   CUSTOM_DPM_SETTING_LCLK,
84   CUSTOM_DPM_SETTING_COUNT,
85 } CUSTOM_DPM_SETTING_e;
86 
87 typedef struct {
88   uint8_t             ActiveHystLimit;
89   uint8_t             IdleHystLimit;
90   uint8_t             FPS;
91   uint8_t             MinActiveFreqType;
92   FloatInIntFormat_t  MinActiveFreq;
93   FloatInIntFormat_t  PD_Data_limit;
94   FloatInIntFormat_t  PD_Data_time_constant;
95   FloatInIntFormat_t  PD_Data_error_coeff;
96   FloatInIntFormat_t  PD_Data_error_rate_coeff;
97 } DpmActivityMonitorCoeffExt_t;
98 
99 typedef struct {
100   DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
101 } CustomDpmSettings_t;
102 
103 #define NUM_DCFCLK_DPM_LEVELS   8
104 #define NUM_DISPCLK_DPM_LEVELS  8
105 #define NUM_DPPCLK_DPM_LEVELS   8
106 #define NUM_SOCCLK_DPM_LEVELS   8
107 #define NUM_VCN_DPM_LEVELS      8
108 #define NUM_SOC_VOLTAGE_LEVELS  8
109 #define NUM_DF_PSTATE_LEVELS    4
110 
111 typedef struct {
112   uint32_t FClk;
113   uint32_t MemClk;
114   uint32_t Voltage;
115   uint8_t  WckRatio;
116   uint8_t  Spare[3];
117 } DfPstateTable_t;
118 
119 //Freq in MHz
120 //Voltage in milli volts with 2 fractional bits
121 typedef struct {
122   uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
123   uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
124   uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
125   uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
126   uint32_t VClocks[NUM_VCN_DPM_LEVELS];
127   uint32_t DClocks[NUM_VCN_DPM_LEVELS];
128   uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
129   DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS];
130 
131   uint8_t  NumDcfClkLevelsEnabled;
132   uint8_t  NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
133   uint8_t  NumSocClkLevelsEnabled;
134   uint8_t  VcnClkLevelsEnabled;     //Applies to both Vclk and Dclk
135   uint8_t  NumDfPstatesEnabled;
136   uint8_t  spare[3];
137 
138   uint32_t MinGfxClk;
139   uint32_t MaxGfxClk;
140 } DpmClocks_t;
141 
142 
143 // Throttler Status Bitmask
144 #define THROTTLER_STATUS_BIT_SPL            0
145 #define THROTTLER_STATUS_BIT_FPPT           1
146 #define THROTTLER_STATUS_BIT_SPPT           2
147 #define THROTTLER_STATUS_BIT_SPPT_APU       3
148 #define THROTTLER_STATUS_BIT_THM_CORE       4
149 #define THROTTLER_STATUS_BIT_THM_GFX        5
150 #define THROTTLER_STATUS_BIT_THM_SOC        6
151 #define THROTTLER_STATUS_BIT_TDC_VDD        7
152 #define THROTTLER_STATUS_BIT_TDC_SOC        8
153 #define THROTTLER_STATUS_BIT_PROCHOT_CPU    9
154 #define THROTTLER_STATUS_BIT_PROCHOT_GFX   10
155 #define THROTTLER_STATUS_BIT_EDC_CPU       11
156 #define THROTTLER_STATUS_BIT_EDC_GFX       12
157 
158 typedef struct {
159   uint16_t GfxclkFrequency;             //[MHz]
160   uint16_t SocclkFrequency;             //[MHz]
161   uint16_t VclkFrequency;               //[MHz]
162   uint16_t DclkFrequency;               //[MHz]
163   uint16_t MemclkFrequency;             //[MHz]
164   uint16_t spare;
165 
166   uint16_t GfxActivity;                 //[centi]
167   uint16_t UvdActivity;                 //[centi]
168 
169   uint16_t Voltage[2];                  //[mV] indices: VDDCR_VDD, VDDCR_SOC
170   uint16_t Current[2];                  //[mA] indices: VDDCR_VDD, VDDCR_SOC
171   uint16_t Power[2];                    //[mW] indices: VDDCR_VDD, VDDCR_SOC
172 
173   //3rd party tools in Windows need this info in the case of APUs
174   uint16_t CoreFrequency[8];            //[MHz]
175   uint16_t CorePower[8];                //[mW]
176   uint16_t CoreTemperature[8];          //[centi-Celsius]
177   uint16_t L3Frequency;                 //[MHz]
178   uint16_t L3Temperature;               //[centi-Celsius]
179 
180   uint16_t GfxTemperature;              //[centi-Celsius]
181   uint16_t SocTemperature;              //[centi-Celsius]
182   uint16_t ThrottlerStatus;
183 
184   uint16_t CurrentSocketPower;          //[mW]
185   uint16_t StapmOpnLimit;               //[W]
186   uint16_t StapmCurrentLimit;           //[W]
187   uint32_t ApuPower;                    //[mW]
188   uint32_t dGpuPower;                   //[mW]
189 
190   uint16_t VddTdcValue;                 //[mA]
191   uint16_t SocTdcValue;                 //[mA]
192   uint16_t VddEdcValue;                 //[mA]
193   uint16_t SocEdcValue;                 //[mA]
194 
195   uint16_t InfrastructureCpuMaxFreq;    //[MHz]
196   uint16_t InfrastructureGfxMaxFreq;    //[MHz]
197 
198   uint16_t SkinTemp;
199   uint16_t DeviceState;
200 } SmuMetrics_t;
201 
202 
203 // Workload bits
204 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
205 #define WORKLOAD_PPLIB_VIDEO_BIT          2
206 #define WORKLOAD_PPLIB_VR_BIT             3
207 #define WORKLOAD_PPLIB_COMPUTE_BIT        4
208 #define WORKLOAD_PPLIB_CUSTOM_BIT         5
209 #define WORKLOAD_PPLIB_COUNT              6
210 
211 #define TABLE_BIOS_IF               0 // Called by BIOS
212 #define TABLE_WATERMARKS            1 // Called by DAL through VBIOS
213 #define TABLE_CUSTOM_DPM            2 // Called by Driver
214 #define TABLE_SPARE1                3
215 #define TABLE_DPMCLOCKS             4 // Called by Driver and VBIOS
216 #define TABLE_MOMENTARY_PM          5 // Called by Tools
217 #define TABLE_MODERN_STDBY          6 // Called by Tools for Modern Standby Log
218 #define TABLE_SMU_METRICS           7 // Called by Driver
219 #define TABLE_INFRASTRUCTURE_LIMITS 8
220 #define TABLE_COUNT                 9
221 
222 #endif
223