1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef SMU13_DRIVER_IF_SMU_13_0_7_H 24 #define SMU13_DRIVER_IF_SMU_13_0_7_H 25 26 // *** IMPORTANT *** 27 // PMFW TEAM: Always increment the interface version on any change to this file 28 #define SMU13_DRIVER_IF_VERSION 0x35 29 30 //Increment this version if SkuTable_t or BoardTable_t change 31 #define PPTABLE_VERSION 0x27 32 33 #define NUM_GFXCLK_DPM_LEVELS 16 34 #define NUM_SOCCLK_DPM_LEVELS 8 35 #define NUM_MP0CLK_DPM_LEVELS 2 36 #define NUM_DCLK_DPM_LEVELS 8 37 #define NUM_VCLK_DPM_LEVELS 8 38 #define NUM_DISPCLK_DPM_LEVELS 8 39 #define NUM_DPPCLK_DPM_LEVELS 8 40 #define NUM_DPREFCLK_DPM_LEVELS 8 41 #define NUM_DCFCLK_DPM_LEVELS 8 42 #define NUM_DTBCLK_DPM_LEVELS 8 43 #define NUM_UCLK_DPM_LEVELS 4 44 #define NUM_LINK_LEVELS 3 45 #define NUM_FCLK_DPM_LEVELS 8 46 #define NUM_OD_FAN_MAX_POINTS 6 47 48 // Feature Control Defines 49 #define FEATURE_FW_DATA_READ_BIT 0 50 #define FEATURE_DPM_GFXCLK_BIT 1 51 #define FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT 2 52 #define FEATURE_DPM_UCLK_BIT 3 53 #define FEATURE_DPM_FCLK_BIT 4 54 #define FEATURE_DPM_SOCCLK_BIT 5 55 #define FEATURE_DPM_MP0CLK_BIT 6 56 #define FEATURE_DPM_LINK_BIT 7 57 #define FEATURE_DPM_DCN_BIT 8 58 #define FEATURE_VMEMP_SCALING_BIT 9 59 #define FEATURE_VDDIO_MEM_SCALING_BIT 10 60 #define FEATURE_DS_GFXCLK_BIT 11 61 #define FEATURE_DS_SOCCLK_BIT 12 62 #define FEATURE_DS_FCLK_BIT 13 63 #define FEATURE_DS_LCLK_BIT 14 64 #define FEATURE_DS_DCFCLK_BIT 15 65 #define FEATURE_DS_UCLK_BIT 16 66 #define FEATURE_GFX_ULV_BIT 17 67 #define FEATURE_FW_DSTATE_BIT 18 68 #define FEATURE_GFXOFF_BIT 19 69 #define FEATURE_BACO_BIT 20 70 #define FEATURE_MM_DPM_BIT 21 71 #define FEATURE_SOC_MPCLK_DS_BIT 22 72 #define FEATURE_BACO_MPCLK_DS_BIT 23 73 #define FEATURE_THROTTLERS_BIT 24 74 #define FEATURE_SMARTSHIFT_BIT 25 75 #define FEATURE_GTHR_BIT 26 76 #define FEATURE_ACDC_BIT 27 77 #define FEATURE_VR0HOT_BIT 28 78 #define FEATURE_FW_CTF_BIT 29 79 #define FEATURE_FAN_CONTROL_BIT 30 80 #define FEATURE_GFX_DCS_BIT 31 81 #define FEATURE_GFX_READ_MARGIN_BIT 32 82 #define FEATURE_LED_DISPLAY_BIT 33 83 #define FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT 34 84 #define FEATURE_OUT_OF_BAND_MONITOR_BIT 35 85 #define FEATURE_OPTIMIZED_VMIN_BIT 36 86 #define FEATURE_GFX_IMU_BIT 37 87 #define FEATURE_BOOT_TIME_CAL_BIT 38 88 #define FEATURE_GFX_PCC_DFLL_BIT 39 89 #define FEATURE_SOC_CG_BIT 40 90 #define FEATURE_DF_CSTATE_BIT 41 91 #define FEATURE_GFX_EDC_BIT 42 92 #define FEATURE_BOOT_POWER_OPT_BIT 43 93 #define FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT 44 94 #define FEATURE_DS_VCN_BIT 45 95 #define FEATURE_BACO_CG_BIT 46 96 #define FEATURE_MEM_TEMP_READ_BIT 47 97 #define FEATURE_ATHUB_MMHUB_PG_BIT 48 98 #define FEATURE_SOC_PCC_BIT 49 99 #define FEATURE_EDC_PWRBRK_BIT 50 100 #define FEATURE_SPARE_51_BIT 51 101 #define FEATURE_SPARE_52_BIT 52 102 #define FEATURE_SPARE_53_BIT 53 103 #define FEATURE_SPARE_54_BIT 54 104 #define FEATURE_SPARE_55_BIT 55 105 #define FEATURE_SPARE_56_BIT 56 106 #define FEATURE_SPARE_57_BIT 57 107 #define FEATURE_SPARE_58_BIT 58 108 #define FEATURE_SPARE_59_BIT 59 109 #define FEATURE_SPARE_60_BIT 60 110 #define FEATURE_SPARE_61_BIT 61 111 #define FEATURE_SPARE_62_BIT 62 112 #define FEATURE_SPARE_63_BIT 63 113 #define NUM_FEATURES 64 114 115 #define ALLOWED_FEATURE_CTRL_DEFAULT 0xFFFFFFFFFFFFFFFFULL 116 #define ALLOWED_FEATURE_CTRL_SCPM (1 << FEATURE_DPM_GFXCLK_BIT) | \ 117 (1 << FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | \ 118 (1 << FEATURE_DPM_UCLK_BIT) | \ 119 (1 << FEATURE_DPM_FCLK_BIT) | \ 120 (1 << FEATURE_DPM_SOCCLK_BIT) | \ 121 (1 << FEATURE_DPM_MP0CLK_BIT) | \ 122 (1 << FEATURE_DPM_LINK_BIT) | \ 123 (1 << FEATURE_DPM_DCN_BIT) | \ 124 (1 << FEATURE_DS_GFXCLK_BIT) | \ 125 (1 << FEATURE_DS_SOCCLK_BIT) | \ 126 (1 << FEATURE_DS_FCLK_BIT) | \ 127 (1 << FEATURE_DS_LCLK_BIT) | \ 128 (1 << FEATURE_DS_DCFCLK_BIT) | \ 129 (1 << FEATURE_DS_UCLK_BIT) 130 131 //For use with feature control messages 132 typedef enum { 133 FEATURE_PWR_ALL, 134 FEATURE_PWR_S5, 135 FEATURE_PWR_BACO, 136 FEATURE_PWR_SOC, 137 FEATURE_PWR_GFX, 138 FEATURE_PWR_DOMAIN_COUNT, 139 } FEATURE_PWR_DOMAIN_e; 140 141 142 // Debug Overrides Bitmask 143 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000001 144 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK 0x00000002 145 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK 0x00000004 146 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK 0x00000008 147 #define DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x00000010 148 #define DEBUG_OVERRIDE_DISABLE_VCN_PG 0x00000020 149 #define DEBUG_OVERRIDE_DISABLE_FMAX_VMAX 0x00000040 150 #define DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS 0x00000080 151 #define DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK 0x00000100 152 #define DEBUG_OVERRIDE_DISABLE_DFLL 0x00000200 153 #define DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE 0x00000400 154 #define DEBUG_OVERRIDE_DFLL_MASTER_MODE 0x00000800 155 #define DEBUG_OVERRIDE_ENABLE_PROFILING_MODE 0x00001000 156 157 // VR Mapping Bit Defines 158 #define VR_MAPPING_VR_SELECT_MASK 0x01 159 #define VR_MAPPING_VR_SELECT_SHIFT 0x00 160 161 #define VR_MAPPING_PLANE_SELECT_MASK 0x02 162 #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 163 164 // PSI Bit Defines 165 #define PSI_SEL_VR0_PLANE0_PSI0 0x01 166 #define PSI_SEL_VR0_PLANE0_PSI1 0x02 167 #define PSI_SEL_VR0_PLANE1_PSI0 0x04 168 #define PSI_SEL_VR0_PLANE1_PSI1 0x08 169 #define PSI_SEL_VR1_PLANE0_PSI0 0x10 170 #define PSI_SEL_VR1_PLANE0_PSI1 0x20 171 #define PSI_SEL_VR1_PLANE1_PSI0 0x40 172 #define PSI_SEL_VR1_PLANE1_PSI1 0x80 173 174 typedef enum { 175 SVI_PSI_0, // Full phase count (default) 176 SVI_PSI_1, // Phase count 1st level 177 SVI_PSI_2, // Phase count 2nd level 178 SVI_PSI_3, // Single phase operation + active diode emulation 179 SVI_PSI_4, // Single phase operation + passive diode emulation *optional* 180 SVI_PSI_5, // Reserved 181 SVI_PSI_6, // Power down to 0V (voltage regulation disabled) 182 SVI_PSI_7, // Automated phase shedding and diode emulation 183 } SVI_PSI_e; 184 185 // Throttler Control/Status Bits 186 #define THROTTLER_TEMP_EDGE_BIT 0 187 #define THROTTLER_TEMP_HOTSPOT_BIT 1 188 #define THROTTLER_TEMP_HOTSPOT_G_BIT 2 189 #define THROTTLER_TEMP_HOTSPOT_M_BIT 3 190 #define THROTTLER_TEMP_MEM_BIT 4 191 #define THROTTLER_TEMP_VR_GFX_BIT 5 192 #define THROTTLER_TEMP_VR_MEM0_BIT 6 193 #define THROTTLER_TEMP_VR_MEM1_BIT 7 194 #define THROTTLER_TEMP_VR_SOC_BIT 8 195 #define THROTTLER_TEMP_VR_U_BIT 9 196 #define THROTTLER_TEMP_LIQUID0_BIT 10 197 #define THROTTLER_TEMP_LIQUID1_BIT 11 198 #define THROTTLER_TEMP_PLX_BIT 12 199 #define THROTTLER_TDC_GFX_BIT 13 200 #define THROTTLER_TDC_SOC_BIT 14 201 #define THROTTLER_TDC_U_BIT 15 202 #define THROTTLER_PPT0_BIT 16 203 #define THROTTLER_PPT1_BIT 17 204 #define THROTTLER_PPT2_BIT 18 205 #define THROTTLER_PPT3_BIT 19 206 #define THROTTLER_FIT_BIT 20 207 #define THROTTLER_GFX_APCC_PLUS_BIT 21 208 #define THROTTLER_COUNT 22 209 210 // FW DState Features Control Bits 211 #define FW_DSTATE_SOC_ULV_BIT 0 212 #define FW_DSTATE_G6_HSR_BIT 1 213 #define FW_DSTATE_G6_PHY_VMEMP_OFF_BIT 2 214 #define FW_DSTATE_SMN_DS_BIT 3 215 #define FW_DSTATE_MP1_WHISPER_MODE_BIT 4 216 #define FW_DSTATE_SOC_LIV_MIN_BIT 5 217 #define FW_DSTATE_SOC_PLL_PWRDN_BIT 6 218 #define FW_DSTATE_MEM_PLL_PWRDN_BIT 7 219 #define FW_DSTATE_MALL_ALLOC_BIT 8 220 #define FW_DSTATE_MEM_PSI_BIT 9 221 #define FW_DSTATE_HSR_NON_STROBE_BIT 10 222 #define FW_DSTATE_MP0_ENTER_WFI_BIT 11 223 #define FW_DSTATE_U_ULV_BIT 12 224 #define FW_DSTATE_MALL_FLUSH_BIT 13 225 #define FW_DSTATE_SOC_PSI_BIT 14 226 #define FW_DSTATE_U_PSI_BIT 15 227 #define FW_DSTATE_UCP_DS_BIT 16 228 #define FW_DSTATE_CSRCLK_DS_BIT 17 229 #define FW_DSTATE_MMHUB_INTERLOCK_BIT 18 230 #define FW_DSTATE_D0i3_2_QUIET_FW_BIT 19 231 #define FW_DSTATE_CLDO_PRG_BIT 20 232 #define FW_DSTATE_DF_PLL_PWRDN_BIT 21 233 #define FW_DSTATE_U_LOW_PWR_MODE_EN_BIT 22 234 #define FW_DSTATE_GFX_PSI6_BIT 23 235 #define FW_DSTATE_GFX_VR_PWR_STAGE_BIT 24 236 237 //LED Display Mask & Control Bits 238 #define LED_DISPLAY_GFX_DPM_BIT 0 239 #define LED_DISPLAY_PCIE_BIT 1 240 #define LED_DISPLAY_ERROR_BIT 2 241 242 243 #define MEM_TEMP_READ_OUT_OF_BAND_BIT 0 244 #define MEM_TEMP_READ_IN_BAND_REFRESH_BIT 1 245 #define MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT 2 246 247 typedef enum { 248 SMARTSHIFT_VERSION_1, 249 SMARTSHIFT_VERSION_2, 250 SMARTSHIFT_VERSION_3, 251 } SMARTSHIFT_VERSION_e; 252 253 typedef enum { 254 FOPT_CALC_AC_CALC_DC, 255 FOPT_PPTABLE_AC_CALC_DC, 256 FOPT_CALC_AC_PPTABLE_DC, 257 FOPT_PPTABLE_AC_PPTABLE_DC, 258 } FOPT_CALC_e; 259 260 typedef enum { 261 DRAM_BIT_WIDTH_DISABLED = 0, 262 DRAM_BIT_WIDTH_X_8 = 8, 263 DRAM_BIT_WIDTH_X_16 = 16, 264 DRAM_BIT_WIDTH_X_32 = 32, 265 DRAM_BIT_WIDTH_X_64 = 64, 266 DRAM_BIT_WIDTH_X_128 = 128, 267 DRAM_BIT_WIDTH_COUNT, 268 } DRAM_BIT_WIDTH_TYPE_e; 269 270 //I2C Interface 271 #define NUM_I2C_CONTROLLERS 8 272 273 #define I2C_CONTROLLER_ENABLED 1 274 #define I2C_CONTROLLER_DISABLED 0 275 276 #define MAX_SW_I2C_COMMANDS 24 277 278 typedef enum { 279 I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0 280 I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1 281 I2C_CONTROLLER_PORT_COUNT, 282 } I2cControllerPort_e; 283 284 typedef enum { 285 I2C_CONTROLLER_NAME_VR_GFX = 0, 286 I2C_CONTROLLER_NAME_VR_SOC, 287 I2C_CONTROLLER_NAME_VR_VMEMP, 288 I2C_CONTROLLER_NAME_VR_VDDIO, 289 I2C_CONTROLLER_NAME_LIQUID0, 290 I2C_CONTROLLER_NAME_LIQUID1, 291 I2C_CONTROLLER_NAME_PLX, 292 I2C_CONTROLLER_NAME_FAN_INTAKE, 293 I2C_CONTROLLER_NAME_COUNT, 294 } I2cControllerName_e; 295 296 typedef enum { 297 I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 298 I2C_CONTROLLER_THROTTLER_VR_GFX, 299 I2C_CONTROLLER_THROTTLER_VR_SOC, 300 I2C_CONTROLLER_THROTTLER_VR_VMEMP, 301 I2C_CONTROLLER_THROTTLER_VR_VDDIO, 302 I2C_CONTROLLER_THROTTLER_LIQUID0, 303 I2C_CONTROLLER_THROTTLER_LIQUID1, 304 I2C_CONTROLLER_THROTTLER_PLX, 305 I2C_CONTROLLER_THROTTLER_FAN_INTAKE, 306 I2C_CONTROLLER_THROTTLER_INA3221, 307 I2C_CONTROLLER_THROTTLER_COUNT, 308 } I2cControllerThrottler_e; 309 310 typedef enum { 311 I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5, 312 I2C_CONTROLLER_PROTOCOL_VR_IR35217, 313 I2C_CONTROLLER_PROTOCOL_TMP_MAX31875, 314 I2C_CONTROLLER_PROTOCOL_INA3221, 315 I2C_CONTROLLER_PROTOCOL_TMP_MAX6604, 316 I2C_CONTROLLER_PROTOCOL_COUNT, 317 } I2cControllerProtocol_e; 318 319 typedef struct { 320 uint8_t Enabled; 321 uint8_t Speed; 322 uint8_t SlaveAddress; 323 uint8_t ControllerPort; 324 uint8_t ControllerName; 325 uint8_t ThermalThrotter; 326 uint8_t I2cProtocol; 327 uint8_t PaddingConfig; 328 } I2cControllerConfig_t; 329 330 typedef enum { 331 I2C_PORT_SVD_SCL = 0, 332 I2C_PORT_GPIO, 333 } I2cPort_e; 334 335 typedef enum { 336 I2C_SPEED_FAST_50K = 0, //50 Kbits/s 337 I2C_SPEED_FAST_100K, //100 Kbits/s 338 I2C_SPEED_FAST_400K, //400 Kbits/s 339 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 340 I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 341 I2C_SPEED_HIGH_2M, //2.3 Mbits/s 342 I2C_SPEED_COUNT, 343 } I2cSpeed_e; 344 345 typedef enum { 346 I2C_CMD_READ = 0, 347 I2C_CMD_WRITE, 348 I2C_CMD_COUNT, 349 } I2cCmdType_e; 350 351 #define CMDCONFIG_STOP_BIT 0 352 #define CMDCONFIG_RESTART_BIT 1 353 #define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write 354 355 #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 356 #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 357 #define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT) 358 359 typedef struct { 360 uint8_t ReadWriteData; //Return data for read. Data to send for write 361 uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write 362 } SwI2cCmd_t; //SW I2C Command Table 363 364 typedef struct { 365 uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 366 uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select 367 uint8_t SlaveAddress; //Slave address of device 368 uint8_t NumCmds; //Number of commands 369 370 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 371 } SwI2cRequest_t; // SW I2C Request Table 372 373 typedef struct { 374 SwI2cRequest_t SwI2cRequest; 375 376 uint32_t Spare[8]; 377 uint32_t MmHubPadding[8]; // SMU internal use 378 } SwI2cRequestExternal_t; 379 380 typedef struct { 381 uint64_t mca_umc_status; 382 uint64_t mca_umc_addr; 383 384 uint16_t ce_count_lo_chip; 385 uint16_t ce_count_hi_chip; 386 387 uint32_t eccPadding; 388 } EccInfo_t; 389 390 typedef struct { 391 EccInfo_t EccInfo[24]; 392 } EccInfoTable_t; 393 394 //D3HOT sequences 395 typedef enum { 396 BACO_SEQUENCE, 397 MSR_SEQUENCE, 398 BAMACO_SEQUENCE, 399 ULPS_SEQUENCE, 400 D3HOT_SEQUENCE_COUNT, 401 } D3HOTSequence_e; 402 403 //This is aligned with RSMU PGFSM Register Mapping 404 typedef enum { 405 PG_DYNAMIC_MODE = 0, 406 PG_STATIC_MODE, 407 } PowerGatingMode_e; 408 409 //This is aligned with RSMU PGFSM Register Mapping 410 typedef enum { 411 PG_POWER_DOWN = 0, 412 PG_POWER_UP, 413 } PowerGatingSettings_e; 414 415 typedef struct { 416 uint32_t a; // store in IEEE float format in this variable 417 uint32_t b; // store in IEEE float format in this variable 418 uint32_t c; // store in IEEE float format in this variable 419 } QuadraticInt_t; 420 421 typedef struct { 422 uint32_t m; // store in IEEE float format in this variable 423 uint32_t b; // store in IEEE float format in this variable 424 } LinearInt_t; 425 426 typedef struct { 427 uint32_t a; // store in IEEE float format in this variable 428 uint32_t b; // store in IEEE float format in this variable 429 uint32_t c; // store in IEEE float format in this variable 430 } DroopInt_t; 431 432 typedef enum { 433 DCS_ARCH_DISABLED, 434 DCS_ARCH_FADCS, 435 DCS_ARCH_ASYNC, 436 } DCS_ARCH_e; 437 438 //Only Clks that have DPM descriptors are listed here 439 typedef enum { 440 PPCLK_GFXCLK = 0, 441 PPCLK_SOCCLK, 442 PPCLK_UCLK, 443 PPCLK_FCLK, 444 PPCLK_DCLK_0, 445 PPCLK_VCLK_0, 446 PPCLK_DCLK_1, 447 PPCLK_VCLK_1, 448 PPCLK_DISPCLK, 449 PPCLK_DPPCLK, 450 PPCLK_DPREFCLK, 451 PPCLK_DCFCLK, 452 PPCLK_DTBCLK, 453 PPCLK_COUNT, 454 } PPCLK_e; 455 456 typedef enum { 457 VOLTAGE_MODE_PPTABLE = 0, 458 VOLTAGE_MODE_FUSES, 459 VOLTAGE_MODE_COUNT, 460 } VOLTAGE_MODE_e; 461 462 463 typedef enum { 464 AVFS_VOLTAGE_GFX = 0, 465 AVFS_VOLTAGE_SOC, 466 AVFS_VOLTAGE_COUNT, 467 } AVFS_VOLTAGE_TYPE_e; 468 469 typedef enum { 470 AVFS_TEMP_COLD = 0, 471 AVFS_TEMP_HOT, 472 AVFS_TEMP_COUNT, 473 } AVFS_TEMP_e; 474 475 typedef enum { 476 AVFS_D_G, 477 AVFS_D_M_B, 478 AVFS_D_M_S, 479 AVFS_D_COUNT, 480 } AVFS_D_e; 481 482 typedef enum { 483 UCLK_DIV_BY_1 = 0, 484 UCLK_DIV_BY_2, 485 UCLK_DIV_BY_4, 486 UCLK_DIV_BY_8, 487 } UCLK_DIV_e; 488 489 typedef enum { 490 GPIO_INT_POLARITY_ACTIVE_LOW = 0, 491 GPIO_INT_POLARITY_ACTIVE_HIGH, 492 } GpioIntPolarity_e; 493 494 typedef enum { 495 PWR_CONFIG_TDP = 0, 496 PWR_CONFIG_TGP, 497 PWR_CONFIG_TCP_ESTIMATED, 498 PWR_CONFIG_TCP_MEASURED, 499 } PwrConfig_e; 500 501 typedef struct { 502 uint8_t Padding; 503 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 504 uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 505 uint8_t CalculateFopt; // Indication whether FW should calculate Fopt or use values below. Reference FOPT_CALC_e 506 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 507 uint32_t Padding3[3]; 508 uint16_t Padding4; 509 uint16_t FoptimalDc; //Foptimal frequency in DC power mode. 510 uint16_t FoptimalAc; //Foptimal frequency in AC power mode. 511 uint16_t Padding2; 512 } DpmDescriptor_t; 513 514 typedef enum { 515 PPT_THROTTLER_PPT0, 516 PPT_THROTTLER_PPT1, 517 PPT_THROTTLER_PPT2, 518 PPT_THROTTLER_PPT3, 519 PPT_THROTTLER_COUNT 520 } PPT_THROTTLER_e; 521 522 typedef enum { 523 TEMP_EDGE, 524 TEMP_HOTSPOT, 525 TEMP_HOTSPOT_G, 526 TEMP_HOTSPOT_M, 527 TEMP_MEM, 528 TEMP_VR_GFX, 529 TEMP_VR_MEM0, 530 TEMP_VR_MEM1, 531 TEMP_VR_SOC, 532 TEMP_VR_U, 533 TEMP_LIQUID0, 534 TEMP_LIQUID1, 535 TEMP_PLX, 536 TEMP_COUNT, 537 } TEMP_e; 538 539 typedef enum { 540 TDC_THROTTLER_GFX, 541 TDC_THROTTLER_SOC, 542 TDC_THROTTLER_U, 543 TDC_THROTTLER_COUNT 544 } TDC_THROTTLER_e; 545 546 typedef enum { 547 SVI_PLANE_GFX, 548 SVI_PLANE_SOC, 549 SVI_PLANE_VMEMP, 550 SVI_PLANE_VDDIO_MEM, 551 SVI_PLANE_U, 552 SVI_PLANE_COUNT, 553 } SVI_PLANE_e; 554 555 typedef enum { 556 PMFW_VOLT_PLANE_GFX, 557 PMFW_VOLT_PLANE_SOC, 558 PMFW_VOLT_PLANE_COUNT 559 } PMFW_VOLT_PLANE_e; 560 561 typedef enum { 562 CUSTOMER_VARIANT_ROW, 563 CUSTOMER_VARIANT_FALCON, 564 CUSTOMER_VARIANT_COUNT, 565 } CUSTOMER_VARIANT_e; 566 567 typedef enum { 568 POWER_SOURCE_AC, 569 POWER_SOURCE_DC, 570 POWER_SOURCE_COUNT, 571 } POWER_SOURCE_e; 572 573 typedef enum { 574 MEM_VENDOR_SAMSUNG, 575 MEM_VENDOR_INFINEON, 576 MEM_VENDOR_ELPIDA, 577 MEM_VENDOR_ETRON, 578 MEM_VENDOR_NANYA, 579 MEM_VENDOR_HYNIX, 580 MEM_VENDOR_MOSEL, 581 MEM_VENDOR_WINBOND, 582 MEM_VENDOR_ESMT, 583 MEM_VENDOR_PLACEHOLDER0, 584 MEM_VENDOR_PLACEHOLDER1, 585 MEM_VENDOR_PLACEHOLDER2, 586 MEM_VENDOR_PLACEHOLDER3, 587 MEM_VENDOR_PLACEHOLDER4, 588 MEM_VENDOR_PLACEHOLDER5, 589 MEM_VENDOR_MICRON, 590 MEM_VENDOR_COUNT, 591 } MEM_VENDOR_e; 592 593 typedef enum { 594 PP_GRTAVFS_HW_CPO_CTL_ZONE0, 595 PP_GRTAVFS_HW_CPO_CTL_ZONE1, 596 PP_GRTAVFS_HW_CPO_CTL_ZONE2, 597 PP_GRTAVFS_HW_CPO_CTL_ZONE3, 598 PP_GRTAVFS_HW_CPO_CTL_ZONE4, 599 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0, 600 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0, 601 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1, 602 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1, 603 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2, 604 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2, 605 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3, 606 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3, 607 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4, 608 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4, 609 PP_GRTAVFS_HW_ZONE0_VF, 610 PP_GRTAVFS_HW_ZONE1_VF1, 611 PP_GRTAVFS_HW_ZONE2_VF2, 612 PP_GRTAVFS_HW_ZONE3_VF3, 613 PP_GRTAVFS_HW_VOLTAGE_GB, 614 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0, 615 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1, 616 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2, 617 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3, 618 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4, 619 PP_GRTAVFS_HW_RESERVED_0, 620 PP_GRTAVFS_HW_RESERVED_1, 621 PP_GRTAVFS_HW_RESERVED_2, 622 PP_GRTAVFS_HW_RESERVED_3, 623 PP_GRTAVFS_HW_RESERVED_4, 624 PP_GRTAVFS_HW_RESERVED_5, 625 PP_GRTAVFS_HW_RESERVED_6, 626 PP_GRTAVFS_HW_FUSE_COUNT, 627 } PP_GRTAVFS_HW_FUSE_e; 628 629 typedef enum { 630 PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0, 631 PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0, 632 PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0, 633 PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0, 634 PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0, 635 PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0, 636 PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0, 637 PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0, 638 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0, 639 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1, 640 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2, 641 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3, 642 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4, 643 PP_GRTAVFS_FW_COMMON_FUSE_COUNT, 644 } PP_GRTAVFS_FW_COMMON_FUSE_e; 645 646 typedef enum { 647 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1, 648 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0, 649 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1, 650 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2, 651 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3, 652 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4, 653 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1, 654 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0, 655 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1, 656 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2, 657 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3, 658 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4, 659 PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY, 660 PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY, 661 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0, 662 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1, 663 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2, 664 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3, 665 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4, 666 PP_GRTAVFS_FW_SEP_FUSE_COUNT, 667 } PP_GRTAVFS_FW_SEP_FUSE_e; 668 669 #define PP_NUM_RTAVFS_PWL_ZONES 5 670 671 672 673 // VBIOS or PPLIB configures telemetry slope and offset. Only slope expected to be set for SVI3 674 // Slope Q1.7, Offset Q1.2 675 typedef struct { 676 int8_t Offset; // in Amps 677 uint8_t Padding; 678 uint16_t MaxCurrent; // in Amps 679 } SviTelemetryScale_t; 680 681 #define PP_NUM_OD_VF_CURVE_POINTS PP_NUM_RTAVFS_PWL_ZONES + 1 682 683 684 #define PP_OD_FEATURE_GFX_VF_CURVE_BIT 0 685 #define PP_OD_FEATURE_VMAX_BIT 1 686 #define PP_OD_FEATURE_PPT_BIT 2 687 #define PP_OD_FEATURE_FAN_CURVE_BIT 3 688 #define PP_OD_FEATURE_FREQ_DETER_BIT 4 689 #define PP_OD_FEATURE_FULL_CTRL_BIT 5 690 #define PP_OD_FEATURE_TDC_BIT 6 691 #define PP_OD_FEATURE_GFXCLK_BIT 7 692 #define PP_OD_FEATURE_UCLK_BIT 8 693 #define PP_OD_FEATURE_ZERO_FAN_BIT 9 694 #define PP_OD_FEATURE_TEMPERATURE_BIT 10 695 #define PP_OD_FEATURE_POWER_FEATURE_CTRL_BIT 11 696 #define PP_OD_FEATURE_ASIC_TDC_BIT 12 697 #define PP_OD_FEATURE_COUNT 13 698 699 typedef enum { 700 PP_OD_POWER_FEATURE_ALWAYS_ENABLED, 701 PP_OD_POWER_FEATURE_DISABLED_WHILE_GAMING, 702 PP_OD_POWER_FEATURE_ALWAYS_DISABLED, 703 } PP_OD_POWER_FEATURE_e; 704 705 typedef enum { 706 FAN_MODE_AUTO = 0, 707 FAN_MODE_MANUAL_LINEAR, 708 } FanMode_e; 709 710 typedef struct { 711 uint32_t FeatureCtrlMask; 712 713 //Voltage control 714 int16_t VoltageOffsetPerZoneBoundary[PP_NUM_OD_VF_CURVE_POINTS]; 715 uint16_t VddGfxVmax; // in mV 716 717 uint8_t IdlePwrSavingFeaturesCtrl; 718 uint8_t RuntimePwrSavingFeaturesCtrl; 719 720 //Frequency changes 721 int16_t GfxclkFmin; // MHz 722 int16_t GfxclkFmax; // MHz 723 uint16_t UclkFmin; // MHz 724 uint16_t UclkFmax; // MHz 725 726 //PPT 727 int16_t Ppt; // % 728 int16_t Tdc; 729 730 //Fan control 731 uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS]; 732 uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS]; 733 uint16_t FanMinimumPwm; 734 uint16_t AcousticTargetRpmThreshold; 735 uint16_t AcousticLimitRpmThreshold; 736 uint16_t FanTargetTemperature; // Degree Celcius 737 uint8_t FanZeroRpmEnable; 738 uint8_t FanZeroRpmStopTemp; 739 uint8_t FanMode; 740 uint8_t MaxOpTemp; 741 uint8_t Padding[4]; 742 743 uint16_t GfxVoltageFullCtrlMode; 744 uint16_t GfxclkFullCtrlMode; 745 uint16_t UclkFullCtrlMode; 746 int16_t AsicTdc; 747 748 uint32_t Spare[10]; 749 uint32_t MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround 750 } OverDriveTable_t; 751 752 typedef struct { 753 OverDriveTable_t OverDriveTable; 754 755 } OverDriveTableExternal_t; 756 757 typedef struct { 758 uint32_t FeatureCtrlMask; 759 760 int16_t VoltageOffsetPerZoneBoundary; 761 uint16_t VddGfxVmax; // in mV 762 763 uint8_t IdlePwrSavingFeaturesCtrl; 764 uint8_t RuntimePwrSavingFeaturesCtrl; 765 766 int16_t GfxclkFmin; // MHz 767 int16_t GfxclkFmax; // MHz 768 uint16_t UclkFmin; // MHz 769 uint16_t UclkFmax; // MHz 770 771 //PPT 772 int16_t Ppt; // % 773 int16_t Tdc; 774 775 uint8_t FanLinearPwmPoints; 776 uint8_t FanLinearTempPoints; 777 uint16_t FanMinimumPwm; 778 uint16_t AcousticTargetRpmThreshold; 779 uint16_t AcousticLimitRpmThreshold; 780 uint16_t FanTargetTemperature; // Degree Celcius 781 uint8_t FanZeroRpmEnable; 782 uint8_t FanZeroRpmStopTemp; 783 uint8_t FanMode; 784 uint8_t MaxOpTemp; 785 uint8_t Padding[4]; 786 787 uint16_t GfxVoltageFullCtrlMode; 788 uint16_t GfxclkFullCtrlMode; 789 uint16_t UclkFullCtrlMode; 790 int16_t AsicTdc; 791 792 uint32_t Spare[10]; 793 794 } OverDriveLimits_t; 795 796 797 typedef enum { 798 BOARD_GPIO_SMUIO_0, 799 BOARD_GPIO_SMUIO_1, 800 BOARD_GPIO_SMUIO_2, 801 BOARD_GPIO_SMUIO_3, 802 BOARD_GPIO_SMUIO_4, 803 BOARD_GPIO_SMUIO_5, 804 BOARD_GPIO_SMUIO_6, 805 BOARD_GPIO_SMUIO_7, 806 BOARD_GPIO_SMUIO_8, 807 BOARD_GPIO_SMUIO_9, 808 BOARD_GPIO_SMUIO_10, 809 BOARD_GPIO_SMUIO_11, 810 BOARD_GPIO_SMUIO_12, 811 BOARD_GPIO_SMUIO_13, 812 BOARD_GPIO_SMUIO_14, 813 BOARD_GPIO_SMUIO_15, 814 BOARD_GPIO_SMUIO_16, 815 BOARD_GPIO_SMUIO_17, 816 BOARD_GPIO_SMUIO_18, 817 BOARD_GPIO_SMUIO_19, 818 BOARD_GPIO_SMUIO_20, 819 BOARD_GPIO_SMUIO_21, 820 BOARD_GPIO_SMUIO_22, 821 BOARD_GPIO_SMUIO_23, 822 BOARD_GPIO_SMUIO_24, 823 BOARD_GPIO_SMUIO_25, 824 BOARD_GPIO_SMUIO_26, 825 BOARD_GPIO_SMUIO_27, 826 BOARD_GPIO_SMUIO_28, 827 BOARD_GPIO_SMUIO_29, 828 BOARD_GPIO_SMUIO_30, 829 BOARD_GPIO_SMUIO_31, 830 MAX_BOARD_GPIO_SMUIO_NUM, 831 BOARD_GPIO_DC_GEN_A, 832 BOARD_GPIO_DC_GEN_B, 833 BOARD_GPIO_DC_GEN_C, 834 BOARD_GPIO_DC_GEN_D, 835 BOARD_GPIO_DC_GEN_E, 836 BOARD_GPIO_DC_GEN_F, 837 BOARD_GPIO_DC_GEN_G, 838 BOARD_GPIO_DC_GENLK_CLK, 839 BOARD_GPIO_DC_GENLK_VSYNC, 840 BOARD_GPIO_DC_SWAPLOCK_A, 841 BOARD_GPIO_DC_SWAPLOCK_B, 842 } BOARD_GPIO_TYPE_e; 843 844 #define INVALID_BOARD_GPIO 0xFF 845 846 847 typedef struct { 848 //PLL 0 849 uint16_t InitGfxclk_bypass; 850 uint16_t InitSocclk; 851 uint16_t InitMp0clk; 852 uint16_t InitMpioclk; 853 uint16_t InitSmnclk; 854 uint16_t InitUcpclk; 855 uint16_t InitCsrclk; 856 //PLL 1 857 858 uint16_t InitDprefclk; 859 uint16_t InitDcfclk; 860 uint16_t InitDtbclk; 861 //PLL 2 862 uint16_t InitDclk; //assume same DCLK/VCLK for both instances 863 uint16_t InitVclk; 864 // PLL 3 865 uint16_t InitUsbdfsclk; 866 uint16_t InitMp1clk; 867 uint16_t InitLclk; 868 uint16_t InitBaco400clk_bypass; 869 uint16_t InitBaco1200clk_bypass; 870 uint16_t InitBaco700clk_bypass; 871 // PLL 4 872 uint16_t InitFclk; 873 // PLL 5 874 uint16_t InitGfxclk_clkb; 875 876 //PLL 6 877 uint8_t InitUclkDPMState; // =0,1,2,3, frequency from FreqTableUclk 878 879 uint8_t Padding[3]; 880 881 uint32_t InitVcoFreqPll0; 882 uint32_t InitVcoFreqPll1; 883 uint32_t InitVcoFreqPll2; 884 uint32_t InitVcoFreqPll3; 885 uint32_t InitVcoFreqPll4; 886 uint32_t InitVcoFreqPll5; 887 uint32_t InitVcoFreqPll6; 888 889 //encoding will change depending on SVI2/SVI3 890 uint16_t InitGfx; // In mV(Q2) , should be 0? 891 uint16_t InitSoc; // In mV(Q2) 892 uint16_t InitU; // In Mv(Q2) not applicable 893 894 uint16_t Padding2; 895 896 uint32_t Spare[8]; 897 898 } BootValues_t; 899 900 901 typedef struct { 902 uint16_t Power[PPT_THROTTLER_COUNT][POWER_SOURCE_COUNT]; // Watts 903 uint16_t Tdc[TDC_THROTTLER_COUNT]; // Amps 904 905 uint16_t Temperature[TEMP_COUNT]; // Celsius 906 907 uint8_t PwmLimitMin; 908 uint8_t PwmLimitMax; 909 uint8_t FanTargetTemperature; 910 uint8_t Spare1[1]; 911 912 uint16_t AcousticTargetRpmThresholdMin; 913 uint16_t AcousticTargetRpmThresholdMax; 914 915 uint16_t AcousticLimitRpmThresholdMin; 916 uint16_t AcousticLimitRpmThresholdMax; 917 918 uint16_t PccLimitMin; 919 uint16_t PccLimitMax; 920 921 uint16_t FanStopTempMin; 922 uint16_t FanStopTempMax; 923 uint16_t FanStartTempMin; 924 uint16_t FanStartTempMax; 925 926 uint16_t PowerMinPpt0[POWER_SOURCE_COUNT]; 927 uint32_t Spare[11]; 928 929 } MsgLimits_t; 930 931 typedef struct { 932 uint16_t BaseClockAc; 933 uint16_t GameClockAc; 934 uint16_t BoostClockAc; 935 uint16_t BaseClockDc; 936 uint16_t GameClockDc; 937 uint16_t BoostClockDc; 938 939 uint32_t Reserved[4]; 940 } DriverReportedClocks_t; 941 942 typedef struct { 943 uint8_t DcBtcEnabled; 944 uint8_t Padding[3]; 945 946 uint16_t DcTol; // mV Q2 947 uint16_t DcBtcGb; // mV Q2 948 949 uint16_t DcBtcMin; // mV Q2 950 uint16_t DcBtcMax; // mV Q2 951 952 LinearInt_t DcBtcGbScalar; 953 954 } AvfsDcBtcParams_t; 955 956 typedef struct { 957 uint16_t AvfsTemp[AVFS_TEMP_COUNT]; //in degrees C 958 uint16_t VftFMin; // in MHz 959 uint16_t VInversion; // in mV Q2 960 QuadraticInt_t qVft[AVFS_TEMP_COUNT]; 961 QuadraticInt_t qAvfsGb; 962 QuadraticInt_t qAvfsGb2; 963 } AvfsFuseOverride_t; 964 965 typedef struct { 966 // SECTION: Version 967 968 uint32_t Version; // should be unique to each SKU(i.e if any value changes in below structure then this value must be different) 969 970 // SECTION: Feature Control 971 uint32_t FeaturesToRun[NUM_FEATURES / 32]; // Features that PMFW will attempt to enable. Use FEATURE_*_BIT as mapping 972 973 // SECTION: Miscellaneous Configuration 974 uint8_t TotalPowerConfig; // Determines how PMFW calculates the power. Use defines from PwrConfig_e 975 uint8_t CustomerVariant; //To specify if this PPTable is intended for a particular customer. Use defines from CUSTOMER_VARIANT_e 976 uint8_t MemoryTemperatureTypeMask; // Bit mapping indicating which methods of memory temperature reading are enabled. Use defines from MEM_TEMP_*BIT 977 uint8_t SmartShiftVersion; // Determine what SmartShift feature version is supported Use defines from SMARTSHIFT_VERSION_e 978 979 // SECTION: Infrastructure Limits 980 uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in AC mode. Multiple limits supported 981 uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in DC mode. Multiple limits supported 982 983 uint16_t SocketPowerLimitSmartShift2; // In Watts. Power limit used SmartShift 984 985 //if set to 1, SocketPowerLimitAc and SocketPowerLimitDc will be interpreted as legacy programs(i.e absolute power). If 0, all except index 0 will be scalars 986 //relative index 0 987 uint8_t EnableLegacyPptLimit; 988 uint8_t UseInputTelemetry; //applicable to SVI3 only and only to be set if VRs support 989 uint8_t SmartShiftMinReportedPptinDcs; //minimum possible active power consumption for this SKU. Used for SmartShift power reporting 990 991 uint8_t PaddingPpt[1]; 992 993 uint16_t VrTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with VR regulator maximum temperature 994 995 uint16_t PlatformTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with platform maximum temperature per VR current rail 996 997 uint16_t TemperatureLimit[TEMP_COUNT]; // In degrees Celsius. Temperature limit associated with each input 998 999 uint16_t HwCtfTempLimit; // In degrees Celsius. Temperature above which HW will trigger CTF. Consumed by VBIOS only 1000 1001 uint16_t PaddingInfra; 1002 1003 // Per year normalized Vmax state failure rates (sum of the two domains divided by life time in years) 1004 uint32_t FitControllerFailureRateLimit; //in IEEE float 1005 //Expected GFX Duty Cycle at Vmax. 1006 uint32_t FitControllerGfxDutyCycle; // in IEEE float 1007 //Expected SOC Duty Cycle at Vmax. 1008 uint32_t FitControllerSocDutyCycle; // in IEEE float 1009 1010 //This offset will be deducted from the controller output to before it goes through the SOC Vset limiter block. 1011 uint32_t FitControllerSocOffset; //in IEEE float 1012 1013 uint32_t GfxApccPlusResidencyLimit; // Percentage value. Used by APCC+ controller to control PCC residency to some value 1014 1015 // SECTION: Throttler settings 1016 uint32_t ThrottlerControlMask; // See THROTTLER_*_BIT for mapping 1017 1018 // SECTION: FW DSTATE Settings 1019 uint32_t FwDStateMask; // See FW_DSTATE_*_BIT for mapping 1020 1021 // SECTION: Voltage Control Parameters 1022 uint16_t UlvVoltageOffset[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2). ULV offset used in either GFX_ULV or SOC_ULV(part of FW_DSTATE) 1023 1024 uint16_t UlvVoltageOffsetU; // In mV(Q2). ULV offset used in either U_ULV(part of FW_DSTATE) 1025 uint16_t DeepUlvVoltageOffsetSoc; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC as part of FW_DSTATE 1026 1027 // Voltage Limits 1028 uint16_t DefaultMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage without FIT controller enabled 1029 uint16_t BoostMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage with FIT controller enabled 1030 1031 //Vmin Optimizations 1032 int16_t VminTempHystersis[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature hysteresis for switching between low/high temperature values for Vmin 1033 int16_t VminTempThreshold[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature threshold for switching between low/high temperature values for Vmin 1034 uint16_t Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at hot. 1035 uint16_t Vmin_Cold_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at cold. 1036 uint16_t Vmin_Hot_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at hot. 1037 uint16_t Vmin_Cold_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at cold. 1038 uint16_t Vmin_Aging_Offset[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Worst-case aging margin 1039 uint16_t Spare_Vmin_Plat_Offset_Hot[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Hot 1040 uint16_t Spare_Vmin_Plat_Offset_Cold[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Cold 1041 1042 //This is a fixed/minimum VMIN aging degradation offset which is applied at T0. This reflects the minimum amount of aging already accounted for. 1043 uint16_t VcBtcFixedVminAgingOffset[PMFW_VOLT_PLANE_COUNT]; 1044 //Linear offset or GB term to account for mis-correlation between PSM and Vmin shift trends across parts. 1045 uint16_t VcBtcVmin2PsmDegrationGb[PMFW_VOLT_PLANE_COUNT]; 1046 //Scalar coefficient of the PSM aging degradation function 1047 uint32_t VcBtcPsmA[PMFW_VOLT_PLANE_COUNT]; // A_PSM 1048 //Exponential coefficient of the PSM aging degradation function 1049 uint32_t VcBtcPsmB[PMFW_VOLT_PLANE_COUNT]; // B_PSM 1050 //Scalar coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 1051 uint32_t VcBtcVminA[PMFW_VOLT_PLANE_COUNT]; // A_VMIN 1052 //Exponential coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 1053 uint32_t VcBtcVminB[PMFW_VOLT_PLANE_COUNT]; // B_VMIN 1054 1055 uint8_t PerPartVminEnabled[PMFW_VOLT_PLANE_COUNT]; 1056 uint8_t VcBtcEnabled[PMFW_VOLT_PLANE_COUNT]; 1057 1058 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 1059 uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 1060 1061 QuadraticInt_t Vmin_droop; 1062 uint32_t SpareVmin[9]; 1063 1064 1065 //SECTION: DPM Configuration 1 1066 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 1067 1068 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1069 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1070 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1071 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1072 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1073 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1074 uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1075 uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1076 uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1077 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1078 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1079 1080 uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1081 1082 // SECTION: DPM Configuration 2 1083 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 1084 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 1085 1086 uint8_t GfxclkSpare[2]; 1087 uint16_t GfxclkFreqCap; 1088 1089 //GFX Idle Power Settings 1090 uint16_t GfxclkFgfxoffEntry; // in Mhz 1091 uint16_t GfxclkFgfxoffExitImu; // in Mhz 1092 uint16_t GfxclkFgfxoffExitRlc; // in Mhz 1093 uint16_t GfxclkThrottleClock; //Used primarily in DCS 1094 uint8_t EnableGfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages 1095 uint8_t GfxIdlePadding; 1096 1097 uint8_t SmsRepairWRCKClkDivEn; 1098 uint8_t SmsRepairWRCKClkDivVal; 1099 uint8_t GfxOffEntryEarlyMGCGEn; 1100 uint8_t GfxOffEntryForceCGCGEn; 1101 uint8_t GfxOffEntryForceCGCGDelayEn; 1102 uint8_t GfxOffEntryForceCGCGDelayVal; // in microseconds 1103 1104 uint16_t GfxclkFreqGfxUlv; // in MHz 1105 uint8_t GfxIdlePadding2[2]; 1106 uint32_t GfxOffEntryHysteresis; //For RLC to count after it enters CGCG, and before triggers GFXOFF entry 1107 uint32_t GfxoffSpare[15]; 1108 1109 // GFX GPO 1110 uint32_t DfllBtcMasterScalerM; 1111 int32_t DfllBtcMasterScalerB; 1112 uint32_t DfllBtcSlaveScalerM; 1113 int32_t DfllBtcSlaveScalerB; 1114 uint32_t DfllPccAsWaitCtrl; //GDFLL_AS_WAIT_CTRL_PCC register value to be passed to RLC msg 1115 uint32_t DfllPccAsStepCtrl; //GDFLL_AS_STEP_CTRL_PCC register value to be passed to RLC msg 1116 uint32_t GfxGpoSpare[10]; 1117 1118 // GFX DCS 1119 1120 uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase 1121 uint16_t PaddingDcs; 1122 1123 uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase 1124 uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. 1125 1126 uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS. 1127 1128 uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. 1129 uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin. 1130 1131 1132 uint32_t DcsSpare[14]; 1133 1134 // UCLK section 1135 uint16_t ShadowFreqTableUclk[NUM_UCLK_DPM_LEVELS]; // In MHz 1136 1137 // UCLK section 1138 uint8_t UseStrobeModeOptimizations; //Set to indicate that FW should use strobe mode optimizations 1139 uint8_t PaddingMem[3]; 1140 1141 uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 1142 uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 1143 1144 uint16_t MemVmempVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1145 uint16_t MemVddioVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1146 1147 //FCLK Section 1148 1149 uint8_t FclkDpmUPstates[NUM_FCLK_DPM_LEVELS]; // U P-state ID associated with each FCLK DPM state. 1150 uint16_t FclkDpmVddU[NUM_FCLK_DPM_LEVELS]; // mV(Q2) Vset U voltage associated with each FCLK DPM state. 1151 uint16_t FclkDpmUSpeed[NUM_FCLK_DPM_LEVELS]; //U speed associated with each FCLK DPM state 1152 uint16_t FclkDpmDisallowPstateFreq; //Frequency which FW will target when indicated that display config cannot support P-state. Set to 0 use FW calculated value 1153 uint16_t PaddingFclk; 1154 1155 // Link DPM Settings 1156 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 1157 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 1158 uint16_t LclkFreq[NUM_LINK_LEVELS]; 1159 1160 // SECTION: Fan Control 1161 uint16_t FanStopTemp[TEMP_COUNT]; //Celsius 1162 uint16_t FanStartTemp[TEMP_COUNT]; //Celsius 1163 1164 uint16_t FanGain[TEMP_COUNT]; 1165 uint16_t FanGainPadding; 1166 1167 uint16_t FanPwmMin; 1168 uint16_t AcousticTargetRpmThreshold; 1169 uint16_t AcousticLimitRpmThreshold; 1170 uint16_t FanMaximumRpm; 1171 uint16_t MGpuAcousticLimitRpmThreshold; 1172 uint16_t FanTargetGfxclk; 1173 uint32_t TempInputSelectMask; 1174 uint8_t FanZeroRpmEnable; 1175 uint8_t FanTachEdgePerRev; 1176 uint16_t FanTargetTemperature[TEMP_COUNT]; 1177 1178 // The following are AFC override parameters. Leave at 0 to use FW defaults. 1179 int16_t FuzzyFan_ErrorSetDelta; 1180 int16_t FuzzyFan_ErrorRateSetDelta; 1181 int16_t FuzzyFan_PwmSetDelta; 1182 uint16_t FuzzyFan_Reserved; 1183 1184 uint16_t FwCtfLimit[TEMP_COUNT]; 1185 1186 uint16_t IntakeTempEnableRPM; 1187 int16_t IntakeTempOffsetTemp; 1188 uint16_t IntakeTempReleaseTemp; 1189 uint16_t IntakeTempHighIntakeAcousticLimit; 1190 uint16_t IntakeTempAcouticLimitReleaseRate; 1191 1192 int16_t FanAbnormalTempLimitOffset; 1193 uint16_t FanStalledTriggerRpm; 1194 uint16_t FanAbnormalTriggerRpmCoeff; 1195 uint16_t FanAbnormalDetectionEnable; 1196 1197 uint8_t FanIntakeSensorSupport; 1198 uint8_t FanIntakePadding[3]; 1199 uint32_t FanSpare[13]; 1200 // SECTION: VDD_GFX AVFS 1201 1202 uint8_t OverrideGfxAvfsFuses; 1203 uint8_t GfxAvfsPadding[3]; 1204 1205 uint32_t L2HwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; //see fusedoc for encoding 1206 uint32_t SeHwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; 1207 1208 uint32_t CommonRtAvfs[PP_GRTAVFS_FW_COMMON_FUSE_COUNT]; 1209 1210 uint32_t L2FwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1211 uint32_t SeFwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1212 1213 uint32_t Droop_PWL_F[PP_NUM_RTAVFS_PWL_ZONES]; 1214 uint32_t Droop_PWL_a[PP_NUM_RTAVFS_PWL_ZONES]; 1215 uint32_t Droop_PWL_b[PP_NUM_RTAVFS_PWL_ZONES]; 1216 uint32_t Droop_PWL_c[PP_NUM_RTAVFS_PWL_ZONES]; 1217 1218 uint32_t Static_PWL_Offset[PP_NUM_RTAVFS_PWL_ZONES]; 1219 1220 uint32_t dGbV_dT_vmin; 1221 uint32_t dGbV_dT_vmax; 1222 1223 uint32_t V2F_vmin_range_low; 1224 uint32_t V2F_vmin_range_high; 1225 uint32_t V2F_vmax_range_low; 1226 uint32_t V2F_vmax_range_high; 1227 1228 AvfsDcBtcParams_t DcBtcGfxParams; 1229 1230 uint32_t GfxAvfsSpare[32]; 1231 1232 //SECTION: VDD_SOC AVFS 1233 1234 uint8_t OverrideSocAvfsFuses; 1235 uint8_t MinSocAvfsRevision; 1236 uint8_t SocAvfsPadding[2]; 1237 1238 AvfsFuseOverride_t SocAvfsFuseOverride[AVFS_D_COUNT]; 1239 1240 DroopInt_t dBtcGbSoc[AVFS_D_COUNT]; // GHz->V BtcGb 1241 1242 LinearInt_t qAgingGb[AVFS_D_COUNT]; // GHz->V 1243 1244 QuadraticInt_t qStaticVoltageOffset[AVFS_D_COUNT]; // GHz->V 1245 1246 AvfsDcBtcParams_t DcBtcSocParams[AVFS_D_COUNT]; 1247 1248 uint32_t SocAvfsSpare[32]; 1249 1250 //SECTION: Boot clock and voltage values 1251 BootValues_t BootValues; 1252 1253 //SECTION: Driver Reported Clocks 1254 DriverReportedClocks_t DriverReportedClocks; 1255 1256 //SECTION: Message Limits 1257 MsgLimits_t MsgLimits; 1258 1259 //SECTION: OverDrive Limits 1260 OverDriveLimits_t OverDriveLimitsMin; 1261 OverDriveLimits_t OverDriveLimitsBasicMax; 1262 OverDriveLimits_t OverDriveLimitsAdvancedMax; 1263 1264 // SECTION: Advanced Options 1265 uint32_t DebugOverrides; 1266 1267 // Section: Total Board Power idle vs active coefficients 1268 uint8_t TotalBoardPowerSupport; 1269 uint8_t TotalBoardPowerPadding[3]; 1270 1271 int16_t TotalIdleBoardPowerM; 1272 int16_t TotalIdleBoardPowerB; 1273 int16_t TotalBoardPowerM; 1274 int16_t TotalBoardPowerB; 1275 1276 QuadraticInt_t qFeffCoeffGameClock[POWER_SOURCE_COUNT]; 1277 QuadraticInt_t qFeffCoeffBaseClock[POWER_SOURCE_COUNT]; 1278 QuadraticInt_t qFeffCoeffBoostClock[POWER_SOURCE_COUNT]; 1279 1280 // SECTION: Sku Reserved 1281 uint32_t Spare[43]; 1282 1283 // Padding for MMHUB - do not modify this 1284 uint32_t MmHubPadding[8]; 1285 1286 } SkuTable_t; 1287 1288 typedef struct { 1289 // SECTION: Version 1290 uint32_t Version; //should be unique to each board type 1291 1292 1293 // SECTION: I2C Control 1294 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 1295 1296 // SECTION: SVI2 Board Parameters 1297 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 1298 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 1299 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 1300 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 1301 1302 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1303 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1304 uint8_t VmempUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1305 uint8_t VddioUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1306 1307 //SECTION SVI3 Board Parameters 1308 uint8_t SlaveAddrMapping[SVI_PLANE_COUNT]; 1309 uint8_t VrPsiSupport[SVI_PLANE_COUNT]; 1310 1311 uint8_t PaddingPsi[SVI_PLANE_COUNT]; 1312 uint8_t EnablePsi6[SVI_PLANE_COUNT]; // only applicable in SVI3 1313 1314 // SECTION: Voltage Regulator Settings 1315 SviTelemetryScale_t SviTelemetryScale[SVI_PLANE_COUNT]; 1316 uint32_t VoltageTelemetryRatio[SVI_PLANE_COUNT]; // This is used for VDDIO Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 1317 1318 uint8_t DownSlewRateVr[SVI_PLANE_COUNT]; 1319 1320 // SECTION: GPIO Settings 1321 1322 uint8_t LedOffGpio; 1323 uint8_t FanOffGpio; 1324 uint8_t GfxVrPowerStageOffGpio; 1325 1326 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 1327 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 1328 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 1329 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 1330 1331 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 1332 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 1333 1334 // LED Display Settings 1335 uint8_t LedPin0; // GPIO number for LedPin[0] 1336 uint8_t LedPin1; // GPIO number for LedPin[1] 1337 uint8_t LedPin2; // GPIO number for LedPin[2] 1338 uint8_t LedEnableMask; 1339 1340 uint8_t LedPcie; // GPIO number for PCIE results 1341 uint8_t LedError; // GPIO number for Error Cases 1342 1343 // SECTION: Clock Spread Spectrum 1344 1345 // UCLK Spread Spectrum 1346 uint8_t UclkTrainingModeSpreadPercent; // Q4.4 1347 uint8_t UclkSpreadPadding; 1348 uint16_t UclkSpreadFreq; // kHz 1349 1350 // UCLK Spread Spectrum 1351 uint8_t UclkSpreadPercent[MEM_VENDOR_COUNT]; 1352 1353 // FCLK Spread Spectrum 1354 uint8_t FclkSpreadPadding; 1355 uint8_t FclkSpreadPercent; // Q4.4 1356 uint16_t FclkSpreadFreq; // kHz 1357 1358 // Section: Memory Config 1359 uint8_t DramWidth; // Width of interface to the channel for each DRAM module. See DRAM_BIT_WIDTH_TYPE_e 1360 uint8_t PaddingMem1[7]; 1361 1362 // SECTION: UMC feature flags 1363 uint8_t HsrEnabled; 1364 uint8_t VddqOffEnabled; 1365 uint8_t PaddingUmcFlags[2]; 1366 1367 uint32_t PostVoltageSetBacoDelay; // in microseconds. Amount of time FW will wait after power good is established or PSI0 command is issued 1368 uint32_t BacoEntryDelay; // in milliseconds. Amount of time FW will wait to trigger BACO entry after receiving entry notification from OS 1369 1370 uint8_t FuseWritePowerMuxPresent; 1371 uint8_t FuseWritePadding[3]; 1372 1373 // SECTION: Board Reserved 1374 uint32_t BoardSpare[63]; 1375 1376 // SECTION: Structure Padding 1377 1378 // Padding for MMHUB - do not modify this 1379 uint32_t MmHubPadding[8]; 1380 } BoardTable_t; 1381 1382 typedef struct { 1383 SkuTable_t SkuTable; 1384 BoardTable_t BoardTable; 1385 } PPTable_t; 1386 1387 typedef struct { 1388 // Time constant parameters for clock averages in ms 1389 uint16_t GfxclkAverageLpfTau; 1390 uint16_t FclkAverageLpfTau; 1391 uint16_t UclkAverageLpfTau; 1392 uint16_t GfxActivityLpfTau; 1393 uint16_t UclkActivityLpfTau; 1394 uint16_t SocketPowerLpfTau; 1395 uint16_t VcnClkAverageLpfTau; 1396 uint16_t VcnUsageAverageLpfTau; 1397 } DriverSmuConfig_t; 1398 1399 typedef struct { 1400 DriverSmuConfig_t DriverSmuConfig; 1401 1402 uint32_t Spare[8]; 1403 // Padding - ignore 1404 uint32_t MmHubPadding[8]; // SMU internal use 1405 } DriverSmuConfigExternal_t; 1406 1407 1408 typedef struct { 1409 1410 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1411 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1412 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1413 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1414 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1415 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1416 uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1417 uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1418 uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1419 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1420 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1421 1422 uint16_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1423 1424 uint16_t Padding; 1425 1426 uint32_t Spare[32]; 1427 1428 // Padding - ignore 1429 uint32_t MmHubPadding[8]; // SMU internal use 1430 1431 } DriverInfoTable_t; 1432 1433 typedef struct { 1434 uint32_t CurrClock[PPCLK_COUNT]; 1435 1436 uint16_t AverageGfxclkFrequencyTarget; 1437 uint16_t AverageGfxclkFrequencyPreDs; 1438 uint16_t AverageGfxclkFrequencyPostDs; 1439 uint16_t AverageFclkFrequencyPreDs; 1440 uint16_t AverageFclkFrequencyPostDs; 1441 uint16_t AverageMemclkFrequencyPreDs ; // this is scaled to actual memory clock 1442 uint16_t AverageMemclkFrequencyPostDs ; // this is scaled to actual memory clock 1443 uint16_t AverageVclk0Frequency ; 1444 uint16_t AverageDclk0Frequency ; 1445 uint16_t AverageVclk1Frequency ; 1446 uint16_t AverageDclk1Frequency ; 1447 uint16_t PCIeBusy ; 1448 uint16_t dGPU_W_MAX ; 1449 uint16_t padding ; 1450 1451 uint32_t MetricsCounter ; 1452 1453 uint16_t AvgVoltage[SVI_PLANE_COUNT]; 1454 uint16_t AvgCurrent[SVI_PLANE_COUNT]; 1455 1456 uint16_t AverageGfxActivity ; 1457 uint16_t AverageUclkActivity ; 1458 uint16_t Vcn0ActivityPercentage ; 1459 uint16_t Vcn1ActivityPercentage ; 1460 1461 uint32_t EnergyAccumulator; 1462 uint16_t AverageSocketPower; 1463 uint16_t AverageTotalBoardPower; 1464 1465 uint16_t AvgTemperature[TEMP_COUNT]; 1466 uint16_t AvgTemperatureFanIntake; 1467 1468 uint8_t PcieRate ; 1469 uint8_t PcieWidth ; 1470 1471 uint8_t AvgFanPwm; 1472 uint8_t Padding[1]; 1473 uint16_t AvgFanRpm; 1474 1475 1476 uint8_t ThrottlingPercentage[THROTTLER_COUNT]; 1477 1478 //metrics for D3hot entry/exit and driver ARM msgs 1479 uint32_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; 1480 uint32_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT]; 1481 uint32_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT]; 1482 1483 uint16_t ApuSTAPMSmartShiftLimit; 1484 uint16_t ApuSTAPMLimit; 1485 uint16_t AvgApuSocketPower; 1486 1487 uint16_t AverageUclkActivity_MAX; 1488 1489 uint32_t PublicSerialNumberLower; 1490 uint32_t PublicSerialNumberUpper; 1491 } SmuMetrics_t; 1492 1493 typedef struct { 1494 SmuMetrics_t SmuMetrics; 1495 uint32_t Spare[30]; 1496 1497 // Padding - ignore 1498 uint32_t MmHubPadding[8]; // SMU internal use 1499 } SmuMetricsExternal_t; 1500 1501 typedef struct { 1502 uint8_t WmSetting; 1503 uint8_t Flags; 1504 uint8_t Padding[2]; 1505 1506 } WatermarkRowGeneric_t; 1507 1508 #define NUM_WM_RANGES 4 1509 1510 typedef enum { 1511 WATERMARKS_CLOCK_RANGE = 0, 1512 WATERMARKS_DUMMY_PSTATE, 1513 WATERMARKS_MALL, 1514 WATERMARKS_COUNT, 1515 } WATERMARKS_FLAGS_e; 1516 1517 typedef struct { 1518 // Watermarks 1519 WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES]; 1520 } Watermarks_t; 1521 1522 typedef struct { 1523 Watermarks_t Watermarks; 1524 uint32_t Spare[16]; 1525 1526 uint32_t MmHubPadding[8]; // SMU internal use 1527 } WatermarksExternal_t; 1528 1529 typedef struct { 1530 uint16_t avgPsmCount[36]; 1531 uint16_t minPsmCount[36]; 1532 float avgPsmVoltage[36]; 1533 float minPsmVoltage[36]; 1534 } AvfsDebugTable_t; 1535 1536 typedef struct { 1537 AvfsDebugTable_t AvfsDebugTable; 1538 1539 uint32_t MmHubPadding[8]; // SMU internal use 1540 } AvfsDebugTableExternal_t; 1541 1542 1543 typedef struct { 1544 uint8_t Gfx_ActiveHystLimit; 1545 uint8_t Gfx_IdleHystLimit; 1546 uint8_t Gfx_FPS; 1547 uint8_t Gfx_MinActiveFreqType; 1548 uint8_t Gfx_BoosterFreqType; 1549 uint8_t PaddingGfx; 1550 uint16_t Gfx_MinActiveFreq; // MHz 1551 uint16_t Gfx_BoosterFreq; // MHz 1552 uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms 1553 uint32_t Gfx_PD_Data_limit_a; // Q16 1554 uint32_t Gfx_PD_Data_limit_b; // Q16 1555 uint32_t Gfx_PD_Data_limit_c; // Q16 1556 uint32_t Gfx_PD_Data_error_coeff; // Q16 1557 uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 1558 1559 uint8_t Fclk_ActiveHystLimit; 1560 uint8_t Fclk_IdleHystLimit; 1561 uint8_t Fclk_FPS; 1562 uint8_t Fclk_MinActiveFreqType; 1563 uint8_t Fclk_BoosterFreqType; 1564 uint8_t PaddingFclk; 1565 uint16_t Fclk_MinActiveFreq; // MHz 1566 uint16_t Fclk_BoosterFreq; // MHz 1567 uint16_t Fclk_PD_Data_time_constant; // Time constant of PD controller in ms 1568 uint32_t Fclk_PD_Data_limit_a; // Q16 1569 uint32_t Fclk_PD_Data_limit_b; // Q16 1570 uint32_t Fclk_PD_Data_limit_c; // Q16 1571 uint32_t Fclk_PD_Data_error_coeff; // Q16 1572 uint32_t Fclk_PD_Data_error_rate_coeff; // Q16 1573 1574 uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16 1575 uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS]; 1576 uint8_t Mem_DownHystLimit[NUM_UCLK_DPM_LEVELS]; 1577 uint16_t Mem_Fps; 1578 uint8_t padding[2]; 1579 1580 } DpmActivityMonitorCoeffInt_t; 1581 1582 1583 typedef struct { 1584 DpmActivityMonitorCoeffInt_t DpmActivityMonitorCoeffInt; 1585 uint32_t MmHubPadding[8]; // SMU internal use 1586 } DpmActivityMonitorCoeffIntExternal_t; 1587 1588 1589 1590 // Workload bits 1591 #define WORKLOAD_PPLIB_DEFAULT_BIT 0 1592 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 1593 #define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 1594 #define WORKLOAD_PPLIB_VIDEO_BIT 3 1595 #define WORKLOAD_PPLIB_VR_BIT 4 1596 #define WORKLOAD_PPLIB_COMPUTE_BIT 5 1597 #define WORKLOAD_PPLIB_CUSTOM_BIT 6 1598 #define WORKLOAD_PPLIB_WINDOW_3D_BIT 7 1599 #define WORKLOAD_PPLIB_COUNT 8 1600 1601 1602 // These defines are used with the following messages: 1603 // SMC_MSG_TransferTableDram2Smu 1604 // SMC_MSG_TransferTableSmu2Dram 1605 1606 // Table transfer status 1607 #define TABLE_TRANSFER_OK 0x0 1608 #define TABLE_TRANSFER_FAILED 0xFF 1609 #define TABLE_TRANSFER_PENDING 0xAB 1610 1611 // Table types 1612 #define TABLE_PPTABLE 0 1613 #define TABLE_COMBO_PPTABLE 1 1614 #define TABLE_WATERMARKS 2 1615 #define TABLE_AVFS_PSM_DEBUG 3 1616 #define TABLE_PMSTATUSLOG 4 1617 #define TABLE_SMU_METRICS 5 1618 #define TABLE_DRIVER_SMU_CONFIG 6 1619 #define TABLE_ACTIVITY_MONITOR_COEFF 7 1620 #define TABLE_OVERDRIVE 8 1621 #define TABLE_I2C_COMMANDS 9 1622 #define TABLE_DRIVER_INFO 10 1623 #define TABLE_ECCINFO 11 1624 #define TABLE_COUNT 12 1625 1626 //IH Interupt ID 1627 #define IH_INTERRUPT_ID_TO_DRIVER 0xFE 1628 #define IH_INTERRUPT_CONTEXT_ID_BACO 0x2 1629 #define IH_INTERRUPT_CONTEXT_ID_AC 0x3 1630 #define IH_INTERRUPT_CONTEXT_ID_DC 0x4 1631 #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 0x5 1632 #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 0x6 1633 #define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING 0x7 1634 #define IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL 0x8 1635 #define IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY 0x9 1636 1637 #endif 1638