1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef SMU13_DRIVER_IF_SMU_13_0_7_H 24 #define SMU13_DRIVER_IF_SMU_13_0_7_H 25 26 // *** IMPORTANT *** 27 // PMFW TEAM: Always increment the interface version on any change to this file 28 #define SMU13_DRIVER_IF_VERSION 0x2A 29 30 //Increment this version if SkuTable_t or BoardTable_t change 31 #define PPTABLE_VERSION 0x1E 32 33 #define NUM_GFXCLK_DPM_LEVELS 16 34 #define NUM_SOCCLK_DPM_LEVELS 8 35 #define NUM_MP0CLK_DPM_LEVELS 2 36 #define NUM_DCLK_DPM_LEVELS 8 37 #define NUM_VCLK_DPM_LEVELS 8 38 #define NUM_DISPCLK_DPM_LEVELS 8 39 #define NUM_DPPCLK_DPM_LEVELS 8 40 #define NUM_DPREFCLK_DPM_LEVELS 8 41 #define NUM_DCFCLK_DPM_LEVELS 8 42 #define NUM_DTBCLK_DPM_LEVELS 8 43 #define NUM_UCLK_DPM_LEVELS 4 44 #define NUM_LINK_LEVELS 3 45 #define NUM_FCLK_DPM_LEVELS 8 46 #define NUM_OD_FAN_MAX_POINTS 6 47 48 // Feature Control Defines 49 #define FEATURE_FW_DATA_READ_BIT 0 50 #define FEATURE_DPM_GFXCLK_BIT 1 51 #define FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT 2 52 #define FEATURE_DPM_UCLK_BIT 3 53 #define FEATURE_DPM_FCLK_BIT 4 54 #define FEATURE_DPM_SOCCLK_BIT 5 55 #define FEATURE_DPM_MP0CLK_BIT 6 56 #define FEATURE_DPM_LINK_BIT 7 57 #define FEATURE_DPM_DCN_BIT 8 58 #define FEATURE_VMEMP_SCALING_BIT 9 59 #define FEATURE_VDDIO_MEM_SCALING_BIT 10 60 #define FEATURE_DS_GFXCLK_BIT 11 61 #define FEATURE_DS_SOCCLK_BIT 12 62 #define FEATURE_DS_FCLK_BIT 13 63 #define FEATURE_DS_LCLK_BIT 14 64 #define FEATURE_DS_DCFCLK_BIT 15 65 #define FEATURE_DS_UCLK_BIT 16 66 #define FEATURE_GFX_ULV_BIT 17 67 #define FEATURE_FW_DSTATE_BIT 18 68 #define FEATURE_GFXOFF_BIT 19 69 #define FEATURE_BACO_BIT 20 70 #define FEATURE_MM_DPM_BIT 21 71 #define FEATURE_SOC_MPCLK_DS_BIT 22 72 #define FEATURE_BACO_MPCLK_DS_BIT 23 73 #define FEATURE_THROTTLERS_BIT 24 74 #define FEATURE_SMARTSHIFT_BIT 25 75 #define FEATURE_GTHR_BIT 26 76 #define FEATURE_ACDC_BIT 27 77 #define FEATURE_VR0HOT_BIT 28 78 #define FEATURE_FW_CTF_BIT 29 79 #define FEATURE_FAN_CONTROL_BIT 30 80 #define FEATURE_GFX_DCS_BIT 31 81 #define FEATURE_GFX_READ_MARGIN_BIT 32 82 #define FEATURE_LED_DISPLAY_BIT 33 83 #define FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT 34 84 #define FEATURE_OUT_OF_BAND_MONITOR_BIT 35 85 #define FEATURE_OPTIMIZED_VMIN_BIT 36 86 #define FEATURE_GFX_IMU_BIT 37 87 #define FEATURE_BOOT_TIME_CAL_BIT 38 88 #define FEATURE_GFX_PCC_DFLL_BIT 39 89 #define FEATURE_SOC_CG_BIT 40 90 #define FEATURE_DF_CSTATE_BIT 41 91 #define FEATURE_GFX_EDC_BIT 42 92 #define FEATURE_BOOT_POWER_OPT_BIT 43 93 #define FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT 44 94 #define FEATURE_DS_VCN_BIT 45 95 #define FEATURE_BACO_CG_BIT 46 96 #define FEATURE_MEM_TEMP_READ_BIT 47 97 #define FEATURE_ATHUB_MMHUB_PG_BIT 48 98 #define FEATURE_SOC_PCC_BIT 49 99 #define FEATURE_SPARE_50_BIT 50 100 #define FEATURE_SPARE_51_BIT 51 101 #define FEATURE_SPARE_52_BIT 52 102 #define FEATURE_SPARE_53_BIT 53 103 #define FEATURE_SPARE_54_BIT 54 104 #define FEATURE_SPARE_55_BIT 55 105 #define FEATURE_SPARE_56_BIT 56 106 #define FEATURE_SPARE_57_BIT 57 107 #define FEATURE_SPARE_58_BIT 58 108 #define FEATURE_SPARE_59_BIT 59 109 #define FEATURE_SPARE_60_BIT 60 110 #define FEATURE_SPARE_61_BIT 61 111 #define FEATURE_SPARE_62_BIT 62 112 #define FEATURE_SPARE_63_BIT 63 113 #define NUM_FEATURES 64 114 115 #define ALLOWED_FEATURE_CTRL_DEFAULT 0xFFFFFFFFFFFFFFFFULL 116 #define ALLOWED_FEATURE_CTRL_SCPM (1 << FEATURE_DPM_GFXCLK_BIT) | \ 117 (1 << FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | \ 118 (1 << FEATURE_DPM_UCLK_BIT) | \ 119 (1 << FEATURE_DPM_FCLK_BIT) | \ 120 (1 << FEATURE_DPM_SOCCLK_BIT) | \ 121 (1 << FEATURE_DPM_MP0CLK_BIT) | \ 122 (1 << FEATURE_DPM_LINK_BIT) | \ 123 (1 << FEATURE_DPM_DCN_BIT) | \ 124 (1 << FEATURE_DS_GFXCLK_BIT) | \ 125 (1 << FEATURE_DS_SOCCLK_BIT) | \ 126 (1 << FEATURE_DS_FCLK_BIT) | \ 127 (1 << FEATURE_DS_LCLK_BIT) | \ 128 (1 << FEATURE_DS_DCFCLK_BIT) | \ 129 (1 << FEATURE_DS_UCLK_BIT) 130 131 //For use with feature control messages 132 typedef enum { 133 FEATURE_PWR_ALL, 134 FEATURE_PWR_S5, 135 FEATURE_PWR_BACO, 136 FEATURE_PWR_SOC, 137 FEATURE_PWR_GFX, 138 FEATURE_PWR_DOMAIN_COUNT, 139 } FEATURE_PWR_DOMAIN_e; 140 141 142 // Debug Overrides Bitmask 143 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000001 144 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK 0x00000002 145 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK 0x00000004 146 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK 0x00000008 147 #define DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x00000010 148 #define DEBUG_OVERRIDE_DISABLE_VCN_PG 0x00000020 149 #define DEBUG_OVERRIDE_DISABLE_FMAX_VMAX 0x00000040 150 #define DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS 0x00000080 151 #define DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK 0x00000100 152 #define DEBUG_OVERRIDE_DISABLE_DFLL 0x00000200 153 #define DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE 0x00000400 154 #define DEBUG_OVERRIDE_DFLL_MASTER_MODE 0x00000800 155 156 // VR Mapping Bit Defines 157 #define VR_MAPPING_VR_SELECT_MASK 0x01 158 #define VR_MAPPING_VR_SELECT_SHIFT 0x00 159 160 #define VR_MAPPING_PLANE_SELECT_MASK 0x02 161 #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 162 163 // PSI Bit Defines 164 #define PSI_SEL_VR0_PLANE0_PSI0 0x01 165 #define PSI_SEL_VR0_PLANE0_PSI1 0x02 166 #define PSI_SEL_VR0_PLANE1_PSI0 0x04 167 #define PSI_SEL_VR0_PLANE1_PSI1 0x08 168 #define PSI_SEL_VR1_PLANE0_PSI0 0x10 169 #define PSI_SEL_VR1_PLANE0_PSI1 0x20 170 #define PSI_SEL_VR1_PLANE1_PSI0 0x40 171 #define PSI_SEL_VR1_PLANE1_PSI1 0x80 172 173 typedef enum { 174 SVI_PSI_0, // Full phase count (default) 175 SVI_PSI_1, // Phase count 1st level 176 SVI_PSI_2, // Phase count 2nd level 177 SVI_PSI_3, // Single phase operation + active diode emulation 178 SVI_PSI_4, // Single phase operation + passive diode emulation *optional* 179 SVI_PSI_5, // Reserved 180 SVI_PSI_6, // Power down to 0V (voltage regulation disabled) 181 SVI_PSI_7, // Automated phase shedding and diode emulation 182 } SVI_PSI_e; 183 184 // Throttler Control/Status Bits 185 #define THROTTLER_TEMP_EDGE_BIT 0 186 #define THROTTLER_TEMP_HOTSPOT_BIT 1 187 #define THROTTLER_TEMP_HOTSPOT_G_BIT 2 188 #define THROTTLER_TEMP_HOTSPOT_M_BIT 3 189 #define THROTTLER_TEMP_MEM_BIT 4 190 #define THROTTLER_TEMP_VR_GFX_BIT 5 191 #define THROTTLER_TEMP_VR_MEM0_BIT 6 192 #define THROTTLER_TEMP_VR_MEM1_BIT 7 193 #define THROTTLER_TEMP_VR_SOC_BIT 8 194 #define THROTTLER_TEMP_VR_U_BIT 9 195 #define THROTTLER_TEMP_LIQUID0_BIT 10 196 #define THROTTLER_TEMP_LIQUID1_BIT 11 197 #define THROTTLER_TEMP_PLX_BIT 12 198 #define THROTTLER_TDC_GFX_BIT 13 199 #define THROTTLER_TDC_SOC_BIT 14 200 #define THROTTLER_TDC_U_BIT 15 201 #define THROTTLER_PPT0_BIT 16 202 #define THROTTLER_PPT1_BIT 17 203 #define THROTTLER_PPT2_BIT 18 204 #define THROTTLER_PPT3_BIT 19 205 #define THROTTLER_FIT_BIT 20 206 #define THROTTLER_GFX_APCC_PLUS_BIT 21 207 #define THROTTLER_COUNT 22 208 209 // FW DState Features Control Bits 210 #define FW_DSTATE_SOC_ULV_BIT 0 211 #define FW_DSTATE_G6_HSR_BIT 1 212 #define FW_DSTATE_G6_PHY_VMEMP_OFF_BIT 2 213 #define FW_DSTATE_SMN_DS_BIT 3 214 #define FW_DSTATE_MP1_WHISPER_MODE_BIT 4 215 #define FW_DSTATE_SOC_LIV_MIN_BIT 5 216 #define FW_DSTATE_SOC_PLL_PWRDN_BIT 6 217 #define FW_DSTATE_MEM_PLL_PWRDN_BIT 7 218 #define FW_DSTATE_MALL_ALLOC_BIT 8 219 #define FW_DSTATE_MEM_PSI_BIT 9 220 #define FW_DSTATE_HSR_NON_STROBE_BIT 10 221 #define FW_DSTATE_MP0_ENTER_WFI_BIT 11 222 #define FW_DSTATE_U_ULV_BIT 12 223 #define FW_DSTATE_MALL_FLUSH_BIT 13 224 #define FW_DSTATE_SOC_PSI_BIT 14 225 #define FW_DSTATE_U_PSI_BIT 15 226 #define FW_DSTATE_UCP_DS_BIT 16 227 #define FW_DSTATE_CSRCLK_DS_BIT 17 228 #define FW_DSTATE_MMHUB_INTERLOCK_BIT 18 229 #define FW_DSTATE_D0i3_2_QUIET_FW_BIT 19 230 #define FW_DSTATE_CLDO_PRG_BIT 20 231 #define FW_DSTATE_DF_PLL_PWRDN_BIT 21 232 #define FW_DSTATE_U_LOW_PWR_MODE_EN_BIT 22 233 #define FW_DSTATE_GFX_PSI6_BIT 23 234 #define FW_DSTATE_GFX_VR_PWR_STAGE_BIT 24 235 236 //LED Display Mask & Control Bits 237 #define LED_DISPLAY_GFX_DPM_BIT 0 238 #define LED_DISPLAY_PCIE_BIT 1 239 #define LED_DISPLAY_ERROR_BIT 2 240 241 242 #define MEM_TEMP_READ_OUT_OF_BAND_BIT 0 243 #define MEM_TEMP_READ_IN_BAND_REFRESH_BIT 1 244 #define MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT 2 245 246 typedef enum { 247 SMARTSHIFT_VERSION_1, 248 SMARTSHIFT_VERSION_2, 249 SMARTSHIFT_VERSION_3, 250 } SMARTSHIFT_VERSION_e; 251 252 typedef enum { 253 FOPT_CALC_AC_CALC_DC, 254 FOPT_PPTABLE_AC_CALC_DC, 255 FOPT_CALC_AC_PPTABLE_DC, 256 FOPT_PPTABLE_AC_PPTABLE_DC, 257 } FOPT_CALC_e; 258 259 typedef enum { 260 DRAM_BIT_WIDTH_DISABLED = 0, 261 DRAM_BIT_WIDTH_X_8 = 8, 262 DRAM_BIT_WIDTH_X_16 = 16, 263 DRAM_BIT_WIDTH_X_32 = 32, 264 DRAM_BIT_WIDTH_X_64 = 64, 265 DRAM_BIT_WIDTH_X_128 = 128, 266 DRAM_BIT_WIDTH_COUNT, 267 } DRAM_BIT_WIDTH_TYPE_e; 268 269 //I2C Interface 270 #define NUM_I2C_CONTROLLERS 8 271 272 #define I2C_CONTROLLER_ENABLED 1 273 #define I2C_CONTROLLER_DISABLED 0 274 275 #define MAX_SW_I2C_COMMANDS 24 276 277 typedef enum { 278 I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0 279 I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1 280 I2C_CONTROLLER_PORT_COUNT, 281 } I2cControllerPort_e; 282 283 typedef enum { 284 I2C_CONTROLLER_NAME_VR_GFX = 0, 285 I2C_CONTROLLER_NAME_VR_SOC, 286 I2C_CONTROLLER_NAME_VR_VMEMP, 287 I2C_CONTROLLER_NAME_VR_VDDIO, 288 I2C_CONTROLLER_NAME_LIQUID0, 289 I2C_CONTROLLER_NAME_LIQUID1, 290 I2C_CONTROLLER_NAME_PLX, 291 I2C_CONTROLLER_NAME_OTHER, 292 I2C_CONTROLLER_NAME_COUNT, 293 } I2cControllerName_e; 294 295 typedef enum { 296 I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 297 I2C_CONTROLLER_THROTTLER_VR_GFX, 298 I2C_CONTROLLER_THROTTLER_VR_SOC, 299 I2C_CONTROLLER_THROTTLER_VR_VMEMP, 300 I2C_CONTROLLER_THROTTLER_VR_VDDIO, 301 I2C_CONTROLLER_THROTTLER_LIQUID0, 302 I2C_CONTROLLER_THROTTLER_LIQUID1, 303 I2C_CONTROLLER_THROTTLER_PLX, 304 I2C_CONTROLLER_THROTTLER_INA3221, 305 I2C_CONTROLLER_THROTTLER_COUNT, 306 } I2cControllerThrottler_e; 307 308 typedef enum { 309 I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5, 310 I2C_CONTROLLER_PROTOCOL_VR_IR35217, 311 I2C_CONTROLLER_PROTOCOL_TMP_TMP102A, 312 I2C_CONTROLLER_PROTOCOL_INA3221, 313 I2C_CONTROLLER_PROTOCOL_COUNT, 314 } I2cControllerProtocol_e; 315 316 typedef struct { 317 uint8_t Enabled; 318 uint8_t Speed; 319 uint8_t SlaveAddress; 320 uint8_t ControllerPort; 321 uint8_t ControllerName; 322 uint8_t ThermalThrotter; 323 uint8_t I2cProtocol; 324 uint8_t PaddingConfig; 325 } I2cControllerConfig_t; 326 327 typedef enum { 328 I2C_PORT_SVD_SCL = 0, 329 I2C_PORT_GPIO, 330 } I2cPort_e; 331 332 typedef enum { 333 I2C_SPEED_FAST_50K = 0, //50 Kbits/s 334 I2C_SPEED_FAST_100K, //100 Kbits/s 335 I2C_SPEED_FAST_400K, //400 Kbits/s 336 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 337 I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 338 I2C_SPEED_HIGH_2M, //2.3 Mbits/s 339 I2C_SPEED_COUNT, 340 } I2cSpeed_e; 341 342 typedef enum { 343 I2C_CMD_READ = 0, 344 I2C_CMD_WRITE, 345 I2C_CMD_COUNT, 346 } I2cCmdType_e; 347 348 #define CMDCONFIG_STOP_BIT 0 349 #define CMDCONFIG_RESTART_BIT 1 350 #define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write 351 352 #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 353 #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 354 #define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT) 355 356 typedef struct { 357 uint8_t ReadWriteData; //Return data for read. Data to send for write 358 uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write 359 } SwI2cCmd_t; //SW I2C Command Table 360 361 typedef struct { 362 uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 363 uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select 364 uint8_t SlaveAddress; //Slave address of device 365 uint8_t NumCmds; //Number of commands 366 367 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 368 } SwI2cRequest_t; // SW I2C Request Table 369 370 typedef struct { 371 SwI2cRequest_t SwI2cRequest; 372 373 uint32_t Spare[8]; 374 uint32_t MmHubPadding[8]; // SMU internal use 375 } SwI2cRequestExternal_t; 376 377 typedef struct { 378 uint64_t mca_umc_status; 379 uint64_t mca_umc_addr; 380 381 uint16_t ce_count_lo_chip; 382 uint16_t ce_count_hi_chip; 383 384 uint32_t eccPadding; 385 } EccInfo_t; 386 387 typedef struct { 388 EccInfo_t EccInfo[24]; 389 } EccInfoTable_t; 390 391 //D3HOT sequences 392 typedef enum { 393 BACO_SEQUENCE, 394 MSR_SEQUENCE, 395 BAMACO_SEQUENCE, 396 ULPS_SEQUENCE, 397 D3HOT_SEQUENCE_COUNT, 398 } D3HOTSequence_e; 399 400 //This is aligned with RSMU PGFSM Register Mapping 401 typedef enum { 402 PG_DYNAMIC_MODE = 0, 403 PG_STATIC_MODE, 404 } PowerGatingMode_e; 405 406 //This is aligned with RSMU PGFSM Register Mapping 407 typedef enum { 408 PG_POWER_DOWN = 0, 409 PG_POWER_UP, 410 } PowerGatingSettings_e; 411 412 typedef struct { 413 uint32_t a; // store in IEEE float format in this variable 414 uint32_t b; // store in IEEE float format in this variable 415 uint32_t c; // store in IEEE float format in this variable 416 } QuadraticInt_t; 417 418 typedef struct { 419 uint32_t m; // store in IEEE float format in this variable 420 uint32_t b; // store in IEEE float format in this variable 421 } LinearInt_t; 422 423 typedef struct { 424 uint32_t a; // store in IEEE float format in this variable 425 uint32_t b; // store in IEEE float format in this variable 426 uint32_t c; // store in IEEE float format in this variable 427 } DroopInt_t; 428 429 typedef enum { 430 DCS_ARCH_DISABLED, 431 DCS_ARCH_FADCS, 432 DCS_ARCH_ASYNC, 433 } DCS_ARCH_e; 434 435 //Only Clks that have DPM descriptors are listed here 436 typedef enum { 437 PPCLK_GFXCLK = 0, 438 PPCLK_SOCCLK, 439 PPCLK_UCLK, 440 PPCLK_FCLK, 441 PPCLK_DCLK_0, 442 PPCLK_VCLK_0, 443 PPCLK_DCLK_1, 444 PPCLK_VCLK_1, 445 PPCLK_DISPCLK, 446 PPCLK_DPPCLK, 447 PPCLK_DPREFCLK, 448 PPCLK_DCFCLK, 449 PPCLK_DTBCLK, 450 PPCLK_COUNT, 451 } PPCLK_e; 452 453 typedef enum { 454 VOLTAGE_MODE_PPTABLE = 0, 455 VOLTAGE_MODE_FUSES, 456 VOLTAGE_MODE_COUNT, 457 } VOLTAGE_MODE_e; 458 459 460 typedef enum { 461 AVFS_VOLTAGE_GFX = 0, 462 AVFS_VOLTAGE_SOC, 463 AVFS_VOLTAGE_COUNT, 464 } AVFS_VOLTAGE_TYPE_e; 465 466 typedef enum { 467 AVFS_TEMP_COLD = 0, 468 AVFS_TEMP_HOT, 469 AVFS_TEMP_COUNT, 470 } AVFS_TEMP_e; 471 472 typedef enum { 473 AVFS_D_G, 474 AVFS_D_M_B, 475 AVFS_D_M_S, 476 AVFS_D_COUNT, 477 } AVFS_D_e; 478 479 typedef enum { 480 UCLK_DIV_BY_1 = 0, 481 UCLK_DIV_BY_2, 482 UCLK_DIV_BY_4, 483 UCLK_DIV_BY_8, 484 } UCLK_DIV_e; 485 486 typedef enum { 487 GPIO_INT_POLARITY_ACTIVE_LOW = 0, 488 GPIO_INT_POLARITY_ACTIVE_HIGH, 489 } GpioIntPolarity_e; 490 491 typedef enum { 492 PWR_CONFIG_TDP = 0, 493 PWR_CONFIG_TGP, 494 PWR_CONFIG_TCP_ESTIMATED, 495 PWR_CONFIG_TCP_MEASURED, 496 } PwrConfig_e; 497 498 typedef struct { 499 uint8_t Padding; 500 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 501 uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 502 uint8_t CalculateFopt; // Indication whether FW should calculate Fopt or use values below. Reference FOPT_CALC_e 503 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 504 uint32_t Padding3[3]; 505 uint16_t Padding4; 506 uint16_t FoptimalDc; //Foptimal frequency in DC power mode. 507 uint16_t FoptimalAc; //Foptimal frequency in AC power mode. 508 uint16_t Padding2; 509 } DpmDescriptor_t; 510 511 typedef enum { 512 PPT_THROTTLER_PPT0, 513 PPT_THROTTLER_PPT1, 514 PPT_THROTTLER_PPT2, 515 PPT_THROTTLER_PPT3, 516 PPT_THROTTLER_COUNT 517 } PPT_THROTTLER_e; 518 519 typedef enum { 520 TEMP_EDGE, 521 TEMP_HOTSPOT, 522 TEMP_HOTSPOT_G, 523 TEMP_HOTSPOT_M, 524 TEMP_MEM, 525 TEMP_VR_GFX, 526 TEMP_VR_MEM0, 527 TEMP_VR_MEM1, 528 TEMP_VR_SOC, 529 TEMP_VR_U, 530 TEMP_LIQUID0, 531 TEMP_LIQUID1, 532 TEMP_PLX, 533 TEMP_COUNT, 534 } TEMP_e; 535 536 typedef enum { 537 TDC_THROTTLER_GFX, 538 TDC_THROTTLER_SOC, 539 TDC_THROTTLER_U, 540 TDC_THROTTLER_COUNT 541 } TDC_THROTTLER_e; 542 543 typedef enum { 544 SVI_PLANE_GFX, 545 SVI_PLANE_SOC, 546 SVI_PLANE_VMEMP, 547 SVI_PLANE_VDDIO_MEM, 548 SVI_PLANE_U, 549 SVI_PLANE_COUNT, 550 } SVI_PLANE_e; 551 552 typedef enum { 553 PMFW_VOLT_PLANE_GFX, 554 PMFW_VOLT_PLANE_SOC, 555 PMFW_VOLT_PLANE_COUNT 556 } PMFW_VOLT_PLANE_e; 557 558 typedef enum { 559 CUSTOMER_VARIANT_ROW, 560 CUSTOMER_VARIANT_FALCON, 561 CUSTOMER_VARIANT_COUNT, 562 } CUSTOMER_VARIANT_e; 563 564 typedef enum { 565 POWER_SOURCE_AC, 566 POWER_SOURCE_DC, 567 POWER_SOURCE_COUNT, 568 } POWER_SOURCE_e; 569 570 typedef enum { 571 MEM_VENDOR_SAMSUNG, 572 MEM_VENDOR_INFINEON, 573 MEM_VENDOR_ELPIDA, 574 MEM_VENDOR_ETRON, 575 MEM_VENDOR_NANYA, 576 MEM_VENDOR_HYNIX, 577 MEM_VENDOR_MOSEL, 578 MEM_VENDOR_WINBOND, 579 MEM_VENDOR_ESMT, 580 MEM_VENDOR_PLACEHOLDER0, 581 MEM_VENDOR_PLACEHOLDER1, 582 MEM_VENDOR_PLACEHOLDER2, 583 MEM_VENDOR_PLACEHOLDER3, 584 MEM_VENDOR_PLACEHOLDER4, 585 MEM_VENDOR_PLACEHOLDER5, 586 MEM_VENDOR_MICRON, 587 MEM_VENDOR_COUNT, 588 } MEM_VENDOR_e; 589 590 typedef enum { 591 PP_GRTAVFS_HW_CPO_CTL_ZONE0, 592 PP_GRTAVFS_HW_CPO_CTL_ZONE1, 593 PP_GRTAVFS_HW_CPO_CTL_ZONE2, 594 PP_GRTAVFS_HW_CPO_CTL_ZONE3, 595 PP_GRTAVFS_HW_CPO_CTL_ZONE4, 596 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0, 597 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0, 598 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1, 599 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1, 600 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2, 601 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2, 602 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3, 603 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3, 604 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4, 605 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4, 606 PP_GRTAVFS_HW_ZONE0_VF, 607 PP_GRTAVFS_HW_ZONE1_VF1, 608 PP_GRTAVFS_HW_ZONE2_VF2, 609 PP_GRTAVFS_HW_ZONE3_VF3, 610 PP_GRTAVFS_HW_VOLTAGE_GB, 611 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0, 612 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1, 613 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2, 614 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3, 615 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4, 616 PP_GRTAVFS_HW_RESERVED_0, 617 PP_GRTAVFS_HW_RESERVED_1, 618 PP_GRTAVFS_HW_RESERVED_2, 619 PP_GRTAVFS_HW_RESERVED_3, 620 PP_GRTAVFS_HW_RESERVED_4, 621 PP_GRTAVFS_HW_RESERVED_5, 622 PP_GRTAVFS_HW_RESERVED_6, 623 PP_GRTAVFS_HW_FUSE_COUNT, 624 } PP_GRTAVFS_HW_FUSE_e; 625 626 typedef enum { 627 PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0, 628 PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0, 629 PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0, 630 PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0, 631 PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0, 632 PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0, 633 PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0, 634 PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0, 635 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0, 636 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1, 637 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2, 638 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3, 639 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4, 640 PP_GRTAVFS_FW_COMMON_FUSE_COUNT, 641 } PP_GRTAVFS_FW_COMMON_FUSE_e; 642 643 typedef enum { 644 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1, 645 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0, 646 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1, 647 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2, 648 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3, 649 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4, 650 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1, 651 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0, 652 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1, 653 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2, 654 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3, 655 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4, 656 PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY, 657 PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY, 658 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0, 659 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1, 660 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2, 661 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3, 662 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4, 663 PP_GRTAVFS_FW_SEP_FUSE_COUNT, 664 } PP_GRTAVFS_FW_SEP_FUSE_e; 665 666 #define PP_NUM_RTAVFS_PWL_ZONES 5 667 668 669 670 // VBIOS or PPLIB configures telemetry slope and offset. Only slope expected to be set for SVI3 671 // Slope Q1.7, Offset Q1.2 672 typedef struct { 673 int8_t Offset; // in Amps 674 uint8_t Padding; 675 uint16_t MaxCurrent; // in Amps 676 } SviTelemetryScale_t; 677 678 #define PP_NUM_OD_VF_CURVE_POINTS PP_NUM_RTAVFS_PWL_ZONES + 1 679 680 681 #define PP_OD_FEATURE_GFX_VF_CURVE_BIT 0 682 #define PP_OD_FEATURE_VMAX_BIT 1 683 #define PP_OD_FEATURE_PPT_BIT 2 684 #define PP_OD_FEATURE_FAN_CURVE_BIT 3 685 #define PP_OD_FEATURE_FREQ_DETER_BIT 4 686 #define PP_OD_FEATURE_FULL_CTRL_BIT 5 687 #define PP_OD_FEATURE_TDC_BIT 6 688 #define PP_OD_FEATURE_GFXCLK_BIT 7 689 #define PP_OD_FEATURE_UCLK_BIT 8 690 #define PP_OD_FEATURE_ZERO_FAN_BIT 9 691 #define PP_OD_FEATURE_TEMPERATURE_BIT 10 692 693 typedef enum { 694 PP_OD_POWER_FEATURE_ALWAYS_ENABLED, 695 PP_OD_POWER_FEATURE_DISABLED_WHILE_GAMING, 696 PP_OD_POWER_FEATURE_ALWAYS_DISABLED, 697 } PP_OD_POWER_FEATURE_e; 698 699 typedef struct { 700 uint32_t FeatureCtrlMask; 701 702 //Voltage control 703 int16_t VoltageOffsetPerZoneBoundary[PP_NUM_OD_VF_CURVE_POINTS]; 704 uint16_t VddGfxVmax; // in mV 705 706 uint8_t IdlePwrSavingFeaturesCtrl; 707 uint8_t RuntimePwrSavingFeaturesCtrl; 708 709 //Frequency changes 710 int16_t GfxclkFmin; // MHz 711 int16_t GfxclkFmax; // MHz 712 uint16_t UclkFmin; // MHz 713 uint16_t UclkFmax; // MHz 714 715 //PPT 716 int16_t Ppt; // % 717 int16_t Tdc; 718 719 //Fan control 720 uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS]; 721 uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS]; 722 uint16_t FanMinimumPwm; 723 uint16_t AcousticTargetRpmThreshold; 724 uint16_t AcousticLimitRpmThreshold; 725 uint16_t FanTargetTemperature; // Degree Celcius 726 uint8_t FanZeroRpmEnable; 727 uint8_t FanZeroRpmStopTemp; 728 uint8_t FanMode; 729 uint8_t MaxOpTemp; 730 uint8_t Padding[4]; 731 732 uint32_t Spare[12]; 733 uint32_t MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround 734 } OverDriveTable_t; 735 736 typedef struct { 737 OverDriveTable_t OverDriveTable; 738 739 } OverDriveTableExternal_t; 740 741 typedef struct { 742 uint32_t FeatureCtrlMask; 743 744 int16_t VoltageOffsetPerZoneBoundary; 745 uint16_t VddGfxVmax; // in mV 746 747 uint8_t IdlePwrSavingFeaturesCtrl; 748 uint8_t RuntimePwrSavingFeaturesCtrl; 749 750 uint16_t GfxclkFmin; // MHz 751 uint16_t GfxclkFmax; // MHz 752 uint16_t UclkFmin; // MHz 753 uint16_t UclkFmax; // MHz 754 755 //PPT 756 int16_t Ppt; // % 757 int16_t Tdc; 758 759 uint8_t FanLinearPwmPoints; 760 uint8_t FanLinearTempPoints; 761 uint16_t FanMinimumPwm; 762 uint16_t AcousticTargetRpmThreshold; 763 uint16_t AcousticLimitRpmThreshold; 764 uint16_t FanTargetTemperature; // Degree Celcius 765 uint8_t FanZeroRpmEnable; 766 uint8_t FanZeroRpmStopTemp; 767 uint8_t FanMode; 768 uint8_t MaxOpTemp; 769 uint8_t Padding[4]; 770 771 uint32_t Spare[12]; 772 773 } OverDriveLimits_t; 774 775 776 typedef enum { 777 BOARD_GPIO_SMUIO_0, 778 BOARD_GPIO_SMUIO_1, 779 BOARD_GPIO_SMUIO_2, 780 BOARD_GPIO_SMUIO_3, 781 BOARD_GPIO_SMUIO_4, 782 BOARD_GPIO_SMUIO_5, 783 BOARD_GPIO_SMUIO_6, 784 BOARD_GPIO_SMUIO_7, 785 BOARD_GPIO_SMUIO_8, 786 BOARD_GPIO_SMUIO_9, 787 BOARD_GPIO_SMUIO_10, 788 BOARD_GPIO_SMUIO_11, 789 BOARD_GPIO_SMUIO_12, 790 BOARD_GPIO_SMUIO_13, 791 BOARD_GPIO_SMUIO_14, 792 BOARD_GPIO_SMUIO_15, 793 BOARD_GPIO_SMUIO_16, 794 BOARD_GPIO_SMUIO_17, 795 BOARD_GPIO_SMUIO_18, 796 BOARD_GPIO_SMUIO_19, 797 BOARD_GPIO_SMUIO_20, 798 BOARD_GPIO_SMUIO_21, 799 BOARD_GPIO_SMUIO_22, 800 BOARD_GPIO_SMUIO_23, 801 BOARD_GPIO_SMUIO_24, 802 BOARD_GPIO_SMUIO_25, 803 BOARD_GPIO_SMUIO_26, 804 BOARD_GPIO_SMUIO_27, 805 BOARD_GPIO_SMUIO_28, 806 BOARD_GPIO_SMUIO_29, 807 BOARD_GPIO_SMUIO_30, 808 BOARD_GPIO_SMUIO_31, 809 MAX_BOARD_GPIO_SMUIO_NUM, 810 BOARD_GPIO_DC_GEN_A, 811 BOARD_GPIO_DC_GEN_B, 812 BOARD_GPIO_DC_GEN_C, 813 BOARD_GPIO_DC_GEN_D, 814 BOARD_GPIO_DC_GEN_E, 815 BOARD_GPIO_DC_GEN_F, 816 BOARD_GPIO_DC_GEN_G, 817 BOARD_GPIO_DC_GENLK_CLK, 818 BOARD_GPIO_DC_GENLK_VSYNC, 819 BOARD_GPIO_DC_SWAPLOCK_A, 820 BOARD_GPIO_DC_SWAPLOCK_B, 821 } BOARD_GPIO_TYPE_e; 822 823 #define INVALID_BOARD_GPIO 0xFF 824 825 826 typedef struct { 827 //PLL 0 828 uint16_t InitGfxclk_bypass; 829 uint16_t InitSocclk; 830 uint16_t InitMp0clk; 831 uint16_t InitMpioclk; 832 uint16_t InitSmnclk; 833 uint16_t InitUcpclk; 834 uint16_t InitCsrclk; 835 //PLL 1 836 837 uint16_t InitDprefclk; 838 uint16_t InitDcfclk; 839 uint16_t InitDtbclk; 840 //PLL 2 841 uint16_t InitDclk; //assume same DCLK/VCLK for both instances 842 uint16_t InitVclk; 843 // PLL 3 844 uint16_t InitUsbdfsclk; 845 uint16_t InitMp1clk; 846 uint16_t InitLclk; 847 uint16_t InitBaco400clk_bypass; 848 uint16_t InitBaco1200clk_bypass; 849 uint16_t InitBaco700clk_bypass; 850 // PLL 4 851 uint16_t InitFclk; 852 // PLL 5 853 uint16_t InitGfxclk_clkb; 854 855 //PLL 6 856 uint8_t InitUclkDPMState; // =0,1,2,3, frequency from FreqTableUclk 857 858 uint8_t Padding[3]; 859 860 uint32_t InitVcoFreqPll0; 861 uint32_t InitVcoFreqPll1; 862 uint32_t InitVcoFreqPll2; 863 uint32_t InitVcoFreqPll3; 864 uint32_t InitVcoFreqPll4; 865 uint32_t InitVcoFreqPll5; 866 uint32_t InitVcoFreqPll6; 867 868 //encoding will change depending on SVI2/SVI3 869 uint16_t InitGfx; // In mV(Q2) , should be 0? 870 uint16_t InitSoc; // In mV(Q2) 871 uint16_t InitU; // In Mv(Q2) not applicable 872 873 uint16_t Padding2; 874 875 uint32_t Spare[8]; 876 877 } BootValues_t; 878 879 880 typedef struct { 881 uint16_t Power[PPT_THROTTLER_COUNT][POWER_SOURCE_COUNT]; // Watts 882 uint16_t Tdc[TDC_THROTTLER_COUNT]; // Amps 883 884 uint16_t Temperature[TEMP_COUNT]; // Celsius 885 886 uint8_t PwmLimitMin; 887 uint8_t PwmLimitMax; 888 uint8_t FanTargetTemperature; 889 uint8_t Spare1[1]; 890 891 uint16_t AcousticTargetRpmThresholdMin; 892 uint16_t AcousticTargetRpmThresholdMax; 893 894 uint16_t AcousticLimitRpmThresholdMin; 895 uint16_t AcousticLimitRpmThresholdMax; 896 897 uint16_t PccLimitMin; 898 uint16_t PccLimitMax; 899 900 uint16_t FanStopTempMin; 901 uint16_t FanStopTempMax; 902 uint16_t FanStartTempMin; 903 uint16_t FanStartTempMax; 904 905 uint32_t Spare[12]; 906 907 } MsgLimits_t; 908 909 typedef struct { 910 uint16_t BaseClockAc; 911 uint16_t GameClockAc; 912 uint16_t BoostClockAc; 913 uint16_t BaseClockDc; 914 uint16_t GameClockDc; 915 uint16_t BoostClockDc; 916 917 uint32_t Reserved[4]; 918 } DriverReportedClocks_t; 919 920 typedef struct { 921 uint8_t DcBtcEnabled; 922 uint8_t Padding[3]; 923 924 uint16_t DcTol; // mV Q2 925 uint16_t DcBtcGb; // mV Q2 926 927 uint16_t DcBtcMin; // mV Q2 928 uint16_t DcBtcMax; // mV Q2 929 930 LinearInt_t DcBtcGbScalar; 931 932 } AvfsDcBtcParams_t; 933 934 typedef struct { 935 uint16_t AvfsTemp[AVFS_TEMP_COUNT]; //in degrees C 936 uint16_t VftFMin; // in MHz 937 uint16_t VInversion; // in mV Q2 938 QuadraticInt_t qVft[AVFS_TEMP_COUNT]; 939 QuadraticInt_t qAvfsGb; 940 QuadraticInt_t qAvfsGb2; 941 } AvfsFuseOverride_t; 942 943 typedef struct { 944 // SECTION: Version 945 946 uint32_t Version; // should be unique to each SKU(i.e if any value changes in below structure then this value must be different) 947 948 // SECTION: Feature Control 949 uint32_t FeaturesToRun[NUM_FEATURES / 32]; // Features that PMFW will attempt to enable. Use FEATURE_*_BIT as mapping 950 951 // SECTION: Miscellaneous Configuration 952 uint8_t TotalPowerConfig; // Determines how PMFW calculates the power. Use defines from PwrConfig_e 953 uint8_t CustomerVariant; //To specify if this PPTable is intended for a particular customer. Use defines from CUSTOMER_VARIANT_e 954 uint8_t MemoryTemperatureTypeMask; // Bit mapping indicating which methods of memory temperature reading are enabled. Use defines from MEM_TEMP_*BIT 955 uint8_t SmartShiftVersion; // Determine what SmartShift feature version is supported Use defines from SMARTSHIFT_VERSION_e 956 957 // SECTION: Infrastructure Limits 958 uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in AC mode. Multiple limits supported 959 uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in DC mode. Multiple limits supported 960 961 uint16_t SocketPowerLimitSmartShift2; // In Watts. Power limit used SmartShift 962 963 //if set to 1, SocketPowerLimitAc and SocketPowerLimitDc will be interpreted as legacy programs(i.e absolute power). If 0, all except index 0 will be scalars 964 //relative index 0 965 uint8_t EnableLegacyPptLimit; 966 uint8_t UseInputTelemetry; //applicable to SVI3 only and only to be set if VRs support 967 uint8_t SmartShiftMinReportedPptinDcs; //minimum possible active power consumption for this SKU. Used for SmartShift power reporting 968 969 uint8_t PaddingPpt[1]; 970 971 uint16_t VrTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with VR regulator maximum temperature 972 973 uint16_t PlatformTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with platform maximum temperature per VR current rail 974 975 uint16_t TemperatureLimit[TEMP_COUNT]; // In degrees Celsius. Temperature limit associated with each input 976 977 uint16_t HwCtfTempLimit; // In degrees Celsius. Temperature above which HW will trigger CTF. Consumed by VBIOS only 978 979 uint16_t PaddingInfra; 980 981 // Per year normalized Vmax state failure rates (sum of the two domains divided by life time in years) 982 uint32_t FitControllerFailureRateLimit; //in IEEE float 983 //Expected GFX Duty Cycle at Vmax. 984 uint32_t FitControllerGfxDutyCycle; // in IEEE float 985 //Expected SOC Duty Cycle at Vmax. 986 uint32_t FitControllerSocDutyCycle; // in IEEE float 987 988 //This offset will be deducted from the controller output to before it goes through the SOC Vset limiter block. 989 uint32_t FitControllerSocOffset; //in IEEE float 990 991 uint32_t GfxApccPlusResidencyLimit; // Percentage value. Used by APCC+ controller to control PCC residency to some value 992 993 // SECTION: Throttler settings 994 uint32_t ThrottlerControlMask; // See THROTTLER_*_BIT for mapping 995 996 // SECTION: FW DSTATE Settings 997 uint32_t FwDStateMask; // See FW_DSTATE_*_BIT for mapping 998 999 // SECTION: Voltage Control Parameters 1000 uint16_t UlvVoltageOffset[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2). ULV offset used in either GFX_ULV or SOC_ULV(part of FW_DSTATE) 1001 1002 uint16_t UlvVoltageOffsetU; // In mV(Q2). ULV offset used in either U_ULV(part of FW_DSTATE) 1003 uint16_t DeepUlvVoltageOffsetSoc; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC as part of FW_DSTATE 1004 1005 // Voltage Limits 1006 uint16_t DefaultMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage without FIT controller enabled 1007 uint16_t BoostMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage with FIT controller enabled 1008 1009 //Vmin Optimizations 1010 int16_t VminTempHystersis[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature hysteresis for switching between low/high temperature values for Vmin 1011 int16_t VminTempThreshold[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature threshold for switching between low/high temperature values for Vmin 1012 uint16_t Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at hot. 1013 uint16_t Vmin_Cold_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at cold. 1014 uint16_t Vmin_Hot_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at hot. 1015 uint16_t Vmin_Cold_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at cold. 1016 uint16_t Vmin_Aging_Offset[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Worst-case aging margin 1017 uint16_t Vmin_Plat_Offset_Hot[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Hot 1018 uint16_t Vmin_Plat_Offset_Cold[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Cold 1019 1020 //This is a fixed/minimum VMIN aging degradation offset which is applied at T0. This reflects the minimum amount of aging already accounted for. 1021 uint16_t VcBtcFixedVminAgingOffset[PMFW_VOLT_PLANE_COUNT]; 1022 //Linear offset or GB term to account for mis-correlation between PSM and Vmin shift trends across parts. 1023 uint16_t VcBtcVmin2PsmDegrationGb[PMFW_VOLT_PLANE_COUNT]; 1024 //Scalar coefficient of the PSM aging degradation function 1025 uint32_t VcBtcPsmA[PMFW_VOLT_PLANE_COUNT]; // A_PSM 1026 //Exponential coefficient of the PSM aging degradation function 1027 uint32_t VcBtcPsmB[PMFW_VOLT_PLANE_COUNT]; // B_PSM 1028 //Scalar coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 1029 uint32_t VcBtcVminA[PMFW_VOLT_PLANE_COUNT]; // A_VMIN 1030 //Exponential coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 1031 uint32_t VcBtcVminB[PMFW_VOLT_PLANE_COUNT]; // B_VMIN 1032 1033 uint8_t PerPartVminEnabled[PMFW_VOLT_PLANE_COUNT]; 1034 uint8_t VcBtcEnabled[PMFW_VOLT_PLANE_COUNT]; 1035 1036 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 1037 uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 1038 1039 QuadraticInt_t Vmin_droop; 1040 uint32_t SpareVmin[9]; 1041 1042 1043 //SECTION: DPM Configuration 1 1044 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 1045 1046 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1047 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1048 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1049 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1050 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1051 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1052 uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1053 uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1054 uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1055 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1056 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1057 1058 uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1059 1060 // SECTION: DPM Configuration 2 1061 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 1062 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 1063 1064 uint8_t GfxclkSpare[2]; 1065 uint16_t GfxclkFreqCap; 1066 1067 //GFX Idle Power Settings 1068 uint16_t GfxclkFgfxoffEntry; // in Mhz 1069 uint16_t GfxclkFgfxoffExitImu; // in Mhz 1070 uint16_t GfxclkFgfxoffExitRlc; // in Mhz 1071 uint16_t GfxclkThrottleClock; //Used primarily in DCS 1072 uint8_t EnableGfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages 1073 uint8_t GfxIdlePadding; 1074 1075 uint8_t SmsRepairWRCKClkDivEn; 1076 uint8_t SmsRepairWRCKClkDivVal; 1077 uint8_t GfxOffEntryEarlyMGCGEn; 1078 uint8_t GfxOffEntryForceCGCGEn; 1079 uint8_t GfxOffEntryForceCGCGDelayEn; 1080 uint8_t GfxOffEntryForceCGCGDelayVal; // in microseconds 1081 1082 uint16_t GfxclkFreqGfxUlv; // in MHz 1083 uint8_t GfxIdlePadding2[2]; 1084 1085 uint32_t GfxoffSpare[16]; 1086 1087 // GFX GPO 1088 uint32_t GfxGpoSpare[16]; 1089 1090 // GFX DCS 1091 1092 uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase 1093 uint16_t PaddingDcs; 1094 1095 uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase 1096 uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. 1097 1098 uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS. 1099 1100 uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. 1101 uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin. 1102 1103 1104 uint32_t DcsSpare[16]; 1105 1106 // UCLK section 1107 uint8_t UseStrobeModeOptimizations; //Set to indicate that FW should use strobe mode optimizations 1108 uint8_t PaddingMem[3]; 1109 1110 uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 1111 uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 1112 1113 uint16_t MemVmempVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1114 uint16_t MemVddioVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1115 1116 //FCLK Section 1117 1118 uint8_t FclkDpmUPstates[NUM_FCLK_DPM_LEVELS]; // U P-state ID associated with each FCLK DPM state. 1119 uint16_t FclkDpmVddU[NUM_FCLK_DPM_LEVELS]; // mV(Q2) Vset U voltage associated with each FCLK DPM state. 1120 uint16_t FclkDpmUSpeed[NUM_FCLK_DPM_LEVELS]; //U speed associated with each FCLK DPM state 1121 uint16_t FclkDpmDisallowPstateFreq; //Frequency which FW will target when indicated that display config cannot support P-state. Set to 0 use FW calculated value 1122 uint16_t PaddingFclk; 1123 1124 // Link DPM Settings 1125 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 1126 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 1127 uint16_t LclkFreq[NUM_LINK_LEVELS]; 1128 1129 // SECTION: Fan Control 1130 uint16_t FanStopTemp[TEMP_COUNT]; //Celsius 1131 uint16_t FanStartTemp[TEMP_COUNT]; //Celsius 1132 1133 uint16_t FanGain[TEMP_COUNT]; 1134 uint16_t FanGainPadding; 1135 1136 uint16_t FanPwmMin; 1137 uint16_t AcousticTargetRpmThreshold; 1138 uint16_t AcousticLimitRpmThreshold; 1139 uint16_t FanMaximumRpm; 1140 uint16_t MGpuAcousticLimitRpmThreshold; 1141 uint16_t FanTargetGfxclk; 1142 uint32_t TempInputSelectMask; 1143 uint8_t FanZeroRpmEnable; 1144 uint8_t FanTachEdgePerRev; 1145 uint16_t FanTargetTemperature[TEMP_COUNT]; 1146 1147 // The following are AFC override parameters. Leave at 0 to use FW defaults. 1148 int16_t FuzzyFan_ErrorSetDelta; 1149 int16_t FuzzyFan_ErrorRateSetDelta; 1150 int16_t FuzzyFan_PwmSetDelta; 1151 uint16_t FuzzyFan_Reserved; 1152 1153 uint16_t FwCtfLimit[TEMP_COUNT]; 1154 1155 uint16_t IntakeTempEnableRPM; 1156 int16_t IntakeTempOffsetTemp; 1157 uint16_t IntakeTempReleaseTemp; 1158 uint16_t IntakeTempHighIntakeAcousticLimit; 1159 uint16_t IntakeTempAcouticLimitReleaseRate; 1160 1161 uint16_t FanStalledTempLimitOffset; 1162 uint16_t FanStalledTriggerRpm; 1163 uint16_t FanAbnormalTriggerRpm; 1164 uint16_t FanPadding; 1165 1166 uint32_t FanSpare[14]; 1167 1168 // SECTION: VDD_GFX AVFS 1169 1170 uint8_t OverrideGfxAvfsFuses; 1171 uint8_t GfxAvfsPadding[3]; 1172 1173 uint32_t L2HwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; //see fusedoc for encoding 1174 uint32_t SeHwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; 1175 1176 uint32_t CommonRtAvfs[PP_GRTAVFS_FW_COMMON_FUSE_COUNT]; 1177 1178 uint32_t L2FwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1179 uint32_t SeFwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1180 1181 uint32_t Droop_PWL_F[PP_NUM_RTAVFS_PWL_ZONES]; 1182 uint32_t Droop_PWL_a[PP_NUM_RTAVFS_PWL_ZONES]; 1183 uint32_t Droop_PWL_b[PP_NUM_RTAVFS_PWL_ZONES]; 1184 uint32_t Droop_PWL_c[PP_NUM_RTAVFS_PWL_ZONES]; 1185 1186 uint32_t Static_PWL_Offset[PP_NUM_RTAVFS_PWL_ZONES]; 1187 1188 uint32_t dGbV_dT_vmin; 1189 uint32_t dGbV_dT_vmax; 1190 1191 //Unused: PMFW-9370 1192 uint32_t V2F_vmin_range_low; 1193 uint32_t V2F_vmin_range_high; 1194 uint32_t V2F_vmax_range_low; 1195 uint32_t V2F_vmax_range_high; 1196 1197 AvfsDcBtcParams_t DcBtcGfxParams; 1198 1199 uint32_t GfxAvfsSpare[32]; 1200 1201 //SECTION: VDD_SOC AVFS 1202 1203 uint8_t OverrideSocAvfsFuses; 1204 uint8_t MinSocAvfsRevision; 1205 uint8_t SocAvfsPadding[2]; 1206 1207 AvfsFuseOverride_t SocAvfsFuseOverride[AVFS_D_COUNT]; 1208 1209 DroopInt_t dBtcGbSoc[AVFS_D_COUNT]; // GHz->V BtcGb 1210 1211 LinearInt_t qAgingGb[AVFS_D_COUNT]; // GHz->V 1212 1213 QuadraticInt_t qStaticVoltageOffset[AVFS_D_COUNT]; // GHz->V 1214 1215 AvfsDcBtcParams_t DcBtcSocParams[AVFS_D_COUNT]; 1216 1217 uint32_t SocAvfsSpare[32]; 1218 1219 //SECTION: Boot clock and voltage values 1220 BootValues_t BootValues; 1221 1222 //SECTION: Driver Reported Clocks 1223 DriverReportedClocks_t DriverReportedClocks; 1224 1225 //SECTION: Message Limits 1226 MsgLimits_t MsgLimits; 1227 1228 //SECTION: OverDrive Limits 1229 OverDriveLimits_t OverDriveLimitsMin; 1230 OverDriveLimits_t OverDriveLimitsBasicMax; 1231 OverDriveLimits_t OverDriveLimitsAdvancedMax; 1232 1233 // SECTION: Advanced Options 1234 uint32_t DebugOverrides; 1235 1236 // SECTION: Sku Reserved 1237 uint32_t Spare[64]; 1238 1239 // Padding for MMHUB - do not modify this 1240 uint32_t MmHubPadding[8]; 1241 1242 } SkuTable_t; 1243 1244 typedef struct { 1245 // SECTION: Version 1246 uint32_t Version; //should be unique to each board type 1247 1248 1249 // SECTION: I2C Control 1250 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 1251 1252 // SECTION: SVI2 Board Parameters 1253 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 1254 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 1255 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 1256 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 1257 1258 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1259 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1260 uint8_t VmempUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1261 uint8_t VddioUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1262 1263 //SECTION SVI3 Board Parameters 1264 uint8_t SlaveAddrMapping[SVI_PLANE_COUNT]; 1265 uint8_t VrPsiSupport[SVI_PLANE_COUNT]; 1266 1267 uint8_t PaddingPsi[SVI_PLANE_COUNT]; 1268 uint8_t EnablePsi6[SVI_PLANE_COUNT]; // only applicable in SVI3 1269 1270 // SECTION: Voltage Regulator Settings 1271 SviTelemetryScale_t SviTelemetryScale[SVI_PLANE_COUNT]; 1272 uint32_t VoltageTelemetryRatio[SVI_PLANE_COUNT]; // This is used for VDDIO Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 1273 1274 uint8_t DownSlewRateVr[SVI_PLANE_COUNT]; 1275 1276 // SECTION: GPIO Settings 1277 1278 uint8_t LedOffGpio; 1279 uint8_t FanOffGpio; 1280 uint8_t GfxVrPowerStageOffGpio; 1281 1282 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 1283 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 1284 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 1285 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 1286 1287 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 1288 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 1289 1290 // LED Display Settings 1291 uint8_t LedPin0; // GPIO number for LedPin[0] 1292 uint8_t LedPin1; // GPIO number for LedPin[1] 1293 uint8_t LedPin2; // GPIO number for LedPin[2] 1294 uint8_t LedEnableMask; 1295 1296 uint8_t LedPcie; // GPIO number for PCIE results 1297 uint8_t LedError; // GPIO number for Error Cases 1298 1299 // SECTION: Clock Spread Spectrum 1300 1301 // UCLK Spread Spectrum 1302 uint16_t UclkSpreadPadding; 1303 uint16_t UclkSpreadFreq; // kHz 1304 1305 // UCLK Spread Spectrum 1306 uint8_t UclkSpreadPercent[MEM_VENDOR_COUNT]; 1307 1308 // FCLK Spread Spectrum 1309 uint8_t FclkSpreadPadding; 1310 uint8_t FclkSpreadPercent; // Q4.4 1311 uint16_t FclkSpreadFreq; // kHz 1312 1313 // Section: Memory Config 1314 uint8_t DramWidth; // Width of interface to the channel for each DRAM module. See DRAM_BIT_WIDTH_TYPE_e 1315 uint8_t PaddingMem1[3]; 1316 1317 // Section: Total Board Power 1318 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 1319 uint16_t BoardPowerPadding; 1320 1321 // SECTION: UMC feature flags 1322 uint8_t HsrEnabled; 1323 uint8_t VddqOffEnabled; 1324 uint8_t PaddingUmcFlags[2]; 1325 1326 uint32_t PostVoltageSetBacoDelay; // in microseconds. Amount of time FW will wait after power good is established or PSI0 command is issued 1327 uint32_t BacoEntryDelay; // in milliseconds. Amount of time FW will wait to trigger BACO entry after receiving entry notification from OS 1328 1329 // SECTION: Board Reserved 1330 uint32_t BoardSpare[64]; 1331 1332 // SECTION: Structure Padding 1333 1334 // Padding for MMHUB - do not modify this 1335 uint32_t MmHubPadding[8]; 1336 } BoardTable_t; 1337 1338 typedef struct { 1339 SkuTable_t SkuTable; 1340 BoardTable_t BoardTable; 1341 } PPTable_t; 1342 1343 typedef struct { 1344 // Time constant parameters for clock averages in ms 1345 uint16_t GfxclkAverageLpfTau; 1346 uint16_t FclkAverageLpfTau; 1347 uint16_t UclkAverageLpfTau; 1348 uint16_t GfxActivityLpfTau; 1349 uint16_t UclkActivityLpfTau; 1350 uint16_t SocketPowerLpfTau; 1351 uint16_t VcnClkAverageLpfTau; 1352 uint16_t VcnUsageAverageLpfTau; 1353 } DriverSmuConfig_t; 1354 1355 typedef struct { 1356 DriverSmuConfig_t DriverSmuConfig; 1357 1358 uint32_t Spare[8]; 1359 // Padding - ignore 1360 uint32_t MmHubPadding[8]; // SMU internal use 1361 } DriverSmuConfigExternal_t; 1362 1363 1364 typedef struct { 1365 1366 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1367 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1368 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1369 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1370 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1371 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1372 uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1373 uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1374 uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1375 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1376 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1377 1378 uint16_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1379 1380 uint16_t Padding; 1381 1382 uint32_t Spare[32]; 1383 1384 // Padding - ignore 1385 uint32_t MmHubPadding[8]; // SMU internal use 1386 1387 } DriverInfoTable_t; 1388 1389 typedef struct { 1390 uint32_t CurrClock[PPCLK_COUNT]; 1391 1392 uint16_t AverageGfxclkFrequencyTarget; 1393 uint16_t AverageGfxclkFrequencyPreDs; 1394 uint16_t AverageGfxclkFrequencyPostDs; 1395 uint16_t AverageFclkFrequencyPreDs; 1396 uint16_t AverageFclkFrequencyPostDs; 1397 uint16_t AverageMemclkFrequencyPreDs ; // this is scaled to actual memory clock 1398 uint16_t AverageMemclkFrequencyPostDs ; // this is scaled to actual memory clock 1399 uint16_t AverageVclk0Frequency ; 1400 uint16_t AverageDclk0Frequency ; 1401 uint16_t AverageVclk1Frequency ; 1402 uint16_t AverageDclk1Frequency ; 1403 uint16_t PCIeBusy ; 1404 uint16_t dGPU_W_MAX ; 1405 uint16_t padding ; 1406 1407 uint32_t MetricsCounter ; 1408 1409 uint16_t AvgVoltage[SVI_PLANE_COUNT]; 1410 uint16_t AvgCurrent[SVI_PLANE_COUNT]; 1411 1412 uint16_t AverageGfxActivity ; 1413 uint16_t AverageUclkActivity ; 1414 uint16_t Vcn0ActivityPercentage ; 1415 uint16_t Vcn1ActivityPercentage ; 1416 1417 uint32_t EnergyAccumulator; 1418 uint16_t AverageSocketPower ; 1419 uint16_t AvgTemperature[TEMP_COUNT]; 1420 1421 uint8_t PcieRate ; 1422 uint8_t PcieWidth ; 1423 1424 uint8_t AvgFanPwm; 1425 uint8_t Padding[1]; 1426 uint16_t AvgFanRpm; 1427 1428 1429 uint8_t ThrottlingPercentage[THROTTLER_COUNT]; 1430 1431 //metrics for D3hot entry/exit and driver ARM msgs 1432 uint32_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; 1433 uint32_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT]; 1434 uint32_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT]; 1435 1436 uint16_t ApuSTAPMSmartShiftLimit; 1437 uint16_t ApuSTAPMLimit; 1438 uint16_t AvgApuSocketPower; 1439 1440 uint16_t AverageUclkActivity_MAX; 1441 1442 uint32_t PublicSerialNumberLower; 1443 uint32_t PublicSerialNumberUpper; 1444 } SmuMetrics_t; 1445 1446 typedef struct { 1447 SmuMetrics_t SmuMetrics; 1448 uint32_t Spare[30]; 1449 1450 // Padding - ignore 1451 uint32_t MmHubPadding[8]; // SMU internal use 1452 } SmuMetricsExternal_t; 1453 1454 typedef struct { 1455 uint8_t WmSetting; 1456 uint8_t Flags; 1457 uint8_t Padding[2]; 1458 1459 } WatermarkRowGeneric_t; 1460 1461 #define NUM_WM_RANGES 4 1462 1463 typedef enum { 1464 WATERMARKS_CLOCK_RANGE = 0, 1465 WATERMARKS_DUMMY_PSTATE, 1466 WATERMARKS_MALL, 1467 WATERMARKS_COUNT, 1468 } WATERMARKS_FLAGS_e; 1469 1470 typedef struct { 1471 // Watermarks 1472 WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES]; 1473 } Watermarks_t; 1474 1475 typedef struct { 1476 Watermarks_t Watermarks; 1477 uint32_t Spare[16]; 1478 1479 uint32_t MmHubPadding[8]; // SMU internal use 1480 } WatermarksExternal_t; 1481 1482 typedef struct { 1483 uint16_t avgPsmCount[36]; 1484 uint16_t minPsmCount[36]; 1485 float avgPsmVoltage[36]; 1486 float minPsmVoltage[36]; 1487 } AvfsDebugTable_t; 1488 1489 typedef struct { 1490 AvfsDebugTable_t AvfsDebugTable; 1491 1492 uint32_t MmHubPadding[8]; // SMU internal use 1493 } AvfsDebugTableExternal_t; 1494 1495 1496 typedef struct { 1497 uint8_t Gfx_ActiveHystLimit; 1498 uint8_t Gfx_IdleHystLimit; 1499 uint8_t Gfx_FPS; 1500 uint8_t Gfx_MinActiveFreqType; 1501 uint8_t Gfx_BoosterFreqType; 1502 uint8_t PaddingGfx; 1503 uint16_t Gfx_MinActiveFreq; // MHz 1504 uint16_t Gfx_BoosterFreq; // MHz 1505 uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms 1506 uint32_t Gfx_PD_Data_limit_a; // Q16 1507 uint32_t Gfx_PD_Data_limit_b; // Q16 1508 uint32_t Gfx_PD_Data_limit_c; // Q16 1509 uint32_t Gfx_PD_Data_error_coeff; // Q16 1510 uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 1511 1512 uint8_t Fclk_ActiveHystLimit; 1513 uint8_t Fclk_IdleHystLimit; 1514 uint8_t Fclk_FPS; 1515 uint8_t Fclk_MinActiveFreqType; 1516 uint8_t Fclk_BoosterFreqType; 1517 uint8_t PaddingFclk; 1518 uint16_t Fclk_MinActiveFreq; // MHz 1519 uint16_t Fclk_BoosterFreq; // MHz 1520 uint16_t Fclk_PD_Data_time_constant; // Time constant of PD controller in ms 1521 uint32_t Fclk_PD_Data_limit_a; // Q16 1522 uint32_t Fclk_PD_Data_limit_b; // Q16 1523 uint32_t Fclk_PD_Data_limit_c; // Q16 1524 uint32_t Fclk_PD_Data_error_coeff; // Q16 1525 uint32_t Fclk_PD_Data_error_rate_coeff; // Q16 1526 1527 uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16 1528 uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS]; 1529 uint8_t Mem_DownHystLimit[NUM_UCLK_DPM_LEVELS]; 1530 uint16_t Mem_Fps; 1531 uint8_t padding[2]; 1532 1533 } DpmActivityMonitorCoeffInt_t; 1534 1535 1536 typedef struct { 1537 DpmActivityMonitorCoeffInt_t DpmActivityMonitorCoeffInt; 1538 uint32_t MmHubPadding[8]; // SMU internal use 1539 } DpmActivityMonitorCoeffIntExternal_t; 1540 1541 1542 1543 // Workload bits 1544 #define WORKLOAD_PPLIB_DEFAULT_BIT 0 1545 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 1546 #define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 1547 #define WORKLOAD_PPLIB_VIDEO_BIT 3 1548 #define WORKLOAD_PPLIB_VR_BIT 4 1549 #define WORKLOAD_PPLIB_COMPUTE_BIT 5 1550 #define WORKLOAD_PPLIB_CUSTOM_BIT 6 1551 #define WORKLOAD_PPLIB_WINDOW_3D_BIT 7 1552 #define WORKLOAD_PPLIB_COUNT 8 1553 1554 1555 // These defines are used with the following messages: 1556 // SMC_MSG_TransferTableDram2Smu 1557 // SMC_MSG_TransferTableSmu2Dram 1558 1559 // Table transfer status 1560 #define TABLE_TRANSFER_OK 0x0 1561 #define TABLE_TRANSFER_FAILED 0xFF 1562 #define TABLE_TRANSFER_PENDING 0xAB 1563 1564 // Table types 1565 #define TABLE_PPTABLE 0 1566 #define TABLE_COMBO_PPTABLE 1 1567 #define TABLE_WATERMARKS 2 1568 #define TABLE_AVFS_PSM_DEBUG 3 1569 #define TABLE_PMSTATUSLOG 4 1570 #define TABLE_SMU_METRICS 5 1571 #define TABLE_DRIVER_SMU_CONFIG 6 1572 #define TABLE_ACTIVITY_MONITOR_COEFF 7 1573 #define TABLE_OVERDRIVE 8 1574 #define TABLE_I2C_COMMANDS 9 1575 #define TABLE_DRIVER_INFO 10 1576 #define TABLE_ECCINFO 11 1577 #define TABLE_COUNT 12 1578 1579 //IH Interupt ID 1580 #define IH_INTERRUPT_ID_TO_DRIVER 0xFE 1581 #define IH_INTERRUPT_CONTEXT_ID_BACO 0x2 1582 #define IH_INTERRUPT_CONTEXT_ID_AC 0x3 1583 #define IH_INTERRUPT_CONTEXT_ID_DC 0x4 1584 #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 0x5 1585 #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 0x6 1586 #define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING 0x7 1587 1588 #endif 1589