1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef SMU13_DRIVER_IF_SMU_13_0_7_H 24 #define SMU13_DRIVER_IF_SMU_13_0_7_H 25 26 // *** IMPORTANT *** 27 // PMFW TEAM: Always increment the interface version on any change to this file 28 #define SMU13_DRIVER_IF_VERSION 0x28 29 30 //Increment this version if SkuTable_t or BoardTable_t change 31 #define PPTABLE_VERSION 0x1D 32 33 #define NUM_GFXCLK_DPM_LEVELS 16 34 #define NUM_SOCCLK_DPM_LEVELS 8 35 #define NUM_MP0CLK_DPM_LEVELS 2 36 #define NUM_DCLK_DPM_LEVELS 8 37 #define NUM_VCLK_DPM_LEVELS 8 38 #define NUM_DISPCLK_DPM_LEVELS 8 39 #define NUM_DPPCLK_DPM_LEVELS 8 40 #define NUM_DPREFCLK_DPM_LEVELS 8 41 #define NUM_DCFCLK_DPM_LEVELS 8 42 #define NUM_DTBCLK_DPM_LEVELS 8 43 #define NUM_UCLK_DPM_LEVELS 4 44 #define NUM_LINK_LEVELS 3 45 #define NUM_FCLK_DPM_LEVELS 8 46 #define NUM_OD_FAN_MAX_POINTS 6 47 48 // Feature Control Defines 49 #define FEATURE_FW_DATA_READ_BIT 0 50 #define FEATURE_DPM_GFXCLK_BIT 1 51 #define FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT 2 52 #define FEATURE_DPM_UCLK_BIT 3 53 #define FEATURE_DPM_FCLK_BIT 4 54 #define FEATURE_DPM_SOCCLK_BIT 5 55 #define FEATURE_DPM_MP0CLK_BIT 6 56 #define FEATURE_DPM_LINK_BIT 7 57 #define FEATURE_DPM_DCN_BIT 8 58 #define FEATURE_VMEMP_SCALING_BIT 9 59 #define FEATURE_VDDIO_MEM_SCALING_BIT 10 60 #define FEATURE_DS_GFXCLK_BIT 11 61 #define FEATURE_DS_SOCCLK_BIT 12 62 #define FEATURE_DS_FCLK_BIT 13 63 #define FEATURE_DS_LCLK_BIT 14 64 #define FEATURE_DS_DCFCLK_BIT 15 65 #define FEATURE_DS_UCLK_BIT 16 66 #define FEATURE_GFX_ULV_BIT 17 67 #define FEATURE_FW_DSTATE_BIT 18 68 #define FEATURE_GFXOFF_BIT 19 69 #define FEATURE_BACO_BIT 20 70 #define FEATURE_MM_DPM_BIT 21 71 #define FEATURE_SOC_MPCLK_DS_BIT 22 72 #define FEATURE_BACO_MPCLK_DS_BIT 23 73 #define FEATURE_THROTTLERS_BIT 24 74 #define FEATURE_SMARTSHIFT_BIT 25 75 #define FEATURE_GTHR_BIT 26 76 #define FEATURE_ACDC_BIT 27 77 #define FEATURE_VR0HOT_BIT 28 78 #define FEATURE_FW_CTF_BIT 29 79 #define FEATURE_FAN_CONTROL_BIT 30 80 #define FEATURE_GFX_DCS_BIT 31 81 #define FEATURE_GFX_READ_MARGIN_BIT 32 82 #define FEATURE_LED_DISPLAY_BIT 33 83 #define FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT 34 84 #define FEATURE_OUT_OF_BAND_MONITOR_BIT 35 85 #define FEATURE_OPTIMIZED_VMIN_BIT 36 86 #define FEATURE_GFX_IMU_BIT 37 87 #define FEATURE_BOOT_TIME_CAL_BIT 38 88 #define FEATURE_GFX_PCC_DFLL_BIT 39 89 #define FEATURE_SOC_CG_BIT 40 90 #define FEATURE_DF_CSTATE_BIT 41 91 #define FEATURE_GFX_EDC_BIT 42 92 #define FEATURE_BOOT_POWER_OPT_BIT 43 93 #define FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT 44 94 #define FEATURE_DS_VCN_BIT 45 95 #define FEATURE_BACO_CG_BIT 46 96 #define FEATURE_MEM_TEMP_READ_BIT 47 97 #define FEATURE_ATHUB_MMHUB_PG_BIT 48 98 #define FEATURE_SOC_PCC_BIT 49 99 #define FEATURE_SPARE_50_BIT 50 100 #define FEATURE_SPARE_51_BIT 51 101 #define FEATURE_SPARE_52_BIT 52 102 #define FEATURE_SPARE_53_BIT 53 103 #define FEATURE_SPARE_54_BIT 54 104 #define FEATURE_SPARE_55_BIT 55 105 #define FEATURE_SPARE_56_BIT 56 106 #define FEATURE_SPARE_57_BIT 57 107 #define FEATURE_SPARE_58_BIT 58 108 #define FEATURE_SPARE_59_BIT 59 109 #define FEATURE_SPARE_60_BIT 60 110 #define FEATURE_SPARE_61_BIT 61 111 #define FEATURE_SPARE_62_BIT 62 112 #define FEATURE_SPARE_63_BIT 63 113 #define NUM_FEATURES 64 114 115 //For use with feature control messages 116 typedef enum { 117 FEATURE_PWR_ALL, 118 FEATURE_PWR_S5, 119 FEATURE_PWR_BACO, 120 FEATURE_PWR_SOC, 121 FEATURE_PWR_GFX, 122 FEATURE_PWR_DOMAIN_COUNT, 123 } FEATURE_PWR_DOMAIN_e; 124 125 126 // Debug Overrides Bitmask 127 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000001 128 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK 0x00000002 129 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK 0x00000004 130 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK 0x00000008 131 #define DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x00000010 132 #define DEBUG_OVERRIDE_DISABLE_VCN_PG 0x00000020 133 #define DEBUG_OVERRIDE_DISABLE_FMAX_VMAX 0x00000040 134 #define DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS 0x00000080 135 #define DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK 0x00000100 136 #define DEBUG_OVERRIDE_DISABLE_DFLL 0x00000200 137 #define DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE 0x00000400 138 #define DEBUG_OVERRIDE_DFLL_MASTER_MODE 0x00000800 139 140 // VR Mapping Bit Defines 141 #define VR_MAPPING_VR_SELECT_MASK 0x01 142 #define VR_MAPPING_VR_SELECT_SHIFT 0x00 143 144 #define VR_MAPPING_PLANE_SELECT_MASK 0x02 145 #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 146 147 // PSI Bit Defines 148 #define PSI_SEL_VR0_PLANE0_PSI0 0x01 149 #define PSI_SEL_VR0_PLANE0_PSI1 0x02 150 #define PSI_SEL_VR0_PLANE1_PSI0 0x04 151 #define PSI_SEL_VR0_PLANE1_PSI1 0x08 152 #define PSI_SEL_VR1_PLANE0_PSI0 0x10 153 #define PSI_SEL_VR1_PLANE0_PSI1 0x20 154 #define PSI_SEL_VR1_PLANE1_PSI0 0x40 155 #define PSI_SEL_VR1_PLANE1_PSI1 0x80 156 157 typedef enum { 158 SVI_PSI_0, // Full phase count (default) 159 SVI_PSI_1, // Phase count 1st level 160 SVI_PSI_2, // Phase count 2nd level 161 SVI_PSI_3, // Single phase operation + active diode emulation 162 SVI_PSI_4, // Single phase operation + passive diode emulation *optional* 163 SVI_PSI_5, // Reserved 164 SVI_PSI_6, // Power down to 0V (voltage regulation disabled) 165 SVI_PSI_7, // Automated phase shedding and diode emulation 166 } SVI_PSI_e; 167 168 // Throttler Control/Status Bits 169 #define THROTTLER_TEMP_EDGE_BIT 0 170 #define THROTTLER_TEMP_HOTSPOT_BIT 1 171 #define THROTTLER_TEMP_HOTSPOT_G_BIT 2 172 #define THROTTLER_TEMP_HOTSPOT_M_BIT 3 173 #define THROTTLER_TEMP_MEM_BIT 4 174 #define THROTTLER_TEMP_VR_GFX_BIT 5 175 #define THROTTLER_TEMP_VR_MEM0_BIT 6 176 #define THROTTLER_TEMP_VR_MEM1_BIT 7 177 #define THROTTLER_TEMP_VR_SOC_BIT 8 178 #define THROTTLER_TEMP_VR_U_BIT 9 179 #define THROTTLER_TEMP_LIQUID0_BIT 10 180 #define THROTTLER_TEMP_LIQUID1_BIT 11 181 #define THROTTLER_TEMP_PLX_BIT 12 182 #define THROTTLER_TDC_GFX_BIT 13 183 #define THROTTLER_TDC_SOC_BIT 14 184 #define THROTTLER_TDC_U_BIT 15 185 #define THROTTLER_PPT0_BIT 16 186 #define THROTTLER_PPT1_BIT 17 187 #define THROTTLER_PPT2_BIT 18 188 #define THROTTLER_PPT3_BIT 19 189 #define THROTTLER_FIT_BIT 20 190 #define THROTTLER_GFX_APCC_PLUS_BIT 21 191 #define THROTTLER_COUNT 22 192 193 // FW DState Features Control Bits 194 #define FW_DSTATE_SOC_ULV_BIT 0 195 #define FW_DSTATE_G6_HSR_BIT 1 196 #define FW_DSTATE_G6_PHY_VMEMP_OFF_BIT 2 197 #define FW_DSTATE_SMN_DS_BIT 3 198 #define FW_DSTATE_MP1_WHISPER_MODE_BIT 4 199 #define FW_DSTATE_SOC_LIV_MIN_BIT 5 200 #define FW_DSTATE_SOC_PLL_PWRDN_BIT 6 201 #define FW_DSTATE_MEM_PLL_PWRDN_BIT 7 202 #define FW_DSTATE_MALL_ALLOC_BIT 8 203 #define FW_DSTATE_MEM_PSI_BIT 9 204 #define FW_DSTATE_HSR_NON_STROBE_BIT 10 205 #define FW_DSTATE_MP0_ENTER_WFI_BIT 11 206 #define FW_DSTATE_U_ULV_BIT 12 207 #define FW_DSTATE_MALL_FLUSH_BIT 13 208 #define FW_DSTATE_SOC_PSI_BIT 14 209 #define FW_DSTATE_U_PSI_BIT 15 210 #define FW_DSTATE_UCP_DS_BIT 16 211 #define FW_DSTATE_CSRCLK_DS_BIT 17 212 #define FW_DSTATE_MMHUB_INTERLOCK_BIT 18 213 #define FW_DSTATE_D0i3_2_QUIET_FW_BIT 19 214 #define FW_DSTATE_CLDO_PRG_BIT 20 215 #define FW_DSTATE_DF_PLL_PWRDN_BIT 21 216 #define FW_DSTATE_U_LOW_PWR_MODE_EN_BIT 22 217 #define FW_DSTATE_GFX_PSI6_BIT 23 218 #define FW_DSTATE_GFX_VR_PWR_STAGE_BIT 24 219 220 //LED Display Mask & Control Bits 221 #define LED_DISPLAY_GFX_DPM_BIT 0 222 #define LED_DISPLAY_PCIE_BIT 1 223 #define LED_DISPLAY_ERROR_BIT 2 224 225 226 #define MEM_TEMP_READ_OUT_OF_BAND_BIT 0 227 #define MEM_TEMP_READ_IN_BAND_REFRESH_BIT 1 228 #define MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT 2 229 230 typedef enum { 231 SMARTSHIFT_VERSION_1, 232 SMARTSHIFT_VERSION_2, 233 SMARTSHIFT_VERSION_3, 234 } SMARTSHIFT_VERSION_e; 235 236 typedef enum { 237 FOPT_CALC_AC_CALC_DC, 238 FOPT_PPTABLE_AC_CALC_DC, 239 FOPT_CALC_AC_PPTABLE_DC, 240 FOPT_PPTABLE_AC_PPTABLE_DC, 241 } FOPT_CALC_e; 242 243 typedef enum { 244 DRAM_BIT_WIDTH_DISABLED = 0, 245 DRAM_BIT_WIDTH_X_8 = 8, 246 DRAM_BIT_WIDTH_X_16 = 16, 247 DRAM_BIT_WIDTH_X_32 = 32, 248 DRAM_BIT_WIDTH_X_64 = 64, 249 DRAM_BIT_WIDTH_X_128 = 128, 250 DRAM_BIT_WIDTH_COUNT, 251 } DRAM_BIT_WIDTH_TYPE_e; 252 253 //I2C Interface 254 #define NUM_I2C_CONTROLLERS 8 255 256 #define I2C_CONTROLLER_ENABLED 1 257 #define I2C_CONTROLLER_DISABLED 0 258 259 #define MAX_SW_I2C_COMMANDS 24 260 261 typedef enum { 262 I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0 263 I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1 264 I2C_CONTROLLER_PORT_COUNT, 265 } I2cControllerPort_e; 266 267 typedef enum { 268 I2C_CONTROLLER_NAME_VR_GFX = 0, 269 I2C_CONTROLLER_NAME_VR_SOC, 270 I2C_CONTROLLER_NAME_VR_VMEMP, 271 I2C_CONTROLLER_NAME_VR_VDDIO, 272 I2C_CONTROLLER_NAME_LIQUID0, 273 I2C_CONTROLLER_NAME_LIQUID1, 274 I2C_CONTROLLER_NAME_PLX, 275 I2C_CONTROLLER_NAME_OTHER, 276 I2C_CONTROLLER_NAME_COUNT, 277 } I2cControllerName_e; 278 279 typedef enum { 280 I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 281 I2C_CONTROLLER_THROTTLER_VR_GFX, 282 I2C_CONTROLLER_THROTTLER_VR_SOC, 283 I2C_CONTROLLER_THROTTLER_VR_VMEMP, 284 I2C_CONTROLLER_THROTTLER_VR_VDDIO, 285 I2C_CONTROLLER_THROTTLER_LIQUID0, 286 I2C_CONTROLLER_THROTTLER_LIQUID1, 287 I2C_CONTROLLER_THROTTLER_PLX, 288 I2C_CONTROLLER_THROTTLER_INA3221, 289 I2C_CONTROLLER_THROTTLER_COUNT, 290 } I2cControllerThrottler_e; 291 292 typedef enum { 293 I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5, 294 I2C_CONTROLLER_PROTOCOL_VR_IR35217, 295 I2C_CONTROLLER_PROTOCOL_TMP_TMP102A, 296 I2C_CONTROLLER_PROTOCOL_INA3221, 297 I2C_CONTROLLER_PROTOCOL_COUNT, 298 } I2cControllerProtocol_e; 299 300 typedef struct { 301 uint8_t Enabled; 302 uint8_t Speed; 303 uint8_t SlaveAddress; 304 uint8_t ControllerPort; 305 uint8_t ControllerName; 306 uint8_t ThermalThrotter; 307 uint8_t I2cProtocol; 308 uint8_t PaddingConfig; 309 } I2cControllerConfig_t; 310 311 typedef enum { 312 I2C_PORT_SVD_SCL = 0, 313 I2C_PORT_GPIO, 314 } I2cPort_e; 315 316 typedef enum { 317 I2C_SPEED_FAST_50K = 0, //50 Kbits/s 318 I2C_SPEED_FAST_100K, //100 Kbits/s 319 I2C_SPEED_FAST_400K, //400 Kbits/s 320 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 321 I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 322 I2C_SPEED_HIGH_2M, //2.3 Mbits/s 323 I2C_SPEED_COUNT, 324 } I2cSpeed_e; 325 326 typedef enum { 327 I2C_CMD_READ = 0, 328 I2C_CMD_WRITE, 329 I2C_CMD_COUNT, 330 } I2cCmdType_e; 331 332 #define CMDCONFIG_STOP_BIT 0 333 #define CMDCONFIG_RESTART_BIT 1 334 #define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write 335 336 #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 337 #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 338 #define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT) 339 340 typedef struct { 341 uint8_t ReadWriteData; //Return data for read. Data to send for write 342 uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write 343 } SwI2cCmd_t; //SW I2C Command Table 344 345 typedef struct { 346 uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 347 uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select 348 uint8_t SlaveAddress; //Slave address of device 349 uint8_t NumCmds; //Number of commands 350 351 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 352 } SwI2cRequest_t; // SW I2C Request Table 353 354 typedef struct { 355 SwI2cRequest_t SwI2cRequest; 356 357 uint32_t Spare[8]; 358 uint32_t MmHubPadding[8]; // SMU internal use 359 } SwI2cRequestExternal_t; 360 361 typedef struct { 362 uint64_t mca_umc_status; 363 uint64_t mca_umc_addr; 364 365 uint16_t ce_count_lo_chip; 366 uint16_t ce_count_hi_chip; 367 368 uint32_t eccPadding; 369 } EccInfo_t; 370 371 typedef struct { 372 EccInfo_t EccInfo[24]; 373 } EccInfoTable_t; 374 375 //D3HOT sequences 376 typedef enum { 377 BACO_SEQUENCE, 378 MSR_SEQUENCE, 379 BAMACO_SEQUENCE, 380 ULPS_SEQUENCE, 381 D3HOT_SEQUENCE_COUNT, 382 } D3HOTSequence_e; 383 384 //This is aligned with RSMU PGFSM Register Mapping 385 typedef enum { 386 PG_DYNAMIC_MODE = 0, 387 PG_STATIC_MODE, 388 } PowerGatingMode_e; 389 390 //This is aligned with RSMU PGFSM Register Mapping 391 typedef enum { 392 PG_POWER_DOWN = 0, 393 PG_POWER_UP, 394 } PowerGatingSettings_e; 395 396 typedef struct { 397 uint32_t a; // store in IEEE float format in this variable 398 uint32_t b; // store in IEEE float format in this variable 399 uint32_t c; // store in IEEE float format in this variable 400 } QuadraticInt_t; 401 402 typedef struct { 403 uint32_t m; // store in IEEE float format in this variable 404 uint32_t b; // store in IEEE float format in this variable 405 } LinearInt_t; 406 407 typedef struct { 408 uint32_t a; // store in IEEE float format in this variable 409 uint32_t b; // store in IEEE float format in this variable 410 uint32_t c; // store in IEEE float format in this variable 411 } DroopInt_t; 412 413 typedef enum { 414 DCS_ARCH_DISABLED, 415 DCS_ARCH_FADCS, 416 DCS_ARCH_ASYNC, 417 } DCS_ARCH_e; 418 419 //Only Clks that have DPM descriptors are listed here 420 typedef enum { 421 PPCLK_GFXCLK = 0, 422 PPCLK_SOCCLK, 423 PPCLK_UCLK, 424 PPCLK_FCLK, 425 PPCLK_DCLK_0, 426 PPCLK_VCLK_0, 427 PPCLK_DCLK_1, 428 PPCLK_VCLK_1, 429 PPCLK_DISPCLK, 430 PPCLK_DPPCLK, 431 PPCLK_DPREFCLK, 432 PPCLK_DCFCLK, 433 PPCLK_DTBCLK, 434 PPCLK_COUNT, 435 } PPCLK_e; 436 437 typedef enum { 438 VOLTAGE_MODE_PPTABLE = 0, 439 VOLTAGE_MODE_FUSES, 440 VOLTAGE_MODE_COUNT, 441 } VOLTAGE_MODE_e; 442 443 444 typedef enum { 445 AVFS_VOLTAGE_GFX = 0, 446 AVFS_VOLTAGE_SOC, 447 AVFS_VOLTAGE_COUNT, 448 } AVFS_VOLTAGE_TYPE_e; 449 450 typedef enum { 451 AVFS_TEMP_COLD = 0, 452 AVFS_TEMP_HOT, 453 AVFS_TEMP_COUNT, 454 } AVFS_TEMP_e; 455 456 typedef enum { 457 AVFS_D_G, 458 AVFS_D_M_B, 459 AVFS_D_M_S, 460 AVFS_D_COUNT, 461 } AVFS_D_e; 462 463 typedef enum { 464 UCLK_DIV_BY_1 = 0, 465 UCLK_DIV_BY_2, 466 UCLK_DIV_BY_4, 467 UCLK_DIV_BY_8, 468 } UCLK_DIV_e; 469 470 typedef enum { 471 GPIO_INT_POLARITY_ACTIVE_LOW = 0, 472 GPIO_INT_POLARITY_ACTIVE_HIGH, 473 } GpioIntPolarity_e; 474 475 typedef enum { 476 PWR_CONFIG_TDP = 0, 477 PWR_CONFIG_TGP, 478 PWR_CONFIG_TCP_ESTIMATED, 479 PWR_CONFIG_TCP_MEASURED, 480 } PwrConfig_e; 481 482 typedef struct { 483 uint8_t Padding; 484 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 485 uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 486 uint8_t CalculateFopt; // Indication whether FW should calculate Fopt or use values below. Reference FOPT_CALC_e 487 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 488 uint32_t Padding3[3]; 489 uint16_t Padding4; 490 uint16_t FoptimalDc; //Foptimal frequency in DC power mode. 491 uint16_t FoptimalAc; //Foptimal frequency in AC power mode. 492 uint16_t Padding2; 493 } DpmDescriptor_t; 494 495 typedef enum { 496 PPT_THROTTLER_PPT0, 497 PPT_THROTTLER_PPT1, 498 PPT_THROTTLER_PPT2, 499 PPT_THROTTLER_PPT3, 500 PPT_THROTTLER_COUNT 501 } PPT_THROTTLER_e; 502 503 typedef enum { 504 TEMP_EDGE, 505 TEMP_HOTSPOT, 506 TEMP_HOTSPOT_G, 507 TEMP_HOTSPOT_M, 508 TEMP_MEM, 509 TEMP_VR_GFX, 510 TEMP_VR_MEM0, 511 TEMP_VR_MEM1, 512 TEMP_VR_SOC, 513 TEMP_VR_U, 514 TEMP_LIQUID0, 515 TEMP_LIQUID1, 516 TEMP_PLX, 517 TEMP_COUNT, 518 } TEMP_e; 519 520 typedef enum { 521 TDC_THROTTLER_GFX, 522 TDC_THROTTLER_SOC, 523 TDC_THROTTLER_U, 524 TDC_THROTTLER_COUNT 525 } TDC_THROTTLER_e; 526 527 typedef enum { 528 SVI_PLANE_GFX, 529 SVI_PLANE_SOC, 530 SVI_PLANE_VMEMP, 531 SVI_PLANE_VDDIO_MEM, 532 SVI_PLANE_U, 533 SVI_PLANE_COUNT, 534 } SVI_PLANE_e; 535 536 typedef enum { 537 PMFW_VOLT_PLANE_GFX, 538 PMFW_VOLT_PLANE_SOC, 539 PMFW_VOLT_PLANE_COUNT 540 } PMFW_VOLT_PLANE_e; 541 542 typedef enum { 543 CUSTOMER_VARIANT_ROW, 544 CUSTOMER_VARIANT_FALCON, 545 CUSTOMER_VARIANT_COUNT, 546 } CUSTOMER_VARIANT_e; 547 548 typedef enum { 549 POWER_SOURCE_AC, 550 POWER_SOURCE_DC, 551 POWER_SOURCE_COUNT, 552 } POWER_SOURCE_e; 553 554 typedef enum { 555 MEM_VENDOR_SAMSUNG, 556 MEM_VENDOR_INFINEON, 557 MEM_VENDOR_ELPIDA, 558 MEM_VENDOR_ETRON, 559 MEM_VENDOR_NANYA, 560 MEM_VENDOR_HYNIX, 561 MEM_VENDOR_MOSEL, 562 MEM_VENDOR_WINBOND, 563 MEM_VENDOR_ESMT, 564 MEM_VENDOR_PLACEHOLDER0, 565 MEM_VENDOR_PLACEHOLDER1, 566 MEM_VENDOR_PLACEHOLDER2, 567 MEM_VENDOR_PLACEHOLDER3, 568 MEM_VENDOR_PLACEHOLDER4, 569 MEM_VENDOR_PLACEHOLDER5, 570 MEM_VENDOR_MICRON, 571 MEM_VENDOR_COUNT, 572 } MEM_VENDOR_e; 573 574 typedef enum { 575 PP_GRTAVFS_HW_CPO_CTL_ZONE0, 576 PP_GRTAVFS_HW_CPO_CTL_ZONE1, 577 PP_GRTAVFS_HW_CPO_CTL_ZONE2, 578 PP_GRTAVFS_HW_CPO_CTL_ZONE3, 579 PP_GRTAVFS_HW_CPO_CTL_ZONE4, 580 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0, 581 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0, 582 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1, 583 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1, 584 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2, 585 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2, 586 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3, 587 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3, 588 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4, 589 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4, 590 PP_GRTAVFS_HW_ZONE0_VF, 591 PP_GRTAVFS_HW_ZONE1_VF1, 592 PP_GRTAVFS_HW_ZONE2_VF2, 593 PP_GRTAVFS_HW_ZONE3_VF3, 594 PP_GRTAVFS_HW_VOLTAGE_GB, 595 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0, 596 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1, 597 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2, 598 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3, 599 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4, 600 PP_GRTAVFS_HW_RESERVED_0, 601 PP_GRTAVFS_HW_RESERVED_1, 602 PP_GRTAVFS_HW_RESERVED_2, 603 PP_GRTAVFS_HW_RESERVED_3, 604 PP_GRTAVFS_HW_RESERVED_4, 605 PP_GRTAVFS_HW_RESERVED_5, 606 PP_GRTAVFS_HW_RESERVED_6, 607 PP_GRTAVFS_HW_FUSE_COUNT, 608 } PP_GRTAVFS_HW_FUSE_e; 609 610 typedef enum { 611 PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0, 612 PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0, 613 PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0, 614 PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0, 615 PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0, 616 PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0, 617 PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0, 618 PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0, 619 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0, 620 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1, 621 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2, 622 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3, 623 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4, 624 PP_GRTAVFS_FW_COMMON_FUSE_COUNT, 625 } PP_GRTAVFS_FW_COMMON_FUSE_e; 626 627 typedef enum { 628 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1, 629 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0, 630 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1, 631 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2, 632 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3, 633 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4, 634 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1, 635 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0, 636 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1, 637 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2, 638 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3, 639 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4, 640 PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY, 641 PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY, 642 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0, 643 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1, 644 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2, 645 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3, 646 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4, 647 PP_GRTAVFS_FW_SEP_FUSE_COUNT, 648 } PP_GRTAVFS_FW_SEP_FUSE_e; 649 650 #define PP_NUM_RTAVFS_PWL_ZONES 5 651 652 653 654 // VBIOS or PPLIB configures telemetry slope and offset. Only slope expected to be set for SVI3 655 // Slope Q1.7, Offset Q1.2 656 typedef struct { 657 int8_t Offset; // in Amps 658 uint8_t Padding; 659 uint16_t MaxCurrent; // in Amps 660 } SviTelemetryScale_t; 661 662 #define PP_NUM_OD_VF_CURVE_POINTS PP_NUM_RTAVFS_PWL_ZONES + 1 663 664 665 #define PP_OD_FEATURE_VF_CURVE_BIT 0 666 #define PP_OD_FEATURE_VMAX_BIT 1 667 #define PP_OD_FEATURE_PPT_BIT 2 668 #define PP_OD_FEATURE_FAN_CURVE_BIT 3 669 #define PP_OD_FEATURE_FREQ_DETER_BIT 4 670 #define PP_OD_FEATURE_FULL_CTRL_BIT 5 671 #define PP_OD_FEATURE_TDC_BIT 6 672 #define PP_OD_FEATURE_GFXCLK_BIT 7 673 #define PP_OD_FEATURE_UCLK_BIT 8 674 675 typedef enum { 676 PP_OD_POWER_FEATURE_ALWAYS_ENABLED, 677 PP_OD_POWER_FEATURE_DISABLED_WHILE_GAMING, 678 PP_OD_POWER_FEATURE_ALWAYS_DISABLED, 679 } PP_OD_POWER_FEATURE_e; 680 681 typedef struct { 682 uint32_t FeatureCtrlMask; 683 684 //Voltage control 685 int16_t VoltageOffsetPerZoneBoundary[PP_NUM_OD_VF_CURVE_POINTS]; 686 uint16_t VddGfxVmax; // in mV 687 688 uint8_t IdlePwrSavingFeaturesCtrl; 689 uint8_t RuntimePwrSavingFeaturesCtrl; 690 691 //Frequency changes 692 uint16_t GfxclkFmin; // MHz 693 uint16_t GfxclkFmax; // MHz 694 uint16_t UclkFmin; // MHz 695 uint16_t UclkFmax; // MHz 696 697 //PPT 698 int16_t Ppt; // % 699 int16_t Tdc; 700 701 //Fan control 702 uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS]; 703 uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS]; 704 uint16_t FanMaximumRpm; 705 uint16_t FanMinimumPwm; 706 uint16_t FanAcousticLimitRpm; 707 uint16_t FanTargetTemperature; // Degree Celcius 708 uint8_t FanZeroRpmEnable; 709 uint8_t FanZeroRpmStopTemp; 710 uint8_t FanMode; 711 uint8_t Padding[1]; 712 713 714 uint32_t Spare[13]; 715 uint32_t MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround 716 } OverDriveTable_t; 717 718 typedef struct { 719 OverDriveTable_t OverDriveTable; 720 721 } OverDriveTableExternal_t; 722 723 typedef struct { 724 uint32_t FeatureCtrlMask; 725 726 int16_t VoltageOffsetPerZoneBoundary; 727 uint16_t VddGfxVmax; // in mV 728 729 uint8_t IdlePwrSavingFeaturesCtrl; 730 uint8_t RuntimePwrSavingFeaturesCtrl; 731 732 uint16_t GfxclkFmin; // MHz 733 uint16_t GfxclkFmax; // MHz 734 uint16_t UclkFmin; // MHz 735 uint16_t UclkFmax; // MHz 736 737 //PPT 738 int16_t Ppt; // % 739 int16_t Tdc; 740 741 uint8_t FanLinearPwmPoints; 742 uint8_t FanLinearTempPoints; 743 uint16_t FanMaximumRpm; 744 uint16_t FanMinimumPwm; 745 uint16_t FanAcousticLimitRpm; 746 uint16_t FanTargetTemperature; // Degree Celcius 747 uint8_t FanZeroRpmEnable; 748 uint8_t FanZeroRpmStopTemp; 749 uint8_t FanMode; 750 uint8_t Padding[1]; 751 752 753 uint32_t Spare[13]; 754 755 } OverDriveLimits_t; 756 757 758 typedef enum { 759 BOARD_GPIO_SMUIO_0, 760 BOARD_GPIO_SMUIO_1, 761 BOARD_GPIO_SMUIO_2, 762 BOARD_GPIO_SMUIO_3, 763 BOARD_GPIO_SMUIO_4, 764 BOARD_GPIO_SMUIO_5, 765 BOARD_GPIO_SMUIO_6, 766 BOARD_GPIO_SMUIO_7, 767 BOARD_GPIO_SMUIO_8, 768 BOARD_GPIO_SMUIO_9, 769 BOARD_GPIO_SMUIO_10, 770 BOARD_GPIO_SMUIO_11, 771 BOARD_GPIO_SMUIO_12, 772 BOARD_GPIO_SMUIO_13, 773 BOARD_GPIO_SMUIO_14, 774 BOARD_GPIO_SMUIO_15, 775 BOARD_GPIO_SMUIO_16, 776 BOARD_GPIO_SMUIO_17, 777 BOARD_GPIO_SMUIO_18, 778 BOARD_GPIO_SMUIO_19, 779 BOARD_GPIO_SMUIO_20, 780 BOARD_GPIO_SMUIO_21, 781 BOARD_GPIO_SMUIO_22, 782 BOARD_GPIO_SMUIO_23, 783 BOARD_GPIO_SMUIO_24, 784 BOARD_GPIO_SMUIO_25, 785 BOARD_GPIO_SMUIO_26, 786 BOARD_GPIO_SMUIO_27, 787 BOARD_GPIO_SMUIO_28, 788 BOARD_GPIO_SMUIO_29, 789 BOARD_GPIO_SMUIO_30, 790 BOARD_GPIO_SMUIO_31, 791 MAX_BOARD_GPIO_SMUIO_NUM, 792 BOARD_GPIO_DC_GEN_A, 793 BOARD_GPIO_DC_GEN_B, 794 BOARD_GPIO_DC_GEN_C, 795 BOARD_GPIO_DC_GEN_D, 796 BOARD_GPIO_DC_GEN_E, 797 BOARD_GPIO_DC_GEN_F, 798 BOARD_GPIO_DC_GEN_G, 799 BOARD_GPIO_DC_GENLK_CLK, 800 BOARD_GPIO_DC_GENLK_VSYNC, 801 BOARD_GPIO_DC_SWAPLOCK_A, 802 BOARD_GPIO_DC_SWAPLOCK_B, 803 } BOARD_GPIO_TYPE_e; 804 805 #define INVALID_BOARD_GPIO 0xFF 806 807 808 typedef struct { 809 //PLL 0 810 uint16_t InitGfxclk_bypass; 811 uint16_t InitSocclk; 812 uint16_t InitMp0clk; 813 uint16_t InitMpioclk; 814 uint16_t InitSmnclk; 815 uint16_t InitUcpclk; 816 uint16_t InitCsrclk; 817 //PLL 1 818 819 uint16_t InitDprefclk; 820 uint16_t InitDcfclk; 821 uint16_t InitDtbclk; 822 //PLL 2 823 uint16_t InitDclk; //assume same DCLK/VCLK for both instances 824 uint16_t InitVclk; 825 // PLL 3 826 uint16_t InitUsbdfsclk; 827 uint16_t InitMp1clk; 828 uint16_t InitLclk; 829 uint16_t InitBaco400clk_bypass; 830 uint16_t InitBaco1200clk_bypass; 831 uint16_t InitBaco700clk_bypass; 832 // PLL 4 833 uint16_t InitFclk; 834 // PLL 5 835 uint16_t InitGfxclk_clkb; 836 837 //PLL 6 838 uint8_t InitUclkDPMState; // =0,1,2,3, frequency from FreqTableUclk 839 840 uint8_t Padding[3]; 841 842 uint32_t InitVcoFreqPll0; 843 uint32_t InitVcoFreqPll1; 844 uint32_t InitVcoFreqPll2; 845 uint32_t InitVcoFreqPll3; 846 uint32_t InitVcoFreqPll4; 847 uint32_t InitVcoFreqPll5; 848 uint32_t InitVcoFreqPll6; 849 850 //encoding will change depending on SVI2/SVI3 851 uint16_t InitGfx; // In mV(Q2) , should be 0? 852 uint16_t InitSoc; // In mV(Q2) 853 uint16_t InitU; // In Mv(Q2) not applicable 854 855 uint16_t Padding2; 856 857 uint32_t Spare[8]; 858 859 } BootValues_t; 860 861 862 typedef struct { 863 uint16_t Power[PPT_THROTTLER_COUNT][POWER_SOURCE_COUNT]; // Watts 864 uint16_t Tdc[TDC_THROTTLER_COUNT]; // Amps 865 866 uint16_t Temperature[TEMP_COUNT]; // Celsius 867 868 uint8_t PwmLimitMin; 869 uint8_t PwmLimitMax; 870 uint8_t FanTargetTemperature; 871 uint8_t Spare1[1]; 872 873 uint16_t AcousticTargetRpmThresholdMin; 874 uint16_t AcousticTargetRpmThresholdMax; 875 876 uint16_t AcousticLimitRpmThresholdMin; 877 uint16_t AcousticLimitRpmThresholdMax; 878 879 uint16_t PccLimitMin; 880 uint16_t PccLimitMax; 881 882 uint16_t FanStopTempMin; 883 uint16_t FanStopTempMax; 884 uint16_t FanStartTempMin; 885 uint16_t FanStartTempMax; 886 887 uint32_t Spare[12]; 888 889 } MsgLimits_t; 890 891 typedef struct { 892 uint16_t BaseClockAc; 893 uint16_t GameClockAc; 894 uint16_t BoostClockAc; 895 uint16_t BaseClockDc; 896 uint16_t GameClockDc; 897 uint16_t BoostClockDc; 898 899 uint32_t Reserved[4]; 900 } DriverReportedClocks_t; 901 902 typedef struct { 903 uint8_t DcBtcEnabled; 904 uint8_t Padding[3]; 905 906 uint16_t DcTol; // mV Q2 907 uint16_t DcBtcGb; // mV Q2 908 909 uint16_t DcBtcMin; // mV Q2 910 uint16_t DcBtcMax; // mV Q2 911 912 LinearInt_t DcBtcGbScalar; 913 914 } AvfsDcBtcParams_t; 915 916 typedef struct { 917 uint16_t AvfsTemp[AVFS_TEMP_COUNT]; //in degrees C 918 uint16_t VftFMin; // in MHz 919 uint16_t VInversion; // in mV Q2 920 QuadraticInt_t qVft[AVFS_TEMP_COUNT]; 921 QuadraticInt_t qAvfsGb; 922 QuadraticInt_t qAvfsGb2; 923 } AvfsFuseOverride_t; 924 925 typedef struct { 926 // SECTION: Version 927 928 uint32_t Version; // should be unique to each SKU(i.e if any value changes in below structure then this value must be different) 929 930 // SECTION: Feature Control 931 uint32_t FeaturesToRun[NUM_FEATURES / 32]; // Features that PMFW will attempt to enable. Use FEATURE_*_BIT as mapping 932 933 // SECTION: Miscellaneous Configuration 934 uint8_t TotalPowerConfig; // Determines how PMFW calculates the power. Use defines from PwrConfig_e 935 uint8_t CustomerVariant; //To specify if this PPTable is intended for a particular customer. Use defines from CUSTOMER_VARIANT_e 936 uint8_t MemoryTemperatureTypeMask; // Bit mapping indicating which methods of memory temperature reading are enabled. Use defines from MEM_TEMP_*BIT 937 uint8_t SmartShiftVersion; // Determine what SmartShift feature version is supported Use defines from SMARTSHIFT_VERSION_e 938 939 // SECTION: Infrastructure Limits 940 uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in AC mode. Multiple limits supported 941 uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in DC mode. Multiple limits supported 942 943 uint16_t SocketPowerLimitSmartShift2; // In Watts. Power limit used SmartShift 944 945 //if set to 1, SocketPowerLimitAc and SocketPowerLimitDc will be interpreted as legacy programs(i.e absolute power). If 0, all except index 0 will be scalars 946 //relative index 0 947 uint8_t EnableLegacyPptLimit; 948 uint8_t UseInputTelemetry; //applicable to SVI3 only and only to be set if VRs support 949 uint8_t SmartShiftMinReportedPptinDcs; //minimum possible active power consumption for this SKU. Used for SmartShift power reporting 950 951 uint8_t PaddingPpt[1]; 952 953 uint16_t VrTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with VR regulator maximum temperature 954 955 uint16_t PlatformTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with platform maximum temperature per VR current rail 956 957 uint16_t TemperatureLimit[TEMP_COUNT]; // In degrees Celsius. Temperature limit associated with each input 958 959 uint16_t HwCtfTempLimit; // In degrees Celsius. Temperature above which HW will trigger CTF. Consumed by VBIOS only 960 961 uint16_t PaddingInfra; 962 963 // Per year normalized Vmax state failure rates (sum of the two domains divided by life time in years) 964 uint32_t FitControllerFailureRateLimit; //in IEEE float 965 //Expected GFX Duty Cycle at Vmax. 966 uint32_t FitControllerGfxDutyCycle; // in IEEE float 967 //Expected SOC Duty Cycle at Vmax. 968 uint32_t FitControllerSocDutyCycle; // in IEEE float 969 970 //This offset will be deducted from the controller output to before it goes through the SOC Vset limiter block. 971 uint32_t FitControllerSocOffset; //in IEEE float 972 973 uint32_t GfxApccPlusResidencyLimit; // Percentage value. Used by APCC+ controller to control PCC residency to some value 974 975 // SECTION: Throttler settings 976 uint32_t ThrottlerControlMask; // See THROTTLER_*_BIT for mapping 977 978 // SECTION: FW DSTATE Settings 979 uint32_t FwDStateMask; // See FW_DSTATE_*_BIT for mapping 980 981 // SECTION: Voltage Control Parameters 982 uint16_t UlvVoltageOffset[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2). ULV offset used in either GFX_ULV or SOC_ULV(part of FW_DSTATE) 983 984 uint16_t UlvVoltageOffsetU; // In mV(Q2). ULV offset used in either U_ULV(part of FW_DSTATE) 985 uint16_t DeepUlvVoltageOffsetSoc; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC as part of FW_DSTATE 986 987 // Voltage Limits 988 uint16_t DefaultMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage without FIT controller enabled 989 uint16_t BoostMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage with FIT controller enabled 990 991 //Vmin Optimizations 992 int16_t VminTempHystersis[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature hysteresis for switching between low/high temperature values for Vmin 993 int16_t VminTempThreshold[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature threshold for switching between low/high temperature values for Vmin 994 uint16_t Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at hot. 995 uint16_t Vmin_Cold_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at cold. 996 uint16_t Vmin_Hot_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at hot. 997 uint16_t Vmin_Cold_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at cold. 998 uint16_t Vmin_Aging_Offset[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Worst-case aging margin 999 uint16_t Vmin_Plat_Offset_Hot[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Hot 1000 uint16_t Vmin_Plat_Offset_Cold[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Cold 1001 1002 //This is a fixed/minimum VMIN aging degradation offset which is applied at T0. This reflects the minimum amount of aging already accounted for. 1003 uint16_t VcBtcFixedVminAgingOffset[PMFW_VOLT_PLANE_COUNT]; 1004 //Linear offset or GB term to account for mis-correlation between PSM and Vmin shift trends across parts. 1005 uint16_t VcBtcVmin2PsmDegrationGb[PMFW_VOLT_PLANE_COUNT]; 1006 //Scalar coefficient of the PSM aging degradation function 1007 uint32_t VcBtcPsmA[PMFW_VOLT_PLANE_COUNT]; // A_PSM 1008 //Exponential coefficient of the PSM aging degradation function 1009 uint32_t VcBtcPsmB[PMFW_VOLT_PLANE_COUNT]; // B_PSM 1010 //Scalar coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 1011 uint32_t VcBtcVminA[PMFW_VOLT_PLANE_COUNT]; // A_VMIN 1012 //Exponential coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 1013 uint32_t VcBtcVminB[PMFW_VOLT_PLANE_COUNT]; // B_VMIN 1014 1015 uint8_t PerPartVminEnabled[PMFW_VOLT_PLANE_COUNT]; 1016 uint8_t VcBtcEnabled[PMFW_VOLT_PLANE_COUNT]; 1017 1018 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 1019 uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 1020 1021 uint32_t SpareVmin[12]; 1022 1023 1024 //SECTION: DPM Configuration 1 1025 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 1026 1027 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1028 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1029 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1030 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1031 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1032 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1033 uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1034 uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1035 uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1036 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1037 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1038 1039 uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1040 1041 // SECTION: DPM Configuration 2 1042 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 1043 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 1044 1045 uint8_t GfxclkSpare[2]; 1046 uint16_t GfxclkFreqCap; 1047 1048 //GFX Idle Power Settings 1049 uint16_t GfxclkFgfxoffEntry; // in Mhz 1050 uint16_t GfxclkFgfxoffExitImu; // in Mhz 1051 uint16_t GfxclkFgfxoffExitRlc; // in Mhz 1052 uint16_t GfxclkThrottleClock; //Used primarily in DCS 1053 uint8_t EnableGfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages 1054 uint8_t GfxIdlePadding; 1055 1056 uint8_t SmsRepairWRCKClkDivEn; 1057 uint8_t SmsRepairWRCKClkDivVal; 1058 uint8_t GfxOffEntryEarlyMGCGEn; 1059 uint8_t GfxOffEntryForceCGCGEn; 1060 uint8_t GfxOffEntryForceCGCGDelayEn; 1061 uint8_t GfxOffEntryForceCGCGDelayVal; // in microseconds 1062 1063 uint16_t GfxclkFreqGfxUlv; // in MHz 1064 uint8_t GfxIdlePadding2[2]; 1065 1066 uint32_t GfxoffSpare[16]; 1067 1068 // GFX GPO 1069 uint32_t GfxGpoSpare[16]; 1070 1071 // GFX DCS 1072 1073 uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase 1074 uint16_t PaddingDcs; 1075 1076 uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase 1077 uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. 1078 1079 uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS. 1080 1081 uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. 1082 uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin. 1083 1084 1085 uint32_t DcsSpare[16]; 1086 1087 // UCLK section 1088 uint8_t UseStrobeModeOptimizations; //Set to indicate that FW should use strobe mode optimizations 1089 uint8_t PaddingMem[3]; 1090 1091 uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 1092 uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 1093 1094 uint16_t MemVmempVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1095 uint16_t MemVddioVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1096 1097 //FCLK Section 1098 1099 uint8_t FclkDpmUPstates[NUM_FCLK_DPM_LEVELS]; // U P-state ID associated with each FCLK DPM state. 1100 uint16_t FclkDpmVddU[NUM_FCLK_DPM_LEVELS]; // mV(Q2) Vset U voltage associated with each FCLK DPM state. 1101 uint16_t FclkDpmUSpeed[NUM_FCLK_DPM_LEVELS]; //U speed associated with each FCLK DPM state 1102 uint16_t FclkDpmDisallowPstateFreq; //Frequency which FW will target when indicated that display config cannot support P-state. Set to 0 use FW calculated value 1103 uint16_t PaddingFclk; 1104 1105 // Link DPM Settings 1106 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 1107 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 1108 uint16_t LclkFreq[NUM_LINK_LEVELS]; 1109 1110 // SECTION: Fan Control 1111 uint16_t FanStopTemp[TEMP_COUNT]; //Celsius 1112 uint16_t FanStartTemp[TEMP_COUNT]; //Celsius 1113 1114 uint16_t FanGain[TEMP_COUNT]; 1115 uint16_t FanGainPadding; 1116 1117 uint16_t FanPwmMin; 1118 uint16_t AcousticTargetRpmThreshold; 1119 uint16_t AcousticLimitRpmThreshold; 1120 uint16_t FanMaximumRpm; 1121 uint16_t MGpuAcousticLimitRpmThreshold; 1122 uint16_t FanTargetGfxclk; 1123 uint32_t TempInputSelectMask; 1124 uint8_t FanZeroRpmEnable; 1125 uint8_t FanTachEdgePerRev; 1126 uint16_t FanTargetTemperature[TEMP_COUNT]; 1127 1128 // The following are AFC override parameters. Leave at 0 to use FW defaults. 1129 int16_t FuzzyFan_ErrorSetDelta; 1130 int16_t FuzzyFan_ErrorRateSetDelta; 1131 int16_t FuzzyFan_PwmSetDelta; 1132 uint16_t FuzzyFan_Reserved; 1133 1134 uint16_t FwCtfLimit[TEMP_COUNT]; 1135 1136 uint16_t IntakeTempEnableRPM; 1137 int16_t IntakeTempOffsetTemp; 1138 uint16_t IntakeTempReleaseTemp; 1139 uint16_t IntakeTempHighIntakeAcousticLimit; 1140 uint16_t IntakeTempAcouticLimitReleaseRate; 1141 1142 uint16_t FanStalledTempLimitOffset; 1143 uint16_t FanStalledTriggerRpm; 1144 uint16_t FanAbnormalTriggerRpm; 1145 uint16_t FanPadding; 1146 1147 uint32_t FanSpare[14]; 1148 1149 // SECTION: VDD_GFX AVFS 1150 1151 uint8_t OverrideGfxAvfsFuses; 1152 uint8_t GfxAvfsPadding[3]; 1153 1154 uint32_t L2HwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; //see fusedoc for encoding 1155 uint32_t SeHwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; 1156 1157 uint32_t CommonRtAvfs[PP_GRTAVFS_FW_COMMON_FUSE_COUNT]; 1158 1159 uint32_t L2FwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1160 uint32_t SeFwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1161 1162 uint32_t Droop_PWL_F[PP_NUM_RTAVFS_PWL_ZONES]; 1163 uint32_t Droop_PWL_a[PP_NUM_RTAVFS_PWL_ZONES]; 1164 uint32_t Droop_PWL_b[PP_NUM_RTAVFS_PWL_ZONES]; 1165 uint32_t Droop_PWL_c[PP_NUM_RTAVFS_PWL_ZONES]; 1166 1167 uint32_t Static_PWL_Offset[PP_NUM_RTAVFS_PWL_ZONES]; 1168 1169 uint32_t dGbV_dT_vmin; 1170 uint32_t dGbV_dT_vmax; 1171 1172 //Unused: PMFW-9370 1173 uint32_t V2F_vmin_range_low; 1174 uint32_t V2F_vmin_range_high; 1175 uint32_t V2F_vmax_range_low; 1176 uint32_t V2F_vmax_range_high; 1177 1178 AvfsDcBtcParams_t DcBtcGfxParams; 1179 1180 uint32_t GfxAvfsSpare[32]; 1181 1182 //SECTION: VDD_SOC AVFS 1183 1184 uint8_t OverrideSocAvfsFuses; 1185 uint8_t MinSocAvfsRevision; 1186 uint8_t SocAvfsPadding[2]; 1187 1188 AvfsFuseOverride_t SocAvfsFuseOverride[AVFS_D_COUNT]; 1189 1190 DroopInt_t dBtcGbSoc[AVFS_D_COUNT]; // GHz->V BtcGb 1191 1192 LinearInt_t qAgingGb[AVFS_D_COUNT]; // GHz->V 1193 1194 QuadraticInt_t qStaticVoltageOffset[AVFS_D_COUNT]; // GHz->V 1195 1196 AvfsDcBtcParams_t DcBtcSocParams[AVFS_D_COUNT]; 1197 1198 uint32_t SocAvfsSpare[32]; 1199 1200 //SECTION: Boot clock and voltage values 1201 BootValues_t BootValues; 1202 1203 //SECTION: Driver Reported Clocks 1204 DriverReportedClocks_t DriverReportedClocks; 1205 1206 //SECTION: Message Limits 1207 MsgLimits_t MsgLimits; 1208 1209 //SECTION: OverDrive Limits 1210 OverDriveLimits_t OverDriveLimitsMin; 1211 OverDriveLimits_t OverDriveLimitsBasicMax; 1212 OverDriveLimits_t OverDriveLimitsAdvancedMax; 1213 1214 // SECTION: Advanced Options 1215 uint32_t DebugOverrides; 1216 1217 // SECTION: Sku Reserved 1218 uint32_t Spare[64]; 1219 1220 // Padding for MMHUB - do not modify this 1221 uint32_t MmHubPadding[8]; 1222 1223 } SkuTable_t; 1224 1225 typedef struct { 1226 // SECTION: Version 1227 uint32_t Version; //should be unique to each board type 1228 1229 1230 // SECTION: I2C Control 1231 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 1232 1233 // SECTION: SVI2 Board Parameters 1234 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 1235 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 1236 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 1237 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 1238 1239 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1240 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1241 uint8_t VmempUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1242 uint8_t VddioUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1243 1244 //SECTION SVI3 Board Parameters 1245 uint8_t SlaveAddrMapping[SVI_PLANE_COUNT]; 1246 uint8_t VrPsiSupport[SVI_PLANE_COUNT]; 1247 1248 uint8_t PaddingPsi[SVI_PLANE_COUNT]; 1249 uint8_t EnablePsi6[SVI_PLANE_COUNT]; // only applicable in SVI3 1250 1251 // SECTION: Voltage Regulator Settings 1252 SviTelemetryScale_t SviTelemetryScale[SVI_PLANE_COUNT]; 1253 uint32_t VoltageTelemetryRatio[SVI_PLANE_COUNT]; // This is used for VDDIO Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 1254 1255 uint8_t DownSlewRateVr[SVI_PLANE_COUNT]; 1256 1257 // SECTION: GPIO Settings 1258 1259 uint8_t LedOffGpio; 1260 uint8_t FanOffGpio; 1261 uint8_t GfxVrPowerStageOffGpio; 1262 1263 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 1264 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 1265 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 1266 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 1267 1268 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 1269 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 1270 1271 // LED Display Settings 1272 uint8_t LedPin0; // GPIO number for LedPin[0] 1273 uint8_t LedPin1; // GPIO number for LedPin[1] 1274 uint8_t LedPin2; // GPIO number for LedPin[2] 1275 uint8_t LedEnableMask; 1276 1277 uint8_t LedPcie; // GPIO number for PCIE results 1278 uint8_t LedError; // GPIO number for Error Cases 1279 1280 // SECTION: Clock Spread Spectrum 1281 1282 // UCLK Spread Spectrum 1283 uint16_t UclkSpreadPadding; 1284 uint16_t UclkSpreadFreq; // kHz 1285 1286 // UCLK Spread Spectrum 1287 uint8_t UclkSpreadPercent[MEM_VENDOR_COUNT]; 1288 1289 // FCLK Spread Spectrum 1290 uint8_t FclkSpreadPadding; 1291 uint8_t FclkSpreadPercent; // Q4.4 1292 uint16_t FclkSpreadFreq; // kHz 1293 1294 // Section: Memory Config 1295 uint8_t DramWidth; // Width of interface to the channel for each DRAM module. See DRAM_BIT_WIDTH_TYPE_e 1296 uint8_t PaddingMem1[3]; 1297 1298 // Section: Total Board Power 1299 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 1300 uint16_t BoardPowerPadding; 1301 1302 // SECTION: UMC feature flags 1303 uint8_t HsrEnabled; 1304 uint8_t VddqOffEnabled; 1305 uint8_t PaddingUmcFlags[2]; 1306 1307 uint32_t PostVoltageSetBacoDelay; // in microseconds. Amount of time FW will wait after power good is established or PSI0 command is issued 1308 uint32_t BacoEntryDelay; // in milliseconds. Amount of time FW will wait to trigger BACO entry after receiving entry notification from OS 1309 1310 1311 // SECTION: Board Reserved 1312 uint32_t BoardSpare[64]; 1313 1314 // SECTION: Structure Padding 1315 1316 // Padding for MMHUB - do not modify this 1317 uint32_t MmHubPadding[8]; 1318 } BoardTable_t; 1319 1320 typedef struct { 1321 SkuTable_t SkuTable; 1322 BoardTable_t BoardTable; 1323 } PPTable_t; 1324 1325 typedef struct { 1326 // Time constant parameters for clock averages in ms 1327 uint16_t GfxclkAverageLpfTau; 1328 uint16_t FclkAverageLpfTau; 1329 uint16_t UclkAverageLpfTau; 1330 uint16_t GfxActivityLpfTau; 1331 uint16_t UclkActivityLpfTau; 1332 uint16_t SocketPowerLpfTau; 1333 uint16_t VcnClkAverageLpfTau; 1334 uint16_t VcnUsageAverageLpfTau; 1335 } DriverSmuConfig_t; 1336 1337 typedef struct { 1338 DriverSmuConfig_t DriverSmuConfig; 1339 1340 uint32_t Spare[8]; 1341 // Padding - ignore 1342 uint32_t MmHubPadding[8]; // SMU internal use 1343 } DriverSmuConfigExternal_t; 1344 1345 1346 typedef struct { 1347 1348 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1349 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1350 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1351 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1352 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1353 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1354 uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1355 uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1356 uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1357 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1358 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1359 1360 uint16_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1361 1362 uint16_t Padding; 1363 1364 uint32_t Spare[32]; 1365 1366 // Padding - ignore 1367 uint32_t MmHubPadding[8]; // SMU internal use 1368 1369 } DriverInfoTable_t; 1370 1371 typedef struct { 1372 uint32_t CurrClock[PPCLK_COUNT]; 1373 1374 uint16_t AverageGfxclkFrequencyTarget; 1375 uint16_t AverageGfxclkFrequencyPreDs; 1376 uint16_t AverageGfxclkFrequencyPostDs; 1377 uint16_t AverageFclkFrequencyPreDs; 1378 uint16_t AverageFclkFrequencyPostDs; 1379 uint16_t AverageMemclkFrequencyPreDs ; // this is scaled to actual memory clock 1380 uint16_t AverageMemclkFrequencyPostDs ; // this is scaled to actual memory clock 1381 uint16_t AverageVclk0Frequency ; 1382 uint16_t AverageDclk0Frequency ; 1383 uint16_t AverageVclk1Frequency ; 1384 uint16_t AverageDclk1Frequency ; 1385 1386 uint16_t AvgVoltage[SVI_PLANE_COUNT]; 1387 1388 uint16_t AverageGfxActivity ; 1389 uint16_t AverageUclkActivity ; 1390 uint16_t Vcn0ActivityPercentage ; 1391 uint16_t Vcn1ActivityPercentage ; 1392 1393 uint32_t EnergyAccumulator; 1394 uint16_t AverageSocketPower ; 1395 uint16_t AvgTemperature[TEMP_COUNT]; 1396 1397 uint8_t PcieRate ; 1398 uint8_t PcieWidth ; 1399 1400 uint8_t AvgFanPwm; 1401 uint8_t Padding[1]; 1402 uint16_t AvgFanRpm; 1403 1404 1405 uint8_t ThrottlingPercentage[THROTTLER_COUNT]; 1406 1407 //metrics for D3hot entry/exit and driver ARM msgs 1408 uint32_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; 1409 uint32_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT]; 1410 uint32_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT]; 1411 1412 uint16_t ApuSTAPMSmartShiftLimit; 1413 uint16_t ApuSTAPMLimit; 1414 uint16_t AvgApuSocketPower; 1415 1416 uint16_t AverageUclkActivity_MAX; 1417 1418 } SmuMetrics_t; 1419 1420 typedef struct { 1421 SmuMetrics_t SmuMetrics; 1422 uint32_t Spare[32]; 1423 1424 // Padding - ignore 1425 uint32_t MmHubPadding[8]; // SMU internal use 1426 } SmuMetricsExternal_t; 1427 1428 typedef struct { 1429 uint8_t WmSetting; 1430 uint8_t Flags; 1431 uint8_t Padding[2]; 1432 1433 } WatermarkRowGeneric_t; 1434 1435 #define NUM_WM_RANGES 4 1436 1437 typedef enum { 1438 WATERMARKS_CLOCK_RANGE = 0, 1439 WATERMARKS_DUMMY_PSTATE, 1440 WATERMARKS_MALL, 1441 WATERMARKS_COUNT, 1442 } WATERMARKS_FLAGS_e; 1443 1444 typedef struct { 1445 // Watermarks 1446 WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES]; 1447 } Watermarks_t; 1448 1449 typedef struct { 1450 Watermarks_t Watermarks; 1451 uint32_t Spare[16]; 1452 1453 uint32_t MmHubPadding[8]; // SMU internal use 1454 } WatermarksExternal_t; 1455 1456 typedef struct { 1457 uint16_t avgPsmCount[36]; 1458 uint16_t minPsmCount[36]; 1459 float avgPsmVoltage[36]; 1460 float minPsmVoltage[36]; 1461 } AvfsDebugTable_t; 1462 1463 typedef struct { 1464 AvfsDebugTable_t AvfsDebugTable; 1465 1466 uint32_t MmHubPadding[8]; // SMU internal use 1467 } AvfsDebugTableExternal_t; 1468 1469 1470 typedef struct { 1471 uint8_t Gfx_ActiveHystLimit; 1472 uint8_t Gfx_IdleHystLimit; 1473 uint8_t Gfx_FPS; 1474 uint8_t Gfx_MinActiveFreqType; 1475 uint8_t Gfx_BoosterFreqType; 1476 uint8_t PaddingGfx; 1477 uint16_t Gfx_MinActiveFreq; // MHz 1478 uint16_t Gfx_BoosterFreq; // MHz 1479 uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms 1480 uint32_t Gfx_PD_Data_limit_a; // Q16 1481 uint32_t Gfx_PD_Data_limit_b; // Q16 1482 uint32_t Gfx_PD_Data_limit_c; // Q16 1483 uint32_t Gfx_PD_Data_error_coeff; // Q16 1484 uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 1485 1486 uint8_t Fclk_ActiveHystLimit; 1487 uint8_t Fclk_IdleHystLimit; 1488 uint8_t Fclk_FPS; 1489 uint8_t Fclk_MinActiveFreqType; 1490 uint8_t Fclk_BoosterFreqType; 1491 uint8_t PaddingFclk; 1492 uint16_t Fclk_MinActiveFreq; // MHz 1493 uint16_t Fclk_BoosterFreq; // MHz 1494 uint16_t Fclk_PD_Data_time_constant; // Time constant of PD controller in ms 1495 uint32_t Fclk_PD_Data_limit_a; // Q16 1496 uint32_t Fclk_PD_Data_limit_b; // Q16 1497 uint32_t Fclk_PD_Data_limit_c; // Q16 1498 uint32_t Fclk_PD_Data_error_coeff; // Q16 1499 uint32_t Fclk_PD_Data_error_rate_coeff; // Q16 1500 1501 uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16 1502 uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS]; 1503 uint8_t Mem_DownHystLimit[NUM_UCLK_DPM_LEVELS]; 1504 uint16_t Mem_Fps; 1505 uint8_t padding[2]; 1506 1507 } DpmActivityMonitorCoeffInt_t; 1508 1509 1510 typedef struct { 1511 DpmActivityMonitorCoeffInt_t DpmActivityMonitorCoeffInt; 1512 uint32_t MmHubPadding[8]; // SMU internal use 1513 } DpmActivityMonitorCoeffIntExternal_t; 1514 1515 1516 1517 // Workload bits 1518 #define WORKLOAD_PPLIB_DEFAULT_BIT 0 1519 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 1520 #define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 1521 #define WORKLOAD_PPLIB_VIDEO_BIT 3 1522 #define WORKLOAD_PPLIB_VR_BIT 4 1523 #define WORKLOAD_PPLIB_COMPUTE_BIT 5 1524 #define WORKLOAD_PPLIB_CUSTOM_BIT 6 1525 #define WORKLOAD_PPLIB_WINDOW_3D_BIT 7 1526 #define WORKLOAD_PPLIB_COUNT 8 1527 1528 1529 // These defines are used with the following messages: 1530 // SMC_MSG_TransferTableDram2Smu 1531 // SMC_MSG_TransferTableSmu2Dram 1532 1533 // Table transfer status 1534 #define TABLE_TRANSFER_OK 0x0 1535 #define TABLE_TRANSFER_FAILED 0xFF 1536 #define TABLE_TRANSFER_PENDING 0xAB 1537 1538 // Table types 1539 #define TABLE_PPTABLE 0 1540 #define TABLE_COMBO_PPTABLE 1 1541 #define TABLE_WATERMARKS 2 1542 #define TABLE_AVFS_PSM_DEBUG 3 1543 #define TABLE_PMSTATUSLOG 4 1544 #define TABLE_SMU_METRICS 5 1545 #define TABLE_DRIVER_SMU_CONFIG 6 1546 #define TABLE_ACTIVITY_MONITOR_COEFF 7 1547 #define TABLE_OVERDRIVE 8 1548 #define TABLE_I2C_COMMANDS 9 1549 #define TABLE_DRIVER_INFO 10 1550 #define TABLE_ECCINFO 11 1551 #define TABLE_COUNT 12 1552 1553 //IH Interupt ID 1554 #define IH_INTERRUPT_ID_TO_DRIVER 0xFE 1555 #define IH_INTERRUPT_CONTEXT_ID_BACO 0x2 1556 #define IH_INTERRUPT_CONTEXT_ID_AC 0x3 1557 #define IH_INTERRUPT_CONTEXT_ID_DC 0x4 1558 #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 0x5 1559 #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 0x6 1560 #define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING 0x7 1561 1562 #endif 1563