1bd1b5799SLijo Lazar /* 2bd1b5799SLijo Lazar * Copyright 2021 Advanced Micro Devices, Inc. 3bd1b5799SLijo Lazar * 4bd1b5799SLijo Lazar * Permission is hereby granted, free of charge, to any person obtaining a 5bd1b5799SLijo Lazar * copy of this software and associated documentation files (the "Software"), 6bd1b5799SLijo Lazar * to deal in the Software without restriction, including without limitation 7bd1b5799SLijo Lazar * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8bd1b5799SLijo Lazar * and/or sell copies of the Software, and to permit persons to whom the 9bd1b5799SLijo Lazar * Software is furnished to do so, subject to the following conditions: 10bd1b5799SLijo Lazar * 11bd1b5799SLijo Lazar * The above copyright notice and this permission notice shall be included in 12bd1b5799SLijo Lazar * all copies or substantial portions of the Software. 13bd1b5799SLijo Lazar * 14bd1b5799SLijo Lazar * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15bd1b5799SLijo Lazar * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16bd1b5799SLijo Lazar * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17bd1b5799SLijo Lazar * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18bd1b5799SLijo Lazar * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19bd1b5799SLijo Lazar * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20bd1b5799SLijo Lazar * OTHER DEALINGS IN THE SOFTWARE. 21bd1b5799SLijo Lazar * 22bd1b5799SLijo Lazar */ 23bd1b5799SLijo Lazar #ifndef SMU_13_0_6_DRIVER_IF_H 24bd1b5799SLijo Lazar #define SMU_13_0_6_DRIVER_IF_H 25bd1b5799SLijo Lazar 26bd1b5799SLijo Lazar // *** IMPORTANT *** 27bd1b5799SLijo Lazar // PMFW TEAM: Always increment the interface version if 28bd1b5799SLijo Lazar // anything is changed in this file 29*023f4d60SLijo Lazar #define SMU13_0_6_DRIVER_IF_VERSION 0x08042024 30bd1b5799SLijo Lazar 31bd1b5799SLijo Lazar //I2C Interface 32bd1b5799SLijo Lazar #define NUM_I2C_CONTROLLERS 8 33bd1b5799SLijo Lazar #define I2C_CONTROLLER_ENABLED 1 34bd1b5799SLijo Lazar #define I2C_CONTROLLER_DISABLED 0 35bd1b5799SLijo Lazar 36bd1b5799SLijo Lazar #define MAX_SW_I2C_COMMANDS 24 37bd1b5799SLijo Lazar 38bd1b5799SLijo Lazar typedef enum { 39bd1b5799SLijo Lazar I2C_CONTROLLER_PORT_0, //CKSVII2C0 40bd1b5799SLijo Lazar I2C_CONTROLLER_PORT_1, //CKSVII2C1 41bd1b5799SLijo Lazar I2C_CONTROLLER_PORT_COUNT, 42bd1b5799SLijo Lazar } I2cControllerPort_e; 43bd1b5799SLijo Lazar 44bd1b5799SLijo Lazar typedef enum { 45bd1b5799SLijo Lazar UNSUPPORTED_1, //50 Kbits/s not supported anymore! 46bd1b5799SLijo Lazar I2C_SPEED_STANDARD_100K, //100 Kbits/s 47bd1b5799SLijo Lazar I2C_SPEED_FAST_400K, //400 Kbits/s 48bd1b5799SLijo Lazar I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 49bd1b5799SLijo Lazar UNSUPPORTED_2, //1 Mbits/s (in high speed mode) not supported anymore! 50bd1b5799SLijo Lazar UNSUPPORTED_3, //2.3 Mbits/s not supported anymore! 51bd1b5799SLijo Lazar I2C_SPEED_COUNT, 52bd1b5799SLijo Lazar } I2cSpeed_e; 53bd1b5799SLijo Lazar 54bd1b5799SLijo Lazar typedef enum { 55bd1b5799SLijo Lazar I2C_CMD_READ, 56bd1b5799SLijo Lazar I2C_CMD_WRITE, 57bd1b5799SLijo Lazar I2C_CMD_COUNT, 58bd1b5799SLijo Lazar } I2cCmdType_e; 59bd1b5799SLijo Lazar 60bd1b5799SLijo Lazar #define CMDCONFIG_STOP_BIT 0 61bd1b5799SLijo Lazar #define CMDCONFIG_RESTART_BIT 1 62bd1b5799SLijo Lazar #define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write 63bd1b5799SLijo Lazar 64bd1b5799SLijo Lazar #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 65bd1b5799SLijo Lazar #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 66bd1b5799SLijo Lazar #define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT) 67bd1b5799SLijo Lazar 68bd1b5799SLijo Lazar typedef struct { 69bd1b5799SLijo Lazar uint8_t ReadWriteData; //Return data for read. Data to send for write 70bd1b5799SLijo Lazar uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write 71bd1b5799SLijo Lazar } SwI2cCmd_t; //SW I2C Command Table 72bd1b5799SLijo Lazar 73bd1b5799SLijo Lazar typedef struct { 74bd1b5799SLijo Lazar uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 75bd1b5799SLijo Lazar uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select 76bd1b5799SLijo Lazar uint8_t SlaveAddress; //Slave address of device 77bd1b5799SLijo Lazar uint8_t NumCmds; //Number of commands 78bd1b5799SLijo Lazar SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 79bd1b5799SLijo Lazar } SwI2cRequest_t; // SW I2C Request Table 80bd1b5799SLijo Lazar 81bd1b5799SLijo Lazar typedef struct { 82bd1b5799SLijo Lazar SwI2cRequest_t SwI2cRequest; 83bd1b5799SLijo Lazar uint32_t Spare[8]; 84bd1b5799SLijo Lazar uint32_t MmHubPadding[8]; // SMU internal use 85bd1b5799SLijo Lazar } SwI2cRequestExternal_t; 86bd1b5799SLijo Lazar 87bd1b5799SLijo Lazar typedef enum { 88bd1b5799SLijo Lazar PPCLK_VCLK, 89bd1b5799SLijo Lazar PPCLK_DCLK, 90bd1b5799SLijo Lazar PPCLK_SOCCLK, 91bd1b5799SLijo Lazar PPCLK_UCLK, 92bd1b5799SLijo Lazar PPCLK_FCLK, 93bd1b5799SLijo Lazar PPCLK_LCLK, 94bd1b5799SLijo Lazar PPCLK_COUNT, 95bd1b5799SLijo Lazar } PPCLK_e; 96bd1b5799SLijo Lazar 97bd1b5799SLijo Lazar typedef enum { 98bd1b5799SLijo Lazar GPIO_INT_POLARITY_ACTIVE_LOW, 99bd1b5799SLijo Lazar GPIO_INT_POLARITY_ACTIVE_HIGH, 100bd1b5799SLijo Lazar } GpioIntPolarity_e; 101bd1b5799SLijo Lazar 102bd1b5799SLijo Lazar //TODO confirm if this is used in SMU_13_0_6 PPSMC_MSG_SetUclkDpmMode 103bd1b5799SLijo Lazar typedef enum { 104bd1b5799SLijo Lazar UCLK_DPM_MODE_BANDWIDTH, 105bd1b5799SLijo Lazar UCLK_DPM_MODE_LATENCY, 106bd1b5799SLijo Lazar } UCLK_DPM_MODE_e; 107bd1b5799SLijo Lazar 108bd1b5799SLijo Lazar typedef struct { 1098d1c1bc1SAsad kamal //0-23 SOC, 24-26 SOCIO, 27-29 SOC 110bd1b5799SLijo Lazar uint16_t avgPsmCount[30]; 111bd1b5799SLijo Lazar uint16_t minPsmCount[30]; 112bd1b5799SLijo Lazar float avgPsmVoltage[30]; 113bd1b5799SLijo Lazar float minPsmVoltage[30]; 114bd1b5799SLijo Lazar } AvfsDebugTableAid_t; 115bd1b5799SLijo Lazar 116bd1b5799SLijo Lazar typedef struct { 117bd1b5799SLijo Lazar //0-27 GFX, 28-29 SOC 118bd1b5799SLijo Lazar uint16_t avgPsmCount[30]; 119bd1b5799SLijo Lazar uint16_t minPsmCount[30]; 120bd1b5799SLijo Lazar float avgPsmVoltage[30]; 121bd1b5799SLijo Lazar float minPsmVoltage[30]; 122bd1b5799SLijo Lazar } AvfsDebugTableXcd_t; 123bd1b5799SLijo Lazar 1246d5f5eafSAsad kamal // Defines used for IH-based thermal interrupts to GFX driver - A/X only 1256d5f5eafSAsad kamal #define IH_INTERRUPT_ID_TO_DRIVER 0xFE 1266d5f5eafSAsad kamal #define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING 0x7 1276d5f5eafSAsad kamal 128*023f4d60SLijo Lazar //thermal over-temp mask defines for IH interrupt to host 129*023f4d60SLijo Lazar #define THROTTLER_PROCHOT_BIT 0 130*023f4d60SLijo Lazar #define THROTTLER_PPT_BIT 1 131*023f4d60SLijo Lazar #define THROTTLER_THERMAL_SOCKET_BIT 2//AID, XCD, CCD throttling 132*023f4d60SLijo Lazar #define THROTTLER_THERMAL_VR_BIT 3//VRHOT 133*023f4d60SLijo Lazar #define THROTTLER_THERMAL_HBM_BIT 4 134*023f4d60SLijo Lazar 135*023f4d60SLijo Lazar // These defines are used with the following messages: 136*023f4d60SLijo Lazar // SMC_MSG_TransferTableDram2Smu 137*023f4d60SLijo Lazar // SMC_MSG_TransferTableSmu2Dram 138*023f4d60SLijo Lazar // #define TABLE_PPTABLE 0 139*023f4d60SLijo Lazar // #define TABLE_AVFS_PSM_DEBUG 1 140*023f4d60SLijo Lazar // #define TABLE_AVFS_FUSE_OVERRIDE 2 141*023f4d60SLijo Lazar // #define TABLE_PMSTATUSLOG 3 142*023f4d60SLijo Lazar // #define TABLE_SMU_METRICS 4 143*023f4d60SLijo Lazar // #define TABLE_DRIVER_SMU_CONFIG 5 144*023f4d60SLijo Lazar // #define TABLE_I2C_COMMANDS 6 145*023f4d60SLijo Lazar // #define TABLE_COUNT 7 146*023f4d60SLijo Lazar 147*023f4d60SLijo Lazar // // Table transfer status 148*023f4d60SLijo Lazar // #define TABLE_TRANSFER_OK 0x0 149*023f4d60SLijo Lazar // #define TABLE_TRANSFER_FAILED 0xFF 150*023f4d60SLijo Lazar // #define TABLE_TRANSFER_PENDING 0xAB 1516d5f5eafSAsad kamal 152bd1b5799SLijo Lazar #endif 153