1 /*
2  * Copyright 2020 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #ifndef __SMU13_DRIVER_IF_V13_0_5_H__
24 #define __SMU13_DRIVER_IF_V13_0_5_H__
25 
26 #define SMU13_0_5_DRIVER_IF_VERSION 5
27 
28 // Throttler Status Bitmask
29 #define THROTTLER_STATUS_BIT_SPL            0
30 #define THROTTLER_STATUS_BIT_FPPT           1
31 #define THROTTLER_STATUS_BIT_SPPT           2
32 #define THROTTLER_STATUS_BIT_SPPT_APU       3
33 #define THROTTLER_STATUS_BIT_THM_CORE       4
34 #define THROTTLER_STATUS_BIT_THM_GFX        5
35 #define THROTTLER_STATUS_BIT_THM_SOC        6
36 #define THROTTLER_STATUS_BIT_TDC_VDD        7
37 #define THROTTLER_STATUS_BIT_TDC_SOC        8
38 #define THROTTLER_STATUS_BIT_PROCHOT_CPU    9
39 #define THROTTLER_STATUS_BIT_PROCHOT_GFX   10
40 #define THROTTLER_STATUS_BIT_EDC_CPU       11
41 #define THROTTLER_STATUS_BIT_EDC_GFX       12
42 
43 #define NUM_DCFCLK_DPM_LEVELS   4
44 #define NUM_DISPCLK_DPM_LEVELS  4
45 #define NUM_DPPCLK_DPM_LEVELS   4
46 #define NUM_SOCCLK_DPM_LEVELS   4
47 #define NUM_VCN_DPM_LEVELS      4
48 #define NUM_SOC_VOLTAGE_LEVELS  4
49 #define NUM_DF_PSTATE_LEVELS    4
50 
51 typedef struct {
52   uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
53   uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
54   uint16_t MinMclk;
55   uint16_t MaxMclk;
56   uint8_t  WmSetting;
57   uint8_t  WmType;  // Used for normal pstate change or memory retraining
58   uint8_t  Padding[2];
59 } WatermarkRowGeneric_t;
60 
61 #define NUM_WM_RANGES 4
62 #define WM_PSTATE_CHG 0
63 #define WM_RETRAINING 1
64 
65 typedef enum {
66   WM_SOCCLK = 0,
67   WM_DCFCLK,
68   WM_COUNT,
69 } WM_CLOCK_e;
70 
71 typedef struct {
72   // Watermarks
73   WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
74   uint32_t MmHubPadding[7]; // SMU internal use
75 } Watermarks_t;
76 
77 typedef struct {
78   uint32_t FClk;
79   uint32_t MemClk;
80   uint32_t Voltage;
81 } DfPstateTable_t;
82 
83 typedef struct {
84   uint16_t GfxclkFrequency;             //[MHz]
85   uint16_t SocclkFrequency;             //[MHz]
86 
87   uint16_t VclkFrequency;               //[MHz]
88   uint16_t DclkFrequency;               //[MHz]
89 
90   uint16_t MemclkFrequency;             //[MHz]
91   uint16_t spare;
92 
93   uint16_t GfxActivity;                 //[centi]
94   uint16_t UvdActivity;                 //[centi]
95 
96   uint16_t Voltage[2];                  //[mV] indices: VDDCR_VDD, VDDCR_SOC
97   uint16_t Current[2];                  //[mA] indices: VDDCR_VDD, VDDCR_SOC
98 
99   uint16_t Power[2];                    //[mW] indices: VDDCR_VDD, VDDCR_SOC
100   uint16_t GfxTemperature;              //[centi-Celsius]
101 
102   uint16_t SocTemperature;              //[centi-Celsius]
103   uint16_t ThrottlerStatus;
104 
105   uint16_t CurrentSocketPower;          //[mW]
106 } SmuMetrics_t;
107 
108 //Freq in MHz
109 //Voltage in milli volts with 2 fractional bits
110 typedef struct {
111   uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
112   uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
113   uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
114   uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
115   uint32_t VClocks[NUM_VCN_DPM_LEVELS];
116   uint32_t DClocks[NUM_VCN_DPM_LEVELS];
117   uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
118   DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS];
119   uint8_t  NumDcfClkLevelsEnabled;
120   uint8_t  NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
121   uint8_t  NumSocClkLevelsEnabled;
122   uint8_t  VcnClkLevelsEnabled;     //Applies to both Vclk and Dclk
123   uint8_t  NumDfPstatesEnabled;
124   uint8_t  spare[3];
125   uint32_t MinGfxClk;
126   uint32_t MaxGfxClk;
127 } DpmClocks_t;
128 
129 #define TABLE_BIOS_IF            0 // Called by BIOS
130 #define TABLE_WATERMARKS         1 // Called by DAL through VBIOS
131 #define TABLE_CUSTOM_DPM         2 // Called by Driver
132 #define TABLE_SPARE1             3
133 #define TABLE_DPMCLOCKS          4 // Called by Driver and VBIOS
134 #define TABLE_MOMENTARY_PM       5 // Called by Tools
135 #define TABLE_MODERN_STDBY       6 // Called by Tools for Modern Standby Log
136 #define TABLE_SMU_METRICS        7 // Called by Driver
137 #define TABLE_COUNT              8
138 
139 #endif
140