1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __SMU13_DRIVER_IF_V13_0_4_H__ 25 #define __SMU13_DRIVER_IF_V13_0_4_H__ 26 27 // *** IMPORTANT *** 28 // SMU TEAM: Always increment the interface version if 29 // any structure is changed in this file 30 #define PMFW_DRIVER_IF_VERSION 8 31 32 typedef struct { 33 int32_t value; 34 uint32_t numFractionalBits; 35 } FloatInIntFormat_t; 36 37 typedef enum { 38 DSPCLK_DCFCLK = 0, 39 DSPCLK_DISPCLK, 40 DSPCLK_PIXCLK, 41 DSPCLK_PHYCLK, 42 DSPCLK_COUNT, 43 } DSPCLK_e; 44 45 typedef struct { 46 uint16_t Freq; // in MHz 47 uint16_t Vid; // min voltage in SVI3 VID 48 } DisplayClockTable_t; 49 50 typedef struct { 51 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) 52 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) 53 uint16_t MinMclk; 54 uint16_t MaxMclk; 55 56 uint8_t WmSetting; 57 uint8_t WmType; // Used for normal pstate change or memory retraining 58 uint8_t Padding[2]; 59 } WatermarkRowGeneric_t; 60 61 #define NUM_WM_RANGES 4 62 #define WM_PSTATE_CHG 0 63 #define WM_RETRAINING 1 64 65 typedef enum { 66 WM_SOCCLK = 0, 67 WM_DCFCLK, 68 WM_COUNT, 69 } WM_CLOCK_e; 70 71 typedef struct { 72 // Watermarks 73 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; 74 75 uint32_t MmHubPadding[7]; // SMU internal use 76 } Watermarks_t; 77 78 typedef enum { 79 CUSTOM_DPM_SETTING_GFXCLK, 80 CUSTOM_DPM_SETTING_CCLK, 81 CUSTOM_DPM_SETTING_FCLK_CCX, 82 CUSTOM_DPM_SETTING_FCLK_GFX, 83 CUSTOM_DPM_SETTING_FCLK_STALLS, 84 CUSTOM_DPM_SETTING_LCLK, 85 CUSTOM_DPM_SETTING_COUNT, 86 } CUSTOM_DPM_SETTING_e; 87 88 typedef struct { 89 uint8_t ActiveHystLimit; 90 uint8_t IdleHystLimit; 91 uint8_t FPS; 92 uint8_t MinActiveFreqType; 93 FloatInIntFormat_t MinActiveFreq; 94 FloatInIntFormat_t PD_Data_limit; 95 FloatInIntFormat_t PD_Data_time_constant; 96 FloatInIntFormat_t PD_Data_error_coeff; 97 FloatInIntFormat_t PD_Data_error_rate_coeff; 98 } DpmActivityMonitorCoeffExt_t; 99 100 typedef struct { 101 DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT]; 102 } CustomDpmSettings_t; 103 104 #define NUM_DCFCLK_DPM_LEVELS 8 105 #define NUM_DISPCLK_DPM_LEVELS 8 106 #define NUM_DPPCLK_DPM_LEVELS 8 107 #define NUM_SOCCLK_DPM_LEVELS 8 108 #define NUM_VCN_DPM_LEVELS 8 109 #define NUM_SOC_VOLTAGE_LEVELS 8 110 #define NUM_DF_PSTATE_LEVELS 4 111 112 typedef struct { 113 uint32_t FClk; 114 uint32_t MemClk; 115 uint32_t Voltage; 116 uint8_t WckRatio; 117 uint8_t Spare[3]; 118 } DfPstateTable_t; 119 120 //Freq in MHz 121 //Voltage in milli volts with 2 fractional bits 122 typedef struct { 123 uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS]; 124 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS]; 125 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS]; 126 uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS]; 127 uint32_t VClocks[NUM_VCN_DPM_LEVELS]; 128 uint32_t DClocks[NUM_VCN_DPM_LEVELS]; 129 uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS]; 130 DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS]; 131 132 uint8_t NumDcfClkLevelsEnabled; 133 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk 134 uint8_t NumSocClkLevelsEnabled; 135 uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk 136 uint8_t NumDfPstatesEnabled; 137 uint8_t spare[3]; 138 139 uint32_t MinGfxClk; 140 uint32_t MaxGfxClk; 141 } DpmClocks_t; 142 143 144 // Throttler Status Bitmask 145 #define THROTTLER_STATUS_BIT_SPL 0 146 #define THROTTLER_STATUS_BIT_FPPT 1 147 #define THROTTLER_STATUS_BIT_SPPT 2 148 #define THROTTLER_STATUS_BIT_SPPT_APU 3 149 #define THROTTLER_STATUS_BIT_THM_CORE 4 150 #define THROTTLER_STATUS_BIT_THM_GFX 5 151 #define THROTTLER_STATUS_BIT_THM_SOC 6 152 #define THROTTLER_STATUS_BIT_TDC_VDD 7 153 #define THROTTLER_STATUS_BIT_TDC_SOC 8 154 #define THROTTLER_STATUS_BIT_PROCHOT_CPU 9 155 #define THROTTLER_STATUS_BIT_PROCHOT_GFX 10 156 #define THROTTLER_STATUS_BIT_EDC_CPU 11 157 #define THROTTLER_STATUS_BIT_EDC_GFX 12 158 159 typedef struct { 160 uint16_t GfxclkFrequency; //[MHz] 161 uint16_t SocclkFrequency; //[MHz] 162 uint16_t VclkFrequency; //[MHz] 163 uint16_t DclkFrequency; //[MHz] 164 uint16_t MemclkFrequency; //[MHz] 165 uint16_t spare; //[centi] 166 uint16_t GfxActivity; //[centi] 167 uint16_t UvdActivity; //[centi] 168 169 uint16_t Voltage[2]; //[mV] indices: VDDCR_VDD, VDDCR_SOC 170 uint16_t Current[2]; //[mA] indices: VDDCR_VDD, VDDCR_SOC 171 uint16_t Power[2]; //[mW] indices: VDDCR_VDD, VDDCR_SOC 172 173 //3rd party tools in Windows need this info in the case of APUs 174 uint16_t CoreFrequency[8]; //[MHz] 175 uint16_t CorePower[8]; //[mW] 176 uint16_t CoreTemperature[8]; //[centi-Celsius] 177 uint16_t L3Frequency; //[MHz] 178 uint16_t L3Temperature; //[centi-Celsius] 179 180 uint16_t GfxTemperature; //[centi-Celsius] 181 uint16_t SocTemperature; //[centi-Celsius] 182 uint16_t ThrottlerStatus; 183 184 uint16_t CurrentSocketPower; //[mW] 185 uint16_t StapmOpnLimit; //[W] 186 uint16_t StapmCurrentLimit; //[W] 187 uint32_t ApuPower; //[mW] 188 uint32_t dGpuPower; //[mW] 189 190 uint16_t VddTdcValue; //[mA] 191 uint16_t SocTdcValue; //[mA] 192 uint16_t VddEdcValue; //[mA] 193 uint16_t SocEdcValue; //[mA] 194 195 uint16_t InfrastructureCpuMaxFreq; //[MHz] 196 uint16_t InfrastructureGfxMaxFreq; //[MHz] 197 198 uint16_t SkinTemp; 199 uint16_t DeviceState; 200 uint16_t CurTemp; //[centi-Celsius] 201 uint16_t FilterAlphaValue; 202 203 uint16_t AverageGfxclkFrequency; 204 uint16_t AverageFclkFrequency; 205 uint16_t AverageGfxActivity; 206 uint16_t AverageSocclkFrequency; 207 uint16_t AverageVclkFrequency; 208 uint16_t AverageVcnActivity; 209 uint16_t AverageDRAMReads; //Filtered DF Bandwidth::DRAM Reads 210 uint16_t AverageDRAMWrites; //Filtered DF Bandwidth::DRAM Writes 211 uint16_t AverageSocketPower; //Filtered value of CurrentSocketPower 212 uint16_t AverageCorePower; //Filtered of [sum of CorePower[8]]) 213 uint16_t AverageCoreC0Residency[8]; //Filtered of [average C0 residency % per core] 214 uint32_t MetricsCounter; //Counts the # of metrics table parameter reads per update to the metrics table, i.e. if the metrics table update happens every 1 second, this value could be up to 1000 if the smu collected metrics data every cycle, or as low as 0 if the smu was asleep the whole time. Reset to 0 after writing. 215 } SmuMetrics_t; 216 217 typedef struct { 218 uint16_t StapmMaxPlatformLimit; //[W] 219 uint16_t StapmMinPlatformLimit; //[W] 220 uint16_t FastPptMaxPlatformLimit; //[W] 221 uint16_t FastPptMinPlatformLimit; //[W] 222 uint16_t SlowPptMaxPlatformLimit; //[W] 223 uint16_t SlowPptMinPlatformLimit; //[W] 224 uint16_t SlowPptApuMaxPlatformLimit; //[W] 225 uint16_t SlowPptApuMinPlatformLimit; //[W] 226 } PmfInfo_t; 227 228 //ISP tile definitions 229 typedef enum { 230 TILE_ISPX = 0, // ISPX 231 TILE_ISPM, // ISPM 232 TILE_ISPC, // ISPCORE 233 TILE_ISPPRE, // ISPPRE 234 TILE_ISPPOST0, // ISPPOST0, 235 TILE_ISPPOST1, // ISPPOST1 236 TILE_MAX 237 } TILE_NUM_e; 238 239 // Tile Selection (Based on arguments) 240 #define TILE_SEL_ISPX (1<<(TILE_ISPX)) 241 #define TILE_SEL_ISPM (1<<(TILE_ISPM)) 242 #define TILE_SEL_ISPC (1<<(TILE_ISPC)) 243 #define TILE_SEL_ISPPRE (1<<(TILE_ISPPRE)) 244 #define TILE_SEL_ISPPOST0 (1<<(TILE_ISPPOST0)) 245 #define TILE_SEL_ISPPOST1 (1<<(TILE_ISPPOST1)) 246 247 248 // Mask for ISP tiles in PGFSM PWR Status Registers 249 //Bit[1:0] maps to ISPX, (ISPX) 250 //Bit[3:2] maps to ISPM, (ISPM) 251 //Bit[5:4] maps to ISPCORE, (ISPCORE) 252 //Bit[7:6] maps to ISPPRE, (ISPPRE) 253 //Bit[9:8] maps to POST, (ISPPOST 254 #define TILE_ISPX_MASK ((1<<0) | (1<<1)) 255 #define TILE_ISPM_MASK ((1<<2) | (1<<3)) 256 #define TILE_ISPC_MASK ((1<<4) | (1<<5)) 257 #define TILE_ISPPRE_MASK ((1<<6) | (1<<7)) 258 #define TILE_ISPPOST0_MASK ((1<<8) | (1<<9)) 259 #define TILE_ISPPOST1_MASK ((1<<10) | (1<<11)) 260 261 262 // Workload bits 263 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0 264 #define WORKLOAD_PPLIB_VIDEO_BIT 2 265 #define WORKLOAD_PPLIB_VR_BIT 3 266 #define WORKLOAD_PPLIB_COMPUTE_BIT 4 267 #define WORKLOAD_PPLIB_CUSTOM_BIT 5 268 #define WORKLOAD_PPLIB_COUNT 6 269 270 #define TABLE_BIOS_IF 0 // Called by BIOS 271 #define TABLE_WATERMARKS 1 // Called by DAL through VBIOS 272 #define TABLE_CUSTOM_DPM 2 // Called by Driver 273 #define TABLE_SPARE1 3 274 #define TABLE_DPMCLOCKS 4 // Called by Driver and VBIOS 275 #define TABLE_MOMENTARY_PM 5 // Called by Tools 276 #define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log 277 #define TABLE_SMU_METRICS 7 // Called by Driver and PMF 278 #define TABLE_INFRASTRUCTURE_LIMITS 8 // Called by PMF 279 #define TABLE_COUNT 9 280 281 #endif 282 283