1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef SMU13_DRIVER_IF_V13_0_0_H 25 #define SMU13_DRIVER_IF_V13_0_0_H 26 27 // *** IMPORTANT *** 28 // PMFW TEAM: Always increment the interface version on any change to this file 29 #define SMU13_DRIVER_IF_VERSION 0x23 30 31 //Increment this version if SkuTable_t or BoardTable_t change 32 #define PPTABLE_VERSION 0x1D 33 34 #define NUM_GFXCLK_DPM_LEVELS 16 35 #define NUM_SOCCLK_DPM_LEVELS 8 36 #define NUM_MP0CLK_DPM_LEVELS 2 37 #define NUM_DCLK_DPM_LEVELS 8 38 #define NUM_VCLK_DPM_LEVELS 8 39 #define NUM_DISPCLK_DPM_LEVELS 8 40 #define NUM_DPPCLK_DPM_LEVELS 8 41 #define NUM_DPREFCLK_DPM_LEVELS 8 42 #define NUM_DCFCLK_DPM_LEVELS 8 43 #define NUM_DTBCLK_DPM_LEVELS 8 44 #define NUM_UCLK_DPM_LEVELS 4 45 #define NUM_LINK_LEVELS 3 46 #define NUM_FCLK_DPM_LEVELS 8 47 #define NUM_OD_FAN_MAX_POINTS 6 48 49 // Feature Control Defines 50 #define FEATURE_FW_DATA_READ_BIT 0 51 #define FEATURE_DPM_GFXCLK_BIT 1 52 #define FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT 2 53 #define FEATURE_DPM_UCLK_BIT 3 54 #define FEATURE_DPM_FCLK_BIT 4 55 #define FEATURE_DPM_SOCCLK_BIT 5 56 #define FEATURE_DPM_MP0CLK_BIT 6 57 #define FEATURE_DPM_LINK_BIT 7 58 #define FEATURE_DPM_DCN_BIT 8 59 #define FEATURE_VMEMP_SCALING_BIT 9 60 #define FEATURE_VDDIO_MEM_SCALING_BIT 10 61 #define FEATURE_DS_GFXCLK_BIT 11 62 #define FEATURE_DS_SOCCLK_BIT 12 63 #define FEATURE_DS_FCLK_BIT 13 64 #define FEATURE_DS_LCLK_BIT 14 65 #define FEATURE_DS_DCFCLK_BIT 15 66 #define FEATURE_DS_UCLK_BIT 16 67 #define FEATURE_GFX_ULV_BIT 17 68 #define FEATURE_FW_DSTATE_BIT 18 69 #define FEATURE_GFXOFF_BIT 19 70 #define FEATURE_BACO_BIT 20 71 #define FEATURE_MM_DPM_BIT 21 72 #define FEATURE_SOC_MPCLK_DS_BIT 22 73 #define FEATURE_BACO_MPCLK_DS_BIT 23 74 #define FEATURE_THROTTLERS_BIT 24 75 #define FEATURE_SMARTSHIFT_BIT 25 76 #define FEATURE_GTHR_BIT 26 77 #define FEATURE_ACDC_BIT 27 78 #define FEATURE_VR0HOT_BIT 28 79 #define FEATURE_FW_CTF_BIT 29 80 #define FEATURE_FAN_CONTROL_BIT 30 81 #define FEATURE_GFX_DCS_BIT 31 82 #define FEATURE_GFX_READ_MARGIN_BIT 32 83 #define FEATURE_LED_DISPLAY_BIT 33 84 #define FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT 34 85 #define FEATURE_OUT_OF_BAND_MONITOR_BIT 35 86 #define FEATURE_OPTIMIZED_VMIN_BIT 36 87 #define FEATURE_GFX_IMU_BIT 37 88 #define FEATURE_BOOT_TIME_CAL_BIT 38 89 #define FEATURE_GFX_PCC_DFLL_BIT 39 90 #define FEATURE_SOC_CG_BIT 40 91 #define FEATURE_DF_CSTATE_BIT 41 92 #define FEATURE_GFX_EDC_BIT 42 93 #define FEATURE_BOOT_POWER_OPT_BIT 43 94 #define FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT 44 95 #define FEATURE_DS_VCN_BIT 45 96 #define FEATURE_BACO_CG_BIT 46 97 #define FEATURE_MEM_TEMP_READ_BIT 47 98 #define FEATURE_ATHUB_MMHUB_PG_BIT 48 99 #define FEATURE_SOC_PCC_BIT 49 100 #define FEATURE_EDC_PWRBRK_BIT 50 101 #define FEATURE_SPARE_51_BIT 51 102 #define FEATURE_SPARE_52_BIT 52 103 #define FEATURE_SPARE_53_BIT 53 104 #define FEATURE_SPARE_54_BIT 54 105 #define FEATURE_SPARE_55_BIT 55 106 #define FEATURE_SPARE_56_BIT 56 107 #define FEATURE_SPARE_57_BIT 57 108 #define FEATURE_SPARE_58_BIT 58 109 #define FEATURE_SPARE_59_BIT 59 110 #define FEATURE_SPARE_60_BIT 60 111 #define FEATURE_SPARE_61_BIT 61 112 #define FEATURE_SPARE_62_BIT 62 113 #define FEATURE_SPARE_63_BIT 63 114 #define NUM_FEATURES 64 115 116 //For use with feature control messages 117 typedef enum { 118 FEATURE_PWR_ALL, 119 FEATURE_PWR_S5, 120 FEATURE_PWR_BACO, 121 FEATURE_PWR_SOC, 122 FEATURE_PWR_GFX, 123 FEATURE_PWR_DOMAIN_COUNT, 124 } FEATURE_PWR_DOMAIN_e; 125 126 127 // Debug Overrides Bitmask 128 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000001 129 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK 0x00000002 130 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK 0x00000004 131 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK 0x00000008 132 #define DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x00000010 133 #define DEBUG_OVERRIDE_DISABLE_VCN_PG 0x00000020 134 #define DEBUG_OVERRIDE_DISABLE_FMAX_VMAX 0x00000040 135 #define DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS 0x00000080 136 #define DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK 0x00000100 137 #define DEBUG_OVERRIDE_DISABLE_DFLL 0x00000200 138 #define DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE 0x00000400 139 #define DEBUG_OVERRIDE_DFLL_MASTER_MODE 0x00000800 140 141 // VR Mapping Bit Defines 142 #define VR_MAPPING_VR_SELECT_MASK 0x01 143 #define VR_MAPPING_VR_SELECT_SHIFT 0x00 144 145 #define VR_MAPPING_PLANE_SELECT_MASK 0x02 146 #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 147 148 // PSI Bit Defines 149 #define PSI_SEL_VR0_PLANE0_PSI0 0x01 150 #define PSI_SEL_VR0_PLANE0_PSI1 0x02 151 #define PSI_SEL_VR0_PLANE1_PSI0 0x04 152 #define PSI_SEL_VR0_PLANE1_PSI1 0x08 153 #define PSI_SEL_VR1_PLANE0_PSI0 0x10 154 #define PSI_SEL_VR1_PLANE0_PSI1 0x20 155 #define PSI_SEL_VR1_PLANE1_PSI0 0x40 156 #define PSI_SEL_VR1_PLANE1_PSI1 0x80 157 158 typedef enum { 159 SVI_PSI_0, // Full phase count (default) 160 SVI_PSI_1, // Phase count 1st level 161 SVI_PSI_2, // Phase count 2nd level 162 SVI_PSI_3, // Single phase operation + active diode emulation 163 SVI_PSI_4, // Single phase operation + passive diode emulation *optional* 164 SVI_PSI_5, // Reserved 165 SVI_PSI_6, // Power down to 0V (voltage regulation disabled) 166 SVI_PSI_7, // Automated phase shedding and diode emulation 167 } SVI_PSI_e; 168 169 // Throttler Control/Status Bits 170 #define THROTTLER_TEMP_EDGE_BIT 0 171 #define THROTTLER_TEMP_HOTSPOT_BIT 1 172 #define THROTTLER_TEMP_HOTSPOT_G_BIT 2 173 #define THROTTLER_TEMP_HOTSPOT_M_BIT 3 174 #define THROTTLER_TEMP_MEM_BIT 4 175 #define THROTTLER_TEMP_VR_GFX_BIT 5 176 #define THROTTLER_TEMP_VR_MEM0_BIT 6 177 #define THROTTLER_TEMP_VR_MEM1_BIT 7 178 #define THROTTLER_TEMP_VR_SOC_BIT 8 179 #define THROTTLER_TEMP_VR_U_BIT 9 180 #define THROTTLER_TEMP_LIQUID0_BIT 10 181 #define THROTTLER_TEMP_LIQUID1_BIT 11 182 #define THROTTLER_TEMP_PLX_BIT 12 183 #define THROTTLER_TDC_GFX_BIT 13 184 #define THROTTLER_TDC_SOC_BIT 14 185 #define THROTTLER_TDC_U_BIT 15 186 #define THROTTLER_PPT0_BIT 16 187 #define THROTTLER_PPT1_BIT 17 188 #define THROTTLER_PPT2_BIT 18 189 #define THROTTLER_PPT3_BIT 19 190 #define THROTTLER_FIT_BIT 20 191 #define THROTTLER_GFX_APCC_PLUS_BIT 21 192 #define THROTTLER_COUNT 22 193 194 // FW DState Features Control Bits 195 #define FW_DSTATE_SOC_ULV_BIT 0 196 #define FW_DSTATE_G6_HSR_BIT 1 197 #define FW_DSTATE_G6_PHY_VMEMP_OFF_BIT 2 198 #define FW_DSTATE_SMN_DS_BIT 3 199 #define FW_DSTATE_MP1_WHISPER_MODE_BIT 4 200 #define FW_DSTATE_SOC_LIV_MIN_BIT 5 201 #define FW_DSTATE_SOC_PLL_PWRDN_BIT 6 202 #define FW_DSTATE_MEM_PLL_PWRDN_BIT 7 203 #define FW_DSTATE_MALL_ALLOC_BIT 8 204 #define FW_DSTATE_MEM_PSI_BIT 9 205 #define FW_DSTATE_HSR_NON_STROBE_BIT 10 206 #define FW_DSTATE_MP0_ENTER_WFI_BIT 11 207 #define FW_DSTATE_U_ULV_BIT 12 208 #define FW_DSTATE_MALL_FLUSH_BIT 13 209 #define FW_DSTATE_SOC_PSI_BIT 14 210 #define FW_DSTATE_U_PSI_BIT 15 211 #define FW_DSTATE_UCP_DS_BIT 16 212 #define FW_DSTATE_CSRCLK_DS_BIT 17 213 #define FW_DSTATE_MMHUB_INTERLOCK_BIT 18 214 #define FW_DSTATE_D0i3_2_QUIET_FW_BIT 19 215 #define FW_DSTATE_CLDO_PRG_BIT 20 216 #define FW_DSTATE_DF_PLL_PWRDN_BIT 21 217 #define FW_DSTATE_U_LOW_PWR_MODE_EN_BIT 22 218 #define FW_DSTATE_GFX_PSI6_BIT 23 219 #define FW_DSTATE_GFX_VR_PWR_STAGE_BIT 24 220 221 //LED Display Mask & Control Bits 222 #define LED_DISPLAY_GFX_DPM_BIT 0 223 #define LED_DISPLAY_PCIE_BIT 1 224 #define LED_DISPLAY_ERROR_BIT 2 225 226 227 #define MEM_TEMP_READ_OUT_OF_BAND_BIT 0 228 #define MEM_TEMP_READ_IN_BAND_REFRESH_BIT 1 229 #define MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT 2 230 231 typedef enum { 232 SMARTSHIFT_VERSION_1, 233 SMARTSHIFT_VERSION_2, 234 SMARTSHIFT_VERSION_3, 235 } SMARTSHIFT_VERSION_e; 236 237 typedef enum { 238 FOPT_CALC_AC_CALC_DC, 239 FOPT_PPTABLE_AC_CALC_DC, 240 FOPT_CALC_AC_PPTABLE_DC, 241 FOPT_PPTABLE_AC_PPTABLE_DC, 242 } FOPT_CALC_e; 243 244 typedef enum { 245 DRAM_BIT_WIDTH_DISABLED = 0, 246 DRAM_BIT_WIDTH_X_8 = 8, 247 DRAM_BIT_WIDTH_X_16 = 16, 248 DRAM_BIT_WIDTH_X_32 = 32, 249 DRAM_BIT_WIDTH_X_64 = 64, 250 DRAM_BIT_WIDTH_X_128 = 128, 251 DRAM_BIT_WIDTH_COUNT, 252 } DRAM_BIT_WIDTH_TYPE_e; 253 254 //I2C Interface 255 #define NUM_I2C_CONTROLLERS 8 256 257 #define I2C_CONTROLLER_ENABLED 1 258 #define I2C_CONTROLLER_DISABLED 0 259 260 #define MAX_SW_I2C_COMMANDS 24 261 262 typedef enum { 263 I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0 264 I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1 265 I2C_CONTROLLER_PORT_COUNT, 266 } I2cControllerPort_e; 267 268 typedef enum { 269 I2C_CONTROLLER_NAME_VR_GFX = 0, 270 I2C_CONTROLLER_NAME_VR_SOC, 271 I2C_CONTROLLER_NAME_VR_VMEMP, 272 I2C_CONTROLLER_NAME_VR_VDDIO, 273 I2C_CONTROLLER_NAME_LIQUID0, 274 I2C_CONTROLLER_NAME_LIQUID1, 275 I2C_CONTROLLER_NAME_PLX, 276 I2C_CONTROLLER_NAME_OTHER, 277 I2C_CONTROLLER_NAME_COUNT, 278 } I2cControllerName_e; 279 280 typedef enum { 281 I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 282 I2C_CONTROLLER_THROTTLER_VR_GFX, 283 I2C_CONTROLLER_THROTTLER_VR_SOC, 284 I2C_CONTROLLER_THROTTLER_VR_VMEMP, 285 I2C_CONTROLLER_THROTTLER_VR_VDDIO, 286 I2C_CONTROLLER_THROTTLER_LIQUID0, 287 I2C_CONTROLLER_THROTTLER_LIQUID1, 288 I2C_CONTROLLER_THROTTLER_PLX, 289 I2C_CONTROLLER_THROTTLER_INA3221, 290 I2C_CONTROLLER_THROTTLER_COUNT, 291 } I2cControllerThrottler_e; 292 293 typedef enum { 294 I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5, 295 I2C_CONTROLLER_PROTOCOL_VR_IR35217, 296 I2C_CONTROLLER_PROTOCOL_TMP_TMP102A, 297 I2C_CONTROLLER_PROTOCOL_INA3221, 298 I2C_CONTROLLER_PROTOCOL_COUNT, 299 } I2cControllerProtocol_e; 300 301 typedef struct { 302 uint8_t Enabled; 303 uint8_t Speed; 304 uint8_t SlaveAddress; 305 uint8_t ControllerPort; 306 uint8_t ControllerName; 307 uint8_t ThermalThrotter; 308 uint8_t I2cProtocol; 309 uint8_t PaddingConfig; 310 } I2cControllerConfig_t; 311 312 typedef enum { 313 I2C_PORT_SVD_SCL = 0, 314 I2C_PORT_GPIO, 315 } I2cPort_e; 316 317 typedef enum { 318 I2C_SPEED_FAST_50K = 0, //50 Kbits/s 319 I2C_SPEED_FAST_100K, //100 Kbits/s 320 I2C_SPEED_FAST_400K, //400 Kbits/s 321 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 322 I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 323 I2C_SPEED_HIGH_2M, //2.3 Mbits/s 324 I2C_SPEED_COUNT, 325 } I2cSpeed_e; 326 327 typedef enum { 328 I2C_CMD_READ = 0, 329 I2C_CMD_WRITE, 330 I2C_CMD_COUNT, 331 } I2cCmdType_e; 332 333 #define CMDCONFIG_STOP_BIT 0 334 #define CMDCONFIG_RESTART_BIT 1 335 #define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write 336 337 #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 338 #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 339 #define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT) 340 341 typedef struct { 342 uint8_t ReadWriteData; //Return data for read. Data to send for write 343 uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write 344 } SwI2cCmd_t; //SW I2C Command Table 345 346 typedef struct { 347 uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 348 uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select 349 uint8_t SlaveAddress; //Slave address of device 350 uint8_t NumCmds; //Number of commands 351 352 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 353 } SwI2cRequest_t; // SW I2C Request Table 354 355 typedef struct { 356 SwI2cRequest_t SwI2cRequest; 357 358 uint32_t Spare[8]; 359 uint32_t MmHubPadding[8]; // SMU internal use 360 } SwI2cRequestExternal_t; 361 362 typedef struct { 363 uint64_t mca_umc_status; 364 uint64_t mca_umc_addr; 365 366 uint16_t ce_count_lo_chip; 367 uint16_t ce_count_hi_chip; 368 369 uint32_t eccPadding; 370 } EccInfo_t; 371 372 typedef struct { 373 EccInfo_t EccInfo[24]; 374 } EccInfoTable_t; 375 376 //D3HOT sequences 377 typedef enum { 378 BACO_SEQUENCE, 379 MSR_SEQUENCE, 380 BAMACO_SEQUENCE, 381 ULPS_SEQUENCE, 382 D3HOT_SEQUENCE_COUNT, 383 } D3HOTSequence_e; 384 385 //This is aligned with RSMU PGFSM Register Mapping 386 typedef enum { 387 PG_DYNAMIC_MODE = 0, 388 PG_STATIC_MODE, 389 } PowerGatingMode_e; 390 391 //This is aligned with RSMU PGFSM Register Mapping 392 typedef enum { 393 PG_POWER_DOWN = 0, 394 PG_POWER_UP, 395 } PowerGatingSettings_e; 396 397 typedef struct { 398 uint32_t a; // store in IEEE float format in this variable 399 uint32_t b; // store in IEEE float format in this variable 400 uint32_t c; // store in IEEE float format in this variable 401 } QuadraticInt_t; 402 403 typedef struct { 404 uint32_t m; // store in IEEE float format in this variable 405 uint32_t b; // store in IEEE float format in this variable 406 } LinearInt_t; 407 408 typedef struct { 409 uint32_t a; // store in IEEE float format in this variable 410 uint32_t b; // store in IEEE float format in this variable 411 uint32_t c; // store in IEEE float format in this variable 412 } DroopInt_t; 413 414 typedef enum { 415 DCS_ARCH_DISABLED, 416 DCS_ARCH_FADCS, 417 DCS_ARCH_ASYNC, 418 } DCS_ARCH_e; 419 420 //Only Clks that have DPM descriptors are listed here 421 typedef enum { 422 PPCLK_GFXCLK = 0, 423 PPCLK_SOCCLK, 424 PPCLK_UCLK, 425 PPCLK_FCLK, 426 PPCLK_DCLK_0, 427 PPCLK_VCLK_0, 428 PPCLK_DCLK_1, 429 PPCLK_VCLK_1, 430 PPCLK_DISPCLK, 431 PPCLK_DPPCLK, 432 PPCLK_DPREFCLK, 433 PPCLK_DCFCLK, 434 PPCLK_DTBCLK, 435 PPCLK_COUNT, 436 } PPCLK_e; 437 438 typedef enum { 439 VOLTAGE_MODE_PPTABLE = 0, 440 VOLTAGE_MODE_FUSES, 441 VOLTAGE_MODE_COUNT, 442 } VOLTAGE_MODE_e; 443 444 445 typedef enum { 446 AVFS_VOLTAGE_GFX = 0, 447 AVFS_VOLTAGE_SOC, 448 AVFS_VOLTAGE_COUNT, 449 } AVFS_VOLTAGE_TYPE_e; 450 451 typedef enum { 452 AVFS_TEMP_COLD = 0, 453 AVFS_TEMP_HOT, 454 AVFS_TEMP_COUNT, 455 } AVFS_TEMP_e; 456 457 typedef enum { 458 AVFS_D_G, 459 AVFS_D_M_B, 460 AVFS_D_M_S, 461 AVFS_D_COUNT, 462 } AVFS_D_e; 463 464 typedef enum { 465 UCLK_DIV_BY_1 = 0, 466 UCLK_DIV_BY_2, 467 UCLK_DIV_BY_4, 468 UCLK_DIV_BY_8, 469 } UCLK_DIV_e; 470 471 typedef enum { 472 GPIO_INT_POLARITY_ACTIVE_LOW = 0, 473 GPIO_INT_POLARITY_ACTIVE_HIGH, 474 } GpioIntPolarity_e; 475 476 typedef enum { 477 PWR_CONFIG_TDP = 0, 478 PWR_CONFIG_TGP, 479 PWR_CONFIG_TCP_ESTIMATED, 480 PWR_CONFIG_TCP_MEASURED, 481 } PwrConfig_e; 482 483 typedef struct { 484 uint8_t Padding; 485 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 486 uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 487 uint8_t CalculateFopt; // Indication whether FW should calculate Fopt or use values below. Reference FOPT_CALC_e 488 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 489 uint32_t Padding3[3]; 490 uint16_t Padding4; 491 uint16_t FoptimalDc; //Foptimal frequency in DC power mode. 492 uint16_t FoptimalAc; //Foptimal frequency in AC power mode. 493 uint16_t Padding2; 494 } DpmDescriptor_t; 495 496 typedef enum { 497 PPT_THROTTLER_PPT0, 498 PPT_THROTTLER_PPT1, 499 PPT_THROTTLER_PPT2, 500 PPT_THROTTLER_PPT3, 501 PPT_THROTTLER_COUNT 502 } PPT_THROTTLER_e; 503 504 typedef enum { 505 TEMP_EDGE, 506 TEMP_HOTSPOT, 507 TEMP_HOTSPOT_G, 508 TEMP_HOTSPOT_M, 509 TEMP_MEM, 510 TEMP_VR_GFX, 511 TEMP_VR_MEM0, 512 TEMP_VR_MEM1, 513 TEMP_VR_SOC, 514 TEMP_VR_U, 515 TEMP_LIQUID0, 516 TEMP_LIQUID1, 517 TEMP_PLX, 518 TEMP_COUNT, 519 } TEMP_e; 520 521 typedef enum { 522 TDC_THROTTLER_GFX, 523 TDC_THROTTLER_SOC, 524 TDC_THROTTLER_U, 525 TDC_THROTTLER_COUNT 526 } TDC_THROTTLER_e; 527 528 typedef enum { 529 SVI_PLANE_GFX, 530 SVI_PLANE_SOC, 531 SVI_PLANE_VMEMP, 532 SVI_PLANE_VDDIO_MEM, 533 SVI_PLANE_U, 534 SVI_PLANE_COUNT, 535 } SVI_PLANE_e; 536 537 typedef enum { 538 PMFW_VOLT_PLANE_GFX, 539 PMFW_VOLT_PLANE_SOC, 540 PMFW_VOLT_PLANE_COUNT 541 } PMFW_VOLT_PLANE_e; 542 543 typedef enum { 544 CUSTOMER_VARIANT_ROW, 545 CUSTOMER_VARIANT_FALCON, 546 CUSTOMER_VARIANT_COUNT, 547 } CUSTOMER_VARIANT_e; 548 549 typedef enum { 550 POWER_SOURCE_AC, 551 POWER_SOURCE_DC, 552 POWER_SOURCE_COUNT, 553 } POWER_SOURCE_e; 554 555 typedef enum { 556 MEM_VENDOR_SAMSUNG, 557 MEM_VENDOR_INFINEON, 558 MEM_VENDOR_ELPIDA, 559 MEM_VENDOR_ETRON, 560 MEM_VENDOR_NANYA, 561 MEM_VENDOR_HYNIX, 562 MEM_VENDOR_MOSEL, 563 MEM_VENDOR_WINBOND, 564 MEM_VENDOR_ESMT, 565 MEM_VENDOR_PLACEHOLDER0, 566 MEM_VENDOR_PLACEHOLDER1, 567 MEM_VENDOR_PLACEHOLDER2, 568 MEM_VENDOR_PLACEHOLDER3, 569 MEM_VENDOR_PLACEHOLDER4, 570 MEM_VENDOR_PLACEHOLDER5, 571 MEM_VENDOR_MICRON, 572 MEM_VENDOR_COUNT, 573 } MEM_VENDOR_e; 574 575 typedef enum { 576 PP_GRTAVFS_HW_CPO_CTL_ZONE0, 577 PP_GRTAVFS_HW_CPO_CTL_ZONE1, 578 PP_GRTAVFS_HW_CPO_CTL_ZONE2, 579 PP_GRTAVFS_HW_CPO_CTL_ZONE3, 580 PP_GRTAVFS_HW_CPO_CTL_ZONE4, 581 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0, 582 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0, 583 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1, 584 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1, 585 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2, 586 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2, 587 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3, 588 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3, 589 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4, 590 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4, 591 PP_GRTAVFS_HW_ZONE0_VF, 592 PP_GRTAVFS_HW_ZONE1_VF1, 593 PP_GRTAVFS_HW_ZONE2_VF2, 594 PP_GRTAVFS_HW_ZONE3_VF3, 595 PP_GRTAVFS_HW_VOLTAGE_GB, 596 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0, 597 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1, 598 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2, 599 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3, 600 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4, 601 PP_GRTAVFS_HW_RESERVED_0, 602 PP_GRTAVFS_HW_RESERVED_1, 603 PP_GRTAVFS_HW_RESERVED_2, 604 PP_GRTAVFS_HW_RESERVED_3, 605 PP_GRTAVFS_HW_RESERVED_4, 606 PP_GRTAVFS_HW_RESERVED_5, 607 PP_GRTAVFS_HW_RESERVED_6, 608 PP_GRTAVFS_HW_FUSE_COUNT, 609 } PP_GRTAVFS_HW_FUSE_e; 610 611 typedef enum { 612 PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0, 613 PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0, 614 PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0, 615 PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0, 616 PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0, 617 PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0, 618 PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0, 619 PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0, 620 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0, 621 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1, 622 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2, 623 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3, 624 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4, 625 PP_GRTAVFS_FW_COMMON_FUSE_COUNT, 626 } PP_GRTAVFS_FW_COMMON_FUSE_e; 627 628 typedef enum { 629 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1, 630 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0, 631 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1, 632 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2, 633 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3, 634 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4, 635 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1, 636 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0, 637 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1, 638 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2, 639 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3, 640 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4, 641 PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY, 642 PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY, 643 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0, 644 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1, 645 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2, 646 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3, 647 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4, 648 PP_GRTAVFS_FW_SEP_FUSE_COUNT, 649 } PP_GRTAVFS_FW_SEP_FUSE_e; 650 651 #define PP_NUM_RTAVFS_PWL_ZONES 5 652 653 654 655 // VBIOS or PPLIB configures telemetry slope and offset. Only slope expected to be set for SVI3 656 // Slope Q1.7, Offset Q1.2 657 typedef struct { 658 int8_t Offset; // in Amps 659 uint8_t Padding; 660 uint16_t MaxCurrent; // in Amps 661 } SviTelemetryScale_t; 662 663 #define PP_NUM_OD_VF_CURVE_POINTS PP_NUM_RTAVFS_PWL_ZONES + 1 664 665 666 typedef struct { 667 uint32_t FeatureCtrlMask; 668 669 //Voltage control 670 int16_t VoltageOffsetPerZoneBoundary[PP_NUM_OD_VF_CURVE_POINTS]; 671 uint16_t reserved[2]; 672 673 //Frequency changes 674 int16_t GfxclkFmin; // MHz 675 int16_t GfxclkFmax; // MHz 676 uint16_t UclkFmin; // MHz 677 uint16_t UclkFmax; // MHz 678 679 //PPT 680 int16_t Ppt; // % 681 int16_t reserved1; 682 683 //Fan control 684 uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS]; 685 uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS]; 686 uint16_t FanMinimumPwm; 687 uint16_t AcousticTargetRpmThreshold; 688 uint16_t AcousticLimitRpmThreshold; 689 uint16_t FanTargetTemperature; // Degree Celcius 690 uint8_t FanZeroRpmEnable; 691 uint8_t FanZeroRpmStopTemp; 692 uint8_t FanMode; 693 uint8_t MaxOpTemp; 694 695 uint32_t Spare[13]; 696 uint32_t MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround 697 } OverDriveTable_t; 698 699 typedef struct { 700 OverDriveTable_t OverDriveTable; 701 702 } OverDriveTableExternal_t; 703 704 typedef struct { 705 uint32_t FeatureCtrlMask; 706 707 int16_t VoltageOffsetPerZoneBoundary; 708 uint16_t reserved[2]; 709 710 uint16_t GfxclkFmin; // MHz 711 uint16_t GfxclkFmax; // MHz 712 uint16_t UclkFmin; // MHz 713 uint16_t UclkFmax; // MHz 714 715 //PPT 716 int16_t Ppt; // % 717 int16_t reserved1; 718 719 uint8_t FanLinearPwmPoints; 720 uint8_t FanLinearTempPoints; 721 uint16_t FanMinimumPwm; 722 uint16_t AcousticTargetRpmThreshold; 723 uint16_t AcousticLimitRpmThreshold; 724 uint16_t FanTargetTemperature; // Degree Celcius 725 uint8_t FanZeroRpmEnable; 726 uint8_t FanZeroRpmStopTemp; 727 uint8_t FanMode; 728 uint8_t MaxOpTemp; 729 730 uint32_t Spare[13]; 731 732 } OverDriveLimits_t; 733 734 735 typedef enum { 736 BOARD_GPIO_SMUIO_0, 737 BOARD_GPIO_SMUIO_1, 738 BOARD_GPIO_SMUIO_2, 739 BOARD_GPIO_SMUIO_3, 740 BOARD_GPIO_SMUIO_4, 741 BOARD_GPIO_SMUIO_5, 742 BOARD_GPIO_SMUIO_6, 743 BOARD_GPIO_SMUIO_7, 744 BOARD_GPIO_SMUIO_8, 745 BOARD_GPIO_SMUIO_9, 746 BOARD_GPIO_SMUIO_10, 747 BOARD_GPIO_SMUIO_11, 748 BOARD_GPIO_SMUIO_12, 749 BOARD_GPIO_SMUIO_13, 750 BOARD_GPIO_SMUIO_14, 751 BOARD_GPIO_SMUIO_15, 752 BOARD_GPIO_SMUIO_16, 753 BOARD_GPIO_SMUIO_17, 754 BOARD_GPIO_SMUIO_18, 755 BOARD_GPIO_SMUIO_19, 756 BOARD_GPIO_SMUIO_20, 757 BOARD_GPIO_SMUIO_21, 758 BOARD_GPIO_SMUIO_22, 759 BOARD_GPIO_SMUIO_23, 760 BOARD_GPIO_SMUIO_24, 761 BOARD_GPIO_SMUIO_25, 762 BOARD_GPIO_SMUIO_26, 763 BOARD_GPIO_SMUIO_27, 764 BOARD_GPIO_SMUIO_28, 765 BOARD_GPIO_SMUIO_29, 766 BOARD_GPIO_SMUIO_30, 767 BOARD_GPIO_SMUIO_31, 768 MAX_BOARD_GPIO_SMUIO_NUM, 769 BOARD_GPIO_DC_GEN_A, 770 BOARD_GPIO_DC_GEN_B, 771 BOARD_GPIO_DC_GEN_C, 772 BOARD_GPIO_DC_GEN_D, 773 BOARD_GPIO_DC_GEN_E, 774 BOARD_GPIO_DC_GEN_F, 775 BOARD_GPIO_DC_GEN_G, 776 BOARD_GPIO_DC_GENLK_CLK, 777 BOARD_GPIO_DC_GENLK_VSYNC, 778 BOARD_GPIO_DC_SWAPLOCK_A, 779 BOARD_GPIO_DC_SWAPLOCK_B, 780 } BOARD_GPIO_TYPE_e; 781 782 #define INVALID_BOARD_GPIO 0xFF 783 784 785 typedef struct { 786 //PLL 0 787 uint16_t InitGfxclk_bypass; 788 uint16_t InitSocclk; 789 uint16_t InitMp0clk; 790 uint16_t InitMpioclk; 791 uint16_t InitSmnclk; 792 uint16_t InitUcpclk; 793 uint16_t InitCsrclk; 794 //PLL 1 795 796 uint16_t InitDprefclk; 797 uint16_t InitDcfclk; 798 uint16_t InitDtbclk; 799 //PLL 2 800 uint16_t InitDclk; //assume same DCLK/VCLK for both instances 801 uint16_t InitVclk; 802 // PLL 3 803 uint16_t InitUsbdfsclk; 804 uint16_t InitMp1clk; 805 uint16_t InitLclk; 806 uint16_t InitBaco400clk_bypass; 807 uint16_t InitBaco1200clk_bypass; 808 uint16_t InitBaco700clk_bypass; 809 // PLL 4 810 uint16_t InitFclk; 811 // PLL 5 812 uint16_t InitGfxclk_clkb; 813 814 //PLL 6 815 uint8_t InitUclkDPMState; // =0,1,2,3, frequency from FreqTableUclk 816 817 uint8_t Padding[3]; 818 819 uint32_t InitVcoFreqPll0; 820 uint32_t InitVcoFreqPll1; 821 uint32_t InitVcoFreqPll2; 822 uint32_t InitVcoFreqPll3; 823 uint32_t InitVcoFreqPll4; 824 uint32_t InitVcoFreqPll5; 825 uint32_t InitVcoFreqPll6; 826 827 //encoding will change depending on SVI2/SVI3 828 uint16_t InitGfx; // In mV(Q2) , should be 0? 829 uint16_t InitSoc; // In mV(Q2) 830 uint16_t InitU; // In Mv(Q2) 831 832 uint16_t Padding2; 833 834 uint32_t Spare[8]; 835 836 } BootValues_t; 837 838 839 typedef struct { 840 uint16_t Power[PPT_THROTTLER_COUNT][POWER_SOURCE_COUNT]; // Watts 841 uint16_t Tdc[TDC_THROTTLER_COUNT]; // Amps 842 843 uint16_t Temperature[TEMP_COUNT]; // Celsius 844 845 uint8_t PwmLimitMin; 846 uint8_t PwmLimitMax; 847 uint8_t FanTargetTemperature; 848 uint8_t Spare1[1]; 849 850 uint16_t AcousticTargetRpmThresholdMin; 851 uint16_t AcousticTargetRpmThresholdMax; 852 853 uint16_t AcousticLimitRpmThresholdMin; 854 uint16_t AcousticLimitRpmThresholdMax; 855 856 uint16_t PccLimitMin; 857 uint16_t PccLimitMax; 858 859 uint16_t FanStopTempMin; 860 uint16_t FanStopTempMax; 861 uint16_t FanStartTempMin; 862 uint16_t FanStartTempMax; 863 864 uint32_t Spare[12]; 865 866 } MsgLimits_t; 867 868 typedef struct { 869 uint16_t BaseClockAc; 870 uint16_t GameClockAc; 871 uint16_t BoostClockAc; 872 uint16_t BaseClockDc; 873 uint16_t GameClockDc; 874 uint16_t BoostClockDc; 875 876 uint32_t Reserved[4]; 877 } DriverReportedClocks_t; 878 879 typedef struct { 880 uint8_t DcBtcEnabled; 881 uint8_t Padding[3]; 882 883 uint16_t DcTol; // mV Q2 884 uint16_t DcBtcGb; // mV Q2 885 886 uint16_t DcBtcMin; // mV Q2 887 uint16_t DcBtcMax; // mV Q2 888 889 LinearInt_t DcBtcGbScalar; 890 891 } AvfsDcBtcParams_t; 892 893 typedef struct { 894 uint16_t AvfsTemp[AVFS_TEMP_COUNT]; //in degrees C 895 uint16_t VftFMin; // in MHz 896 uint16_t VInversion; // in mV Q2 897 QuadraticInt_t qVft[AVFS_TEMP_COUNT]; 898 QuadraticInt_t qAvfsGb; 899 QuadraticInt_t qAvfsGb2; 900 } AvfsFuseOverride_t; 901 902 typedef struct { 903 // SECTION: Version 904 905 uint32_t Version; // should be unique to each SKU(i.e if any value changes in below structure then this value must be different) 906 907 // SECTION: Feature Control 908 uint32_t FeaturesToRun[NUM_FEATURES / 32]; // Features that PMFW will attempt to enable. Use FEATURE_*_BIT as mapping 909 910 // SECTION: Miscellaneous Configuration 911 uint8_t TotalPowerConfig; // Determines how PMFW calculates the power. Use defines from PwrConfig_e 912 uint8_t CustomerVariant; //To specify if this PPTable is intended for a particular customer. Use defines from CUSTOMER_VARIANT_e 913 uint8_t MemoryTemperatureTypeMask; // Bit mapping indicating which methods of memory temperature reading are enabled. Use defines from MEM_TEMP_*BIT 914 uint8_t SmartShiftVersion; // Determine what SmartShift feature version is supported Use defines from SMARTSHIFT_VERSION_e 915 916 // SECTION: Infrastructure Limits 917 uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in AC mode. Multiple limits supported 918 uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in DC mode. Multiple limits supported 919 920 uint16_t SocketPowerLimitSmartShift2; // In Watts. Power limit used SmartShift 921 922 //if set to 1, SocketPowerLimitAc and SocketPowerLimitDc will be interpreted as legacy programs(i.e absolute power). If 0, all except index 0 will be scalars 923 //relative index 0 924 uint8_t EnableLegacyPptLimit; 925 uint8_t UseInputTelemetry; //applicable to SVI3 only and only to be set if VRs support 926 uint8_t SmartShiftMinReportedPptinDcs; //minimum possible active power consumption for this SKU. Used for SmartShift power reporting 927 928 uint8_t PaddingPpt[1]; 929 930 uint16_t VrTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with VR regulator maximum temperature 931 932 uint16_t PlatformTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with platform maximum temperature per VR current rail 933 934 uint16_t TemperatureLimit[TEMP_COUNT]; // In degrees Celsius. Temperature limit associated with each input 935 936 uint16_t HwCtfTempLimit; // In degrees Celsius. Temperature above which HW will trigger CTF. Consumed by VBIOS only 937 938 uint16_t PaddingInfra; 939 940 // Per year normalized Vmax state failure rates (sum of the two domains divided by life time in years) 941 uint32_t FitControllerFailureRateLimit; //in IEEE float 942 //Expected GFX Duty Cycle at Vmax. 943 uint32_t FitControllerGfxDutyCycle; // in IEEE float 944 //Expected SOC Duty Cycle at Vmax. 945 uint32_t FitControllerSocDutyCycle; // in IEEE float 946 947 //This offset will be deducted from the controller output to before it goes through the SOC Vset limiter block. 948 uint32_t FitControllerSocOffset; //in IEEE float 949 950 uint32_t GfxApccPlusResidencyLimit; // Percentage value. Used by APCC+ controller to control PCC residency to some value 951 952 // SECTION: Throttler settings 953 uint32_t ThrottlerControlMask; // See THROTTLER_*_BIT for mapping 954 955 // SECTION: FW DSTATE Settings 956 uint32_t FwDStateMask; // See FW_DSTATE_*_BIT for mapping 957 958 // SECTION: Voltage Control Parameters 959 uint16_t UlvVoltageOffset[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2). ULV offset used in either GFX_ULV or SOC_ULV(part of FW_DSTATE) 960 961 uint16_t UlvVoltageOffsetU; // In mV(Q2). ULV offset used in either U_ULV(part of FW_DSTATE) 962 uint16_t DeepUlvVoltageOffsetSoc; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC as part of FW_DSTATE 963 964 // Voltage Limits 965 uint16_t DefaultMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage without FIT controller enabled 966 uint16_t BoostMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage with FIT controller enabled 967 968 //Vmin Optimizations 969 int16_t VminTempHystersis[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature hysteresis for switching between low/high temperature values for Vmin 970 int16_t VminTempThreshold[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature threshold for switching between low/high temperature values for Vmin 971 uint16_t Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at hot. 972 uint16_t Vmin_Cold_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at cold. 973 uint16_t Vmin_Hot_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at hot. 974 uint16_t Vmin_Cold_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at cold. 975 uint16_t Vmin_Aging_Offset[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Worst-case aging margin 976 uint16_t Spare_Vmin_Plat_Offset_Hot[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Hot 977 uint16_t Spare_Vmin_Plat_Offset_Cold[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Cold 978 979 //This is a fixed/minimum VMIN aging degradation offset which is applied at T0. This reflects the minimum amount of aging already accounted for. 980 uint16_t VcBtcFixedVminAgingOffset[PMFW_VOLT_PLANE_COUNT]; 981 //Linear offset or GB term to account for mis-correlation between PSM and Vmin shift trends across parts. 982 uint16_t VcBtcVmin2PsmDegrationGb[PMFW_VOLT_PLANE_COUNT]; 983 //Scalar coefficient of the PSM aging degradation function 984 uint32_t VcBtcPsmA[PMFW_VOLT_PLANE_COUNT]; // A_PSM 985 //Exponential coefficient of the PSM aging degradation function 986 uint32_t VcBtcPsmB[PMFW_VOLT_PLANE_COUNT]; // B_PSM 987 //Scalar coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 988 uint32_t VcBtcVminA[PMFW_VOLT_PLANE_COUNT]; // A_VMIN 989 //Exponential coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 990 uint32_t VcBtcVminB[PMFW_VOLT_PLANE_COUNT]; // B_VMIN 991 992 uint8_t PerPartVminEnabled[PMFW_VOLT_PLANE_COUNT]; 993 uint8_t VcBtcEnabled[PMFW_VOLT_PLANE_COUNT]; 994 995 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 996 uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 997 998 QuadraticInt_t Vmin_droop; 999 uint32_t SpareVmin[9]; 1000 1001 1002 //SECTION: DPM Configuration 1 1003 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 1004 1005 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1006 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1007 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1008 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1009 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1010 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1011 uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1012 uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1013 uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1014 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1015 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1016 1017 uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1018 1019 // SECTION: DPM Configuration 2 1020 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 1021 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 1022 1023 uint8_t GfxclkSpare[2]; 1024 uint16_t GfxclkFreqCap; 1025 1026 //GFX Idle Power Settings 1027 uint16_t GfxclkFgfxoffEntry; // in Mhz 1028 uint16_t GfxclkFgfxoffExitImu; // in Mhz 1029 uint16_t GfxclkFgfxoffExitRlc; // in Mhz 1030 uint16_t GfxclkThrottleClock; //Used primarily in DCS 1031 uint8_t EnableGfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages 1032 uint8_t GfxIdlePadding; 1033 1034 uint8_t SmsRepairWRCKClkDivEn; 1035 uint8_t SmsRepairWRCKClkDivVal; 1036 uint8_t GfxOffEntryEarlyMGCGEn; 1037 uint8_t GfxOffEntryForceCGCGEn; 1038 uint8_t GfxOffEntryForceCGCGDelayEn; 1039 uint8_t GfxOffEntryForceCGCGDelayVal; // in microseconds 1040 1041 uint16_t GfxclkFreqGfxUlv; // in MHz 1042 uint8_t GfxIdlePadding2[2]; 1043 1044 uint32_t GfxOffEntryHysteresis; 1045 uint32_t GfxoffSpare[15]; 1046 1047 // GFX GPO 1048 uint32_t GfxGpoSpare[16]; 1049 1050 // GFX DCS 1051 1052 uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase 1053 uint16_t PaddingDcs; 1054 1055 uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase 1056 uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. 1057 1058 uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS. 1059 1060 uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. 1061 uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin. 1062 1063 1064 uint32_t DcsSpare[16]; 1065 1066 // UCLK section 1067 uint8_t UseStrobeModeOptimizations; //Set to indicate that FW should use strobe mode optimizations 1068 uint8_t PaddingMem[3]; 1069 1070 uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 1071 uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 1072 1073 uint16_t MemVmempVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1074 uint16_t MemVddioVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1075 1076 //FCLK Section 1077 1078 uint8_t FclkDpmUPstates[NUM_FCLK_DPM_LEVELS]; // U P-state ID associated with each FCLK DPM state. 1079 uint16_t FclkDpmVddU[NUM_FCLK_DPM_LEVELS]; // mV(Q2) Vset U voltage associated with each FCLK DPM state. 1080 uint16_t FclkDpmUSpeed[NUM_FCLK_DPM_LEVELS]; //U speed associated with each FCLK DPM state 1081 uint16_t FclkDpmDisallowPstateFreq; //Frequency which FW will target when indicated that display config cannot support P-state. Set to 0 use FW calculated value 1082 uint16_t PaddingFclk; 1083 1084 // Link DPM Settings 1085 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 1086 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 1087 uint16_t LclkFreq[NUM_LINK_LEVELS]; 1088 1089 // SECTION: Fan Control 1090 uint16_t FanStopTemp[TEMP_COUNT]; //Celsius 1091 uint16_t FanStartTemp[TEMP_COUNT]; //Celsius 1092 1093 uint16_t FanGain[TEMP_COUNT]; 1094 uint16_t FanGainPadding; 1095 1096 uint16_t FanPwmMin; 1097 uint16_t AcousticTargetRpmThreshold; 1098 uint16_t AcousticLimitRpmThreshold; 1099 uint16_t FanMaximumRpm; 1100 uint16_t MGpuAcousticLimitRpmThreshold; 1101 uint16_t FanTargetGfxclk; 1102 uint32_t TempInputSelectMask; 1103 uint8_t FanZeroRpmEnable; 1104 uint8_t FanTachEdgePerRev; 1105 uint16_t FanTargetTemperature[TEMP_COUNT]; 1106 1107 // The following are AFC override parameters. Leave at 0 to use FW defaults. 1108 int16_t FuzzyFan_ErrorSetDelta; 1109 int16_t FuzzyFan_ErrorRateSetDelta; 1110 int16_t FuzzyFan_PwmSetDelta; 1111 uint16_t FuzzyFan_Reserved; 1112 1113 uint16_t FwCtfLimit[TEMP_COUNT]; 1114 1115 uint16_t IntakeTempEnableRPM; 1116 int16_t IntakeTempOffsetTemp; 1117 uint16_t IntakeTempReleaseTemp; 1118 uint16_t IntakeTempHighIntakeAcousticLimit; 1119 uint16_t IntakeTempAcouticLimitReleaseRate; 1120 1121 uint16_t FanStalledTempLimitOffset; 1122 uint16_t FanStalledTriggerRpm; 1123 uint16_t FanAbnormalTriggerRpm; 1124 uint16_t FanPadding; 1125 1126 uint32_t FanSpare[14]; 1127 1128 // SECTION: VDD_GFX AVFS 1129 1130 uint8_t OverrideGfxAvfsFuses; 1131 uint8_t GfxAvfsPadding[3]; 1132 1133 uint32_t L2HwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; //see fusedoc for encoding 1134 uint32_t SeHwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; 1135 1136 uint32_t CommonRtAvfs[PP_GRTAVFS_FW_COMMON_FUSE_COUNT]; 1137 1138 uint32_t L2FwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1139 uint32_t SeFwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1140 1141 uint32_t Droop_PWL_F[PP_NUM_RTAVFS_PWL_ZONES]; 1142 uint32_t Droop_PWL_a[PP_NUM_RTAVFS_PWL_ZONES]; 1143 uint32_t Droop_PWL_b[PP_NUM_RTAVFS_PWL_ZONES]; 1144 uint32_t Droop_PWL_c[PP_NUM_RTAVFS_PWL_ZONES]; 1145 1146 uint32_t Static_PWL_Offset[PP_NUM_RTAVFS_PWL_ZONES]; 1147 1148 uint32_t dGbV_dT_vmin; 1149 uint32_t dGbV_dT_vmax; 1150 1151 //Unused: PMFW-9370 1152 uint32_t V2F_vmin_range_low; 1153 uint32_t V2F_vmin_range_high; 1154 uint32_t V2F_vmax_range_low; 1155 uint32_t V2F_vmax_range_high; 1156 1157 AvfsDcBtcParams_t DcBtcGfxParams; 1158 1159 uint32_t GfxAvfsSpare[32]; 1160 1161 //SECTION: VDD_SOC AVFS 1162 1163 uint8_t OverrideSocAvfsFuses; 1164 uint8_t MinSocAvfsRevision; 1165 uint8_t SocAvfsPadding[2]; 1166 1167 AvfsFuseOverride_t SocAvfsFuseOverride[AVFS_D_COUNT]; 1168 1169 DroopInt_t dBtcGbSoc[AVFS_D_COUNT]; // GHz->V BtcGb 1170 1171 LinearInt_t qAgingGb[AVFS_D_COUNT]; // GHz->V 1172 1173 QuadraticInt_t qStaticVoltageOffset[AVFS_D_COUNT]; // GHz->V 1174 1175 AvfsDcBtcParams_t DcBtcSocParams[AVFS_D_COUNT]; 1176 1177 uint32_t SocAvfsSpare[32]; 1178 1179 //SECTION: Boot clock and voltage values 1180 BootValues_t BootValues; 1181 1182 //SECTION: Driver Reported Clocks 1183 DriverReportedClocks_t DriverReportedClocks; 1184 1185 //SECTION: Message Limits 1186 MsgLimits_t MsgLimits; 1187 1188 //SECTION: OverDrive Limits 1189 OverDriveLimits_t OverDriveLimitsMin; 1190 OverDriveLimits_t OverDriveLimitsBasicMax; 1191 uint32_t reserved[22]; 1192 1193 // SECTION: Advanced Options 1194 uint32_t DebugOverrides; 1195 1196 // SECTION: Sku Reserved 1197 uint32_t Spare[64]; 1198 1199 // Padding for MMHUB - do not modify this 1200 uint32_t MmHubPadding[8]; 1201 1202 } SkuTable_t; 1203 1204 typedef struct { 1205 // SECTION: Version 1206 uint32_t Version; //should be unique to each board type 1207 1208 1209 // SECTION: I2C Control 1210 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 1211 1212 // SECTION: SVI2 Board Parameters 1213 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 1214 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 1215 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 1216 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 1217 1218 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1219 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1220 uint8_t VmempUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1221 uint8_t VddioUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1222 1223 //SECTION SVI3 Board Parameters 1224 uint8_t SlaveAddrMapping[SVI_PLANE_COUNT]; 1225 uint8_t VrPsiSupport[SVI_PLANE_COUNT]; 1226 1227 uint8_t PaddingPsi[SVI_PLANE_COUNT]; 1228 uint8_t EnablePsi6[SVI_PLANE_COUNT]; // only applicable in SVI3 1229 1230 // SECTION: Voltage Regulator Settings 1231 SviTelemetryScale_t SviTelemetryScale[SVI_PLANE_COUNT]; 1232 uint32_t VoltageTelemetryRatio[SVI_PLANE_COUNT]; // This is used for VDDIO Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 1233 1234 uint8_t DownSlewRateVr[SVI_PLANE_COUNT]; 1235 1236 // SECTION: GPIO Settings 1237 1238 uint8_t LedOffGpio; 1239 uint8_t FanOffGpio; 1240 uint8_t GfxVrPowerStageOffGpio; 1241 1242 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 1243 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 1244 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 1245 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 1246 1247 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 1248 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 1249 1250 // LED Display Settings 1251 uint8_t LedPin0; // GPIO number for LedPin[0] 1252 uint8_t LedPin1; // GPIO number for LedPin[1] 1253 uint8_t LedPin2; // GPIO number for LedPin[2] 1254 uint8_t LedEnableMask; 1255 1256 uint8_t LedPcie; // GPIO number for PCIE results 1257 uint8_t LedError; // GPIO number for Error Cases 1258 1259 // SECTION: Clock Spread Spectrum 1260 1261 // UCLK Spread Spectrum 1262 uint16_t UclkSpreadPadding; 1263 uint16_t UclkSpreadFreq; // kHz 1264 1265 // UCLK Spread Spectrum 1266 uint8_t UclkSpreadPercent[MEM_VENDOR_COUNT]; 1267 1268 // FCLK Spread Spectrum 1269 uint8_t FclkSpreadPadding; 1270 uint8_t FclkSpreadPercent; // Q4.4 1271 uint16_t FclkSpreadFreq; // kHz 1272 1273 // Section: Memory Config 1274 uint8_t DramWidth; // Width of interface to the channel for each DRAM module. See DRAM_BIT_WIDTH_TYPE_e 1275 uint8_t PaddingMem1[3]; 1276 1277 // Section: Total Board Power 1278 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 1279 uint16_t BoardPowerPadding; 1280 1281 // SECTION: UMC feature flags 1282 uint8_t HsrEnabled; 1283 uint8_t VddqOffEnabled; 1284 uint8_t PaddingUmcFlags[2]; 1285 1286 uint32_t PostVoltageSetBacoDelay; // in microseconds. Amount of time FW will wait after power good is established or PSI0 command is issued 1287 uint32_t BacoEntryDelay; // in milliseconds. Amount of time FW will wait to trigger BACO entry after receiving entry notification from OS 1288 1289 // SECTION: Board Reserved 1290 uint32_t BoardSpare[64]; 1291 1292 // SECTION: Structure Padding 1293 1294 // Padding for MMHUB - do not modify this 1295 uint32_t MmHubPadding[8]; 1296 } BoardTable_t; 1297 1298 typedef struct { 1299 SkuTable_t SkuTable; 1300 BoardTable_t BoardTable; 1301 } PPTable_t; 1302 1303 typedef struct { 1304 // Time constant parameters for clock averages in ms 1305 uint16_t GfxclkAverageLpfTau; 1306 uint16_t FclkAverageLpfTau; 1307 uint16_t UclkAverageLpfTau; 1308 uint16_t GfxActivityLpfTau; 1309 uint16_t UclkActivityLpfTau; 1310 uint16_t SocketPowerLpfTau; 1311 uint16_t VcnClkAverageLpfTau; 1312 uint16_t VcnUsageAverageLpfTau; 1313 } DriverSmuConfig_t; 1314 1315 typedef struct { 1316 DriverSmuConfig_t DriverSmuConfig; 1317 1318 uint32_t Spare[8]; 1319 // Padding - ignore 1320 uint32_t MmHubPadding[8]; // SMU internal use 1321 } DriverSmuConfigExternal_t; 1322 1323 1324 typedef struct { 1325 1326 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1327 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1328 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1329 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1330 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1331 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1332 uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1333 uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1334 uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1335 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1336 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1337 1338 uint16_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1339 1340 uint16_t Padding; 1341 1342 uint32_t Spare[32]; 1343 1344 // Padding - ignore 1345 uint32_t MmHubPadding[8]; // SMU internal use 1346 1347 } DriverInfoTable_t; 1348 1349 typedef struct { 1350 uint32_t CurrClock[PPCLK_COUNT]; 1351 1352 uint16_t AverageGfxclkFrequencyTarget; 1353 uint16_t AverageGfxclkFrequencyPreDs; 1354 uint16_t AverageGfxclkFrequencyPostDs; 1355 uint16_t AverageFclkFrequencyPreDs; 1356 uint16_t AverageFclkFrequencyPostDs; 1357 uint16_t AverageMemclkFrequencyPreDs ; // this is scaled to actual memory clock 1358 uint16_t AverageMemclkFrequencyPostDs ; // this is scaled to actual memory clock 1359 uint16_t AverageVclk0Frequency ; 1360 uint16_t AverageDclk0Frequency ; 1361 uint16_t AverageVclk1Frequency ; 1362 uint16_t AverageDclk1Frequency ; 1363 uint16_t PCIeBusy; 1364 uint16_t dGPU_W_MAX; 1365 uint16_t padding; 1366 1367 uint32_t MetricsCounter; 1368 1369 uint16_t AvgVoltage[SVI_PLANE_COUNT]; 1370 uint16_t AvgCurrent[SVI_PLANE_COUNT]; 1371 1372 uint16_t AverageGfxActivity ; 1373 uint16_t AverageUclkActivity ; 1374 uint16_t Vcn0ActivityPercentage ; 1375 uint16_t Vcn1ActivityPercentage ; 1376 1377 uint32_t EnergyAccumulator; 1378 uint16_t AverageSocketPower ; 1379 uint16_t AvgTemperature[TEMP_COUNT]; 1380 1381 uint8_t PcieRate ; 1382 uint8_t PcieWidth ; 1383 1384 uint8_t AvgFanPwm; 1385 uint8_t Padding[1]; 1386 uint16_t AvgFanRpm; 1387 1388 1389 uint8_t ThrottlingPercentage[THROTTLER_COUNT]; 1390 1391 //metrics for D3hot entry/exit and driver ARM msgs 1392 uint32_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; 1393 uint32_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT]; 1394 uint32_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT]; 1395 1396 uint16_t ApuSTAPMSmartShiftLimit; 1397 uint16_t ApuSTAPMLimit; 1398 uint16_t AvgApuSocketPower; 1399 1400 uint16_t AverageUclkActivity_MAX; 1401 1402 uint32_t PublicSerialNumberLower; 1403 uint32_t PublicSerialNumberUpper; 1404 1405 } SmuMetrics_t; 1406 1407 typedef struct { 1408 SmuMetrics_t SmuMetrics; 1409 uint32_t Spare[30]; 1410 1411 // Padding - ignore 1412 uint32_t MmHubPadding[8]; // SMU internal use 1413 } SmuMetricsExternal_t; 1414 1415 typedef struct { 1416 uint8_t WmSetting; 1417 uint8_t Flags; 1418 uint8_t Padding[2]; 1419 1420 } WatermarkRowGeneric_t; 1421 1422 #define NUM_WM_RANGES 4 1423 1424 typedef enum { 1425 WATERMARKS_CLOCK_RANGE = 0, 1426 WATERMARKS_DUMMY_PSTATE, 1427 WATERMARKS_MALL, 1428 WATERMARKS_COUNT, 1429 } WATERMARKS_FLAGS_e; 1430 1431 typedef struct { 1432 // Watermarks 1433 WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES]; 1434 } Watermarks_t; 1435 1436 typedef struct { 1437 Watermarks_t Watermarks; 1438 uint32_t Spare[16]; 1439 1440 uint32_t MmHubPadding[8]; // SMU internal use 1441 } WatermarksExternal_t; 1442 1443 typedef struct { 1444 uint16_t avgPsmCount[214]; 1445 uint16_t minPsmCount[214]; 1446 float avgPsmVoltage[214]; 1447 float minPsmVoltage[214]; 1448 } AvfsDebugTable_t; 1449 1450 typedef struct { 1451 AvfsDebugTable_t AvfsDebugTable; 1452 1453 uint32_t MmHubPadding[8]; // SMU internal use 1454 } AvfsDebugTableExternal_t; 1455 1456 1457 typedef struct { 1458 uint8_t Gfx_ActiveHystLimit; 1459 uint8_t Gfx_IdleHystLimit; 1460 uint8_t Gfx_FPS; 1461 uint8_t Gfx_MinActiveFreqType; 1462 uint8_t Gfx_BoosterFreqType; 1463 uint8_t PaddingGfx; 1464 uint16_t Gfx_MinActiveFreq; // MHz 1465 uint16_t Gfx_BoosterFreq; // MHz 1466 uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms 1467 uint32_t Gfx_PD_Data_limit_a; // Q16 1468 uint32_t Gfx_PD_Data_limit_b; // Q16 1469 uint32_t Gfx_PD_Data_limit_c; // Q16 1470 uint32_t Gfx_PD_Data_error_coeff; // Q16 1471 uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 1472 1473 uint8_t Fclk_ActiveHystLimit; 1474 uint8_t Fclk_IdleHystLimit; 1475 uint8_t Fclk_FPS; 1476 uint8_t Fclk_MinActiveFreqType; 1477 uint8_t Fclk_BoosterFreqType; 1478 uint8_t PaddingFclk; 1479 uint16_t Fclk_MinActiveFreq; // MHz 1480 uint16_t Fclk_BoosterFreq; // MHz 1481 uint16_t Fclk_PD_Data_time_constant; // Time constant of PD controller in ms 1482 uint32_t Fclk_PD_Data_limit_a; // Q16 1483 uint32_t Fclk_PD_Data_limit_b; // Q16 1484 uint32_t Fclk_PD_Data_limit_c; // Q16 1485 uint32_t Fclk_PD_Data_error_coeff; // Q16 1486 uint32_t Fclk_PD_Data_error_rate_coeff; // Q16 1487 1488 uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16 1489 uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS]; 1490 uint8_t Mem_DownHystLimit[NUM_UCLK_DPM_LEVELS]; 1491 uint16_t Mem_Fps; 1492 uint8_t padding[2]; 1493 1494 } DpmActivityMonitorCoeffInt_t; 1495 1496 1497 typedef struct { 1498 DpmActivityMonitorCoeffInt_t DpmActivityMonitorCoeffInt; 1499 uint32_t MmHubPadding[8]; // SMU internal use 1500 } DpmActivityMonitorCoeffIntExternal_t; 1501 1502 1503 1504 // Workload bits 1505 #define WORKLOAD_PPLIB_DEFAULT_BIT 0 1506 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 1507 #define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 1508 #define WORKLOAD_PPLIB_VIDEO_BIT 3 1509 #define WORKLOAD_PPLIB_VR_BIT 4 1510 #define WORKLOAD_PPLIB_COMPUTE_BIT 5 1511 #define WORKLOAD_PPLIB_CUSTOM_BIT 6 1512 #define WORKLOAD_PPLIB_WINDOW_3D_BIT 7 1513 #define WORKLOAD_PPLIB_COUNT 8 1514 1515 1516 // These defines are used with the following messages: 1517 // SMC_MSG_TransferTableDram2Smu 1518 // SMC_MSG_TransferTableSmu2Dram 1519 1520 // Table transfer status 1521 #define TABLE_TRANSFER_OK 0x0 1522 #define TABLE_TRANSFER_FAILED 0xFF 1523 #define TABLE_TRANSFER_PENDING 0xAB 1524 1525 // Table types 1526 #define TABLE_PPTABLE 0 1527 #define TABLE_COMBO_PPTABLE 1 1528 #define TABLE_WATERMARKS 2 1529 #define TABLE_AVFS_PSM_DEBUG 3 1530 #define TABLE_PMSTATUSLOG 4 1531 #define TABLE_SMU_METRICS 5 1532 #define TABLE_DRIVER_SMU_CONFIG 6 1533 #define TABLE_ACTIVITY_MONITOR_COEFF 7 1534 #define TABLE_OVERDRIVE 8 1535 #define TABLE_I2C_COMMANDS 9 1536 #define TABLE_DRIVER_INFO 10 1537 #define TABLE_ECCINFO 11 1538 #define TABLE_COUNT 12 1539 1540 //IH Interupt ID 1541 #define IH_INTERRUPT_ID_TO_DRIVER 0xFE 1542 #define IH_INTERRUPT_CONTEXT_ID_BACO 0x2 1543 #define IH_INTERRUPT_CONTEXT_ID_AC 0x3 1544 #define IH_INTERRUPT_CONTEXT_ID_DC 0x4 1545 #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 0x5 1546 #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 0x6 1547 #define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING 0x7 1548 1549 #endif 1550