1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef SMU13_DRIVER_IF_V13_0_0_H 25 #define SMU13_DRIVER_IF_V13_0_0_H 26 27 //Increment this version if SkuTable_t or BoardTable_t change 28 #define PPTABLE_VERSION 0x26 29 30 #define NUM_GFXCLK_DPM_LEVELS 16 31 #define NUM_SOCCLK_DPM_LEVELS 8 32 #define NUM_MP0CLK_DPM_LEVELS 2 33 #define NUM_DCLK_DPM_LEVELS 8 34 #define NUM_VCLK_DPM_LEVELS 8 35 #define NUM_DISPCLK_DPM_LEVELS 8 36 #define NUM_DPPCLK_DPM_LEVELS 8 37 #define NUM_DPREFCLK_DPM_LEVELS 8 38 #define NUM_DCFCLK_DPM_LEVELS 8 39 #define NUM_DTBCLK_DPM_LEVELS 8 40 #define NUM_UCLK_DPM_LEVELS 4 41 #define NUM_LINK_LEVELS 3 42 #define NUM_FCLK_DPM_LEVELS 8 43 #define NUM_OD_FAN_MAX_POINTS 6 44 45 // Feature Control Defines 46 #define FEATURE_FW_DATA_READ_BIT 0 47 #define FEATURE_DPM_GFXCLK_BIT 1 48 #define FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT 2 49 #define FEATURE_DPM_UCLK_BIT 3 50 #define FEATURE_DPM_FCLK_BIT 4 51 #define FEATURE_DPM_SOCCLK_BIT 5 52 #define FEATURE_DPM_MP0CLK_BIT 6 53 #define FEATURE_DPM_LINK_BIT 7 54 #define FEATURE_DPM_DCN_BIT 8 55 #define FEATURE_VMEMP_SCALING_BIT 9 56 #define FEATURE_VDDIO_MEM_SCALING_BIT 10 57 #define FEATURE_DS_GFXCLK_BIT 11 58 #define FEATURE_DS_SOCCLK_BIT 12 59 #define FEATURE_DS_FCLK_BIT 13 60 #define FEATURE_DS_LCLK_BIT 14 61 #define FEATURE_DS_DCFCLK_BIT 15 62 #define FEATURE_DS_UCLK_BIT 16 63 #define FEATURE_GFX_ULV_BIT 17 64 #define FEATURE_FW_DSTATE_BIT 18 65 #define FEATURE_GFXOFF_BIT 19 66 #define FEATURE_BACO_BIT 20 67 #define FEATURE_MM_DPM_BIT 21 68 #define FEATURE_SOC_MPCLK_DS_BIT 22 69 #define FEATURE_BACO_MPCLK_DS_BIT 23 70 #define FEATURE_THROTTLERS_BIT 24 71 #define FEATURE_SMARTSHIFT_BIT 25 72 #define FEATURE_GTHR_BIT 26 73 #define FEATURE_ACDC_BIT 27 74 #define FEATURE_VR0HOT_BIT 28 75 #define FEATURE_FW_CTF_BIT 29 76 #define FEATURE_FAN_CONTROL_BIT 30 77 #define FEATURE_GFX_DCS_BIT 31 78 #define FEATURE_GFX_READ_MARGIN_BIT 32 79 #define FEATURE_LED_DISPLAY_BIT 33 80 #define FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT 34 81 #define FEATURE_OUT_OF_BAND_MONITOR_BIT 35 82 #define FEATURE_OPTIMIZED_VMIN_BIT 36 83 #define FEATURE_GFX_IMU_BIT 37 84 #define FEATURE_BOOT_TIME_CAL_BIT 38 85 #define FEATURE_GFX_PCC_DFLL_BIT 39 86 #define FEATURE_SOC_CG_BIT 40 87 #define FEATURE_DF_CSTATE_BIT 41 88 #define FEATURE_GFX_EDC_BIT 42 89 #define FEATURE_BOOT_POWER_OPT_BIT 43 90 #define FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT 44 91 #define FEATURE_DS_VCN_BIT 45 92 #define FEATURE_BACO_CG_BIT 46 93 #define FEATURE_MEM_TEMP_READ_BIT 47 94 #define FEATURE_ATHUB_MMHUB_PG_BIT 48 95 #define FEATURE_SOC_PCC_BIT 49 96 #define FEATURE_EDC_PWRBRK_BIT 50 97 #define FEATURE_SPARE_51_BIT 51 98 #define FEATURE_SPARE_52_BIT 52 99 #define FEATURE_SPARE_53_BIT 53 100 #define FEATURE_SPARE_54_BIT 54 101 #define FEATURE_SPARE_55_BIT 55 102 #define FEATURE_SPARE_56_BIT 56 103 #define FEATURE_SPARE_57_BIT 57 104 #define FEATURE_SPARE_58_BIT 58 105 #define FEATURE_SPARE_59_BIT 59 106 #define FEATURE_SPARE_60_BIT 60 107 #define FEATURE_SPARE_61_BIT 61 108 #define FEATURE_SPARE_62_BIT 62 109 #define FEATURE_SPARE_63_BIT 63 110 #define NUM_FEATURES 64 111 112 #define ALLOWED_FEATURE_CTRL_DEFAULT 0xFFFFFFFFFFFFFFFFULL 113 #define ALLOWED_FEATURE_CTRL_SCPM ((1 << FEATURE_DPM_GFXCLK_BIT) | \ 114 (1 << FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | \ 115 (1 << FEATURE_DPM_UCLK_BIT) | \ 116 (1 << FEATURE_DPM_FCLK_BIT) | \ 117 (1 << FEATURE_DPM_SOCCLK_BIT) | \ 118 (1 << FEATURE_DPM_MP0CLK_BIT) | \ 119 (1 << FEATURE_DPM_LINK_BIT) | \ 120 (1 << FEATURE_DPM_DCN_BIT) | \ 121 (1 << FEATURE_DS_GFXCLK_BIT) | \ 122 (1 << FEATURE_DS_SOCCLK_BIT) | \ 123 (1 << FEATURE_DS_FCLK_BIT) | \ 124 (1 << FEATURE_DS_LCLK_BIT) | \ 125 (1 << FEATURE_DS_DCFCLK_BIT) | \ 126 (1 << FEATURE_DS_UCLK_BIT) | \ 127 (1ULL << FEATURE_DS_VCN_BIT)) 128 129 //For use with feature control messages 130 typedef enum { 131 FEATURE_PWR_ALL, 132 FEATURE_PWR_S5, 133 FEATURE_PWR_BACO, 134 FEATURE_PWR_SOC, 135 FEATURE_PWR_GFX, 136 FEATURE_PWR_DOMAIN_COUNT, 137 } FEATURE_PWR_DOMAIN_e; 138 139 140 // Debug Overrides Bitmask 141 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000001 142 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK 0x00000002 143 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK 0x00000004 144 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK 0x00000008 145 #define DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x00000010 146 #define DEBUG_OVERRIDE_DISABLE_VCN_PG 0x00000020 147 #define DEBUG_OVERRIDE_DISABLE_FMAX_VMAX 0x00000040 148 #define DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS 0x00000080 149 #define DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK 0x00000100 150 #define DEBUG_OVERRIDE_DISABLE_DFLL 0x00000200 151 #define DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE 0x00000400 152 #define DEBUG_OVERRIDE_DFLL_MASTER_MODE 0x00000800 153 #define DEBUG_OVERRIDE_ENABLE_PROFILING_MODE 0x00001000 154 155 // VR Mapping Bit Defines 156 #define VR_MAPPING_VR_SELECT_MASK 0x01 157 #define VR_MAPPING_VR_SELECT_SHIFT 0x00 158 159 #define VR_MAPPING_PLANE_SELECT_MASK 0x02 160 #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 161 162 // PSI Bit Defines 163 #define PSI_SEL_VR0_PLANE0_PSI0 0x01 164 #define PSI_SEL_VR0_PLANE0_PSI1 0x02 165 #define PSI_SEL_VR0_PLANE1_PSI0 0x04 166 #define PSI_SEL_VR0_PLANE1_PSI1 0x08 167 #define PSI_SEL_VR1_PLANE0_PSI0 0x10 168 #define PSI_SEL_VR1_PLANE0_PSI1 0x20 169 #define PSI_SEL_VR1_PLANE1_PSI0 0x40 170 #define PSI_SEL_VR1_PLANE1_PSI1 0x80 171 172 typedef enum { 173 SVI_PSI_0, // Full phase count (default) 174 SVI_PSI_1, // Phase count 1st level 175 SVI_PSI_2, // Phase count 2nd level 176 SVI_PSI_3, // Single phase operation + active diode emulation 177 SVI_PSI_4, // Single phase operation + passive diode emulation *optional* 178 SVI_PSI_5, // Reserved 179 SVI_PSI_6, // Power down to 0V (voltage regulation disabled) 180 SVI_PSI_7, // Automated phase shedding and diode emulation 181 } SVI_PSI_e; 182 183 // Throttler Control/Status Bits 184 #define THROTTLER_TEMP_EDGE_BIT 0 185 #define THROTTLER_TEMP_HOTSPOT_BIT 1 186 #define THROTTLER_TEMP_HOTSPOT_G_BIT 2 187 #define THROTTLER_TEMP_HOTSPOT_M_BIT 3 188 #define THROTTLER_TEMP_MEM_BIT 4 189 #define THROTTLER_TEMP_VR_GFX_BIT 5 190 #define THROTTLER_TEMP_VR_MEM0_BIT 6 191 #define THROTTLER_TEMP_VR_MEM1_BIT 7 192 #define THROTTLER_TEMP_VR_SOC_BIT 8 193 #define THROTTLER_TEMP_VR_U_BIT 9 194 #define THROTTLER_TEMP_LIQUID0_BIT 10 195 #define THROTTLER_TEMP_LIQUID1_BIT 11 196 #define THROTTLER_TEMP_PLX_BIT 12 197 #define THROTTLER_TDC_GFX_BIT 13 198 #define THROTTLER_TDC_SOC_BIT 14 199 #define THROTTLER_TDC_U_BIT 15 200 #define THROTTLER_PPT0_BIT 16 201 #define THROTTLER_PPT1_BIT 17 202 #define THROTTLER_PPT2_BIT 18 203 #define THROTTLER_PPT3_BIT 19 204 #define THROTTLER_FIT_BIT 20 205 #define THROTTLER_GFX_APCC_PLUS_BIT 21 206 #define THROTTLER_COUNT 22 207 208 // FW DState Features Control Bits 209 #define FW_DSTATE_SOC_ULV_BIT 0 210 #define FW_DSTATE_G6_HSR_BIT 1 211 #define FW_DSTATE_G6_PHY_VMEMP_OFF_BIT 2 212 #define FW_DSTATE_SMN_DS_BIT 3 213 #define FW_DSTATE_MP1_WHISPER_MODE_BIT 4 214 #define FW_DSTATE_SOC_LIV_MIN_BIT 5 215 #define FW_DSTATE_SOC_PLL_PWRDN_BIT 6 216 #define FW_DSTATE_MEM_PLL_PWRDN_BIT 7 217 #define FW_DSTATE_MALL_ALLOC_BIT 8 218 #define FW_DSTATE_MEM_PSI_BIT 9 219 #define FW_DSTATE_HSR_NON_STROBE_BIT 10 220 #define FW_DSTATE_MP0_ENTER_WFI_BIT 11 221 #define FW_DSTATE_U_ULV_BIT 12 222 #define FW_DSTATE_MALL_FLUSH_BIT 13 223 #define FW_DSTATE_SOC_PSI_BIT 14 224 #define FW_DSTATE_U_PSI_BIT 15 225 #define FW_DSTATE_UCP_DS_BIT 16 226 #define FW_DSTATE_CSRCLK_DS_BIT 17 227 #define FW_DSTATE_MMHUB_INTERLOCK_BIT 18 228 #define FW_DSTATE_D0i3_2_QUIET_FW_BIT 19 229 #define FW_DSTATE_CLDO_PRG_BIT 20 230 #define FW_DSTATE_DF_PLL_PWRDN_BIT 21 231 #define FW_DSTATE_U_LOW_PWR_MODE_EN_BIT 22 232 #define FW_DSTATE_GFX_PSI6_BIT 23 233 #define FW_DSTATE_GFX_VR_PWR_STAGE_BIT 24 234 235 //LED Display Mask & Control Bits 236 #define LED_DISPLAY_GFX_DPM_BIT 0 237 #define LED_DISPLAY_PCIE_BIT 1 238 #define LED_DISPLAY_ERROR_BIT 2 239 240 241 #define MEM_TEMP_READ_OUT_OF_BAND_BIT 0 242 #define MEM_TEMP_READ_IN_BAND_REFRESH_BIT 1 243 #define MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT 2 244 245 typedef enum { 246 SMARTSHIFT_VERSION_1, 247 SMARTSHIFT_VERSION_2, 248 SMARTSHIFT_VERSION_3, 249 } SMARTSHIFT_VERSION_e; 250 251 typedef enum { 252 FOPT_CALC_AC_CALC_DC, 253 FOPT_PPTABLE_AC_CALC_DC, 254 FOPT_CALC_AC_PPTABLE_DC, 255 FOPT_PPTABLE_AC_PPTABLE_DC, 256 } FOPT_CALC_e; 257 258 typedef enum { 259 DRAM_BIT_WIDTH_DISABLED = 0, 260 DRAM_BIT_WIDTH_X_8 = 8, 261 DRAM_BIT_WIDTH_X_16 = 16, 262 DRAM_BIT_WIDTH_X_32 = 32, 263 DRAM_BIT_WIDTH_X_64 = 64, 264 DRAM_BIT_WIDTH_X_128 = 128, 265 DRAM_BIT_WIDTH_COUNT, 266 } DRAM_BIT_WIDTH_TYPE_e; 267 268 //I2C Interface 269 #define NUM_I2C_CONTROLLERS 8 270 271 #define I2C_CONTROLLER_ENABLED 1 272 #define I2C_CONTROLLER_DISABLED 0 273 274 #define MAX_SW_I2C_COMMANDS 24 275 276 typedef enum { 277 I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0 278 I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1 279 I2C_CONTROLLER_PORT_COUNT, 280 } I2cControllerPort_e; 281 282 typedef enum { 283 I2C_CONTROLLER_NAME_VR_GFX = 0, 284 I2C_CONTROLLER_NAME_VR_SOC, 285 I2C_CONTROLLER_NAME_VR_VMEMP, 286 I2C_CONTROLLER_NAME_VR_VDDIO, 287 I2C_CONTROLLER_NAME_LIQUID0, 288 I2C_CONTROLLER_NAME_LIQUID1, 289 I2C_CONTROLLER_NAME_PLX, 290 I2C_CONTROLLER_NAME_FAN_INTAKE, 291 I2C_CONTROLLER_NAME_COUNT, 292 } I2cControllerName_e; 293 294 typedef enum { 295 I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 296 I2C_CONTROLLER_THROTTLER_VR_GFX, 297 I2C_CONTROLLER_THROTTLER_VR_SOC, 298 I2C_CONTROLLER_THROTTLER_VR_VMEMP, 299 I2C_CONTROLLER_THROTTLER_VR_VDDIO, 300 I2C_CONTROLLER_THROTTLER_LIQUID0, 301 I2C_CONTROLLER_THROTTLER_LIQUID1, 302 I2C_CONTROLLER_THROTTLER_PLX, 303 I2C_CONTROLLER_THROTTLER_FAN_INTAKE, 304 I2C_CONTROLLER_THROTTLER_INA3221, 305 I2C_CONTROLLER_THROTTLER_COUNT, 306 } I2cControllerThrottler_e; 307 308 typedef enum { 309 I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5, 310 I2C_CONTROLLER_PROTOCOL_VR_IR35217, 311 I2C_CONTROLLER_PROTOCOL_TMP_MAX31875, 312 I2C_CONTROLLER_PROTOCOL_INA3221, 313 I2C_CONTROLLER_PROTOCOL_COUNT, 314 } I2cControllerProtocol_e; 315 316 typedef struct { 317 uint8_t Enabled; 318 uint8_t Speed; 319 uint8_t SlaveAddress; 320 uint8_t ControllerPort; 321 uint8_t ControllerName; 322 uint8_t ThermalThrotter; 323 uint8_t I2cProtocol; 324 uint8_t PaddingConfig; 325 } I2cControllerConfig_t; 326 327 typedef enum { 328 I2C_PORT_SVD_SCL = 0, 329 I2C_PORT_GPIO, 330 } I2cPort_e; 331 332 typedef enum { 333 I2C_SPEED_FAST_50K = 0, //50 Kbits/s 334 I2C_SPEED_FAST_100K, //100 Kbits/s 335 I2C_SPEED_FAST_400K, //400 Kbits/s 336 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 337 I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 338 I2C_SPEED_HIGH_2M, //2.3 Mbits/s 339 I2C_SPEED_COUNT, 340 } I2cSpeed_e; 341 342 typedef enum { 343 I2C_CMD_READ = 0, 344 I2C_CMD_WRITE, 345 I2C_CMD_COUNT, 346 } I2cCmdType_e; 347 348 #define CMDCONFIG_STOP_BIT 0 349 #define CMDCONFIG_RESTART_BIT 1 350 #define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write 351 352 #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 353 #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 354 #define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT) 355 356 typedef struct { 357 uint8_t ReadWriteData; //Return data for read. Data to send for write 358 uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write 359 } SwI2cCmd_t; //SW I2C Command Table 360 361 typedef struct { 362 uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 363 uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select 364 uint8_t SlaveAddress; //Slave address of device 365 uint8_t NumCmds; //Number of commands 366 367 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 368 } SwI2cRequest_t; // SW I2C Request Table 369 370 typedef struct { 371 SwI2cRequest_t SwI2cRequest; 372 373 uint32_t Spare[8]; 374 uint32_t MmHubPadding[8]; // SMU internal use 375 } SwI2cRequestExternal_t; 376 377 typedef struct { 378 uint64_t mca_umc_status; 379 uint64_t mca_umc_addr; 380 381 uint16_t ce_count_lo_chip; 382 uint16_t ce_count_hi_chip; 383 384 uint32_t eccPadding; 385 } EccInfo_t; 386 387 typedef struct { 388 EccInfo_t EccInfo[24]; 389 } EccInfoTable_t; 390 391 //D3HOT sequences 392 typedef enum { 393 BACO_SEQUENCE, 394 MSR_SEQUENCE, 395 BAMACO_SEQUENCE, 396 ULPS_SEQUENCE, 397 D3HOT_SEQUENCE_COUNT, 398 } D3HOTSequence_e; 399 400 //This is aligned with RSMU PGFSM Register Mapping 401 typedef enum { 402 PG_DYNAMIC_MODE = 0, 403 PG_STATIC_MODE, 404 } PowerGatingMode_e; 405 406 //This is aligned with RSMU PGFSM Register Mapping 407 typedef enum { 408 PG_POWER_DOWN = 0, 409 PG_POWER_UP, 410 } PowerGatingSettings_e; 411 412 typedef struct { 413 uint32_t a; // store in IEEE float format in this variable 414 uint32_t b; // store in IEEE float format in this variable 415 uint32_t c; // store in IEEE float format in this variable 416 } QuadraticInt_t; 417 418 typedef struct { 419 uint32_t m; // store in IEEE float format in this variable 420 uint32_t b; // store in IEEE float format in this variable 421 } LinearInt_t; 422 423 typedef struct { 424 uint32_t a; // store in IEEE float format in this variable 425 uint32_t b; // store in IEEE float format in this variable 426 uint32_t c; // store in IEEE float format in this variable 427 } DroopInt_t; 428 429 typedef enum { 430 DCS_ARCH_DISABLED, 431 DCS_ARCH_FADCS, 432 DCS_ARCH_ASYNC, 433 } DCS_ARCH_e; 434 435 //Only Clks that have DPM descriptors are listed here 436 typedef enum { 437 PPCLK_GFXCLK = 0, 438 PPCLK_SOCCLK, 439 PPCLK_UCLK, 440 PPCLK_FCLK, 441 PPCLK_DCLK_0, 442 PPCLK_VCLK_0, 443 PPCLK_DCLK_1, 444 PPCLK_VCLK_1, 445 PPCLK_DISPCLK, 446 PPCLK_DPPCLK, 447 PPCLK_DPREFCLK, 448 PPCLK_DCFCLK, 449 PPCLK_DTBCLK, 450 PPCLK_COUNT, 451 } PPCLK_e; 452 453 typedef enum { 454 VOLTAGE_MODE_PPTABLE = 0, 455 VOLTAGE_MODE_FUSES, 456 VOLTAGE_MODE_COUNT, 457 } VOLTAGE_MODE_e; 458 459 460 typedef enum { 461 AVFS_VOLTAGE_GFX = 0, 462 AVFS_VOLTAGE_SOC, 463 AVFS_VOLTAGE_COUNT, 464 } AVFS_VOLTAGE_TYPE_e; 465 466 typedef enum { 467 AVFS_TEMP_COLD = 0, 468 AVFS_TEMP_HOT, 469 AVFS_TEMP_COUNT, 470 } AVFS_TEMP_e; 471 472 typedef enum { 473 AVFS_D_G, 474 AVFS_D_M_B, 475 AVFS_D_M_S, 476 AVFS_D_COUNT, 477 } AVFS_D_e; 478 479 typedef enum { 480 UCLK_DIV_BY_1 = 0, 481 UCLK_DIV_BY_2, 482 UCLK_DIV_BY_4, 483 UCLK_DIV_BY_8, 484 } UCLK_DIV_e; 485 486 typedef enum { 487 GPIO_INT_POLARITY_ACTIVE_LOW = 0, 488 GPIO_INT_POLARITY_ACTIVE_HIGH, 489 } GpioIntPolarity_e; 490 491 typedef enum { 492 PWR_CONFIG_TDP = 0, 493 PWR_CONFIG_TGP, 494 PWR_CONFIG_TCP_ESTIMATED, 495 PWR_CONFIG_TCP_MEASURED, 496 } PwrConfig_e; 497 498 typedef struct { 499 uint8_t Padding; 500 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 501 uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 502 uint8_t CalculateFopt; // Indication whether FW should calculate Fopt or use values below. Reference FOPT_CALC_e 503 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 504 uint32_t Padding3[3]; 505 uint16_t Padding4; 506 uint16_t FoptimalDc; //Foptimal frequency in DC power mode. 507 uint16_t FoptimalAc; //Foptimal frequency in AC power mode. 508 uint16_t Padding2; 509 } DpmDescriptor_t; 510 511 typedef enum { 512 PPT_THROTTLER_PPT0, 513 PPT_THROTTLER_PPT1, 514 PPT_THROTTLER_PPT2, 515 PPT_THROTTLER_PPT3, 516 PPT_THROTTLER_COUNT 517 } PPT_THROTTLER_e; 518 519 typedef enum { 520 TEMP_EDGE, 521 TEMP_HOTSPOT, 522 TEMP_HOTSPOT_G, 523 TEMP_HOTSPOT_M, 524 TEMP_MEM, 525 TEMP_VR_GFX, 526 TEMP_VR_MEM0, 527 TEMP_VR_MEM1, 528 TEMP_VR_SOC, 529 TEMP_VR_U, 530 TEMP_LIQUID0, 531 TEMP_LIQUID1, 532 TEMP_PLX, 533 TEMP_COUNT, 534 } TEMP_e; 535 536 typedef enum { 537 TDC_THROTTLER_GFX, 538 TDC_THROTTLER_SOC, 539 TDC_THROTTLER_U, 540 TDC_THROTTLER_COUNT 541 } TDC_THROTTLER_e; 542 543 typedef enum { 544 SVI_PLANE_GFX, 545 SVI_PLANE_SOC, 546 SVI_PLANE_VMEMP, 547 SVI_PLANE_VDDIO_MEM, 548 SVI_PLANE_U, 549 SVI_PLANE_COUNT, 550 } SVI_PLANE_e; 551 552 typedef enum { 553 PMFW_VOLT_PLANE_GFX, 554 PMFW_VOLT_PLANE_SOC, 555 PMFW_VOLT_PLANE_COUNT 556 } PMFW_VOLT_PLANE_e; 557 558 typedef enum { 559 CUSTOMER_VARIANT_ROW, 560 CUSTOMER_VARIANT_FALCON, 561 CUSTOMER_VARIANT_COUNT, 562 } CUSTOMER_VARIANT_e; 563 564 typedef enum { 565 POWER_SOURCE_AC, 566 POWER_SOURCE_DC, 567 POWER_SOURCE_COUNT, 568 } POWER_SOURCE_e; 569 570 typedef enum { 571 MEM_VENDOR_SAMSUNG, 572 MEM_VENDOR_INFINEON, 573 MEM_VENDOR_ELPIDA, 574 MEM_VENDOR_ETRON, 575 MEM_VENDOR_NANYA, 576 MEM_VENDOR_HYNIX, 577 MEM_VENDOR_MOSEL, 578 MEM_VENDOR_WINBOND, 579 MEM_VENDOR_ESMT, 580 MEM_VENDOR_PLACEHOLDER0, 581 MEM_VENDOR_PLACEHOLDER1, 582 MEM_VENDOR_PLACEHOLDER2, 583 MEM_VENDOR_PLACEHOLDER3, 584 MEM_VENDOR_PLACEHOLDER4, 585 MEM_VENDOR_PLACEHOLDER5, 586 MEM_VENDOR_MICRON, 587 MEM_VENDOR_COUNT, 588 } MEM_VENDOR_e; 589 590 typedef enum { 591 PP_GRTAVFS_HW_CPO_CTL_ZONE0, 592 PP_GRTAVFS_HW_CPO_CTL_ZONE1, 593 PP_GRTAVFS_HW_CPO_CTL_ZONE2, 594 PP_GRTAVFS_HW_CPO_CTL_ZONE3, 595 PP_GRTAVFS_HW_CPO_CTL_ZONE4, 596 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0, 597 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0, 598 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1, 599 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1, 600 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2, 601 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2, 602 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3, 603 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3, 604 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4, 605 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4, 606 PP_GRTAVFS_HW_ZONE0_VF, 607 PP_GRTAVFS_HW_ZONE1_VF1, 608 PP_GRTAVFS_HW_ZONE2_VF2, 609 PP_GRTAVFS_HW_ZONE3_VF3, 610 PP_GRTAVFS_HW_VOLTAGE_GB, 611 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0, 612 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1, 613 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2, 614 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3, 615 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4, 616 PP_GRTAVFS_HW_RESERVED_0, 617 PP_GRTAVFS_HW_RESERVED_1, 618 PP_GRTAVFS_HW_RESERVED_2, 619 PP_GRTAVFS_HW_RESERVED_3, 620 PP_GRTAVFS_HW_RESERVED_4, 621 PP_GRTAVFS_HW_RESERVED_5, 622 PP_GRTAVFS_HW_RESERVED_6, 623 PP_GRTAVFS_HW_FUSE_COUNT, 624 } PP_GRTAVFS_HW_FUSE_e; 625 626 typedef enum { 627 PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0, 628 PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0, 629 PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0, 630 PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0, 631 PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0, 632 PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0, 633 PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0, 634 PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0, 635 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0, 636 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1, 637 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2, 638 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3, 639 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4, 640 PP_GRTAVFS_FW_COMMON_FUSE_COUNT, 641 } PP_GRTAVFS_FW_COMMON_FUSE_e; 642 643 typedef enum { 644 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1, 645 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0, 646 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1, 647 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2, 648 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3, 649 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4, 650 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1, 651 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0, 652 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1, 653 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2, 654 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3, 655 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4, 656 PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY, 657 PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY, 658 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0, 659 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1, 660 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2, 661 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3, 662 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4, 663 PP_GRTAVFS_FW_SEP_FUSE_COUNT, 664 } PP_GRTAVFS_FW_SEP_FUSE_e; 665 666 #define PP_NUM_RTAVFS_PWL_ZONES 5 667 668 669 670 // VBIOS or PPLIB configures telemetry slope and offset. Only slope expected to be set for SVI3 671 // Slope Q1.7, Offset Q1.2 672 typedef struct { 673 int8_t Offset; // in Amps 674 uint8_t Padding; 675 uint16_t MaxCurrent; // in Amps 676 } SviTelemetryScale_t; 677 678 #define PP_NUM_OD_VF_CURVE_POINTS PP_NUM_RTAVFS_PWL_ZONES + 1 679 680 typedef enum { 681 FAN_MODE_AUTO = 0, 682 FAN_MODE_MANUAL_LINEAR, 683 } FanMode_e; 684 685 typedef struct { 686 uint32_t FeatureCtrlMask; 687 688 //Voltage control 689 int16_t VoltageOffsetPerZoneBoundary[PP_NUM_OD_VF_CURVE_POINTS]; 690 uint16_t VddGfxVmax; // in mV 691 692 uint8_t IdlePwrSavingFeaturesCtrl; 693 uint8_t RuntimePwrSavingFeaturesCtrl; 694 695 //Frequency changes 696 int16_t GfxclkFmin; // MHz 697 int16_t GfxclkFmax; // MHz 698 uint16_t UclkFmin; // MHz 699 uint16_t UclkFmax; // MHz 700 701 //PPT 702 int16_t Ppt; // % 703 int16_t Tdc; 704 705 //Fan control 706 uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS]; 707 uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS]; 708 uint16_t FanMinimumPwm; 709 uint16_t AcousticTargetRpmThreshold; 710 uint16_t AcousticLimitRpmThreshold; 711 uint16_t FanTargetTemperature; // Degree Celcius 712 uint8_t FanZeroRpmEnable; 713 uint8_t FanZeroRpmStopTemp; 714 uint8_t FanMode; 715 uint8_t MaxOpTemp; 716 717 uint32_t Spare[13]; 718 uint32_t MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround 719 } OverDriveTable_t; 720 721 typedef struct { 722 OverDriveTable_t OverDriveTable; 723 724 } OverDriveTableExternal_t; 725 726 typedef struct { 727 uint32_t FeatureCtrlMask; 728 729 int16_t VoltageOffsetPerZoneBoundary; 730 uint16_t VddGfxVmax; // in mV 731 732 uint8_t IdlePwrSavingFeaturesCtrl; 733 uint8_t RuntimePwrSavingFeaturesCtrl; 734 735 int16_t GfxclkFmin; // MHz 736 int16_t GfxclkFmax; // MHz 737 uint16_t UclkFmin; // MHz 738 uint16_t UclkFmax; // MHz 739 740 //PPT 741 int16_t Ppt; // % 742 int16_t Tdc; 743 744 uint8_t FanLinearPwmPoints; 745 uint8_t FanLinearTempPoints; 746 uint16_t FanMinimumPwm; 747 uint16_t AcousticTargetRpmThreshold; 748 uint16_t AcousticLimitRpmThreshold; 749 uint16_t FanTargetTemperature; // Degree Celcius 750 uint8_t FanZeroRpmEnable; 751 uint8_t FanZeroRpmStopTemp; 752 uint8_t FanMode; 753 uint8_t MaxOpTemp; 754 755 uint32_t Spare[13]; 756 757 } OverDriveLimits_t; 758 759 760 typedef enum { 761 BOARD_GPIO_SMUIO_0, 762 BOARD_GPIO_SMUIO_1, 763 BOARD_GPIO_SMUIO_2, 764 BOARD_GPIO_SMUIO_3, 765 BOARD_GPIO_SMUIO_4, 766 BOARD_GPIO_SMUIO_5, 767 BOARD_GPIO_SMUIO_6, 768 BOARD_GPIO_SMUIO_7, 769 BOARD_GPIO_SMUIO_8, 770 BOARD_GPIO_SMUIO_9, 771 BOARD_GPIO_SMUIO_10, 772 BOARD_GPIO_SMUIO_11, 773 BOARD_GPIO_SMUIO_12, 774 BOARD_GPIO_SMUIO_13, 775 BOARD_GPIO_SMUIO_14, 776 BOARD_GPIO_SMUIO_15, 777 BOARD_GPIO_SMUIO_16, 778 BOARD_GPIO_SMUIO_17, 779 BOARD_GPIO_SMUIO_18, 780 BOARD_GPIO_SMUIO_19, 781 BOARD_GPIO_SMUIO_20, 782 BOARD_GPIO_SMUIO_21, 783 BOARD_GPIO_SMUIO_22, 784 BOARD_GPIO_SMUIO_23, 785 BOARD_GPIO_SMUIO_24, 786 BOARD_GPIO_SMUIO_25, 787 BOARD_GPIO_SMUIO_26, 788 BOARD_GPIO_SMUIO_27, 789 BOARD_GPIO_SMUIO_28, 790 BOARD_GPIO_SMUIO_29, 791 BOARD_GPIO_SMUIO_30, 792 BOARD_GPIO_SMUIO_31, 793 MAX_BOARD_GPIO_SMUIO_NUM, 794 BOARD_GPIO_DC_GEN_A, 795 BOARD_GPIO_DC_GEN_B, 796 BOARD_GPIO_DC_GEN_C, 797 BOARD_GPIO_DC_GEN_D, 798 BOARD_GPIO_DC_GEN_E, 799 BOARD_GPIO_DC_GEN_F, 800 BOARD_GPIO_DC_GEN_G, 801 BOARD_GPIO_DC_GENLK_CLK, 802 BOARD_GPIO_DC_GENLK_VSYNC, 803 BOARD_GPIO_DC_SWAPLOCK_A, 804 BOARD_GPIO_DC_SWAPLOCK_B, 805 } BOARD_GPIO_TYPE_e; 806 807 #define INVALID_BOARD_GPIO 0xFF 808 809 810 typedef struct { 811 //PLL 0 812 uint16_t InitGfxclk_bypass; 813 uint16_t InitSocclk; 814 uint16_t InitMp0clk; 815 uint16_t InitMpioclk; 816 uint16_t InitSmnclk; 817 uint16_t InitUcpclk; 818 uint16_t InitCsrclk; 819 //PLL 1 820 821 uint16_t InitDprefclk; 822 uint16_t InitDcfclk; 823 uint16_t InitDtbclk; 824 //PLL 2 825 uint16_t InitDclk; //assume same DCLK/VCLK for both instances 826 uint16_t InitVclk; 827 // PLL 3 828 uint16_t InitUsbdfsclk; 829 uint16_t InitMp1clk; 830 uint16_t InitLclk; 831 uint16_t InitBaco400clk_bypass; 832 uint16_t InitBaco1200clk_bypass; 833 uint16_t InitBaco700clk_bypass; 834 // PLL 4 835 uint16_t InitFclk; 836 // PLL 5 837 uint16_t InitGfxclk_clkb; 838 839 //PLL 6 840 uint8_t InitUclkDPMState; // =0,1,2,3, frequency from FreqTableUclk 841 842 uint8_t Padding[3]; 843 844 uint32_t InitVcoFreqPll0; 845 uint32_t InitVcoFreqPll1; 846 uint32_t InitVcoFreqPll2; 847 uint32_t InitVcoFreqPll3; 848 uint32_t InitVcoFreqPll4; 849 uint32_t InitVcoFreqPll5; 850 uint32_t InitVcoFreqPll6; 851 852 //encoding will change depending on SVI2/SVI3 853 uint16_t InitGfx; // In mV(Q2) , should be 0? 854 uint16_t InitSoc; // In mV(Q2) 855 uint16_t InitU; // In Mv(Q2) 856 857 uint16_t Padding2; 858 859 uint32_t Spare[8]; 860 861 } BootValues_t; 862 863 864 typedef struct { 865 uint16_t Power[PPT_THROTTLER_COUNT][POWER_SOURCE_COUNT]; // Watts 866 uint16_t Tdc[TDC_THROTTLER_COUNT]; // Amps 867 868 uint16_t Temperature[TEMP_COUNT]; // Celsius 869 870 uint8_t PwmLimitMin; 871 uint8_t PwmLimitMax; 872 uint8_t FanTargetTemperature; 873 uint8_t Spare1[1]; 874 875 uint16_t AcousticTargetRpmThresholdMin; 876 uint16_t AcousticTargetRpmThresholdMax; 877 878 uint16_t AcousticLimitRpmThresholdMin; 879 uint16_t AcousticLimitRpmThresholdMax; 880 881 uint16_t PccLimitMin; 882 uint16_t PccLimitMax; 883 884 uint16_t FanStopTempMin; 885 uint16_t FanStopTempMax; 886 uint16_t FanStartTempMin; 887 uint16_t FanStartTempMax; 888 889 uint16_t PowerMinPpt0[POWER_SOURCE_COUNT]; 890 uint32_t Spare[11]; 891 892 } MsgLimits_t; 893 894 typedef struct { 895 uint16_t BaseClockAc; 896 uint16_t GameClockAc; 897 uint16_t BoostClockAc; 898 uint16_t BaseClockDc; 899 uint16_t GameClockDc; 900 uint16_t BoostClockDc; 901 902 uint32_t Reserved[4]; 903 } DriverReportedClocks_t; 904 905 typedef struct { 906 uint8_t DcBtcEnabled; 907 uint8_t Padding[3]; 908 909 uint16_t DcTol; // mV Q2 910 uint16_t DcBtcGb; // mV Q2 911 912 uint16_t DcBtcMin; // mV Q2 913 uint16_t DcBtcMax; // mV Q2 914 915 LinearInt_t DcBtcGbScalar; 916 917 } AvfsDcBtcParams_t; 918 919 typedef struct { 920 uint16_t AvfsTemp[AVFS_TEMP_COUNT]; //in degrees C 921 uint16_t VftFMin; // in MHz 922 uint16_t VInversion; // in mV Q2 923 QuadraticInt_t qVft[AVFS_TEMP_COUNT]; 924 QuadraticInt_t qAvfsGb; 925 QuadraticInt_t qAvfsGb2; 926 } AvfsFuseOverride_t; 927 928 typedef struct { 929 // SECTION: Version 930 931 uint32_t Version; // should be unique to each SKU(i.e if any value changes in below structure then this value must be different) 932 933 // SECTION: Feature Control 934 uint32_t FeaturesToRun[NUM_FEATURES / 32]; // Features that PMFW will attempt to enable. Use FEATURE_*_BIT as mapping 935 936 // SECTION: Miscellaneous Configuration 937 uint8_t TotalPowerConfig; // Determines how PMFW calculates the power. Use defines from PwrConfig_e 938 uint8_t CustomerVariant; //To specify if this PPTable is intended for a particular customer. Use defines from CUSTOMER_VARIANT_e 939 uint8_t MemoryTemperatureTypeMask; // Bit mapping indicating which methods of memory temperature reading are enabled. Use defines from MEM_TEMP_*BIT 940 uint8_t SmartShiftVersion; // Determine what SmartShift feature version is supported Use defines from SMARTSHIFT_VERSION_e 941 942 // SECTION: Infrastructure Limits 943 uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in AC mode. Multiple limits supported 944 uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in DC mode. Multiple limits supported 945 946 uint16_t SocketPowerLimitSmartShift2; // In Watts. Power limit used SmartShift 947 948 //if set to 1, SocketPowerLimitAc and SocketPowerLimitDc will be interpreted as legacy programs(i.e absolute power). If 0, all except index 0 will be scalars 949 //relative index 0 950 uint8_t EnableLegacyPptLimit; 951 uint8_t UseInputTelemetry; //applicable to SVI3 only and only to be set if VRs support 952 uint8_t SmartShiftMinReportedPptinDcs; //minimum possible active power consumption for this SKU. Used for SmartShift power reporting 953 954 uint8_t PaddingPpt[1]; 955 956 uint16_t VrTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with VR regulator maximum temperature 957 958 uint16_t PlatformTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with platform maximum temperature per VR current rail 959 960 uint16_t TemperatureLimit[TEMP_COUNT]; // In degrees Celsius. Temperature limit associated with each input 961 962 uint16_t HwCtfTempLimit; // In degrees Celsius. Temperature above which HW will trigger CTF. Consumed by VBIOS only 963 964 uint16_t PaddingInfra; 965 966 // Per year normalized Vmax state failure rates (sum of the two domains divided by life time in years) 967 uint32_t FitControllerFailureRateLimit; //in IEEE float 968 //Expected GFX Duty Cycle at Vmax. 969 uint32_t FitControllerGfxDutyCycle; // in IEEE float 970 //Expected SOC Duty Cycle at Vmax. 971 uint32_t FitControllerSocDutyCycle; // in IEEE float 972 973 //This offset will be deducted from the controller output to before it goes through the SOC Vset limiter block. 974 uint32_t FitControllerSocOffset; //in IEEE float 975 976 uint32_t GfxApccPlusResidencyLimit; // Percentage value. Used by APCC+ controller to control PCC residency to some value 977 978 // SECTION: Throttler settings 979 uint32_t ThrottlerControlMask; // See THROTTLER_*_BIT for mapping 980 981 // SECTION: FW DSTATE Settings 982 uint32_t FwDStateMask; // See FW_DSTATE_*_BIT for mapping 983 984 // SECTION: Voltage Control Parameters 985 uint16_t UlvVoltageOffset[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2). ULV offset used in either GFX_ULV or SOC_ULV(part of FW_DSTATE) 986 987 uint16_t UlvVoltageOffsetU; // In mV(Q2). ULV offset used in either U_ULV(part of FW_DSTATE) 988 uint16_t DeepUlvVoltageOffsetSoc; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC as part of FW_DSTATE 989 990 // Voltage Limits 991 uint16_t DefaultMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage without FIT controller enabled 992 uint16_t BoostMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage with FIT controller enabled 993 994 //Vmin Optimizations 995 int16_t VminTempHystersis[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature hysteresis for switching between low/high temperature values for Vmin 996 int16_t VminTempThreshold[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature threshold for switching between low/high temperature values for Vmin 997 uint16_t Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at hot. 998 uint16_t Vmin_Cold_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at cold. 999 uint16_t Vmin_Hot_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at hot. 1000 uint16_t Vmin_Cold_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at cold. 1001 uint16_t Vmin_Aging_Offset[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Worst-case aging margin 1002 uint16_t Spare_Vmin_Plat_Offset_Hot[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Hot 1003 uint16_t Spare_Vmin_Plat_Offset_Cold[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Cold 1004 1005 //This is a fixed/minimum VMIN aging degradation offset which is applied at T0. This reflects the minimum amount of aging already accounted for. 1006 uint16_t VcBtcFixedVminAgingOffset[PMFW_VOLT_PLANE_COUNT]; 1007 //Linear offset or GB term to account for mis-correlation between PSM and Vmin shift trends across parts. 1008 uint16_t VcBtcVmin2PsmDegrationGb[PMFW_VOLT_PLANE_COUNT]; 1009 //Scalar coefficient of the PSM aging degradation function 1010 uint32_t VcBtcPsmA[PMFW_VOLT_PLANE_COUNT]; // A_PSM 1011 //Exponential coefficient of the PSM aging degradation function 1012 uint32_t VcBtcPsmB[PMFW_VOLT_PLANE_COUNT]; // B_PSM 1013 //Scalar coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 1014 uint32_t VcBtcVminA[PMFW_VOLT_PLANE_COUNT]; // A_VMIN 1015 //Exponential coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 1016 uint32_t VcBtcVminB[PMFW_VOLT_PLANE_COUNT]; // B_VMIN 1017 1018 uint8_t PerPartVminEnabled[PMFW_VOLT_PLANE_COUNT]; 1019 uint8_t VcBtcEnabled[PMFW_VOLT_PLANE_COUNT]; 1020 1021 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 1022 uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 1023 1024 QuadraticInt_t Vmin_droop; 1025 uint32_t SpareVmin[9]; 1026 1027 1028 //SECTION: DPM Configuration 1 1029 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 1030 1031 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1032 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1033 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1034 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1035 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1036 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1037 uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1038 uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1039 uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1040 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1041 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1042 1043 uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1044 1045 // SECTION: DPM Configuration 2 1046 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 1047 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 1048 1049 uint8_t GfxclkSpare[2]; 1050 uint16_t GfxclkFreqCap; 1051 1052 //GFX Idle Power Settings 1053 uint16_t GfxclkFgfxoffEntry; // in Mhz 1054 uint16_t GfxclkFgfxoffExitImu; // in Mhz 1055 uint16_t GfxclkFgfxoffExitRlc; // in Mhz 1056 uint16_t GfxclkThrottleClock; //Used primarily in DCS 1057 uint8_t EnableGfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages 1058 uint8_t GfxIdlePadding; 1059 1060 uint8_t SmsRepairWRCKClkDivEn; 1061 uint8_t SmsRepairWRCKClkDivVal; 1062 uint8_t GfxOffEntryEarlyMGCGEn; 1063 uint8_t GfxOffEntryForceCGCGEn; 1064 uint8_t GfxOffEntryForceCGCGDelayEn; 1065 uint8_t GfxOffEntryForceCGCGDelayVal; // in microseconds 1066 1067 uint16_t GfxclkFreqGfxUlv; // in MHz 1068 uint8_t GfxIdlePadding2[2]; 1069 1070 uint32_t GfxOffEntryHysteresis; 1071 uint32_t GfxoffSpare[15]; 1072 1073 // GFX GPO 1074 uint32_t DfllBtcMasterScalerM; 1075 int32_t DfllBtcMasterScalerB; 1076 uint32_t DfllBtcSlaveScalerM; 1077 int32_t DfllBtcSlaveScalerB; 1078 1079 uint32_t DfllPccAsWaitCtrl; //GDFLL_AS_WAIT_CTRL_PCC register value to be passed to RLC msg 1080 uint32_t DfllPccAsStepCtrl; //GDFLL_AS_STEP_CTRL_PCC register value to be passed to RLC msg 1081 1082 uint32_t DfllL2FrequencyBoostM; //Unitless (float) 1083 uint32_t DfllL2FrequencyBoostB; //In MHz (integer) 1084 uint32_t GfxGpoSpare[8]; 1085 1086 // GFX DCS 1087 1088 uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase 1089 uint16_t PaddingDcs; 1090 1091 uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase 1092 uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. 1093 1094 uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS. 1095 1096 uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. 1097 uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin. 1098 1099 1100 uint32_t DcsSpare[16]; 1101 1102 // UCLK section 1103 uint8_t UseStrobeModeOptimizations; //Set to indicate that FW should use strobe mode optimizations 1104 uint8_t PaddingMem[3]; 1105 1106 uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 1107 uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 1108 1109 uint16_t MemVmempVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1110 uint16_t MemVddioVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1111 1112 //FCLK Section 1113 1114 uint8_t FclkDpmUPstates[NUM_FCLK_DPM_LEVELS]; // U P-state ID associated with each FCLK DPM state. 1115 uint16_t FclkDpmVddU[NUM_FCLK_DPM_LEVELS]; // mV(Q2) Vset U voltage associated with each FCLK DPM state. 1116 uint16_t FclkDpmUSpeed[NUM_FCLK_DPM_LEVELS]; //U speed associated with each FCLK DPM state 1117 uint16_t FclkDpmDisallowPstateFreq; //Frequency which FW will target when indicated that display config cannot support P-state. Set to 0 use FW calculated value 1118 uint16_t PaddingFclk; 1119 1120 // Link DPM Settings 1121 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 1122 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 1123 uint16_t LclkFreq[NUM_LINK_LEVELS]; 1124 1125 // SECTION: Fan Control 1126 uint16_t FanStopTemp[TEMP_COUNT]; //Celsius 1127 uint16_t FanStartTemp[TEMP_COUNT]; //Celsius 1128 1129 uint16_t FanGain[TEMP_COUNT]; 1130 uint16_t FanGainPadding; 1131 1132 uint16_t FanPwmMin; 1133 uint16_t AcousticTargetRpmThreshold; 1134 uint16_t AcousticLimitRpmThreshold; 1135 uint16_t FanMaximumRpm; 1136 uint16_t MGpuAcousticLimitRpmThreshold; 1137 uint16_t FanTargetGfxclk; 1138 uint32_t TempInputSelectMask; 1139 uint8_t FanZeroRpmEnable; 1140 uint8_t FanTachEdgePerRev; 1141 uint16_t FanTargetTemperature[TEMP_COUNT]; 1142 1143 // The following are AFC override parameters. Leave at 0 to use FW defaults. 1144 int16_t FuzzyFan_ErrorSetDelta; 1145 int16_t FuzzyFan_ErrorRateSetDelta; 1146 int16_t FuzzyFan_PwmSetDelta; 1147 uint16_t FuzzyFan_Reserved; 1148 1149 uint16_t FwCtfLimit[TEMP_COUNT]; 1150 1151 uint16_t IntakeTempEnableRPM; 1152 int16_t IntakeTempOffsetTemp; 1153 uint16_t IntakeTempReleaseTemp; 1154 uint16_t IntakeTempHighIntakeAcousticLimit; 1155 uint16_t IntakeTempAcouticLimitReleaseRate; 1156 1157 int16_t FanAbnormalTempLimitOffset; 1158 uint16_t FanStalledTriggerRpm; 1159 uint16_t FanAbnormalTriggerRpmCoeff; 1160 uint16_t FanAbnormalDetectionEnable; 1161 1162 uint8_t FanIntakeSensorSupport; 1163 uint8_t FanIntakePadding[3]; 1164 uint32_t FanSpare[13]; 1165 1166 // SECTION: VDD_GFX AVFS 1167 1168 uint8_t OverrideGfxAvfsFuses; 1169 uint8_t GfxAvfsPadding[3]; 1170 1171 uint32_t L2HwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; //see fusedoc for encoding 1172 uint32_t SeHwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; 1173 1174 uint32_t CommonRtAvfs[PP_GRTAVFS_FW_COMMON_FUSE_COUNT]; 1175 1176 uint32_t L2FwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1177 uint32_t SeFwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1178 1179 uint32_t Droop_PWL_F[PP_NUM_RTAVFS_PWL_ZONES]; 1180 uint32_t Droop_PWL_a[PP_NUM_RTAVFS_PWL_ZONES]; 1181 uint32_t Droop_PWL_b[PP_NUM_RTAVFS_PWL_ZONES]; 1182 uint32_t Droop_PWL_c[PP_NUM_RTAVFS_PWL_ZONES]; 1183 1184 uint32_t Static_PWL_Offset[PP_NUM_RTAVFS_PWL_ZONES]; 1185 1186 uint32_t dGbV_dT_vmin; 1187 uint32_t dGbV_dT_vmax; 1188 1189 //Unused: PMFW-9370 1190 uint32_t V2F_vmin_range_low; 1191 uint32_t V2F_vmin_range_high; 1192 uint32_t V2F_vmax_range_low; 1193 uint32_t V2F_vmax_range_high; 1194 1195 AvfsDcBtcParams_t DcBtcGfxParams; 1196 1197 uint32_t GfxAvfsSpare[32]; 1198 1199 //SECTION: VDD_SOC AVFS 1200 1201 uint8_t OverrideSocAvfsFuses; 1202 uint8_t MinSocAvfsRevision; 1203 uint8_t SocAvfsPadding[2]; 1204 1205 AvfsFuseOverride_t SocAvfsFuseOverride[AVFS_D_COUNT]; 1206 1207 DroopInt_t dBtcGbSoc[AVFS_D_COUNT]; // GHz->V BtcGb 1208 1209 LinearInt_t qAgingGb[AVFS_D_COUNT]; // GHz->V 1210 1211 QuadraticInt_t qStaticVoltageOffset[AVFS_D_COUNT]; // GHz->V 1212 1213 AvfsDcBtcParams_t DcBtcSocParams[AVFS_D_COUNT]; 1214 1215 uint32_t SocAvfsSpare[32]; 1216 1217 //SECTION: Boot clock and voltage values 1218 BootValues_t BootValues; 1219 1220 //SECTION: Driver Reported Clocks 1221 DriverReportedClocks_t DriverReportedClocks; 1222 1223 //SECTION: Message Limits 1224 MsgLimits_t MsgLimits; 1225 1226 //SECTION: OverDrive Limits 1227 OverDriveLimits_t OverDriveLimitsMin; 1228 OverDriveLimits_t OverDriveLimitsBasicMax; 1229 uint32_t reserved[22]; 1230 1231 // SECTION: Advanced Options 1232 uint32_t DebugOverrides; 1233 1234 // Section: Total Board Power idle vs active coefficients 1235 uint8_t TotalBoardPowerSupport; 1236 uint8_t TotalBoardPowerPadding[3]; 1237 1238 int16_t TotalIdleBoardPowerM; 1239 int16_t TotalIdleBoardPowerB; 1240 int16_t TotalBoardPowerM; 1241 int16_t TotalBoardPowerB; 1242 1243 //PMFW-11158 1244 QuadraticInt_t qFeffCoeffGameClock[POWER_SOURCE_COUNT]; 1245 QuadraticInt_t qFeffCoeffBaseClock[POWER_SOURCE_COUNT]; 1246 QuadraticInt_t qFeffCoeffBoostClock[POWER_SOURCE_COUNT]; 1247 1248 // SECTION: Sku Reserved 1249 uint32_t Spare[43]; 1250 1251 // Padding for MMHUB - do not modify this 1252 uint32_t MmHubPadding[8]; 1253 1254 } SkuTable_t; 1255 1256 typedef struct { 1257 // SECTION: Version 1258 uint32_t Version; //should be unique to each board type 1259 1260 1261 // SECTION: I2C Control 1262 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 1263 1264 // SECTION: SVI2 Board Parameters 1265 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 1266 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 1267 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 1268 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 1269 1270 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1271 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1272 uint8_t VmempUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1273 uint8_t VddioUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1274 1275 //SECTION SVI3 Board Parameters 1276 uint8_t SlaveAddrMapping[SVI_PLANE_COUNT]; 1277 uint8_t VrPsiSupport[SVI_PLANE_COUNT]; 1278 1279 uint8_t PaddingPsi[SVI_PLANE_COUNT]; 1280 uint8_t EnablePsi6[SVI_PLANE_COUNT]; // only applicable in SVI3 1281 1282 // SECTION: Voltage Regulator Settings 1283 SviTelemetryScale_t SviTelemetryScale[SVI_PLANE_COUNT]; 1284 uint32_t VoltageTelemetryRatio[SVI_PLANE_COUNT]; // This is used for VDDIO Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 1285 1286 uint8_t DownSlewRateVr[SVI_PLANE_COUNT]; 1287 1288 // SECTION: GPIO Settings 1289 1290 uint8_t LedOffGpio; 1291 uint8_t FanOffGpio; 1292 uint8_t GfxVrPowerStageOffGpio; 1293 1294 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 1295 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 1296 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 1297 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 1298 1299 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 1300 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 1301 1302 // LED Display Settings 1303 uint8_t LedPin0; // GPIO number for LedPin[0] 1304 uint8_t LedPin1; // GPIO number for LedPin[1] 1305 uint8_t LedPin2; // GPIO number for LedPin[2] 1306 uint8_t LedEnableMask; 1307 1308 uint8_t LedPcie; // GPIO number for PCIE results 1309 uint8_t LedError; // GPIO number for Error Cases 1310 1311 // SECTION: Clock Spread Spectrum 1312 1313 // UCLK Spread Spectrum 1314 uint8_t UclkTrainingModeSpreadPercent; 1315 uint8_t UclkSpreadPadding; 1316 uint16_t UclkSpreadFreq; // kHz 1317 1318 // UCLK Spread Spectrum 1319 uint8_t UclkSpreadPercent[MEM_VENDOR_COUNT]; 1320 1321 // FCLK Spread Spectrum 1322 uint8_t FclkSpreadPadding; 1323 uint8_t FclkSpreadPercent; // Q4.4 1324 uint16_t FclkSpreadFreq; // kHz 1325 1326 // Section: Memory Config 1327 uint8_t DramWidth; // Width of interface to the channel for each DRAM module. See DRAM_BIT_WIDTH_TYPE_e 1328 uint8_t PaddingMem1[7]; 1329 1330 // SECTION: UMC feature flags 1331 uint8_t HsrEnabled; 1332 uint8_t VddqOffEnabled; 1333 uint8_t PaddingUmcFlags[2]; 1334 1335 uint32_t PostVoltageSetBacoDelay; // in microseconds. Amount of time FW will wait after power good is established or PSI0 command is issued 1336 uint32_t BacoEntryDelay; // in milliseconds. Amount of time FW will wait to trigger BACO entry after receiving entry notification from OS 1337 1338 uint8_t FuseWritePowerMuxPresent; 1339 uint8_t FuseWritePadding[3]; 1340 1341 // SECTION: Board Reserved 1342 uint32_t BoardSpare[63]; 1343 1344 // SECTION: Structure Padding 1345 1346 // Padding for MMHUB - do not modify this 1347 uint32_t MmHubPadding[8]; 1348 } BoardTable_t; 1349 1350 #pragma pack(push, 1) 1351 typedef struct { 1352 SkuTable_t SkuTable; 1353 BoardTable_t BoardTable; 1354 } PPTable_t; 1355 #pragma pack(pop) 1356 1357 typedef struct { 1358 // Time constant parameters for clock averages in ms 1359 uint16_t GfxclkAverageLpfTau; 1360 uint16_t FclkAverageLpfTau; 1361 uint16_t UclkAverageLpfTau; 1362 uint16_t GfxActivityLpfTau; 1363 uint16_t UclkActivityLpfTau; 1364 uint16_t SocketPowerLpfTau; 1365 uint16_t VcnClkAverageLpfTau; 1366 uint16_t VcnUsageAverageLpfTau; 1367 } DriverSmuConfig_t; 1368 1369 typedef struct { 1370 DriverSmuConfig_t DriverSmuConfig; 1371 1372 uint32_t Spare[8]; 1373 // Padding - ignore 1374 uint32_t MmHubPadding[8]; // SMU internal use 1375 } DriverSmuConfigExternal_t; 1376 1377 1378 typedef struct { 1379 1380 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1381 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1382 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1383 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1384 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1385 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1386 uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1387 uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1388 uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1389 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1390 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1391 1392 uint16_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1393 1394 uint16_t Padding; 1395 1396 uint32_t Spare[32]; 1397 1398 // Padding - ignore 1399 uint32_t MmHubPadding[8]; // SMU internal use 1400 1401 } DriverInfoTable_t; 1402 1403 typedef struct { 1404 uint32_t CurrClock[PPCLK_COUNT]; 1405 1406 uint16_t AverageGfxclkFrequencyTarget; 1407 uint16_t AverageGfxclkFrequencyPreDs; 1408 uint16_t AverageGfxclkFrequencyPostDs; 1409 uint16_t AverageFclkFrequencyPreDs; 1410 uint16_t AverageFclkFrequencyPostDs; 1411 uint16_t AverageMemclkFrequencyPreDs ; // this is scaled to actual memory clock 1412 uint16_t AverageMemclkFrequencyPostDs ; // this is scaled to actual memory clock 1413 uint16_t AverageVclk0Frequency ; 1414 uint16_t AverageDclk0Frequency ; 1415 uint16_t AverageVclk1Frequency ; 1416 uint16_t AverageDclk1Frequency ; 1417 uint16_t PCIeBusy; 1418 uint16_t dGPU_W_MAX; 1419 uint16_t padding; 1420 1421 uint32_t MetricsCounter; 1422 1423 uint16_t AvgVoltage[SVI_PLANE_COUNT]; 1424 uint16_t AvgCurrent[SVI_PLANE_COUNT]; 1425 1426 uint16_t AverageGfxActivity ; 1427 uint16_t AverageUclkActivity ; 1428 uint16_t Vcn0ActivityPercentage ; 1429 uint16_t Vcn1ActivityPercentage ; 1430 1431 uint32_t EnergyAccumulator; 1432 uint16_t AverageSocketPower; 1433 uint16_t AverageTotalBoardPower; 1434 1435 uint16_t AvgTemperature[TEMP_COUNT]; 1436 uint16_t AvgTemperatureFanIntake; 1437 1438 uint8_t PcieRate ; 1439 uint8_t PcieWidth ; 1440 1441 uint8_t AvgFanPwm; 1442 uint8_t Padding[1]; 1443 uint16_t AvgFanRpm; 1444 1445 1446 uint8_t ThrottlingPercentage[THROTTLER_COUNT]; 1447 1448 //metrics for D3hot entry/exit and driver ARM msgs 1449 uint32_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; 1450 uint32_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT]; 1451 uint32_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT]; 1452 1453 uint16_t ApuSTAPMSmartShiftLimit; 1454 uint16_t ApuSTAPMLimit; 1455 uint16_t AvgApuSocketPower; 1456 1457 uint16_t AverageUclkActivity_MAX; 1458 1459 uint32_t PublicSerialNumberLower; 1460 uint32_t PublicSerialNumberUpper; 1461 1462 } SmuMetrics_t; 1463 1464 typedef struct { 1465 SmuMetrics_t SmuMetrics; 1466 uint32_t Spare[30]; 1467 1468 // Padding - ignore 1469 uint32_t MmHubPadding[8]; // SMU internal use 1470 } SmuMetricsExternal_t; 1471 1472 typedef struct { 1473 uint8_t WmSetting; 1474 uint8_t Flags; 1475 uint8_t Padding[2]; 1476 1477 } WatermarkRowGeneric_t; 1478 1479 #define NUM_WM_RANGES 4 1480 1481 typedef enum { 1482 WATERMARKS_CLOCK_RANGE = 0, 1483 WATERMARKS_DUMMY_PSTATE, 1484 WATERMARKS_MALL, 1485 WATERMARKS_COUNT, 1486 } WATERMARKS_FLAGS_e; 1487 1488 typedef struct { 1489 // Watermarks 1490 WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES]; 1491 } Watermarks_t; 1492 1493 typedef struct { 1494 Watermarks_t Watermarks; 1495 uint32_t Spare[16]; 1496 1497 uint32_t MmHubPadding[8]; // SMU internal use 1498 } WatermarksExternal_t; 1499 1500 typedef struct { 1501 uint16_t avgPsmCount[214]; 1502 uint16_t minPsmCount[214]; 1503 float avgPsmVoltage[214]; 1504 float minPsmVoltage[214]; 1505 } AvfsDebugTable_t; 1506 1507 typedef struct { 1508 AvfsDebugTable_t AvfsDebugTable; 1509 1510 uint32_t MmHubPadding[8]; // SMU internal use 1511 } AvfsDebugTableExternal_t; 1512 1513 1514 typedef struct { 1515 uint8_t Gfx_ActiveHystLimit; 1516 uint8_t Gfx_IdleHystLimit; 1517 uint8_t Gfx_FPS; 1518 uint8_t Gfx_MinActiveFreqType; 1519 uint8_t Gfx_BoosterFreqType; 1520 uint8_t PaddingGfx; 1521 uint16_t Gfx_MinActiveFreq; // MHz 1522 uint16_t Gfx_BoosterFreq; // MHz 1523 uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms 1524 uint32_t Gfx_PD_Data_limit_a; // Q16 1525 uint32_t Gfx_PD_Data_limit_b; // Q16 1526 uint32_t Gfx_PD_Data_limit_c; // Q16 1527 uint32_t Gfx_PD_Data_error_coeff; // Q16 1528 uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 1529 1530 uint8_t Fclk_ActiveHystLimit; 1531 uint8_t Fclk_IdleHystLimit; 1532 uint8_t Fclk_FPS; 1533 uint8_t Fclk_MinActiveFreqType; 1534 uint8_t Fclk_BoosterFreqType; 1535 uint8_t PaddingFclk; 1536 uint16_t Fclk_MinActiveFreq; // MHz 1537 uint16_t Fclk_BoosterFreq; // MHz 1538 uint16_t Fclk_PD_Data_time_constant; // Time constant of PD controller in ms 1539 uint32_t Fclk_PD_Data_limit_a; // Q16 1540 uint32_t Fclk_PD_Data_limit_b; // Q16 1541 uint32_t Fclk_PD_Data_limit_c; // Q16 1542 uint32_t Fclk_PD_Data_error_coeff; // Q16 1543 uint32_t Fclk_PD_Data_error_rate_coeff; // Q16 1544 1545 uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16 1546 uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS]; 1547 uint8_t Mem_DownHystLimit[NUM_UCLK_DPM_LEVELS]; 1548 uint16_t Mem_Fps; 1549 uint8_t padding[2]; 1550 1551 } DpmActivityMonitorCoeffInt_t; 1552 1553 1554 typedef struct { 1555 DpmActivityMonitorCoeffInt_t DpmActivityMonitorCoeffInt; 1556 uint32_t MmHubPadding[8]; // SMU internal use 1557 } DpmActivityMonitorCoeffIntExternal_t; 1558 1559 1560 1561 // Workload bits 1562 #define WORKLOAD_PPLIB_DEFAULT_BIT 0 1563 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 1564 #define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 1565 #define WORKLOAD_PPLIB_VIDEO_BIT 3 1566 #define WORKLOAD_PPLIB_VR_BIT 4 1567 #define WORKLOAD_PPLIB_COMPUTE_BIT 5 1568 #define WORKLOAD_PPLIB_CUSTOM_BIT 6 1569 #define WORKLOAD_PPLIB_WINDOW_3D_BIT 7 1570 #define WORKLOAD_PPLIB_COUNT 8 1571 1572 1573 // These defines are used with the following messages: 1574 // SMC_MSG_TransferTableDram2Smu 1575 // SMC_MSG_TransferTableSmu2Dram 1576 1577 // Table transfer status 1578 #define TABLE_TRANSFER_OK 0x0 1579 #define TABLE_TRANSFER_FAILED 0xFF 1580 #define TABLE_TRANSFER_PENDING 0xAB 1581 1582 // Table types 1583 #define TABLE_PPTABLE 0 1584 #define TABLE_COMBO_PPTABLE 1 1585 #define TABLE_WATERMARKS 2 1586 #define TABLE_AVFS_PSM_DEBUG 3 1587 #define TABLE_PMSTATUSLOG 4 1588 #define TABLE_SMU_METRICS 5 1589 #define TABLE_DRIVER_SMU_CONFIG 6 1590 #define TABLE_ACTIVITY_MONITOR_COEFF 7 1591 #define TABLE_OVERDRIVE 8 1592 #define TABLE_I2C_COMMANDS 9 1593 #define TABLE_DRIVER_INFO 10 1594 #define TABLE_ECCINFO 11 1595 #define TABLE_COUNT 12 1596 1597 //IH Interupt ID 1598 #define IH_INTERRUPT_ID_TO_DRIVER 0xFE 1599 #define IH_INTERRUPT_CONTEXT_ID_BACO 0x2 1600 #define IH_INTERRUPT_CONTEXT_ID_AC 0x3 1601 #define IH_INTERRUPT_CONTEXT_ID_DC 0x4 1602 #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 0x5 1603 #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 0x6 1604 #define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING 0x7 1605 #define IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL 0x8 1606 #define IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY 0x9 1607 1608 #endif 1609