1ce81151cSLikun Gao /* 2ce81151cSLikun Gao * Copyright 2021 Advanced Micro Devices, Inc. 3ce81151cSLikun Gao * 4ce81151cSLikun Gao * Permission is hereby granted, free of charge, to any person obtaining a 5ce81151cSLikun Gao * copy of this software and associated documentation files (the "Software"), 6ce81151cSLikun Gao * to deal in the Software without restriction, including without limitation 7ce81151cSLikun Gao * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8ce81151cSLikun Gao * and/or sell copies of the Software, and to permit persons to whom the 9ce81151cSLikun Gao * Software is furnished to do so, subject to the following conditions: 10ce81151cSLikun Gao * 11ce81151cSLikun Gao * The above copyright notice and this permission notice shall be included in 12ce81151cSLikun Gao * all copies or substantial portions of the Software. 13ce81151cSLikun Gao * 14ce81151cSLikun Gao * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15ce81151cSLikun Gao * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16ce81151cSLikun Gao * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17ce81151cSLikun Gao * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18ce81151cSLikun Gao * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19ce81151cSLikun Gao * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20ce81151cSLikun Gao * OTHER DEALINGS IN THE SOFTWARE. 21ce81151cSLikun Gao * 22ce81151cSLikun Gao */ 23ce81151cSLikun Gao 24ce81151cSLikun Gao #ifndef SMU13_DRIVER_IF_V13_0_0_H 25ce81151cSLikun Gao #define SMU13_DRIVER_IF_V13_0_0_H 26ce81151cSLikun Gao 27ce81151cSLikun Gao //Increment this version if SkuTable_t or BoardTable_t change 28*da1acbb1SEvan Quan #define PPTABLE_VERSION 0x22 29ce81151cSLikun Gao 30ce81151cSLikun Gao #define NUM_GFXCLK_DPM_LEVELS 16 31ce81151cSLikun Gao #define NUM_SOCCLK_DPM_LEVELS 8 32ce81151cSLikun Gao #define NUM_MP0CLK_DPM_LEVELS 2 33ce81151cSLikun Gao #define NUM_DCLK_DPM_LEVELS 8 34ce81151cSLikun Gao #define NUM_VCLK_DPM_LEVELS 8 35ce81151cSLikun Gao #define NUM_DISPCLK_DPM_LEVELS 8 36ce81151cSLikun Gao #define NUM_DPPCLK_DPM_LEVELS 8 37ce81151cSLikun Gao #define NUM_DPREFCLK_DPM_LEVELS 8 38ce81151cSLikun Gao #define NUM_DCFCLK_DPM_LEVELS 8 39ce81151cSLikun Gao #define NUM_DTBCLK_DPM_LEVELS 8 40ce81151cSLikun Gao #define NUM_UCLK_DPM_LEVELS 4 41ce81151cSLikun Gao #define NUM_LINK_LEVELS 3 42ce81151cSLikun Gao #define NUM_FCLK_DPM_LEVELS 8 43ce81151cSLikun Gao #define NUM_OD_FAN_MAX_POINTS 6 44ce81151cSLikun Gao 45ce81151cSLikun Gao // Feature Control Defines 46ce81151cSLikun Gao #define FEATURE_FW_DATA_READ_BIT 0 47ce81151cSLikun Gao #define FEATURE_DPM_GFXCLK_BIT 1 48ce81151cSLikun Gao #define FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT 2 49ce81151cSLikun Gao #define FEATURE_DPM_UCLK_BIT 3 50ce81151cSLikun Gao #define FEATURE_DPM_FCLK_BIT 4 51ce81151cSLikun Gao #define FEATURE_DPM_SOCCLK_BIT 5 52ce81151cSLikun Gao #define FEATURE_DPM_MP0CLK_BIT 6 53ce81151cSLikun Gao #define FEATURE_DPM_LINK_BIT 7 54ce81151cSLikun Gao #define FEATURE_DPM_DCN_BIT 8 55ce81151cSLikun Gao #define FEATURE_VMEMP_SCALING_BIT 9 56ce81151cSLikun Gao #define FEATURE_VDDIO_MEM_SCALING_BIT 10 57ce81151cSLikun Gao #define FEATURE_DS_GFXCLK_BIT 11 58ce81151cSLikun Gao #define FEATURE_DS_SOCCLK_BIT 12 59ce81151cSLikun Gao #define FEATURE_DS_FCLK_BIT 13 60ce81151cSLikun Gao #define FEATURE_DS_LCLK_BIT 14 61ce81151cSLikun Gao #define FEATURE_DS_DCFCLK_BIT 15 62ce81151cSLikun Gao #define FEATURE_DS_UCLK_BIT 16 63ce81151cSLikun Gao #define FEATURE_GFX_ULV_BIT 17 64ce81151cSLikun Gao #define FEATURE_FW_DSTATE_BIT 18 65ce81151cSLikun Gao #define FEATURE_GFXOFF_BIT 19 66ce81151cSLikun Gao #define FEATURE_BACO_BIT 20 67ce81151cSLikun Gao #define FEATURE_MM_DPM_BIT 21 68ce81151cSLikun Gao #define FEATURE_SOC_MPCLK_DS_BIT 22 69ce81151cSLikun Gao #define FEATURE_BACO_MPCLK_DS_BIT 23 70ce81151cSLikun Gao #define FEATURE_THROTTLERS_BIT 24 71ce81151cSLikun Gao #define FEATURE_SMARTSHIFT_BIT 25 72ce81151cSLikun Gao #define FEATURE_GTHR_BIT 26 73ce81151cSLikun Gao #define FEATURE_ACDC_BIT 27 74ce81151cSLikun Gao #define FEATURE_VR0HOT_BIT 28 75ce81151cSLikun Gao #define FEATURE_FW_CTF_BIT 29 76ce81151cSLikun Gao #define FEATURE_FAN_CONTROL_BIT 30 77ce81151cSLikun Gao #define FEATURE_GFX_DCS_BIT 31 78ce81151cSLikun Gao #define FEATURE_GFX_READ_MARGIN_BIT 32 79ce81151cSLikun Gao #define FEATURE_LED_DISPLAY_BIT 33 80ce81151cSLikun Gao #define FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT 34 81ce81151cSLikun Gao #define FEATURE_OUT_OF_BAND_MONITOR_BIT 35 82ce81151cSLikun Gao #define FEATURE_OPTIMIZED_VMIN_BIT 36 83ce81151cSLikun Gao #define FEATURE_GFX_IMU_BIT 37 84ce81151cSLikun Gao #define FEATURE_BOOT_TIME_CAL_BIT 38 85ce81151cSLikun Gao #define FEATURE_GFX_PCC_DFLL_BIT 39 86ce81151cSLikun Gao #define FEATURE_SOC_CG_BIT 40 87ce81151cSLikun Gao #define FEATURE_DF_CSTATE_BIT 41 88ce81151cSLikun Gao #define FEATURE_GFX_EDC_BIT 42 89ce81151cSLikun Gao #define FEATURE_BOOT_POWER_OPT_BIT 43 90ce81151cSLikun Gao #define FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT 44 91ce81151cSLikun Gao #define FEATURE_DS_VCN_BIT 45 92ce81151cSLikun Gao #define FEATURE_BACO_CG_BIT 46 93ce81151cSLikun Gao #define FEATURE_MEM_TEMP_READ_BIT 47 94ce81151cSLikun Gao #define FEATURE_ATHUB_MMHUB_PG_BIT 48 95ce81151cSLikun Gao #define FEATURE_SOC_PCC_BIT 49 961f3dfde4SEvan Quan #define FEATURE_EDC_PWRBRK_BIT 50 97ce81151cSLikun Gao #define FEATURE_SPARE_51_BIT 51 98ce81151cSLikun Gao #define FEATURE_SPARE_52_BIT 52 99ce81151cSLikun Gao #define FEATURE_SPARE_53_BIT 53 100ce81151cSLikun Gao #define FEATURE_SPARE_54_BIT 54 101ce81151cSLikun Gao #define FEATURE_SPARE_55_BIT 55 102ce81151cSLikun Gao #define FEATURE_SPARE_56_BIT 56 103ce81151cSLikun Gao #define FEATURE_SPARE_57_BIT 57 104ce81151cSLikun Gao #define FEATURE_SPARE_58_BIT 58 105ce81151cSLikun Gao #define FEATURE_SPARE_59_BIT 59 106ce81151cSLikun Gao #define FEATURE_SPARE_60_BIT 60 107ce81151cSLikun Gao #define FEATURE_SPARE_61_BIT 61 108ce81151cSLikun Gao #define FEATURE_SPARE_62_BIT 62 109ce81151cSLikun Gao #define FEATURE_SPARE_63_BIT 63 110ce81151cSLikun Gao #define NUM_FEATURES 64 111ce81151cSLikun Gao 112ce81151cSLikun Gao //For use with feature control messages 113ce81151cSLikun Gao typedef enum { 114ce81151cSLikun Gao FEATURE_PWR_ALL, 115ce81151cSLikun Gao FEATURE_PWR_S5, 116ce81151cSLikun Gao FEATURE_PWR_BACO, 117ce81151cSLikun Gao FEATURE_PWR_SOC, 118ce81151cSLikun Gao FEATURE_PWR_GFX, 119ce81151cSLikun Gao FEATURE_PWR_DOMAIN_COUNT, 120ce81151cSLikun Gao } FEATURE_PWR_DOMAIN_e; 121ce81151cSLikun Gao 122ce81151cSLikun Gao 123ce81151cSLikun Gao // Debug Overrides Bitmask 124ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000001 125ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK 0x00000002 126ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK 0x00000004 127ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK 0x00000008 128ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x00000010 129ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_VCN_PG 0x00000020 130ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_FMAX_VMAX 0x00000040 131ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS 0x00000080 132ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK 0x00000100 133ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_DFLL 0x00000200 134ce81151cSLikun Gao #define DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE 0x00000400 135ce81151cSLikun Gao #define DEBUG_OVERRIDE_DFLL_MASTER_MODE 0x00000800 136ce81151cSLikun Gao 137ce81151cSLikun Gao // VR Mapping Bit Defines 138ce81151cSLikun Gao #define VR_MAPPING_VR_SELECT_MASK 0x01 139ce81151cSLikun Gao #define VR_MAPPING_VR_SELECT_SHIFT 0x00 140ce81151cSLikun Gao 141ce81151cSLikun Gao #define VR_MAPPING_PLANE_SELECT_MASK 0x02 142ce81151cSLikun Gao #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 143ce81151cSLikun Gao 144ce81151cSLikun Gao // PSI Bit Defines 145ce81151cSLikun Gao #define PSI_SEL_VR0_PLANE0_PSI0 0x01 146ce81151cSLikun Gao #define PSI_SEL_VR0_PLANE0_PSI1 0x02 147ce81151cSLikun Gao #define PSI_SEL_VR0_PLANE1_PSI0 0x04 148ce81151cSLikun Gao #define PSI_SEL_VR0_PLANE1_PSI1 0x08 149ce81151cSLikun Gao #define PSI_SEL_VR1_PLANE0_PSI0 0x10 150ce81151cSLikun Gao #define PSI_SEL_VR1_PLANE0_PSI1 0x20 151ce81151cSLikun Gao #define PSI_SEL_VR1_PLANE1_PSI0 0x40 152ce81151cSLikun Gao #define PSI_SEL_VR1_PLANE1_PSI1 0x80 153ce81151cSLikun Gao 154ce81151cSLikun Gao typedef enum { 155ce81151cSLikun Gao SVI_PSI_0, // Full phase count (default) 156ce81151cSLikun Gao SVI_PSI_1, // Phase count 1st level 157ce81151cSLikun Gao SVI_PSI_2, // Phase count 2nd level 158ce81151cSLikun Gao SVI_PSI_3, // Single phase operation + active diode emulation 159ce81151cSLikun Gao SVI_PSI_4, // Single phase operation + passive diode emulation *optional* 160ce81151cSLikun Gao SVI_PSI_5, // Reserved 161ce81151cSLikun Gao SVI_PSI_6, // Power down to 0V (voltage regulation disabled) 162ce81151cSLikun Gao SVI_PSI_7, // Automated phase shedding and diode emulation 163ce81151cSLikun Gao } SVI_PSI_e; 164ce81151cSLikun Gao 165ce81151cSLikun Gao // Throttler Control/Status Bits 166ce81151cSLikun Gao #define THROTTLER_TEMP_EDGE_BIT 0 167ce81151cSLikun Gao #define THROTTLER_TEMP_HOTSPOT_BIT 1 168ce81151cSLikun Gao #define THROTTLER_TEMP_HOTSPOT_G_BIT 2 169ce81151cSLikun Gao #define THROTTLER_TEMP_HOTSPOT_M_BIT 3 170ce81151cSLikun Gao #define THROTTLER_TEMP_MEM_BIT 4 171ce81151cSLikun Gao #define THROTTLER_TEMP_VR_GFX_BIT 5 172ce81151cSLikun Gao #define THROTTLER_TEMP_VR_MEM0_BIT 6 173ce81151cSLikun Gao #define THROTTLER_TEMP_VR_MEM1_BIT 7 174ce81151cSLikun Gao #define THROTTLER_TEMP_VR_SOC_BIT 8 175ce81151cSLikun Gao #define THROTTLER_TEMP_VR_U_BIT 9 176ce81151cSLikun Gao #define THROTTLER_TEMP_LIQUID0_BIT 10 177ce81151cSLikun Gao #define THROTTLER_TEMP_LIQUID1_BIT 11 178ce81151cSLikun Gao #define THROTTLER_TEMP_PLX_BIT 12 179ce81151cSLikun Gao #define THROTTLER_TDC_GFX_BIT 13 180ce81151cSLikun Gao #define THROTTLER_TDC_SOC_BIT 14 181ce81151cSLikun Gao #define THROTTLER_TDC_U_BIT 15 182ce81151cSLikun Gao #define THROTTLER_PPT0_BIT 16 183ce81151cSLikun Gao #define THROTTLER_PPT1_BIT 17 184ce81151cSLikun Gao #define THROTTLER_PPT2_BIT 18 185ce81151cSLikun Gao #define THROTTLER_PPT3_BIT 19 186ce81151cSLikun Gao #define THROTTLER_FIT_BIT 20 187ce81151cSLikun Gao #define THROTTLER_GFX_APCC_PLUS_BIT 21 188ce81151cSLikun Gao #define THROTTLER_COUNT 22 189ce81151cSLikun Gao 190ce81151cSLikun Gao // FW DState Features Control Bits 191ce81151cSLikun Gao #define FW_DSTATE_SOC_ULV_BIT 0 192ce81151cSLikun Gao #define FW_DSTATE_G6_HSR_BIT 1 193ce81151cSLikun Gao #define FW_DSTATE_G6_PHY_VMEMP_OFF_BIT 2 194ce81151cSLikun Gao #define FW_DSTATE_SMN_DS_BIT 3 195ce81151cSLikun Gao #define FW_DSTATE_MP1_WHISPER_MODE_BIT 4 196ce81151cSLikun Gao #define FW_DSTATE_SOC_LIV_MIN_BIT 5 197ce81151cSLikun Gao #define FW_DSTATE_SOC_PLL_PWRDN_BIT 6 198ce81151cSLikun Gao #define FW_DSTATE_MEM_PLL_PWRDN_BIT 7 199ce81151cSLikun Gao #define FW_DSTATE_MALL_ALLOC_BIT 8 200ce81151cSLikun Gao #define FW_DSTATE_MEM_PSI_BIT 9 201ce81151cSLikun Gao #define FW_DSTATE_HSR_NON_STROBE_BIT 10 202ce81151cSLikun Gao #define FW_DSTATE_MP0_ENTER_WFI_BIT 11 203ce81151cSLikun Gao #define FW_DSTATE_U_ULV_BIT 12 204ce81151cSLikun Gao #define FW_DSTATE_MALL_FLUSH_BIT 13 205ce81151cSLikun Gao #define FW_DSTATE_SOC_PSI_BIT 14 206ce81151cSLikun Gao #define FW_DSTATE_U_PSI_BIT 15 207ce81151cSLikun Gao #define FW_DSTATE_UCP_DS_BIT 16 208ce81151cSLikun Gao #define FW_DSTATE_CSRCLK_DS_BIT 17 209ce81151cSLikun Gao #define FW_DSTATE_MMHUB_INTERLOCK_BIT 18 210ce81151cSLikun Gao #define FW_DSTATE_D0i3_2_QUIET_FW_BIT 19 211ce81151cSLikun Gao #define FW_DSTATE_CLDO_PRG_BIT 20 212ce81151cSLikun Gao #define FW_DSTATE_DF_PLL_PWRDN_BIT 21 213ce81151cSLikun Gao #define FW_DSTATE_U_LOW_PWR_MODE_EN_BIT 22 214ce81151cSLikun Gao #define FW_DSTATE_GFX_PSI6_BIT 23 215ce81151cSLikun Gao #define FW_DSTATE_GFX_VR_PWR_STAGE_BIT 24 216ce81151cSLikun Gao 217ce81151cSLikun Gao //LED Display Mask & Control Bits 218ce81151cSLikun Gao #define LED_DISPLAY_GFX_DPM_BIT 0 219ce81151cSLikun Gao #define LED_DISPLAY_PCIE_BIT 1 220ce81151cSLikun Gao #define LED_DISPLAY_ERROR_BIT 2 221ce81151cSLikun Gao 222ce81151cSLikun Gao 223ce81151cSLikun Gao #define MEM_TEMP_READ_OUT_OF_BAND_BIT 0 224ce81151cSLikun Gao #define MEM_TEMP_READ_IN_BAND_REFRESH_BIT 1 225ce81151cSLikun Gao #define MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT 2 226ce81151cSLikun Gao 227ce81151cSLikun Gao typedef enum { 228ce81151cSLikun Gao SMARTSHIFT_VERSION_1, 229ce81151cSLikun Gao SMARTSHIFT_VERSION_2, 230ce81151cSLikun Gao SMARTSHIFT_VERSION_3, 231ce81151cSLikun Gao } SMARTSHIFT_VERSION_e; 232ce81151cSLikun Gao 233ce81151cSLikun Gao typedef enum { 234ce81151cSLikun Gao FOPT_CALC_AC_CALC_DC, 235ce81151cSLikun Gao FOPT_PPTABLE_AC_CALC_DC, 236ce81151cSLikun Gao FOPT_CALC_AC_PPTABLE_DC, 237ce81151cSLikun Gao FOPT_PPTABLE_AC_PPTABLE_DC, 238ce81151cSLikun Gao } FOPT_CALC_e; 239ce81151cSLikun Gao 240ce81151cSLikun Gao typedef enum { 241ce81151cSLikun Gao DRAM_BIT_WIDTH_DISABLED = 0, 242ce81151cSLikun Gao DRAM_BIT_WIDTH_X_8 = 8, 243ce81151cSLikun Gao DRAM_BIT_WIDTH_X_16 = 16, 244ce81151cSLikun Gao DRAM_BIT_WIDTH_X_32 = 32, 245ce81151cSLikun Gao DRAM_BIT_WIDTH_X_64 = 64, 246ce81151cSLikun Gao DRAM_BIT_WIDTH_X_128 = 128, 247ce81151cSLikun Gao DRAM_BIT_WIDTH_COUNT, 248ce81151cSLikun Gao } DRAM_BIT_WIDTH_TYPE_e; 249ce81151cSLikun Gao 250ce81151cSLikun Gao //I2C Interface 251ce81151cSLikun Gao #define NUM_I2C_CONTROLLERS 8 252ce81151cSLikun Gao 253ce81151cSLikun Gao #define I2C_CONTROLLER_ENABLED 1 254ce81151cSLikun Gao #define I2C_CONTROLLER_DISABLED 0 255ce81151cSLikun Gao 256ce81151cSLikun Gao #define MAX_SW_I2C_COMMANDS 24 257ce81151cSLikun Gao 258ce81151cSLikun Gao typedef enum { 259ce81151cSLikun Gao I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0 260ce81151cSLikun Gao I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1 261ce81151cSLikun Gao I2C_CONTROLLER_PORT_COUNT, 262ce81151cSLikun Gao } I2cControllerPort_e; 263ce81151cSLikun Gao 264ce81151cSLikun Gao typedef enum { 265ce81151cSLikun Gao I2C_CONTROLLER_NAME_VR_GFX = 0, 266ce81151cSLikun Gao I2C_CONTROLLER_NAME_VR_SOC, 267ce81151cSLikun Gao I2C_CONTROLLER_NAME_VR_VMEMP, 268ce81151cSLikun Gao I2C_CONTROLLER_NAME_VR_VDDIO, 269ce81151cSLikun Gao I2C_CONTROLLER_NAME_LIQUID0, 270ce81151cSLikun Gao I2C_CONTROLLER_NAME_LIQUID1, 271ce81151cSLikun Gao I2C_CONTROLLER_NAME_PLX, 272ce81151cSLikun Gao I2C_CONTROLLER_NAME_OTHER, 273ce81151cSLikun Gao I2C_CONTROLLER_NAME_COUNT, 274ce81151cSLikun Gao } I2cControllerName_e; 275ce81151cSLikun Gao 276ce81151cSLikun Gao typedef enum { 277ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 278ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_VR_GFX, 279ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_VR_SOC, 280ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_VR_VMEMP, 281ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_VR_VDDIO, 282ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_LIQUID0, 283ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_LIQUID1, 284ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_PLX, 285ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_INA3221, 286ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_COUNT, 287ce81151cSLikun Gao } I2cControllerThrottler_e; 288ce81151cSLikun Gao 289ce81151cSLikun Gao typedef enum { 290ce81151cSLikun Gao I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5, 291ce81151cSLikun Gao I2C_CONTROLLER_PROTOCOL_VR_IR35217, 292ce81151cSLikun Gao I2C_CONTROLLER_PROTOCOL_TMP_TMP102A, 293ce81151cSLikun Gao I2C_CONTROLLER_PROTOCOL_INA3221, 294ce81151cSLikun Gao I2C_CONTROLLER_PROTOCOL_COUNT, 295ce81151cSLikun Gao } I2cControllerProtocol_e; 296ce81151cSLikun Gao 297ce81151cSLikun Gao typedef struct { 298ce81151cSLikun Gao uint8_t Enabled; 299ce81151cSLikun Gao uint8_t Speed; 300ce81151cSLikun Gao uint8_t SlaveAddress; 301ce81151cSLikun Gao uint8_t ControllerPort; 302ce81151cSLikun Gao uint8_t ControllerName; 303ce81151cSLikun Gao uint8_t ThermalThrotter; 304ce81151cSLikun Gao uint8_t I2cProtocol; 305ce81151cSLikun Gao uint8_t PaddingConfig; 306ce81151cSLikun Gao } I2cControllerConfig_t; 307ce81151cSLikun Gao 308ce81151cSLikun Gao typedef enum { 309ce81151cSLikun Gao I2C_PORT_SVD_SCL = 0, 310ce81151cSLikun Gao I2C_PORT_GPIO, 311ce81151cSLikun Gao } I2cPort_e; 312ce81151cSLikun Gao 313ce81151cSLikun Gao typedef enum { 314ce81151cSLikun Gao I2C_SPEED_FAST_50K = 0, //50 Kbits/s 315ce81151cSLikun Gao I2C_SPEED_FAST_100K, //100 Kbits/s 316ce81151cSLikun Gao I2C_SPEED_FAST_400K, //400 Kbits/s 317ce81151cSLikun Gao I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 318ce81151cSLikun Gao I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 319ce81151cSLikun Gao I2C_SPEED_HIGH_2M, //2.3 Mbits/s 320ce81151cSLikun Gao I2C_SPEED_COUNT, 321ce81151cSLikun Gao } I2cSpeed_e; 322ce81151cSLikun Gao 323ce81151cSLikun Gao typedef enum { 324ce81151cSLikun Gao I2C_CMD_READ = 0, 325ce81151cSLikun Gao I2C_CMD_WRITE, 326ce81151cSLikun Gao I2C_CMD_COUNT, 327ce81151cSLikun Gao } I2cCmdType_e; 328ce81151cSLikun Gao 329ce81151cSLikun Gao #define CMDCONFIG_STOP_BIT 0 330ce81151cSLikun Gao #define CMDCONFIG_RESTART_BIT 1 331ce81151cSLikun Gao #define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write 332ce81151cSLikun Gao 333ce81151cSLikun Gao #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 334ce81151cSLikun Gao #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 335ce81151cSLikun Gao #define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT) 336ce81151cSLikun Gao 337ce81151cSLikun Gao typedef struct { 338ce81151cSLikun Gao uint8_t ReadWriteData; //Return data for read. Data to send for write 339ce81151cSLikun Gao uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write 340ce81151cSLikun Gao } SwI2cCmd_t; //SW I2C Command Table 341ce81151cSLikun Gao 342ce81151cSLikun Gao typedef struct { 343ce81151cSLikun Gao uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 344ce81151cSLikun Gao uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select 345ce81151cSLikun Gao uint8_t SlaveAddress; //Slave address of device 346ce81151cSLikun Gao uint8_t NumCmds; //Number of commands 347ce81151cSLikun Gao 348ce81151cSLikun Gao SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 349ce81151cSLikun Gao } SwI2cRequest_t; // SW I2C Request Table 350ce81151cSLikun Gao 351ce81151cSLikun Gao typedef struct { 352ce81151cSLikun Gao SwI2cRequest_t SwI2cRequest; 353ce81151cSLikun Gao 354ce81151cSLikun Gao uint32_t Spare[8]; 355ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 356ce81151cSLikun Gao } SwI2cRequestExternal_t; 357ce81151cSLikun Gao 358ce81151cSLikun Gao typedef struct { 359ce81151cSLikun Gao uint64_t mca_umc_status; 360ce81151cSLikun Gao uint64_t mca_umc_addr; 361ce81151cSLikun Gao 362ce81151cSLikun Gao uint16_t ce_count_lo_chip; 363ce81151cSLikun Gao uint16_t ce_count_hi_chip; 364ce81151cSLikun Gao 365ce81151cSLikun Gao uint32_t eccPadding; 366ce81151cSLikun Gao } EccInfo_t; 367ce81151cSLikun Gao 368ce81151cSLikun Gao typedef struct { 369ce81151cSLikun Gao EccInfo_t EccInfo[24]; 370ce81151cSLikun Gao } EccInfoTable_t; 371ce81151cSLikun Gao 372ce81151cSLikun Gao //D3HOT sequences 373ce81151cSLikun Gao typedef enum { 374ce81151cSLikun Gao BACO_SEQUENCE, 375ce81151cSLikun Gao MSR_SEQUENCE, 376ce81151cSLikun Gao BAMACO_SEQUENCE, 377ce81151cSLikun Gao ULPS_SEQUENCE, 378ce81151cSLikun Gao D3HOT_SEQUENCE_COUNT, 379ce81151cSLikun Gao } D3HOTSequence_e; 380ce81151cSLikun Gao 381ce81151cSLikun Gao //This is aligned with RSMU PGFSM Register Mapping 382ce81151cSLikun Gao typedef enum { 383ce81151cSLikun Gao PG_DYNAMIC_MODE = 0, 384ce81151cSLikun Gao PG_STATIC_MODE, 385ce81151cSLikun Gao } PowerGatingMode_e; 386ce81151cSLikun Gao 387ce81151cSLikun Gao //This is aligned with RSMU PGFSM Register Mapping 388ce81151cSLikun Gao typedef enum { 389ce81151cSLikun Gao PG_POWER_DOWN = 0, 390ce81151cSLikun Gao PG_POWER_UP, 391ce81151cSLikun Gao } PowerGatingSettings_e; 392ce81151cSLikun Gao 393ce81151cSLikun Gao typedef struct { 394ce81151cSLikun Gao uint32_t a; // store in IEEE float format in this variable 395ce81151cSLikun Gao uint32_t b; // store in IEEE float format in this variable 396ce81151cSLikun Gao uint32_t c; // store in IEEE float format in this variable 397ce81151cSLikun Gao } QuadraticInt_t; 398ce81151cSLikun Gao 399ce81151cSLikun Gao typedef struct { 400ce81151cSLikun Gao uint32_t m; // store in IEEE float format in this variable 401ce81151cSLikun Gao uint32_t b; // store in IEEE float format in this variable 402ce81151cSLikun Gao } LinearInt_t; 403ce81151cSLikun Gao 404ce81151cSLikun Gao typedef struct { 405ce81151cSLikun Gao uint32_t a; // store in IEEE float format in this variable 406ce81151cSLikun Gao uint32_t b; // store in IEEE float format in this variable 407ce81151cSLikun Gao uint32_t c; // store in IEEE float format in this variable 408ce81151cSLikun Gao } DroopInt_t; 409ce81151cSLikun Gao 410ce81151cSLikun Gao typedef enum { 411ce81151cSLikun Gao DCS_ARCH_DISABLED, 412ce81151cSLikun Gao DCS_ARCH_FADCS, 413ce81151cSLikun Gao DCS_ARCH_ASYNC, 414ce81151cSLikun Gao } DCS_ARCH_e; 415ce81151cSLikun Gao 416ce81151cSLikun Gao //Only Clks that have DPM descriptors are listed here 417ce81151cSLikun Gao typedef enum { 418ce81151cSLikun Gao PPCLK_GFXCLK = 0, 419ce81151cSLikun Gao PPCLK_SOCCLK, 420ce81151cSLikun Gao PPCLK_UCLK, 421ce81151cSLikun Gao PPCLK_FCLK, 422ce81151cSLikun Gao PPCLK_DCLK_0, 423ce81151cSLikun Gao PPCLK_VCLK_0, 424ce81151cSLikun Gao PPCLK_DCLK_1, 425ce81151cSLikun Gao PPCLK_VCLK_1, 426ce81151cSLikun Gao PPCLK_DISPCLK, 427ce81151cSLikun Gao PPCLK_DPPCLK, 428ce81151cSLikun Gao PPCLK_DPREFCLK, 429ce81151cSLikun Gao PPCLK_DCFCLK, 430ce81151cSLikun Gao PPCLK_DTBCLK, 431ce81151cSLikun Gao PPCLK_COUNT, 432ce81151cSLikun Gao } PPCLK_e; 433ce81151cSLikun Gao 434ce81151cSLikun Gao typedef enum { 435ce81151cSLikun Gao VOLTAGE_MODE_PPTABLE = 0, 436ce81151cSLikun Gao VOLTAGE_MODE_FUSES, 437ce81151cSLikun Gao VOLTAGE_MODE_COUNT, 438ce81151cSLikun Gao } VOLTAGE_MODE_e; 439ce81151cSLikun Gao 440ce81151cSLikun Gao 441ce81151cSLikun Gao typedef enum { 442ce81151cSLikun Gao AVFS_VOLTAGE_GFX = 0, 443ce81151cSLikun Gao AVFS_VOLTAGE_SOC, 444ce81151cSLikun Gao AVFS_VOLTAGE_COUNT, 445ce81151cSLikun Gao } AVFS_VOLTAGE_TYPE_e; 446ce81151cSLikun Gao 447ce81151cSLikun Gao typedef enum { 448ce81151cSLikun Gao AVFS_TEMP_COLD = 0, 449ce81151cSLikun Gao AVFS_TEMP_HOT, 450ce81151cSLikun Gao AVFS_TEMP_COUNT, 451ce81151cSLikun Gao } AVFS_TEMP_e; 452ce81151cSLikun Gao 453ce81151cSLikun Gao typedef enum { 454ce81151cSLikun Gao AVFS_D_G, 455ce81151cSLikun Gao AVFS_D_M_B, 456ce81151cSLikun Gao AVFS_D_M_S, 457ce81151cSLikun Gao AVFS_D_COUNT, 458ce81151cSLikun Gao } AVFS_D_e; 459ce81151cSLikun Gao 460ce81151cSLikun Gao typedef enum { 461ce81151cSLikun Gao UCLK_DIV_BY_1 = 0, 462ce81151cSLikun Gao UCLK_DIV_BY_2, 463ce81151cSLikun Gao UCLK_DIV_BY_4, 464ce81151cSLikun Gao UCLK_DIV_BY_8, 465ce81151cSLikun Gao } UCLK_DIV_e; 466ce81151cSLikun Gao 467ce81151cSLikun Gao typedef enum { 468ce81151cSLikun Gao GPIO_INT_POLARITY_ACTIVE_LOW = 0, 469ce81151cSLikun Gao GPIO_INT_POLARITY_ACTIVE_HIGH, 470ce81151cSLikun Gao } GpioIntPolarity_e; 471ce81151cSLikun Gao 472ce81151cSLikun Gao typedef enum { 473ce81151cSLikun Gao PWR_CONFIG_TDP = 0, 474ce81151cSLikun Gao PWR_CONFIG_TGP, 475ce81151cSLikun Gao PWR_CONFIG_TCP_ESTIMATED, 476ce81151cSLikun Gao PWR_CONFIG_TCP_MEASURED, 477ce81151cSLikun Gao } PwrConfig_e; 478ce81151cSLikun Gao 479ce81151cSLikun Gao typedef struct { 480ce81151cSLikun Gao uint8_t Padding; 481ce81151cSLikun Gao uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 482ce81151cSLikun Gao uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 483ce81151cSLikun Gao uint8_t CalculateFopt; // Indication whether FW should calculate Fopt or use values below. Reference FOPT_CALC_e 484ce81151cSLikun Gao LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 485ce81151cSLikun Gao uint32_t Padding3[3]; 486ce81151cSLikun Gao uint16_t Padding4; 487ce81151cSLikun Gao uint16_t FoptimalDc; //Foptimal frequency in DC power mode. 488ce81151cSLikun Gao uint16_t FoptimalAc; //Foptimal frequency in AC power mode. 489ce81151cSLikun Gao uint16_t Padding2; 490ce81151cSLikun Gao } DpmDescriptor_t; 491ce81151cSLikun Gao 492ce81151cSLikun Gao typedef enum { 493ce81151cSLikun Gao PPT_THROTTLER_PPT0, 494ce81151cSLikun Gao PPT_THROTTLER_PPT1, 495ce81151cSLikun Gao PPT_THROTTLER_PPT2, 496ce81151cSLikun Gao PPT_THROTTLER_PPT3, 497ce81151cSLikun Gao PPT_THROTTLER_COUNT 498ce81151cSLikun Gao } PPT_THROTTLER_e; 499ce81151cSLikun Gao 500ce81151cSLikun Gao typedef enum { 501ce81151cSLikun Gao TEMP_EDGE, 502ce81151cSLikun Gao TEMP_HOTSPOT, 503ce81151cSLikun Gao TEMP_HOTSPOT_G, 504ce81151cSLikun Gao TEMP_HOTSPOT_M, 505ce81151cSLikun Gao TEMP_MEM, 506ce81151cSLikun Gao TEMP_VR_GFX, 507ce81151cSLikun Gao TEMP_VR_MEM0, 508ce81151cSLikun Gao TEMP_VR_MEM1, 509ce81151cSLikun Gao TEMP_VR_SOC, 510ce81151cSLikun Gao TEMP_VR_U, 511ce81151cSLikun Gao TEMP_LIQUID0, 512ce81151cSLikun Gao TEMP_LIQUID1, 513ce81151cSLikun Gao TEMP_PLX, 514ce81151cSLikun Gao TEMP_COUNT, 515ce81151cSLikun Gao } TEMP_e; 516ce81151cSLikun Gao 517ce81151cSLikun Gao typedef enum { 518ce81151cSLikun Gao TDC_THROTTLER_GFX, 519ce81151cSLikun Gao TDC_THROTTLER_SOC, 520ce81151cSLikun Gao TDC_THROTTLER_U, 521ce81151cSLikun Gao TDC_THROTTLER_COUNT 522ce81151cSLikun Gao } TDC_THROTTLER_e; 523ce81151cSLikun Gao 524ce81151cSLikun Gao typedef enum { 525ce81151cSLikun Gao SVI_PLANE_GFX, 526ce81151cSLikun Gao SVI_PLANE_SOC, 527ce81151cSLikun Gao SVI_PLANE_VMEMP, 528ce81151cSLikun Gao SVI_PLANE_VDDIO_MEM, 529ce81151cSLikun Gao SVI_PLANE_U, 530ce81151cSLikun Gao SVI_PLANE_COUNT, 531ce81151cSLikun Gao } SVI_PLANE_e; 532ce81151cSLikun Gao 533ce81151cSLikun Gao typedef enum { 534ce81151cSLikun Gao PMFW_VOLT_PLANE_GFX, 535ce81151cSLikun Gao PMFW_VOLT_PLANE_SOC, 536ce81151cSLikun Gao PMFW_VOLT_PLANE_COUNT 537ce81151cSLikun Gao } PMFW_VOLT_PLANE_e; 538ce81151cSLikun Gao 539ce81151cSLikun Gao typedef enum { 540ce81151cSLikun Gao CUSTOMER_VARIANT_ROW, 541ce81151cSLikun Gao CUSTOMER_VARIANT_FALCON, 542ce81151cSLikun Gao CUSTOMER_VARIANT_COUNT, 543ce81151cSLikun Gao } CUSTOMER_VARIANT_e; 544ce81151cSLikun Gao 545ce81151cSLikun Gao typedef enum { 546ce81151cSLikun Gao POWER_SOURCE_AC, 547ce81151cSLikun Gao POWER_SOURCE_DC, 548ce81151cSLikun Gao POWER_SOURCE_COUNT, 549ce81151cSLikun Gao } POWER_SOURCE_e; 550ce81151cSLikun Gao 551ce81151cSLikun Gao typedef enum { 552ce81151cSLikun Gao MEM_VENDOR_SAMSUNG, 553ce81151cSLikun Gao MEM_VENDOR_INFINEON, 554ce81151cSLikun Gao MEM_VENDOR_ELPIDA, 555ce81151cSLikun Gao MEM_VENDOR_ETRON, 556ce81151cSLikun Gao MEM_VENDOR_NANYA, 557ce81151cSLikun Gao MEM_VENDOR_HYNIX, 558ce81151cSLikun Gao MEM_VENDOR_MOSEL, 559ce81151cSLikun Gao MEM_VENDOR_WINBOND, 560ce81151cSLikun Gao MEM_VENDOR_ESMT, 561ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER0, 562ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER1, 563ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER2, 564ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER3, 565ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER4, 566ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER5, 567ce81151cSLikun Gao MEM_VENDOR_MICRON, 568ce81151cSLikun Gao MEM_VENDOR_COUNT, 569ce81151cSLikun Gao } MEM_VENDOR_e; 570ce81151cSLikun Gao 571ce81151cSLikun Gao typedef enum { 572ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_CTL_ZONE0, 573ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_CTL_ZONE1, 574ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_CTL_ZONE2, 575ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_CTL_ZONE3, 576ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_CTL_ZONE4, 577ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0, 578ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0, 579ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1, 580ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1, 581ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2, 582ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2, 583ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3, 584ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3, 585ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4, 586ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4, 587ce81151cSLikun Gao PP_GRTAVFS_HW_ZONE0_VF, 588ce81151cSLikun Gao PP_GRTAVFS_HW_ZONE1_VF1, 589ce81151cSLikun Gao PP_GRTAVFS_HW_ZONE2_VF2, 590ce81151cSLikun Gao PP_GRTAVFS_HW_ZONE3_VF3, 591ce81151cSLikun Gao PP_GRTAVFS_HW_VOLTAGE_GB, 592ce81151cSLikun Gao PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0, 593ce81151cSLikun Gao PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1, 594ce81151cSLikun Gao PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2, 595ce81151cSLikun Gao PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3, 596ce81151cSLikun Gao PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4, 597ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_0, 598ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_1, 599ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_2, 600ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_3, 601ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_4, 602ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_5, 603ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_6, 604ce81151cSLikun Gao PP_GRTAVFS_HW_FUSE_COUNT, 605ce81151cSLikun Gao } PP_GRTAVFS_HW_FUSE_e; 606ce81151cSLikun Gao 607ce81151cSLikun Gao typedef enum { 608ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0, 609ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0, 610ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0, 611ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0, 612ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0, 613ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0, 614ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0, 615ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0, 616ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0, 617ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1, 618ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2, 619ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3, 620ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4, 621ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_FUSE_COUNT, 622ce81151cSLikun Gao } PP_GRTAVFS_FW_COMMON_FUSE_e; 623ce81151cSLikun Gao 624ce81151cSLikun Gao typedef enum { 625ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1, 626ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0, 627ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1, 628ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2, 629ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3, 630ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4, 631ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1, 632ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0, 633ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1, 634ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2, 635ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3, 636ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4, 637ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY, 638ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY, 639ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0, 640ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1, 641ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2, 642ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3, 643ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4, 644ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_COUNT, 645ce81151cSLikun Gao } PP_GRTAVFS_FW_SEP_FUSE_e; 646ce81151cSLikun Gao 647ce81151cSLikun Gao #define PP_NUM_RTAVFS_PWL_ZONES 5 648ce81151cSLikun Gao 649ce81151cSLikun Gao 650ce81151cSLikun Gao 651ce81151cSLikun Gao // VBIOS or PPLIB configures telemetry slope and offset. Only slope expected to be set for SVI3 652ce81151cSLikun Gao // Slope Q1.7, Offset Q1.2 653ce81151cSLikun Gao typedef struct { 654ce81151cSLikun Gao int8_t Offset; // in Amps 655ce81151cSLikun Gao uint8_t Padding; 656ce81151cSLikun Gao uint16_t MaxCurrent; // in Amps 657ce81151cSLikun Gao } SviTelemetryScale_t; 658ce81151cSLikun Gao 659ce81151cSLikun Gao #define PP_NUM_OD_VF_CURVE_POINTS PP_NUM_RTAVFS_PWL_ZONES + 1 660ce81151cSLikun Gao 661ce81151cSLikun Gao 662ce81151cSLikun Gao typedef struct { 663ce81151cSLikun Gao uint32_t FeatureCtrlMask; 664ce81151cSLikun Gao 665ce81151cSLikun Gao //Voltage control 666ce81151cSLikun Gao int16_t VoltageOffsetPerZoneBoundary[PP_NUM_OD_VF_CURVE_POINTS]; 667ce81151cSLikun Gao uint16_t reserved[2]; 668ce81151cSLikun Gao 669ce81151cSLikun Gao //Frequency changes 6701c65e548SEvan Quan int16_t GfxclkFmin; // MHz 6711c65e548SEvan Quan int16_t GfxclkFmax; // MHz 672ce81151cSLikun Gao uint16_t UclkFmin; // MHz 673ce81151cSLikun Gao uint16_t UclkFmax; // MHz 674ce81151cSLikun Gao 675ce81151cSLikun Gao //PPT 676ce81151cSLikun Gao int16_t Ppt; // % 677ce81151cSLikun Gao int16_t reserved1; 678ce81151cSLikun Gao 679ce81151cSLikun Gao //Fan control 680ce81151cSLikun Gao uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS]; 681ce81151cSLikun Gao uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS]; 682ce81151cSLikun Gao uint16_t FanMinimumPwm; 6831c65e548SEvan Quan uint16_t AcousticTargetRpmThreshold; 6841c65e548SEvan Quan uint16_t AcousticLimitRpmThreshold; 685ce81151cSLikun Gao uint16_t FanTargetTemperature; // Degree Celcius 686ce81151cSLikun Gao uint8_t FanZeroRpmEnable; 687ce81151cSLikun Gao uint8_t FanZeroRpmStopTemp; 688ce81151cSLikun Gao uint8_t FanMode; 6891c65e548SEvan Quan uint8_t MaxOpTemp; 690ce81151cSLikun Gao 691ce81151cSLikun Gao uint32_t Spare[13]; 692ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround 693ce81151cSLikun Gao } OverDriveTable_t; 694ce81151cSLikun Gao 695ce81151cSLikun Gao typedef struct { 696ce81151cSLikun Gao OverDriveTable_t OverDriveTable; 697ce81151cSLikun Gao 698ce81151cSLikun Gao } OverDriveTableExternal_t; 699ce81151cSLikun Gao 700ce81151cSLikun Gao typedef struct { 701ce81151cSLikun Gao uint32_t FeatureCtrlMask; 702ce81151cSLikun Gao 703ce81151cSLikun Gao int16_t VoltageOffsetPerZoneBoundary; 704ce81151cSLikun Gao uint16_t reserved[2]; 705ce81151cSLikun Gao 706ce81151cSLikun Gao uint16_t GfxclkFmin; // MHz 707ce81151cSLikun Gao uint16_t GfxclkFmax; // MHz 708ce81151cSLikun Gao uint16_t UclkFmin; // MHz 709ce81151cSLikun Gao uint16_t UclkFmax; // MHz 710ce81151cSLikun Gao 711ce81151cSLikun Gao //PPT 712ce81151cSLikun Gao int16_t Ppt; // % 713ce81151cSLikun Gao int16_t reserved1; 714ce81151cSLikun Gao 715ce81151cSLikun Gao uint8_t FanLinearPwmPoints; 716ce81151cSLikun Gao uint8_t FanLinearTempPoints; 717ce81151cSLikun Gao uint16_t FanMinimumPwm; 7181c65e548SEvan Quan uint16_t AcousticTargetRpmThreshold; 7191c65e548SEvan Quan uint16_t AcousticLimitRpmThreshold; 720ce81151cSLikun Gao uint16_t FanTargetTemperature; // Degree Celcius 721ce81151cSLikun Gao uint8_t FanZeroRpmEnable; 722ce81151cSLikun Gao uint8_t FanZeroRpmStopTemp; 723ce81151cSLikun Gao uint8_t FanMode; 7241c65e548SEvan Quan uint8_t MaxOpTemp; 725ce81151cSLikun Gao 726ce81151cSLikun Gao uint32_t Spare[13]; 727ce81151cSLikun Gao 728ce81151cSLikun Gao } OverDriveLimits_t; 729ce81151cSLikun Gao 730ce81151cSLikun Gao 731ce81151cSLikun Gao typedef enum { 732ce81151cSLikun Gao BOARD_GPIO_SMUIO_0, 733ce81151cSLikun Gao BOARD_GPIO_SMUIO_1, 734ce81151cSLikun Gao BOARD_GPIO_SMUIO_2, 735ce81151cSLikun Gao BOARD_GPIO_SMUIO_3, 736ce81151cSLikun Gao BOARD_GPIO_SMUIO_4, 737ce81151cSLikun Gao BOARD_GPIO_SMUIO_5, 738ce81151cSLikun Gao BOARD_GPIO_SMUIO_6, 739ce81151cSLikun Gao BOARD_GPIO_SMUIO_7, 740ce81151cSLikun Gao BOARD_GPIO_SMUIO_8, 741ce81151cSLikun Gao BOARD_GPIO_SMUIO_9, 742ce81151cSLikun Gao BOARD_GPIO_SMUIO_10, 743ce81151cSLikun Gao BOARD_GPIO_SMUIO_11, 744ce81151cSLikun Gao BOARD_GPIO_SMUIO_12, 745ce81151cSLikun Gao BOARD_GPIO_SMUIO_13, 746ce81151cSLikun Gao BOARD_GPIO_SMUIO_14, 747ce81151cSLikun Gao BOARD_GPIO_SMUIO_15, 748ce81151cSLikun Gao BOARD_GPIO_SMUIO_16, 749ce81151cSLikun Gao BOARD_GPIO_SMUIO_17, 750ce81151cSLikun Gao BOARD_GPIO_SMUIO_18, 751ce81151cSLikun Gao BOARD_GPIO_SMUIO_19, 752ce81151cSLikun Gao BOARD_GPIO_SMUIO_20, 753ce81151cSLikun Gao BOARD_GPIO_SMUIO_21, 754ce81151cSLikun Gao BOARD_GPIO_SMUIO_22, 755ce81151cSLikun Gao BOARD_GPIO_SMUIO_23, 756ce81151cSLikun Gao BOARD_GPIO_SMUIO_24, 757ce81151cSLikun Gao BOARD_GPIO_SMUIO_25, 758ce81151cSLikun Gao BOARD_GPIO_SMUIO_26, 759ce81151cSLikun Gao BOARD_GPIO_SMUIO_27, 760ce81151cSLikun Gao BOARD_GPIO_SMUIO_28, 761ce81151cSLikun Gao BOARD_GPIO_SMUIO_29, 762ce81151cSLikun Gao BOARD_GPIO_SMUIO_30, 763ce81151cSLikun Gao BOARD_GPIO_SMUIO_31, 764ce81151cSLikun Gao MAX_BOARD_GPIO_SMUIO_NUM, 765ce81151cSLikun Gao BOARD_GPIO_DC_GEN_A, 766ce81151cSLikun Gao BOARD_GPIO_DC_GEN_B, 767ce81151cSLikun Gao BOARD_GPIO_DC_GEN_C, 768ce81151cSLikun Gao BOARD_GPIO_DC_GEN_D, 769ce81151cSLikun Gao BOARD_GPIO_DC_GEN_E, 770ce81151cSLikun Gao BOARD_GPIO_DC_GEN_F, 771ce81151cSLikun Gao BOARD_GPIO_DC_GEN_G, 772ce81151cSLikun Gao BOARD_GPIO_DC_GENLK_CLK, 773ce81151cSLikun Gao BOARD_GPIO_DC_GENLK_VSYNC, 774ce81151cSLikun Gao BOARD_GPIO_DC_SWAPLOCK_A, 775ce81151cSLikun Gao BOARD_GPIO_DC_SWAPLOCK_B, 776ce81151cSLikun Gao } BOARD_GPIO_TYPE_e; 777ce81151cSLikun Gao 778ce81151cSLikun Gao #define INVALID_BOARD_GPIO 0xFF 779ce81151cSLikun Gao 780ce81151cSLikun Gao 781ce81151cSLikun Gao typedef struct { 782ce81151cSLikun Gao //PLL 0 783ce81151cSLikun Gao uint16_t InitGfxclk_bypass; 784ce81151cSLikun Gao uint16_t InitSocclk; 785ce81151cSLikun Gao uint16_t InitMp0clk; 786ce81151cSLikun Gao uint16_t InitMpioclk; 787ce81151cSLikun Gao uint16_t InitSmnclk; 788ce81151cSLikun Gao uint16_t InitUcpclk; 789ce81151cSLikun Gao uint16_t InitCsrclk; 790ce81151cSLikun Gao //PLL 1 791ce81151cSLikun Gao 792ce81151cSLikun Gao uint16_t InitDprefclk; 793ce81151cSLikun Gao uint16_t InitDcfclk; 794ce81151cSLikun Gao uint16_t InitDtbclk; 795ce81151cSLikun Gao //PLL 2 796ce81151cSLikun Gao uint16_t InitDclk; //assume same DCLK/VCLK for both instances 797ce81151cSLikun Gao uint16_t InitVclk; 798ce81151cSLikun Gao // PLL 3 799ce81151cSLikun Gao uint16_t InitUsbdfsclk; 800ce81151cSLikun Gao uint16_t InitMp1clk; 801ce81151cSLikun Gao uint16_t InitLclk; 802ce81151cSLikun Gao uint16_t InitBaco400clk_bypass; 803ce81151cSLikun Gao uint16_t InitBaco1200clk_bypass; 804ce81151cSLikun Gao uint16_t InitBaco700clk_bypass; 805ce81151cSLikun Gao // PLL 4 806ce81151cSLikun Gao uint16_t InitFclk; 807ce81151cSLikun Gao // PLL 5 808ce81151cSLikun Gao uint16_t InitGfxclk_clkb; 809ce81151cSLikun Gao 810ce81151cSLikun Gao //PLL 6 811ce81151cSLikun Gao uint8_t InitUclkDPMState; // =0,1,2,3, frequency from FreqTableUclk 812ce81151cSLikun Gao 813ce81151cSLikun Gao uint8_t Padding[3]; 814ce81151cSLikun Gao 815ce81151cSLikun Gao uint32_t InitVcoFreqPll0; 816ce81151cSLikun Gao uint32_t InitVcoFreqPll1; 817ce81151cSLikun Gao uint32_t InitVcoFreqPll2; 818ce81151cSLikun Gao uint32_t InitVcoFreqPll3; 819ce81151cSLikun Gao uint32_t InitVcoFreqPll4; 820ce81151cSLikun Gao uint32_t InitVcoFreqPll5; 821ce81151cSLikun Gao uint32_t InitVcoFreqPll6; 822ce81151cSLikun Gao 823ce81151cSLikun Gao //encoding will change depending on SVI2/SVI3 824ce81151cSLikun Gao uint16_t InitGfx; // In mV(Q2) , should be 0? 825ce81151cSLikun Gao uint16_t InitSoc; // In mV(Q2) 826ce81151cSLikun Gao uint16_t InitU; // In Mv(Q2) 827ce81151cSLikun Gao 828ce81151cSLikun Gao uint16_t Padding2; 829ce81151cSLikun Gao 830ce81151cSLikun Gao uint32_t Spare[8]; 831ce81151cSLikun Gao 832ce81151cSLikun Gao } BootValues_t; 833ce81151cSLikun Gao 834ce81151cSLikun Gao 835ce81151cSLikun Gao typedef struct { 836ce81151cSLikun Gao uint16_t Power[PPT_THROTTLER_COUNT][POWER_SOURCE_COUNT]; // Watts 837ce81151cSLikun Gao uint16_t Tdc[TDC_THROTTLER_COUNT]; // Amps 838ce81151cSLikun Gao 839ce81151cSLikun Gao uint16_t Temperature[TEMP_COUNT]; // Celsius 840ce81151cSLikun Gao 841ce81151cSLikun Gao uint8_t PwmLimitMin; 842ce81151cSLikun Gao uint8_t PwmLimitMax; 843ce81151cSLikun Gao uint8_t FanTargetTemperature; 844ce81151cSLikun Gao uint8_t Spare1[1]; 845ce81151cSLikun Gao 846ce81151cSLikun Gao uint16_t AcousticTargetRpmThresholdMin; 847ce81151cSLikun Gao uint16_t AcousticTargetRpmThresholdMax; 848ce81151cSLikun Gao 849ce81151cSLikun Gao uint16_t AcousticLimitRpmThresholdMin; 850ce81151cSLikun Gao uint16_t AcousticLimitRpmThresholdMax; 851ce81151cSLikun Gao 852ce81151cSLikun Gao uint16_t PccLimitMin; 853ce81151cSLikun Gao uint16_t PccLimitMax; 854ce81151cSLikun Gao 855ce81151cSLikun Gao uint16_t FanStopTempMin; 856ce81151cSLikun Gao uint16_t FanStopTempMax; 857ce81151cSLikun Gao uint16_t FanStartTempMin; 858ce81151cSLikun Gao uint16_t FanStartTempMax; 859ce81151cSLikun Gao 860ce81151cSLikun Gao uint32_t Spare[12]; 861ce81151cSLikun Gao 862ce81151cSLikun Gao } MsgLimits_t; 863ce81151cSLikun Gao 864ce81151cSLikun Gao typedef struct { 865ce81151cSLikun Gao uint16_t BaseClockAc; 866ce81151cSLikun Gao uint16_t GameClockAc; 867ce81151cSLikun Gao uint16_t BoostClockAc; 868ce81151cSLikun Gao uint16_t BaseClockDc; 869ce81151cSLikun Gao uint16_t GameClockDc; 870ce81151cSLikun Gao uint16_t BoostClockDc; 871ce81151cSLikun Gao 872ce81151cSLikun Gao uint32_t Reserved[4]; 873ce81151cSLikun Gao } DriverReportedClocks_t; 874ce81151cSLikun Gao 875ce81151cSLikun Gao typedef struct { 876ce81151cSLikun Gao uint8_t DcBtcEnabled; 877ce81151cSLikun Gao uint8_t Padding[3]; 878ce81151cSLikun Gao 879ce81151cSLikun Gao uint16_t DcTol; // mV Q2 880ce81151cSLikun Gao uint16_t DcBtcGb; // mV Q2 881ce81151cSLikun Gao 882ce81151cSLikun Gao uint16_t DcBtcMin; // mV Q2 883ce81151cSLikun Gao uint16_t DcBtcMax; // mV Q2 884ce81151cSLikun Gao 885ce81151cSLikun Gao LinearInt_t DcBtcGbScalar; 886ce81151cSLikun Gao 887ce81151cSLikun Gao } AvfsDcBtcParams_t; 888ce81151cSLikun Gao 889ce81151cSLikun Gao typedef struct { 890ce81151cSLikun Gao uint16_t AvfsTemp[AVFS_TEMP_COUNT]; //in degrees C 891ce81151cSLikun Gao uint16_t VftFMin; // in MHz 892ce81151cSLikun Gao uint16_t VInversion; // in mV Q2 893ce81151cSLikun Gao QuadraticInt_t qVft[AVFS_TEMP_COUNT]; 894ce81151cSLikun Gao QuadraticInt_t qAvfsGb; 895ce81151cSLikun Gao QuadraticInt_t qAvfsGb2; 896ce81151cSLikun Gao } AvfsFuseOverride_t; 897ce81151cSLikun Gao 898ce81151cSLikun Gao typedef struct { 899ce81151cSLikun Gao // SECTION: Version 900ce81151cSLikun Gao 901ce81151cSLikun Gao uint32_t Version; // should be unique to each SKU(i.e if any value changes in below structure then this value must be different) 902ce81151cSLikun Gao 903ce81151cSLikun Gao // SECTION: Feature Control 904ce81151cSLikun Gao uint32_t FeaturesToRun[NUM_FEATURES / 32]; // Features that PMFW will attempt to enable. Use FEATURE_*_BIT as mapping 905ce81151cSLikun Gao 906ce81151cSLikun Gao // SECTION: Miscellaneous Configuration 907ce81151cSLikun Gao uint8_t TotalPowerConfig; // Determines how PMFW calculates the power. Use defines from PwrConfig_e 908ce81151cSLikun Gao uint8_t CustomerVariant; //To specify if this PPTable is intended for a particular customer. Use defines from CUSTOMER_VARIANT_e 909ce81151cSLikun Gao uint8_t MemoryTemperatureTypeMask; // Bit mapping indicating which methods of memory temperature reading are enabled. Use defines from MEM_TEMP_*BIT 910ce81151cSLikun Gao uint8_t SmartShiftVersion; // Determine what SmartShift feature version is supported Use defines from SMARTSHIFT_VERSION_e 911ce81151cSLikun Gao 912ce81151cSLikun Gao // SECTION: Infrastructure Limits 913ce81151cSLikun Gao uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in AC mode. Multiple limits supported 914ce81151cSLikun Gao uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in DC mode. Multiple limits supported 915ce81151cSLikun Gao 916ce81151cSLikun Gao uint16_t SocketPowerLimitSmartShift2; // In Watts. Power limit used SmartShift 917ce81151cSLikun Gao 918ce81151cSLikun Gao //if set to 1, SocketPowerLimitAc and SocketPowerLimitDc will be interpreted as legacy programs(i.e absolute power). If 0, all except index 0 will be scalars 919ce81151cSLikun Gao //relative index 0 920ce81151cSLikun Gao uint8_t EnableLegacyPptLimit; 921ce81151cSLikun Gao uint8_t UseInputTelemetry; //applicable to SVI3 only and only to be set if VRs support 922ce81151cSLikun Gao uint8_t SmartShiftMinReportedPptinDcs; //minimum possible active power consumption for this SKU. Used for SmartShift power reporting 923ce81151cSLikun Gao 924ce81151cSLikun Gao uint8_t PaddingPpt[1]; 925ce81151cSLikun Gao 926ce81151cSLikun Gao uint16_t VrTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with VR regulator maximum temperature 927ce81151cSLikun Gao 928ce81151cSLikun Gao uint16_t PlatformTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with platform maximum temperature per VR current rail 929ce81151cSLikun Gao 930ce81151cSLikun Gao uint16_t TemperatureLimit[TEMP_COUNT]; // In degrees Celsius. Temperature limit associated with each input 931ce81151cSLikun Gao 932ce81151cSLikun Gao uint16_t HwCtfTempLimit; // In degrees Celsius. Temperature above which HW will trigger CTF. Consumed by VBIOS only 933ce81151cSLikun Gao 934ce81151cSLikun Gao uint16_t PaddingInfra; 935ce81151cSLikun Gao 936ce81151cSLikun Gao // Per year normalized Vmax state failure rates (sum of the two domains divided by life time in years) 937ce81151cSLikun Gao uint32_t FitControllerFailureRateLimit; //in IEEE float 938ce81151cSLikun Gao //Expected GFX Duty Cycle at Vmax. 939ce81151cSLikun Gao uint32_t FitControllerGfxDutyCycle; // in IEEE float 940ce81151cSLikun Gao //Expected SOC Duty Cycle at Vmax. 941ce81151cSLikun Gao uint32_t FitControllerSocDutyCycle; // in IEEE float 942ce81151cSLikun Gao 943ce81151cSLikun Gao //This offset will be deducted from the controller output to before it goes through the SOC Vset limiter block. 944ce81151cSLikun Gao uint32_t FitControllerSocOffset; //in IEEE float 945ce81151cSLikun Gao 946ce81151cSLikun Gao uint32_t GfxApccPlusResidencyLimit; // Percentage value. Used by APCC+ controller to control PCC residency to some value 947ce81151cSLikun Gao 948ce81151cSLikun Gao // SECTION: Throttler settings 949ce81151cSLikun Gao uint32_t ThrottlerControlMask; // See THROTTLER_*_BIT for mapping 950ce81151cSLikun Gao 951ce81151cSLikun Gao // SECTION: FW DSTATE Settings 952ce81151cSLikun Gao uint32_t FwDStateMask; // See FW_DSTATE_*_BIT for mapping 953ce81151cSLikun Gao 954ce81151cSLikun Gao // SECTION: Voltage Control Parameters 955ce81151cSLikun Gao uint16_t UlvVoltageOffset[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2). ULV offset used in either GFX_ULV or SOC_ULV(part of FW_DSTATE) 956ce81151cSLikun Gao 957ce81151cSLikun Gao uint16_t UlvVoltageOffsetU; // In mV(Q2). ULV offset used in either U_ULV(part of FW_DSTATE) 958ce81151cSLikun Gao uint16_t DeepUlvVoltageOffsetSoc; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC as part of FW_DSTATE 959ce81151cSLikun Gao 960ce81151cSLikun Gao // Voltage Limits 961ce81151cSLikun Gao uint16_t DefaultMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage without FIT controller enabled 962ce81151cSLikun Gao uint16_t BoostMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage with FIT controller enabled 963ce81151cSLikun Gao 964ce81151cSLikun Gao //Vmin Optimizations 965ce81151cSLikun Gao int16_t VminTempHystersis[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature hysteresis for switching between low/high temperature values for Vmin 966ce81151cSLikun Gao int16_t VminTempThreshold[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature threshold for switching between low/high temperature values for Vmin 967ce81151cSLikun Gao uint16_t Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at hot. 968ce81151cSLikun Gao uint16_t Vmin_Cold_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at cold. 969ce81151cSLikun Gao uint16_t Vmin_Hot_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at hot. 970ce81151cSLikun Gao uint16_t Vmin_Cold_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at cold. 971ce81151cSLikun Gao uint16_t Vmin_Aging_Offset[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Worst-case aging margin 97225dfc8faSEvan Quan uint16_t Spare_Vmin_Plat_Offset_Hot[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Hot 97325dfc8faSEvan Quan uint16_t Spare_Vmin_Plat_Offset_Cold[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Cold 974ce81151cSLikun Gao 975ce81151cSLikun Gao //This is a fixed/minimum VMIN aging degradation offset which is applied at T0. This reflects the minimum amount of aging already accounted for. 976ce81151cSLikun Gao uint16_t VcBtcFixedVminAgingOffset[PMFW_VOLT_PLANE_COUNT]; 977ce81151cSLikun Gao //Linear offset or GB term to account for mis-correlation between PSM and Vmin shift trends across parts. 978ce81151cSLikun Gao uint16_t VcBtcVmin2PsmDegrationGb[PMFW_VOLT_PLANE_COUNT]; 979ce81151cSLikun Gao //Scalar coefficient of the PSM aging degradation function 980ce81151cSLikun Gao uint32_t VcBtcPsmA[PMFW_VOLT_PLANE_COUNT]; // A_PSM 981ce81151cSLikun Gao //Exponential coefficient of the PSM aging degradation function 982ce81151cSLikun Gao uint32_t VcBtcPsmB[PMFW_VOLT_PLANE_COUNT]; // B_PSM 983ce81151cSLikun Gao //Scalar coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 984ce81151cSLikun Gao uint32_t VcBtcVminA[PMFW_VOLT_PLANE_COUNT]; // A_VMIN 985ce81151cSLikun Gao //Exponential coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 986ce81151cSLikun Gao uint32_t VcBtcVminB[PMFW_VOLT_PLANE_COUNT]; // B_VMIN 987ce81151cSLikun Gao 988ce81151cSLikun Gao uint8_t PerPartVminEnabled[PMFW_VOLT_PLANE_COUNT]; 989ce81151cSLikun Gao uint8_t VcBtcEnabled[PMFW_VOLT_PLANE_COUNT]; 990ce81151cSLikun Gao 991ce81151cSLikun Gao uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 992ce81151cSLikun Gao uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 993ce81151cSLikun Gao 9941c65e548SEvan Quan QuadraticInt_t Vmin_droop; 9951c65e548SEvan Quan uint32_t SpareVmin[9]; 996ce81151cSLikun Gao 997ce81151cSLikun Gao 998ce81151cSLikun Gao //SECTION: DPM Configuration 1 999ce81151cSLikun Gao DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 1000ce81151cSLikun Gao 1001ce81151cSLikun Gao uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1002ce81151cSLikun Gao uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1003ce81151cSLikun Gao uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1004ce81151cSLikun Gao uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1005ce81151cSLikun Gao uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1006ce81151cSLikun Gao uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1007ce81151cSLikun Gao uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1008ce81151cSLikun Gao uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1009ce81151cSLikun Gao uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1010ce81151cSLikun Gao uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1011ce81151cSLikun Gao uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1012ce81151cSLikun Gao 1013ce81151cSLikun Gao uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1014ce81151cSLikun Gao 1015ce81151cSLikun Gao // SECTION: DPM Configuration 2 1016ce81151cSLikun Gao uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 1017ce81151cSLikun Gao uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 1018ce81151cSLikun Gao 1019ce81151cSLikun Gao uint8_t GfxclkSpare[2]; 1020ce81151cSLikun Gao uint16_t GfxclkFreqCap; 1021ce81151cSLikun Gao 1022ce81151cSLikun Gao //GFX Idle Power Settings 1023ce81151cSLikun Gao uint16_t GfxclkFgfxoffEntry; // in Mhz 1024ce81151cSLikun Gao uint16_t GfxclkFgfxoffExitImu; // in Mhz 1025ce81151cSLikun Gao uint16_t GfxclkFgfxoffExitRlc; // in Mhz 1026ce81151cSLikun Gao uint16_t GfxclkThrottleClock; //Used primarily in DCS 1027ce81151cSLikun Gao uint8_t EnableGfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages 1028ce81151cSLikun Gao uint8_t GfxIdlePadding; 1029ce81151cSLikun Gao 1030ce81151cSLikun Gao uint8_t SmsRepairWRCKClkDivEn; 1031ce81151cSLikun Gao uint8_t SmsRepairWRCKClkDivVal; 1032ce81151cSLikun Gao uint8_t GfxOffEntryEarlyMGCGEn; 1033ce81151cSLikun Gao uint8_t GfxOffEntryForceCGCGEn; 1034ce81151cSLikun Gao uint8_t GfxOffEntryForceCGCGDelayEn; 1035ce81151cSLikun Gao uint8_t GfxOffEntryForceCGCGDelayVal; // in microseconds 1036ce81151cSLikun Gao 1037ce81151cSLikun Gao uint16_t GfxclkFreqGfxUlv; // in MHz 1038ce81151cSLikun Gao uint8_t GfxIdlePadding2[2]; 1039ce81151cSLikun Gao 1040cbe07c98SEvan Quan uint32_t GfxOffEntryHysteresis; 1041cbe07c98SEvan Quan uint32_t GfxoffSpare[15]; 1042ce81151cSLikun Gao 1043ce81151cSLikun Gao // GFX GPO 1044ce81151cSLikun Gao uint32_t GfxGpoSpare[16]; 1045ce81151cSLikun Gao 1046ce81151cSLikun Gao // GFX DCS 1047ce81151cSLikun Gao 1048ce81151cSLikun Gao uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase 1049ce81151cSLikun Gao uint16_t PaddingDcs; 1050ce81151cSLikun Gao 1051ce81151cSLikun Gao uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase 1052ce81151cSLikun Gao uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. 1053ce81151cSLikun Gao 1054ce81151cSLikun Gao uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS. 1055ce81151cSLikun Gao 1056ce81151cSLikun Gao uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. 1057ce81151cSLikun Gao uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin. 1058ce81151cSLikun Gao 1059ce81151cSLikun Gao 1060ce81151cSLikun Gao uint32_t DcsSpare[16]; 1061ce81151cSLikun Gao 1062ce81151cSLikun Gao // UCLK section 1063ce81151cSLikun Gao uint8_t UseStrobeModeOptimizations; //Set to indicate that FW should use strobe mode optimizations 1064ce81151cSLikun Gao uint8_t PaddingMem[3]; 1065ce81151cSLikun Gao 1066ce81151cSLikun Gao uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 1067ce81151cSLikun Gao uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 1068ce81151cSLikun Gao 1069ce81151cSLikun Gao uint16_t MemVmempVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1070ce81151cSLikun Gao uint16_t MemVddioVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1071ce81151cSLikun Gao 1072ce81151cSLikun Gao //FCLK Section 1073ce81151cSLikun Gao 1074ce81151cSLikun Gao uint8_t FclkDpmUPstates[NUM_FCLK_DPM_LEVELS]; // U P-state ID associated with each FCLK DPM state. 1075ce81151cSLikun Gao uint16_t FclkDpmVddU[NUM_FCLK_DPM_LEVELS]; // mV(Q2) Vset U voltage associated with each FCLK DPM state. 1076ce81151cSLikun Gao uint16_t FclkDpmUSpeed[NUM_FCLK_DPM_LEVELS]; //U speed associated with each FCLK DPM state 1077ce81151cSLikun Gao uint16_t FclkDpmDisallowPstateFreq; //Frequency which FW will target when indicated that display config cannot support P-state. Set to 0 use FW calculated value 1078ce81151cSLikun Gao uint16_t PaddingFclk; 1079ce81151cSLikun Gao 1080ce81151cSLikun Gao // Link DPM Settings 1081ce81151cSLikun Gao uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 1082ce81151cSLikun Gao uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 1083ce81151cSLikun Gao uint16_t LclkFreq[NUM_LINK_LEVELS]; 1084ce81151cSLikun Gao 1085ce81151cSLikun Gao // SECTION: Fan Control 1086ce81151cSLikun Gao uint16_t FanStopTemp[TEMP_COUNT]; //Celsius 1087ce81151cSLikun Gao uint16_t FanStartTemp[TEMP_COUNT]; //Celsius 1088ce81151cSLikun Gao 1089ce81151cSLikun Gao uint16_t FanGain[TEMP_COUNT]; 1090ce81151cSLikun Gao uint16_t FanGainPadding; 1091ce81151cSLikun Gao 1092ce81151cSLikun Gao uint16_t FanPwmMin; 1093ce81151cSLikun Gao uint16_t AcousticTargetRpmThreshold; 1094ce81151cSLikun Gao uint16_t AcousticLimitRpmThreshold; 1095ce81151cSLikun Gao uint16_t FanMaximumRpm; 1096ce81151cSLikun Gao uint16_t MGpuAcousticLimitRpmThreshold; 1097ce81151cSLikun Gao uint16_t FanTargetGfxclk; 1098ce81151cSLikun Gao uint32_t TempInputSelectMask; 1099ce81151cSLikun Gao uint8_t FanZeroRpmEnable; 1100ce81151cSLikun Gao uint8_t FanTachEdgePerRev; 1101ce81151cSLikun Gao uint16_t FanTargetTemperature[TEMP_COUNT]; 1102ce81151cSLikun Gao 1103ce81151cSLikun Gao // The following are AFC override parameters. Leave at 0 to use FW defaults. 1104ce81151cSLikun Gao int16_t FuzzyFan_ErrorSetDelta; 1105ce81151cSLikun Gao int16_t FuzzyFan_ErrorRateSetDelta; 1106ce81151cSLikun Gao int16_t FuzzyFan_PwmSetDelta; 1107ce81151cSLikun Gao uint16_t FuzzyFan_Reserved; 1108ce81151cSLikun Gao 1109ce81151cSLikun Gao uint16_t FwCtfLimit[TEMP_COUNT]; 1110ce81151cSLikun Gao 1111ce81151cSLikun Gao uint16_t IntakeTempEnableRPM; 1112ce81151cSLikun Gao int16_t IntakeTempOffsetTemp; 1113ce81151cSLikun Gao uint16_t IntakeTempReleaseTemp; 1114ce81151cSLikun Gao uint16_t IntakeTempHighIntakeAcousticLimit; 1115ce81151cSLikun Gao uint16_t IntakeTempAcouticLimitReleaseRate; 1116ce81151cSLikun Gao 1117ce81151cSLikun Gao uint16_t FanStalledTempLimitOffset; 1118ce81151cSLikun Gao uint16_t FanStalledTriggerRpm; 1119ce81151cSLikun Gao uint16_t FanAbnormalTriggerRpm; 1120ce81151cSLikun Gao uint16_t FanPadding; 1121ce81151cSLikun Gao 1122ce81151cSLikun Gao uint32_t FanSpare[14]; 1123ce81151cSLikun Gao 1124ce81151cSLikun Gao // SECTION: VDD_GFX AVFS 1125ce81151cSLikun Gao 1126ce81151cSLikun Gao uint8_t OverrideGfxAvfsFuses; 1127ce81151cSLikun Gao uint8_t GfxAvfsPadding[3]; 1128ce81151cSLikun Gao 1129ce81151cSLikun Gao uint32_t L2HwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; //see fusedoc for encoding 1130ce81151cSLikun Gao uint32_t SeHwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; 1131ce81151cSLikun Gao 1132ce81151cSLikun Gao uint32_t CommonRtAvfs[PP_GRTAVFS_FW_COMMON_FUSE_COUNT]; 1133ce81151cSLikun Gao 1134ce81151cSLikun Gao uint32_t L2FwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1135ce81151cSLikun Gao uint32_t SeFwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1136ce81151cSLikun Gao 1137ce81151cSLikun Gao uint32_t Droop_PWL_F[PP_NUM_RTAVFS_PWL_ZONES]; 1138ce81151cSLikun Gao uint32_t Droop_PWL_a[PP_NUM_RTAVFS_PWL_ZONES]; 1139ce81151cSLikun Gao uint32_t Droop_PWL_b[PP_NUM_RTAVFS_PWL_ZONES]; 1140ce81151cSLikun Gao uint32_t Droop_PWL_c[PP_NUM_RTAVFS_PWL_ZONES]; 1141ce81151cSLikun Gao 1142ce81151cSLikun Gao uint32_t Static_PWL_Offset[PP_NUM_RTAVFS_PWL_ZONES]; 1143ce81151cSLikun Gao 1144ce81151cSLikun Gao uint32_t dGbV_dT_vmin; 1145ce81151cSLikun Gao uint32_t dGbV_dT_vmax; 1146ce81151cSLikun Gao 1147ce81151cSLikun Gao //Unused: PMFW-9370 1148ce81151cSLikun Gao uint32_t V2F_vmin_range_low; 1149ce81151cSLikun Gao uint32_t V2F_vmin_range_high; 1150ce81151cSLikun Gao uint32_t V2F_vmax_range_low; 1151ce81151cSLikun Gao uint32_t V2F_vmax_range_high; 1152ce81151cSLikun Gao 1153ce81151cSLikun Gao AvfsDcBtcParams_t DcBtcGfxParams; 1154ce81151cSLikun Gao 1155ce81151cSLikun Gao uint32_t GfxAvfsSpare[32]; 1156ce81151cSLikun Gao 1157ce81151cSLikun Gao //SECTION: VDD_SOC AVFS 1158ce81151cSLikun Gao 1159ce81151cSLikun Gao uint8_t OverrideSocAvfsFuses; 1160ce81151cSLikun Gao uint8_t MinSocAvfsRevision; 1161ce81151cSLikun Gao uint8_t SocAvfsPadding[2]; 1162ce81151cSLikun Gao 1163ce81151cSLikun Gao AvfsFuseOverride_t SocAvfsFuseOverride[AVFS_D_COUNT]; 1164ce81151cSLikun Gao 1165ce81151cSLikun Gao DroopInt_t dBtcGbSoc[AVFS_D_COUNT]; // GHz->V BtcGb 1166ce81151cSLikun Gao 1167ce81151cSLikun Gao LinearInt_t qAgingGb[AVFS_D_COUNT]; // GHz->V 1168ce81151cSLikun Gao 1169ce81151cSLikun Gao QuadraticInt_t qStaticVoltageOffset[AVFS_D_COUNT]; // GHz->V 1170ce81151cSLikun Gao 1171ce81151cSLikun Gao AvfsDcBtcParams_t DcBtcSocParams[AVFS_D_COUNT]; 1172ce81151cSLikun Gao 1173ce81151cSLikun Gao uint32_t SocAvfsSpare[32]; 1174ce81151cSLikun Gao 1175ce81151cSLikun Gao //SECTION: Boot clock and voltage values 1176ce81151cSLikun Gao BootValues_t BootValues; 1177ce81151cSLikun Gao 1178ce81151cSLikun Gao //SECTION: Driver Reported Clocks 1179ce81151cSLikun Gao DriverReportedClocks_t DriverReportedClocks; 1180ce81151cSLikun Gao 1181ce81151cSLikun Gao //SECTION: Message Limits 1182ce81151cSLikun Gao MsgLimits_t MsgLimits; 1183ce81151cSLikun Gao 1184ce81151cSLikun Gao //SECTION: OverDrive Limits 1185ce81151cSLikun Gao OverDriveLimits_t OverDriveLimitsMin; 1186ce81151cSLikun Gao OverDriveLimits_t OverDriveLimitsBasicMax; 1187ce81151cSLikun Gao uint32_t reserved[22]; 1188ce81151cSLikun Gao 1189ce81151cSLikun Gao // SECTION: Advanced Options 1190ce81151cSLikun Gao uint32_t DebugOverrides; 1191ce81151cSLikun Gao 1192*da1acbb1SEvan Quan // Section: Total Board Power idle vs active coefficients 1193*da1acbb1SEvan Quan uint8_t TotalBoardPowerSupport; 1194*da1acbb1SEvan Quan uint8_t TotalBoardPowerPadding[3]; 1195*da1acbb1SEvan Quan 1196*da1acbb1SEvan Quan int16_t TotalIdleBoardPowerM; 1197*da1acbb1SEvan Quan int16_t TotalIdleBoardPowerB; 1198*da1acbb1SEvan Quan int16_t TotalBoardPowerM; 1199*da1acbb1SEvan Quan int16_t TotalBoardPowerB; 1200*da1acbb1SEvan Quan 1201ce81151cSLikun Gao // SECTION: Sku Reserved 1202*da1acbb1SEvan Quan uint32_t Spare[61]; 1203ce81151cSLikun Gao 1204ce81151cSLikun Gao // Padding for MMHUB - do not modify this 1205ce81151cSLikun Gao uint32_t MmHubPadding[8]; 1206ce81151cSLikun Gao 1207ce81151cSLikun Gao } SkuTable_t; 1208ce81151cSLikun Gao 1209ce81151cSLikun Gao typedef struct { 1210ce81151cSLikun Gao // SECTION: Version 1211ce81151cSLikun Gao uint32_t Version; //should be unique to each board type 1212ce81151cSLikun Gao 1213ce81151cSLikun Gao 1214ce81151cSLikun Gao // SECTION: I2C Control 1215ce81151cSLikun Gao I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 1216ce81151cSLikun Gao 1217ce81151cSLikun Gao // SECTION: SVI2 Board Parameters 1218ce81151cSLikun Gao uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 1219ce81151cSLikun Gao uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 1220ce81151cSLikun Gao uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 1221ce81151cSLikun Gao uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 1222ce81151cSLikun Gao 1223ce81151cSLikun Gao uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1224ce81151cSLikun Gao uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1225ce81151cSLikun Gao uint8_t VmempUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1226ce81151cSLikun Gao uint8_t VddioUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1227ce81151cSLikun Gao 1228ce81151cSLikun Gao //SECTION SVI3 Board Parameters 1229ce81151cSLikun Gao uint8_t SlaveAddrMapping[SVI_PLANE_COUNT]; 1230ce81151cSLikun Gao uint8_t VrPsiSupport[SVI_PLANE_COUNT]; 1231ce81151cSLikun Gao 1232ce81151cSLikun Gao uint8_t PaddingPsi[SVI_PLANE_COUNT]; 1233ce81151cSLikun Gao uint8_t EnablePsi6[SVI_PLANE_COUNT]; // only applicable in SVI3 1234ce81151cSLikun Gao 1235ce81151cSLikun Gao // SECTION: Voltage Regulator Settings 1236ce81151cSLikun Gao SviTelemetryScale_t SviTelemetryScale[SVI_PLANE_COUNT]; 1237ce81151cSLikun Gao uint32_t VoltageTelemetryRatio[SVI_PLANE_COUNT]; // This is used for VDDIO Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 1238ce81151cSLikun Gao 1239ce81151cSLikun Gao uint8_t DownSlewRateVr[SVI_PLANE_COUNT]; 1240ce81151cSLikun Gao 1241ce81151cSLikun Gao // SECTION: GPIO Settings 1242ce81151cSLikun Gao 1243ce81151cSLikun Gao uint8_t LedOffGpio; 1244ce81151cSLikun Gao uint8_t FanOffGpio; 1245ce81151cSLikun Gao uint8_t GfxVrPowerStageOffGpio; 1246ce81151cSLikun Gao 1247ce81151cSLikun Gao uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 1248ce81151cSLikun Gao uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 1249ce81151cSLikun Gao uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 1250ce81151cSLikun Gao uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 1251ce81151cSLikun Gao 1252ce81151cSLikun Gao uint8_t GthrGpio; // GPIO pin configured for GTHR Event 1253ce81151cSLikun Gao uint8_t GthrPolarity; // replace GPIO polarity for GTHR 1254ce81151cSLikun Gao 1255ce81151cSLikun Gao // LED Display Settings 1256ce81151cSLikun Gao uint8_t LedPin0; // GPIO number for LedPin[0] 1257ce81151cSLikun Gao uint8_t LedPin1; // GPIO number for LedPin[1] 1258ce81151cSLikun Gao uint8_t LedPin2; // GPIO number for LedPin[2] 1259ce81151cSLikun Gao uint8_t LedEnableMask; 1260ce81151cSLikun Gao 1261ce81151cSLikun Gao uint8_t LedPcie; // GPIO number for PCIE results 1262ce81151cSLikun Gao uint8_t LedError; // GPIO number for Error Cases 1263ce81151cSLikun Gao 1264ce81151cSLikun Gao // SECTION: Clock Spread Spectrum 1265ce81151cSLikun Gao 1266ce81151cSLikun Gao // UCLK Spread Spectrum 1267*da1acbb1SEvan Quan uint8_t UclkTrainingModeSpreadPercent; 1268*da1acbb1SEvan Quan uint8_t UclkSpreadPadding; 1269ce81151cSLikun Gao uint16_t UclkSpreadFreq; // kHz 1270ce81151cSLikun Gao 1271ce81151cSLikun Gao // UCLK Spread Spectrum 1272ce81151cSLikun Gao uint8_t UclkSpreadPercent[MEM_VENDOR_COUNT]; 1273ce81151cSLikun Gao 1274ce81151cSLikun Gao // FCLK Spread Spectrum 1275ce81151cSLikun Gao uint8_t FclkSpreadPadding; 1276ce81151cSLikun Gao uint8_t FclkSpreadPercent; // Q4.4 1277ce81151cSLikun Gao uint16_t FclkSpreadFreq; // kHz 1278ce81151cSLikun Gao 1279ce81151cSLikun Gao // Section: Memory Config 1280ce81151cSLikun Gao uint8_t DramWidth; // Width of interface to the channel for each DRAM module. See DRAM_BIT_WIDTH_TYPE_e 1281*da1acbb1SEvan Quan uint8_t PaddingMem1[7]; 1282ce81151cSLikun Gao 1283ce81151cSLikun Gao // SECTION: UMC feature flags 1284ce81151cSLikun Gao uint8_t HsrEnabled; 1285ce81151cSLikun Gao uint8_t VddqOffEnabled; 1286ce81151cSLikun Gao uint8_t PaddingUmcFlags[2]; 1287ce81151cSLikun Gao 1288ce81151cSLikun Gao uint32_t PostVoltageSetBacoDelay; // in microseconds. Amount of time FW will wait after power good is established or PSI0 command is issued 1289ce81151cSLikun Gao uint32_t BacoEntryDelay; // in milliseconds. Amount of time FW will wait to trigger BACO entry after receiving entry notification from OS 1290ce81151cSLikun Gao 1291ce81151cSLikun Gao // SECTION: Board Reserved 1292ce81151cSLikun Gao uint32_t BoardSpare[64]; 1293ce81151cSLikun Gao 1294ce81151cSLikun Gao // SECTION: Structure Padding 1295ce81151cSLikun Gao 1296ce81151cSLikun Gao // Padding for MMHUB - do not modify this 1297ce81151cSLikun Gao uint32_t MmHubPadding[8]; 1298ce81151cSLikun Gao } BoardTable_t; 1299ce81151cSLikun Gao 1300ce81151cSLikun Gao typedef struct { 1301ce81151cSLikun Gao SkuTable_t SkuTable; 1302ce81151cSLikun Gao BoardTable_t BoardTable; 1303ce81151cSLikun Gao } PPTable_t; 1304ce81151cSLikun Gao 1305ce81151cSLikun Gao typedef struct { 1306ce81151cSLikun Gao // Time constant parameters for clock averages in ms 1307ce81151cSLikun Gao uint16_t GfxclkAverageLpfTau; 1308ce81151cSLikun Gao uint16_t FclkAverageLpfTau; 1309ce81151cSLikun Gao uint16_t UclkAverageLpfTau; 1310ce81151cSLikun Gao uint16_t GfxActivityLpfTau; 1311ce81151cSLikun Gao uint16_t UclkActivityLpfTau; 1312ce81151cSLikun Gao uint16_t SocketPowerLpfTau; 1313ce81151cSLikun Gao uint16_t VcnClkAverageLpfTau; 1314ce81151cSLikun Gao uint16_t VcnUsageAverageLpfTau; 1315ce81151cSLikun Gao } DriverSmuConfig_t; 1316ce81151cSLikun Gao 1317ce81151cSLikun Gao typedef struct { 1318ce81151cSLikun Gao DriverSmuConfig_t DriverSmuConfig; 1319ce81151cSLikun Gao 1320ce81151cSLikun Gao uint32_t Spare[8]; 1321ce81151cSLikun Gao // Padding - ignore 1322ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1323ce81151cSLikun Gao } DriverSmuConfigExternal_t; 1324ce81151cSLikun Gao 1325ce81151cSLikun Gao 1326ce81151cSLikun Gao typedef struct { 1327ce81151cSLikun Gao 1328ce81151cSLikun Gao uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1329ce81151cSLikun Gao uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1330ce81151cSLikun Gao uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1331ce81151cSLikun Gao uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1332ce81151cSLikun Gao uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1333ce81151cSLikun Gao uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1334ce81151cSLikun Gao uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1335ce81151cSLikun Gao uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1336ce81151cSLikun Gao uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1337ce81151cSLikun Gao uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1338ce81151cSLikun Gao uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1339ce81151cSLikun Gao 1340ce81151cSLikun Gao uint16_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1341ce81151cSLikun Gao 1342ce81151cSLikun Gao uint16_t Padding; 1343ce81151cSLikun Gao 1344ce81151cSLikun Gao uint32_t Spare[32]; 1345ce81151cSLikun Gao 1346ce81151cSLikun Gao // Padding - ignore 1347ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1348ce81151cSLikun Gao 1349ce81151cSLikun Gao } DriverInfoTable_t; 1350ce81151cSLikun Gao 1351ce81151cSLikun Gao typedef struct { 1352ce81151cSLikun Gao uint32_t CurrClock[PPCLK_COUNT]; 1353ce81151cSLikun Gao 1354ce81151cSLikun Gao uint16_t AverageGfxclkFrequencyTarget; 1355ce81151cSLikun Gao uint16_t AverageGfxclkFrequencyPreDs; 1356ce81151cSLikun Gao uint16_t AverageGfxclkFrequencyPostDs; 1357ce81151cSLikun Gao uint16_t AverageFclkFrequencyPreDs; 1358ce81151cSLikun Gao uint16_t AverageFclkFrequencyPostDs; 1359ce81151cSLikun Gao uint16_t AverageMemclkFrequencyPreDs ; // this is scaled to actual memory clock 1360ce81151cSLikun Gao uint16_t AverageMemclkFrequencyPostDs ; // this is scaled to actual memory clock 1361ce81151cSLikun Gao uint16_t AverageVclk0Frequency ; 1362ce81151cSLikun Gao uint16_t AverageDclk0Frequency ; 1363ce81151cSLikun Gao uint16_t AverageVclk1Frequency ; 1364ce81151cSLikun Gao uint16_t AverageDclk1Frequency ; 136566f54992SEvan Quan uint16_t PCIeBusy; 136666f54992SEvan Quan uint16_t dGPU_W_MAX; 136766f54992SEvan Quan uint16_t padding; 136866f54992SEvan Quan 136966f54992SEvan Quan uint32_t MetricsCounter; 1370ce81151cSLikun Gao 1371ce81151cSLikun Gao uint16_t AvgVoltage[SVI_PLANE_COUNT]; 137266f54992SEvan Quan uint16_t AvgCurrent[SVI_PLANE_COUNT]; 1373ce81151cSLikun Gao 1374ce81151cSLikun Gao uint16_t AverageGfxActivity ; 1375ce81151cSLikun Gao uint16_t AverageUclkActivity ; 1376ce81151cSLikun Gao uint16_t Vcn0ActivityPercentage ; 1377ce81151cSLikun Gao uint16_t Vcn1ActivityPercentage ; 1378ce81151cSLikun Gao 1379ce81151cSLikun Gao uint32_t EnergyAccumulator; 1380ce81151cSLikun Gao uint16_t AverageSocketPower; 1381*da1acbb1SEvan Quan uint16_t AverageTotalBoardPower; 1382*da1acbb1SEvan Quan 1383ce81151cSLikun Gao uint16_t AvgTemperature[TEMP_COUNT]; 1384*da1acbb1SEvan Quan uint16_t TempPadding; 1385ce81151cSLikun Gao 1386ce81151cSLikun Gao uint8_t PcieRate ; 1387ce81151cSLikun Gao uint8_t PcieWidth ; 1388ce81151cSLikun Gao 1389ce81151cSLikun Gao uint8_t AvgFanPwm; 1390ce81151cSLikun Gao uint8_t Padding[1]; 1391ce81151cSLikun Gao uint16_t AvgFanRpm; 1392ce81151cSLikun Gao 1393ce81151cSLikun Gao 1394ce81151cSLikun Gao uint8_t ThrottlingPercentage[THROTTLER_COUNT]; 1395ce81151cSLikun Gao 1396ce81151cSLikun Gao //metrics for D3hot entry/exit and driver ARM msgs 1397ce81151cSLikun Gao uint32_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; 1398ce81151cSLikun Gao uint32_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT]; 1399ce81151cSLikun Gao uint32_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT]; 1400ce81151cSLikun Gao 1401ce81151cSLikun Gao uint16_t ApuSTAPMSmartShiftLimit; 1402ce81151cSLikun Gao uint16_t ApuSTAPMLimit; 1403ce81151cSLikun Gao uint16_t AvgApuSocketPower; 1404ce81151cSLikun Gao 1405ce81151cSLikun Gao uint16_t AverageUclkActivity_MAX; 1406ce81151cSLikun Gao 1407ce81151cSLikun Gao uint32_t PublicSerialNumberLower; 1408ce81151cSLikun Gao uint32_t PublicSerialNumberUpper; 1409ce81151cSLikun Gao 1410ce81151cSLikun Gao } SmuMetrics_t; 1411ce81151cSLikun Gao 1412ce81151cSLikun Gao typedef struct { 1413ce81151cSLikun Gao SmuMetrics_t SmuMetrics; 1414ce81151cSLikun Gao uint32_t Spare[30]; 1415ce81151cSLikun Gao 1416ce81151cSLikun Gao // Padding - ignore 1417ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1418ce81151cSLikun Gao } SmuMetricsExternal_t; 1419ce81151cSLikun Gao 1420ce81151cSLikun Gao typedef struct { 1421ce81151cSLikun Gao uint8_t WmSetting; 1422ce81151cSLikun Gao uint8_t Flags; 1423ce81151cSLikun Gao uint8_t Padding[2]; 1424ce81151cSLikun Gao 1425ce81151cSLikun Gao } WatermarkRowGeneric_t; 1426ce81151cSLikun Gao 1427ce81151cSLikun Gao #define NUM_WM_RANGES 4 1428ce81151cSLikun Gao 1429ce81151cSLikun Gao typedef enum { 1430ce81151cSLikun Gao WATERMARKS_CLOCK_RANGE = 0, 1431ce81151cSLikun Gao WATERMARKS_DUMMY_PSTATE, 1432ce81151cSLikun Gao WATERMARKS_MALL, 1433ce81151cSLikun Gao WATERMARKS_COUNT, 1434ce81151cSLikun Gao } WATERMARKS_FLAGS_e; 1435ce81151cSLikun Gao 1436ce81151cSLikun Gao typedef struct { 1437ce81151cSLikun Gao // Watermarks 1438ce81151cSLikun Gao WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES]; 1439ce81151cSLikun Gao } Watermarks_t; 1440ce81151cSLikun Gao 1441ce81151cSLikun Gao typedef struct { 1442ce81151cSLikun Gao Watermarks_t Watermarks; 1443ce81151cSLikun Gao uint32_t Spare[16]; 1444ce81151cSLikun Gao 1445ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1446ce81151cSLikun Gao } WatermarksExternal_t; 1447ce81151cSLikun Gao 1448ce81151cSLikun Gao typedef struct { 1449ce81151cSLikun Gao uint16_t avgPsmCount[214]; 1450ce81151cSLikun Gao uint16_t minPsmCount[214]; 1451ce81151cSLikun Gao float avgPsmVoltage[214]; 1452ce81151cSLikun Gao float minPsmVoltage[214]; 1453ce81151cSLikun Gao } AvfsDebugTable_t; 1454ce81151cSLikun Gao 1455ce81151cSLikun Gao typedef struct { 1456ce81151cSLikun Gao AvfsDebugTable_t AvfsDebugTable; 1457ce81151cSLikun Gao 1458ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1459ce81151cSLikun Gao } AvfsDebugTableExternal_t; 1460ce81151cSLikun Gao 1461ce81151cSLikun Gao 1462ce81151cSLikun Gao typedef struct { 1463ce81151cSLikun Gao uint8_t Gfx_ActiveHystLimit; 1464ce81151cSLikun Gao uint8_t Gfx_IdleHystLimit; 1465ce81151cSLikun Gao uint8_t Gfx_FPS; 1466ce81151cSLikun Gao uint8_t Gfx_MinActiveFreqType; 1467ce81151cSLikun Gao uint8_t Gfx_BoosterFreqType; 1468ce81151cSLikun Gao uint8_t PaddingGfx; 1469ce81151cSLikun Gao uint16_t Gfx_MinActiveFreq; // MHz 1470ce81151cSLikun Gao uint16_t Gfx_BoosterFreq; // MHz 1471ce81151cSLikun Gao uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms 1472ce81151cSLikun Gao uint32_t Gfx_PD_Data_limit_a; // Q16 1473ce81151cSLikun Gao uint32_t Gfx_PD_Data_limit_b; // Q16 1474ce81151cSLikun Gao uint32_t Gfx_PD_Data_limit_c; // Q16 1475ce81151cSLikun Gao uint32_t Gfx_PD_Data_error_coeff; // Q16 1476ce81151cSLikun Gao uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 1477ce81151cSLikun Gao 1478ce81151cSLikun Gao uint8_t Fclk_ActiveHystLimit; 1479ce81151cSLikun Gao uint8_t Fclk_IdleHystLimit; 1480ce81151cSLikun Gao uint8_t Fclk_FPS; 1481ce81151cSLikun Gao uint8_t Fclk_MinActiveFreqType; 1482ce81151cSLikun Gao uint8_t Fclk_BoosterFreqType; 1483ce81151cSLikun Gao uint8_t PaddingFclk; 1484ce81151cSLikun Gao uint16_t Fclk_MinActiveFreq; // MHz 1485ce81151cSLikun Gao uint16_t Fclk_BoosterFreq; // MHz 1486ce81151cSLikun Gao uint16_t Fclk_PD_Data_time_constant; // Time constant of PD controller in ms 1487ce81151cSLikun Gao uint32_t Fclk_PD_Data_limit_a; // Q16 1488ce81151cSLikun Gao uint32_t Fclk_PD_Data_limit_b; // Q16 1489ce81151cSLikun Gao uint32_t Fclk_PD_Data_limit_c; // Q16 1490ce81151cSLikun Gao uint32_t Fclk_PD_Data_error_coeff; // Q16 1491ce81151cSLikun Gao uint32_t Fclk_PD_Data_error_rate_coeff; // Q16 1492ce81151cSLikun Gao 1493ce81151cSLikun Gao uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16 1494ce81151cSLikun Gao uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS]; 1495ce81151cSLikun Gao uint8_t Mem_DownHystLimit[NUM_UCLK_DPM_LEVELS]; 1496ce81151cSLikun Gao uint16_t Mem_Fps; 1497ce81151cSLikun Gao uint8_t padding[2]; 1498ce81151cSLikun Gao 1499ce81151cSLikun Gao } DpmActivityMonitorCoeffInt_t; 1500ce81151cSLikun Gao 1501ce81151cSLikun Gao 1502ce81151cSLikun Gao typedef struct { 1503ce81151cSLikun Gao DpmActivityMonitorCoeffInt_t DpmActivityMonitorCoeffInt; 1504ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1505ce81151cSLikun Gao } DpmActivityMonitorCoeffIntExternal_t; 1506ce81151cSLikun Gao 1507ce81151cSLikun Gao 1508ce81151cSLikun Gao 1509ce81151cSLikun Gao // Workload bits 1510ce81151cSLikun Gao #define WORKLOAD_PPLIB_DEFAULT_BIT 0 1511ce81151cSLikun Gao #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 1512ce81151cSLikun Gao #define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 1513ce81151cSLikun Gao #define WORKLOAD_PPLIB_VIDEO_BIT 3 1514ce81151cSLikun Gao #define WORKLOAD_PPLIB_VR_BIT 4 1515ce81151cSLikun Gao #define WORKLOAD_PPLIB_COMPUTE_BIT 5 1516ce81151cSLikun Gao #define WORKLOAD_PPLIB_CUSTOM_BIT 6 1517ce81151cSLikun Gao #define WORKLOAD_PPLIB_WINDOW_3D_BIT 7 1518ce81151cSLikun Gao #define WORKLOAD_PPLIB_COUNT 8 1519ce81151cSLikun Gao 1520ce81151cSLikun Gao 1521ce81151cSLikun Gao // These defines are used with the following messages: 1522ce81151cSLikun Gao // SMC_MSG_TransferTableDram2Smu 1523ce81151cSLikun Gao // SMC_MSG_TransferTableSmu2Dram 1524ce81151cSLikun Gao 1525ce81151cSLikun Gao // Table transfer status 1526ce81151cSLikun Gao #define TABLE_TRANSFER_OK 0x0 1527ce81151cSLikun Gao #define TABLE_TRANSFER_FAILED 0xFF 1528ce81151cSLikun Gao #define TABLE_TRANSFER_PENDING 0xAB 1529ce81151cSLikun Gao 1530ce81151cSLikun Gao // Table types 1531ce81151cSLikun Gao #define TABLE_PPTABLE 0 1532ce81151cSLikun Gao #define TABLE_COMBO_PPTABLE 1 1533ce81151cSLikun Gao #define TABLE_WATERMARKS 2 1534ce81151cSLikun Gao #define TABLE_AVFS_PSM_DEBUG 3 1535ce81151cSLikun Gao #define TABLE_PMSTATUSLOG 4 1536ce81151cSLikun Gao #define TABLE_SMU_METRICS 5 1537ce81151cSLikun Gao #define TABLE_DRIVER_SMU_CONFIG 6 1538ce81151cSLikun Gao #define TABLE_ACTIVITY_MONITOR_COEFF 7 1539ce81151cSLikun Gao #define TABLE_OVERDRIVE 8 1540ce81151cSLikun Gao #define TABLE_I2C_COMMANDS 9 1541ce81151cSLikun Gao #define TABLE_DRIVER_INFO 10 1542ce81151cSLikun Gao #define TABLE_ECCINFO 11 1543ce81151cSLikun Gao #define TABLE_COUNT 12 1544ce81151cSLikun Gao 1545ce81151cSLikun Gao //IH Interupt ID 1546ce81151cSLikun Gao #define IH_INTERRUPT_ID_TO_DRIVER 0xFE 1547ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_BACO 0x2 1548ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_AC 0x3 1549ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_DC 0x4 1550ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 0x5 1551ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 0x6 1552ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING 0x7 1553ce81151cSLikun Gao 1554ce81151cSLikun Gao #endif 1555