1ce81151cSLikun Gao /* 2ce81151cSLikun Gao * Copyright 2021 Advanced Micro Devices, Inc. 3ce81151cSLikun Gao * 4ce81151cSLikun Gao * Permission is hereby granted, free of charge, to any person obtaining a 5ce81151cSLikun Gao * copy of this software and associated documentation files (the "Software"), 6ce81151cSLikun Gao * to deal in the Software without restriction, including without limitation 7ce81151cSLikun Gao * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8ce81151cSLikun Gao * and/or sell copies of the Software, and to permit persons to whom the 9ce81151cSLikun Gao * Software is furnished to do so, subject to the following conditions: 10ce81151cSLikun Gao * 11ce81151cSLikun Gao * The above copyright notice and this permission notice shall be included in 12ce81151cSLikun Gao * all copies or substantial portions of the Software. 13ce81151cSLikun Gao * 14ce81151cSLikun Gao * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15ce81151cSLikun Gao * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16ce81151cSLikun Gao * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17ce81151cSLikun Gao * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18ce81151cSLikun Gao * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19ce81151cSLikun Gao * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20ce81151cSLikun Gao * OTHER DEALINGS IN THE SOFTWARE. 21ce81151cSLikun Gao * 22ce81151cSLikun Gao */ 23ce81151cSLikun Gao 24ce81151cSLikun Gao #ifndef SMU13_DRIVER_IF_V13_0_0_H 25ce81151cSLikun Gao #define SMU13_DRIVER_IF_V13_0_0_H 26ce81151cSLikun Gao 27*d522ca27SKenneth Feng #define SMU13_0_0_DRIVER_IF_VERSION 0x3D 289661bf68SLijo Lazar 29ce81151cSLikun Gao //Increment this version if SkuTable_t or BoardTable_t change 30*d522ca27SKenneth Feng #define PPTABLE_VERSION 0x2B 31ce81151cSLikun Gao 32ce81151cSLikun Gao #define NUM_GFXCLK_DPM_LEVELS 16 33ce81151cSLikun Gao #define NUM_SOCCLK_DPM_LEVELS 8 34ce81151cSLikun Gao #define NUM_MP0CLK_DPM_LEVELS 2 35ce81151cSLikun Gao #define NUM_DCLK_DPM_LEVELS 8 36ce81151cSLikun Gao #define NUM_VCLK_DPM_LEVELS 8 37ce81151cSLikun Gao #define NUM_DISPCLK_DPM_LEVELS 8 38ce81151cSLikun Gao #define NUM_DPPCLK_DPM_LEVELS 8 39ce81151cSLikun Gao #define NUM_DPREFCLK_DPM_LEVELS 8 40ce81151cSLikun Gao #define NUM_DCFCLK_DPM_LEVELS 8 41ce81151cSLikun Gao #define NUM_DTBCLK_DPM_LEVELS 8 42ce81151cSLikun Gao #define NUM_UCLK_DPM_LEVELS 4 43ce81151cSLikun Gao #define NUM_LINK_LEVELS 3 44ce81151cSLikun Gao #define NUM_FCLK_DPM_LEVELS 8 45ce81151cSLikun Gao #define NUM_OD_FAN_MAX_POINTS 6 46ce81151cSLikun Gao 47ce81151cSLikun Gao // Feature Control Defines 48ce81151cSLikun Gao #define FEATURE_FW_DATA_READ_BIT 0 49ce81151cSLikun Gao #define FEATURE_DPM_GFXCLK_BIT 1 50ce81151cSLikun Gao #define FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT 2 51ce81151cSLikun Gao #define FEATURE_DPM_UCLK_BIT 3 52ce81151cSLikun Gao #define FEATURE_DPM_FCLK_BIT 4 53ce81151cSLikun Gao #define FEATURE_DPM_SOCCLK_BIT 5 54ce81151cSLikun Gao #define FEATURE_DPM_MP0CLK_BIT 6 55ce81151cSLikun Gao #define FEATURE_DPM_LINK_BIT 7 56ce81151cSLikun Gao #define FEATURE_DPM_DCN_BIT 8 57ce81151cSLikun Gao #define FEATURE_VMEMP_SCALING_BIT 9 58ce81151cSLikun Gao #define FEATURE_VDDIO_MEM_SCALING_BIT 10 59ce81151cSLikun Gao #define FEATURE_DS_GFXCLK_BIT 11 60ce81151cSLikun Gao #define FEATURE_DS_SOCCLK_BIT 12 61ce81151cSLikun Gao #define FEATURE_DS_FCLK_BIT 13 62ce81151cSLikun Gao #define FEATURE_DS_LCLK_BIT 14 63ce81151cSLikun Gao #define FEATURE_DS_DCFCLK_BIT 15 64ce81151cSLikun Gao #define FEATURE_DS_UCLK_BIT 16 65ce81151cSLikun Gao #define FEATURE_GFX_ULV_BIT 17 66ce81151cSLikun Gao #define FEATURE_FW_DSTATE_BIT 18 67ce81151cSLikun Gao #define FEATURE_GFXOFF_BIT 19 68ce81151cSLikun Gao #define FEATURE_BACO_BIT 20 69ce81151cSLikun Gao #define FEATURE_MM_DPM_BIT 21 70ce81151cSLikun Gao #define FEATURE_SOC_MPCLK_DS_BIT 22 71ce81151cSLikun Gao #define FEATURE_BACO_MPCLK_DS_BIT 23 72ce81151cSLikun Gao #define FEATURE_THROTTLERS_BIT 24 73ce81151cSLikun Gao #define FEATURE_SMARTSHIFT_BIT 25 74ce81151cSLikun Gao #define FEATURE_GTHR_BIT 26 75ce81151cSLikun Gao #define FEATURE_ACDC_BIT 27 76ce81151cSLikun Gao #define FEATURE_VR0HOT_BIT 28 77ce81151cSLikun Gao #define FEATURE_FW_CTF_BIT 29 78ce81151cSLikun Gao #define FEATURE_FAN_CONTROL_BIT 30 79ce81151cSLikun Gao #define FEATURE_GFX_DCS_BIT 31 80ce81151cSLikun Gao #define FEATURE_GFX_READ_MARGIN_BIT 32 81ce81151cSLikun Gao #define FEATURE_LED_DISPLAY_BIT 33 82ce81151cSLikun Gao #define FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT 34 83ce81151cSLikun Gao #define FEATURE_OUT_OF_BAND_MONITOR_BIT 35 84ce81151cSLikun Gao #define FEATURE_OPTIMIZED_VMIN_BIT 36 85ce81151cSLikun Gao #define FEATURE_GFX_IMU_BIT 37 86ce81151cSLikun Gao #define FEATURE_BOOT_TIME_CAL_BIT 38 87ce81151cSLikun Gao #define FEATURE_GFX_PCC_DFLL_BIT 39 88ce81151cSLikun Gao #define FEATURE_SOC_CG_BIT 40 89ce81151cSLikun Gao #define FEATURE_DF_CSTATE_BIT 41 90ce81151cSLikun Gao #define FEATURE_GFX_EDC_BIT 42 91ce81151cSLikun Gao #define FEATURE_BOOT_POWER_OPT_BIT 43 92ce81151cSLikun Gao #define FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT 44 93ce81151cSLikun Gao #define FEATURE_DS_VCN_BIT 45 94ce81151cSLikun Gao #define FEATURE_BACO_CG_BIT 46 95ce81151cSLikun Gao #define FEATURE_MEM_TEMP_READ_BIT 47 96ce81151cSLikun Gao #define FEATURE_ATHUB_MMHUB_PG_BIT 48 97ce81151cSLikun Gao #define FEATURE_SOC_PCC_BIT 49 981f3dfde4SEvan Quan #define FEATURE_EDC_PWRBRK_BIT 50 99*d522ca27SKenneth Feng #define FEATURE_BOMXCO_SVI3_PROG_BIT 51 100ce81151cSLikun Gao #define FEATURE_SPARE_52_BIT 52 101ce81151cSLikun Gao #define FEATURE_SPARE_53_BIT 53 102ce81151cSLikun Gao #define FEATURE_SPARE_54_BIT 54 103ce81151cSLikun Gao #define FEATURE_SPARE_55_BIT 55 104ce81151cSLikun Gao #define FEATURE_SPARE_56_BIT 56 105ce81151cSLikun Gao #define FEATURE_SPARE_57_BIT 57 106ce81151cSLikun Gao #define FEATURE_SPARE_58_BIT 58 107ce81151cSLikun Gao #define FEATURE_SPARE_59_BIT 59 108ce81151cSLikun Gao #define FEATURE_SPARE_60_BIT 60 109ce81151cSLikun Gao #define FEATURE_SPARE_61_BIT 61 110ce81151cSLikun Gao #define FEATURE_SPARE_62_BIT 62 111ce81151cSLikun Gao #define FEATURE_SPARE_63_BIT 63 112ce81151cSLikun Gao #define NUM_FEATURES 64 113ce81151cSLikun Gao 1147e5632cdSKenneth Feng #define ALLOWED_FEATURE_CTRL_DEFAULT 0xFFFFFFFFFFFFFFFFULL 1157e5632cdSKenneth Feng #define ALLOWED_FEATURE_CTRL_SCPM ((1 << FEATURE_DPM_GFXCLK_BIT) | \ 1167e5632cdSKenneth Feng (1 << FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | \ 1177e5632cdSKenneth Feng (1 << FEATURE_DPM_UCLK_BIT) | \ 1187e5632cdSKenneth Feng (1 << FEATURE_DPM_FCLK_BIT) | \ 1197e5632cdSKenneth Feng (1 << FEATURE_DPM_SOCCLK_BIT) | \ 1207e5632cdSKenneth Feng (1 << FEATURE_DPM_MP0CLK_BIT) | \ 1217e5632cdSKenneth Feng (1 << FEATURE_DPM_LINK_BIT) | \ 1227e5632cdSKenneth Feng (1 << FEATURE_DPM_DCN_BIT) | \ 1237e5632cdSKenneth Feng (1 << FEATURE_DS_GFXCLK_BIT) | \ 1247e5632cdSKenneth Feng (1 << FEATURE_DS_SOCCLK_BIT) | \ 1257e5632cdSKenneth Feng (1 << FEATURE_DS_FCLK_BIT) | \ 1267e5632cdSKenneth Feng (1 << FEATURE_DS_LCLK_BIT) | \ 1277e5632cdSKenneth Feng (1 << FEATURE_DS_DCFCLK_BIT) | \ 1282bce0f9bSEvan Quan (1 << FEATURE_DS_UCLK_BIT) | \ 1292bce0f9bSEvan Quan (1ULL << FEATURE_DS_VCN_BIT)) 1307e5632cdSKenneth Feng 131ce81151cSLikun Gao //For use with feature control messages 132ce81151cSLikun Gao typedef enum { 133ce81151cSLikun Gao FEATURE_PWR_ALL, 134ce81151cSLikun Gao FEATURE_PWR_S5, 135ce81151cSLikun Gao FEATURE_PWR_BACO, 136ce81151cSLikun Gao FEATURE_PWR_SOC, 137ce81151cSLikun Gao FEATURE_PWR_GFX, 138ce81151cSLikun Gao FEATURE_PWR_DOMAIN_COUNT, 139ce81151cSLikun Gao } FEATURE_PWR_DOMAIN_e; 140ce81151cSLikun Gao 141ce81151cSLikun Gao 142ce81151cSLikun Gao // Debug Overrides Bitmask 143ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000001 144ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK 0x00000002 145ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK 0x00000004 146ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK 0x00000008 147ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x00000010 148ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_VCN_PG 0x00000020 149ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_FMAX_VMAX 0x00000040 150ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS 0x00000080 151ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK 0x00000100 152ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_DFLL 0x00000200 153ce81151cSLikun Gao #define DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE 0x00000400 154ce81151cSLikun Gao #define DEBUG_OVERRIDE_DFLL_MASTER_MODE 0x00000800 1557e5632cdSKenneth Feng #define DEBUG_OVERRIDE_ENABLE_PROFILING_MODE 0x00001000 156ce81151cSLikun Gao 157ce81151cSLikun Gao // VR Mapping Bit Defines 158ce81151cSLikun Gao #define VR_MAPPING_VR_SELECT_MASK 0x01 159ce81151cSLikun Gao #define VR_MAPPING_VR_SELECT_SHIFT 0x00 160ce81151cSLikun Gao 161ce81151cSLikun Gao #define VR_MAPPING_PLANE_SELECT_MASK 0x02 162ce81151cSLikun Gao #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 163ce81151cSLikun Gao 164ce81151cSLikun Gao // PSI Bit Defines 165ce81151cSLikun Gao #define PSI_SEL_VR0_PLANE0_PSI0 0x01 166ce81151cSLikun Gao #define PSI_SEL_VR0_PLANE0_PSI1 0x02 167ce81151cSLikun Gao #define PSI_SEL_VR0_PLANE1_PSI0 0x04 168ce81151cSLikun Gao #define PSI_SEL_VR0_PLANE1_PSI1 0x08 169ce81151cSLikun Gao #define PSI_SEL_VR1_PLANE0_PSI0 0x10 170ce81151cSLikun Gao #define PSI_SEL_VR1_PLANE0_PSI1 0x20 171ce81151cSLikun Gao #define PSI_SEL_VR1_PLANE1_PSI0 0x40 172ce81151cSLikun Gao #define PSI_SEL_VR1_PLANE1_PSI1 0x80 173ce81151cSLikun Gao 174ce81151cSLikun Gao typedef enum { 175ce81151cSLikun Gao SVI_PSI_0, // Full phase count (default) 176ce81151cSLikun Gao SVI_PSI_1, // Phase count 1st level 177ce81151cSLikun Gao SVI_PSI_2, // Phase count 2nd level 178ce81151cSLikun Gao SVI_PSI_3, // Single phase operation + active diode emulation 179ce81151cSLikun Gao SVI_PSI_4, // Single phase operation + passive diode emulation *optional* 180ce81151cSLikun Gao SVI_PSI_5, // Reserved 181ce81151cSLikun Gao SVI_PSI_6, // Power down to 0V (voltage regulation disabled) 182ce81151cSLikun Gao SVI_PSI_7, // Automated phase shedding and diode emulation 183ce81151cSLikun Gao } SVI_PSI_e; 184ce81151cSLikun Gao 185ce81151cSLikun Gao // Throttler Control/Status Bits 186ce81151cSLikun Gao #define THROTTLER_TEMP_EDGE_BIT 0 187ce81151cSLikun Gao #define THROTTLER_TEMP_HOTSPOT_BIT 1 188ce81151cSLikun Gao #define THROTTLER_TEMP_HOTSPOT_G_BIT 2 189ce81151cSLikun Gao #define THROTTLER_TEMP_HOTSPOT_M_BIT 3 190ce81151cSLikun Gao #define THROTTLER_TEMP_MEM_BIT 4 191ce81151cSLikun Gao #define THROTTLER_TEMP_VR_GFX_BIT 5 192ce81151cSLikun Gao #define THROTTLER_TEMP_VR_MEM0_BIT 6 193ce81151cSLikun Gao #define THROTTLER_TEMP_VR_MEM1_BIT 7 194ce81151cSLikun Gao #define THROTTLER_TEMP_VR_SOC_BIT 8 195ce81151cSLikun Gao #define THROTTLER_TEMP_VR_U_BIT 9 196ce81151cSLikun Gao #define THROTTLER_TEMP_LIQUID0_BIT 10 197ce81151cSLikun Gao #define THROTTLER_TEMP_LIQUID1_BIT 11 198ce81151cSLikun Gao #define THROTTLER_TEMP_PLX_BIT 12 199ce81151cSLikun Gao #define THROTTLER_TDC_GFX_BIT 13 200ce81151cSLikun Gao #define THROTTLER_TDC_SOC_BIT 14 201ce81151cSLikun Gao #define THROTTLER_TDC_U_BIT 15 202ce81151cSLikun Gao #define THROTTLER_PPT0_BIT 16 203ce81151cSLikun Gao #define THROTTLER_PPT1_BIT 17 204ce81151cSLikun Gao #define THROTTLER_PPT2_BIT 18 205ce81151cSLikun Gao #define THROTTLER_PPT3_BIT 19 206ce81151cSLikun Gao #define THROTTLER_FIT_BIT 20 207ce81151cSLikun Gao #define THROTTLER_GFX_APCC_PLUS_BIT 21 208ce81151cSLikun Gao #define THROTTLER_COUNT 22 209ce81151cSLikun Gao 210ce81151cSLikun Gao // FW DState Features Control Bits 211ce81151cSLikun Gao #define FW_DSTATE_SOC_ULV_BIT 0 212ce81151cSLikun Gao #define FW_DSTATE_G6_HSR_BIT 1 213ce81151cSLikun Gao #define FW_DSTATE_G6_PHY_VMEMP_OFF_BIT 2 214ce81151cSLikun Gao #define FW_DSTATE_SMN_DS_BIT 3 215ce81151cSLikun Gao #define FW_DSTATE_MP1_WHISPER_MODE_BIT 4 216ce81151cSLikun Gao #define FW_DSTATE_SOC_LIV_MIN_BIT 5 217ce81151cSLikun Gao #define FW_DSTATE_SOC_PLL_PWRDN_BIT 6 218ce81151cSLikun Gao #define FW_DSTATE_MEM_PLL_PWRDN_BIT 7 219ce81151cSLikun Gao #define FW_DSTATE_MALL_ALLOC_BIT 8 220ce81151cSLikun Gao #define FW_DSTATE_MEM_PSI_BIT 9 221ce81151cSLikun Gao #define FW_DSTATE_HSR_NON_STROBE_BIT 10 222ce81151cSLikun Gao #define FW_DSTATE_MP0_ENTER_WFI_BIT 11 223ce81151cSLikun Gao #define FW_DSTATE_U_ULV_BIT 12 224ce81151cSLikun Gao #define FW_DSTATE_MALL_FLUSH_BIT 13 225ce81151cSLikun Gao #define FW_DSTATE_SOC_PSI_BIT 14 226ce81151cSLikun Gao #define FW_DSTATE_U_PSI_BIT 15 227ce81151cSLikun Gao #define FW_DSTATE_UCP_DS_BIT 16 228ce81151cSLikun Gao #define FW_DSTATE_CSRCLK_DS_BIT 17 229ce81151cSLikun Gao #define FW_DSTATE_MMHUB_INTERLOCK_BIT 18 230ce81151cSLikun Gao #define FW_DSTATE_D0i3_2_QUIET_FW_BIT 19 231ce81151cSLikun Gao #define FW_DSTATE_CLDO_PRG_BIT 20 232ce81151cSLikun Gao #define FW_DSTATE_DF_PLL_PWRDN_BIT 21 233ce81151cSLikun Gao #define FW_DSTATE_U_LOW_PWR_MODE_EN_BIT 22 234ce81151cSLikun Gao #define FW_DSTATE_GFX_PSI6_BIT 23 235ce81151cSLikun Gao #define FW_DSTATE_GFX_VR_PWR_STAGE_BIT 24 236ce81151cSLikun Gao 237ce81151cSLikun Gao //LED Display Mask & Control Bits 238ce81151cSLikun Gao #define LED_DISPLAY_GFX_DPM_BIT 0 239ce81151cSLikun Gao #define LED_DISPLAY_PCIE_BIT 1 240ce81151cSLikun Gao #define LED_DISPLAY_ERROR_BIT 2 241ce81151cSLikun Gao 242ce81151cSLikun Gao 243ce81151cSLikun Gao #define MEM_TEMP_READ_OUT_OF_BAND_BIT 0 244ce81151cSLikun Gao #define MEM_TEMP_READ_IN_BAND_REFRESH_BIT 1 245ce81151cSLikun Gao #define MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT 2 246ce81151cSLikun Gao 247ce81151cSLikun Gao typedef enum { 248ce81151cSLikun Gao SMARTSHIFT_VERSION_1, 249ce81151cSLikun Gao SMARTSHIFT_VERSION_2, 250ce81151cSLikun Gao SMARTSHIFT_VERSION_3, 251ce81151cSLikun Gao } SMARTSHIFT_VERSION_e; 252ce81151cSLikun Gao 253ce81151cSLikun Gao typedef enum { 254ce81151cSLikun Gao FOPT_CALC_AC_CALC_DC, 255ce81151cSLikun Gao FOPT_PPTABLE_AC_CALC_DC, 256ce81151cSLikun Gao FOPT_CALC_AC_PPTABLE_DC, 257ce81151cSLikun Gao FOPT_PPTABLE_AC_PPTABLE_DC, 258ce81151cSLikun Gao } FOPT_CALC_e; 259ce81151cSLikun Gao 260ce81151cSLikun Gao typedef enum { 261ce81151cSLikun Gao DRAM_BIT_WIDTH_DISABLED = 0, 262ce81151cSLikun Gao DRAM_BIT_WIDTH_X_8 = 8, 263ce81151cSLikun Gao DRAM_BIT_WIDTH_X_16 = 16, 264ce81151cSLikun Gao DRAM_BIT_WIDTH_X_32 = 32, 265ce81151cSLikun Gao DRAM_BIT_WIDTH_X_64 = 64, 266ce81151cSLikun Gao DRAM_BIT_WIDTH_X_128 = 128, 267ce81151cSLikun Gao DRAM_BIT_WIDTH_COUNT, 268ce81151cSLikun Gao } DRAM_BIT_WIDTH_TYPE_e; 269ce81151cSLikun Gao 270ce81151cSLikun Gao //I2C Interface 271ce81151cSLikun Gao #define NUM_I2C_CONTROLLERS 8 272ce81151cSLikun Gao 273ce81151cSLikun Gao #define I2C_CONTROLLER_ENABLED 1 274ce81151cSLikun Gao #define I2C_CONTROLLER_DISABLED 0 275ce81151cSLikun Gao 276ce81151cSLikun Gao #define MAX_SW_I2C_COMMANDS 24 277ce81151cSLikun Gao 278ce81151cSLikun Gao typedef enum { 279ce81151cSLikun Gao I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0 280ce81151cSLikun Gao I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1 281ce81151cSLikun Gao I2C_CONTROLLER_PORT_COUNT, 282ce81151cSLikun Gao } I2cControllerPort_e; 283ce81151cSLikun Gao 284ce81151cSLikun Gao typedef enum { 285ce81151cSLikun Gao I2C_CONTROLLER_NAME_VR_GFX = 0, 286ce81151cSLikun Gao I2C_CONTROLLER_NAME_VR_SOC, 287ce81151cSLikun Gao I2C_CONTROLLER_NAME_VR_VMEMP, 288ce81151cSLikun Gao I2C_CONTROLLER_NAME_VR_VDDIO, 289ce81151cSLikun Gao I2C_CONTROLLER_NAME_LIQUID0, 290ce81151cSLikun Gao I2C_CONTROLLER_NAME_LIQUID1, 291ce81151cSLikun Gao I2C_CONTROLLER_NAME_PLX, 2927e5632cdSKenneth Feng I2C_CONTROLLER_NAME_FAN_INTAKE, 293ce81151cSLikun Gao I2C_CONTROLLER_NAME_COUNT, 294ce81151cSLikun Gao } I2cControllerName_e; 295ce81151cSLikun Gao 296ce81151cSLikun Gao typedef enum { 297ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 298ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_VR_GFX, 299ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_VR_SOC, 300ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_VR_VMEMP, 301ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_VR_VDDIO, 302ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_LIQUID0, 303ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_LIQUID1, 304ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_PLX, 3057e5632cdSKenneth Feng I2C_CONTROLLER_THROTTLER_FAN_INTAKE, 306ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_INA3221, 307ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_COUNT, 308ce81151cSLikun Gao } I2cControllerThrottler_e; 309ce81151cSLikun Gao 310ce81151cSLikun Gao typedef enum { 311ce81151cSLikun Gao I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5, 312ce81151cSLikun Gao I2C_CONTROLLER_PROTOCOL_VR_IR35217, 3137e5632cdSKenneth Feng I2C_CONTROLLER_PROTOCOL_TMP_MAX31875, 314ce81151cSLikun Gao I2C_CONTROLLER_PROTOCOL_INA3221, 315*d522ca27SKenneth Feng I2C_CONTROLLER_PROTOCOL_TMP_MAX6604, 316ce81151cSLikun Gao I2C_CONTROLLER_PROTOCOL_COUNT, 317ce81151cSLikun Gao } I2cControllerProtocol_e; 318ce81151cSLikun Gao 319ce81151cSLikun Gao typedef struct { 320ce81151cSLikun Gao uint8_t Enabled; 321ce81151cSLikun Gao uint8_t Speed; 322ce81151cSLikun Gao uint8_t SlaveAddress; 323ce81151cSLikun Gao uint8_t ControllerPort; 324ce81151cSLikun Gao uint8_t ControllerName; 325ce81151cSLikun Gao uint8_t ThermalThrotter; 326ce81151cSLikun Gao uint8_t I2cProtocol; 327ce81151cSLikun Gao uint8_t PaddingConfig; 328ce81151cSLikun Gao } I2cControllerConfig_t; 329ce81151cSLikun Gao 330ce81151cSLikun Gao typedef enum { 331ce81151cSLikun Gao I2C_PORT_SVD_SCL = 0, 332ce81151cSLikun Gao I2C_PORT_GPIO, 333ce81151cSLikun Gao } I2cPort_e; 334ce81151cSLikun Gao 335ce81151cSLikun Gao typedef enum { 336ce81151cSLikun Gao I2C_SPEED_FAST_50K = 0, //50 Kbits/s 337ce81151cSLikun Gao I2C_SPEED_FAST_100K, //100 Kbits/s 338ce81151cSLikun Gao I2C_SPEED_FAST_400K, //400 Kbits/s 339ce81151cSLikun Gao I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 340ce81151cSLikun Gao I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 341ce81151cSLikun Gao I2C_SPEED_HIGH_2M, //2.3 Mbits/s 342ce81151cSLikun Gao I2C_SPEED_COUNT, 343ce81151cSLikun Gao } I2cSpeed_e; 344ce81151cSLikun Gao 345ce81151cSLikun Gao typedef enum { 346ce81151cSLikun Gao I2C_CMD_READ = 0, 347ce81151cSLikun Gao I2C_CMD_WRITE, 348ce81151cSLikun Gao I2C_CMD_COUNT, 349ce81151cSLikun Gao } I2cCmdType_e; 350ce81151cSLikun Gao 351ce81151cSLikun Gao #define CMDCONFIG_STOP_BIT 0 352ce81151cSLikun Gao #define CMDCONFIG_RESTART_BIT 1 353ce81151cSLikun Gao #define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write 354ce81151cSLikun Gao 355ce81151cSLikun Gao #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 356ce81151cSLikun Gao #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 357ce81151cSLikun Gao #define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT) 358ce81151cSLikun Gao 359ce81151cSLikun Gao typedef struct { 360ce81151cSLikun Gao uint8_t ReadWriteData; //Return data for read. Data to send for write 361ce81151cSLikun Gao uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write 362ce81151cSLikun Gao } SwI2cCmd_t; //SW I2C Command Table 363ce81151cSLikun Gao 364ce81151cSLikun Gao typedef struct { 365ce81151cSLikun Gao uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 366ce81151cSLikun Gao uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select 367ce81151cSLikun Gao uint8_t SlaveAddress; //Slave address of device 368ce81151cSLikun Gao uint8_t NumCmds; //Number of commands 369ce81151cSLikun Gao 370ce81151cSLikun Gao SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 371ce81151cSLikun Gao } SwI2cRequest_t; // SW I2C Request Table 372ce81151cSLikun Gao 373ce81151cSLikun Gao typedef struct { 374ce81151cSLikun Gao SwI2cRequest_t SwI2cRequest; 375ce81151cSLikun Gao 376ce81151cSLikun Gao uint32_t Spare[8]; 377ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 378ce81151cSLikun Gao } SwI2cRequestExternal_t; 379ce81151cSLikun Gao 380ce81151cSLikun Gao typedef struct { 381ce81151cSLikun Gao uint64_t mca_umc_status; 382ce81151cSLikun Gao uint64_t mca_umc_addr; 383ce81151cSLikun Gao 384ce81151cSLikun Gao uint16_t ce_count_lo_chip; 385ce81151cSLikun Gao uint16_t ce_count_hi_chip; 386ce81151cSLikun Gao 387ce81151cSLikun Gao uint32_t eccPadding; 388ce81151cSLikun Gao } EccInfo_t; 389ce81151cSLikun Gao 390ce81151cSLikun Gao typedef struct { 391ce81151cSLikun Gao EccInfo_t EccInfo[24]; 392ce81151cSLikun Gao } EccInfoTable_t; 393ce81151cSLikun Gao 394ce81151cSLikun Gao //D3HOT sequences 395ce81151cSLikun Gao typedef enum { 396ce81151cSLikun Gao BACO_SEQUENCE, 397ce81151cSLikun Gao MSR_SEQUENCE, 398ce81151cSLikun Gao BAMACO_SEQUENCE, 399ce81151cSLikun Gao ULPS_SEQUENCE, 400ce81151cSLikun Gao D3HOT_SEQUENCE_COUNT, 401ce81151cSLikun Gao } D3HOTSequence_e; 402ce81151cSLikun Gao 403ce81151cSLikun Gao //This is aligned with RSMU PGFSM Register Mapping 404ce81151cSLikun Gao typedef enum { 405ce81151cSLikun Gao PG_DYNAMIC_MODE = 0, 406ce81151cSLikun Gao PG_STATIC_MODE, 407ce81151cSLikun Gao } PowerGatingMode_e; 408ce81151cSLikun Gao 409ce81151cSLikun Gao //This is aligned with RSMU PGFSM Register Mapping 410ce81151cSLikun Gao typedef enum { 411ce81151cSLikun Gao PG_POWER_DOWN = 0, 412ce81151cSLikun Gao PG_POWER_UP, 413ce81151cSLikun Gao } PowerGatingSettings_e; 414ce81151cSLikun Gao 415ce81151cSLikun Gao typedef struct { 416ce81151cSLikun Gao uint32_t a; // store in IEEE float format in this variable 417ce81151cSLikun Gao uint32_t b; // store in IEEE float format in this variable 418ce81151cSLikun Gao uint32_t c; // store in IEEE float format in this variable 419ce81151cSLikun Gao } QuadraticInt_t; 420ce81151cSLikun Gao 421ce81151cSLikun Gao typedef struct { 422ce81151cSLikun Gao uint32_t m; // store in IEEE float format in this variable 423ce81151cSLikun Gao uint32_t b; // store in IEEE float format in this variable 424ce81151cSLikun Gao } LinearInt_t; 425ce81151cSLikun Gao 426ce81151cSLikun Gao typedef struct { 427ce81151cSLikun Gao uint32_t a; // store in IEEE float format in this variable 428ce81151cSLikun Gao uint32_t b; // store in IEEE float format in this variable 429ce81151cSLikun Gao uint32_t c; // store in IEEE float format in this variable 430ce81151cSLikun Gao } DroopInt_t; 431ce81151cSLikun Gao 432ce81151cSLikun Gao typedef enum { 433ce81151cSLikun Gao DCS_ARCH_DISABLED, 434ce81151cSLikun Gao DCS_ARCH_FADCS, 435ce81151cSLikun Gao DCS_ARCH_ASYNC, 436ce81151cSLikun Gao } DCS_ARCH_e; 437ce81151cSLikun Gao 438ce81151cSLikun Gao //Only Clks that have DPM descriptors are listed here 439ce81151cSLikun Gao typedef enum { 440ce81151cSLikun Gao PPCLK_GFXCLK = 0, 441ce81151cSLikun Gao PPCLK_SOCCLK, 442ce81151cSLikun Gao PPCLK_UCLK, 443ce81151cSLikun Gao PPCLK_FCLK, 444ce81151cSLikun Gao PPCLK_DCLK_0, 445ce81151cSLikun Gao PPCLK_VCLK_0, 446ce81151cSLikun Gao PPCLK_DCLK_1, 447ce81151cSLikun Gao PPCLK_VCLK_1, 448ce81151cSLikun Gao PPCLK_DISPCLK, 449ce81151cSLikun Gao PPCLK_DPPCLK, 450ce81151cSLikun Gao PPCLK_DPREFCLK, 451ce81151cSLikun Gao PPCLK_DCFCLK, 452ce81151cSLikun Gao PPCLK_DTBCLK, 453ce81151cSLikun Gao PPCLK_COUNT, 454ce81151cSLikun Gao } PPCLK_e; 455ce81151cSLikun Gao 456ce81151cSLikun Gao typedef enum { 457ce81151cSLikun Gao VOLTAGE_MODE_PPTABLE = 0, 458ce81151cSLikun Gao VOLTAGE_MODE_FUSES, 459ce81151cSLikun Gao VOLTAGE_MODE_COUNT, 460ce81151cSLikun Gao } VOLTAGE_MODE_e; 461ce81151cSLikun Gao 462ce81151cSLikun Gao 463ce81151cSLikun Gao typedef enum { 464ce81151cSLikun Gao AVFS_VOLTAGE_GFX = 0, 465ce81151cSLikun Gao AVFS_VOLTAGE_SOC, 466ce81151cSLikun Gao AVFS_VOLTAGE_COUNT, 467ce81151cSLikun Gao } AVFS_VOLTAGE_TYPE_e; 468ce81151cSLikun Gao 469ce81151cSLikun Gao typedef enum { 470ce81151cSLikun Gao AVFS_TEMP_COLD = 0, 471ce81151cSLikun Gao AVFS_TEMP_HOT, 472ce81151cSLikun Gao AVFS_TEMP_COUNT, 473ce81151cSLikun Gao } AVFS_TEMP_e; 474ce81151cSLikun Gao 475ce81151cSLikun Gao typedef enum { 476ce81151cSLikun Gao AVFS_D_G, 477ce81151cSLikun Gao AVFS_D_M_B, 478ce81151cSLikun Gao AVFS_D_M_S, 479ce81151cSLikun Gao AVFS_D_COUNT, 480ce81151cSLikun Gao } AVFS_D_e; 481ce81151cSLikun Gao 482ce81151cSLikun Gao typedef enum { 483ce81151cSLikun Gao UCLK_DIV_BY_1 = 0, 484ce81151cSLikun Gao UCLK_DIV_BY_2, 485ce81151cSLikun Gao UCLK_DIV_BY_4, 486ce81151cSLikun Gao UCLK_DIV_BY_8, 487ce81151cSLikun Gao } UCLK_DIV_e; 488ce81151cSLikun Gao 489ce81151cSLikun Gao typedef enum { 490ce81151cSLikun Gao GPIO_INT_POLARITY_ACTIVE_LOW = 0, 491ce81151cSLikun Gao GPIO_INT_POLARITY_ACTIVE_HIGH, 492ce81151cSLikun Gao } GpioIntPolarity_e; 493ce81151cSLikun Gao 494ce81151cSLikun Gao typedef enum { 495ce81151cSLikun Gao PWR_CONFIG_TDP = 0, 496ce81151cSLikun Gao PWR_CONFIG_TGP, 497ce81151cSLikun Gao PWR_CONFIG_TCP_ESTIMATED, 498ce81151cSLikun Gao PWR_CONFIG_TCP_MEASURED, 499ce81151cSLikun Gao } PwrConfig_e; 500ce81151cSLikun Gao 501ce81151cSLikun Gao typedef struct { 502ce81151cSLikun Gao uint8_t Padding; 503ce81151cSLikun Gao uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 504ce81151cSLikun Gao uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 505ce81151cSLikun Gao uint8_t CalculateFopt; // Indication whether FW should calculate Fopt or use values below. Reference FOPT_CALC_e 506ce81151cSLikun Gao LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 507ce81151cSLikun Gao uint32_t Padding3[3]; 508ce81151cSLikun Gao uint16_t Padding4; 509ce81151cSLikun Gao uint16_t FoptimalDc; //Foptimal frequency in DC power mode. 510ce81151cSLikun Gao uint16_t FoptimalAc; //Foptimal frequency in AC power mode. 511ce81151cSLikun Gao uint16_t Padding2; 512ce81151cSLikun Gao } DpmDescriptor_t; 513ce81151cSLikun Gao 514ce81151cSLikun Gao typedef enum { 515ce81151cSLikun Gao PPT_THROTTLER_PPT0, 516ce81151cSLikun Gao PPT_THROTTLER_PPT1, 517ce81151cSLikun Gao PPT_THROTTLER_PPT2, 518ce81151cSLikun Gao PPT_THROTTLER_PPT3, 519ce81151cSLikun Gao PPT_THROTTLER_COUNT 520ce81151cSLikun Gao } PPT_THROTTLER_e; 521ce81151cSLikun Gao 522ce81151cSLikun Gao typedef enum { 523ce81151cSLikun Gao TEMP_EDGE, 524ce81151cSLikun Gao TEMP_HOTSPOT, 525ce81151cSLikun Gao TEMP_HOTSPOT_G, 526ce81151cSLikun Gao TEMP_HOTSPOT_M, 527ce81151cSLikun Gao TEMP_MEM, 528ce81151cSLikun Gao TEMP_VR_GFX, 529ce81151cSLikun Gao TEMP_VR_MEM0, 530ce81151cSLikun Gao TEMP_VR_MEM1, 5312bce0f9bSEvan Quan TEMP_VR_SOC, 532ce81151cSLikun Gao TEMP_VR_U, 533ce81151cSLikun Gao TEMP_LIQUID0, 534ce81151cSLikun Gao TEMP_LIQUID1, 535ce81151cSLikun Gao TEMP_PLX, 536ce81151cSLikun Gao TEMP_COUNT, 537ce81151cSLikun Gao } TEMP_e; 538ce81151cSLikun Gao 539ce81151cSLikun Gao typedef enum { 540ce81151cSLikun Gao TDC_THROTTLER_GFX, 541ce81151cSLikun Gao TDC_THROTTLER_SOC, 542ce81151cSLikun Gao TDC_THROTTLER_U, 543ce81151cSLikun Gao TDC_THROTTLER_COUNT 544ce81151cSLikun Gao } TDC_THROTTLER_e; 545ce81151cSLikun Gao 546ce81151cSLikun Gao typedef enum { 547ce81151cSLikun Gao SVI_PLANE_GFX, 548ce81151cSLikun Gao SVI_PLANE_SOC, 549ce81151cSLikun Gao SVI_PLANE_VMEMP, 550ce81151cSLikun Gao SVI_PLANE_VDDIO_MEM, 551ce81151cSLikun Gao SVI_PLANE_U, 552ce81151cSLikun Gao SVI_PLANE_COUNT, 553ce81151cSLikun Gao } SVI_PLANE_e; 554ce81151cSLikun Gao 555ce81151cSLikun Gao typedef enum { 556ce81151cSLikun Gao PMFW_VOLT_PLANE_GFX, 557ce81151cSLikun Gao PMFW_VOLT_PLANE_SOC, 558ce81151cSLikun Gao PMFW_VOLT_PLANE_COUNT 559ce81151cSLikun Gao } PMFW_VOLT_PLANE_e; 560ce81151cSLikun Gao 561ce81151cSLikun Gao typedef enum { 562ce81151cSLikun Gao CUSTOMER_VARIANT_ROW, 563ce81151cSLikun Gao CUSTOMER_VARIANT_FALCON, 564ce81151cSLikun Gao CUSTOMER_VARIANT_COUNT, 565ce81151cSLikun Gao } CUSTOMER_VARIANT_e; 566ce81151cSLikun Gao 567ce81151cSLikun Gao typedef enum { 568ce81151cSLikun Gao POWER_SOURCE_AC, 569ce81151cSLikun Gao POWER_SOURCE_DC, 570ce81151cSLikun Gao POWER_SOURCE_COUNT, 571ce81151cSLikun Gao } POWER_SOURCE_e; 572ce81151cSLikun Gao 573ce81151cSLikun Gao typedef enum { 574*d522ca27SKenneth Feng MEM_VENDOR_PLACEHOLDER0, 575ce81151cSLikun Gao MEM_VENDOR_SAMSUNG, 576ce81151cSLikun Gao MEM_VENDOR_INFINEON, 577ce81151cSLikun Gao MEM_VENDOR_ELPIDA, 578ce81151cSLikun Gao MEM_VENDOR_ETRON, 579ce81151cSLikun Gao MEM_VENDOR_NANYA, 580ce81151cSLikun Gao MEM_VENDOR_HYNIX, 581ce81151cSLikun Gao MEM_VENDOR_MOSEL, 582ce81151cSLikun Gao MEM_VENDOR_WINBOND, 583ce81151cSLikun Gao MEM_VENDOR_ESMT, 584ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER1, 585ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER2, 586ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER3, 587ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER4, 588ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER5, 589ce81151cSLikun Gao MEM_VENDOR_MICRON, 590ce81151cSLikun Gao MEM_VENDOR_COUNT, 591ce81151cSLikun Gao } MEM_VENDOR_e; 592ce81151cSLikun Gao 593ce81151cSLikun Gao typedef enum { 594ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_CTL_ZONE0, 595ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_CTL_ZONE1, 596ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_CTL_ZONE2, 597ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_CTL_ZONE3, 598ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_CTL_ZONE4, 599ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0, 600ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0, 601ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1, 602ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1, 603ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2, 604ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2, 605ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3, 606ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3, 607ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4, 608ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4, 609ce81151cSLikun Gao PP_GRTAVFS_HW_ZONE0_VF, 610ce81151cSLikun Gao PP_GRTAVFS_HW_ZONE1_VF1, 611ce81151cSLikun Gao PP_GRTAVFS_HW_ZONE2_VF2, 612ce81151cSLikun Gao PP_GRTAVFS_HW_ZONE3_VF3, 613ce81151cSLikun Gao PP_GRTAVFS_HW_VOLTAGE_GB, 614ce81151cSLikun Gao PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0, 615ce81151cSLikun Gao PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1, 616ce81151cSLikun Gao PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2, 617ce81151cSLikun Gao PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3, 618ce81151cSLikun Gao PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4, 619ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_0, 620ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_1, 621ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_2, 622ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_3, 623ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_4, 624ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_5, 625ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_6, 626ce81151cSLikun Gao PP_GRTAVFS_HW_FUSE_COUNT, 627ce81151cSLikun Gao } PP_GRTAVFS_HW_FUSE_e; 628ce81151cSLikun Gao 629ce81151cSLikun Gao typedef enum { 630ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0, 631ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0, 632ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0, 633ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0, 634ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0, 635ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0, 636ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0, 637ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0, 638ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0, 639ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1, 640ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2, 641ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3, 642ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4, 643ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_FUSE_COUNT, 644ce81151cSLikun Gao } PP_GRTAVFS_FW_COMMON_FUSE_e; 645ce81151cSLikun Gao 646ce81151cSLikun Gao typedef enum { 647ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1, 648ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0, 649ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1, 650ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2, 651ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3, 652ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4, 653ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1, 654ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0, 655ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1, 656ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2, 657ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3, 658ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4, 659ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY, 660ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY, 661ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0, 662ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1, 663ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2, 664ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3, 665ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4, 666ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_COUNT, 667ce81151cSLikun Gao } PP_GRTAVFS_FW_SEP_FUSE_e; 668ce81151cSLikun Gao 669ce81151cSLikun Gao #define PP_NUM_RTAVFS_PWL_ZONES 5 670ce81151cSLikun Gao 671a37d23f8SEvan Quan #define PP_OD_FEATURE_GFX_VF_CURVE_BIT 0 672a37d23f8SEvan Quan #define PP_OD_FEATURE_PPT_BIT 2 673a37d23f8SEvan Quan #define PP_OD_FEATURE_FAN_CURVE_BIT 3 674a37d23f8SEvan Quan #define PP_OD_FEATURE_GFXCLK_BIT 7 675a37d23f8SEvan Quan #define PP_OD_FEATURE_UCLK_BIT 8 676a37d23f8SEvan Quan #define PP_OD_FEATURE_ZERO_FAN_BIT 9 677a37d23f8SEvan Quan #define PP_OD_FEATURE_TEMPERATURE_BIT 10 678a37d23f8SEvan Quan #define PP_OD_FEATURE_COUNT 13 679ce81151cSLikun Gao 680ce81151cSLikun Gao // VBIOS or PPLIB configures telemetry slope and offset. Only slope expected to be set for SVI3 681ce81151cSLikun Gao // Slope Q1.7, Offset Q1.2 682ce81151cSLikun Gao typedef struct { 683ce81151cSLikun Gao int8_t Offset; // in Amps 684ce81151cSLikun Gao uint8_t Padding; 685ce81151cSLikun Gao uint16_t MaxCurrent; // in Amps 686ce81151cSLikun Gao } SviTelemetryScale_t; 687ce81151cSLikun Gao 688ce81151cSLikun Gao #define PP_NUM_OD_VF_CURVE_POINTS PP_NUM_RTAVFS_PWL_ZONES + 1 689ce81151cSLikun Gao 6907e5632cdSKenneth Feng typedef enum { 6917e5632cdSKenneth Feng FAN_MODE_AUTO = 0, 6927e5632cdSKenneth Feng FAN_MODE_MANUAL_LINEAR, 6937e5632cdSKenneth Feng } FanMode_e; 694ce81151cSLikun Gao 695ce81151cSLikun Gao typedef struct { 696ce81151cSLikun Gao uint32_t FeatureCtrlMask; 697ce81151cSLikun Gao 698ce81151cSLikun Gao //Voltage control 699ce81151cSLikun Gao int16_t VoltageOffsetPerZoneBoundary[PP_NUM_OD_VF_CURVE_POINTS]; 7007e5632cdSKenneth Feng 701a37d23f8SEvan Quan uint32_t Reserved; 702ce81151cSLikun Gao 703ce81151cSLikun Gao //Frequency changes 7041c65e548SEvan Quan int16_t GfxclkFmin; // MHz 7051c65e548SEvan Quan int16_t GfxclkFmax; // MHz 706ce81151cSLikun Gao uint16_t UclkFmin; // MHz 707ce81151cSLikun Gao uint16_t UclkFmax; // MHz 708ce81151cSLikun Gao 709ce81151cSLikun Gao //PPT 710ce81151cSLikun Gao int16_t Ppt; // % 7117e5632cdSKenneth Feng int16_t Tdc; 712ce81151cSLikun Gao 713ce81151cSLikun Gao //Fan control 714ce81151cSLikun Gao uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS]; 715ce81151cSLikun Gao uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS]; 716ce81151cSLikun Gao uint16_t FanMinimumPwm; 7171c65e548SEvan Quan uint16_t AcousticTargetRpmThreshold; 7181c65e548SEvan Quan uint16_t AcousticLimitRpmThreshold; 719ce81151cSLikun Gao uint16_t FanTargetTemperature; // Degree Celcius 720ce81151cSLikun Gao uint8_t FanZeroRpmEnable; 721ce81151cSLikun Gao uint8_t FanZeroRpmStopTemp; 722ce81151cSLikun Gao uint8_t FanMode; 7231c65e548SEvan Quan uint8_t MaxOpTemp; 724ce81151cSLikun Gao 725ce81151cSLikun Gao uint32_t Spare[13]; 726ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround 727ce81151cSLikun Gao } OverDriveTable_t; 728ce81151cSLikun Gao 729ce81151cSLikun Gao typedef struct { 730ce81151cSLikun Gao OverDriveTable_t OverDriveTable; 731ce81151cSLikun Gao 732ce81151cSLikun Gao } OverDriveTableExternal_t; 733ce81151cSLikun Gao 734ce81151cSLikun Gao typedef struct { 735ce81151cSLikun Gao uint32_t FeatureCtrlMask; 736ce81151cSLikun Gao 737ce81151cSLikun Gao int16_t VoltageOffsetPerZoneBoundary; 738a37d23f8SEvan Quan uint16_t Reserved1; 739ce81151cSLikun Gao 740a37d23f8SEvan Quan uint16_t Reserved2; 7417e5632cdSKenneth Feng 7427e5632cdSKenneth Feng int16_t GfxclkFmin; // MHz 7437e5632cdSKenneth Feng int16_t GfxclkFmax; // MHz 744ce81151cSLikun Gao uint16_t UclkFmin; // MHz 745ce81151cSLikun Gao uint16_t UclkFmax; // MHz 746ce81151cSLikun Gao 747ce81151cSLikun Gao //PPT 748ce81151cSLikun Gao int16_t Ppt; // % 7497e5632cdSKenneth Feng int16_t Tdc; 750ce81151cSLikun Gao 751ce81151cSLikun Gao uint8_t FanLinearPwmPoints; 752ce81151cSLikun Gao uint8_t FanLinearTempPoints; 753ce81151cSLikun Gao uint16_t FanMinimumPwm; 7541c65e548SEvan Quan uint16_t AcousticTargetRpmThreshold; 7551c65e548SEvan Quan uint16_t AcousticLimitRpmThreshold; 756ce81151cSLikun Gao uint16_t FanTargetTemperature; // Degree Celcius 757ce81151cSLikun Gao uint8_t FanZeroRpmEnable; 758ce81151cSLikun Gao uint8_t FanZeroRpmStopTemp; 759ce81151cSLikun Gao uint8_t FanMode; 7601c65e548SEvan Quan uint8_t MaxOpTemp; 761ce81151cSLikun Gao 762ce81151cSLikun Gao uint32_t Spare[13]; 763ce81151cSLikun Gao 764ce81151cSLikun Gao } OverDriveLimits_t; 765ce81151cSLikun Gao 766ce81151cSLikun Gao 767ce81151cSLikun Gao typedef enum { 768ce81151cSLikun Gao BOARD_GPIO_SMUIO_0, 769ce81151cSLikun Gao BOARD_GPIO_SMUIO_1, 770ce81151cSLikun Gao BOARD_GPIO_SMUIO_2, 771ce81151cSLikun Gao BOARD_GPIO_SMUIO_3, 772ce81151cSLikun Gao BOARD_GPIO_SMUIO_4, 773ce81151cSLikun Gao BOARD_GPIO_SMUIO_5, 774ce81151cSLikun Gao BOARD_GPIO_SMUIO_6, 775ce81151cSLikun Gao BOARD_GPIO_SMUIO_7, 776ce81151cSLikun Gao BOARD_GPIO_SMUIO_8, 777ce81151cSLikun Gao BOARD_GPIO_SMUIO_9, 778ce81151cSLikun Gao BOARD_GPIO_SMUIO_10, 779ce81151cSLikun Gao BOARD_GPIO_SMUIO_11, 780ce81151cSLikun Gao BOARD_GPIO_SMUIO_12, 781ce81151cSLikun Gao BOARD_GPIO_SMUIO_13, 782ce81151cSLikun Gao BOARD_GPIO_SMUIO_14, 783ce81151cSLikun Gao BOARD_GPIO_SMUIO_15, 784ce81151cSLikun Gao BOARD_GPIO_SMUIO_16, 785ce81151cSLikun Gao BOARD_GPIO_SMUIO_17, 786ce81151cSLikun Gao BOARD_GPIO_SMUIO_18, 787ce81151cSLikun Gao BOARD_GPIO_SMUIO_19, 788ce81151cSLikun Gao BOARD_GPIO_SMUIO_20, 789ce81151cSLikun Gao BOARD_GPIO_SMUIO_21, 790ce81151cSLikun Gao BOARD_GPIO_SMUIO_22, 791ce81151cSLikun Gao BOARD_GPIO_SMUIO_23, 792ce81151cSLikun Gao BOARD_GPIO_SMUIO_24, 793ce81151cSLikun Gao BOARD_GPIO_SMUIO_25, 794ce81151cSLikun Gao BOARD_GPIO_SMUIO_26, 795ce81151cSLikun Gao BOARD_GPIO_SMUIO_27, 796ce81151cSLikun Gao BOARD_GPIO_SMUIO_28, 797ce81151cSLikun Gao BOARD_GPIO_SMUIO_29, 798ce81151cSLikun Gao BOARD_GPIO_SMUIO_30, 799ce81151cSLikun Gao BOARD_GPIO_SMUIO_31, 800ce81151cSLikun Gao MAX_BOARD_GPIO_SMUIO_NUM, 801ce81151cSLikun Gao BOARD_GPIO_DC_GEN_A, 802ce81151cSLikun Gao BOARD_GPIO_DC_GEN_B, 803ce81151cSLikun Gao BOARD_GPIO_DC_GEN_C, 804ce81151cSLikun Gao BOARD_GPIO_DC_GEN_D, 805ce81151cSLikun Gao BOARD_GPIO_DC_GEN_E, 806ce81151cSLikun Gao BOARD_GPIO_DC_GEN_F, 807ce81151cSLikun Gao BOARD_GPIO_DC_GEN_G, 808ce81151cSLikun Gao BOARD_GPIO_DC_GENLK_CLK, 809ce81151cSLikun Gao BOARD_GPIO_DC_GENLK_VSYNC, 810ce81151cSLikun Gao BOARD_GPIO_DC_SWAPLOCK_A, 811ce81151cSLikun Gao BOARD_GPIO_DC_SWAPLOCK_B, 812ce81151cSLikun Gao } BOARD_GPIO_TYPE_e; 813ce81151cSLikun Gao 814ce81151cSLikun Gao #define INVALID_BOARD_GPIO 0xFF 815ce81151cSLikun Gao 816*d522ca27SKenneth Feng #define MARKETING_BASE_CLOCKS 0 817*d522ca27SKenneth Feng #define MARKETING_GAME_CLOCKS 1 818*d522ca27SKenneth Feng #define MARKETING_BOOST_CLOCKS 2 819ce81151cSLikun Gao 820ce81151cSLikun Gao typedef struct { 821ce81151cSLikun Gao //PLL 0 822ce81151cSLikun Gao uint16_t InitGfxclk_bypass; 823ce81151cSLikun Gao uint16_t InitSocclk; 824ce81151cSLikun Gao uint16_t InitMp0clk; 825ce81151cSLikun Gao uint16_t InitMpioclk; 826ce81151cSLikun Gao uint16_t InitSmnclk; 827ce81151cSLikun Gao uint16_t InitUcpclk; 828ce81151cSLikun Gao uint16_t InitCsrclk; 829ce81151cSLikun Gao //PLL 1 830ce81151cSLikun Gao 831ce81151cSLikun Gao uint16_t InitDprefclk; 832ce81151cSLikun Gao uint16_t InitDcfclk; 833ce81151cSLikun Gao uint16_t InitDtbclk; 834ce81151cSLikun Gao //PLL 2 835ce81151cSLikun Gao uint16_t InitDclk; //assume same DCLK/VCLK for both instances 836ce81151cSLikun Gao uint16_t InitVclk; 837ce81151cSLikun Gao // PLL 3 838ce81151cSLikun Gao uint16_t InitUsbdfsclk; 839ce81151cSLikun Gao uint16_t InitMp1clk; 840ce81151cSLikun Gao uint16_t InitLclk; 841ce81151cSLikun Gao uint16_t InitBaco400clk_bypass; 842ce81151cSLikun Gao uint16_t InitBaco1200clk_bypass; 843ce81151cSLikun Gao uint16_t InitBaco700clk_bypass; 844ce81151cSLikun Gao // PLL 4 845ce81151cSLikun Gao uint16_t InitFclk; 846ce81151cSLikun Gao // PLL 5 847ce81151cSLikun Gao uint16_t InitGfxclk_clkb; 848ce81151cSLikun Gao 849ce81151cSLikun Gao //PLL 6 850ce81151cSLikun Gao uint8_t InitUclkDPMState; // =0,1,2,3, frequency from FreqTableUclk 851ce81151cSLikun Gao 852ce81151cSLikun Gao uint8_t Padding[3]; 853ce81151cSLikun Gao 854ce81151cSLikun Gao uint32_t InitVcoFreqPll0; 855ce81151cSLikun Gao uint32_t InitVcoFreqPll1; 856ce81151cSLikun Gao uint32_t InitVcoFreqPll2; 857ce81151cSLikun Gao uint32_t InitVcoFreqPll3; 858ce81151cSLikun Gao uint32_t InitVcoFreqPll4; 859ce81151cSLikun Gao uint32_t InitVcoFreqPll5; 860ce81151cSLikun Gao uint32_t InitVcoFreqPll6; 861ce81151cSLikun Gao 862ce81151cSLikun Gao //encoding will change depending on SVI2/SVI3 863ce81151cSLikun Gao uint16_t InitGfx; // In mV(Q2) , should be 0? 864ce81151cSLikun Gao uint16_t InitSoc; // In mV(Q2) 865ce81151cSLikun Gao uint16_t InitU; // In Mv(Q2) 866ce81151cSLikun Gao 867ce81151cSLikun Gao uint16_t Padding2; 868ce81151cSLikun Gao 869ce81151cSLikun Gao uint32_t Spare[8]; 870ce81151cSLikun Gao 871ce81151cSLikun Gao } BootValues_t; 872ce81151cSLikun Gao 873ce81151cSLikun Gao 874ce81151cSLikun Gao typedef struct { 875ce81151cSLikun Gao uint16_t Power[PPT_THROTTLER_COUNT][POWER_SOURCE_COUNT]; // Watts 876ce81151cSLikun Gao uint16_t Tdc[TDC_THROTTLER_COUNT]; // Amps 877ce81151cSLikun Gao 878ce81151cSLikun Gao uint16_t Temperature[TEMP_COUNT]; // Celsius 879ce81151cSLikun Gao 880ce81151cSLikun Gao uint8_t PwmLimitMin; 881ce81151cSLikun Gao uint8_t PwmLimitMax; 882ce81151cSLikun Gao uint8_t FanTargetTemperature; 883ce81151cSLikun Gao uint8_t Spare1[1]; 884ce81151cSLikun Gao 885ce81151cSLikun Gao uint16_t AcousticTargetRpmThresholdMin; 886ce81151cSLikun Gao uint16_t AcousticTargetRpmThresholdMax; 887ce81151cSLikun Gao 888ce81151cSLikun Gao uint16_t AcousticLimitRpmThresholdMin; 889ce81151cSLikun Gao uint16_t AcousticLimitRpmThresholdMax; 890ce81151cSLikun Gao 891ce81151cSLikun Gao uint16_t PccLimitMin; 892ce81151cSLikun Gao uint16_t PccLimitMax; 893ce81151cSLikun Gao 894ce81151cSLikun Gao uint16_t FanStopTempMin; 895ce81151cSLikun Gao uint16_t FanStopTempMax; 896ce81151cSLikun Gao uint16_t FanStartTempMin; 897ce81151cSLikun Gao uint16_t FanStartTempMax; 898ce81151cSLikun Gao 8997e5632cdSKenneth Feng uint16_t PowerMinPpt0[POWER_SOURCE_COUNT]; 9007e5632cdSKenneth Feng uint32_t Spare[11]; 901ce81151cSLikun Gao 902ce81151cSLikun Gao } MsgLimits_t; 903ce81151cSLikun Gao 904ce81151cSLikun Gao typedef struct { 905ce81151cSLikun Gao uint16_t BaseClockAc; 906ce81151cSLikun Gao uint16_t GameClockAc; 907ce81151cSLikun Gao uint16_t BoostClockAc; 908ce81151cSLikun Gao uint16_t BaseClockDc; 909ce81151cSLikun Gao uint16_t GameClockDc; 910ce81151cSLikun Gao uint16_t BoostClockDc; 911ce81151cSLikun Gao 912ce81151cSLikun Gao uint32_t Reserved[4]; 913ce81151cSLikun Gao } DriverReportedClocks_t; 914ce81151cSLikun Gao 915ce81151cSLikun Gao typedef struct { 916ce81151cSLikun Gao uint8_t DcBtcEnabled; 917ce81151cSLikun Gao uint8_t Padding[3]; 918ce81151cSLikun Gao 919ce81151cSLikun Gao uint16_t DcTol; // mV Q2 920ce81151cSLikun Gao uint16_t DcBtcGb; // mV Q2 921ce81151cSLikun Gao 922ce81151cSLikun Gao uint16_t DcBtcMin; // mV Q2 923ce81151cSLikun Gao uint16_t DcBtcMax; // mV Q2 924ce81151cSLikun Gao 925ce81151cSLikun Gao LinearInt_t DcBtcGbScalar; 926ce81151cSLikun Gao 927ce81151cSLikun Gao } AvfsDcBtcParams_t; 928ce81151cSLikun Gao 929ce81151cSLikun Gao typedef struct { 930ce81151cSLikun Gao uint16_t AvfsTemp[AVFS_TEMP_COUNT]; //in degrees C 931ce81151cSLikun Gao uint16_t VftFMin; // in MHz 932ce81151cSLikun Gao uint16_t VInversion; // in mV Q2 933ce81151cSLikun Gao QuadraticInt_t qVft[AVFS_TEMP_COUNT]; 934ce81151cSLikun Gao QuadraticInt_t qAvfsGb; 935ce81151cSLikun Gao QuadraticInt_t qAvfsGb2; 936ce81151cSLikun Gao } AvfsFuseOverride_t; 937ce81151cSLikun Gao 938ce81151cSLikun Gao typedef struct { 939ce81151cSLikun Gao // SECTION: Version 940ce81151cSLikun Gao 941ce81151cSLikun Gao uint32_t Version; // should be unique to each SKU(i.e if any value changes in below structure then this value must be different) 942ce81151cSLikun Gao 943ce81151cSLikun Gao // SECTION: Feature Control 944ce81151cSLikun Gao uint32_t FeaturesToRun[NUM_FEATURES / 32]; // Features that PMFW will attempt to enable. Use FEATURE_*_BIT as mapping 945ce81151cSLikun Gao 946ce81151cSLikun Gao // SECTION: Miscellaneous Configuration 947ce81151cSLikun Gao uint8_t TotalPowerConfig; // Determines how PMFW calculates the power. Use defines from PwrConfig_e 948ce81151cSLikun Gao uint8_t CustomerVariant; //To specify if this PPTable is intended for a particular customer. Use defines from CUSTOMER_VARIANT_e 949ce81151cSLikun Gao uint8_t MemoryTemperatureTypeMask; // Bit mapping indicating which methods of memory temperature reading are enabled. Use defines from MEM_TEMP_*BIT 950ce81151cSLikun Gao uint8_t SmartShiftVersion; // Determine what SmartShift feature version is supported Use defines from SMARTSHIFT_VERSION_e 951ce81151cSLikun Gao 952ce81151cSLikun Gao // SECTION: Infrastructure Limits 953ce81151cSLikun Gao uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in AC mode. Multiple limits supported 954ce81151cSLikun Gao uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in DC mode. Multiple limits supported 955ce81151cSLikun Gao 956ce81151cSLikun Gao uint16_t SocketPowerLimitSmartShift2; // In Watts. Power limit used SmartShift 957ce81151cSLikun Gao 958ce81151cSLikun Gao //if set to 1, SocketPowerLimitAc and SocketPowerLimitDc will be interpreted as legacy programs(i.e absolute power). If 0, all except index 0 will be scalars 959ce81151cSLikun Gao //relative index 0 960ce81151cSLikun Gao uint8_t EnableLegacyPptLimit; 961ce81151cSLikun Gao uint8_t UseInputTelemetry; //applicable to SVI3 only and only to be set if VRs support 962ce81151cSLikun Gao uint8_t SmartShiftMinReportedPptinDcs; //minimum possible active power consumption for this SKU. Used for SmartShift power reporting 963ce81151cSLikun Gao 964ce81151cSLikun Gao uint8_t PaddingPpt[1]; 965ce81151cSLikun Gao 966ce81151cSLikun Gao uint16_t VrTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with VR regulator maximum temperature 967ce81151cSLikun Gao 968ce81151cSLikun Gao uint16_t PlatformTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with platform maximum temperature per VR current rail 969ce81151cSLikun Gao 970ce81151cSLikun Gao uint16_t TemperatureLimit[TEMP_COUNT]; // In degrees Celsius. Temperature limit associated with each input 971ce81151cSLikun Gao 972ce81151cSLikun Gao uint16_t HwCtfTempLimit; // In degrees Celsius. Temperature above which HW will trigger CTF. Consumed by VBIOS only 973ce81151cSLikun Gao 974ce81151cSLikun Gao uint16_t PaddingInfra; 975ce81151cSLikun Gao 976ce81151cSLikun Gao // Per year normalized Vmax state failure rates (sum of the two domains divided by life time in years) 977ce81151cSLikun Gao uint32_t FitControllerFailureRateLimit; //in IEEE float 978ce81151cSLikun Gao //Expected GFX Duty Cycle at Vmax. 979ce81151cSLikun Gao uint32_t FitControllerGfxDutyCycle; // in IEEE float 980ce81151cSLikun Gao //Expected SOC Duty Cycle at Vmax. 981ce81151cSLikun Gao uint32_t FitControllerSocDutyCycle; // in IEEE float 982ce81151cSLikun Gao 983ce81151cSLikun Gao //This offset will be deducted from the controller output to before it goes through the SOC Vset limiter block. 984ce81151cSLikun Gao uint32_t FitControllerSocOffset; //in IEEE float 985ce81151cSLikun Gao 986ce81151cSLikun Gao uint32_t GfxApccPlusResidencyLimit; // Percentage value. Used by APCC+ controller to control PCC residency to some value 987ce81151cSLikun Gao 988ce81151cSLikun Gao // SECTION: Throttler settings 989ce81151cSLikun Gao uint32_t ThrottlerControlMask; // See THROTTLER_*_BIT for mapping 990ce81151cSLikun Gao 991ce81151cSLikun Gao // SECTION: FW DSTATE Settings 992ce81151cSLikun Gao uint32_t FwDStateMask; // See FW_DSTATE_*_BIT for mapping 993ce81151cSLikun Gao 994ce81151cSLikun Gao // SECTION: Voltage Control Parameters 995ce81151cSLikun Gao uint16_t UlvVoltageOffset[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2). ULV offset used in either GFX_ULV or SOC_ULV(part of FW_DSTATE) 996ce81151cSLikun Gao 997ce81151cSLikun Gao uint16_t UlvVoltageOffsetU; // In mV(Q2). ULV offset used in either U_ULV(part of FW_DSTATE) 998ce81151cSLikun Gao uint16_t DeepUlvVoltageOffsetSoc; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC as part of FW_DSTATE 999ce81151cSLikun Gao 1000ce81151cSLikun Gao // Voltage Limits 1001ce81151cSLikun Gao uint16_t DefaultMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage without FIT controller enabled 1002ce81151cSLikun Gao uint16_t BoostMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage with FIT controller enabled 1003ce81151cSLikun Gao 1004ce81151cSLikun Gao //Vmin Optimizations 1005ce81151cSLikun Gao int16_t VminTempHystersis[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature hysteresis for switching between low/high temperature values for Vmin 1006ce81151cSLikun Gao int16_t VminTempThreshold[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature threshold for switching between low/high temperature values for Vmin 1007ce81151cSLikun Gao uint16_t Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at hot. 1008ce81151cSLikun Gao uint16_t Vmin_Cold_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at cold. 1009ce81151cSLikun Gao uint16_t Vmin_Hot_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at hot. 1010ce81151cSLikun Gao uint16_t Vmin_Cold_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at cold. 1011ce81151cSLikun Gao uint16_t Vmin_Aging_Offset[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Worst-case aging margin 101225dfc8faSEvan Quan uint16_t Spare_Vmin_Plat_Offset_Hot[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Hot 101325dfc8faSEvan Quan uint16_t Spare_Vmin_Plat_Offset_Cold[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Cold 1014ce81151cSLikun Gao 1015ce81151cSLikun Gao //This is a fixed/minimum VMIN aging degradation offset which is applied at T0. This reflects the minimum amount of aging already accounted for. 1016ce81151cSLikun Gao uint16_t VcBtcFixedVminAgingOffset[PMFW_VOLT_PLANE_COUNT]; 1017ce81151cSLikun Gao //Linear offset or GB term to account for mis-correlation between PSM and Vmin shift trends across parts. 1018ce81151cSLikun Gao uint16_t VcBtcVmin2PsmDegrationGb[PMFW_VOLT_PLANE_COUNT]; 1019ce81151cSLikun Gao //Scalar coefficient of the PSM aging degradation function 1020ce81151cSLikun Gao uint32_t VcBtcPsmA[PMFW_VOLT_PLANE_COUNT]; // A_PSM 1021ce81151cSLikun Gao //Exponential coefficient of the PSM aging degradation function 1022ce81151cSLikun Gao uint32_t VcBtcPsmB[PMFW_VOLT_PLANE_COUNT]; // B_PSM 1023ce81151cSLikun Gao //Scalar coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 1024ce81151cSLikun Gao uint32_t VcBtcVminA[PMFW_VOLT_PLANE_COUNT]; // A_VMIN 1025ce81151cSLikun Gao //Exponential coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 1026ce81151cSLikun Gao uint32_t VcBtcVminB[PMFW_VOLT_PLANE_COUNT]; // B_VMIN 1027ce81151cSLikun Gao 1028ce81151cSLikun Gao uint8_t PerPartVminEnabled[PMFW_VOLT_PLANE_COUNT]; 1029ce81151cSLikun Gao uint8_t VcBtcEnabled[PMFW_VOLT_PLANE_COUNT]; 1030ce81151cSLikun Gao 1031ce81151cSLikun Gao uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 1032ce81151cSLikun Gao uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 1033ce81151cSLikun Gao 10341c65e548SEvan Quan QuadraticInt_t Vmin_droop; 10351c65e548SEvan Quan uint32_t SpareVmin[9]; 1036ce81151cSLikun Gao 1037ce81151cSLikun Gao 1038ce81151cSLikun Gao //SECTION: DPM Configuration 1 1039ce81151cSLikun Gao DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 1040ce81151cSLikun Gao 1041ce81151cSLikun Gao uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1042ce81151cSLikun Gao uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1043ce81151cSLikun Gao uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1044ce81151cSLikun Gao uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1045ce81151cSLikun Gao uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1046ce81151cSLikun Gao uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1047ce81151cSLikun Gao uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1048ce81151cSLikun Gao uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1049ce81151cSLikun Gao uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1050ce81151cSLikun Gao uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1051ce81151cSLikun Gao uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1052ce81151cSLikun Gao 1053ce81151cSLikun Gao uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1054ce81151cSLikun Gao 1055ce81151cSLikun Gao // SECTION: DPM Configuration 2 1056ce81151cSLikun Gao uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 1057ce81151cSLikun Gao uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 1058ce81151cSLikun Gao 1059ce81151cSLikun Gao uint8_t GfxclkSpare[2]; 1060ce81151cSLikun Gao uint16_t GfxclkFreqCap; 1061ce81151cSLikun Gao 1062ce81151cSLikun Gao //GFX Idle Power Settings 1063ce81151cSLikun Gao uint16_t GfxclkFgfxoffEntry; // in Mhz 1064ce81151cSLikun Gao uint16_t GfxclkFgfxoffExitImu; // in Mhz 1065ce81151cSLikun Gao uint16_t GfxclkFgfxoffExitRlc; // in Mhz 1066ce81151cSLikun Gao uint16_t GfxclkThrottleClock; //Used primarily in DCS 1067ce81151cSLikun Gao uint8_t EnableGfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages 1068ce81151cSLikun Gao uint8_t GfxIdlePadding; 1069ce81151cSLikun Gao 1070ce81151cSLikun Gao uint8_t SmsRepairWRCKClkDivEn; 1071ce81151cSLikun Gao uint8_t SmsRepairWRCKClkDivVal; 1072ce81151cSLikun Gao uint8_t GfxOffEntryEarlyMGCGEn; 1073ce81151cSLikun Gao uint8_t GfxOffEntryForceCGCGEn; 1074ce81151cSLikun Gao uint8_t GfxOffEntryForceCGCGDelayEn; 1075ce81151cSLikun Gao uint8_t GfxOffEntryForceCGCGDelayVal; // in microseconds 1076ce81151cSLikun Gao 1077ce81151cSLikun Gao uint16_t GfxclkFreqGfxUlv; // in MHz 1078ce81151cSLikun Gao uint8_t GfxIdlePadding2[2]; 1079ce81151cSLikun Gao 1080cbe07c98SEvan Quan uint32_t GfxOffEntryHysteresis; 1081cbe07c98SEvan Quan uint32_t GfxoffSpare[15]; 1082ce81151cSLikun Gao 1083ce81151cSLikun Gao // GFX GPO 10847e5632cdSKenneth Feng uint32_t DfllBtcMasterScalerM; 10857e5632cdSKenneth Feng int32_t DfllBtcMasterScalerB; 10867e5632cdSKenneth Feng uint32_t DfllBtcSlaveScalerM; 10877e5632cdSKenneth Feng int32_t DfllBtcSlaveScalerB; 10887e5632cdSKenneth Feng 10897e5632cdSKenneth Feng uint32_t DfllPccAsWaitCtrl; //GDFLL_AS_WAIT_CTRL_PCC register value to be passed to RLC msg 10907e5632cdSKenneth Feng uint32_t DfllPccAsStepCtrl; //GDFLL_AS_STEP_CTRL_PCC register value to be passed to RLC msg 10917e5632cdSKenneth Feng 10927e5632cdSKenneth Feng uint32_t DfllL2FrequencyBoostM; //Unitless (float) 10937e5632cdSKenneth Feng uint32_t DfllL2FrequencyBoostB; //In MHz (integer) 10947e5632cdSKenneth Feng uint32_t GfxGpoSpare[8]; 1095ce81151cSLikun Gao 1096ce81151cSLikun Gao // GFX DCS 1097ce81151cSLikun Gao 1098ce81151cSLikun Gao uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase 1099ce81151cSLikun Gao uint16_t PaddingDcs; 1100ce81151cSLikun Gao 1101ce81151cSLikun Gao uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase 1102ce81151cSLikun Gao uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. 1103ce81151cSLikun Gao 1104ce81151cSLikun Gao uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS. 1105ce81151cSLikun Gao 1106ce81151cSLikun Gao uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. 1107ce81151cSLikun Gao uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin. 1108ce81151cSLikun Gao 1109*d522ca27SKenneth Feng uint8_t FoptEnabled; 1110*d522ca27SKenneth Feng uint8_t DcsSpare2[3]; 1111*d522ca27SKenneth Feng uint32_t DcsFoptM; //Tuning paramters to shift Fopt calculation 1112*d522ca27SKenneth Feng uint32_t DcsFoptB; //Tuning paramters to shift Fopt calculation 1113ce81151cSLikun Gao 1114*d522ca27SKenneth Feng uint32_t DcsSpare[11]; 1115ce81151cSLikun Gao 1116ce81151cSLikun Gao // UCLK section 1117*d522ca27SKenneth Feng uint16_t ShadowFreqTableUclk[NUM_UCLK_DPM_LEVELS]; // In MHz 1118ce81151cSLikun Gao uint8_t UseStrobeModeOptimizations; //Set to indicate that FW should use strobe mode optimizations 1119ce81151cSLikun Gao uint8_t PaddingMem[3]; 1120ce81151cSLikun Gao 1121ce81151cSLikun Gao uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 1122ce81151cSLikun Gao uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 1123ce81151cSLikun Gao 1124ce81151cSLikun Gao uint16_t MemVmempVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1125ce81151cSLikun Gao uint16_t MemVddioVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1126ce81151cSLikun Gao 1127ce81151cSLikun Gao //FCLK Section 1128ce81151cSLikun Gao 1129ce81151cSLikun Gao uint8_t FclkDpmUPstates[NUM_FCLK_DPM_LEVELS]; // U P-state ID associated with each FCLK DPM state. 1130ce81151cSLikun Gao uint16_t FclkDpmVddU[NUM_FCLK_DPM_LEVELS]; // mV(Q2) Vset U voltage associated with each FCLK DPM state. 1131ce81151cSLikun Gao uint16_t FclkDpmUSpeed[NUM_FCLK_DPM_LEVELS]; //U speed associated with each FCLK DPM state 1132ce81151cSLikun Gao uint16_t FclkDpmDisallowPstateFreq; //Frequency which FW will target when indicated that display config cannot support P-state. Set to 0 use FW calculated value 1133ce81151cSLikun Gao uint16_t PaddingFclk; 1134ce81151cSLikun Gao 1135ce81151cSLikun Gao // Link DPM Settings 1136ce81151cSLikun Gao uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 1137ce81151cSLikun Gao uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 1138ce81151cSLikun Gao uint16_t LclkFreq[NUM_LINK_LEVELS]; 1139ce81151cSLikun Gao 1140ce81151cSLikun Gao // SECTION: Fan Control 1141ce81151cSLikun Gao uint16_t FanStopTemp[TEMP_COUNT]; //Celsius 1142ce81151cSLikun Gao uint16_t FanStartTemp[TEMP_COUNT]; //Celsius 1143ce81151cSLikun Gao 1144ce81151cSLikun Gao uint16_t FanGain[TEMP_COUNT]; 1145ce81151cSLikun Gao uint16_t FanGainPadding; 1146ce81151cSLikun Gao 1147ce81151cSLikun Gao uint16_t FanPwmMin; 1148ce81151cSLikun Gao uint16_t AcousticTargetRpmThreshold; 1149ce81151cSLikun Gao uint16_t AcousticLimitRpmThreshold; 1150ce81151cSLikun Gao uint16_t FanMaximumRpm; 1151ce81151cSLikun Gao uint16_t MGpuAcousticLimitRpmThreshold; 1152ce81151cSLikun Gao uint16_t FanTargetGfxclk; 1153ce81151cSLikun Gao uint32_t TempInputSelectMask; 1154ce81151cSLikun Gao uint8_t FanZeroRpmEnable; 1155ce81151cSLikun Gao uint8_t FanTachEdgePerRev; 1156ce81151cSLikun Gao uint16_t FanTargetTemperature[TEMP_COUNT]; 1157ce81151cSLikun Gao 1158ce81151cSLikun Gao // The following are AFC override parameters. Leave at 0 to use FW defaults. 1159ce81151cSLikun Gao int16_t FuzzyFan_ErrorSetDelta; 1160ce81151cSLikun Gao int16_t FuzzyFan_ErrorRateSetDelta; 1161ce81151cSLikun Gao int16_t FuzzyFan_PwmSetDelta; 1162ce81151cSLikun Gao uint16_t FuzzyFan_Reserved; 1163ce81151cSLikun Gao 1164ce81151cSLikun Gao uint16_t FwCtfLimit[TEMP_COUNT]; 1165ce81151cSLikun Gao 1166ce81151cSLikun Gao uint16_t IntakeTempEnableRPM; 1167ce81151cSLikun Gao int16_t IntakeTempOffsetTemp; 1168ce81151cSLikun Gao uint16_t IntakeTempReleaseTemp; 1169ce81151cSLikun Gao uint16_t IntakeTempHighIntakeAcousticLimit; 1170ce81151cSLikun Gao uint16_t IntakeTempAcouticLimitReleaseRate; 1171ce81151cSLikun Gao 11727e5632cdSKenneth Feng int16_t FanAbnormalTempLimitOffset; 1173ce81151cSLikun Gao uint16_t FanStalledTriggerRpm; 11747e5632cdSKenneth Feng uint16_t FanAbnormalTriggerRpmCoeff; 11757e5632cdSKenneth Feng uint16_t FanAbnormalDetectionEnable; 1176ce81151cSLikun Gao 11777e5632cdSKenneth Feng uint8_t FanIntakeSensorSupport; 11787e5632cdSKenneth Feng uint8_t FanIntakePadding[3]; 11797e5632cdSKenneth Feng uint32_t FanSpare[13]; 1180ce81151cSLikun Gao 1181ce81151cSLikun Gao // SECTION: VDD_GFX AVFS 1182ce81151cSLikun Gao 1183ce81151cSLikun Gao uint8_t OverrideGfxAvfsFuses; 1184ce81151cSLikun Gao uint8_t GfxAvfsPadding[3]; 1185ce81151cSLikun Gao 1186ce81151cSLikun Gao uint32_t L2HwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; //see fusedoc for encoding 1187ce81151cSLikun Gao uint32_t SeHwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; 1188ce81151cSLikun Gao 1189ce81151cSLikun Gao uint32_t CommonRtAvfs[PP_GRTAVFS_FW_COMMON_FUSE_COUNT]; 1190ce81151cSLikun Gao 1191ce81151cSLikun Gao uint32_t L2FwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1192ce81151cSLikun Gao uint32_t SeFwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1193ce81151cSLikun Gao 1194ce81151cSLikun Gao uint32_t Droop_PWL_F[PP_NUM_RTAVFS_PWL_ZONES]; 1195ce81151cSLikun Gao uint32_t Droop_PWL_a[PP_NUM_RTAVFS_PWL_ZONES]; 1196ce81151cSLikun Gao uint32_t Droop_PWL_b[PP_NUM_RTAVFS_PWL_ZONES]; 1197ce81151cSLikun Gao uint32_t Droop_PWL_c[PP_NUM_RTAVFS_PWL_ZONES]; 1198ce81151cSLikun Gao 1199ce81151cSLikun Gao uint32_t Static_PWL_Offset[PP_NUM_RTAVFS_PWL_ZONES]; 1200ce81151cSLikun Gao 1201ce81151cSLikun Gao uint32_t dGbV_dT_vmin; 1202ce81151cSLikun Gao uint32_t dGbV_dT_vmax; 1203ce81151cSLikun Gao 1204ce81151cSLikun Gao //Unused: PMFW-9370 1205ce81151cSLikun Gao uint32_t V2F_vmin_range_low; 1206ce81151cSLikun Gao uint32_t V2F_vmin_range_high; 1207ce81151cSLikun Gao uint32_t V2F_vmax_range_low; 1208ce81151cSLikun Gao uint32_t V2F_vmax_range_high; 1209ce81151cSLikun Gao 1210ce81151cSLikun Gao AvfsDcBtcParams_t DcBtcGfxParams; 1211ce81151cSLikun Gao 1212ce81151cSLikun Gao uint32_t GfxAvfsSpare[32]; 1213ce81151cSLikun Gao 1214ce81151cSLikun Gao //SECTION: VDD_SOC AVFS 1215ce81151cSLikun Gao 1216ce81151cSLikun Gao uint8_t OverrideSocAvfsFuses; 1217ce81151cSLikun Gao uint8_t MinSocAvfsRevision; 1218ce81151cSLikun Gao uint8_t SocAvfsPadding[2]; 1219ce81151cSLikun Gao 1220ce81151cSLikun Gao AvfsFuseOverride_t SocAvfsFuseOverride[AVFS_D_COUNT]; 1221ce81151cSLikun Gao 1222ce81151cSLikun Gao DroopInt_t dBtcGbSoc[AVFS_D_COUNT]; // GHz->V BtcGb 1223ce81151cSLikun Gao 1224ce81151cSLikun Gao LinearInt_t qAgingGb[AVFS_D_COUNT]; // GHz->V 1225ce81151cSLikun Gao 1226ce81151cSLikun Gao QuadraticInt_t qStaticVoltageOffset[AVFS_D_COUNT]; // GHz->V 1227ce81151cSLikun Gao 1228ce81151cSLikun Gao AvfsDcBtcParams_t DcBtcSocParams[AVFS_D_COUNT]; 1229ce81151cSLikun Gao 1230ce81151cSLikun Gao uint32_t SocAvfsSpare[32]; 1231ce81151cSLikun Gao 1232ce81151cSLikun Gao //SECTION: Boot clock and voltage values 1233ce81151cSLikun Gao BootValues_t BootValues; 1234ce81151cSLikun Gao 1235ce81151cSLikun Gao //SECTION: Driver Reported Clocks 1236ce81151cSLikun Gao DriverReportedClocks_t DriverReportedClocks; 1237ce81151cSLikun Gao 1238ce81151cSLikun Gao //SECTION: Message Limits 1239ce81151cSLikun Gao MsgLimits_t MsgLimits; 1240ce81151cSLikun Gao 1241ce81151cSLikun Gao //SECTION: OverDrive Limits 1242ce81151cSLikun Gao OverDriveLimits_t OverDriveLimitsMin; 1243ce81151cSLikun Gao OverDriveLimits_t OverDriveLimitsBasicMax; 1244ce81151cSLikun Gao uint32_t reserved[22]; 1245ce81151cSLikun Gao 1246ce81151cSLikun Gao // SECTION: Advanced Options 1247ce81151cSLikun Gao uint32_t DebugOverrides; 1248ce81151cSLikun Gao 1249da1acbb1SEvan Quan // Section: Total Board Power idle vs active coefficients 1250da1acbb1SEvan Quan uint8_t TotalBoardPowerSupport; 1251da1acbb1SEvan Quan uint8_t TotalBoardPowerPadding[3]; 1252da1acbb1SEvan Quan 1253da1acbb1SEvan Quan int16_t TotalIdleBoardPowerM; 1254da1acbb1SEvan Quan int16_t TotalIdleBoardPowerB; 1255da1acbb1SEvan Quan int16_t TotalBoardPowerM; 1256da1acbb1SEvan Quan int16_t TotalBoardPowerB; 1257da1acbb1SEvan Quan 12587e5632cdSKenneth Feng //PMFW-11158 12597e5632cdSKenneth Feng QuadraticInt_t qFeffCoeffGameClock[POWER_SOURCE_COUNT]; 12607e5632cdSKenneth Feng QuadraticInt_t qFeffCoeffBaseClock[POWER_SOURCE_COUNT]; 12617e5632cdSKenneth Feng QuadraticInt_t qFeffCoeffBoostClock[POWER_SOURCE_COUNT]; 12627e5632cdSKenneth Feng 1263*d522ca27SKenneth Feng uint16_t TemperatureLimit_Hynix; // In degrees Celsius. Memory temperature limit associated with Hynix 1264*d522ca27SKenneth Feng uint16_t TemperatureLimit_Micron; // In degrees Celsius. Memory temperature limit associated with Micron 1265*d522ca27SKenneth Feng uint16_t TemperatureFwCtfLimit_Hynix; 1266*d522ca27SKenneth Feng uint16_t TemperatureFwCtfLimit_Micron; 1267*d522ca27SKenneth Feng 1268ce81151cSLikun Gao // SECTION: Sku Reserved 1269*d522ca27SKenneth Feng uint32_t Spare[41]; 1270ce81151cSLikun Gao 1271ce81151cSLikun Gao // Padding for MMHUB - do not modify this 1272ce81151cSLikun Gao uint32_t MmHubPadding[8]; 1273ce81151cSLikun Gao 1274ce81151cSLikun Gao } SkuTable_t; 1275ce81151cSLikun Gao 1276ce81151cSLikun Gao typedef struct { 1277ce81151cSLikun Gao // SECTION: Version 1278ce81151cSLikun Gao uint32_t Version; //should be unique to each board type 1279ce81151cSLikun Gao 1280ce81151cSLikun Gao 1281ce81151cSLikun Gao // SECTION: I2C Control 1282ce81151cSLikun Gao I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 1283ce81151cSLikun Gao 1284ce81151cSLikun Gao // SECTION: SVI2 Board Parameters 1285ce81151cSLikun Gao uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 1286ce81151cSLikun Gao uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 1287ce81151cSLikun Gao uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 1288ce81151cSLikun Gao uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 1289ce81151cSLikun Gao 1290ce81151cSLikun Gao uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1291ce81151cSLikun Gao uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1292ce81151cSLikun Gao uint8_t VmempUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1293ce81151cSLikun Gao uint8_t VddioUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1294ce81151cSLikun Gao 1295ce81151cSLikun Gao //SECTION SVI3 Board Parameters 1296ce81151cSLikun Gao uint8_t SlaveAddrMapping[SVI_PLANE_COUNT]; 1297ce81151cSLikun Gao uint8_t VrPsiSupport[SVI_PLANE_COUNT]; 1298ce81151cSLikun Gao 1299ce81151cSLikun Gao uint8_t PaddingPsi[SVI_PLANE_COUNT]; 1300ce81151cSLikun Gao uint8_t EnablePsi6[SVI_PLANE_COUNT]; // only applicable in SVI3 1301ce81151cSLikun Gao 1302ce81151cSLikun Gao // SECTION: Voltage Regulator Settings 1303ce81151cSLikun Gao SviTelemetryScale_t SviTelemetryScale[SVI_PLANE_COUNT]; 1304ce81151cSLikun Gao uint32_t VoltageTelemetryRatio[SVI_PLANE_COUNT]; // This is used for VDDIO Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 1305ce81151cSLikun Gao 1306ce81151cSLikun Gao uint8_t DownSlewRateVr[SVI_PLANE_COUNT]; 1307ce81151cSLikun Gao 1308ce81151cSLikun Gao // SECTION: GPIO Settings 1309ce81151cSLikun Gao 1310ce81151cSLikun Gao uint8_t LedOffGpio; 1311ce81151cSLikun Gao uint8_t FanOffGpio; 1312ce81151cSLikun Gao uint8_t GfxVrPowerStageOffGpio; 1313ce81151cSLikun Gao 1314ce81151cSLikun Gao uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 1315ce81151cSLikun Gao uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 1316ce81151cSLikun Gao uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 1317ce81151cSLikun Gao uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 1318ce81151cSLikun Gao 1319ce81151cSLikun Gao uint8_t GthrGpio; // GPIO pin configured for GTHR Event 1320ce81151cSLikun Gao uint8_t GthrPolarity; // replace GPIO polarity for GTHR 1321ce81151cSLikun Gao 1322ce81151cSLikun Gao // LED Display Settings 1323ce81151cSLikun Gao uint8_t LedPin0; // GPIO number for LedPin[0] 1324ce81151cSLikun Gao uint8_t LedPin1; // GPIO number for LedPin[1] 1325ce81151cSLikun Gao uint8_t LedPin2; // GPIO number for LedPin[2] 1326ce81151cSLikun Gao uint8_t LedEnableMask; 1327ce81151cSLikun Gao 1328ce81151cSLikun Gao uint8_t LedPcie; // GPIO number for PCIE results 1329ce81151cSLikun Gao uint8_t LedError; // GPIO number for Error Cases 1330ce81151cSLikun Gao 1331ce81151cSLikun Gao // SECTION: Clock Spread Spectrum 1332ce81151cSLikun Gao 1333ce81151cSLikun Gao // UCLK Spread Spectrum 1334da1acbb1SEvan Quan uint8_t UclkTrainingModeSpreadPercent; 1335da1acbb1SEvan Quan uint8_t UclkSpreadPadding; 1336ce81151cSLikun Gao uint16_t UclkSpreadFreq; // kHz 1337ce81151cSLikun Gao 1338ce81151cSLikun Gao // UCLK Spread Spectrum 1339ce81151cSLikun Gao uint8_t UclkSpreadPercent[MEM_VENDOR_COUNT]; 1340ce81151cSLikun Gao 1341*d522ca27SKenneth Feng uint8_t GfxclkSpreadEnable; 1342*d522ca27SKenneth Feng 1343ce81151cSLikun Gao // FCLK Spread Spectrum 1344ce81151cSLikun Gao uint8_t FclkSpreadPercent; // Q4.4 1345ce81151cSLikun Gao uint16_t FclkSpreadFreq; // kHz 1346ce81151cSLikun Gao 1347ce81151cSLikun Gao // Section: Memory Config 1348ce81151cSLikun Gao uint8_t DramWidth; // Width of interface to the channel for each DRAM module. See DRAM_BIT_WIDTH_TYPE_e 1349da1acbb1SEvan Quan uint8_t PaddingMem1[7]; 1350ce81151cSLikun Gao 1351ce81151cSLikun Gao // SECTION: UMC feature flags 1352ce81151cSLikun Gao uint8_t HsrEnabled; 1353ce81151cSLikun Gao uint8_t VddqOffEnabled; 1354ce81151cSLikun Gao uint8_t PaddingUmcFlags[2]; 1355ce81151cSLikun Gao 1356ce81151cSLikun Gao uint32_t PostVoltageSetBacoDelay; // in microseconds. Amount of time FW will wait after power good is established or PSI0 command is issued 1357ce81151cSLikun Gao uint32_t BacoEntryDelay; // in milliseconds. Amount of time FW will wait to trigger BACO entry after receiving entry notification from OS 1358ce81151cSLikun Gao 13597e5632cdSKenneth Feng uint8_t FuseWritePowerMuxPresent; 13607e5632cdSKenneth Feng uint8_t FuseWritePadding[3]; 13617e5632cdSKenneth Feng 1362ce81151cSLikun Gao // SECTION: Board Reserved 13637e5632cdSKenneth Feng uint32_t BoardSpare[63]; 1364ce81151cSLikun Gao 1365ce81151cSLikun Gao // SECTION: Structure Padding 1366ce81151cSLikun Gao 1367ce81151cSLikun Gao // Padding for MMHUB - do not modify this 1368ce81151cSLikun Gao uint32_t MmHubPadding[8]; 1369ce81151cSLikun Gao } BoardTable_t; 1370ce81151cSLikun Gao 1371f989fa29SJonathan Gray #pragma pack(push, 1) 1372ce81151cSLikun Gao typedef struct { 1373ce81151cSLikun Gao SkuTable_t SkuTable; 1374ce81151cSLikun Gao BoardTable_t BoardTable; 1375ce81151cSLikun Gao } PPTable_t; 1376f989fa29SJonathan Gray #pragma pack(pop) 1377ce81151cSLikun Gao 1378ce81151cSLikun Gao typedef struct { 1379ce81151cSLikun Gao // Time constant parameters for clock averages in ms 1380ce81151cSLikun Gao uint16_t GfxclkAverageLpfTau; 1381ce81151cSLikun Gao uint16_t FclkAverageLpfTau; 1382ce81151cSLikun Gao uint16_t UclkAverageLpfTau; 1383ce81151cSLikun Gao uint16_t GfxActivityLpfTau; 1384ce81151cSLikun Gao uint16_t UclkActivityLpfTau; 1385ce81151cSLikun Gao uint16_t SocketPowerLpfTau; 1386ce81151cSLikun Gao uint16_t VcnClkAverageLpfTau; 1387ce81151cSLikun Gao uint16_t VcnUsageAverageLpfTau; 1388ce81151cSLikun Gao } DriverSmuConfig_t; 1389ce81151cSLikun Gao 1390ce81151cSLikun Gao typedef struct { 1391ce81151cSLikun Gao DriverSmuConfig_t DriverSmuConfig; 1392ce81151cSLikun Gao 1393ce81151cSLikun Gao uint32_t Spare[8]; 1394ce81151cSLikun Gao // Padding - ignore 1395ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1396ce81151cSLikun Gao } DriverSmuConfigExternal_t; 1397ce81151cSLikun Gao 1398ce81151cSLikun Gao 1399ce81151cSLikun Gao typedef struct { 1400ce81151cSLikun Gao 1401ce81151cSLikun Gao uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1402ce81151cSLikun Gao uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1403ce81151cSLikun Gao uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1404ce81151cSLikun Gao uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1405ce81151cSLikun Gao uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1406ce81151cSLikun Gao uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1407ce81151cSLikun Gao uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1408ce81151cSLikun Gao uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1409ce81151cSLikun Gao uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1410ce81151cSLikun Gao uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1411ce81151cSLikun Gao uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1412ce81151cSLikun Gao 1413ce81151cSLikun Gao uint16_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1414ce81151cSLikun Gao 1415ce81151cSLikun Gao uint16_t Padding; 1416ce81151cSLikun Gao 1417ce81151cSLikun Gao uint32_t Spare[32]; 1418ce81151cSLikun Gao 1419ce81151cSLikun Gao // Padding - ignore 1420ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1421ce81151cSLikun Gao 1422ce81151cSLikun Gao } DriverInfoTable_t; 1423ce81151cSLikun Gao 1424ce81151cSLikun Gao typedef struct { 1425ce81151cSLikun Gao uint32_t CurrClock[PPCLK_COUNT]; 1426ce81151cSLikun Gao 1427ce81151cSLikun Gao uint16_t AverageGfxclkFrequencyTarget; 1428ce81151cSLikun Gao uint16_t AverageGfxclkFrequencyPreDs; 1429ce81151cSLikun Gao uint16_t AverageGfxclkFrequencyPostDs; 1430ce81151cSLikun Gao uint16_t AverageFclkFrequencyPreDs; 1431ce81151cSLikun Gao uint16_t AverageFclkFrequencyPostDs; 1432ce81151cSLikun Gao uint16_t AverageMemclkFrequencyPreDs ; // this is scaled to actual memory clock 1433ce81151cSLikun Gao uint16_t AverageMemclkFrequencyPostDs ; // this is scaled to actual memory clock 1434ce81151cSLikun Gao uint16_t AverageVclk0Frequency ; 1435ce81151cSLikun Gao uint16_t AverageDclk0Frequency ; 1436ce81151cSLikun Gao uint16_t AverageVclk1Frequency ; 1437ce81151cSLikun Gao uint16_t AverageDclk1Frequency ; 143866f54992SEvan Quan uint16_t PCIeBusy; 143966f54992SEvan Quan uint16_t dGPU_W_MAX; 144066f54992SEvan Quan uint16_t padding; 144166f54992SEvan Quan 144266f54992SEvan Quan uint32_t MetricsCounter; 1443ce81151cSLikun Gao 1444ce81151cSLikun Gao uint16_t AvgVoltage[SVI_PLANE_COUNT]; 144566f54992SEvan Quan uint16_t AvgCurrent[SVI_PLANE_COUNT]; 1446ce81151cSLikun Gao 1447ce81151cSLikun Gao uint16_t AverageGfxActivity ; 1448ce81151cSLikun Gao uint16_t AverageUclkActivity ; 1449ce81151cSLikun Gao uint16_t Vcn0ActivityPercentage ; 1450ce81151cSLikun Gao uint16_t Vcn1ActivityPercentage ; 1451ce81151cSLikun Gao 1452ce81151cSLikun Gao uint32_t EnergyAccumulator; 1453ce81151cSLikun Gao uint16_t AverageSocketPower; 1454da1acbb1SEvan Quan uint16_t AverageTotalBoardPower; 1455da1acbb1SEvan Quan 1456ce81151cSLikun Gao uint16_t AvgTemperature[TEMP_COUNT]; 14577e5632cdSKenneth Feng uint16_t AvgTemperatureFanIntake; 1458ce81151cSLikun Gao 1459ce81151cSLikun Gao uint8_t PcieRate ; 1460ce81151cSLikun Gao uint8_t PcieWidth ; 1461ce81151cSLikun Gao 1462ce81151cSLikun Gao uint8_t AvgFanPwm; 1463ce81151cSLikun Gao uint8_t Padding[1]; 1464ce81151cSLikun Gao uint16_t AvgFanRpm; 1465ce81151cSLikun Gao 1466ce81151cSLikun Gao 1467ce81151cSLikun Gao uint8_t ThrottlingPercentage[THROTTLER_COUNT]; 1468*d522ca27SKenneth Feng uint8_t VmaxThrottlingPercentage; 1469*d522ca27SKenneth Feng uint8_t Padding1[3]; 1470ce81151cSLikun Gao 1471ce81151cSLikun Gao //metrics for D3hot entry/exit and driver ARM msgs 1472ce81151cSLikun Gao uint32_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; 1473ce81151cSLikun Gao uint32_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT]; 1474ce81151cSLikun Gao uint32_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT]; 1475ce81151cSLikun Gao 1476ce81151cSLikun Gao uint16_t ApuSTAPMSmartShiftLimit; 1477ce81151cSLikun Gao uint16_t ApuSTAPMLimit; 1478ce81151cSLikun Gao uint16_t AvgApuSocketPower; 1479ce81151cSLikun Gao 1480ce81151cSLikun Gao uint16_t AverageUclkActivity_MAX; 1481ce81151cSLikun Gao 1482ce81151cSLikun Gao uint32_t PublicSerialNumberLower; 1483ce81151cSLikun Gao uint32_t PublicSerialNumberUpper; 1484ce81151cSLikun Gao 1485ce81151cSLikun Gao } SmuMetrics_t; 1486ce81151cSLikun Gao 1487ce81151cSLikun Gao typedef struct { 1488ce81151cSLikun Gao SmuMetrics_t SmuMetrics; 1489*d522ca27SKenneth Feng uint32_t Spare[29]; 1490ce81151cSLikun Gao 1491ce81151cSLikun Gao // Padding - ignore 1492ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1493ce81151cSLikun Gao } SmuMetricsExternal_t; 1494ce81151cSLikun Gao 1495ce81151cSLikun Gao typedef struct { 1496ce81151cSLikun Gao uint8_t WmSetting; 1497ce81151cSLikun Gao uint8_t Flags; 1498ce81151cSLikun Gao uint8_t Padding[2]; 1499ce81151cSLikun Gao 1500ce81151cSLikun Gao } WatermarkRowGeneric_t; 1501ce81151cSLikun Gao 1502ce81151cSLikun Gao #define NUM_WM_RANGES 4 1503ce81151cSLikun Gao 1504ce81151cSLikun Gao typedef enum { 1505ce81151cSLikun Gao WATERMARKS_CLOCK_RANGE = 0, 1506ce81151cSLikun Gao WATERMARKS_DUMMY_PSTATE, 1507ce81151cSLikun Gao WATERMARKS_MALL, 1508ce81151cSLikun Gao WATERMARKS_COUNT, 1509ce81151cSLikun Gao } WATERMARKS_FLAGS_e; 1510ce81151cSLikun Gao 1511ce81151cSLikun Gao typedef struct { 1512ce81151cSLikun Gao // Watermarks 1513ce81151cSLikun Gao WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES]; 1514ce81151cSLikun Gao } Watermarks_t; 1515ce81151cSLikun Gao 1516ce81151cSLikun Gao typedef struct { 1517ce81151cSLikun Gao Watermarks_t Watermarks; 1518ce81151cSLikun Gao uint32_t Spare[16]; 1519ce81151cSLikun Gao 1520ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1521ce81151cSLikun Gao } WatermarksExternal_t; 1522ce81151cSLikun Gao 1523ce81151cSLikun Gao typedef struct { 1524ce81151cSLikun Gao uint16_t avgPsmCount[214]; 1525ce81151cSLikun Gao uint16_t minPsmCount[214]; 1526ce81151cSLikun Gao float avgPsmVoltage[214]; 1527ce81151cSLikun Gao float minPsmVoltage[214]; 1528ce81151cSLikun Gao } AvfsDebugTable_t; 1529ce81151cSLikun Gao 1530ce81151cSLikun Gao typedef struct { 1531ce81151cSLikun Gao AvfsDebugTable_t AvfsDebugTable; 1532ce81151cSLikun Gao 1533ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1534ce81151cSLikun Gao } AvfsDebugTableExternal_t; 1535ce81151cSLikun Gao 1536ce81151cSLikun Gao 1537ce81151cSLikun Gao typedef struct { 1538ce81151cSLikun Gao uint8_t Gfx_ActiveHystLimit; 1539ce81151cSLikun Gao uint8_t Gfx_IdleHystLimit; 1540ce81151cSLikun Gao uint8_t Gfx_FPS; 1541ce81151cSLikun Gao uint8_t Gfx_MinActiveFreqType; 1542ce81151cSLikun Gao uint8_t Gfx_BoosterFreqType; 1543ce81151cSLikun Gao uint8_t PaddingGfx; 1544ce81151cSLikun Gao uint16_t Gfx_MinActiveFreq; // MHz 1545ce81151cSLikun Gao uint16_t Gfx_BoosterFreq; // MHz 1546ce81151cSLikun Gao uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms 1547ce81151cSLikun Gao uint32_t Gfx_PD_Data_limit_a; // Q16 1548ce81151cSLikun Gao uint32_t Gfx_PD_Data_limit_b; // Q16 1549ce81151cSLikun Gao uint32_t Gfx_PD_Data_limit_c; // Q16 1550ce81151cSLikun Gao uint32_t Gfx_PD_Data_error_coeff; // Q16 1551ce81151cSLikun Gao uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 1552ce81151cSLikun Gao 1553ce81151cSLikun Gao uint8_t Fclk_ActiveHystLimit; 1554ce81151cSLikun Gao uint8_t Fclk_IdleHystLimit; 1555ce81151cSLikun Gao uint8_t Fclk_FPS; 1556ce81151cSLikun Gao uint8_t Fclk_MinActiveFreqType; 1557ce81151cSLikun Gao uint8_t Fclk_BoosterFreqType; 1558ce81151cSLikun Gao uint8_t PaddingFclk; 1559ce81151cSLikun Gao uint16_t Fclk_MinActiveFreq; // MHz 1560ce81151cSLikun Gao uint16_t Fclk_BoosterFreq; // MHz 1561ce81151cSLikun Gao uint16_t Fclk_PD_Data_time_constant; // Time constant of PD controller in ms 1562ce81151cSLikun Gao uint32_t Fclk_PD_Data_limit_a; // Q16 1563ce81151cSLikun Gao uint32_t Fclk_PD_Data_limit_b; // Q16 1564ce81151cSLikun Gao uint32_t Fclk_PD_Data_limit_c; // Q16 1565ce81151cSLikun Gao uint32_t Fclk_PD_Data_error_coeff; // Q16 1566ce81151cSLikun Gao uint32_t Fclk_PD_Data_error_rate_coeff; // Q16 1567ce81151cSLikun Gao 1568ce81151cSLikun Gao uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16 1569ce81151cSLikun Gao uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS]; 1570ce81151cSLikun Gao uint8_t Mem_DownHystLimit[NUM_UCLK_DPM_LEVELS]; 1571ce81151cSLikun Gao uint16_t Mem_Fps; 1572ce81151cSLikun Gao uint8_t padding[2]; 1573ce81151cSLikun Gao 1574ce81151cSLikun Gao } DpmActivityMonitorCoeffInt_t; 1575ce81151cSLikun Gao 1576ce81151cSLikun Gao 1577ce81151cSLikun Gao typedef struct { 1578ce81151cSLikun Gao DpmActivityMonitorCoeffInt_t DpmActivityMonitorCoeffInt; 1579ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1580ce81151cSLikun Gao } DpmActivityMonitorCoeffIntExternal_t; 1581ce81151cSLikun Gao 1582ce81151cSLikun Gao 1583ce81151cSLikun Gao 1584ce81151cSLikun Gao // Workload bits 1585ce81151cSLikun Gao #define WORKLOAD_PPLIB_DEFAULT_BIT 0 1586ce81151cSLikun Gao #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 1587ce81151cSLikun Gao #define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 1588ce81151cSLikun Gao #define WORKLOAD_PPLIB_VIDEO_BIT 3 1589ce81151cSLikun Gao #define WORKLOAD_PPLIB_VR_BIT 4 1590ce81151cSLikun Gao #define WORKLOAD_PPLIB_COMPUTE_BIT 5 1591ce81151cSLikun Gao #define WORKLOAD_PPLIB_CUSTOM_BIT 6 1592ce81151cSLikun Gao #define WORKLOAD_PPLIB_WINDOW_3D_BIT 7 1593ce81151cSLikun Gao #define WORKLOAD_PPLIB_COUNT 8 1594ce81151cSLikun Gao 1595ce81151cSLikun Gao 1596ce81151cSLikun Gao // These defines are used with the following messages: 1597ce81151cSLikun Gao // SMC_MSG_TransferTableDram2Smu 1598ce81151cSLikun Gao // SMC_MSG_TransferTableSmu2Dram 1599ce81151cSLikun Gao 1600ce81151cSLikun Gao // Table transfer status 1601ce81151cSLikun Gao #define TABLE_TRANSFER_OK 0x0 1602ce81151cSLikun Gao #define TABLE_TRANSFER_FAILED 0xFF 1603ce81151cSLikun Gao #define TABLE_TRANSFER_PENDING 0xAB 1604ce81151cSLikun Gao 1605ce81151cSLikun Gao // Table types 1606ce81151cSLikun Gao #define TABLE_PPTABLE 0 1607ce81151cSLikun Gao #define TABLE_COMBO_PPTABLE 1 1608ce81151cSLikun Gao #define TABLE_WATERMARKS 2 1609ce81151cSLikun Gao #define TABLE_AVFS_PSM_DEBUG 3 1610ce81151cSLikun Gao #define TABLE_PMSTATUSLOG 4 1611ce81151cSLikun Gao #define TABLE_SMU_METRICS 5 1612ce81151cSLikun Gao #define TABLE_DRIVER_SMU_CONFIG 6 1613ce81151cSLikun Gao #define TABLE_ACTIVITY_MONITOR_COEFF 7 1614ce81151cSLikun Gao #define TABLE_OVERDRIVE 8 1615ce81151cSLikun Gao #define TABLE_I2C_COMMANDS 9 1616ce81151cSLikun Gao #define TABLE_DRIVER_INFO 10 1617ce81151cSLikun Gao #define TABLE_ECCINFO 11 1618ce81151cSLikun Gao #define TABLE_COUNT 12 1619ce81151cSLikun Gao 1620ce81151cSLikun Gao //IH Interupt ID 1621ce81151cSLikun Gao #define IH_INTERRUPT_ID_TO_DRIVER 0xFE 1622ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_BACO 0x2 1623ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_AC 0x3 1624ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_DC 0x4 1625ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 0x5 1626ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 0x6 1627ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING 0x7 16287e5632cdSKenneth Feng #define IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL 0x8 16297e5632cdSKenneth Feng #define IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY 0x9 1630ce81151cSLikun Gao 1631ce81151cSLikun Gao #endif 1632