1ce81151cSLikun Gao /* 2ce81151cSLikun Gao * Copyright 2021 Advanced Micro Devices, Inc. 3ce81151cSLikun Gao * 4ce81151cSLikun Gao * Permission is hereby granted, free of charge, to any person obtaining a 5ce81151cSLikun Gao * copy of this software and associated documentation files (the "Software"), 6ce81151cSLikun Gao * to deal in the Software without restriction, including without limitation 7ce81151cSLikun Gao * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8ce81151cSLikun Gao * and/or sell copies of the Software, and to permit persons to whom the 9ce81151cSLikun Gao * Software is furnished to do so, subject to the following conditions: 10ce81151cSLikun Gao * 11ce81151cSLikun Gao * The above copyright notice and this permission notice shall be included in 12ce81151cSLikun Gao * all copies or substantial portions of the Software. 13ce81151cSLikun Gao * 14ce81151cSLikun Gao * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15ce81151cSLikun Gao * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16ce81151cSLikun Gao * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17ce81151cSLikun Gao * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18ce81151cSLikun Gao * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19ce81151cSLikun Gao * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20ce81151cSLikun Gao * OTHER DEALINGS IN THE SOFTWARE. 21ce81151cSLikun Gao * 22ce81151cSLikun Gao */ 23ce81151cSLikun Gao 24ce81151cSLikun Gao #ifndef SMU13_DRIVER_IF_V13_0_0_H 25ce81151cSLikun Gao #define SMU13_DRIVER_IF_V13_0_0_H 26ce81151cSLikun Gao 27*9661bf68SLijo Lazar #define SMU13_0_0_DRIVER_IF_VERSION 0x32 28*9661bf68SLijo Lazar 29ce81151cSLikun Gao //Increment this version if SkuTable_t or BoardTable_t change 307e5632cdSKenneth Feng #define PPTABLE_VERSION 0x26 31ce81151cSLikun Gao 32ce81151cSLikun Gao #define NUM_GFXCLK_DPM_LEVELS 16 33ce81151cSLikun Gao #define NUM_SOCCLK_DPM_LEVELS 8 34ce81151cSLikun Gao #define NUM_MP0CLK_DPM_LEVELS 2 35ce81151cSLikun Gao #define NUM_DCLK_DPM_LEVELS 8 36ce81151cSLikun Gao #define NUM_VCLK_DPM_LEVELS 8 37ce81151cSLikun Gao #define NUM_DISPCLK_DPM_LEVELS 8 38ce81151cSLikun Gao #define NUM_DPPCLK_DPM_LEVELS 8 39ce81151cSLikun Gao #define NUM_DPREFCLK_DPM_LEVELS 8 40ce81151cSLikun Gao #define NUM_DCFCLK_DPM_LEVELS 8 41ce81151cSLikun Gao #define NUM_DTBCLK_DPM_LEVELS 8 42ce81151cSLikun Gao #define NUM_UCLK_DPM_LEVELS 4 43ce81151cSLikun Gao #define NUM_LINK_LEVELS 3 44ce81151cSLikun Gao #define NUM_FCLK_DPM_LEVELS 8 45ce81151cSLikun Gao #define NUM_OD_FAN_MAX_POINTS 6 46ce81151cSLikun Gao 47ce81151cSLikun Gao // Feature Control Defines 48ce81151cSLikun Gao #define FEATURE_FW_DATA_READ_BIT 0 49ce81151cSLikun Gao #define FEATURE_DPM_GFXCLK_BIT 1 50ce81151cSLikun Gao #define FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT 2 51ce81151cSLikun Gao #define FEATURE_DPM_UCLK_BIT 3 52ce81151cSLikun Gao #define FEATURE_DPM_FCLK_BIT 4 53ce81151cSLikun Gao #define FEATURE_DPM_SOCCLK_BIT 5 54ce81151cSLikun Gao #define FEATURE_DPM_MP0CLK_BIT 6 55ce81151cSLikun Gao #define FEATURE_DPM_LINK_BIT 7 56ce81151cSLikun Gao #define FEATURE_DPM_DCN_BIT 8 57ce81151cSLikun Gao #define FEATURE_VMEMP_SCALING_BIT 9 58ce81151cSLikun Gao #define FEATURE_VDDIO_MEM_SCALING_BIT 10 59ce81151cSLikun Gao #define FEATURE_DS_GFXCLK_BIT 11 60ce81151cSLikun Gao #define FEATURE_DS_SOCCLK_BIT 12 61ce81151cSLikun Gao #define FEATURE_DS_FCLK_BIT 13 62ce81151cSLikun Gao #define FEATURE_DS_LCLK_BIT 14 63ce81151cSLikun Gao #define FEATURE_DS_DCFCLK_BIT 15 64ce81151cSLikun Gao #define FEATURE_DS_UCLK_BIT 16 65ce81151cSLikun Gao #define FEATURE_GFX_ULV_BIT 17 66ce81151cSLikun Gao #define FEATURE_FW_DSTATE_BIT 18 67ce81151cSLikun Gao #define FEATURE_GFXOFF_BIT 19 68ce81151cSLikun Gao #define FEATURE_BACO_BIT 20 69ce81151cSLikun Gao #define FEATURE_MM_DPM_BIT 21 70ce81151cSLikun Gao #define FEATURE_SOC_MPCLK_DS_BIT 22 71ce81151cSLikun Gao #define FEATURE_BACO_MPCLK_DS_BIT 23 72ce81151cSLikun Gao #define FEATURE_THROTTLERS_BIT 24 73ce81151cSLikun Gao #define FEATURE_SMARTSHIFT_BIT 25 74ce81151cSLikun Gao #define FEATURE_GTHR_BIT 26 75ce81151cSLikun Gao #define FEATURE_ACDC_BIT 27 76ce81151cSLikun Gao #define FEATURE_VR0HOT_BIT 28 77ce81151cSLikun Gao #define FEATURE_FW_CTF_BIT 29 78ce81151cSLikun Gao #define FEATURE_FAN_CONTROL_BIT 30 79ce81151cSLikun Gao #define FEATURE_GFX_DCS_BIT 31 80ce81151cSLikun Gao #define FEATURE_GFX_READ_MARGIN_BIT 32 81ce81151cSLikun Gao #define FEATURE_LED_DISPLAY_BIT 33 82ce81151cSLikun Gao #define FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT 34 83ce81151cSLikun Gao #define FEATURE_OUT_OF_BAND_MONITOR_BIT 35 84ce81151cSLikun Gao #define FEATURE_OPTIMIZED_VMIN_BIT 36 85ce81151cSLikun Gao #define FEATURE_GFX_IMU_BIT 37 86ce81151cSLikun Gao #define FEATURE_BOOT_TIME_CAL_BIT 38 87ce81151cSLikun Gao #define FEATURE_GFX_PCC_DFLL_BIT 39 88ce81151cSLikun Gao #define FEATURE_SOC_CG_BIT 40 89ce81151cSLikun Gao #define FEATURE_DF_CSTATE_BIT 41 90ce81151cSLikun Gao #define FEATURE_GFX_EDC_BIT 42 91ce81151cSLikun Gao #define FEATURE_BOOT_POWER_OPT_BIT 43 92ce81151cSLikun Gao #define FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT 44 93ce81151cSLikun Gao #define FEATURE_DS_VCN_BIT 45 94ce81151cSLikun Gao #define FEATURE_BACO_CG_BIT 46 95ce81151cSLikun Gao #define FEATURE_MEM_TEMP_READ_BIT 47 96ce81151cSLikun Gao #define FEATURE_ATHUB_MMHUB_PG_BIT 48 97ce81151cSLikun Gao #define FEATURE_SOC_PCC_BIT 49 981f3dfde4SEvan Quan #define FEATURE_EDC_PWRBRK_BIT 50 99ce81151cSLikun Gao #define FEATURE_SPARE_51_BIT 51 100ce81151cSLikun Gao #define FEATURE_SPARE_52_BIT 52 101ce81151cSLikun Gao #define FEATURE_SPARE_53_BIT 53 102ce81151cSLikun Gao #define FEATURE_SPARE_54_BIT 54 103ce81151cSLikun Gao #define FEATURE_SPARE_55_BIT 55 104ce81151cSLikun Gao #define FEATURE_SPARE_56_BIT 56 105ce81151cSLikun Gao #define FEATURE_SPARE_57_BIT 57 106ce81151cSLikun Gao #define FEATURE_SPARE_58_BIT 58 107ce81151cSLikun Gao #define FEATURE_SPARE_59_BIT 59 108ce81151cSLikun Gao #define FEATURE_SPARE_60_BIT 60 109ce81151cSLikun Gao #define FEATURE_SPARE_61_BIT 61 110ce81151cSLikun Gao #define FEATURE_SPARE_62_BIT 62 111ce81151cSLikun Gao #define FEATURE_SPARE_63_BIT 63 112ce81151cSLikun Gao #define NUM_FEATURES 64 113ce81151cSLikun Gao 1147e5632cdSKenneth Feng #define ALLOWED_FEATURE_CTRL_DEFAULT 0xFFFFFFFFFFFFFFFFULL 1157e5632cdSKenneth Feng #define ALLOWED_FEATURE_CTRL_SCPM ((1 << FEATURE_DPM_GFXCLK_BIT) | \ 1167e5632cdSKenneth Feng (1 << FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | \ 1177e5632cdSKenneth Feng (1 << FEATURE_DPM_UCLK_BIT) | \ 1187e5632cdSKenneth Feng (1 << FEATURE_DPM_FCLK_BIT) | \ 1197e5632cdSKenneth Feng (1 << FEATURE_DPM_SOCCLK_BIT) | \ 1207e5632cdSKenneth Feng (1 << FEATURE_DPM_MP0CLK_BIT) | \ 1217e5632cdSKenneth Feng (1 << FEATURE_DPM_LINK_BIT) | \ 1227e5632cdSKenneth Feng (1 << FEATURE_DPM_DCN_BIT) | \ 1237e5632cdSKenneth Feng (1 << FEATURE_DS_GFXCLK_BIT) | \ 1247e5632cdSKenneth Feng (1 << FEATURE_DS_SOCCLK_BIT) | \ 1257e5632cdSKenneth Feng (1 << FEATURE_DS_FCLK_BIT) | \ 1267e5632cdSKenneth Feng (1 << FEATURE_DS_LCLK_BIT) | \ 1277e5632cdSKenneth Feng (1 << FEATURE_DS_DCFCLK_BIT) | \ 1282bce0f9bSEvan Quan (1 << FEATURE_DS_UCLK_BIT) | \ 1292bce0f9bSEvan Quan (1ULL << FEATURE_DS_VCN_BIT)) 1307e5632cdSKenneth Feng 131ce81151cSLikun Gao //For use with feature control messages 132ce81151cSLikun Gao typedef enum { 133ce81151cSLikun Gao FEATURE_PWR_ALL, 134ce81151cSLikun Gao FEATURE_PWR_S5, 135ce81151cSLikun Gao FEATURE_PWR_BACO, 136ce81151cSLikun Gao FEATURE_PWR_SOC, 137ce81151cSLikun Gao FEATURE_PWR_GFX, 138ce81151cSLikun Gao FEATURE_PWR_DOMAIN_COUNT, 139ce81151cSLikun Gao } FEATURE_PWR_DOMAIN_e; 140ce81151cSLikun Gao 141ce81151cSLikun Gao 142ce81151cSLikun Gao // Debug Overrides Bitmask 143ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000001 144ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK 0x00000002 145ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK 0x00000004 146ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK 0x00000008 147ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x00000010 148ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_VCN_PG 0x00000020 149ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_FMAX_VMAX 0x00000040 150ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS 0x00000080 151ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK 0x00000100 152ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_DFLL 0x00000200 153ce81151cSLikun Gao #define DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE 0x00000400 154ce81151cSLikun Gao #define DEBUG_OVERRIDE_DFLL_MASTER_MODE 0x00000800 1557e5632cdSKenneth Feng #define DEBUG_OVERRIDE_ENABLE_PROFILING_MODE 0x00001000 156ce81151cSLikun Gao 157ce81151cSLikun Gao // VR Mapping Bit Defines 158ce81151cSLikun Gao #define VR_MAPPING_VR_SELECT_MASK 0x01 159ce81151cSLikun Gao #define VR_MAPPING_VR_SELECT_SHIFT 0x00 160ce81151cSLikun Gao 161ce81151cSLikun Gao #define VR_MAPPING_PLANE_SELECT_MASK 0x02 162ce81151cSLikun Gao #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 163ce81151cSLikun Gao 164ce81151cSLikun Gao // PSI Bit Defines 165ce81151cSLikun Gao #define PSI_SEL_VR0_PLANE0_PSI0 0x01 166ce81151cSLikun Gao #define PSI_SEL_VR0_PLANE0_PSI1 0x02 167ce81151cSLikun Gao #define PSI_SEL_VR0_PLANE1_PSI0 0x04 168ce81151cSLikun Gao #define PSI_SEL_VR0_PLANE1_PSI1 0x08 169ce81151cSLikun Gao #define PSI_SEL_VR1_PLANE0_PSI0 0x10 170ce81151cSLikun Gao #define PSI_SEL_VR1_PLANE0_PSI1 0x20 171ce81151cSLikun Gao #define PSI_SEL_VR1_PLANE1_PSI0 0x40 172ce81151cSLikun Gao #define PSI_SEL_VR1_PLANE1_PSI1 0x80 173ce81151cSLikun Gao 174ce81151cSLikun Gao typedef enum { 175ce81151cSLikun Gao SVI_PSI_0, // Full phase count (default) 176ce81151cSLikun Gao SVI_PSI_1, // Phase count 1st level 177ce81151cSLikun Gao SVI_PSI_2, // Phase count 2nd level 178ce81151cSLikun Gao SVI_PSI_3, // Single phase operation + active diode emulation 179ce81151cSLikun Gao SVI_PSI_4, // Single phase operation + passive diode emulation *optional* 180ce81151cSLikun Gao SVI_PSI_5, // Reserved 181ce81151cSLikun Gao SVI_PSI_6, // Power down to 0V (voltage regulation disabled) 182ce81151cSLikun Gao SVI_PSI_7, // Automated phase shedding and diode emulation 183ce81151cSLikun Gao } SVI_PSI_e; 184ce81151cSLikun Gao 185ce81151cSLikun Gao // Throttler Control/Status Bits 186ce81151cSLikun Gao #define THROTTLER_TEMP_EDGE_BIT 0 187ce81151cSLikun Gao #define THROTTLER_TEMP_HOTSPOT_BIT 1 188ce81151cSLikun Gao #define THROTTLER_TEMP_HOTSPOT_G_BIT 2 189ce81151cSLikun Gao #define THROTTLER_TEMP_HOTSPOT_M_BIT 3 190ce81151cSLikun Gao #define THROTTLER_TEMP_MEM_BIT 4 191ce81151cSLikun Gao #define THROTTLER_TEMP_VR_GFX_BIT 5 192ce81151cSLikun Gao #define THROTTLER_TEMP_VR_MEM0_BIT 6 193ce81151cSLikun Gao #define THROTTLER_TEMP_VR_MEM1_BIT 7 194ce81151cSLikun Gao #define THROTTLER_TEMP_VR_SOC_BIT 8 195ce81151cSLikun Gao #define THROTTLER_TEMP_VR_U_BIT 9 196ce81151cSLikun Gao #define THROTTLER_TEMP_LIQUID0_BIT 10 197ce81151cSLikun Gao #define THROTTLER_TEMP_LIQUID1_BIT 11 198ce81151cSLikun Gao #define THROTTLER_TEMP_PLX_BIT 12 199ce81151cSLikun Gao #define THROTTLER_TDC_GFX_BIT 13 200ce81151cSLikun Gao #define THROTTLER_TDC_SOC_BIT 14 201ce81151cSLikun Gao #define THROTTLER_TDC_U_BIT 15 202ce81151cSLikun Gao #define THROTTLER_PPT0_BIT 16 203ce81151cSLikun Gao #define THROTTLER_PPT1_BIT 17 204ce81151cSLikun Gao #define THROTTLER_PPT2_BIT 18 205ce81151cSLikun Gao #define THROTTLER_PPT3_BIT 19 206ce81151cSLikun Gao #define THROTTLER_FIT_BIT 20 207ce81151cSLikun Gao #define THROTTLER_GFX_APCC_PLUS_BIT 21 208ce81151cSLikun Gao #define THROTTLER_COUNT 22 209ce81151cSLikun Gao 210ce81151cSLikun Gao // FW DState Features Control Bits 211ce81151cSLikun Gao #define FW_DSTATE_SOC_ULV_BIT 0 212ce81151cSLikun Gao #define FW_DSTATE_G6_HSR_BIT 1 213ce81151cSLikun Gao #define FW_DSTATE_G6_PHY_VMEMP_OFF_BIT 2 214ce81151cSLikun Gao #define FW_DSTATE_SMN_DS_BIT 3 215ce81151cSLikun Gao #define FW_DSTATE_MP1_WHISPER_MODE_BIT 4 216ce81151cSLikun Gao #define FW_DSTATE_SOC_LIV_MIN_BIT 5 217ce81151cSLikun Gao #define FW_DSTATE_SOC_PLL_PWRDN_BIT 6 218ce81151cSLikun Gao #define FW_DSTATE_MEM_PLL_PWRDN_BIT 7 219ce81151cSLikun Gao #define FW_DSTATE_MALL_ALLOC_BIT 8 220ce81151cSLikun Gao #define FW_DSTATE_MEM_PSI_BIT 9 221ce81151cSLikun Gao #define FW_DSTATE_HSR_NON_STROBE_BIT 10 222ce81151cSLikun Gao #define FW_DSTATE_MP0_ENTER_WFI_BIT 11 223ce81151cSLikun Gao #define FW_DSTATE_U_ULV_BIT 12 224ce81151cSLikun Gao #define FW_DSTATE_MALL_FLUSH_BIT 13 225ce81151cSLikun Gao #define FW_DSTATE_SOC_PSI_BIT 14 226ce81151cSLikun Gao #define FW_DSTATE_U_PSI_BIT 15 227ce81151cSLikun Gao #define FW_DSTATE_UCP_DS_BIT 16 228ce81151cSLikun Gao #define FW_DSTATE_CSRCLK_DS_BIT 17 229ce81151cSLikun Gao #define FW_DSTATE_MMHUB_INTERLOCK_BIT 18 230ce81151cSLikun Gao #define FW_DSTATE_D0i3_2_QUIET_FW_BIT 19 231ce81151cSLikun Gao #define FW_DSTATE_CLDO_PRG_BIT 20 232ce81151cSLikun Gao #define FW_DSTATE_DF_PLL_PWRDN_BIT 21 233ce81151cSLikun Gao #define FW_DSTATE_U_LOW_PWR_MODE_EN_BIT 22 234ce81151cSLikun Gao #define FW_DSTATE_GFX_PSI6_BIT 23 235ce81151cSLikun Gao #define FW_DSTATE_GFX_VR_PWR_STAGE_BIT 24 236ce81151cSLikun Gao 237ce81151cSLikun Gao //LED Display Mask & Control Bits 238ce81151cSLikun Gao #define LED_DISPLAY_GFX_DPM_BIT 0 239ce81151cSLikun Gao #define LED_DISPLAY_PCIE_BIT 1 240ce81151cSLikun Gao #define LED_DISPLAY_ERROR_BIT 2 241ce81151cSLikun Gao 242ce81151cSLikun Gao 243ce81151cSLikun Gao #define MEM_TEMP_READ_OUT_OF_BAND_BIT 0 244ce81151cSLikun Gao #define MEM_TEMP_READ_IN_BAND_REFRESH_BIT 1 245ce81151cSLikun Gao #define MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT 2 246ce81151cSLikun Gao 247ce81151cSLikun Gao typedef enum { 248ce81151cSLikun Gao SMARTSHIFT_VERSION_1, 249ce81151cSLikun Gao SMARTSHIFT_VERSION_2, 250ce81151cSLikun Gao SMARTSHIFT_VERSION_3, 251ce81151cSLikun Gao } SMARTSHIFT_VERSION_e; 252ce81151cSLikun Gao 253ce81151cSLikun Gao typedef enum { 254ce81151cSLikun Gao FOPT_CALC_AC_CALC_DC, 255ce81151cSLikun Gao FOPT_PPTABLE_AC_CALC_DC, 256ce81151cSLikun Gao FOPT_CALC_AC_PPTABLE_DC, 257ce81151cSLikun Gao FOPT_PPTABLE_AC_PPTABLE_DC, 258ce81151cSLikun Gao } FOPT_CALC_e; 259ce81151cSLikun Gao 260ce81151cSLikun Gao typedef enum { 261ce81151cSLikun Gao DRAM_BIT_WIDTH_DISABLED = 0, 262ce81151cSLikun Gao DRAM_BIT_WIDTH_X_8 = 8, 263ce81151cSLikun Gao DRAM_BIT_WIDTH_X_16 = 16, 264ce81151cSLikun Gao DRAM_BIT_WIDTH_X_32 = 32, 265ce81151cSLikun Gao DRAM_BIT_WIDTH_X_64 = 64, 266ce81151cSLikun Gao DRAM_BIT_WIDTH_X_128 = 128, 267ce81151cSLikun Gao DRAM_BIT_WIDTH_COUNT, 268ce81151cSLikun Gao } DRAM_BIT_WIDTH_TYPE_e; 269ce81151cSLikun Gao 270ce81151cSLikun Gao //I2C Interface 271ce81151cSLikun Gao #define NUM_I2C_CONTROLLERS 8 272ce81151cSLikun Gao 273ce81151cSLikun Gao #define I2C_CONTROLLER_ENABLED 1 274ce81151cSLikun Gao #define I2C_CONTROLLER_DISABLED 0 275ce81151cSLikun Gao 276ce81151cSLikun Gao #define MAX_SW_I2C_COMMANDS 24 277ce81151cSLikun Gao 278ce81151cSLikun Gao typedef enum { 279ce81151cSLikun Gao I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0 280ce81151cSLikun Gao I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1 281ce81151cSLikun Gao I2C_CONTROLLER_PORT_COUNT, 282ce81151cSLikun Gao } I2cControllerPort_e; 283ce81151cSLikun Gao 284ce81151cSLikun Gao typedef enum { 285ce81151cSLikun Gao I2C_CONTROLLER_NAME_VR_GFX = 0, 286ce81151cSLikun Gao I2C_CONTROLLER_NAME_VR_SOC, 287ce81151cSLikun Gao I2C_CONTROLLER_NAME_VR_VMEMP, 288ce81151cSLikun Gao I2C_CONTROLLER_NAME_VR_VDDIO, 289ce81151cSLikun Gao I2C_CONTROLLER_NAME_LIQUID0, 290ce81151cSLikun Gao I2C_CONTROLLER_NAME_LIQUID1, 291ce81151cSLikun Gao I2C_CONTROLLER_NAME_PLX, 2927e5632cdSKenneth Feng I2C_CONTROLLER_NAME_FAN_INTAKE, 293ce81151cSLikun Gao I2C_CONTROLLER_NAME_COUNT, 294ce81151cSLikun Gao } I2cControllerName_e; 295ce81151cSLikun Gao 296ce81151cSLikun Gao typedef enum { 297ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 298ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_VR_GFX, 299ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_VR_SOC, 300ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_VR_VMEMP, 301ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_VR_VDDIO, 302ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_LIQUID0, 303ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_LIQUID1, 304ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_PLX, 3057e5632cdSKenneth Feng I2C_CONTROLLER_THROTTLER_FAN_INTAKE, 306ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_INA3221, 307ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_COUNT, 308ce81151cSLikun Gao } I2cControllerThrottler_e; 309ce81151cSLikun Gao 310ce81151cSLikun Gao typedef enum { 311ce81151cSLikun Gao I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5, 312ce81151cSLikun Gao I2C_CONTROLLER_PROTOCOL_VR_IR35217, 3137e5632cdSKenneth Feng I2C_CONTROLLER_PROTOCOL_TMP_MAX31875, 314ce81151cSLikun Gao I2C_CONTROLLER_PROTOCOL_INA3221, 315ce81151cSLikun Gao I2C_CONTROLLER_PROTOCOL_COUNT, 316ce81151cSLikun Gao } I2cControllerProtocol_e; 317ce81151cSLikun Gao 318ce81151cSLikun Gao typedef struct { 319ce81151cSLikun Gao uint8_t Enabled; 320ce81151cSLikun Gao uint8_t Speed; 321ce81151cSLikun Gao uint8_t SlaveAddress; 322ce81151cSLikun Gao uint8_t ControllerPort; 323ce81151cSLikun Gao uint8_t ControllerName; 324ce81151cSLikun Gao uint8_t ThermalThrotter; 325ce81151cSLikun Gao uint8_t I2cProtocol; 326ce81151cSLikun Gao uint8_t PaddingConfig; 327ce81151cSLikun Gao } I2cControllerConfig_t; 328ce81151cSLikun Gao 329ce81151cSLikun Gao typedef enum { 330ce81151cSLikun Gao I2C_PORT_SVD_SCL = 0, 331ce81151cSLikun Gao I2C_PORT_GPIO, 332ce81151cSLikun Gao } I2cPort_e; 333ce81151cSLikun Gao 334ce81151cSLikun Gao typedef enum { 335ce81151cSLikun Gao I2C_SPEED_FAST_50K = 0, //50 Kbits/s 336ce81151cSLikun Gao I2C_SPEED_FAST_100K, //100 Kbits/s 337ce81151cSLikun Gao I2C_SPEED_FAST_400K, //400 Kbits/s 338ce81151cSLikun Gao I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 339ce81151cSLikun Gao I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 340ce81151cSLikun Gao I2C_SPEED_HIGH_2M, //2.3 Mbits/s 341ce81151cSLikun Gao I2C_SPEED_COUNT, 342ce81151cSLikun Gao } I2cSpeed_e; 343ce81151cSLikun Gao 344ce81151cSLikun Gao typedef enum { 345ce81151cSLikun Gao I2C_CMD_READ = 0, 346ce81151cSLikun Gao I2C_CMD_WRITE, 347ce81151cSLikun Gao I2C_CMD_COUNT, 348ce81151cSLikun Gao } I2cCmdType_e; 349ce81151cSLikun Gao 350ce81151cSLikun Gao #define CMDCONFIG_STOP_BIT 0 351ce81151cSLikun Gao #define CMDCONFIG_RESTART_BIT 1 352ce81151cSLikun Gao #define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write 353ce81151cSLikun Gao 354ce81151cSLikun Gao #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 355ce81151cSLikun Gao #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 356ce81151cSLikun Gao #define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT) 357ce81151cSLikun Gao 358ce81151cSLikun Gao typedef struct { 359ce81151cSLikun Gao uint8_t ReadWriteData; //Return data for read. Data to send for write 360ce81151cSLikun Gao uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write 361ce81151cSLikun Gao } SwI2cCmd_t; //SW I2C Command Table 362ce81151cSLikun Gao 363ce81151cSLikun Gao typedef struct { 364ce81151cSLikun Gao uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 365ce81151cSLikun Gao uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select 366ce81151cSLikun Gao uint8_t SlaveAddress; //Slave address of device 367ce81151cSLikun Gao uint8_t NumCmds; //Number of commands 368ce81151cSLikun Gao 369ce81151cSLikun Gao SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 370ce81151cSLikun Gao } SwI2cRequest_t; // SW I2C Request Table 371ce81151cSLikun Gao 372ce81151cSLikun Gao typedef struct { 373ce81151cSLikun Gao SwI2cRequest_t SwI2cRequest; 374ce81151cSLikun Gao 375ce81151cSLikun Gao uint32_t Spare[8]; 376ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 377ce81151cSLikun Gao } SwI2cRequestExternal_t; 378ce81151cSLikun Gao 379ce81151cSLikun Gao typedef struct { 380ce81151cSLikun Gao uint64_t mca_umc_status; 381ce81151cSLikun Gao uint64_t mca_umc_addr; 382ce81151cSLikun Gao 383ce81151cSLikun Gao uint16_t ce_count_lo_chip; 384ce81151cSLikun Gao uint16_t ce_count_hi_chip; 385ce81151cSLikun Gao 386ce81151cSLikun Gao uint32_t eccPadding; 387ce81151cSLikun Gao } EccInfo_t; 388ce81151cSLikun Gao 389ce81151cSLikun Gao typedef struct { 390ce81151cSLikun Gao EccInfo_t EccInfo[24]; 391ce81151cSLikun Gao } EccInfoTable_t; 392ce81151cSLikun Gao 393ce81151cSLikun Gao //D3HOT sequences 394ce81151cSLikun Gao typedef enum { 395ce81151cSLikun Gao BACO_SEQUENCE, 396ce81151cSLikun Gao MSR_SEQUENCE, 397ce81151cSLikun Gao BAMACO_SEQUENCE, 398ce81151cSLikun Gao ULPS_SEQUENCE, 399ce81151cSLikun Gao D3HOT_SEQUENCE_COUNT, 400ce81151cSLikun Gao } D3HOTSequence_e; 401ce81151cSLikun Gao 402ce81151cSLikun Gao //This is aligned with RSMU PGFSM Register Mapping 403ce81151cSLikun Gao typedef enum { 404ce81151cSLikun Gao PG_DYNAMIC_MODE = 0, 405ce81151cSLikun Gao PG_STATIC_MODE, 406ce81151cSLikun Gao } PowerGatingMode_e; 407ce81151cSLikun Gao 408ce81151cSLikun Gao //This is aligned with RSMU PGFSM Register Mapping 409ce81151cSLikun Gao typedef enum { 410ce81151cSLikun Gao PG_POWER_DOWN = 0, 411ce81151cSLikun Gao PG_POWER_UP, 412ce81151cSLikun Gao } PowerGatingSettings_e; 413ce81151cSLikun Gao 414ce81151cSLikun Gao typedef struct { 415ce81151cSLikun Gao uint32_t a; // store in IEEE float format in this variable 416ce81151cSLikun Gao uint32_t b; // store in IEEE float format in this variable 417ce81151cSLikun Gao uint32_t c; // store in IEEE float format in this variable 418ce81151cSLikun Gao } QuadraticInt_t; 419ce81151cSLikun Gao 420ce81151cSLikun Gao typedef struct { 421ce81151cSLikun Gao uint32_t m; // store in IEEE float format in this variable 422ce81151cSLikun Gao uint32_t b; // store in IEEE float format in this variable 423ce81151cSLikun Gao } LinearInt_t; 424ce81151cSLikun Gao 425ce81151cSLikun Gao typedef struct { 426ce81151cSLikun Gao uint32_t a; // store in IEEE float format in this variable 427ce81151cSLikun Gao uint32_t b; // store in IEEE float format in this variable 428ce81151cSLikun Gao uint32_t c; // store in IEEE float format in this variable 429ce81151cSLikun Gao } DroopInt_t; 430ce81151cSLikun Gao 431ce81151cSLikun Gao typedef enum { 432ce81151cSLikun Gao DCS_ARCH_DISABLED, 433ce81151cSLikun Gao DCS_ARCH_FADCS, 434ce81151cSLikun Gao DCS_ARCH_ASYNC, 435ce81151cSLikun Gao } DCS_ARCH_e; 436ce81151cSLikun Gao 437ce81151cSLikun Gao //Only Clks that have DPM descriptors are listed here 438ce81151cSLikun Gao typedef enum { 439ce81151cSLikun Gao PPCLK_GFXCLK = 0, 440ce81151cSLikun Gao PPCLK_SOCCLK, 441ce81151cSLikun Gao PPCLK_UCLK, 442ce81151cSLikun Gao PPCLK_FCLK, 443ce81151cSLikun Gao PPCLK_DCLK_0, 444ce81151cSLikun Gao PPCLK_VCLK_0, 445ce81151cSLikun Gao PPCLK_DCLK_1, 446ce81151cSLikun Gao PPCLK_VCLK_1, 447ce81151cSLikun Gao PPCLK_DISPCLK, 448ce81151cSLikun Gao PPCLK_DPPCLK, 449ce81151cSLikun Gao PPCLK_DPREFCLK, 450ce81151cSLikun Gao PPCLK_DCFCLK, 451ce81151cSLikun Gao PPCLK_DTBCLK, 452ce81151cSLikun Gao PPCLK_COUNT, 453ce81151cSLikun Gao } PPCLK_e; 454ce81151cSLikun Gao 455ce81151cSLikun Gao typedef enum { 456ce81151cSLikun Gao VOLTAGE_MODE_PPTABLE = 0, 457ce81151cSLikun Gao VOLTAGE_MODE_FUSES, 458ce81151cSLikun Gao VOLTAGE_MODE_COUNT, 459ce81151cSLikun Gao } VOLTAGE_MODE_e; 460ce81151cSLikun Gao 461ce81151cSLikun Gao 462ce81151cSLikun Gao typedef enum { 463ce81151cSLikun Gao AVFS_VOLTAGE_GFX = 0, 464ce81151cSLikun Gao AVFS_VOLTAGE_SOC, 465ce81151cSLikun Gao AVFS_VOLTAGE_COUNT, 466ce81151cSLikun Gao } AVFS_VOLTAGE_TYPE_e; 467ce81151cSLikun Gao 468ce81151cSLikun Gao typedef enum { 469ce81151cSLikun Gao AVFS_TEMP_COLD = 0, 470ce81151cSLikun Gao AVFS_TEMP_HOT, 471ce81151cSLikun Gao AVFS_TEMP_COUNT, 472ce81151cSLikun Gao } AVFS_TEMP_e; 473ce81151cSLikun Gao 474ce81151cSLikun Gao typedef enum { 475ce81151cSLikun Gao AVFS_D_G, 476ce81151cSLikun Gao AVFS_D_M_B, 477ce81151cSLikun Gao AVFS_D_M_S, 478ce81151cSLikun Gao AVFS_D_COUNT, 479ce81151cSLikun Gao } AVFS_D_e; 480ce81151cSLikun Gao 481ce81151cSLikun Gao typedef enum { 482ce81151cSLikun Gao UCLK_DIV_BY_1 = 0, 483ce81151cSLikun Gao UCLK_DIV_BY_2, 484ce81151cSLikun Gao UCLK_DIV_BY_4, 485ce81151cSLikun Gao UCLK_DIV_BY_8, 486ce81151cSLikun Gao } UCLK_DIV_e; 487ce81151cSLikun Gao 488ce81151cSLikun Gao typedef enum { 489ce81151cSLikun Gao GPIO_INT_POLARITY_ACTIVE_LOW = 0, 490ce81151cSLikun Gao GPIO_INT_POLARITY_ACTIVE_HIGH, 491ce81151cSLikun Gao } GpioIntPolarity_e; 492ce81151cSLikun Gao 493ce81151cSLikun Gao typedef enum { 494ce81151cSLikun Gao PWR_CONFIG_TDP = 0, 495ce81151cSLikun Gao PWR_CONFIG_TGP, 496ce81151cSLikun Gao PWR_CONFIG_TCP_ESTIMATED, 497ce81151cSLikun Gao PWR_CONFIG_TCP_MEASURED, 498ce81151cSLikun Gao } PwrConfig_e; 499ce81151cSLikun Gao 500ce81151cSLikun Gao typedef struct { 501ce81151cSLikun Gao uint8_t Padding; 502ce81151cSLikun Gao uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 503ce81151cSLikun Gao uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 504ce81151cSLikun Gao uint8_t CalculateFopt; // Indication whether FW should calculate Fopt or use values below. Reference FOPT_CALC_e 505ce81151cSLikun Gao LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 506ce81151cSLikun Gao uint32_t Padding3[3]; 507ce81151cSLikun Gao uint16_t Padding4; 508ce81151cSLikun Gao uint16_t FoptimalDc; //Foptimal frequency in DC power mode. 509ce81151cSLikun Gao uint16_t FoptimalAc; //Foptimal frequency in AC power mode. 510ce81151cSLikun Gao uint16_t Padding2; 511ce81151cSLikun Gao } DpmDescriptor_t; 512ce81151cSLikun Gao 513ce81151cSLikun Gao typedef enum { 514ce81151cSLikun Gao PPT_THROTTLER_PPT0, 515ce81151cSLikun Gao PPT_THROTTLER_PPT1, 516ce81151cSLikun Gao PPT_THROTTLER_PPT2, 517ce81151cSLikun Gao PPT_THROTTLER_PPT3, 518ce81151cSLikun Gao PPT_THROTTLER_COUNT 519ce81151cSLikun Gao } PPT_THROTTLER_e; 520ce81151cSLikun Gao 521ce81151cSLikun Gao typedef enum { 522ce81151cSLikun Gao TEMP_EDGE, 523ce81151cSLikun Gao TEMP_HOTSPOT, 524ce81151cSLikun Gao TEMP_HOTSPOT_G, 525ce81151cSLikun Gao TEMP_HOTSPOT_M, 526ce81151cSLikun Gao TEMP_MEM, 527ce81151cSLikun Gao TEMP_VR_GFX, 528ce81151cSLikun Gao TEMP_VR_MEM0, 529ce81151cSLikun Gao TEMP_VR_MEM1, 5302bce0f9bSEvan Quan TEMP_VR_SOC, 531ce81151cSLikun Gao TEMP_VR_U, 532ce81151cSLikun Gao TEMP_LIQUID0, 533ce81151cSLikun Gao TEMP_LIQUID1, 534ce81151cSLikun Gao TEMP_PLX, 535ce81151cSLikun Gao TEMP_COUNT, 536ce81151cSLikun Gao } TEMP_e; 537ce81151cSLikun Gao 538ce81151cSLikun Gao typedef enum { 539ce81151cSLikun Gao TDC_THROTTLER_GFX, 540ce81151cSLikun Gao TDC_THROTTLER_SOC, 541ce81151cSLikun Gao TDC_THROTTLER_U, 542ce81151cSLikun Gao TDC_THROTTLER_COUNT 543ce81151cSLikun Gao } TDC_THROTTLER_e; 544ce81151cSLikun Gao 545ce81151cSLikun Gao typedef enum { 546ce81151cSLikun Gao SVI_PLANE_GFX, 547ce81151cSLikun Gao SVI_PLANE_SOC, 548ce81151cSLikun Gao SVI_PLANE_VMEMP, 549ce81151cSLikun Gao SVI_PLANE_VDDIO_MEM, 550ce81151cSLikun Gao SVI_PLANE_U, 551ce81151cSLikun Gao SVI_PLANE_COUNT, 552ce81151cSLikun Gao } SVI_PLANE_e; 553ce81151cSLikun Gao 554ce81151cSLikun Gao typedef enum { 555ce81151cSLikun Gao PMFW_VOLT_PLANE_GFX, 556ce81151cSLikun Gao PMFW_VOLT_PLANE_SOC, 557ce81151cSLikun Gao PMFW_VOLT_PLANE_COUNT 558ce81151cSLikun Gao } PMFW_VOLT_PLANE_e; 559ce81151cSLikun Gao 560ce81151cSLikun Gao typedef enum { 561ce81151cSLikun Gao CUSTOMER_VARIANT_ROW, 562ce81151cSLikun Gao CUSTOMER_VARIANT_FALCON, 563ce81151cSLikun Gao CUSTOMER_VARIANT_COUNT, 564ce81151cSLikun Gao } CUSTOMER_VARIANT_e; 565ce81151cSLikun Gao 566ce81151cSLikun Gao typedef enum { 567ce81151cSLikun Gao POWER_SOURCE_AC, 568ce81151cSLikun Gao POWER_SOURCE_DC, 569ce81151cSLikun Gao POWER_SOURCE_COUNT, 570ce81151cSLikun Gao } POWER_SOURCE_e; 571ce81151cSLikun Gao 572ce81151cSLikun Gao typedef enum { 573ce81151cSLikun Gao MEM_VENDOR_SAMSUNG, 574ce81151cSLikun Gao MEM_VENDOR_INFINEON, 575ce81151cSLikun Gao MEM_VENDOR_ELPIDA, 576ce81151cSLikun Gao MEM_VENDOR_ETRON, 577ce81151cSLikun Gao MEM_VENDOR_NANYA, 578ce81151cSLikun Gao MEM_VENDOR_HYNIX, 579ce81151cSLikun Gao MEM_VENDOR_MOSEL, 580ce81151cSLikun Gao MEM_VENDOR_WINBOND, 581ce81151cSLikun Gao MEM_VENDOR_ESMT, 582ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER0, 583ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER1, 584ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER2, 585ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER3, 586ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER4, 587ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER5, 588ce81151cSLikun Gao MEM_VENDOR_MICRON, 589ce81151cSLikun Gao MEM_VENDOR_COUNT, 590ce81151cSLikun Gao } MEM_VENDOR_e; 591ce81151cSLikun Gao 592ce81151cSLikun Gao typedef enum { 593ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_CTL_ZONE0, 594ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_CTL_ZONE1, 595ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_CTL_ZONE2, 596ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_CTL_ZONE3, 597ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_CTL_ZONE4, 598ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0, 599ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0, 600ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1, 601ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1, 602ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2, 603ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2, 604ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3, 605ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3, 606ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4, 607ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4, 608ce81151cSLikun Gao PP_GRTAVFS_HW_ZONE0_VF, 609ce81151cSLikun Gao PP_GRTAVFS_HW_ZONE1_VF1, 610ce81151cSLikun Gao PP_GRTAVFS_HW_ZONE2_VF2, 611ce81151cSLikun Gao PP_GRTAVFS_HW_ZONE3_VF3, 612ce81151cSLikun Gao PP_GRTAVFS_HW_VOLTAGE_GB, 613ce81151cSLikun Gao PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0, 614ce81151cSLikun Gao PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1, 615ce81151cSLikun Gao PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2, 616ce81151cSLikun Gao PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3, 617ce81151cSLikun Gao PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4, 618ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_0, 619ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_1, 620ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_2, 621ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_3, 622ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_4, 623ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_5, 624ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_6, 625ce81151cSLikun Gao PP_GRTAVFS_HW_FUSE_COUNT, 626ce81151cSLikun Gao } PP_GRTAVFS_HW_FUSE_e; 627ce81151cSLikun Gao 628ce81151cSLikun Gao typedef enum { 629ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0, 630ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0, 631ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0, 632ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0, 633ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0, 634ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0, 635ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0, 636ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0, 637ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0, 638ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1, 639ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2, 640ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3, 641ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4, 642ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_FUSE_COUNT, 643ce81151cSLikun Gao } PP_GRTAVFS_FW_COMMON_FUSE_e; 644ce81151cSLikun Gao 645ce81151cSLikun Gao typedef enum { 646ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1, 647ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0, 648ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1, 649ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2, 650ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3, 651ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4, 652ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1, 653ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0, 654ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1, 655ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2, 656ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3, 657ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4, 658ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY, 659ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY, 660ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0, 661ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1, 662ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2, 663ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3, 664ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4, 665ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_COUNT, 666ce81151cSLikun Gao } PP_GRTAVFS_FW_SEP_FUSE_e; 667ce81151cSLikun Gao 668ce81151cSLikun Gao #define PP_NUM_RTAVFS_PWL_ZONES 5 669ce81151cSLikun Gao 670ce81151cSLikun Gao 671ce81151cSLikun Gao 672ce81151cSLikun Gao // VBIOS or PPLIB configures telemetry slope and offset. Only slope expected to be set for SVI3 673ce81151cSLikun Gao // Slope Q1.7, Offset Q1.2 674ce81151cSLikun Gao typedef struct { 675ce81151cSLikun Gao int8_t Offset; // in Amps 676ce81151cSLikun Gao uint8_t Padding; 677ce81151cSLikun Gao uint16_t MaxCurrent; // in Amps 678ce81151cSLikun Gao } SviTelemetryScale_t; 679ce81151cSLikun Gao 680ce81151cSLikun Gao #define PP_NUM_OD_VF_CURVE_POINTS PP_NUM_RTAVFS_PWL_ZONES + 1 681ce81151cSLikun Gao 6827e5632cdSKenneth Feng typedef enum { 6837e5632cdSKenneth Feng FAN_MODE_AUTO = 0, 6847e5632cdSKenneth Feng FAN_MODE_MANUAL_LINEAR, 6857e5632cdSKenneth Feng } FanMode_e; 686ce81151cSLikun Gao 687ce81151cSLikun Gao typedef struct { 688ce81151cSLikun Gao uint32_t FeatureCtrlMask; 689ce81151cSLikun Gao 690ce81151cSLikun Gao //Voltage control 691ce81151cSLikun Gao int16_t VoltageOffsetPerZoneBoundary[PP_NUM_OD_VF_CURVE_POINTS]; 6927e5632cdSKenneth Feng uint16_t VddGfxVmax; // in mV 6937e5632cdSKenneth Feng 6947e5632cdSKenneth Feng uint8_t IdlePwrSavingFeaturesCtrl; 6957e5632cdSKenneth Feng uint8_t RuntimePwrSavingFeaturesCtrl; 696ce81151cSLikun Gao 697ce81151cSLikun Gao //Frequency changes 6981c65e548SEvan Quan int16_t GfxclkFmin; // MHz 6991c65e548SEvan Quan int16_t GfxclkFmax; // MHz 700ce81151cSLikun Gao uint16_t UclkFmin; // MHz 701ce81151cSLikun Gao uint16_t UclkFmax; // MHz 702ce81151cSLikun Gao 703ce81151cSLikun Gao //PPT 704ce81151cSLikun Gao int16_t Ppt; // % 7057e5632cdSKenneth Feng int16_t Tdc; 706ce81151cSLikun Gao 707ce81151cSLikun Gao //Fan control 708ce81151cSLikun Gao uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS]; 709ce81151cSLikun Gao uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS]; 710ce81151cSLikun Gao uint16_t FanMinimumPwm; 7111c65e548SEvan Quan uint16_t AcousticTargetRpmThreshold; 7121c65e548SEvan Quan uint16_t AcousticLimitRpmThreshold; 713ce81151cSLikun Gao uint16_t FanTargetTemperature; // Degree Celcius 714ce81151cSLikun Gao uint8_t FanZeroRpmEnable; 715ce81151cSLikun Gao uint8_t FanZeroRpmStopTemp; 716ce81151cSLikun Gao uint8_t FanMode; 7171c65e548SEvan Quan uint8_t MaxOpTemp; 718ce81151cSLikun Gao 719ce81151cSLikun Gao uint32_t Spare[13]; 720ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround 721ce81151cSLikun Gao } OverDriveTable_t; 722ce81151cSLikun Gao 723ce81151cSLikun Gao typedef struct { 724ce81151cSLikun Gao OverDriveTable_t OverDriveTable; 725ce81151cSLikun Gao 726ce81151cSLikun Gao } OverDriveTableExternal_t; 727ce81151cSLikun Gao 728ce81151cSLikun Gao typedef struct { 729ce81151cSLikun Gao uint32_t FeatureCtrlMask; 730ce81151cSLikun Gao 731ce81151cSLikun Gao int16_t VoltageOffsetPerZoneBoundary; 7327e5632cdSKenneth Feng uint16_t VddGfxVmax; // in mV 733ce81151cSLikun Gao 7347e5632cdSKenneth Feng uint8_t IdlePwrSavingFeaturesCtrl; 7357e5632cdSKenneth Feng uint8_t RuntimePwrSavingFeaturesCtrl; 7367e5632cdSKenneth Feng 7377e5632cdSKenneth Feng int16_t GfxclkFmin; // MHz 7387e5632cdSKenneth Feng int16_t GfxclkFmax; // MHz 739ce81151cSLikun Gao uint16_t UclkFmin; // MHz 740ce81151cSLikun Gao uint16_t UclkFmax; // MHz 741ce81151cSLikun Gao 742ce81151cSLikun Gao //PPT 743ce81151cSLikun Gao int16_t Ppt; // % 7447e5632cdSKenneth Feng int16_t Tdc; 745ce81151cSLikun Gao 746ce81151cSLikun Gao uint8_t FanLinearPwmPoints; 747ce81151cSLikun Gao uint8_t FanLinearTempPoints; 748ce81151cSLikun Gao uint16_t FanMinimumPwm; 7491c65e548SEvan Quan uint16_t AcousticTargetRpmThreshold; 7501c65e548SEvan Quan uint16_t AcousticLimitRpmThreshold; 751ce81151cSLikun Gao uint16_t FanTargetTemperature; // Degree Celcius 752ce81151cSLikun Gao uint8_t FanZeroRpmEnable; 753ce81151cSLikun Gao uint8_t FanZeroRpmStopTemp; 754ce81151cSLikun Gao uint8_t FanMode; 7551c65e548SEvan Quan uint8_t MaxOpTemp; 756ce81151cSLikun Gao 757ce81151cSLikun Gao uint32_t Spare[13]; 758ce81151cSLikun Gao 759ce81151cSLikun Gao } OverDriveLimits_t; 760ce81151cSLikun Gao 761ce81151cSLikun Gao 762ce81151cSLikun Gao typedef enum { 763ce81151cSLikun Gao BOARD_GPIO_SMUIO_0, 764ce81151cSLikun Gao BOARD_GPIO_SMUIO_1, 765ce81151cSLikun Gao BOARD_GPIO_SMUIO_2, 766ce81151cSLikun Gao BOARD_GPIO_SMUIO_3, 767ce81151cSLikun Gao BOARD_GPIO_SMUIO_4, 768ce81151cSLikun Gao BOARD_GPIO_SMUIO_5, 769ce81151cSLikun Gao BOARD_GPIO_SMUIO_6, 770ce81151cSLikun Gao BOARD_GPIO_SMUIO_7, 771ce81151cSLikun Gao BOARD_GPIO_SMUIO_8, 772ce81151cSLikun Gao BOARD_GPIO_SMUIO_9, 773ce81151cSLikun Gao BOARD_GPIO_SMUIO_10, 774ce81151cSLikun Gao BOARD_GPIO_SMUIO_11, 775ce81151cSLikun Gao BOARD_GPIO_SMUIO_12, 776ce81151cSLikun Gao BOARD_GPIO_SMUIO_13, 777ce81151cSLikun Gao BOARD_GPIO_SMUIO_14, 778ce81151cSLikun Gao BOARD_GPIO_SMUIO_15, 779ce81151cSLikun Gao BOARD_GPIO_SMUIO_16, 780ce81151cSLikun Gao BOARD_GPIO_SMUIO_17, 781ce81151cSLikun Gao BOARD_GPIO_SMUIO_18, 782ce81151cSLikun Gao BOARD_GPIO_SMUIO_19, 783ce81151cSLikun Gao BOARD_GPIO_SMUIO_20, 784ce81151cSLikun Gao BOARD_GPIO_SMUIO_21, 785ce81151cSLikun Gao BOARD_GPIO_SMUIO_22, 786ce81151cSLikun Gao BOARD_GPIO_SMUIO_23, 787ce81151cSLikun Gao BOARD_GPIO_SMUIO_24, 788ce81151cSLikun Gao BOARD_GPIO_SMUIO_25, 789ce81151cSLikun Gao BOARD_GPIO_SMUIO_26, 790ce81151cSLikun Gao BOARD_GPIO_SMUIO_27, 791ce81151cSLikun Gao BOARD_GPIO_SMUIO_28, 792ce81151cSLikun Gao BOARD_GPIO_SMUIO_29, 793ce81151cSLikun Gao BOARD_GPIO_SMUIO_30, 794ce81151cSLikun Gao BOARD_GPIO_SMUIO_31, 795ce81151cSLikun Gao MAX_BOARD_GPIO_SMUIO_NUM, 796ce81151cSLikun Gao BOARD_GPIO_DC_GEN_A, 797ce81151cSLikun Gao BOARD_GPIO_DC_GEN_B, 798ce81151cSLikun Gao BOARD_GPIO_DC_GEN_C, 799ce81151cSLikun Gao BOARD_GPIO_DC_GEN_D, 800ce81151cSLikun Gao BOARD_GPIO_DC_GEN_E, 801ce81151cSLikun Gao BOARD_GPIO_DC_GEN_F, 802ce81151cSLikun Gao BOARD_GPIO_DC_GEN_G, 803ce81151cSLikun Gao BOARD_GPIO_DC_GENLK_CLK, 804ce81151cSLikun Gao BOARD_GPIO_DC_GENLK_VSYNC, 805ce81151cSLikun Gao BOARD_GPIO_DC_SWAPLOCK_A, 806ce81151cSLikun Gao BOARD_GPIO_DC_SWAPLOCK_B, 807ce81151cSLikun Gao } BOARD_GPIO_TYPE_e; 808ce81151cSLikun Gao 809ce81151cSLikun Gao #define INVALID_BOARD_GPIO 0xFF 810ce81151cSLikun Gao 811ce81151cSLikun Gao 812ce81151cSLikun Gao typedef struct { 813ce81151cSLikun Gao //PLL 0 814ce81151cSLikun Gao uint16_t InitGfxclk_bypass; 815ce81151cSLikun Gao uint16_t InitSocclk; 816ce81151cSLikun Gao uint16_t InitMp0clk; 817ce81151cSLikun Gao uint16_t InitMpioclk; 818ce81151cSLikun Gao uint16_t InitSmnclk; 819ce81151cSLikun Gao uint16_t InitUcpclk; 820ce81151cSLikun Gao uint16_t InitCsrclk; 821ce81151cSLikun Gao //PLL 1 822ce81151cSLikun Gao 823ce81151cSLikun Gao uint16_t InitDprefclk; 824ce81151cSLikun Gao uint16_t InitDcfclk; 825ce81151cSLikun Gao uint16_t InitDtbclk; 826ce81151cSLikun Gao //PLL 2 827ce81151cSLikun Gao uint16_t InitDclk; //assume same DCLK/VCLK for both instances 828ce81151cSLikun Gao uint16_t InitVclk; 829ce81151cSLikun Gao // PLL 3 830ce81151cSLikun Gao uint16_t InitUsbdfsclk; 831ce81151cSLikun Gao uint16_t InitMp1clk; 832ce81151cSLikun Gao uint16_t InitLclk; 833ce81151cSLikun Gao uint16_t InitBaco400clk_bypass; 834ce81151cSLikun Gao uint16_t InitBaco1200clk_bypass; 835ce81151cSLikun Gao uint16_t InitBaco700clk_bypass; 836ce81151cSLikun Gao // PLL 4 837ce81151cSLikun Gao uint16_t InitFclk; 838ce81151cSLikun Gao // PLL 5 839ce81151cSLikun Gao uint16_t InitGfxclk_clkb; 840ce81151cSLikun Gao 841ce81151cSLikun Gao //PLL 6 842ce81151cSLikun Gao uint8_t InitUclkDPMState; // =0,1,2,3, frequency from FreqTableUclk 843ce81151cSLikun Gao 844ce81151cSLikun Gao uint8_t Padding[3]; 845ce81151cSLikun Gao 846ce81151cSLikun Gao uint32_t InitVcoFreqPll0; 847ce81151cSLikun Gao uint32_t InitVcoFreqPll1; 848ce81151cSLikun Gao uint32_t InitVcoFreqPll2; 849ce81151cSLikun Gao uint32_t InitVcoFreqPll3; 850ce81151cSLikun Gao uint32_t InitVcoFreqPll4; 851ce81151cSLikun Gao uint32_t InitVcoFreqPll5; 852ce81151cSLikun Gao uint32_t InitVcoFreqPll6; 853ce81151cSLikun Gao 854ce81151cSLikun Gao //encoding will change depending on SVI2/SVI3 855ce81151cSLikun Gao uint16_t InitGfx; // In mV(Q2) , should be 0? 856ce81151cSLikun Gao uint16_t InitSoc; // In mV(Q2) 857ce81151cSLikun Gao uint16_t InitU; // In Mv(Q2) 858ce81151cSLikun Gao 859ce81151cSLikun Gao uint16_t Padding2; 860ce81151cSLikun Gao 861ce81151cSLikun Gao uint32_t Spare[8]; 862ce81151cSLikun Gao 863ce81151cSLikun Gao } BootValues_t; 864ce81151cSLikun Gao 865ce81151cSLikun Gao 866ce81151cSLikun Gao typedef struct { 867ce81151cSLikun Gao uint16_t Power[PPT_THROTTLER_COUNT][POWER_SOURCE_COUNT]; // Watts 868ce81151cSLikun Gao uint16_t Tdc[TDC_THROTTLER_COUNT]; // Amps 869ce81151cSLikun Gao 870ce81151cSLikun Gao uint16_t Temperature[TEMP_COUNT]; // Celsius 871ce81151cSLikun Gao 872ce81151cSLikun Gao uint8_t PwmLimitMin; 873ce81151cSLikun Gao uint8_t PwmLimitMax; 874ce81151cSLikun Gao uint8_t FanTargetTemperature; 875ce81151cSLikun Gao uint8_t Spare1[1]; 876ce81151cSLikun Gao 877ce81151cSLikun Gao uint16_t AcousticTargetRpmThresholdMin; 878ce81151cSLikun Gao uint16_t AcousticTargetRpmThresholdMax; 879ce81151cSLikun Gao 880ce81151cSLikun Gao uint16_t AcousticLimitRpmThresholdMin; 881ce81151cSLikun Gao uint16_t AcousticLimitRpmThresholdMax; 882ce81151cSLikun Gao 883ce81151cSLikun Gao uint16_t PccLimitMin; 884ce81151cSLikun Gao uint16_t PccLimitMax; 885ce81151cSLikun Gao 886ce81151cSLikun Gao uint16_t FanStopTempMin; 887ce81151cSLikun Gao uint16_t FanStopTempMax; 888ce81151cSLikun Gao uint16_t FanStartTempMin; 889ce81151cSLikun Gao uint16_t FanStartTempMax; 890ce81151cSLikun Gao 8917e5632cdSKenneth Feng uint16_t PowerMinPpt0[POWER_SOURCE_COUNT]; 8927e5632cdSKenneth Feng uint32_t Spare[11]; 893ce81151cSLikun Gao 894ce81151cSLikun Gao } MsgLimits_t; 895ce81151cSLikun Gao 896ce81151cSLikun Gao typedef struct { 897ce81151cSLikun Gao uint16_t BaseClockAc; 898ce81151cSLikun Gao uint16_t GameClockAc; 899ce81151cSLikun Gao uint16_t BoostClockAc; 900ce81151cSLikun Gao uint16_t BaseClockDc; 901ce81151cSLikun Gao uint16_t GameClockDc; 902ce81151cSLikun Gao uint16_t BoostClockDc; 903ce81151cSLikun Gao 904ce81151cSLikun Gao uint32_t Reserved[4]; 905ce81151cSLikun Gao } DriverReportedClocks_t; 906ce81151cSLikun Gao 907ce81151cSLikun Gao typedef struct { 908ce81151cSLikun Gao uint8_t DcBtcEnabled; 909ce81151cSLikun Gao uint8_t Padding[3]; 910ce81151cSLikun Gao 911ce81151cSLikun Gao uint16_t DcTol; // mV Q2 912ce81151cSLikun Gao uint16_t DcBtcGb; // mV Q2 913ce81151cSLikun Gao 914ce81151cSLikun Gao uint16_t DcBtcMin; // mV Q2 915ce81151cSLikun Gao uint16_t DcBtcMax; // mV Q2 916ce81151cSLikun Gao 917ce81151cSLikun Gao LinearInt_t DcBtcGbScalar; 918ce81151cSLikun Gao 919ce81151cSLikun Gao } AvfsDcBtcParams_t; 920ce81151cSLikun Gao 921ce81151cSLikun Gao typedef struct { 922ce81151cSLikun Gao uint16_t AvfsTemp[AVFS_TEMP_COUNT]; //in degrees C 923ce81151cSLikun Gao uint16_t VftFMin; // in MHz 924ce81151cSLikun Gao uint16_t VInversion; // in mV Q2 925ce81151cSLikun Gao QuadraticInt_t qVft[AVFS_TEMP_COUNT]; 926ce81151cSLikun Gao QuadraticInt_t qAvfsGb; 927ce81151cSLikun Gao QuadraticInt_t qAvfsGb2; 928ce81151cSLikun Gao } AvfsFuseOverride_t; 929ce81151cSLikun Gao 930ce81151cSLikun Gao typedef struct { 931ce81151cSLikun Gao // SECTION: Version 932ce81151cSLikun Gao 933ce81151cSLikun Gao uint32_t Version; // should be unique to each SKU(i.e if any value changes in below structure then this value must be different) 934ce81151cSLikun Gao 935ce81151cSLikun Gao // SECTION: Feature Control 936ce81151cSLikun Gao uint32_t FeaturesToRun[NUM_FEATURES / 32]; // Features that PMFW will attempt to enable. Use FEATURE_*_BIT as mapping 937ce81151cSLikun Gao 938ce81151cSLikun Gao // SECTION: Miscellaneous Configuration 939ce81151cSLikun Gao uint8_t TotalPowerConfig; // Determines how PMFW calculates the power. Use defines from PwrConfig_e 940ce81151cSLikun Gao uint8_t CustomerVariant; //To specify if this PPTable is intended for a particular customer. Use defines from CUSTOMER_VARIANT_e 941ce81151cSLikun Gao uint8_t MemoryTemperatureTypeMask; // Bit mapping indicating which methods of memory temperature reading are enabled. Use defines from MEM_TEMP_*BIT 942ce81151cSLikun Gao uint8_t SmartShiftVersion; // Determine what SmartShift feature version is supported Use defines from SMARTSHIFT_VERSION_e 943ce81151cSLikun Gao 944ce81151cSLikun Gao // SECTION: Infrastructure Limits 945ce81151cSLikun Gao uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in AC mode. Multiple limits supported 946ce81151cSLikun Gao uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in DC mode. Multiple limits supported 947ce81151cSLikun Gao 948ce81151cSLikun Gao uint16_t SocketPowerLimitSmartShift2; // In Watts. Power limit used SmartShift 949ce81151cSLikun Gao 950ce81151cSLikun Gao //if set to 1, SocketPowerLimitAc and SocketPowerLimitDc will be interpreted as legacy programs(i.e absolute power). If 0, all except index 0 will be scalars 951ce81151cSLikun Gao //relative index 0 952ce81151cSLikun Gao uint8_t EnableLegacyPptLimit; 953ce81151cSLikun Gao uint8_t UseInputTelemetry; //applicable to SVI3 only and only to be set if VRs support 954ce81151cSLikun Gao uint8_t SmartShiftMinReportedPptinDcs; //minimum possible active power consumption for this SKU. Used for SmartShift power reporting 955ce81151cSLikun Gao 956ce81151cSLikun Gao uint8_t PaddingPpt[1]; 957ce81151cSLikun Gao 958ce81151cSLikun Gao uint16_t VrTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with VR regulator maximum temperature 959ce81151cSLikun Gao 960ce81151cSLikun Gao uint16_t PlatformTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with platform maximum temperature per VR current rail 961ce81151cSLikun Gao 962ce81151cSLikun Gao uint16_t TemperatureLimit[TEMP_COUNT]; // In degrees Celsius. Temperature limit associated with each input 963ce81151cSLikun Gao 964ce81151cSLikun Gao uint16_t HwCtfTempLimit; // In degrees Celsius. Temperature above which HW will trigger CTF. Consumed by VBIOS only 965ce81151cSLikun Gao 966ce81151cSLikun Gao uint16_t PaddingInfra; 967ce81151cSLikun Gao 968ce81151cSLikun Gao // Per year normalized Vmax state failure rates (sum of the two domains divided by life time in years) 969ce81151cSLikun Gao uint32_t FitControllerFailureRateLimit; //in IEEE float 970ce81151cSLikun Gao //Expected GFX Duty Cycle at Vmax. 971ce81151cSLikun Gao uint32_t FitControllerGfxDutyCycle; // in IEEE float 972ce81151cSLikun Gao //Expected SOC Duty Cycle at Vmax. 973ce81151cSLikun Gao uint32_t FitControllerSocDutyCycle; // in IEEE float 974ce81151cSLikun Gao 975ce81151cSLikun Gao //This offset will be deducted from the controller output to before it goes through the SOC Vset limiter block. 976ce81151cSLikun Gao uint32_t FitControllerSocOffset; //in IEEE float 977ce81151cSLikun Gao 978ce81151cSLikun Gao uint32_t GfxApccPlusResidencyLimit; // Percentage value. Used by APCC+ controller to control PCC residency to some value 979ce81151cSLikun Gao 980ce81151cSLikun Gao // SECTION: Throttler settings 981ce81151cSLikun Gao uint32_t ThrottlerControlMask; // See THROTTLER_*_BIT for mapping 982ce81151cSLikun Gao 983ce81151cSLikun Gao // SECTION: FW DSTATE Settings 984ce81151cSLikun Gao uint32_t FwDStateMask; // See FW_DSTATE_*_BIT for mapping 985ce81151cSLikun Gao 986ce81151cSLikun Gao // SECTION: Voltage Control Parameters 987ce81151cSLikun Gao uint16_t UlvVoltageOffset[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2). ULV offset used in either GFX_ULV or SOC_ULV(part of FW_DSTATE) 988ce81151cSLikun Gao 989ce81151cSLikun Gao uint16_t UlvVoltageOffsetU; // In mV(Q2). ULV offset used in either U_ULV(part of FW_DSTATE) 990ce81151cSLikun Gao uint16_t DeepUlvVoltageOffsetSoc; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC as part of FW_DSTATE 991ce81151cSLikun Gao 992ce81151cSLikun Gao // Voltage Limits 993ce81151cSLikun Gao uint16_t DefaultMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage without FIT controller enabled 994ce81151cSLikun Gao uint16_t BoostMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage with FIT controller enabled 995ce81151cSLikun Gao 996ce81151cSLikun Gao //Vmin Optimizations 997ce81151cSLikun Gao int16_t VminTempHystersis[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature hysteresis for switching between low/high temperature values for Vmin 998ce81151cSLikun Gao int16_t VminTempThreshold[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature threshold for switching between low/high temperature values for Vmin 999ce81151cSLikun Gao uint16_t Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at hot. 1000ce81151cSLikun Gao uint16_t Vmin_Cold_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at cold. 1001ce81151cSLikun Gao uint16_t Vmin_Hot_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at hot. 1002ce81151cSLikun Gao uint16_t Vmin_Cold_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at cold. 1003ce81151cSLikun Gao uint16_t Vmin_Aging_Offset[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Worst-case aging margin 100425dfc8faSEvan Quan uint16_t Spare_Vmin_Plat_Offset_Hot[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Hot 100525dfc8faSEvan Quan uint16_t Spare_Vmin_Plat_Offset_Cold[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Cold 1006ce81151cSLikun Gao 1007ce81151cSLikun Gao //This is a fixed/minimum VMIN aging degradation offset which is applied at T0. This reflects the minimum amount of aging already accounted for. 1008ce81151cSLikun Gao uint16_t VcBtcFixedVminAgingOffset[PMFW_VOLT_PLANE_COUNT]; 1009ce81151cSLikun Gao //Linear offset or GB term to account for mis-correlation between PSM and Vmin shift trends across parts. 1010ce81151cSLikun Gao uint16_t VcBtcVmin2PsmDegrationGb[PMFW_VOLT_PLANE_COUNT]; 1011ce81151cSLikun Gao //Scalar coefficient of the PSM aging degradation function 1012ce81151cSLikun Gao uint32_t VcBtcPsmA[PMFW_VOLT_PLANE_COUNT]; // A_PSM 1013ce81151cSLikun Gao //Exponential coefficient of the PSM aging degradation function 1014ce81151cSLikun Gao uint32_t VcBtcPsmB[PMFW_VOLT_PLANE_COUNT]; // B_PSM 1015ce81151cSLikun Gao //Scalar coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 1016ce81151cSLikun Gao uint32_t VcBtcVminA[PMFW_VOLT_PLANE_COUNT]; // A_VMIN 1017ce81151cSLikun Gao //Exponential coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 1018ce81151cSLikun Gao uint32_t VcBtcVminB[PMFW_VOLT_PLANE_COUNT]; // B_VMIN 1019ce81151cSLikun Gao 1020ce81151cSLikun Gao uint8_t PerPartVminEnabled[PMFW_VOLT_PLANE_COUNT]; 1021ce81151cSLikun Gao uint8_t VcBtcEnabled[PMFW_VOLT_PLANE_COUNT]; 1022ce81151cSLikun Gao 1023ce81151cSLikun Gao uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 1024ce81151cSLikun Gao uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 1025ce81151cSLikun Gao 10261c65e548SEvan Quan QuadraticInt_t Vmin_droop; 10271c65e548SEvan Quan uint32_t SpareVmin[9]; 1028ce81151cSLikun Gao 1029ce81151cSLikun Gao 1030ce81151cSLikun Gao //SECTION: DPM Configuration 1 1031ce81151cSLikun Gao DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 1032ce81151cSLikun Gao 1033ce81151cSLikun Gao uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1034ce81151cSLikun Gao uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1035ce81151cSLikun Gao uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1036ce81151cSLikun Gao uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1037ce81151cSLikun Gao uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1038ce81151cSLikun Gao uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1039ce81151cSLikun Gao uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1040ce81151cSLikun Gao uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1041ce81151cSLikun Gao uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1042ce81151cSLikun Gao uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1043ce81151cSLikun Gao uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1044ce81151cSLikun Gao 1045ce81151cSLikun Gao uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1046ce81151cSLikun Gao 1047ce81151cSLikun Gao // SECTION: DPM Configuration 2 1048ce81151cSLikun Gao uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 1049ce81151cSLikun Gao uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 1050ce81151cSLikun Gao 1051ce81151cSLikun Gao uint8_t GfxclkSpare[2]; 1052ce81151cSLikun Gao uint16_t GfxclkFreqCap; 1053ce81151cSLikun Gao 1054ce81151cSLikun Gao //GFX Idle Power Settings 1055ce81151cSLikun Gao uint16_t GfxclkFgfxoffEntry; // in Mhz 1056ce81151cSLikun Gao uint16_t GfxclkFgfxoffExitImu; // in Mhz 1057ce81151cSLikun Gao uint16_t GfxclkFgfxoffExitRlc; // in Mhz 1058ce81151cSLikun Gao uint16_t GfxclkThrottleClock; //Used primarily in DCS 1059ce81151cSLikun Gao uint8_t EnableGfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages 1060ce81151cSLikun Gao uint8_t GfxIdlePadding; 1061ce81151cSLikun Gao 1062ce81151cSLikun Gao uint8_t SmsRepairWRCKClkDivEn; 1063ce81151cSLikun Gao uint8_t SmsRepairWRCKClkDivVal; 1064ce81151cSLikun Gao uint8_t GfxOffEntryEarlyMGCGEn; 1065ce81151cSLikun Gao uint8_t GfxOffEntryForceCGCGEn; 1066ce81151cSLikun Gao uint8_t GfxOffEntryForceCGCGDelayEn; 1067ce81151cSLikun Gao uint8_t GfxOffEntryForceCGCGDelayVal; // in microseconds 1068ce81151cSLikun Gao 1069ce81151cSLikun Gao uint16_t GfxclkFreqGfxUlv; // in MHz 1070ce81151cSLikun Gao uint8_t GfxIdlePadding2[2]; 1071ce81151cSLikun Gao 1072cbe07c98SEvan Quan uint32_t GfxOffEntryHysteresis; 1073cbe07c98SEvan Quan uint32_t GfxoffSpare[15]; 1074ce81151cSLikun Gao 1075ce81151cSLikun Gao // GFX GPO 10767e5632cdSKenneth Feng uint32_t DfllBtcMasterScalerM; 10777e5632cdSKenneth Feng int32_t DfllBtcMasterScalerB; 10787e5632cdSKenneth Feng uint32_t DfllBtcSlaveScalerM; 10797e5632cdSKenneth Feng int32_t DfllBtcSlaveScalerB; 10807e5632cdSKenneth Feng 10817e5632cdSKenneth Feng uint32_t DfllPccAsWaitCtrl; //GDFLL_AS_WAIT_CTRL_PCC register value to be passed to RLC msg 10827e5632cdSKenneth Feng uint32_t DfllPccAsStepCtrl; //GDFLL_AS_STEP_CTRL_PCC register value to be passed to RLC msg 10837e5632cdSKenneth Feng 10847e5632cdSKenneth Feng uint32_t DfllL2FrequencyBoostM; //Unitless (float) 10857e5632cdSKenneth Feng uint32_t DfllL2FrequencyBoostB; //In MHz (integer) 10867e5632cdSKenneth Feng uint32_t GfxGpoSpare[8]; 1087ce81151cSLikun Gao 1088ce81151cSLikun Gao // GFX DCS 1089ce81151cSLikun Gao 1090ce81151cSLikun Gao uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase 1091ce81151cSLikun Gao uint16_t PaddingDcs; 1092ce81151cSLikun Gao 1093ce81151cSLikun Gao uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase 1094ce81151cSLikun Gao uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. 1095ce81151cSLikun Gao 1096ce81151cSLikun Gao uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS. 1097ce81151cSLikun Gao 1098ce81151cSLikun Gao uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. 1099ce81151cSLikun Gao uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin. 1100ce81151cSLikun Gao 1101ce81151cSLikun Gao 1102ce81151cSLikun Gao uint32_t DcsSpare[16]; 1103ce81151cSLikun Gao 1104ce81151cSLikun Gao // UCLK section 1105ce81151cSLikun Gao uint8_t UseStrobeModeOptimizations; //Set to indicate that FW should use strobe mode optimizations 1106ce81151cSLikun Gao uint8_t PaddingMem[3]; 1107ce81151cSLikun Gao 1108ce81151cSLikun Gao uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 1109ce81151cSLikun Gao uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 1110ce81151cSLikun Gao 1111ce81151cSLikun Gao uint16_t MemVmempVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1112ce81151cSLikun Gao uint16_t MemVddioVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1113ce81151cSLikun Gao 1114ce81151cSLikun Gao //FCLK Section 1115ce81151cSLikun Gao 1116ce81151cSLikun Gao uint8_t FclkDpmUPstates[NUM_FCLK_DPM_LEVELS]; // U P-state ID associated with each FCLK DPM state. 1117ce81151cSLikun Gao uint16_t FclkDpmVddU[NUM_FCLK_DPM_LEVELS]; // mV(Q2) Vset U voltage associated with each FCLK DPM state. 1118ce81151cSLikun Gao uint16_t FclkDpmUSpeed[NUM_FCLK_DPM_LEVELS]; //U speed associated with each FCLK DPM state 1119ce81151cSLikun Gao uint16_t FclkDpmDisallowPstateFreq; //Frequency which FW will target when indicated that display config cannot support P-state. Set to 0 use FW calculated value 1120ce81151cSLikun Gao uint16_t PaddingFclk; 1121ce81151cSLikun Gao 1122ce81151cSLikun Gao // Link DPM Settings 1123ce81151cSLikun Gao uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 1124ce81151cSLikun Gao uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 1125ce81151cSLikun Gao uint16_t LclkFreq[NUM_LINK_LEVELS]; 1126ce81151cSLikun Gao 1127ce81151cSLikun Gao // SECTION: Fan Control 1128ce81151cSLikun Gao uint16_t FanStopTemp[TEMP_COUNT]; //Celsius 1129ce81151cSLikun Gao uint16_t FanStartTemp[TEMP_COUNT]; //Celsius 1130ce81151cSLikun Gao 1131ce81151cSLikun Gao uint16_t FanGain[TEMP_COUNT]; 1132ce81151cSLikun Gao uint16_t FanGainPadding; 1133ce81151cSLikun Gao 1134ce81151cSLikun Gao uint16_t FanPwmMin; 1135ce81151cSLikun Gao uint16_t AcousticTargetRpmThreshold; 1136ce81151cSLikun Gao uint16_t AcousticLimitRpmThreshold; 1137ce81151cSLikun Gao uint16_t FanMaximumRpm; 1138ce81151cSLikun Gao uint16_t MGpuAcousticLimitRpmThreshold; 1139ce81151cSLikun Gao uint16_t FanTargetGfxclk; 1140ce81151cSLikun Gao uint32_t TempInputSelectMask; 1141ce81151cSLikun Gao uint8_t FanZeroRpmEnable; 1142ce81151cSLikun Gao uint8_t FanTachEdgePerRev; 1143ce81151cSLikun Gao uint16_t FanTargetTemperature[TEMP_COUNT]; 1144ce81151cSLikun Gao 1145ce81151cSLikun Gao // The following are AFC override parameters. Leave at 0 to use FW defaults. 1146ce81151cSLikun Gao int16_t FuzzyFan_ErrorSetDelta; 1147ce81151cSLikun Gao int16_t FuzzyFan_ErrorRateSetDelta; 1148ce81151cSLikun Gao int16_t FuzzyFan_PwmSetDelta; 1149ce81151cSLikun Gao uint16_t FuzzyFan_Reserved; 1150ce81151cSLikun Gao 1151ce81151cSLikun Gao uint16_t FwCtfLimit[TEMP_COUNT]; 1152ce81151cSLikun Gao 1153ce81151cSLikun Gao uint16_t IntakeTempEnableRPM; 1154ce81151cSLikun Gao int16_t IntakeTempOffsetTemp; 1155ce81151cSLikun Gao uint16_t IntakeTempReleaseTemp; 1156ce81151cSLikun Gao uint16_t IntakeTempHighIntakeAcousticLimit; 1157ce81151cSLikun Gao uint16_t IntakeTempAcouticLimitReleaseRate; 1158ce81151cSLikun Gao 11597e5632cdSKenneth Feng int16_t FanAbnormalTempLimitOffset; 1160ce81151cSLikun Gao uint16_t FanStalledTriggerRpm; 11617e5632cdSKenneth Feng uint16_t FanAbnormalTriggerRpmCoeff; 11627e5632cdSKenneth Feng uint16_t FanAbnormalDetectionEnable; 1163ce81151cSLikun Gao 11647e5632cdSKenneth Feng uint8_t FanIntakeSensorSupport; 11657e5632cdSKenneth Feng uint8_t FanIntakePadding[3]; 11667e5632cdSKenneth Feng uint32_t FanSpare[13]; 1167ce81151cSLikun Gao 1168ce81151cSLikun Gao // SECTION: VDD_GFX AVFS 1169ce81151cSLikun Gao 1170ce81151cSLikun Gao uint8_t OverrideGfxAvfsFuses; 1171ce81151cSLikun Gao uint8_t GfxAvfsPadding[3]; 1172ce81151cSLikun Gao 1173ce81151cSLikun Gao uint32_t L2HwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; //see fusedoc for encoding 1174ce81151cSLikun Gao uint32_t SeHwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; 1175ce81151cSLikun Gao 1176ce81151cSLikun Gao uint32_t CommonRtAvfs[PP_GRTAVFS_FW_COMMON_FUSE_COUNT]; 1177ce81151cSLikun Gao 1178ce81151cSLikun Gao uint32_t L2FwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1179ce81151cSLikun Gao uint32_t SeFwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1180ce81151cSLikun Gao 1181ce81151cSLikun Gao uint32_t Droop_PWL_F[PP_NUM_RTAVFS_PWL_ZONES]; 1182ce81151cSLikun Gao uint32_t Droop_PWL_a[PP_NUM_RTAVFS_PWL_ZONES]; 1183ce81151cSLikun Gao uint32_t Droop_PWL_b[PP_NUM_RTAVFS_PWL_ZONES]; 1184ce81151cSLikun Gao uint32_t Droop_PWL_c[PP_NUM_RTAVFS_PWL_ZONES]; 1185ce81151cSLikun Gao 1186ce81151cSLikun Gao uint32_t Static_PWL_Offset[PP_NUM_RTAVFS_PWL_ZONES]; 1187ce81151cSLikun Gao 1188ce81151cSLikun Gao uint32_t dGbV_dT_vmin; 1189ce81151cSLikun Gao uint32_t dGbV_dT_vmax; 1190ce81151cSLikun Gao 1191ce81151cSLikun Gao //Unused: PMFW-9370 1192ce81151cSLikun Gao uint32_t V2F_vmin_range_low; 1193ce81151cSLikun Gao uint32_t V2F_vmin_range_high; 1194ce81151cSLikun Gao uint32_t V2F_vmax_range_low; 1195ce81151cSLikun Gao uint32_t V2F_vmax_range_high; 1196ce81151cSLikun Gao 1197ce81151cSLikun Gao AvfsDcBtcParams_t DcBtcGfxParams; 1198ce81151cSLikun Gao 1199ce81151cSLikun Gao uint32_t GfxAvfsSpare[32]; 1200ce81151cSLikun Gao 1201ce81151cSLikun Gao //SECTION: VDD_SOC AVFS 1202ce81151cSLikun Gao 1203ce81151cSLikun Gao uint8_t OverrideSocAvfsFuses; 1204ce81151cSLikun Gao uint8_t MinSocAvfsRevision; 1205ce81151cSLikun Gao uint8_t SocAvfsPadding[2]; 1206ce81151cSLikun Gao 1207ce81151cSLikun Gao AvfsFuseOverride_t SocAvfsFuseOverride[AVFS_D_COUNT]; 1208ce81151cSLikun Gao 1209ce81151cSLikun Gao DroopInt_t dBtcGbSoc[AVFS_D_COUNT]; // GHz->V BtcGb 1210ce81151cSLikun Gao 1211ce81151cSLikun Gao LinearInt_t qAgingGb[AVFS_D_COUNT]; // GHz->V 1212ce81151cSLikun Gao 1213ce81151cSLikun Gao QuadraticInt_t qStaticVoltageOffset[AVFS_D_COUNT]; // GHz->V 1214ce81151cSLikun Gao 1215ce81151cSLikun Gao AvfsDcBtcParams_t DcBtcSocParams[AVFS_D_COUNT]; 1216ce81151cSLikun Gao 1217ce81151cSLikun Gao uint32_t SocAvfsSpare[32]; 1218ce81151cSLikun Gao 1219ce81151cSLikun Gao //SECTION: Boot clock and voltage values 1220ce81151cSLikun Gao BootValues_t BootValues; 1221ce81151cSLikun Gao 1222ce81151cSLikun Gao //SECTION: Driver Reported Clocks 1223ce81151cSLikun Gao DriverReportedClocks_t DriverReportedClocks; 1224ce81151cSLikun Gao 1225ce81151cSLikun Gao //SECTION: Message Limits 1226ce81151cSLikun Gao MsgLimits_t MsgLimits; 1227ce81151cSLikun Gao 1228ce81151cSLikun Gao //SECTION: OverDrive Limits 1229ce81151cSLikun Gao OverDriveLimits_t OverDriveLimitsMin; 1230ce81151cSLikun Gao OverDriveLimits_t OverDriveLimitsBasicMax; 1231ce81151cSLikun Gao uint32_t reserved[22]; 1232ce81151cSLikun Gao 1233ce81151cSLikun Gao // SECTION: Advanced Options 1234ce81151cSLikun Gao uint32_t DebugOverrides; 1235ce81151cSLikun Gao 1236da1acbb1SEvan Quan // Section: Total Board Power idle vs active coefficients 1237da1acbb1SEvan Quan uint8_t TotalBoardPowerSupport; 1238da1acbb1SEvan Quan uint8_t TotalBoardPowerPadding[3]; 1239da1acbb1SEvan Quan 1240da1acbb1SEvan Quan int16_t TotalIdleBoardPowerM; 1241da1acbb1SEvan Quan int16_t TotalIdleBoardPowerB; 1242da1acbb1SEvan Quan int16_t TotalBoardPowerM; 1243da1acbb1SEvan Quan int16_t TotalBoardPowerB; 1244da1acbb1SEvan Quan 12457e5632cdSKenneth Feng //PMFW-11158 12467e5632cdSKenneth Feng QuadraticInt_t qFeffCoeffGameClock[POWER_SOURCE_COUNT]; 12477e5632cdSKenneth Feng QuadraticInt_t qFeffCoeffBaseClock[POWER_SOURCE_COUNT]; 12487e5632cdSKenneth Feng QuadraticInt_t qFeffCoeffBoostClock[POWER_SOURCE_COUNT]; 12497e5632cdSKenneth Feng 1250ce81151cSLikun Gao // SECTION: Sku Reserved 12517e5632cdSKenneth Feng uint32_t Spare[43]; 1252ce81151cSLikun Gao 1253ce81151cSLikun Gao // Padding for MMHUB - do not modify this 1254ce81151cSLikun Gao uint32_t MmHubPadding[8]; 1255ce81151cSLikun Gao 1256ce81151cSLikun Gao } SkuTable_t; 1257ce81151cSLikun Gao 1258ce81151cSLikun Gao typedef struct { 1259ce81151cSLikun Gao // SECTION: Version 1260ce81151cSLikun Gao uint32_t Version; //should be unique to each board type 1261ce81151cSLikun Gao 1262ce81151cSLikun Gao 1263ce81151cSLikun Gao // SECTION: I2C Control 1264ce81151cSLikun Gao I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 1265ce81151cSLikun Gao 1266ce81151cSLikun Gao // SECTION: SVI2 Board Parameters 1267ce81151cSLikun Gao uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 1268ce81151cSLikun Gao uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 1269ce81151cSLikun Gao uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 1270ce81151cSLikun Gao uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 1271ce81151cSLikun Gao 1272ce81151cSLikun Gao uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1273ce81151cSLikun Gao uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1274ce81151cSLikun Gao uint8_t VmempUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1275ce81151cSLikun Gao uint8_t VddioUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1276ce81151cSLikun Gao 1277ce81151cSLikun Gao //SECTION SVI3 Board Parameters 1278ce81151cSLikun Gao uint8_t SlaveAddrMapping[SVI_PLANE_COUNT]; 1279ce81151cSLikun Gao uint8_t VrPsiSupport[SVI_PLANE_COUNT]; 1280ce81151cSLikun Gao 1281ce81151cSLikun Gao uint8_t PaddingPsi[SVI_PLANE_COUNT]; 1282ce81151cSLikun Gao uint8_t EnablePsi6[SVI_PLANE_COUNT]; // only applicable in SVI3 1283ce81151cSLikun Gao 1284ce81151cSLikun Gao // SECTION: Voltage Regulator Settings 1285ce81151cSLikun Gao SviTelemetryScale_t SviTelemetryScale[SVI_PLANE_COUNT]; 1286ce81151cSLikun Gao uint32_t VoltageTelemetryRatio[SVI_PLANE_COUNT]; // This is used for VDDIO Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 1287ce81151cSLikun Gao 1288ce81151cSLikun Gao uint8_t DownSlewRateVr[SVI_PLANE_COUNT]; 1289ce81151cSLikun Gao 1290ce81151cSLikun Gao // SECTION: GPIO Settings 1291ce81151cSLikun Gao 1292ce81151cSLikun Gao uint8_t LedOffGpio; 1293ce81151cSLikun Gao uint8_t FanOffGpio; 1294ce81151cSLikun Gao uint8_t GfxVrPowerStageOffGpio; 1295ce81151cSLikun Gao 1296ce81151cSLikun Gao uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 1297ce81151cSLikun Gao uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 1298ce81151cSLikun Gao uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 1299ce81151cSLikun Gao uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 1300ce81151cSLikun Gao 1301ce81151cSLikun Gao uint8_t GthrGpio; // GPIO pin configured for GTHR Event 1302ce81151cSLikun Gao uint8_t GthrPolarity; // replace GPIO polarity for GTHR 1303ce81151cSLikun Gao 1304ce81151cSLikun Gao // LED Display Settings 1305ce81151cSLikun Gao uint8_t LedPin0; // GPIO number for LedPin[0] 1306ce81151cSLikun Gao uint8_t LedPin1; // GPIO number for LedPin[1] 1307ce81151cSLikun Gao uint8_t LedPin2; // GPIO number for LedPin[2] 1308ce81151cSLikun Gao uint8_t LedEnableMask; 1309ce81151cSLikun Gao 1310ce81151cSLikun Gao uint8_t LedPcie; // GPIO number for PCIE results 1311ce81151cSLikun Gao uint8_t LedError; // GPIO number for Error Cases 1312ce81151cSLikun Gao 1313ce81151cSLikun Gao // SECTION: Clock Spread Spectrum 1314ce81151cSLikun Gao 1315ce81151cSLikun Gao // UCLK Spread Spectrum 1316da1acbb1SEvan Quan uint8_t UclkTrainingModeSpreadPercent; 1317da1acbb1SEvan Quan uint8_t UclkSpreadPadding; 1318ce81151cSLikun Gao uint16_t UclkSpreadFreq; // kHz 1319ce81151cSLikun Gao 1320ce81151cSLikun Gao // UCLK Spread Spectrum 1321ce81151cSLikun Gao uint8_t UclkSpreadPercent[MEM_VENDOR_COUNT]; 1322ce81151cSLikun Gao 1323ce81151cSLikun Gao // FCLK Spread Spectrum 1324ce81151cSLikun Gao uint8_t FclkSpreadPadding; 1325ce81151cSLikun Gao uint8_t FclkSpreadPercent; // Q4.4 1326ce81151cSLikun Gao uint16_t FclkSpreadFreq; // kHz 1327ce81151cSLikun Gao 1328ce81151cSLikun Gao // Section: Memory Config 1329ce81151cSLikun Gao uint8_t DramWidth; // Width of interface to the channel for each DRAM module. See DRAM_BIT_WIDTH_TYPE_e 1330da1acbb1SEvan Quan uint8_t PaddingMem1[7]; 1331ce81151cSLikun Gao 1332ce81151cSLikun Gao // SECTION: UMC feature flags 1333ce81151cSLikun Gao uint8_t HsrEnabled; 1334ce81151cSLikun Gao uint8_t VddqOffEnabled; 1335ce81151cSLikun Gao uint8_t PaddingUmcFlags[2]; 1336ce81151cSLikun Gao 1337ce81151cSLikun Gao uint32_t PostVoltageSetBacoDelay; // in microseconds. Amount of time FW will wait after power good is established or PSI0 command is issued 1338ce81151cSLikun Gao uint32_t BacoEntryDelay; // in milliseconds. Amount of time FW will wait to trigger BACO entry after receiving entry notification from OS 1339ce81151cSLikun Gao 13407e5632cdSKenneth Feng uint8_t FuseWritePowerMuxPresent; 13417e5632cdSKenneth Feng uint8_t FuseWritePadding[3]; 13427e5632cdSKenneth Feng 1343ce81151cSLikun Gao // SECTION: Board Reserved 13447e5632cdSKenneth Feng uint32_t BoardSpare[63]; 1345ce81151cSLikun Gao 1346ce81151cSLikun Gao // SECTION: Structure Padding 1347ce81151cSLikun Gao 1348ce81151cSLikun Gao // Padding for MMHUB - do not modify this 1349ce81151cSLikun Gao uint32_t MmHubPadding[8]; 1350ce81151cSLikun Gao } BoardTable_t; 1351ce81151cSLikun Gao 1352f989fa29SJonathan Gray #pragma pack(push, 1) 1353ce81151cSLikun Gao typedef struct { 1354ce81151cSLikun Gao SkuTable_t SkuTable; 1355ce81151cSLikun Gao BoardTable_t BoardTable; 1356ce81151cSLikun Gao } PPTable_t; 1357f989fa29SJonathan Gray #pragma pack(pop) 1358ce81151cSLikun Gao 1359ce81151cSLikun Gao typedef struct { 1360ce81151cSLikun Gao // Time constant parameters for clock averages in ms 1361ce81151cSLikun Gao uint16_t GfxclkAverageLpfTau; 1362ce81151cSLikun Gao uint16_t FclkAverageLpfTau; 1363ce81151cSLikun Gao uint16_t UclkAverageLpfTau; 1364ce81151cSLikun Gao uint16_t GfxActivityLpfTau; 1365ce81151cSLikun Gao uint16_t UclkActivityLpfTau; 1366ce81151cSLikun Gao uint16_t SocketPowerLpfTau; 1367ce81151cSLikun Gao uint16_t VcnClkAverageLpfTau; 1368ce81151cSLikun Gao uint16_t VcnUsageAverageLpfTau; 1369ce81151cSLikun Gao } DriverSmuConfig_t; 1370ce81151cSLikun Gao 1371ce81151cSLikun Gao typedef struct { 1372ce81151cSLikun Gao DriverSmuConfig_t DriverSmuConfig; 1373ce81151cSLikun Gao 1374ce81151cSLikun Gao uint32_t Spare[8]; 1375ce81151cSLikun Gao // Padding - ignore 1376ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1377ce81151cSLikun Gao } DriverSmuConfigExternal_t; 1378ce81151cSLikun Gao 1379ce81151cSLikun Gao 1380ce81151cSLikun Gao typedef struct { 1381ce81151cSLikun Gao 1382ce81151cSLikun Gao uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1383ce81151cSLikun Gao uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1384ce81151cSLikun Gao uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1385ce81151cSLikun Gao uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1386ce81151cSLikun Gao uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1387ce81151cSLikun Gao uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1388ce81151cSLikun Gao uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1389ce81151cSLikun Gao uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1390ce81151cSLikun Gao uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1391ce81151cSLikun Gao uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1392ce81151cSLikun Gao uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1393ce81151cSLikun Gao 1394ce81151cSLikun Gao uint16_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1395ce81151cSLikun Gao 1396ce81151cSLikun Gao uint16_t Padding; 1397ce81151cSLikun Gao 1398ce81151cSLikun Gao uint32_t Spare[32]; 1399ce81151cSLikun Gao 1400ce81151cSLikun Gao // Padding - ignore 1401ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1402ce81151cSLikun Gao 1403ce81151cSLikun Gao } DriverInfoTable_t; 1404ce81151cSLikun Gao 1405ce81151cSLikun Gao typedef struct { 1406ce81151cSLikun Gao uint32_t CurrClock[PPCLK_COUNT]; 1407ce81151cSLikun Gao 1408ce81151cSLikun Gao uint16_t AverageGfxclkFrequencyTarget; 1409ce81151cSLikun Gao uint16_t AverageGfxclkFrequencyPreDs; 1410ce81151cSLikun Gao uint16_t AverageGfxclkFrequencyPostDs; 1411ce81151cSLikun Gao uint16_t AverageFclkFrequencyPreDs; 1412ce81151cSLikun Gao uint16_t AverageFclkFrequencyPostDs; 1413ce81151cSLikun Gao uint16_t AverageMemclkFrequencyPreDs ; // this is scaled to actual memory clock 1414ce81151cSLikun Gao uint16_t AverageMemclkFrequencyPostDs ; // this is scaled to actual memory clock 1415ce81151cSLikun Gao uint16_t AverageVclk0Frequency ; 1416ce81151cSLikun Gao uint16_t AverageDclk0Frequency ; 1417ce81151cSLikun Gao uint16_t AverageVclk1Frequency ; 1418ce81151cSLikun Gao uint16_t AverageDclk1Frequency ; 141966f54992SEvan Quan uint16_t PCIeBusy; 142066f54992SEvan Quan uint16_t dGPU_W_MAX; 142166f54992SEvan Quan uint16_t padding; 142266f54992SEvan Quan 142366f54992SEvan Quan uint32_t MetricsCounter; 1424ce81151cSLikun Gao 1425ce81151cSLikun Gao uint16_t AvgVoltage[SVI_PLANE_COUNT]; 142666f54992SEvan Quan uint16_t AvgCurrent[SVI_PLANE_COUNT]; 1427ce81151cSLikun Gao 1428ce81151cSLikun Gao uint16_t AverageGfxActivity ; 1429ce81151cSLikun Gao uint16_t AverageUclkActivity ; 1430ce81151cSLikun Gao uint16_t Vcn0ActivityPercentage ; 1431ce81151cSLikun Gao uint16_t Vcn1ActivityPercentage ; 1432ce81151cSLikun Gao 1433ce81151cSLikun Gao uint32_t EnergyAccumulator; 1434ce81151cSLikun Gao uint16_t AverageSocketPower; 1435da1acbb1SEvan Quan uint16_t AverageTotalBoardPower; 1436da1acbb1SEvan Quan 1437ce81151cSLikun Gao uint16_t AvgTemperature[TEMP_COUNT]; 14387e5632cdSKenneth Feng uint16_t AvgTemperatureFanIntake; 1439ce81151cSLikun Gao 1440ce81151cSLikun Gao uint8_t PcieRate ; 1441ce81151cSLikun Gao uint8_t PcieWidth ; 1442ce81151cSLikun Gao 1443ce81151cSLikun Gao uint8_t AvgFanPwm; 1444ce81151cSLikun Gao uint8_t Padding[1]; 1445ce81151cSLikun Gao uint16_t AvgFanRpm; 1446ce81151cSLikun Gao 1447ce81151cSLikun Gao 1448ce81151cSLikun Gao uint8_t ThrottlingPercentage[THROTTLER_COUNT]; 1449ce81151cSLikun Gao 1450ce81151cSLikun Gao //metrics for D3hot entry/exit and driver ARM msgs 1451ce81151cSLikun Gao uint32_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; 1452ce81151cSLikun Gao uint32_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT]; 1453ce81151cSLikun Gao uint32_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT]; 1454ce81151cSLikun Gao 1455ce81151cSLikun Gao uint16_t ApuSTAPMSmartShiftLimit; 1456ce81151cSLikun Gao uint16_t ApuSTAPMLimit; 1457ce81151cSLikun Gao uint16_t AvgApuSocketPower; 1458ce81151cSLikun Gao 1459ce81151cSLikun Gao uint16_t AverageUclkActivity_MAX; 1460ce81151cSLikun Gao 1461ce81151cSLikun Gao uint32_t PublicSerialNumberLower; 1462ce81151cSLikun Gao uint32_t PublicSerialNumberUpper; 1463ce81151cSLikun Gao 1464ce81151cSLikun Gao } SmuMetrics_t; 1465ce81151cSLikun Gao 1466ce81151cSLikun Gao typedef struct { 1467ce81151cSLikun Gao SmuMetrics_t SmuMetrics; 1468ce81151cSLikun Gao uint32_t Spare[30]; 1469ce81151cSLikun Gao 1470ce81151cSLikun Gao // Padding - ignore 1471ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1472ce81151cSLikun Gao } SmuMetricsExternal_t; 1473ce81151cSLikun Gao 1474ce81151cSLikun Gao typedef struct { 1475ce81151cSLikun Gao uint8_t WmSetting; 1476ce81151cSLikun Gao uint8_t Flags; 1477ce81151cSLikun Gao uint8_t Padding[2]; 1478ce81151cSLikun Gao 1479ce81151cSLikun Gao } WatermarkRowGeneric_t; 1480ce81151cSLikun Gao 1481ce81151cSLikun Gao #define NUM_WM_RANGES 4 1482ce81151cSLikun Gao 1483ce81151cSLikun Gao typedef enum { 1484ce81151cSLikun Gao WATERMARKS_CLOCK_RANGE = 0, 1485ce81151cSLikun Gao WATERMARKS_DUMMY_PSTATE, 1486ce81151cSLikun Gao WATERMARKS_MALL, 1487ce81151cSLikun Gao WATERMARKS_COUNT, 1488ce81151cSLikun Gao } WATERMARKS_FLAGS_e; 1489ce81151cSLikun Gao 1490ce81151cSLikun Gao typedef struct { 1491ce81151cSLikun Gao // Watermarks 1492ce81151cSLikun Gao WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES]; 1493ce81151cSLikun Gao } Watermarks_t; 1494ce81151cSLikun Gao 1495ce81151cSLikun Gao typedef struct { 1496ce81151cSLikun Gao Watermarks_t Watermarks; 1497ce81151cSLikun Gao uint32_t Spare[16]; 1498ce81151cSLikun Gao 1499ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1500ce81151cSLikun Gao } WatermarksExternal_t; 1501ce81151cSLikun Gao 1502ce81151cSLikun Gao typedef struct { 1503ce81151cSLikun Gao uint16_t avgPsmCount[214]; 1504ce81151cSLikun Gao uint16_t minPsmCount[214]; 1505ce81151cSLikun Gao float avgPsmVoltage[214]; 1506ce81151cSLikun Gao float minPsmVoltage[214]; 1507ce81151cSLikun Gao } AvfsDebugTable_t; 1508ce81151cSLikun Gao 1509ce81151cSLikun Gao typedef struct { 1510ce81151cSLikun Gao AvfsDebugTable_t AvfsDebugTable; 1511ce81151cSLikun Gao 1512ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1513ce81151cSLikun Gao } AvfsDebugTableExternal_t; 1514ce81151cSLikun Gao 1515ce81151cSLikun Gao 1516ce81151cSLikun Gao typedef struct { 1517ce81151cSLikun Gao uint8_t Gfx_ActiveHystLimit; 1518ce81151cSLikun Gao uint8_t Gfx_IdleHystLimit; 1519ce81151cSLikun Gao uint8_t Gfx_FPS; 1520ce81151cSLikun Gao uint8_t Gfx_MinActiveFreqType; 1521ce81151cSLikun Gao uint8_t Gfx_BoosterFreqType; 1522ce81151cSLikun Gao uint8_t PaddingGfx; 1523ce81151cSLikun Gao uint16_t Gfx_MinActiveFreq; // MHz 1524ce81151cSLikun Gao uint16_t Gfx_BoosterFreq; // MHz 1525ce81151cSLikun Gao uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms 1526ce81151cSLikun Gao uint32_t Gfx_PD_Data_limit_a; // Q16 1527ce81151cSLikun Gao uint32_t Gfx_PD_Data_limit_b; // Q16 1528ce81151cSLikun Gao uint32_t Gfx_PD_Data_limit_c; // Q16 1529ce81151cSLikun Gao uint32_t Gfx_PD_Data_error_coeff; // Q16 1530ce81151cSLikun Gao uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 1531ce81151cSLikun Gao 1532ce81151cSLikun Gao uint8_t Fclk_ActiveHystLimit; 1533ce81151cSLikun Gao uint8_t Fclk_IdleHystLimit; 1534ce81151cSLikun Gao uint8_t Fclk_FPS; 1535ce81151cSLikun Gao uint8_t Fclk_MinActiveFreqType; 1536ce81151cSLikun Gao uint8_t Fclk_BoosterFreqType; 1537ce81151cSLikun Gao uint8_t PaddingFclk; 1538ce81151cSLikun Gao uint16_t Fclk_MinActiveFreq; // MHz 1539ce81151cSLikun Gao uint16_t Fclk_BoosterFreq; // MHz 1540ce81151cSLikun Gao uint16_t Fclk_PD_Data_time_constant; // Time constant of PD controller in ms 1541ce81151cSLikun Gao uint32_t Fclk_PD_Data_limit_a; // Q16 1542ce81151cSLikun Gao uint32_t Fclk_PD_Data_limit_b; // Q16 1543ce81151cSLikun Gao uint32_t Fclk_PD_Data_limit_c; // Q16 1544ce81151cSLikun Gao uint32_t Fclk_PD_Data_error_coeff; // Q16 1545ce81151cSLikun Gao uint32_t Fclk_PD_Data_error_rate_coeff; // Q16 1546ce81151cSLikun Gao 1547ce81151cSLikun Gao uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16 1548ce81151cSLikun Gao uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS]; 1549ce81151cSLikun Gao uint8_t Mem_DownHystLimit[NUM_UCLK_DPM_LEVELS]; 1550ce81151cSLikun Gao uint16_t Mem_Fps; 1551ce81151cSLikun Gao uint8_t padding[2]; 1552ce81151cSLikun Gao 1553ce81151cSLikun Gao } DpmActivityMonitorCoeffInt_t; 1554ce81151cSLikun Gao 1555ce81151cSLikun Gao 1556ce81151cSLikun Gao typedef struct { 1557ce81151cSLikun Gao DpmActivityMonitorCoeffInt_t DpmActivityMonitorCoeffInt; 1558ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1559ce81151cSLikun Gao } DpmActivityMonitorCoeffIntExternal_t; 1560ce81151cSLikun Gao 1561ce81151cSLikun Gao 1562ce81151cSLikun Gao 1563ce81151cSLikun Gao // Workload bits 1564ce81151cSLikun Gao #define WORKLOAD_PPLIB_DEFAULT_BIT 0 1565ce81151cSLikun Gao #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 1566ce81151cSLikun Gao #define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 1567ce81151cSLikun Gao #define WORKLOAD_PPLIB_VIDEO_BIT 3 1568ce81151cSLikun Gao #define WORKLOAD_PPLIB_VR_BIT 4 1569ce81151cSLikun Gao #define WORKLOAD_PPLIB_COMPUTE_BIT 5 1570ce81151cSLikun Gao #define WORKLOAD_PPLIB_CUSTOM_BIT 6 1571ce81151cSLikun Gao #define WORKLOAD_PPLIB_WINDOW_3D_BIT 7 1572ce81151cSLikun Gao #define WORKLOAD_PPLIB_COUNT 8 1573ce81151cSLikun Gao 1574ce81151cSLikun Gao 1575ce81151cSLikun Gao // These defines are used with the following messages: 1576ce81151cSLikun Gao // SMC_MSG_TransferTableDram2Smu 1577ce81151cSLikun Gao // SMC_MSG_TransferTableSmu2Dram 1578ce81151cSLikun Gao 1579ce81151cSLikun Gao // Table transfer status 1580ce81151cSLikun Gao #define TABLE_TRANSFER_OK 0x0 1581ce81151cSLikun Gao #define TABLE_TRANSFER_FAILED 0xFF 1582ce81151cSLikun Gao #define TABLE_TRANSFER_PENDING 0xAB 1583ce81151cSLikun Gao 1584ce81151cSLikun Gao // Table types 1585ce81151cSLikun Gao #define TABLE_PPTABLE 0 1586ce81151cSLikun Gao #define TABLE_COMBO_PPTABLE 1 1587ce81151cSLikun Gao #define TABLE_WATERMARKS 2 1588ce81151cSLikun Gao #define TABLE_AVFS_PSM_DEBUG 3 1589ce81151cSLikun Gao #define TABLE_PMSTATUSLOG 4 1590ce81151cSLikun Gao #define TABLE_SMU_METRICS 5 1591ce81151cSLikun Gao #define TABLE_DRIVER_SMU_CONFIG 6 1592ce81151cSLikun Gao #define TABLE_ACTIVITY_MONITOR_COEFF 7 1593ce81151cSLikun Gao #define TABLE_OVERDRIVE 8 1594ce81151cSLikun Gao #define TABLE_I2C_COMMANDS 9 1595ce81151cSLikun Gao #define TABLE_DRIVER_INFO 10 1596ce81151cSLikun Gao #define TABLE_ECCINFO 11 1597ce81151cSLikun Gao #define TABLE_COUNT 12 1598ce81151cSLikun Gao 1599ce81151cSLikun Gao //IH Interupt ID 1600ce81151cSLikun Gao #define IH_INTERRUPT_ID_TO_DRIVER 0xFE 1601ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_BACO 0x2 1602ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_AC 0x3 1603ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_DC 0x4 1604ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 0x5 1605ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 0x6 1606ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING 0x7 16077e5632cdSKenneth Feng #define IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL 0x8 16087e5632cdSKenneth Feng #define IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY 0x9 1609ce81151cSLikun Gao 1610ce81151cSLikun Gao #endif 1611