1ce81151cSLikun Gao /* 2ce81151cSLikun Gao * Copyright 2021 Advanced Micro Devices, Inc. 3ce81151cSLikun Gao * 4ce81151cSLikun Gao * Permission is hereby granted, free of charge, to any person obtaining a 5ce81151cSLikun Gao * copy of this software and associated documentation files (the "Software"), 6ce81151cSLikun Gao * to deal in the Software without restriction, including without limitation 7ce81151cSLikun Gao * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8ce81151cSLikun Gao * and/or sell copies of the Software, and to permit persons to whom the 9ce81151cSLikun Gao * Software is furnished to do so, subject to the following conditions: 10ce81151cSLikun Gao * 11ce81151cSLikun Gao * The above copyright notice and this permission notice shall be included in 12ce81151cSLikun Gao * all copies or substantial portions of the Software. 13ce81151cSLikun Gao * 14ce81151cSLikun Gao * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15ce81151cSLikun Gao * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16ce81151cSLikun Gao * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17ce81151cSLikun Gao * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18ce81151cSLikun Gao * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19ce81151cSLikun Gao * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20ce81151cSLikun Gao * OTHER DEALINGS IN THE SOFTWARE. 21ce81151cSLikun Gao * 22ce81151cSLikun Gao */ 23ce81151cSLikun Gao 24ce81151cSLikun Gao #ifndef SMU13_DRIVER_IF_V13_0_0_H 25ce81151cSLikun Gao #define SMU13_DRIVER_IF_V13_0_0_H 26ce81151cSLikun Gao 27ce81151cSLikun Gao // *** IMPORTANT *** 28ce81151cSLikun Gao // PMFW TEAM: Always increment the interface version on any change to this file 29ce81151cSLikun Gao #define SMU13_DRIVER_IF_VERSION 0x23 30ce81151cSLikun Gao 31ce81151cSLikun Gao //Increment this version if SkuTable_t or BoardTable_t change 32ce81151cSLikun Gao #define PPTABLE_VERSION 0x1D 33ce81151cSLikun Gao 34ce81151cSLikun Gao #define NUM_GFXCLK_DPM_LEVELS 16 35ce81151cSLikun Gao #define NUM_SOCCLK_DPM_LEVELS 8 36ce81151cSLikun Gao #define NUM_MP0CLK_DPM_LEVELS 2 37ce81151cSLikun Gao #define NUM_DCLK_DPM_LEVELS 8 38ce81151cSLikun Gao #define NUM_VCLK_DPM_LEVELS 8 39ce81151cSLikun Gao #define NUM_DISPCLK_DPM_LEVELS 8 40ce81151cSLikun Gao #define NUM_DPPCLK_DPM_LEVELS 8 41ce81151cSLikun Gao #define NUM_DPREFCLK_DPM_LEVELS 8 42ce81151cSLikun Gao #define NUM_DCFCLK_DPM_LEVELS 8 43ce81151cSLikun Gao #define NUM_DTBCLK_DPM_LEVELS 8 44ce81151cSLikun Gao #define NUM_UCLK_DPM_LEVELS 4 45ce81151cSLikun Gao #define NUM_LINK_LEVELS 3 46ce81151cSLikun Gao #define NUM_FCLK_DPM_LEVELS 8 47ce81151cSLikun Gao #define NUM_OD_FAN_MAX_POINTS 6 48ce81151cSLikun Gao 49ce81151cSLikun Gao // Feature Control Defines 50ce81151cSLikun Gao #define FEATURE_FW_DATA_READ_BIT 0 51ce81151cSLikun Gao #define FEATURE_DPM_GFXCLK_BIT 1 52ce81151cSLikun Gao #define FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT 2 53ce81151cSLikun Gao #define FEATURE_DPM_UCLK_BIT 3 54ce81151cSLikun Gao #define FEATURE_DPM_FCLK_BIT 4 55ce81151cSLikun Gao #define FEATURE_DPM_SOCCLK_BIT 5 56ce81151cSLikun Gao #define FEATURE_DPM_MP0CLK_BIT 6 57ce81151cSLikun Gao #define FEATURE_DPM_LINK_BIT 7 58ce81151cSLikun Gao #define FEATURE_DPM_DCN_BIT 8 59ce81151cSLikun Gao #define FEATURE_VMEMP_SCALING_BIT 9 60ce81151cSLikun Gao #define FEATURE_VDDIO_MEM_SCALING_BIT 10 61ce81151cSLikun Gao #define FEATURE_DS_GFXCLK_BIT 11 62ce81151cSLikun Gao #define FEATURE_DS_SOCCLK_BIT 12 63ce81151cSLikun Gao #define FEATURE_DS_FCLK_BIT 13 64ce81151cSLikun Gao #define FEATURE_DS_LCLK_BIT 14 65ce81151cSLikun Gao #define FEATURE_DS_DCFCLK_BIT 15 66ce81151cSLikun Gao #define FEATURE_DS_UCLK_BIT 16 67ce81151cSLikun Gao #define FEATURE_GFX_ULV_BIT 17 68ce81151cSLikun Gao #define FEATURE_FW_DSTATE_BIT 18 69ce81151cSLikun Gao #define FEATURE_GFXOFF_BIT 19 70ce81151cSLikun Gao #define FEATURE_BACO_BIT 20 71ce81151cSLikun Gao #define FEATURE_MM_DPM_BIT 21 72ce81151cSLikun Gao #define FEATURE_SOC_MPCLK_DS_BIT 22 73ce81151cSLikun Gao #define FEATURE_BACO_MPCLK_DS_BIT 23 74ce81151cSLikun Gao #define FEATURE_THROTTLERS_BIT 24 75ce81151cSLikun Gao #define FEATURE_SMARTSHIFT_BIT 25 76ce81151cSLikun Gao #define FEATURE_GTHR_BIT 26 77ce81151cSLikun Gao #define FEATURE_ACDC_BIT 27 78ce81151cSLikun Gao #define FEATURE_VR0HOT_BIT 28 79ce81151cSLikun Gao #define FEATURE_FW_CTF_BIT 29 80ce81151cSLikun Gao #define FEATURE_FAN_CONTROL_BIT 30 81ce81151cSLikun Gao #define FEATURE_GFX_DCS_BIT 31 82ce81151cSLikun Gao #define FEATURE_GFX_READ_MARGIN_BIT 32 83ce81151cSLikun Gao #define FEATURE_LED_DISPLAY_BIT 33 84ce81151cSLikun Gao #define FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT 34 85ce81151cSLikun Gao #define FEATURE_OUT_OF_BAND_MONITOR_BIT 35 86ce81151cSLikun Gao #define FEATURE_OPTIMIZED_VMIN_BIT 36 87ce81151cSLikun Gao #define FEATURE_GFX_IMU_BIT 37 88ce81151cSLikun Gao #define FEATURE_BOOT_TIME_CAL_BIT 38 89ce81151cSLikun Gao #define FEATURE_GFX_PCC_DFLL_BIT 39 90ce81151cSLikun Gao #define FEATURE_SOC_CG_BIT 40 91ce81151cSLikun Gao #define FEATURE_DF_CSTATE_BIT 41 92ce81151cSLikun Gao #define FEATURE_GFX_EDC_BIT 42 93ce81151cSLikun Gao #define FEATURE_BOOT_POWER_OPT_BIT 43 94ce81151cSLikun Gao #define FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT 44 95ce81151cSLikun Gao #define FEATURE_DS_VCN_BIT 45 96ce81151cSLikun Gao #define FEATURE_BACO_CG_BIT 46 97ce81151cSLikun Gao #define FEATURE_MEM_TEMP_READ_BIT 47 98ce81151cSLikun Gao #define FEATURE_ATHUB_MMHUB_PG_BIT 48 99ce81151cSLikun Gao #define FEATURE_SOC_PCC_BIT 49 100ce81151cSLikun Gao #define FEATURE_SPARE_50_BIT 50 101ce81151cSLikun Gao #define FEATURE_SPARE_51_BIT 51 102ce81151cSLikun Gao #define FEATURE_SPARE_52_BIT 52 103ce81151cSLikun Gao #define FEATURE_SPARE_53_BIT 53 104ce81151cSLikun Gao #define FEATURE_SPARE_54_BIT 54 105ce81151cSLikun Gao #define FEATURE_SPARE_55_BIT 55 106ce81151cSLikun Gao #define FEATURE_SPARE_56_BIT 56 107ce81151cSLikun Gao #define FEATURE_SPARE_57_BIT 57 108ce81151cSLikun Gao #define FEATURE_SPARE_58_BIT 58 109ce81151cSLikun Gao #define FEATURE_SPARE_59_BIT 59 110ce81151cSLikun Gao #define FEATURE_SPARE_60_BIT 60 111ce81151cSLikun Gao #define FEATURE_SPARE_61_BIT 61 112ce81151cSLikun Gao #define FEATURE_SPARE_62_BIT 62 113ce81151cSLikun Gao #define FEATURE_SPARE_63_BIT 63 114ce81151cSLikun Gao #define NUM_FEATURES 64 115ce81151cSLikun Gao 116ce81151cSLikun Gao //For use with feature control messages 117ce81151cSLikun Gao typedef enum { 118ce81151cSLikun Gao FEATURE_PWR_ALL, 119ce81151cSLikun Gao FEATURE_PWR_S5, 120ce81151cSLikun Gao FEATURE_PWR_BACO, 121ce81151cSLikun Gao FEATURE_PWR_SOC, 122ce81151cSLikun Gao FEATURE_PWR_GFX, 123ce81151cSLikun Gao FEATURE_PWR_DOMAIN_COUNT, 124ce81151cSLikun Gao } FEATURE_PWR_DOMAIN_e; 125ce81151cSLikun Gao 126ce81151cSLikun Gao 127ce81151cSLikun Gao // Debug Overrides Bitmask 128ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000001 129ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK 0x00000002 130ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK 0x00000004 131ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK 0x00000008 132ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x00000010 133ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_VCN_PG 0x00000020 134ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_FMAX_VMAX 0x00000040 135ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS 0x00000080 136ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK 0x00000100 137ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_DFLL 0x00000200 138ce81151cSLikun Gao #define DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE 0x00000400 139ce81151cSLikun Gao #define DEBUG_OVERRIDE_DFLL_MASTER_MODE 0x00000800 140ce81151cSLikun Gao 141ce81151cSLikun Gao // VR Mapping Bit Defines 142ce81151cSLikun Gao #define VR_MAPPING_VR_SELECT_MASK 0x01 143ce81151cSLikun Gao #define VR_MAPPING_VR_SELECT_SHIFT 0x00 144ce81151cSLikun Gao 145ce81151cSLikun Gao #define VR_MAPPING_PLANE_SELECT_MASK 0x02 146ce81151cSLikun Gao #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 147ce81151cSLikun Gao 148ce81151cSLikun Gao // PSI Bit Defines 149ce81151cSLikun Gao #define PSI_SEL_VR0_PLANE0_PSI0 0x01 150ce81151cSLikun Gao #define PSI_SEL_VR0_PLANE0_PSI1 0x02 151ce81151cSLikun Gao #define PSI_SEL_VR0_PLANE1_PSI0 0x04 152ce81151cSLikun Gao #define PSI_SEL_VR0_PLANE1_PSI1 0x08 153ce81151cSLikun Gao #define PSI_SEL_VR1_PLANE0_PSI0 0x10 154ce81151cSLikun Gao #define PSI_SEL_VR1_PLANE0_PSI1 0x20 155ce81151cSLikun Gao #define PSI_SEL_VR1_PLANE1_PSI0 0x40 156ce81151cSLikun Gao #define PSI_SEL_VR1_PLANE1_PSI1 0x80 157ce81151cSLikun Gao 158ce81151cSLikun Gao typedef enum { 159ce81151cSLikun Gao SVI_PSI_0, // Full phase count (default) 160ce81151cSLikun Gao SVI_PSI_1, // Phase count 1st level 161ce81151cSLikun Gao SVI_PSI_2, // Phase count 2nd level 162ce81151cSLikun Gao SVI_PSI_3, // Single phase operation + active diode emulation 163ce81151cSLikun Gao SVI_PSI_4, // Single phase operation + passive diode emulation *optional* 164ce81151cSLikun Gao SVI_PSI_5, // Reserved 165ce81151cSLikun Gao SVI_PSI_6, // Power down to 0V (voltage regulation disabled) 166ce81151cSLikun Gao SVI_PSI_7, // Automated phase shedding and diode emulation 167ce81151cSLikun Gao } SVI_PSI_e; 168ce81151cSLikun Gao 169ce81151cSLikun Gao // Throttler Control/Status Bits 170ce81151cSLikun Gao #define THROTTLER_TEMP_EDGE_BIT 0 171ce81151cSLikun Gao #define THROTTLER_TEMP_HOTSPOT_BIT 1 172ce81151cSLikun Gao #define THROTTLER_TEMP_HOTSPOT_G_BIT 2 173ce81151cSLikun Gao #define THROTTLER_TEMP_HOTSPOT_M_BIT 3 174ce81151cSLikun Gao #define THROTTLER_TEMP_MEM_BIT 4 175ce81151cSLikun Gao #define THROTTLER_TEMP_VR_GFX_BIT 5 176ce81151cSLikun Gao #define THROTTLER_TEMP_VR_MEM0_BIT 6 177ce81151cSLikun Gao #define THROTTLER_TEMP_VR_MEM1_BIT 7 178ce81151cSLikun Gao #define THROTTLER_TEMP_VR_SOC_BIT 8 179ce81151cSLikun Gao #define THROTTLER_TEMP_VR_U_BIT 9 180ce81151cSLikun Gao #define THROTTLER_TEMP_LIQUID0_BIT 10 181ce81151cSLikun Gao #define THROTTLER_TEMP_LIQUID1_BIT 11 182ce81151cSLikun Gao #define THROTTLER_TEMP_PLX_BIT 12 183ce81151cSLikun Gao #define THROTTLER_TDC_GFX_BIT 13 184ce81151cSLikun Gao #define THROTTLER_TDC_SOC_BIT 14 185ce81151cSLikun Gao #define THROTTLER_TDC_U_BIT 15 186ce81151cSLikun Gao #define THROTTLER_PPT0_BIT 16 187ce81151cSLikun Gao #define THROTTLER_PPT1_BIT 17 188ce81151cSLikun Gao #define THROTTLER_PPT2_BIT 18 189ce81151cSLikun Gao #define THROTTLER_PPT3_BIT 19 190ce81151cSLikun Gao #define THROTTLER_FIT_BIT 20 191ce81151cSLikun Gao #define THROTTLER_GFX_APCC_PLUS_BIT 21 192ce81151cSLikun Gao #define THROTTLER_COUNT 22 193ce81151cSLikun Gao 194ce81151cSLikun Gao // FW DState Features Control Bits 195ce81151cSLikun Gao #define FW_DSTATE_SOC_ULV_BIT 0 196ce81151cSLikun Gao #define FW_DSTATE_G6_HSR_BIT 1 197ce81151cSLikun Gao #define FW_DSTATE_G6_PHY_VMEMP_OFF_BIT 2 198ce81151cSLikun Gao #define FW_DSTATE_SMN_DS_BIT 3 199ce81151cSLikun Gao #define FW_DSTATE_MP1_WHISPER_MODE_BIT 4 200ce81151cSLikun Gao #define FW_DSTATE_SOC_LIV_MIN_BIT 5 201ce81151cSLikun Gao #define FW_DSTATE_SOC_PLL_PWRDN_BIT 6 202ce81151cSLikun Gao #define FW_DSTATE_MEM_PLL_PWRDN_BIT 7 203ce81151cSLikun Gao #define FW_DSTATE_MALL_ALLOC_BIT 8 204ce81151cSLikun Gao #define FW_DSTATE_MEM_PSI_BIT 9 205ce81151cSLikun Gao #define FW_DSTATE_HSR_NON_STROBE_BIT 10 206ce81151cSLikun Gao #define FW_DSTATE_MP0_ENTER_WFI_BIT 11 207ce81151cSLikun Gao #define FW_DSTATE_U_ULV_BIT 12 208ce81151cSLikun Gao #define FW_DSTATE_MALL_FLUSH_BIT 13 209ce81151cSLikun Gao #define FW_DSTATE_SOC_PSI_BIT 14 210ce81151cSLikun Gao #define FW_DSTATE_U_PSI_BIT 15 211ce81151cSLikun Gao #define FW_DSTATE_UCP_DS_BIT 16 212ce81151cSLikun Gao #define FW_DSTATE_CSRCLK_DS_BIT 17 213ce81151cSLikun Gao #define FW_DSTATE_MMHUB_INTERLOCK_BIT 18 214ce81151cSLikun Gao #define FW_DSTATE_D0i3_2_QUIET_FW_BIT 19 215ce81151cSLikun Gao #define FW_DSTATE_CLDO_PRG_BIT 20 216ce81151cSLikun Gao #define FW_DSTATE_DF_PLL_PWRDN_BIT 21 217ce81151cSLikun Gao #define FW_DSTATE_U_LOW_PWR_MODE_EN_BIT 22 218ce81151cSLikun Gao #define FW_DSTATE_GFX_PSI6_BIT 23 219ce81151cSLikun Gao #define FW_DSTATE_GFX_VR_PWR_STAGE_BIT 24 220ce81151cSLikun Gao 221ce81151cSLikun Gao //LED Display Mask & Control Bits 222ce81151cSLikun Gao #define LED_DISPLAY_GFX_DPM_BIT 0 223ce81151cSLikun Gao #define LED_DISPLAY_PCIE_BIT 1 224ce81151cSLikun Gao #define LED_DISPLAY_ERROR_BIT 2 225ce81151cSLikun Gao 226ce81151cSLikun Gao 227ce81151cSLikun Gao #define MEM_TEMP_READ_OUT_OF_BAND_BIT 0 228ce81151cSLikun Gao #define MEM_TEMP_READ_IN_BAND_REFRESH_BIT 1 229ce81151cSLikun Gao #define MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT 2 230ce81151cSLikun Gao 231ce81151cSLikun Gao typedef enum { 232ce81151cSLikun Gao SMARTSHIFT_VERSION_1, 233ce81151cSLikun Gao SMARTSHIFT_VERSION_2, 234ce81151cSLikun Gao SMARTSHIFT_VERSION_3, 235ce81151cSLikun Gao } SMARTSHIFT_VERSION_e; 236ce81151cSLikun Gao 237ce81151cSLikun Gao typedef enum { 238ce81151cSLikun Gao FOPT_CALC_AC_CALC_DC, 239ce81151cSLikun Gao FOPT_PPTABLE_AC_CALC_DC, 240ce81151cSLikun Gao FOPT_CALC_AC_PPTABLE_DC, 241ce81151cSLikun Gao FOPT_PPTABLE_AC_PPTABLE_DC, 242ce81151cSLikun Gao } FOPT_CALC_e; 243ce81151cSLikun Gao 244ce81151cSLikun Gao typedef enum { 245ce81151cSLikun Gao DRAM_BIT_WIDTH_DISABLED = 0, 246ce81151cSLikun Gao DRAM_BIT_WIDTH_X_8 = 8, 247ce81151cSLikun Gao DRAM_BIT_WIDTH_X_16 = 16, 248ce81151cSLikun Gao DRAM_BIT_WIDTH_X_32 = 32, 249ce81151cSLikun Gao DRAM_BIT_WIDTH_X_64 = 64, 250ce81151cSLikun Gao DRAM_BIT_WIDTH_X_128 = 128, 251ce81151cSLikun Gao DRAM_BIT_WIDTH_COUNT, 252ce81151cSLikun Gao } DRAM_BIT_WIDTH_TYPE_e; 253ce81151cSLikun Gao 254ce81151cSLikun Gao //I2C Interface 255ce81151cSLikun Gao #define NUM_I2C_CONTROLLERS 8 256ce81151cSLikun Gao 257ce81151cSLikun Gao #define I2C_CONTROLLER_ENABLED 1 258ce81151cSLikun Gao #define I2C_CONTROLLER_DISABLED 0 259ce81151cSLikun Gao 260ce81151cSLikun Gao #define MAX_SW_I2C_COMMANDS 24 261ce81151cSLikun Gao 262ce81151cSLikun Gao typedef enum { 263ce81151cSLikun Gao I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0 264ce81151cSLikun Gao I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1 265ce81151cSLikun Gao I2C_CONTROLLER_PORT_COUNT, 266ce81151cSLikun Gao } I2cControllerPort_e; 267ce81151cSLikun Gao 268ce81151cSLikun Gao typedef enum { 269ce81151cSLikun Gao I2C_CONTROLLER_NAME_VR_GFX = 0, 270ce81151cSLikun Gao I2C_CONTROLLER_NAME_VR_SOC, 271ce81151cSLikun Gao I2C_CONTROLLER_NAME_VR_VMEMP, 272ce81151cSLikun Gao I2C_CONTROLLER_NAME_VR_VDDIO, 273ce81151cSLikun Gao I2C_CONTROLLER_NAME_LIQUID0, 274ce81151cSLikun Gao I2C_CONTROLLER_NAME_LIQUID1, 275ce81151cSLikun Gao I2C_CONTROLLER_NAME_PLX, 276ce81151cSLikun Gao I2C_CONTROLLER_NAME_OTHER, 277ce81151cSLikun Gao I2C_CONTROLLER_NAME_COUNT, 278ce81151cSLikun Gao } I2cControllerName_e; 279ce81151cSLikun Gao 280ce81151cSLikun Gao typedef enum { 281ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 282ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_VR_GFX, 283ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_VR_SOC, 284ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_VR_VMEMP, 285ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_VR_VDDIO, 286ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_LIQUID0, 287ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_LIQUID1, 288ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_PLX, 289ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_INA3221, 290ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_COUNT, 291ce81151cSLikun Gao } I2cControllerThrottler_e; 292ce81151cSLikun Gao 293ce81151cSLikun Gao typedef enum { 294ce81151cSLikun Gao I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5, 295ce81151cSLikun Gao I2C_CONTROLLER_PROTOCOL_VR_IR35217, 296ce81151cSLikun Gao I2C_CONTROLLER_PROTOCOL_TMP_TMP102A, 297ce81151cSLikun Gao I2C_CONTROLLER_PROTOCOL_INA3221, 298ce81151cSLikun Gao I2C_CONTROLLER_PROTOCOL_COUNT, 299ce81151cSLikun Gao } I2cControllerProtocol_e; 300ce81151cSLikun Gao 301ce81151cSLikun Gao typedef struct { 302ce81151cSLikun Gao uint8_t Enabled; 303ce81151cSLikun Gao uint8_t Speed; 304ce81151cSLikun Gao uint8_t SlaveAddress; 305ce81151cSLikun Gao uint8_t ControllerPort; 306ce81151cSLikun Gao uint8_t ControllerName; 307ce81151cSLikun Gao uint8_t ThermalThrotter; 308ce81151cSLikun Gao uint8_t I2cProtocol; 309ce81151cSLikun Gao uint8_t PaddingConfig; 310ce81151cSLikun Gao } I2cControllerConfig_t; 311ce81151cSLikun Gao 312ce81151cSLikun Gao typedef enum { 313ce81151cSLikun Gao I2C_PORT_SVD_SCL = 0, 314ce81151cSLikun Gao I2C_PORT_GPIO, 315ce81151cSLikun Gao } I2cPort_e; 316ce81151cSLikun Gao 317ce81151cSLikun Gao typedef enum { 318ce81151cSLikun Gao I2C_SPEED_FAST_50K = 0, //50 Kbits/s 319ce81151cSLikun Gao I2C_SPEED_FAST_100K, //100 Kbits/s 320ce81151cSLikun Gao I2C_SPEED_FAST_400K, //400 Kbits/s 321ce81151cSLikun Gao I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 322ce81151cSLikun Gao I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 323ce81151cSLikun Gao I2C_SPEED_HIGH_2M, //2.3 Mbits/s 324ce81151cSLikun Gao I2C_SPEED_COUNT, 325ce81151cSLikun Gao } I2cSpeed_e; 326ce81151cSLikun Gao 327ce81151cSLikun Gao typedef enum { 328ce81151cSLikun Gao I2C_CMD_READ = 0, 329ce81151cSLikun Gao I2C_CMD_WRITE, 330ce81151cSLikun Gao I2C_CMD_COUNT, 331ce81151cSLikun Gao } I2cCmdType_e; 332ce81151cSLikun Gao 333ce81151cSLikun Gao #define CMDCONFIG_STOP_BIT 0 334ce81151cSLikun Gao #define CMDCONFIG_RESTART_BIT 1 335ce81151cSLikun Gao #define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write 336ce81151cSLikun Gao 337ce81151cSLikun Gao #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 338ce81151cSLikun Gao #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 339ce81151cSLikun Gao #define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT) 340ce81151cSLikun Gao 341ce81151cSLikun Gao typedef struct { 342ce81151cSLikun Gao uint8_t ReadWriteData; //Return data for read. Data to send for write 343ce81151cSLikun Gao uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write 344ce81151cSLikun Gao } SwI2cCmd_t; //SW I2C Command Table 345ce81151cSLikun Gao 346ce81151cSLikun Gao typedef struct { 347ce81151cSLikun Gao uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 348ce81151cSLikun Gao uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select 349ce81151cSLikun Gao uint8_t SlaveAddress; //Slave address of device 350ce81151cSLikun Gao uint8_t NumCmds; //Number of commands 351ce81151cSLikun Gao 352ce81151cSLikun Gao SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 353ce81151cSLikun Gao } SwI2cRequest_t; // SW I2C Request Table 354ce81151cSLikun Gao 355ce81151cSLikun Gao typedef struct { 356ce81151cSLikun Gao SwI2cRequest_t SwI2cRequest; 357ce81151cSLikun Gao 358ce81151cSLikun Gao uint32_t Spare[8]; 359ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 360ce81151cSLikun Gao } SwI2cRequestExternal_t; 361ce81151cSLikun Gao 362ce81151cSLikun Gao typedef struct { 363ce81151cSLikun Gao uint64_t mca_umc_status; 364ce81151cSLikun Gao uint64_t mca_umc_addr; 365ce81151cSLikun Gao 366ce81151cSLikun Gao uint16_t ce_count_lo_chip; 367ce81151cSLikun Gao uint16_t ce_count_hi_chip; 368ce81151cSLikun Gao 369ce81151cSLikun Gao uint32_t eccPadding; 370ce81151cSLikun Gao } EccInfo_t; 371ce81151cSLikun Gao 372ce81151cSLikun Gao typedef struct { 373ce81151cSLikun Gao EccInfo_t EccInfo[24]; 374ce81151cSLikun Gao } EccInfoTable_t; 375ce81151cSLikun Gao 376ce81151cSLikun Gao //D3HOT sequences 377ce81151cSLikun Gao typedef enum { 378ce81151cSLikun Gao BACO_SEQUENCE, 379ce81151cSLikun Gao MSR_SEQUENCE, 380ce81151cSLikun Gao BAMACO_SEQUENCE, 381ce81151cSLikun Gao ULPS_SEQUENCE, 382ce81151cSLikun Gao D3HOT_SEQUENCE_COUNT, 383ce81151cSLikun Gao } D3HOTSequence_e; 384ce81151cSLikun Gao 385ce81151cSLikun Gao //This is aligned with RSMU PGFSM Register Mapping 386ce81151cSLikun Gao typedef enum { 387ce81151cSLikun Gao PG_DYNAMIC_MODE = 0, 388ce81151cSLikun Gao PG_STATIC_MODE, 389ce81151cSLikun Gao } PowerGatingMode_e; 390ce81151cSLikun Gao 391ce81151cSLikun Gao //This is aligned with RSMU PGFSM Register Mapping 392ce81151cSLikun Gao typedef enum { 393ce81151cSLikun Gao PG_POWER_DOWN = 0, 394ce81151cSLikun Gao PG_POWER_UP, 395ce81151cSLikun Gao } PowerGatingSettings_e; 396ce81151cSLikun Gao 397ce81151cSLikun Gao typedef struct { 398ce81151cSLikun Gao uint32_t a; // store in IEEE float format in this variable 399ce81151cSLikun Gao uint32_t b; // store in IEEE float format in this variable 400ce81151cSLikun Gao uint32_t c; // store in IEEE float format in this variable 401ce81151cSLikun Gao } QuadraticInt_t; 402ce81151cSLikun Gao 403ce81151cSLikun Gao typedef struct { 404ce81151cSLikun Gao uint32_t m; // store in IEEE float format in this variable 405ce81151cSLikun Gao uint32_t b; // store in IEEE float format in this variable 406ce81151cSLikun Gao } LinearInt_t; 407ce81151cSLikun Gao 408ce81151cSLikun Gao typedef struct { 409ce81151cSLikun Gao uint32_t a; // store in IEEE float format in this variable 410ce81151cSLikun Gao uint32_t b; // store in IEEE float format in this variable 411ce81151cSLikun Gao uint32_t c; // store in IEEE float format in this variable 412ce81151cSLikun Gao } DroopInt_t; 413ce81151cSLikun Gao 414ce81151cSLikun Gao typedef enum { 415ce81151cSLikun Gao DCS_ARCH_DISABLED, 416ce81151cSLikun Gao DCS_ARCH_FADCS, 417ce81151cSLikun Gao DCS_ARCH_ASYNC, 418ce81151cSLikun Gao } DCS_ARCH_e; 419ce81151cSLikun Gao 420ce81151cSLikun Gao //Only Clks that have DPM descriptors are listed here 421ce81151cSLikun Gao typedef enum { 422ce81151cSLikun Gao PPCLK_GFXCLK = 0, 423ce81151cSLikun Gao PPCLK_SOCCLK, 424ce81151cSLikun Gao PPCLK_UCLK, 425ce81151cSLikun Gao PPCLK_FCLK, 426ce81151cSLikun Gao PPCLK_DCLK_0, 427ce81151cSLikun Gao PPCLK_VCLK_0, 428ce81151cSLikun Gao PPCLK_DCLK_1, 429ce81151cSLikun Gao PPCLK_VCLK_1, 430ce81151cSLikun Gao PPCLK_DISPCLK, 431ce81151cSLikun Gao PPCLK_DPPCLK, 432ce81151cSLikun Gao PPCLK_DPREFCLK, 433ce81151cSLikun Gao PPCLK_DCFCLK, 434ce81151cSLikun Gao PPCLK_DTBCLK, 435ce81151cSLikun Gao PPCLK_COUNT, 436ce81151cSLikun Gao } PPCLK_e; 437ce81151cSLikun Gao 438ce81151cSLikun Gao typedef enum { 439ce81151cSLikun Gao VOLTAGE_MODE_PPTABLE = 0, 440ce81151cSLikun Gao VOLTAGE_MODE_FUSES, 441ce81151cSLikun Gao VOLTAGE_MODE_COUNT, 442ce81151cSLikun Gao } VOLTAGE_MODE_e; 443ce81151cSLikun Gao 444ce81151cSLikun Gao 445ce81151cSLikun Gao typedef enum { 446ce81151cSLikun Gao AVFS_VOLTAGE_GFX = 0, 447ce81151cSLikun Gao AVFS_VOLTAGE_SOC, 448ce81151cSLikun Gao AVFS_VOLTAGE_COUNT, 449ce81151cSLikun Gao } AVFS_VOLTAGE_TYPE_e; 450ce81151cSLikun Gao 451ce81151cSLikun Gao typedef enum { 452ce81151cSLikun Gao AVFS_TEMP_COLD = 0, 453ce81151cSLikun Gao AVFS_TEMP_HOT, 454ce81151cSLikun Gao AVFS_TEMP_COUNT, 455ce81151cSLikun Gao } AVFS_TEMP_e; 456ce81151cSLikun Gao 457ce81151cSLikun Gao typedef enum { 458ce81151cSLikun Gao AVFS_D_G, 459ce81151cSLikun Gao AVFS_D_M_B, 460ce81151cSLikun Gao AVFS_D_M_S, 461ce81151cSLikun Gao AVFS_D_COUNT, 462ce81151cSLikun Gao } AVFS_D_e; 463ce81151cSLikun Gao 464ce81151cSLikun Gao typedef enum { 465ce81151cSLikun Gao UCLK_DIV_BY_1 = 0, 466ce81151cSLikun Gao UCLK_DIV_BY_2, 467ce81151cSLikun Gao UCLK_DIV_BY_4, 468ce81151cSLikun Gao UCLK_DIV_BY_8, 469ce81151cSLikun Gao } UCLK_DIV_e; 470ce81151cSLikun Gao 471ce81151cSLikun Gao typedef enum { 472ce81151cSLikun Gao GPIO_INT_POLARITY_ACTIVE_LOW = 0, 473ce81151cSLikun Gao GPIO_INT_POLARITY_ACTIVE_HIGH, 474ce81151cSLikun Gao } GpioIntPolarity_e; 475ce81151cSLikun Gao 476ce81151cSLikun Gao typedef enum { 477ce81151cSLikun Gao PWR_CONFIG_TDP = 0, 478ce81151cSLikun Gao PWR_CONFIG_TGP, 479ce81151cSLikun Gao PWR_CONFIG_TCP_ESTIMATED, 480ce81151cSLikun Gao PWR_CONFIG_TCP_MEASURED, 481ce81151cSLikun Gao } PwrConfig_e; 482ce81151cSLikun Gao 483ce81151cSLikun Gao typedef struct { 484ce81151cSLikun Gao uint8_t Padding; 485ce81151cSLikun Gao uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 486ce81151cSLikun Gao uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 487ce81151cSLikun Gao uint8_t CalculateFopt; // Indication whether FW should calculate Fopt or use values below. Reference FOPT_CALC_e 488ce81151cSLikun Gao LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 489ce81151cSLikun Gao uint32_t Padding3[3]; 490ce81151cSLikun Gao uint16_t Padding4; 491ce81151cSLikun Gao uint16_t FoptimalDc; //Foptimal frequency in DC power mode. 492ce81151cSLikun Gao uint16_t FoptimalAc; //Foptimal frequency in AC power mode. 493ce81151cSLikun Gao uint16_t Padding2; 494ce81151cSLikun Gao } DpmDescriptor_t; 495ce81151cSLikun Gao 496ce81151cSLikun Gao typedef enum { 497ce81151cSLikun Gao PPT_THROTTLER_PPT0, 498ce81151cSLikun Gao PPT_THROTTLER_PPT1, 499ce81151cSLikun Gao PPT_THROTTLER_PPT2, 500ce81151cSLikun Gao PPT_THROTTLER_PPT3, 501ce81151cSLikun Gao PPT_THROTTLER_COUNT 502ce81151cSLikun Gao } PPT_THROTTLER_e; 503ce81151cSLikun Gao 504ce81151cSLikun Gao typedef enum { 505ce81151cSLikun Gao TEMP_EDGE, 506ce81151cSLikun Gao TEMP_HOTSPOT, 507ce81151cSLikun Gao TEMP_HOTSPOT_G, 508ce81151cSLikun Gao TEMP_HOTSPOT_M, 509ce81151cSLikun Gao TEMP_MEM, 510ce81151cSLikun Gao TEMP_VR_GFX, 511ce81151cSLikun Gao TEMP_VR_MEM0, 512ce81151cSLikun Gao TEMP_VR_MEM1, 513ce81151cSLikun Gao TEMP_VR_SOC, 514ce81151cSLikun Gao TEMP_VR_U, 515ce81151cSLikun Gao TEMP_LIQUID0, 516ce81151cSLikun Gao TEMP_LIQUID1, 517ce81151cSLikun Gao TEMP_PLX, 518ce81151cSLikun Gao TEMP_COUNT, 519ce81151cSLikun Gao } TEMP_e; 520ce81151cSLikun Gao 521ce81151cSLikun Gao typedef enum { 522ce81151cSLikun Gao TDC_THROTTLER_GFX, 523ce81151cSLikun Gao TDC_THROTTLER_SOC, 524ce81151cSLikun Gao TDC_THROTTLER_U, 525ce81151cSLikun Gao TDC_THROTTLER_COUNT 526ce81151cSLikun Gao } TDC_THROTTLER_e; 527ce81151cSLikun Gao 528ce81151cSLikun Gao typedef enum { 529ce81151cSLikun Gao SVI_PLANE_GFX, 530ce81151cSLikun Gao SVI_PLANE_SOC, 531ce81151cSLikun Gao SVI_PLANE_VMEMP, 532ce81151cSLikun Gao SVI_PLANE_VDDIO_MEM, 533ce81151cSLikun Gao SVI_PLANE_U, 534ce81151cSLikun Gao SVI_PLANE_COUNT, 535ce81151cSLikun Gao } SVI_PLANE_e; 536ce81151cSLikun Gao 537ce81151cSLikun Gao typedef enum { 538ce81151cSLikun Gao PMFW_VOLT_PLANE_GFX, 539ce81151cSLikun Gao PMFW_VOLT_PLANE_SOC, 540ce81151cSLikun Gao PMFW_VOLT_PLANE_COUNT 541ce81151cSLikun Gao } PMFW_VOLT_PLANE_e; 542ce81151cSLikun Gao 543ce81151cSLikun Gao typedef enum { 544ce81151cSLikun Gao CUSTOMER_VARIANT_ROW, 545ce81151cSLikun Gao CUSTOMER_VARIANT_FALCON, 546ce81151cSLikun Gao CUSTOMER_VARIANT_COUNT, 547ce81151cSLikun Gao } CUSTOMER_VARIANT_e; 548ce81151cSLikun Gao 549ce81151cSLikun Gao typedef enum { 550ce81151cSLikun Gao POWER_SOURCE_AC, 551ce81151cSLikun Gao POWER_SOURCE_DC, 552ce81151cSLikun Gao POWER_SOURCE_COUNT, 553ce81151cSLikun Gao } POWER_SOURCE_e; 554ce81151cSLikun Gao 555ce81151cSLikun Gao typedef enum { 556ce81151cSLikun Gao MEM_VENDOR_SAMSUNG, 557ce81151cSLikun Gao MEM_VENDOR_INFINEON, 558ce81151cSLikun Gao MEM_VENDOR_ELPIDA, 559ce81151cSLikun Gao MEM_VENDOR_ETRON, 560ce81151cSLikun Gao MEM_VENDOR_NANYA, 561ce81151cSLikun Gao MEM_VENDOR_HYNIX, 562ce81151cSLikun Gao MEM_VENDOR_MOSEL, 563ce81151cSLikun Gao MEM_VENDOR_WINBOND, 564ce81151cSLikun Gao MEM_VENDOR_ESMT, 565ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER0, 566ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER1, 567ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER2, 568ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER3, 569ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER4, 570ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER5, 571ce81151cSLikun Gao MEM_VENDOR_MICRON, 572ce81151cSLikun Gao MEM_VENDOR_COUNT, 573ce81151cSLikun Gao } MEM_VENDOR_e; 574ce81151cSLikun Gao 575ce81151cSLikun Gao typedef enum { 576ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_CTL_ZONE0, 577ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_CTL_ZONE1, 578ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_CTL_ZONE2, 579ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_CTL_ZONE3, 580ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_CTL_ZONE4, 581ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0, 582ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0, 583ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1, 584ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1, 585ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2, 586ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2, 587ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3, 588ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3, 589ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4, 590ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4, 591ce81151cSLikun Gao PP_GRTAVFS_HW_ZONE0_VF, 592ce81151cSLikun Gao PP_GRTAVFS_HW_ZONE1_VF1, 593ce81151cSLikun Gao PP_GRTAVFS_HW_ZONE2_VF2, 594ce81151cSLikun Gao PP_GRTAVFS_HW_ZONE3_VF3, 595ce81151cSLikun Gao PP_GRTAVFS_HW_VOLTAGE_GB, 596ce81151cSLikun Gao PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0, 597ce81151cSLikun Gao PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1, 598ce81151cSLikun Gao PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2, 599ce81151cSLikun Gao PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3, 600ce81151cSLikun Gao PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4, 601ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_0, 602ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_1, 603ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_2, 604ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_3, 605ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_4, 606ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_5, 607ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_6, 608ce81151cSLikun Gao PP_GRTAVFS_HW_FUSE_COUNT, 609ce81151cSLikun Gao } PP_GRTAVFS_HW_FUSE_e; 610ce81151cSLikun Gao 611ce81151cSLikun Gao typedef enum { 612ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0, 613ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0, 614ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0, 615ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0, 616ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0, 617ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0, 618ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0, 619ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0, 620ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0, 621ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1, 622ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2, 623ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3, 624ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4, 625ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_FUSE_COUNT, 626ce81151cSLikun Gao } PP_GRTAVFS_FW_COMMON_FUSE_e; 627ce81151cSLikun Gao 628ce81151cSLikun Gao typedef enum { 629ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1, 630ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0, 631ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1, 632ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2, 633ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3, 634ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4, 635ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1, 636ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0, 637ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1, 638ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2, 639ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3, 640ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4, 641ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY, 642ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY, 643ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0, 644ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1, 645ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2, 646ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3, 647ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4, 648ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_COUNT, 649ce81151cSLikun Gao } PP_GRTAVFS_FW_SEP_FUSE_e; 650ce81151cSLikun Gao 651ce81151cSLikun Gao #define PP_NUM_RTAVFS_PWL_ZONES 5 652ce81151cSLikun Gao 653ce81151cSLikun Gao 654ce81151cSLikun Gao 655ce81151cSLikun Gao // VBIOS or PPLIB configures telemetry slope and offset. Only slope expected to be set for SVI3 656ce81151cSLikun Gao // Slope Q1.7, Offset Q1.2 657ce81151cSLikun Gao typedef struct { 658ce81151cSLikun Gao int8_t Offset; // in Amps 659ce81151cSLikun Gao uint8_t Padding; 660ce81151cSLikun Gao uint16_t MaxCurrent; // in Amps 661ce81151cSLikun Gao } SviTelemetryScale_t; 662ce81151cSLikun Gao 663ce81151cSLikun Gao #define PP_NUM_OD_VF_CURVE_POINTS PP_NUM_RTAVFS_PWL_ZONES + 1 664ce81151cSLikun Gao 665ce81151cSLikun Gao 666ce81151cSLikun Gao typedef struct { 667ce81151cSLikun Gao uint32_t FeatureCtrlMask; 668ce81151cSLikun Gao 669ce81151cSLikun Gao //Voltage control 670ce81151cSLikun Gao int16_t VoltageOffsetPerZoneBoundary[PP_NUM_OD_VF_CURVE_POINTS]; 671ce81151cSLikun Gao uint16_t reserved[2]; 672ce81151cSLikun Gao 673ce81151cSLikun Gao //Frequency changes 6741c65e548SEvan Quan int16_t GfxclkFmin; // MHz 6751c65e548SEvan Quan int16_t GfxclkFmax; // MHz 676ce81151cSLikun Gao uint16_t UclkFmin; // MHz 677ce81151cSLikun Gao uint16_t UclkFmax; // MHz 678ce81151cSLikun Gao 679ce81151cSLikun Gao //PPT 680ce81151cSLikun Gao int16_t Ppt; // % 681ce81151cSLikun Gao int16_t reserved1; 682ce81151cSLikun Gao 683ce81151cSLikun Gao //Fan control 684ce81151cSLikun Gao uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS]; 685ce81151cSLikun Gao uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS]; 686ce81151cSLikun Gao uint16_t FanMinimumPwm; 6871c65e548SEvan Quan uint16_t AcousticTargetRpmThreshold; 6881c65e548SEvan Quan uint16_t AcousticLimitRpmThreshold; 689ce81151cSLikun Gao uint16_t FanTargetTemperature; // Degree Celcius 690ce81151cSLikun Gao uint8_t FanZeroRpmEnable; 691ce81151cSLikun Gao uint8_t FanZeroRpmStopTemp; 692ce81151cSLikun Gao uint8_t FanMode; 6931c65e548SEvan Quan uint8_t MaxOpTemp; 694ce81151cSLikun Gao 695ce81151cSLikun Gao uint32_t Spare[13]; 696ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround 697ce81151cSLikun Gao } OverDriveTable_t; 698ce81151cSLikun Gao 699ce81151cSLikun Gao typedef struct { 700ce81151cSLikun Gao OverDriveTable_t OverDriveTable; 701ce81151cSLikun Gao 702ce81151cSLikun Gao } OverDriveTableExternal_t; 703ce81151cSLikun Gao 704ce81151cSLikun Gao typedef struct { 705ce81151cSLikun Gao uint32_t FeatureCtrlMask; 706ce81151cSLikun Gao 707ce81151cSLikun Gao int16_t VoltageOffsetPerZoneBoundary; 708ce81151cSLikun Gao uint16_t reserved[2]; 709ce81151cSLikun Gao 710ce81151cSLikun Gao uint16_t GfxclkFmin; // MHz 711ce81151cSLikun Gao uint16_t GfxclkFmax; // MHz 712ce81151cSLikun Gao uint16_t UclkFmin; // MHz 713ce81151cSLikun Gao uint16_t UclkFmax; // MHz 714ce81151cSLikun Gao 715ce81151cSLikun Gao //PPT 716ce81151cSLikun Gao int16_t Ppt; // % 717ce81151cSLikun Gao int16_t reserved1; 718ce81151cSLikun Gao 719ce81151cSLikun Gao uint8_t FanLinearPwmPoints; 720ce81151cSLikun Gao uint8_t FanLinearTempPoints; 721ce81151cSLikun Gao uint16_t FanMinimumPwm; 7221c65e548SEvan Quan uint16_t AcousticTargetRpmThreshold; 7231c65e548SEvan Quan uint16_t AcousticLimitRpmThreshold; 724ce81151cSLikun Gao uint16_t FanTargetTemperature; // Degree Celcius 725ce81151cSLikun Gao uint8_t FanZeroRpmEnable; 726ce81151cSLikun Gao uint8_t FanZeroRpmStopTemp; 727ce81151cSLikun Gao uint8_t FanMode; 7281c65e548SEvan Quan uint8_t MaxOpTemp; 729ce81151cSLikun Gao 730ce81151cSLikun Gao uint32_t Spare[13]; 731ce81151cSLikun Gao 732ce81151cSLikun Gao } OverDriveLimits_t; 733ce81151cSLikun Gao 734ce81151cSLikun Gao 735ce81151cSLikun Gao typedef enum { 736ce81151cSLikun Gao BOARD_GPIO_SMUIO_0, 737ce81151cSLikun Gao BOARD_GPIO_SMUIO_1, 738ce81151cSLikun Gao BOARD_GPIO_SMUIO_2, 739ce81151cSLikun Gao BOARD_GPIO_SMUIO_3, 740ce81151cSLikun Gao BOARD_GPIO_SMUIO_4, 741ce81151cSLikun Gao BOARD_GPIO_SMUIO_5, 742ce81151cSLikun Gao BOARD_GPIO_SMUIO_6, 743ce81151cSLikun Gao BOARD_GPIO_SMUIO_7, 744ce81151cSLikun Gao BOARD_GPIO_SMUIO_8, 745ce81151cSLikun Gao BOARD_GPIO_SMUIO_9, 746ce81151cSLikun Gao BOARD_GPIO_SMUIO_10, 747ce81151cSLikun Gao BOARD_GPIO_SMUIO_11, 748ce81151cSLikun Gao BOARD_GPIO_SMUIO_12, 749ce81151cSLikun Gao BOARD_GPIO_SMUIO_13, 750ce81151cSLikun Gao BOARD_GPIO_SMUIO_14, 751ce81151cSLikun Gao BOARD_GPIO_SMUIO_15, 752ce81151cSLikun Gao BOARD_GPIO_SMUIO_16, 753ce81151cSLikun Gao BOARD_GPIO_SMUIO_17, 754ce81151cSLikun Gao BOARD_GPIO_SMUIO_18, 755ce81151cSLikun Gao BOARD_GPIO_SMUIO_19, 756ce81151cSLikun Gao BOARD_GPIO_SMUIO_20, 757ce81151cSLikun Gao BOARD_GPIO_SMUIO_21, 758ce81151cSLikun Gao BOARD_GPIO_SMUIO_22, 759ce81151cSLikun Gao BOARD_GPIO_SMUIO_23, 760ce81151cSLikun Gao BOARD_GPIO_SMUIO_24, 761ce81151cSLikun Gao BOARD_GPIO_SMUIO_25, 762ce81151cSLikun Gao BOARD_GPIO_SMUIO_26, 763ce81151cSLikun Gao BOARD_GPIO_SMUIO_27, 764ce81151cSLikun Gao BOARD_GPIO_SMUIO_28, 765ce81151cSLikun Gao BOARD_GPIO_SMUIO_29, 766ce81151cSLikun Gao BOARD_GPIO_SMUIO_30, 767ce81151cSLikun Gao BOARD_GPIO_SMUIO_31, 768ce81151cSLikun Gao MAX_BOARD_GPIO_SMUIO_NUM, 769ce81151cSLikun Gao BOARD_GPIO_DC_GEN_A, 770ce81151cSLikun Gao BOARD_GPIO_DC_GEN_B, 771ce81151cSLikun Gao BOARD_GPIO_DC_GEN_C, 772ce81151cSLikun Gao BOARD_GPIO_DC_GEN_D, 773ce81151cSLikun Gao BOARD_GPIO_DC_GEN_E, 774ce81151cSLikun Gao BOARD_GPIO_DC_GEN_F, 775ce81151cSLikun Gao BOARD_GPIO_DC_GEN_G, 776ce81151cSLikun Gao BOARD_GPIO_DC_GENLK_CLK, 777ce81151cSLikun Gao BOARD_GPIO_DC_GENLK_VSYNC, 778ce81151cSLikun Gao BOARD_GPIO_DC_SWAPLOCK_A, 779ce81151cSLikun Gao BOARD_GPIO_DC_SWAPLOCK_B, 780ce81151cSLikun Gao } BOARD_GPIO_TYPE_e; 781ce81151cSLikun Gao 782ce81151cSLikun Gao #define INVALID_BOARD_GPIO 0xFF 783ce81151cSLikun Gao 784ce81151cSLikun Gao 785ce81151cSLikun Gao typedef struct { 786ce81151cSLikun Gao //PLL 0 787ce81151cSLikun Gao uint16_t InitGfxclk_bypass; 788ce81151cSLikun Gao uint16_t InitSocclk; 789ce81151cSLikun Gao uint16_t InitMp0clk; 790ce81151cSLikun Gao uint16_t InitMpioclk; 791ce81151cSLikun Gao uint16_t InitSmnclk; 792ce81151cSLikun Gao uint16_t InitUcpclk; 793ce81151cSLikun Gao uint16_t InitCsrclk; 794ce81151cSLikun Gao //PLL 1 795ce81151cSLikun Gao 796ce81151cSLikun Gao uint16_t InitDprefclk; 797ce81151cSLikun Gao uint16_t InitDcfclk; 798ce81151cSLikun Gao uint16_t InitDtbclk; 799ce81151cSLikun Gao //PLL 2 800ce81151cSLikun Gao uint16_t InitDclk; //assume same DCLK/VCLK for both instances 801ce81151cSLikun Gao uint16_t InitVclk; 802ce81151cSLikun Gao // PLL 3 803ce81151cSLikun Gao uint16_t InitUsbdfsclk; 804ce81151cSLikun Gao uint16_t InitMp1clk; 805ce81151cSLikun Gao uint16_t InitLclk; 806ce81151cSLikun Gao uint16_t InitBaco400clk_bypass; 807ce81151cSLikun Gao uint16_t InitBaco1200clk_bypass; 808ce81151cSLikun Gao uint16_t InitBaco700clk_bypass; 809ce81151cSLikun Gao // PLL 4 810ce81151cSLikun Gao uint16_t InitFclk; 811ce81151cSLikun Gao // PLL 5 812ce81151cSLikun Gao uint16_t InitGfxclk_clkb; 813ce81151cSLikun Gao 814ce81151cSLikun Gao //PLL 6 815ce81151cSLikun Gao uint8_t InitUclkDPMState; // =0,1,2,3, frequency from FreqTableUclk 816ce81151cSLikun Gao 817ce81151cSLikun Gao uint8_t Padding[3]; 818ce81151cSLikun Gao 819ce81151cSLikun Gao uint32_t InitVcoFreqPll0; 820ce81151cSLikun Gao uint32_t InitVcoFreqPll1; 821ce81151cSLikun Gao uint32_t InitVcoFreqPll2; 822ce81151cSLikun Gao uint32_t InitVcoFreqPll3; 823ce81151cSLikun Gao uint32_t InitVcoFreqPll4; 824ce81151cSLikun Gao uint32_t InitVcoFreqPll5; 825ce81151cSLikun Gao uint32_t InitVcoFreqPll6; 826ce81151cSLikun Gao 827ce81151cSLikun Gao //encoding will change depending on SVI2/SVI3 828ce81151cSLikun Gao uint16_t InitGfx; // In mV(Q2) , should be 0? 829ce81151cSLikun Gao uint16_t InitSoc; // In mV(Q2) 830ce81151cSLikun Gao uint16_t InitU; // In Mv(Q2) 831ce81151cSLikun Gao 832ce81151cSLikun Gao uint16_t Padding2; 833ce81151cSLikun Gao 834ce81151cSLikun Gao uint32_t Spare[8]; 835ce81151cSLikun Gao 836ce81151cSLikun Gao } BootValues_t; 837ce81151cSLikun Gao 838ce81151cSLikun Gao 839ce81151cSLikun Gao typedef struct { 840ce81151cSLikun Gao uint16_t Power[PPT_THROTTLER_COUNT][POWER_SOURCE_COUNT]; // Watts 841ce81151cSLikun Gao uint16_t Tdc[TDC_THROTTLER_COUNT]; // Amps 842ce81151cSLikun Gao 843ce81151cSLikun Gao uint16_t Temperature[TEMP_COUNT]; // Celsius 844ce81151cSLikun Gao 845ce81151cSLikun Gao uint8_t PwmLimitMin; 846ce81151cSLikun Gao uint8_t PwmLimitMax; 847ce81151cSLikun Gao uint8_t FanTargetTemperature; 848ce81151cSLikun Gao uint8_t Spare1[1]; 849ce81151cSLikun Gao 850ce81151cSLikun Gao uint16_t AcousticTargetRpmThresholdMin; 851ce81151cSLikun Gao uint16_t AcousticTargetRpmThresholdMax; 852ce81151cSLikun Gao 853ce81151cSLikun Gao uint16_t AcousticLimitRpmThresholdMin; 854ce81151cSLikun Gao uint16_t AcousticLimitRpmThresholdMax; 855ce81151cSLikun Gao 856ce81151cSLikun Gao uint16_t PccLimitMin; 857ce81151cSLikun Gao uint16_t PccLimitMax; 858ce81151cSLikun Gao 859ce81151cSLikun Gao uint16_t FanStopTempMin; 860ce81151cSLikun Gao uint16_t FanStopTempMax; 861ce81151cSLikun Gao uint16_t FanStartTempMin; 862ce81151cSLikun Gao uint16_t FanStartTempMax; 863ce81151cSLikun Gao 864ce81151cSLikun Gao uint32_t Spare[12]; 865ce81151cSLikun Gao 866ce81151cSLikun Gao } MsgLimits_t; 867ce81151cSLikun Gao 868ce81151cSLikun Gao typedef struct { 869ce81151cSLikun Gao uint16_t BaseClockAc; 870ce81151cSLikun Gao uint16_t GameClockAc; 871ce81151cSLikun Gao uint16_t BoostClockAc; 872ce81151cSLikun Gao uint16_t BaseClockDc; 873ce81151cSLikun Gao uint16_t GameClockDc; 874ce81151cSLikun Gao uint16_t BoostClockDc; 875ce81151cSLikun Gao 876ce81151cSLikun Gao uint32_t Reserved[4]; 877ce81151cSLikun Gao } DriverReportedClocks_t; 878ce81151cSLikun Gao 879ce81151cSLikun Gao typedef struct { 880ce81151cSLikun Gao uint8_t DcBtcEnabled; 881ce81151cSLikun Gao uint8_t Padding[3]; 882ce81151cSLikun Gao 883ce81151cSLikun Gao uint16_t DcTol; // mV Q2 884ce81151cSLikun Gao uint16_t DcBtcGb; // mV Q2 885ce81151cSLikun Gao 886ce81151cSLikun Gao uint16_t DcBtcMin; // mV Q2 887ce81151cSLikun Gao uint16_t DcBtcMax; // mV Q2 888ce81151cSLikun Gao 889ce81151cSLikun Gao LinearInt_t DcBtcGbScalar; 890ce81151cSLikun Gao 891ce81151cSLikun Gao } AvfsDcBtcParams_t; 892ce81151cSLikun Gao 893ce81151cSLikun Gao typedef struct { 894ce81151cSLikun Gao uint16_t AvfsTemp[AVFS_TEMP_COUNT]; //in degrees C 895ce81151cSLikun Gao uint16_t VftFMin; // in MHz 896ce81151cSLikun Gao uint16_t VInversion; // in mV Q2 897ce81151cSLikun Gao QuadraticInt_t qVft[AVFS_TEMP_COUNT]; 898ce81151cSLikun Gao QuadraticInt_t qAvfsGb; 899ce81151cSLikun Gao QuadraticInt_t qAvfsGb2; 900ce81151cSLikun Gao } AvfsFuseOverride_t; 901ce81151cSLikun Gao 902ce81151cSLikun Gao typedef struct { 903ce81151cSLikun Gao // SECTION: Version 904ce81151cSLikun Gao 905ce81151cSLikun Gao uint32_t Version; // should be unique to each SKU(i.e if any value changes in below structure then this value must be different) 906ce81151cSLikun Gao 907ce81151cSLikun Gao // SECTION: Feature Control 908ce81151cSLikun Gao uint32_t FeaturesToRun[NUM_FEATURES / 32]; // Features that PMFW will attempt to enable. Use FEATURE_*_BIT as mapping 909ce81151cSLikun Gao 910ce81151cSLikun Gao // SECTION: Miscellaneous Configuration 911ce81151cSLikun Gao uint8_t TotalPowerConfig; // Determines how PMFW calculates the power. Use defines from PwrConfig_e 912ce81151cSLikun Gao uint8_t CustomerVariant; //To specify if this PPTable is intended for a particular customer. Use defines from CUSTOMER_VARIANT_e 913ce81151cSLikun Gao uint8_t MemoryTemperatureTypeMask; // Bit mapping indicating which methods of memory temperature reading are enabled. Use defines from MEM_TEMP_*BIT 914ce81151cSLikun Gao uint8_t SmartShiftVersion; // Determine what SmartShift feature version is supported Use defines from SMARTSHIFT_VERSION_e 915ce81151cSLikun Gao 916ce81151cSLikun Gao // SECTION: Infrastructure Limits 917ce81151cSLikun Gao uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in AC mode. Multiple limits supported 918ce81151cSLikun Gao uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in DC mode. Multiple limits supported 919ce81151cSLikun Gao 920ce81151cSLikun Gao uint16_t SocketPowerLimitSmartShift2; // In Watts. Power limit used SmartShift 921ce81151cSLikun Gao 922ce81151cSLikun Gao //if set to 1, SocketPowerLimitAc and SocketPowerLimitDc will be interpreted as legacy programs(i.e absolute power). If 0, all except index 0 will be scalars 923ce81151cSLikun Gao //relative index 0 924ce81151cSLikun Gao uint8_t EnableLegacyPptLimit; 925ce81151cSLikun Gao uint8_t UseInputTelemetry; //applicable to SVI3 only and only to be set if VRs support 926ce81151cSLikun Gao uint8_t SmartShiftMinReportedPptinDcs; //minimum possible active power consumption for this SKU. Used for SmartShift power reporting 927ce81151cSLikun Gao 928ce81151cSLikun Gao uint8_t PaddingPpt[1]; 929ce81151cSLikun Gao 930ce81151cSLikun Gao uint16_t VrTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with VR regulator maximum temperature 931ce81151cSLikun Gao 932ce81151cSLikun Gao uint16_t PlatformTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with platform maximum temperature per VR current rail 933ce81151cSLikun Gao 934ce81151cSLikun Gao uint16_t TemperatureLimit[TEMP_COUNT]; // In degrees Celsius. Temperature limit associated with each input 935ce81151cSLikun Gao 936ce81151cSLikun Gao uint16_t HwCtfTempLimit; // In degrees Celsius. Temperature above which HW will trigger CTF. Consumed by VBIOS only 937ce81151cSLikun Gao 938ce81151cSLikun Gao uint16_t PaddingInfra; 939ce81151cSLikun Gao 940ce81151cSLikun Gao // Per year normalized Vmax state failure rates (sum of the two domains divided by life time in years) 941ce81151cSLikun Gao uint32_t FitControllerFailureRateLimit; //in IEEE float 942ce81151cSLikun Gao //Expected GFX Duty Cycle at Vmax. 943ce81151cSLikun Gao uint32_t FitControllerGfxDutyCycle; // in IEEE float 944ce81151cSLikun Gao //Expected SOC Duty Cycle at Vmax. 945ce81151cSLikun Gao uint32_t FitControllerSocDutyCycle; // in IEEE float 946ce81151cSLikun Gao 947ce81151cSLikun Gao //This offset will be deducted from the controller output to before it goes through the SOC Vset limiter block. 948ce81151cSLikun Gao uint32_t FitControllerSocOffset; //in IEEE float 949ce81151cSLikun Gao 950ce81151cSLikun Gao uint32_t GfxApccPlusResidencyLimit; // Percentage value. Used by APCC+ controller to control PCC residency to some value 951ce81151cSLikun Gao 952ce81151cSLikun Gao // SECTION: Throttler settings 953ce81151cSLikun Gao uint32_t ThrottlerControlMask; // See THROTTLER_*_BIT for mapping 954ce81151cSLikun Gao 955ce81151cSLikun Gao // SECTION: FW DSTATE Settings 956ce81151cSLikun Gao uint32_t FwDStateMask; // See FW_DSTATE_*_BIT for mapping 957ce81151cSLikun Gao 958ce81151cSLikun Gao // SECTION: Voltage Control Parameters 959ce81151cSLikun Gao uint16_t UlvVoltageOffset[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2). ULV offset used in either GFX_ULV or SOC_ULV(part of FW_DSTATE) 960ce81151cSLikun Gao 961ce81151cSLikun Gao uint16_t UlvVoltageOffsetU; // In mV(Q2). ULV offset used in either U_ULV(part of FW_DSTATE) 962ce81151cSLikun Gao uint16_t DeepUlvVoltageOffsetSoc; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC as part of FW_DSTATE 963ce81151cSLikun Gao 964ce81151cSLikun Gao // Voltage Limits 965ce81151cSLikun Gao uint16_t DefaultMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage without FIT controller enabled 966ce81151cSLikun Gao uint16_t BoostMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage with FIT controller enabled 967ce81151cSLikun Gao 968ce81151cSLikun Gao //Vmin Optimizations 969ce81151cSLikun Gao int16_t VminTempHystersis[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature hysteresis for switching between low/high temperature values for Vmin 970ce81151cSLikun Gao int16_t VminTempThreshold[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature threshold for switching between low/high temperature values for Vmin 971ce81151cSLikun Gao uint16_t Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at hot. 972ce81151cSLikun Gao uint16_t Vmin_Cold_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at cold. 973ce81151cSLikun Gao uint16_t Vmin_Hot_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at hot. 974ce81151cSLikun Gao uint16_t Vmin_Cold_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at cold. 975ce81151cSLikun Gao uint16_t Vmin_Aging_Offset[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Worst-case aging margin 976ce81151cSLikun Gao uint16_t Vmin_Plat_Offset_Hot[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Hot 977ce81151cSLikun Gao uint16_t Vmin_Plat_Offset_Cold[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Cold 978ce81151cSLikun Gao 979ce81151cSLikun Gao //This is a fixed/minimum VMIN aging degradation offset which is applied at T0. This reflects the minimum amount of aging already accounted for. 980ce81151cSLikun Gao uint16_t VcBtcFixedVminAgingOffset[PMFW_VOLT_PLANE_COUNT]; 981ce81151cSLikun Gao //Linear offset or GB term to account for mis-correlation between PSM and Vmin shift trends across parts. 982ce81151cSLikun Gao uint16_t VcBtcVmin2PsmDegrationGb[PMFW_VOLT_PLANE_COUNT]; 983ce81151cSLikun Gao //Scalar coefficient of the PSM aging degradation function 984ce81151cSLikun Gao uint32_t VcBtcPsmA[PMFW_VOLT_PLANE_COUNT]; // A_PSM 985ce81151cSLikun Gao //Exponential coefficient of the PSM aging degradation function 986ce81151cSLikun Gao uint32_t VcBtcPsmB[PMFW_VOLT_PLANE_COUNT]; // B_PSM 987ce81151cSLikun Gao //Scalar coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 988ce81151cSLikun Gao uint32_t VcBtcVminA[PMFW_VOLT_PLANE_COUNT]; // A_VMIN 989ce81151cSLikun Gao //Exponential coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 990ce81151cSLikun Gao uint32_t VcBtcVminB[PMFW_VOLT_PLANE_COUNT]; // B_VMIN 991ce81151cSLikun Gao 992ce81151cSLikun Gao uint8_t PerPartVminEnabled[PMFW_VOLT_PLANE_COUNT]; 993ce81151cSLikun Gao uint8_t VcBtcEnabled[PMFW_VOLT_PLANE_COUNT]; 994ce81151cSLikun Gao 995ce81151cSLikun Gao uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 996ce81151cSLikun Gao uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 997ce81151cSLikun Gao 9981c65e548SEvan Quan QuadraticInt_t Vmin_droop; 9991c65e548SEvan Quan uint32_t SpareVmin[9]; 1000ce81151cSLikun Gao 1001ce81151cSLikun Gao 1002ce81151cSLikun Gao //SECTION: DPM Configuration 1 1003ce81151cSLikun Gao DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 1004ce81151cSLikun Gao 1005ce81151cSLikun Gao uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1006ce81151cSLikun Gao uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1007ce81151cSLikun Gao uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1008ce81151cSLikun Gao uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1009ce81151cSLikun Gao uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1010ce81151cSLikun Gao uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1011ce81151cSLikun Gao uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1012ce81151cSLikun Gao uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1013ce81151cSLikun Gao uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1014ce81151cSLikun Gao uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1015ce81151cSLikun Gao uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1016ce81151cSLikun Gao 1017ce81151cSLikun Gao uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1018ce81151cSLikun Gao 1019ce81151cSLikun Gao // SECTION: DPM Configuration 2 1020ce81151cSLikun Gao uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 1021ce81151cSLikun Gao uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 1022ce81151cSLikun Gao 1023ce81151cSLikun Gao uint8_t GfxclkSpare[2]; 1024ce81151cSLikun Gao uint16_t GfxclkFreqCap; 1025ce81151cSLikun Gao 1026ce81151cSLikun Gao //GFX Idle Power Settings 1027ce81151cSLikun Gao uint16_t GfxclkFgfxoffEntry; // in Mhz 1028ce81151cSLikun Gao uint16_t GfxclkFgfxoffExitImu; // in Mhz 1029ce81151cSLikun Gao uint16_t GfxclkFgfxoffExitRlc; // in Mhz 1030ce81151cSLikun Gao uint16_t GfxclkThrottleClock; //Used primarily in DCS 1031ce81151cSLikun Gao uint8_t EnableGfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages 1032ce81151cSLikun Gao uint8_t GfxIdlePadding; 1033ce81151cSLikun Gao 1034ce81151cSLikun Gao uint8_t SmsRepairWRCKClkDivEn; 1035ce81151cSLikun Gao uint8_t SmsRepairWRCKClkDivVal; 1036ce81151cSLikun Gao uint8_t GfxOffEntryEarlyMGCGEn; 1037ce81151cSLikun Gao uint8_t GfxOffEntryForceCGCGEn; 1038ce81151cSLikun Gao uint8_t GfxOffEntryForceCGCGDelayEn; 1039ce81151cSLikun Gao uint8_t GfxOffEntryForceCGCGDelayVal; // in microseconds 1040ce81151cSLikun Gao 1041ce81151cSLikun Gao uint16_t GfxclkFreqGfxUlv; // in MHz 1042ce81151cSLikun Gao uint8_t GfxIdlePadding2[2]; 1043ce81151cSLikun Gao 1044ce81151cSLikun Gao uint32_t GfxoffSpare[16]; 1045ce81151cSLikun Gao 1046ce81151cSLikun Gao // GFX GPO 1047ce81151cSLikun Gao uint32_t GfxGpoSpare[16]; 1048ce81151cSLikun Gao 1049ce81151cSLikun Gao // GFX DCS 1050ce81151cSLikun Gao 1051ce81151cSLikun Gao uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase 1052ce81151cSLikun Gao uint16_t PaddingDcs; 1053ce81151cSLikun Gao 1054ce81151cSLikun Gao uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase 1055ce81151cSLikun Gao uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. 1056ce81151cSLikun Gao 1057ce81151cSLikun Gao uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS. 1058ce81151cSLikun Gao 1059ce81151cSLikun Gao uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. 1060ce81151cSLikun Gao uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin. 1061ce81151cSLikun Gao 1062ce81151cSLikun Gao 1063ce81151cSLikun Gao uint32_t DcsSpare[16]; 1064ce81151cSLikun Gao 1065ce81151cSLikun Gao // UCLK section 1066ce81151cSLikun Gao uint8_t UseStrobeModeOptimizations; //Set to indicate that FW should use strobe mode optimizations 1067ce81151cSLikun Gao uint8_t PaddingMem[3]; 1068ce81151cSLikun Gao 1069ce81151cSLikun Gao uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 1070ce81151cSLikun Gao uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 1071ce81151cSLikun Gao 1072ce81151cSLikun Gao uint16_t MemVmempVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1073ce81151cSLikun Gao uint16_t MemVddioVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1074ce81151cSLikun Gao 1075ce81151cSLikun Gao //FCLK Section 1076ce81151cSLikun Gao 1077ce81151cSLikun Gao uint8_t FclkDpmUPstates[NUM_FCLK_DPM_LEVELS]; // U P-state ID associated with each FCLK DPM state. 1078ce81151cSLikun Gao uint16_t FclkDpmVddU[NUM_FCLK_DPM_LEVELS]; // mV(Q2) Vset U voltage associated with each FCLK DPM state. 1079ce81151cSLikun Gao uint16_t FclkDpmUSpeed[NUM_FCLK_DPM_LEVELS]; //U speed associated with each FCLK DPM state 1080ce81151cSLikun Gao uint16_t FclkDpmDisallowPstateFreq; //Frequency which FW will target when indicated that display config cannot support P-state. Set to 0 use FW calculated value 1081ce81151cSLikun Gao uint16_t PaddingFclk; 1082ce81151cSLikun Gao 1083ce81151cSLikun Gao // Link DPM Settings 1084ce81151cSLikun Gao uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 1085ce81151cSLikun Gao uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 1086ce81151cSLikun Gao uint16_t LclkFreq[NUM_LINK_LEVELS]; 1087ce81151cSLikun Gao 1088ce81151cSLikun Gao // SECTION: Fan Control 1089ce81151cSLikun Gao uint16_t FanStopTemp[TEMP_COUNT]; //Celsius 1090ce81151cSLikun Gao uint16_t FanStartTemp[TEMP_COUNT]; //Celsius 1091ce81151cSLikun Gao 1092ce81151cSLikun Gao uint16_t FanGain[TEMP_COUNT]; 1093ce81151cSLikun Gao uint16_t FanGainPadding; 1094ce81151cSLikun Gao 1095ce81151cSLikun Gao uint16_t FanPwmMin; 1096ce81151cSLikun Gao uint16_t AcousticTargetRpmThreshold; 1097ce81151cSLikun Gao uint16_t AcousticLimitRpmThreshold; 1098ce81151cSLikun Gao uint16_t FanMaximumRpm; 1099ce81151cSLikun Gao uint16_t MGpuAcousticLimitRpmThreshold; 1100ce81151cSLikun Gao uint16_t FanTargetGfxclk; 1101ce81151cSLikun Gao uint32_t TempInputSelectMask; 1102ce81151cSLikun Gao uint8_t FanZeroRpmEnable; 1103ce81151cSLikun Gao uint8_t FanTachEdgePerRev; 1104ce81151cSLikun Gao uint16_t FanTargetTemperature[TEMP_COUNT]; 1105ce81151cSLikun Gao 1106ce81151cSLikun Gao // The following are AFC override parameters. Leave at 0 to use FW defaults. 1107ce81151cSLikun Gao int16_t FuzzyFan_ErrorSetDelta; 1108ce81151cSLikun Gao int16_t FuzzyFan_ErrorRateSetDelta; 1109ce81151cSLikun Gao int16_t FuzzyFan_PwmSetDelta; 1110ce81151cSLikun Gao uint16_t FuzzyFan_Reserved; 1111ce81151cSLikun Gao 1112ce81151cSLikun Gao uint16_t FwCtfLimit[TEMP_COUNT]; 1113ce81151cSLikun Gao 1114ce81151cSLikun Gao uint16_t IntakeTempEnableRPM; 1115ce81151cSLikun Gao int16_t IntakeTempOffsetTemp; 1116ce81151cSLikun Gao uint16_t IntakeTempReleaseTemp; 1117ce81151cSLikun Gao uint16_t IntakeTempHighIntakeAcousticLimit; 1118ce81151cSLikun Gao uint16_t IntakeTempAcouticLimitReleaseRate; 1119ce81151cSLikun Gao 1120ce81151cSLikun Gao uint16_t FanStalledTempLimitOffset; 1121ce81151cSLikun Gao uint16_t FanStalledTriggerRpm; 1122ce81151cSLikun Gao uint16_t FanAbnormalTriggerRpm; 1123ce81151cSLikun Gao uint16_t FanPadding; 1124ce81151cSLikun Gao 1125ce81151cSLikun Gao uint32_t FanSpare[14]; 1126ce81151cSLikun Gao 1127ce81151cSLikun Gao // SECTION: VDD_GFX AVFS 1128ce81151cSLikun Gao 1129ce81151cSLikun Gao uint8_t OverrideGfxAvfsFuses; 1130ce81151cSLikun Gao uint8_t GfxAvfsPadding[3]; 1131ce81151cSLikun Gao 1132ce81151cSLikun Gao uint32_t L2HwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; //see fusedoc for encoding 1133ce81151cSLikun Gao uint32_t SeHwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; 1134ce81151cSLikun Gao 1135ce81151cSLikun Gao uint32_t CommonRtAvfs[PP_GRTAVFS_FW_COMMON_FUSE_COUNT]; 1136ce81151cSLikun Gao 1137ce81151cSLikun Gao uint32_t L2FwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1138ce81151cSLikun Gao uint32_t SeFwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1139ce81151cSLikun Gao 1140ce81151cSLikun Gao uint32_t Droop_PWL_F[PP_NUM_RTAVFS_PWL_ZONES]; 1141ce81151cSLikun Gao uint32_t Droop_PWL_a[PP_NUM_RTAVFS_PWL_ZONES]; 1142ce81151cSLikun Gao uint32_t Droop_PWL_b[PP_NUM_RTAVFS_PWL_ZONES]; 1143ce81151cSLikun Gao uint32_t Droop_PWL_c[PP_NUM_RTAVFS_PWL_ZONES]; 1144ce81151cSLikun Gao 1145ce81151cSLikun Gao uint32_t Static_PWL_Offset[PP_NUM_RTAVFS_PWL_ZONES]; 1146ce81151cSLikun Gao 1147ce81151cSLikun Gao uint32_t dGbV_dT_vmin; 1148ce81151cSLikun Gao uint32_t dGbV_dT_vmax; 1149ce81151cSLikun Gao 1150ce81151cSLikun Gao //Unused: PMFW-9370 1151ce81151cSLikun Gao uint32_t V2F_vmin_range_low; 1152ce81151cSLikun Gao uint32_t V2F_vmin_range_high; 1153ce81151cSLikun Gao uint32_t V2F_vmax_range_low; 1154ce81151cSLikun Gao uint32_t V2F_vmax_range_high; 1155ce81151cSLikun Gao 1156ce81151cSLikun Gao AvfsDcBtcParams_t DcBtcGfxParams; 1157ce81151cSLikun Gao 1158ce81151cSLikun Gao uint32_t GfxAvfsSpare[32]; 1159ce81151cSLikun Gao 1160ce81151cSLikun Gao //SECTION: VDD_SOC AVFS 1161ce81151cSLikun Gao 1162ce81151cSLikun Gao uint8_t OverrideSocAvfsFuses; 1163ce81151cSLikun Gao uint8_t MinSocAvfsRevision; 1164ce81151cSLikun Gao uint8_t SocAvfsPadding[2]; 1165ce81151cSLikun Gao 1166ce81151cSLikun Gao AvfsFuseOverride_t SocAvfsFuseOverride[AVFS_D_COUNT]; 1167ce81151cSLikun Gao 1168ce81151cSLikun Gao DroopInt_t dBtcGbSoc[AVFS_D_COUNT]; // GHz->V BtcGb 1169ce81151cSLikun Gao 1170ce81151cSLikun Gao LinearInt_t qAgingGb[AVFS_D_COUNT]; // GHz->V 1171ce81151cSLikun Gao 1172ce81151cSLikun Gao QuadraticInt_t qStaticVoltageOffset[AVFS_D_COUNT]; // GHz->V 1173ce81151cSLikun Gao 1174ce81151cSLikun Gao AvfsDcBtcParams_t DcBtcSocParams[AVFS_D_COUNT]; 1175ce81151cSLikun Gao 1176ce81151cSLikun Gao uint32_t SocAvfsSpare[32]; 1177ce81151cSLikun Gao 1178ce81151cSLikun Gao //SECTION: Boot clock and voltage values 1179ce81151cSLikun Gao BootValues_t BootValues; 1180ce81151cSLikun Gao 1181ce81151cSLikun Gao //SECTION: Driver Reported Clocks 1182ce81151cSLikun Gao DriverReportedClocks_t DriverReportedClocks; 1183ce81151cSLikun Gao 1184ce81151cSLikun Gao //SECTION: Message Limits 1185ce81151cSLikun Gao MsgLimits_t MsgLimits; 1186ce81151cSLikun Gao 1187ce81151cSLikun Gao //SECTION: OverDrive Limits 1188ce81151cSLikun Gao OverDriveLimits_t OverDriveLimitsMin; 1189ce81151cSLikun Gao OverDriveLimits_t OverDriveLimitsBasicMax; 1190ce81151cSLikun Gao uint32_t reserved[22]; 1191ce81151cSLikun Gao 1192ce81151cSLikun Gao // SECTION: Advanced Options 1193ce81151cSLikun Gao uint32_t DebugOverrides; 1194ce81151cSLikun Gao 1195ce81151cSLikun Gao // SECTION: Sku Reserved 1196ce81151cSLikun Gao uint32_t Spare[64]; 1197ce81151cSLikun Gao 1198ce81151cSLikun Gao // Padding for MMHUB - do not modify this 1199ce81151cSLikun Gao uint32_t MmHubPadding[8]; 1200ce81151cSLikun Gao 1201ce81151cSLikun Gao } SkuTable_t; 1202ce81151cSLikun Gao 1203ce81151cSLikun Gao typedef struct { 1204ce81151cSLikun Gao // SECTION: Version 1205ce81151cSLikun Gao uint32_t Version; //should be unique to each board type 1206ce81151cSLikun Gao 1207ce81151cSLikun Gao 1208ce81151cSLikun Gao // SECTION: I2C Control 1209ce81151cSLikun Gao I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 1210ce81151cSLikun Gao 1211ce81151cSLikun Gao // SECTION: SVI2 Board Parameters 1212ce81151cSLikun Gao uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 1213ce81151cSLikun Gao uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 1214ce81151cSLikun Gao uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 1215ce81151cSLikun Gao uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 1216ce81151cSLikun Gao 1217ce81151cSLikun Gao uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1218ce81151cSLikun Gao uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1219ce81151cSLikun Gao uint8_t VmempUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1220ce81151cSLikun Gao uint8_t VddioUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1221ce81151cSLikun Gao 1222ce81151cSLikun Gao //SECTION SVI3 Board Parameters 1223ce81151cSLikun Gao uint8_t SlaveAddrMapping[SVI_PLANE_COUNT]; 1224ce81151cSLikun Gao uint8_t VrPsiSupport[SVI_PLANE_COUNT]; 1225ce81151cSLikun Gao 1226ce81151cSLikun Gao uint8_t PaddingPsi[SVI_PLANE_COUNT]; 1227ce81151cSLikun Gao uint8_t EnablePsi6[SVI_PLANE_COUNT]; // only applicable in SVI3 1228ce81151cSLikun Gao 1229ce81151cSLikun Gao // SECTION: Voltage Regulator Settings 1230ce81151cSLikun Gao SviTelemetryScale_t SviTelemetryScale[SVI_PLANE_COUNT]; 1231ce81151cSLikun Gao uint32_t VoltageTelemetryRatio[SVI_PLANE_COUNT]; // This is used for VDDIO Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 1232ce81151cSLikun Gao 1233ce81151cSLikun Gao uint8_t DownSlewRateVr[SVI_PLANE_COUNT]; 1234ce81151cSLikun Gao 1235ce81151cSLikun Gao // SECTION: GPIO Settings 1236ce81151cSLikun Gao 1237ce81151cSLikun Gao uint8_t LedOffGpio; 1238ce81151cSLikun Gao uint8_t FanOffGpio; 1239ce81151cSLikun Gao uint8_t GfxVrPowerStageOffGpio; 1240ce81151cSLikun Gao 1241ce81151cSLikun Gao uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 1242ce81151cSLikun Gao uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 1243ce81151cSLikun Gao uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 1244ce81151cSLikun Gao uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 1245ce81151cSLikun Gao 1246ce81151cSLikun Gao uint8_t GthrGpio; // GPIO pin configured for GTHR Event 1247ce81151cSLikun Gao uint8_t GthrPolarity; // replace GPIO polarity for GTHR 1248ce81151cSLikun Gao 1249ce81151cSLikun Gao // LED Display Settings 1250ce81151cSLikun Gao uint8_t LedPin0; // GPIO number for LedPin[0] 1251ce81151cSLikun Gao uint8_t LedPin1; // GPIO number for LedPin[1] 1252ce81151cSLikun Gao uint8_t LedPin2; // GPIO number for LedPin[2] 1253ce81151cSLikun Gao uint8_t LedEnableMask; 1254ce81151cSLikun Gao 1255ce81151cSLikun Gao uint8_t LedPcie; // GPIO number for PCIE results 1256ce81151cSLikun Gao uint8_t LedError; // GPIO number for Error Cases 1257ce81151cSLikun Gao 1258ce81151cSLikun Gao // SECTION: Clock Spread Spectrum 1259ce81151cSLikun Gao 1260ce81151cSLikun Gao // UCLK Spread Spectrum 1261ce81151cSLikun Gao uint16_t UclkSpreadPadding; 1262ce81151cSLikun Gao uint16_t UclkSpreadFreq; // kHz 1263ce81151cSLikun Gao 1264ce81151cSLikun Gao // UCLK Spread Spectrum 1265ce81151cSLikun Gao uint8_t UclkSpreadPercent[MEM_VENDOR_COUNT]; 1266ce81151cSLikun Gao 1267ce81151cSLikun Gao // FCLK Spread Spectrum 1268ce81151cSLikun Gao uint8_t FclkSpreadPadding; 1269ce81151cSLikun Gao uint8_t FclkSpreadPercent; // Q4.4 1270ce81151cSLikun Gao uint16_t FclkSpreadFreq; // kHz 1271ce81151cSLikun Gao 1272ce81151cSLikun Gao // Section: Memory Config 1273ce81151cSLikun Gao uint8_t DramWidth; // Width of interface to the channel for each DRAM module. See DRAM_BIT_WIDTH_TYPE_e 1274ce81151cSLikun Gao uint8_t PaddingMem1[3]; 1275ce81151cSLikun Gao 1276ce81151cSLikun Gao // Section: Total Board Power 1277ce81151cSLikun Gao uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 1278ce81151cSLikun Gao uint16_t BoardPowerPadding; 1279ce81151cSLikun Gao 1280ce81151cSLikun Gao // SECTION: UMC feature flags 1281ce81151cSLikun Gao uint8_t HsrEnabled; 1282ce81151cSLikun Gao uint8_t VddqOffEnabled; 1283ce81151cSLikun Gao uint8_t PaddingUmcFlags[2]; 1284ce81151cSLikun Gao 1285ce81151cSLikun Gao uint32_t PostVoltageSetBacoDelay; // in microseconds. Amount of time FW will wait after power good is established or PSI0 command is issued 1286ce81151cSLikun Gao uint32_t BacoEntryDelay; // in milliseconds. Amount of time FW will wait to trigger BACO entry after receiving entry notification from OS 1287ce81151cSLikun Gao 1288ce81151cSLikun Gao // SECTION: Board Reserved 1289ce81151cSLikun Gao uint32_t BoardSpare[64]; 1290ce81151cSLikun Gao 1291ce81151cSLikun Gao // SECTION: Structure Padding 1292ce81151cSLikun Gao 1293ce81151cSLikun Gao // Padding for MMHUB - do not modify this 1294ce81151cSLikun Gao uint32_t MmHubPadding[8]; 1295ce81151cSLikun Gao } BoardTable_t; 1296ce81151cSLikun Gao 1297ce81151cSLikun Gao typedef struct { 1298ce81151cSLikun Gao SkuTable_t SkuTable; 1299ce81151cSLikun Gao BoardTable_t BoardTable; 1300ce81151cSLikun Gao } PPTable_t; 1301ce81151cSLikun Gao 1302ce81151cSLikun Gao typedef struct { 1303ce81151cSLikun Gao // Time constant parameters for clock averages in ms 1304ce81151cSLikun Gao uint16_t GfxclkAverageLpfTau; 1305ce81151cSLikun Gao uint16_t FclkAverageLpfTau; 1306ce81151cSLikun Gao uint16_t UclkAverageLpfTau; 1307ce81151cSLikun Gao uint16_t GfxActivityLpfTau; 1308ce81151cSLikun Gao uint16_t UclkActivityLpfTau; 1309ce81151cSLikun Gao uint16_t SocketPowerLpfTau; 1310ce81151cSLikun Gao uint16_t VcnClkAverageLpfTau; 1311ce81151cSLikun Gao uint16_t VcnUsageAverageLpfTau; 1312ce81151cSLikun Gao } DriverSmuConfig_t; 1313ce81151cSLikun Gao 1314ce81151cSLikun Gao typedef struct { 1315ce81151cSLikun Gao DriverSmuConfig_t DriverSmuConfig; 1316ce81151cSLikun Gao 1317ce81151cSLikun Gao uint32_t Spare[8]; 1318ce81151cSLikun Gao // Padding - ignore 1319ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1320ce81151cSLikun Gao } DriverSmuConfigExternal_t; 1321ce81151cSLikun Gao 1322ce81151cSLikun Gao 1323ce81151cSLikun Gao typedef struct { 1324ce81151cSLikun Gao 1325ce81151cSLikun Gao uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1326ce81151cSLikun Gao uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1327ce81151cSLikun Gao uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1328ce81151cSLikun Gao uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1329ce81151cSLikun Gao uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1330ce81151cSLikun Gao uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1331ce81151cSLikun Gao uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1332ce81151cSLikun Gao uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1333ce81151cSLikun Gao uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1334ce81151cSLikun Gao uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1335ce81151cSLikun Gao uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1336ce81151cSLikun Gao 1337ce81151cSLikun Gao uint16_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1338ce81151cSLikun Gao 1339ce81151cSLikun Gao uint16_t Padding; 1340ce81151cSLikun Gao 1341ce81151cSLikun Gao uint32_t Spare[32]; 1342ce81151cSLikun Gao 1343ce81151cSLikun Gao // Padding - ignore 1344ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1345ce81151cSLikun Gao 1346ce81151cSLikun Gao } DriverInfoTable_t; 1347ce81151cSLikun Gao 1348ce81151cSLikun Gao typedef struct { 1349ce81151cSLikun Gao uint32_t CurrClock[PPCLK_COUNT]; 1350ce81151cSLikun Gao 1351ce81151cSLikun Gao uint16_t AverageGfxclkFrequencyTarget; 1352ce81151cSLikun Gao uint16_t AverageGfxclkFrequencyPreDs; 1353ce81151cSLikun Gao uint16_t AverageGfxclkFrequencyPostDs; 1354ce81151cSLikun Gao uint16_t AverageFclkFrequencyPreDs; 1355ce81151cSLikun Gao uint16_t AverageFclkFrequencyPostDs; 1356ce81151cSLikun Gao uint16_t AverageMemclkFrequencyPreDs ; // this is scaled to actual memory clock 1357ce81151cSLikun Gao uint16_t AverageMemclkFrequencyPostDs ; // this is scaled to actual memory clock 1358ce81151cSLikun Gao uint16_t AverageVclk0Frequency ; 1359ce81151cSLikun Gao uint16_t AverageDclk0Frequency ; 1360ce81151cSLikun Gao uint16_t AverageVclk1Frequency ; 1361ce81151cSLikun Gao uint16_t AverageDclk1Frequency ; 1362*66f54992SEvan Quan uint16_t PCIeBusy; 1363*66f54992SEvan Quan uint16_t dGPU_W_MAX; 1364*66f54992SEvan Quan uint16_t padding; 1365*66f54992SEvan Quan 1366*66f54992SEvan Quan uint32_t MetricsCounter; 1367ce81151cSLikun Gao 1368ce81151cSLikun Gao uint16_t AvgVoltage[SVI_PLANE_COUNT]; 1369*66f54992SEvan Quan uint16_t AvgCurrent[SVI_PLANE_COUNT]; 1370ce81151cSLikun Gao 1371ce81151cSLikun Gao uint16_t AverageGfxActivity ; 1372ce81151cSLikun Gao uint16_t AverageUclkActivity ; 1373ce81151cSLikun Gao uint16_t Vcn0ActivityPercentage ; 1374ce81151cSLikun Gao uint16_t Vcn1ActivityPercentage ; 1375ce81151cSLikun Gao 1376ce81151cSLikun Gao uint32_t EnergyAccumulator; 1377ce81151cSLikun Gao uint16_t AverageSocketPower ; 1378ce81151cSLikun Gao uint16_t AvgTemperature[TEMP_COUNT]; 1379ce81151cSLikun Gao 1380ce81151cSLikun Gao uint8_t PcieRate ; 1381ce81151cSLikun Gao uint8_t PcieWidth ; 1382ce81151cSLikun Gao 1383ce81151cSLikun Gao uint8_t AvgFanPwm; 1384ce81151cSLikun Gao uint8_t Padding[1]; 1385ce81151cSLikun Gao uint16_t AvgFanRpm; 1386ce81151cSLikun Gao 1387ce81151cSLikun Gao 1388ce81151cSLikun Gao uint8_t ThrottlingPercentage[THROTTLER_COUNT]; 1389ce81151cSLikun Gao 1390ce81151cSLikun Gao //metrics for D3hot entry/exit and driver ARM msgs 1391ce81151cSLikun Gao uint32_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; 1392ce81151cSLikun Gao uint32_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT]; 1393ce81151cSLikun Gao uint32_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT]; 1394ce81151cSLikun Gao 1395ce81151cSLikun Gao uint16_t ApuSTAPMSmartShiftLimit; 1396ce81151cSLikun Gao uint16_t ApuSTAPMLimit; 1397ce81151cSLikun Gao uint16_t AvgApuSocketPower; 1398ce81151cSLikun Gao 1399ce81151cSLikun Gao uint16_t AverageUclkActivity_MAX; 1400ce81151cSLikun Gao 1401ce81151cSLikun Gao uint32_t PublicSerialNumberLower; 1402ce81151cSLikun Gao uint32_t PublicSerialNumberUpper; 1403ce81151cSLikun Gao 1404ce81151cSLikun Gao } SmuMetrics_t; 1405ce81151cSLikun Gao 1406ce81151cSLikun Gao typedef struct { 1407ce81151cSLikun Gao SmuMetrics_t SmuMetrics; 1408ce81151cSLikun Gao uint32_t Spare[30]; 1409ce81151cSLikun Gao 1410ce81151cSLikun Gao // Padding - ignore 1411ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1412ce81151cSLikun Gao } SmuMetricsExternal_t; 1413ce81151cSLikun Gao 1414ce81151cSLikun Gao typedef struct { 1415ce81151cSLikun Gao uint8_t WmSetting; 1416ce81151cSLikun Gao uint8_t Flags; 1417ce81151cSLikun Gao uint8_t Padding[2]; 1418ce81151cSLikun Gao 1419ce81151cSLikun Gao } WatermarkRowGeneric_t; 1420ce81151cSLikun Gao 1421ce81151cSLikun Gao #define NUM_WM_RANGES 4 1422ce81151cSLikun Gao 1423ce81151cSLikun Gao typedef enum { 1424ce81151cSLikun Gao WATERMARKS_CLOCK_RANGE = 0, 1425ce81151cSLikun Gao WATERMARKS_DUMMY_PSTATE, 1426ce81151cSLikun Gao WATERMARKS_MALL, 1427ce81151cSLikun Gao WATERMARKS_COUNT, 1428ce81151cSLikun Gao } WATERMARKS_FLAGS_e; 1429ce81151cSLikun Gao 1430ce81151cSLikun Gao typedef struct { 1431ce81151cSLikun Gao // Watermarks 1432ce81151cSLikun Gao WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES]; 1433ce81151cSLikun Gao } Watermarks_t; 1434ce81151cSLikun Gao 1435ce81151cSLikun Gao typedef struct { 1436ce81151cSLikun Gao Watermarks_t Watermarks; 1437ce81151cSLikun Gao uint32_t Spare[16]; 1438ce81151cSLikun Gao 1439ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1440ce81151cSLikun Gao } WatermarksExternal_t; 1441ce81151cSLikun Gao 1442ce81151cSLikun Gao typedef struct { 1443ce81151cSLikun Gao uint16_t avgPsmCount[214]; 1444ce81151cSLikun Gao uint16_t minPsmCount[214]; 1445ce81151cSLikun Gao float avgPsmVoltage[214]; 1446ce81151cSLikun Gao float minPsmVoltage[214]; 1447ce81151cSLikun Gao } AvfsDebugTable_t; 1448ce81151cSLikun Gao 1449ce81151cSLikun Gao typedef struct { 1450ce81151cSLikun Gao AvfsDebugTable_t AvfsDebugTable; 1451ce81151cSLikun Gao 1452ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1453ce81151cSLikun Gao } AvfsDebugTableExternal_t; 1454ce81151cSLikun Gao 1455ce81151cSLikun Gao 1456ce81151cSLikun Gao typedef struct { 1457ce81151cSLikun Gao uint8_t Gfx_ActiveHystLimit; 1458ce81151cSLikun Gao uint8_t Gfx_IdleHystLimit; 1459ce81151cSLikun Gao uint8_t Gfx_FPS; 1460ce81151cSLikun Gao uint8_t Gfx_MinActiveFreqType; 1461ce81151cSLikun Gao uint8_t Gfx_BoosterFreqType; 1462ce81151cSLikun Gao uint8_t PaddingGfx; 1463ce81151cSLikun Gao uint16_t Gfx_MinActiveFreq; // MHz 1464ce81151cSLikun Gao uint16_t Gfx_BoosterFreq; // MHz 1465ce81151cSLikun Gao uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms 1466ce81151cSLikun Gao uint32_t Gfx_PD_Data_limit_a; // Q16 1467ce81151cSLikun Gao uint32_t Gfx_PD_Data_limit_b; // Q16 1468ce81151cSLikun Gao uint32_t Gfx_PD_Data_limit_c; // Q16 1469ce81151cSLikun Gao uint32_t Gfx_PD_Data_error_coeff; // Q16 1470ce81151cSLikun Gao uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 1471ce81151cSLikun Gao 1472ce81151cSLikun Gao uint8_t Fclk_ActiveHystLimit; 1473ce81151cSLikun Gao uint8_t Fclk_IdleHystLimit; 1474ce81151cSLikun Gao uint8_t Fclk_FPS; 1475ce81151cSLikun Gao uint8_t Fclk_MinActiveFreqType; 1476ce81151cSLikun Gao uint8_t Fclk_BoosterFreqType; 1477ce81151cSLikun Gao uint8_t PaddingFclk; 1478ce81151cSLikun Gao uint16_t Fclk_MinActiveFreq; // MHz 1479ce81151cSLikun Gao uint16_t Fclk_BoosterFreq; // MHz 1480ce81151cSLikun Gao uint16_t Fclk_PD_Data_time_constant; // Time constant of PD controller in ms 1481ce81151cSLikun Gao uint32_t Fclk_PD_Data_limit_a; // Q16 1482ce81151cSLikun Gao uint32_t Fclk_PD_Data_limit_b; // Q16 1483ce81151cSLikun Gao uint32_t Fclk_PD_Data_limit_c; // Q16 1484ce81151cSLikun Gao uint32_t Fclk_PD_Data_error_coeff; // Q16 1485ce81151cSLikun Gao uint32_t Fclk_PD_Data_error_rate_coeff; // Q16 1486ce81151cSLikun Gao 1487ce81151cSLikun Gao uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16 1488ce81151cSLikun Gao uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS]; 1489ce81151cSLikun Gao uint8_t Mem_DownHystLimit[NUM_UCLK_DPM_LEVELS]; 1490ce81151cSLikun Gao uint16_t Mem_Fps; 1491ce81151cSLikun Gao uint8_t padding[2]; 1492ce81151cSLikun Gao 1493ce81151cSLikun Gao } DpmActivityMonitorCoeffInt_t; 1494ce81151cSLikun Gao 1495ce81151cSLikun Gao 1496ce81151cSLikun Gao typedef struct { 1497ce81151cSLikun Gao DpmActivityMonitorCoeffInt_t DpmActivityMonitorCoeffInt; 1498ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1499ce81151cSLikun Gao } DpmActivityMonitorCoeffIntExternal_t; 1500ce81151cSLikun Gao 1501ce81151cSLikun Gao 1502ce81151cSLikun Gao 1503ce81151cSLikun Gao // Workload bits 1504ce81151cSLikun Gao #define WORKLOAD_PPLIB_DEFAULT_BIT 0 1505ce81151cSLikun Gao #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 1506ce81151cSLikun Gao #define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 1507ce81151cSLikun Gao #define WORKLOAD_PPLIB_VIDEO_BIT 3 1508ce81151cSLikun Gao #define WORKLOAD_PPLIB_VR_BIT 4 1509ce81151cSLikun Gao #define WORKLOAD_PPLIB_COMPUTE_BIT 5 1510ce81151cSLikun Gao #define WORKLOAD_PPLIB_CUSTOM_BIT 6 1511ce81151cSLikun Gao #define WORKLOAD_PPLIB_WINDOW_3D_BIT 7 1512ce81151cSLikun Gao #define WORKLOAD_PPLIB_COUNT 8 1513ce81151cSLikun Gao 1514ce81151cSLikun Gao 1515ce81151cSLikun Gao // These defines are used with the following messages: 1516ce81151cSLikun Gao // SMC_MSG_TransferTableDram2Smu 1517ce81151cSLikun Gao // SMC_MSG_TransferTableSmu2Dram 1518ce81151cSLikun Gao 1519ce81151cSLikun Gao // Table transfer status 1520ce81151cSLikun Gao #define TABLE_TRANSFER_OK 0x0 1521ce81151cSLikun Gao #define TABLE_TRANSFER_FAILED 0xFF 1522ce81151cSLikun Gao #define TABLE_TRANSFER_PENDING 0xAB 1523ce81151cSLikun Gao 1524ce81151cSLikun Gao // Table types 1525ce81151cSLikun Gao #define TABLE_PPTABLE 0 1526ce81151cSLikun Gao #define TABLE_COMBO_PPTABLE 1 1527ce81151cSLikun Gao #define TABLE_WATERMARKS 2 1528ce81151cSLikun Gao #define TABLE_AVFS_PSM_DEBUG 3 1529ce81151cSLikun Gao #define TABLE_PMSTATUSLOG 4 1530ce81151cSLikun Gao #define TABLE_SMU_METRICS 5 1531ce81151cSLikun Gao #define TABLE_DRIVER_SMU_CONFIG 6 1532ce81151cSLikun Gao #define TABLE_ACTIVITY_MONITOR_COEFF 7 1533ce81151cSLikun Gao #define TABLE_OVERDRIVE 8 1534ce81151cSLikun Gao #define TABLE_I2C_COMMANDS 9 1535ce81151cSLikun Gao #define TABLE_DRIVER_INFO 10 1536ce81151cSLikun Gao #define TABLE_ECCINFO 11 1537ce81151cSLikun Gao #define TABLE_COUNT 12 1538ce81151cSLikun Gao 1539ce81151cSLikun Gao //IH Interupt ID 1540ce81151cSLikun Gao #define IH_INTERRUPT_ID_TO_DRIVER 0xFE 1541ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_BACO 0x2 1542ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_AC 0x3 1543ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_DC 0x4 1544ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 0x5 1545ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 0x6 1546ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING 0x7 1547ce81151cSLikun Gao 1548ce81151cSLikun Gao #endif 1549