1ce81151cSLikun Gao /* 2ce81151cSLikun Gao * Copyright 2021 Advanced Micro Devices, Inc. 3ce81151cSLikun Gao * 4ce81151cSLikun Gao * Permission is hereby granted, free of charge, to any person obtaining a 5ce81151cSLikun Gao * copy of this software and associated documentation files (the "Software"), 6ce81151cSLikun Gao * to deal in the Software without restriction, including without limitation 7ce81151cSLikun Gao * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8ce81151cSLikun Gao * and/or sell copies of the Software, and to permit persons to whom the 9ce81151cSLikun Gao * Software is furnished to do so, subject to the following conditions: 10ce81151cSLikun Gao * 11ce81151cSLikun Gao * The above copyright notice and this permission notice shall be included in 12ce81151cSLikun Gao * all copies or substantial portions of the Software. 13ce81151cSLikun Gao * 14ce81151cSLikun Gao * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15ce81151cSLikun Gao * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16ce81151cSLikun Gao * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17ce81151cSLikun Gao * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18ce81151cSLikun Gao * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19ce81151cSLikun Gao * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20ce81151cSLikun Gao * OTHER DEALINGS IN THE SOFTWARE. 21ce81151cSLikun Gao * 22ce81151cSLikun Gao */ 23ce81151cSLikun Gao 24ce81151cSLikun Gao #ifndef SMU13_DRIVER_IF_V13_0_0_H 25ce81151cSLikun Gao #define SMU13_DRIVER_IF_V13_0_0_H 26ce81151cSLikun Gao 27ce81151cSLikun Gao //Increment this version if SkuTable_t or BoardTable_t change 287e5632cdSKenneth Feng #define PPTABLE_VERSION 0x26 29ce81151cSLikun Gao 30ce81151cSLikun Gao #define NUM_GFXCLK_DPM_LEVELS 16 31ce81151cSLikun Gao #define NUM_SOCCLK_DPM_LEVELS 8 32ce81151cSLikun Gao #define NUM_MP0CLK_DPM_LEVELS 2 33ce81151cSLikun Gao #define NUM_DCLK_DPM_LEVELS 8 34ce81151cSLikun Gao #define NUM_VCLK_DPM_LEVELS 8 35ce81151cSLikun Gao #define NUM_DISPCLK_DPM_LEVELS 8 36ce81151cSLikun Gao #define NUM_DPPCLK_DPM_LEVELS 8 37ce81151cSLikun Gao #define NUM_DPREFCLK_DPM_LEVELS 8 38ce81151cSLikun Gao #define NUM_DCFCLK_DPM_LEVELS 8 39ce81151cSLikun Gao #define NUM_DTBCLK_DPM_LEVELS 8 40ce81151cSLikun Gao #define NUM_UCLK_DPM_LEVELS 4 41ce81151cSLikun Gao #define NUM_LINK_LEVELS 3 42ce81151cSLikun Gao #define NUM_FCLK_DPM_LEVELS 8 43ce81151cSLikun Gao #define NUM_OD_FAN_MAX_POINTS 6 44ce81151cSLikun Gao 45ce81151cSLikun Gao // Feature Control Defines 46ce81151cSLikun Gao #define FEATURE_FW_DATA_READ_BIT 0 47ce81151cSLikun Gao #define FEATURE_DPM_GFXCLK_BIT 1 48ce81151cSLikun Gao #define FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT 2 49ce81151cSLikun Gao #define FEATURE_DPM_UCLK_BIT 3 50ce81151cSLikun Gao #define FEATURE_DPM_FCLK_BIT 4 51ce81151cSLikun Gao #define FEATURE_DPM_SOCCLK_BIT 5 52ce81151cSLikun Gao #define FEATURE_DPM_MP0CLK_BIT 6 53ce81151cSLikun Gao #define FEATURE_DPM_LINK_BIT 7 54ce81151cSLikun Gao #define FEATURE_DPM_DCN_BIT 8 55ce81151cSLikun Gao #define FEATURE_VMEMP_SCALING_BIT 9 56ce81151cSLikun Gao #define FEATURE_VDDIO_MEM_SCALING_BIT 10 57ce81151cSLikun Gao #define FEATURE_DS_GFXCLK_BIT 11 58ce81151cSLikun Gao #define FEATURE_DS_SOCCLK_BIT 12 59ce81151cSLikun Gao #define FEATURE_DS_FCLK_BIT 13 60ce81151cSLikun Gao #define FEATURE_DS_LCLK_BIT 14 61ce81151cSLikun Gao #define FEATURE_DS_DCFCLK_BIT 15 62ce81151cSLikun Gao #define FEATURE_DS_UCLK_BIT 16 63ce81151cSLikun Gao #define FEATURE_GFX_ULV_BIT 17 64ce81151cSLikun Gao #define FEATURE_FW_DSTATE_BIT 18 65ce81151cSLikun Gao #define FEATURE_GFXOFF_BIT 19 66ce81151cSLikun Gao #define FEATURE_BACO_BIT 20 67ce81151cSLikun Gao #define FEATURE_MM_DPM_BIT 21 68ce81151cSLikun Gao #define FEATURE_SOC_MPCLK_DS_BIT 22 69ce81151cSLikun Gao #define FEATURE_BACO_MPCLK_DS_BIT 23 70ce81151cSLikun Gao #define FEATURE_THROTTLERS_BIT 24 71ce81151cSLikun Gao #define FEATURE_SMARTSHIFT_BIT 25 72ce81151cSLikun Gao #define FEATURE_GTHR_BIT 26 73ce81151cSLikun Gao #define FEATURE_ACDC_BIT 27 74ce81151cSLikun Gao #define FEATURE_VR0HOT_BIT 28 75ce81151cSLikun Gao #define FEATURE_FW_CTF_BIT 29 76ce81151cSLikun Gao #define FEATURE_FAN_CONTROL_BIT 30 77ce81151cSLikun Gao #define FEATURE_GFX_DCS_BIT 31 78ce81151cSLikun Gao #define FEATURE_GFX_READ_MARGIN_BIT 32 79ce81151cSLikun Gao #define FEATURE_LED_DISPLAY_BIT 33 80ce81151cSLikun Gao #define FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT 34 81ce81151cSLikun Gao #define FEATURE_OUT_OF_BAND_MONITOR_BIT 35 82ce81151cSLikun Gao #define FEATURE_OPTIMIZED_VMIN_BIT 36 83ce81151cSLikun Gao #define FEATURE_GFX_IMU_BIT 37 84ce81151cSLikun Gao #define FEATURE_BOOT_TIME_CAL_BIT 38 85ce81151cSLikun Gao #define FEATURE_GFX_PCC_DFLL_BIT 39 86ce81151cSLikun Gao #define FEATURE_SOC_CG_BIT 40 87ce81151cSLikun Gao #define FEATURE_DF_CSTATE_BIT 41 88ce81151cSLikun Gao #define FEATURE_GFX_EDC_BIT 42 89ce81151cSLikun Gao #define FEATURE_BOOT_POWER_OPT_BIT 43 90ce81151cSLikun Gao #define FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT 44 91ce81151cSLikun Gao #define FEATURE_DS_VCN_BIT 45 92ce81151cSLikun Gao #define FEATURE_BACO_CG_BIT 46 93ce81151cSLikun Gao #define FEATURE_MEM_TEMP_READ_BIT 47 94ce81151cSLikun Gao #define FEATURE_ATHUB_MMHUB_PG_BIT 48 95ce81151cSLikun Gao #define FEATURE_SOC_PCC_BIT 49 961f3dfde4SEvan Quan #define FEATURE_EDC_PWRBRK_BIT 50 97ce81151cSLikun Gao #define FEATURE_SPARE_51_BIT 51 98ce81151cSLikun Gao #define FEATURE_SPARE_52_BIT 52 99ce81151cSLikun Gao #define FEATURE_SPARE_53_BIT 53 100ce81151cSLikun Gao #define FEATURE_SPARE_54_BIT 54 101ce81151cSLikun Gao #define FEATURE_SPARE_55_BIT 55 102ce81151cSLikun Gao #define FEATURE_SPARE_56_BIT 56 103ce81151cSLikun Gao #define FEATURE_SPARE_57_BIT 57 104ce81151cSLikun Gao #define FEATURE_SPARE_58_BIT 58 105ce81151cSLikun Gao #define FEATURE_SPARE_59_BIT 59 106ce81151cSLikun Gao #define FEATURE_SPARE_60_BIT 60 107ce81151cSLikun Gao #define FEATURE_SPARE_61_BIT 61 108ce81151cSLikun Gao #define FEATURE_SPARE_62_BIT 62 109ce81151cSLikun Gao #define FEATURE_SPARE_63_BIT 63 110ce81151cSLikun Gao #define NUM_FEATURES 64 111ce81151cSLikun Gao 1127e5632cdSKenneth Feng #define ALLOWED_FEATURE_CTRL_DEFAULT 0xFFFFFFFFFFFFFFFFULL 1137e5632cdSKenneth Feng #define ALLOWED_FEATURE_CTRL_SCPM ((1 << FEATURE_DPM_GFXCLK_BIT) | \ 1147e5632cdSKenneth Feng (1 << FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | \ 1157e5632cdSKenneth Feng (1 << FEATURE_DPM_UCLK_BIT) | \ 1167e5632cdSKenneth Feng (1 << FEATURE_DPM_FCLK_BIT) | \ 1177e5632cdSKenneth Feng (1 << FEATURE_DPM_SOCCLK_BIT) | \ 1187e5632cdSKenneth Feng (1 << FEATURE_DPM_MP0CLK_BIT) | \ 1197e5632cdSKenneth Feng (1 << FEATURE_DPM_LINK_BIT) | \ 1207e5632cdSKenneth Feng (1 << FEATURE_DPM_DCN_BIT) | \ 1217e5632cdSKenneth Feng (1 << FEATURE_DS_GFXCLK_BIT) | \ 1227e5632cdSKenneth Feng (1 << FEATURE_DS_SOCCLK_BIT) | \ 1237e5632cdSKenneth Feng (1 << FEATURE_DS_FCLK_BIT) | \ 1247e5632cdSKenneth Feng (1 << FEATURE_DS_LCLK_BIT) | \ 1257e5632cdSKenneth Feng (1 << FEATURE_DS_DCFCLK_BIT) | \ 126*2bce0f9bSEvan Quan (1 << FEATURE_DS_UCLK_BIT) | \ 127*2bce0f9bSEvan Quan (1ULL << FEATURE_DS_VCN_BIT)) 1287e5632cdSKenneth Feng 129ce81151cSLikun Gao //For use with feature control messages 130ce81151cSLikun Gao typedef enum { 131ce81151cSLikun Gao FEATURE_PWR_ALL, 132ce81151cSLikun Gao FEATURE_PWR_S5, 133ce81151cSLikun Gao FEATURE_PWR_BACO, 134ce81151cSLikun Gao FEATURE_PWR_SOC, 135ce81151cSLikun Gao FEATURE_PWR_GFX, 136ce81151cSLikun Gao FEATURE_PWR_DOMAIN_COUNT, 137ce81151cSLikun Gao } FEATURE_PWR_DOMAIN_e; 138ce81151cSLikun Gao 139ce81151cSLikun Gao 140ce81151cSLikun Gao // Debug Overrides Bitmask 141ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000001 142ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK 0x00000002 143ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK 0x00000004 144ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK 0x00000008 145ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x00000010 146ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_VCN_PG 0x00000020 147ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_FMAX_VMAX 0x00000040 148ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS 0x00000080 149ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK 0x00000100 150ce81151cSLikun Gao #define DEBUG_OVERRIDE_DISABLE_DFLL 0x00000200 151ce81151cSLikun Gao #define DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE 0x00000400 152ce81151cSLikun Gao #define DEBUG_OVERRIDE_DFLL_MASTER_MODE 0x00000800 1537e5632cdSKenneth Feng #define DEBUG_OVERRIDE_ENABLE_PROFILING_MODE 0x00001000 154ce81151cSLikun Gao 155ce81151cSLikun Gao // VR Mapping Bit Defines 156ce81151cSLikun Gao #define VR_MAPPING_VR_SELECT_MASK 0x01 157ce81151cSLikun Gao #define VR_MAPPING_VR_SELECT_SHIFT 0x00 158ce81151cSLikun Gao 159ce81151cSLikun Gao #define VR_MAPPING_PLANE_SELECT_MASK 0x02 160ce81151cSLikun Gao #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 161ce81151cSLikun Gao 162ce81151cSLikun Gao // PSI Bit Defines 163ce81151cSLikun Gao #define PSI_SEL_VR0_PLANE0_PSI0 0x01 164ce81151cSLikun Gao #define PSI_SEL_VR0_PLANE0_PSI1 0x02 165ce81151cSLikun Gao #define PSI_SEL_VR0_PLANE1_PSI0 0x04 166ce81151cSLikun Gao #define PSI_SEL_VR0_PLANE1_PSI1 0x08 167ce81151cSLikun Gao #define PSI_SEL_VR1_PLANE0_PSI0 0x10 168ce81151cSLikun Gao #define PSI_SEL_VR1_PLANE0_PSI1 0x20 169ce81151cSLikun Gao #define PSI_SEL_VR1_PLANE1_PSI0 0x40 170ce81151cSLikun Gao #define PSI_SEL_VR1_PLANE1_PSI1 0x80 171ce81151cSLikun Gao 172ce81151cSLikun Gao typedef enum { 173ce81151cSLikun Gao SVI_PSI_0, // Full phase count (default) 174ce81151cSLikun Gao SVI_PSI_1, // Phase count 1st level 175ce81151cSLikun Gao SVI_PSI_2, // Phase count 2nd level 176ce81151cSLikun Gao SVI_PSI_3, // Single phase operation + active diode emulation 177ce81151cSLikun Gao SVI_PSI_4, // Single phase operation + passive diode emulation *optional* 178ce81151cSLikun Gao SVI_PSI_5, // Reserved 179ce81151cSLikun Gao SVI_PSI_6, // Power down to 0V (voltage regulation disabled) 180ce81151cSLikun Gao SVI_PSI_7, // Automated phase shedding and diode emulation 181ce81151cSLikun Gao } SVI_PSI_e; 182ce81151cSLikun Gao 183ce81151cSLikun Gao // Throttler Control/Status Bits 184ce81151cSLikun Gao #define THROTTLER_TEMP_EDGE_BIT 0 185ce81151cSLikun Gao #define THROTTLER_TEMP_HOTSPOT_BIT 1 186ce81151cSLikun Gao #define THROTTLER_TEMP_HOTSPOT_G_BIT 2 187ce81151cSLikun Gao #define THROTTLER_TEMP_HOTSPOT_M_BIT 3 188ce81151cSLikun Gao #define THROTTLER_TEMP_MEM_BIT 4 189ce81151cSLikun Gao #define THROTTLER_TEMP_VR_GFX_BIT 5 190ce81151cSLikun Gao #define THROTTLER_TEMP_VR_MEM0_BIT 6 191ce81151cSLikun Gao #define THROTTLER_TEMP_VR_MEM1_BIT 7 192ce81151cSLikun Gao #define THROTTLER_TEMP_VR_SOC_BIT 8 193ce81151cSLikun Gao #define THROTTLER_TEMP_VR_U_BIT 9 194ce81151cSLikun Gao #define THROTTLER_TEMP_LIQUID0_BIT 10 195ce81151cSLikun Gao #define THROTTLER_TEMP_LIQUID1_BIT 11 196ce81151cSLikun Gao #define THROTTLER_TEMP_PLX_BIT 12 197ce81151cSLikun Gao #define THROTTLER_TDC_GFX_BIT 13 198ce81151cSLikun Gao #define THROTTLER_TDC_SOC_BIT 14 199ce81151cSLikun Gao #define THROTTLER_TDC_U_BIT 15 200ce81151cSLikun Gao #define THROTTLER_PPT0_BIT 16 201ce81151cSLikun Gao #define THROTTLER_PPT1_BIT 17 202ce81151cSLikun Gao #define THROTTLER_PPT2_BIT 18 203ce81151cSLikun Gao #define THROTTLER_PPT3_BIT 19 204ce81151cSLikun Gao #define THROTTLER_FIT_BIT 20 205ce81151cSLikun Gao #define THROTTLER_GFX_APCC_PLUS_BIT 21 206ce81151cSLikun Gao #define THROTTLER_COUNT 22 207ce81151cSLikun Gao 208ce81151cSLikun Gao // FW DState Features Control Bits 209ce81151cSLikun Gao #define FW_DSTATE_SOC_ULV_BIT 0 210ce81151cSLikun Gao #define FW_DSTATE_G6_HSR_BIT 1 211ce81151cSLikun Gao #define FW_DSTATE_G6_PHY_VMEMP_OFF_BIT 2 212ce81151cSLikun Gao #define FW_DSTATE_SMN_DS_BIT 3 213ce81151cSLikun Gao #define FW_DSTATE_MP1_WHISPER_MODE_BIT 4 214ce81151cSLikun Gao #define FW_DSTATE_SOC_LIV_MIN_BIT 5 215ce81151cSLikun Gao #define FW_DSTATE_SOC_PLL_PWRDN_BIT 6 216ce81151cSLikun Gao #define FW_DSTATE_MEM_PLL_PWRDN_BIT 7 217ce81151cSLikun Gao #define FW_DSTATE_MALL_ALLOC_BIT 8 218ce81151cSLikun Gao #define FW_DSTATE_MEM_PSI_BIT 9 219ce81151cSLikun Gao #define FW_DSTATE_HSR_NON_STROBE_BIT 10 220ce81151cSLikun Gao #define FW_DSTATE_MP0_ENTER_WFI_BIT 11 221ce81151cSLikun Gao #define FW_DSTATE_U_ULV_BIT 12 222ce81151cSLikun Gao #define FW_DSTATE_MALL_FLUSH_BIT 13 223ce81151cSLikun Gao #define FW_DSTATE_SOC_PSI_BIT 14 224ce81151cSLikun Gao #define FW_DSTATE_U_PSI_BIT 15 225ce81151cSLikun Gao #define FW_DSTATE_UCP_DS_BIT 16 226ce81151cSLikun Gao #define FW_DSTATE_CSRCLK_DS_BIT 17 227ce81151cSLikun Gao #define FW_DSTATE_MMHUB_INTERLOCK_BIT 18 228ce81151cSLikun Gao #define FW_DSTATE_D0i3_2_QUIET_FW_BIT 19 229ce81151cSLikun Gao #define FW_DSTATE_CLDO_PRG_BIT 20 230ce81151cSLikun Gao #define FW_DSTATE_DF_PLL_PWRDN_BIT 21 231ce81151cSLikun Gao #define FW_DSTATE_U_LOW_PWR_MODE_EN_BIT 22 232ce81151cSLikun Gao #define FW_DSTATE_GFX_PSI6_BIT 23 233ce81151cSLikun Gao #define FW_DSTATE_GFX_VR_PWR_STAGE_BIT 24 234ce81151cSLikun Gao 235ce81151cSLikun Gao //LED Display Mask & Control Bits 236ce81151cSLikun Gao #define LED_DISPLAY_GFX_DPM_BIT 0 237ce81151cSLikun Gao #define LED_DISPLAY_PCIE_BIT 1 238ce81151cSLikun Gao #define LED_DISPLAY_ERROR_BIT 2 239ce81151cSLikun Gao 240ce81151cSLikun Gao 241ce81151cSLikun Gao #define MEM_TEMP_READ_OUT_OF_BAND_BIT 0 242ce81151cSLikun Gao #define MEM_TEMP_READ_IN_BAND_REFRESH_BIT 1 243ce81151cSLikun Gao #define MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT 2 244ce81151cSLikun Gao 245ce81151cSLikun Gao typedef enum { 246ce81151cSLikun Gao SMARTSHIFT_VERSION_1, 247ce81151cSLikun Gao SMARTSHIFT_VERSION_2, 248ce81151cSLikun Gao SMARTSHIFT_VERSION_3, 249ce81151cSLikun Gao } SMARTSHIFT_VERSION_e; 250ce81151cSLikun Gao 251ce81151cSLikun Gao typedef enum { 252ce81151cSLikun Gao FOPT_CALC_AC_CALC_DC, 253ce81151cSLikun Gao FOPT_PPTABLE_AC_CALC_DC, 254ce81151cSLikun Gao FOPT_CALC_AC_PPTABLE_DC, 255ce81151cSLikun Gao FOPT_PPTABLE_AC_PPTABLE_DC, 256ce81151cSLikun Gao } FOPT_CALC_e; 257ce81151cSLikun Gao 258ce81151cSLikun Gao typedef enum { 259ce81151cSLikun Gao DRAM_BIT_WIDTH_DISABLED = 0, 260ce81151cSLikun Gao DRAM_BIT_WIDTH_X_8 = 8, 261ce81151cSLikun Gao DRAM_BIT_WIDTH_X_16 = 16, 262ce81151cSLikun Gao DRAM_BIT_WIDTH_X_32 = 32, 263ce81151cSLikun Gao DRAM_BIT_WIDTH_X_64 = 64, 264ce81151cSLikun Gao DRAM_BIT_WIDTH_X_128 = 128, 265ce81151cSLikun Gao DRAM_BIT_WIDTH_COUNT, 266ce81151cSLikun Gao } DRAM_BIT_WIDTH_TYPE_e; 267ce81151cSLikun Gao 268ce81151cSLikun Gao //I2C Interface 269ce81151cSLikun Gao #define NUM_I2C_CONTROLLERS 8 270ce81151cSLikun Gao 271ce81151cSLikun Gao #define I2C_CONTROLLER_ENABLED 1 272ce81151cSLikun Gao #define I2C_CONTROLLER_DISABLED 0 273ce81151cSLikun Gao 274ce81151cSLikun Gao #define MAX_SW_I2C_COMMANDS 24 275ce81151cSLikun Gao 276ce81151cSLikun Gao typedef enum { 277ce81151cSLikun Gao I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0 278ce81151cSLikun Gao I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1 279ce81151cSLikun Gao I2C_CONTROLLER_PORT_COUNT, 280ce81151cSLikun Gao } I2cControllerPort_e; 281ce81151cSLikun Gao 282ce81151cSLikun Gao typedef enum { 283ce81151cSLikun Gao I2C_CONTROLLER_NAME_VR_GFX = 0, 284ce81151cSLikun Gao I2C_CONTROLLER_NAME_VR_SOC, 285ce81151cSLikun Gao I2C_CONTROLLER_NAME_VR_VMEMP, 286ce81151cSLikun Gao I2C_CONTROLLER_NAME_VR_VDDIO, 287ce81151cSLikun Gao I2C_CONTROLLER_NAME_LIQUID0, 288ce81151cSLikun Gao I2C_CONTROLLER_NAME_LIQUID1, 289ce81151cSLikun Gao I2C_CONTROLLER_NAME_PLX, 2907e5632cdSKenneth Feng I2C_CONTROLLER_NAME_FAN_INTAKE, 291ce81151cSLikun Gao I2C_CONTROLLER_NAME_COUNT, 292ce81151cSLikun Gao } I2cControllerName_e; 293ce81151cSLikun Gao 294ce81151cSLikun Gao typedef enum { 295ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 296ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_VR_GFX, 297ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_VR_SOC, 298ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_VR_VMEMP, 299ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_VR_VDDIO, 300ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_LIQUID0, 301ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_LIQUID1, 302ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_PLX, 3037e5632cdSKenneth Feng I2C_CONTROLLER_THROTTLER_FAN_INTAKE, 304ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_INA3221, 305ce81151cSLikun Gao I2C_CONTROLLER_THROTTLER_COUNT, 306ce81151cSLikun Gao } I2cControllerThrottler_e; 307ce81151cSLikun Gao 308ce81151cSLikun Gao typedef enum { 309ce81151cSLikun Gao I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5, 310ce81151cSLikun Gao I2C_CONTROLLER_PROTOCOL_VR_IR35217, 3117e5632cdSKenneth Feng I2C_CONTROLLER_PROTOCOL_TMP_MAX31875, 312ce81151cSLikun Gao I2C_CONTROLLER_PROTOCOL_INA3221, 313ce81151cSLikun Gao I2C_CONTROLLER_PROTOCOL_COUNT, 314ce81151cSLikun Gao } I2cControllerProtocol_e; 315ce81151cSLikun Gao 316ce81151cSLikun Gao typedef struct { 317ce81151cSLikun Gao uint8_t Enabled; 318ce81151cSLikun Gao uint8_t Speed; 319ce81151cSLikun Gao uint8_t SlaveAddress; 320ce81151cSLikun Gao uint8_t ControllerPort; 321ce81151cSLikun Gao uint8_t ControllerName; 322ce81151cSLikun Gao uint8_t ThermalThrotter; 323ce81151cSLikun Gao uint8_t I2cProtocol; 324ce81151cSLikun Gao uint8_t PaddingConfig; 325ce81151cSLikun Gao } I2cControllerConfig_t; 326ce81151cSLikun Gao 327ce81151cSLikun Gao typedef enum { 328ce81151cSLikun Gao I2C_PORT_SVD_SCL = 0, 329ce81151cSLikun Gao I2C_PORT_GPIO, 330ce81151cSLikun Gao } I2cPort_e; 331ce81151cSLikun Gao 332ce81151cSLikun Gao typedef enum { 333ce81151cSLikun Gao I2C_SPEED_FAST_50K = 0, //50 Kbits/s 334ce81151cSLikun Gao I2C_SPEED_FAST_100K, //100 Kbits/s 335ce81151cSLikun Gao I2C_SPEED_FAST_400K, //400 Kbits/s 336ce81151cSLikun Gao I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 337ce81151cSLikun Gao I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 338ce81151cSLikun Gao I2C_SPEED_HIGH_2M, //2.3 Mbits/s 339ce81151cSLikun Gao I2C_SPEED_COUNT, 340ce81151cSLikun Gao } I2cSpeed_e; 341ce81151cSLikun Gao 342ce81151cSLikun Gao typedef enum { 343ce81151cSLikun Gao I2C_CMD_READ = 0, 344ce81151cSLikun Gao I2C_CMD_WRITE, 345ce81151cSLikun Gao I2C_CMD_COUNT, 346ce81151cSLikun Gao } I2cCmdType_e; 347ce81151cSLikun Gao 348ce81151cSLikun Gao #define CMDCONFIG_STOP_BIT 0 349ce81151cSLikun Gao #define CMDCONFIG_RESTART_BIT 1 350ce81151cSLikun Gao #define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write 351ce81151cSLikun Gao 352ce81151cSLikun Gao #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 353ce81151cSLikun Gao #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 354ce81151cSLikun Gao #define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT) 355ce81151cSLikun Gao 356ce81151cSLikun Gao typedef struct { 357ce81151cSLikun Gao uint8_t ReadWriteData; //Return data for read. Data to send for write 358ce81151cSLikun Gao uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write 359ce81151cSLikun Gao } SwI2cCmd_t; //SW I2C Command Table 360ce81151cSLikun Gao 361ce81151cSLikun Gao typedef struct { 362ce81151cSLikun Gao uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 363ce81151cSLikun Gao uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select 364ce81151cSLikun Gao uint8_t SlaveAddress; //Slave address of device 365ce81151cSLikun Gao uint8_t NumCmds; //Number of commands 366ce81151cSLikun Gao 367ce81151cSLikun Gao SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 368ce81151cSLikun Gao } SwI2cRequest_t; // SW I2C Request Table 369ce81151cSLikun Gao 370ce81151cSLikun Gao typedef struct { 371ce81151cSLikun Gao SwI2cRequest_t SwI2cRequest; 372ce81151cSLikun Gao 373ce81151cSLikun Gao uint32_t Spare[8]; 374ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 375ce81151cSLikun Gao } SwI2cRequestExternal_t; 376ce81151cSLikun Gao 377ce81151cSLikun Gao typedef struct { 378ce81151cSLikun Gao uint64_t mca_umc_status; 379ce81151cSLikun Gao uint64_t mca_umc_addr; 380ce81151cSLikun Gao 381ce81151cSLikun Gao uint16_t ce_count_lo_chip; 382ce81151cSLikun Gao uint16_t ce_count_hi_chip; 383ce81151cSLikun Gao 384ce81151cSLikun Gao uint32_t eccPadding; 385ce81151cSLikun Gao } EccInfo_t; 386ce81151cSLikun Gao 387ce81151cSLikun Gao typedef struct { 388ce81151cSLikun Gao EccInfo_t EccInfo[24]; 389ce81151cSLikun Gao } EccInfoTable_t; 390ce81151cSLikun Gao 391ce81151cSLikun Gao //D3HOT sequences 392ce81151cSLikun Gao typedef enum { 393ce81151cSLikun Gao BACO_SEQUENCE, 394ce81151cSLikun Gao MSR_SEQUENCE, 395ce81151cSLikun Gao BAMACO_SEQUENCE, 396ce81151cSLikun Gao ULPS_SEQUENCE, 397ce81151cSLikun Gao D3HOT_SEQUENCE_COUNT, 398ce81151cSLikun Gao } D3HOTSequence_e; 399ce81151cSLikun Gao 400ce81151cSLikun Gao //This is aligned with RSMU PGFSM Register Mapping 401ce81151cSLikun Gao typedef enum { 402ce81151cSLikun Gao PG_DYNAMIC_MODE = 0, 403ce81151cSLikun Gao PG_STATIC_MODE, 404ce81151cSLikun Gao } PowerGatingMode_e; 405ce81151cSLikun Gao 406ce81151cSLikun Gao //This is aligned with RSMU PGFSM Register Mapping 407ce81151cSLikun Gao typedef enum { 408ce81151cSLikun Gao PG_POWER_DOWN = 0, 409ce81151cSLikun Gao PG_POWER_UP, 410ce81151cSLikun Gao } PowerGatingSettings_e; 411ce81151cSLikun Gao 412ce81151cSLikun Gao typedef struct { 413ce81151cSLikun Gao uint32_t a; // store in IEEE float format in this variable 414ce81151cSLikun Gao uint32_t b; // store in IEEE float format in this variable 415ce81151cSLikun Gao uint32_t c; // store in IEEE float format in this variable 416ce81151cSLikun Gao } QuadraticInt_t; 417ce81151cSLikun Gao 418ce81151cSLikun Gao typedef struct { 419ce81151cSLikun Gao uint32_t m; // store in IEEE float format in this variable 420ce81151cSLikun Gao uint32_t b; // store in IEEE float format in this variable 421ce81151cSLikun Gao } LinearInt_t; 422ce81151cSLikun Gao 423ce81151cSLikun Gao typedef struct { 424ce81151cSLikun Gao uint32_t a; // store in IEEE float format in this variable 425ce81151cSLikun Gao uint32_t b; // store in IEEE float format in this variable 426ce81151cSLikun Gao uint32_t c; // store in IEEE float format in this variable 427ce81151cSLikun Gao } DroopInt_t; 428ce81151cSLikun Gao 429ce81151cSLikun Gao typedef enum { 430ce81151cSLikun Gao DCS_ARCH_DISABLED, 431ce81151cSLikun Gao DCS_ARCH_FADCS, 432ce81151cSLikun Gao DCS_ARCH_ASYNC, 433ce81151cSLikun Gao } DCS_ARCH_e; 434ce81151cSLikun Gao 435ce81151cSLikun Gao //Only Clks that have DPM descriptors are listed here 436ce81151cSLikun Gao typedef enum { 437ce81151cSLikun Gao PPCLK_GFXCLK = 0, 438ce81151cSLikun Gao PPCLK_SOCCLK, 439ce81151cSLikun Gao PPCLK_UCLK, 440ce81151cSLikun Gao PPCLK_FCLK, 441ce81151cSLikun Gao PPCLK_DCLK_0, 442ce81151cSLikun Gao PPCLK_VCLK_0, 443ce81151cSLikun Gao PPCLK_DCLK_1, 444ce81151cSLikun Gao PPCLK_VCLK_1, 445ce81151cSLikun Gao PPCLK_DISPCLK, 446ce81151cSLikun Gao PPCLK_DPPCLK, 447ce81151cSLikun Gao PPCLK_DPREFCLK, 448ce81151cSLikun Gao PPCLK_DCFCLK, 449ce81151cSLikun Gao PPCLK_DTBCLK, 450ce81151cSLikun Gao PPCLK_COUNT, 451ce81151cSLikun Gao } PPCLK_e; 452ce81151cSLikun Gao 453ce81151cSLikun Gao typedef enum { 454ce81151cSLikun Gao VOLTAGE_MODE_PPTABLE = 0, 455ce81151cSLikun Gao VOLTAGE_MODE_FUSES, 456ce81151cSLikun Gao VOLTAGE_MODE_COUNT, 457ce81151cSLikun Gao } VOLTAGE_MODE_e; 458ce81151cSLikun Gao 459ce81151cSLikun Gao 460ce81151cSLikun Gao typedef enum { 461ce81151cSLikun Gao AVFS_VOLTAGE_GFX = 0, 462ce81151cSLikun Gao AVFS_VOLTAGE_SOC, 463ce81151cSLikun Gao AVFS_VOLTAGE_COUNT, 464ce81151cSLikun Gao } AVFS_VOLTAGE_TYPE_e; 465ce81151cSLikun Gao 466ce81151cSLikun Gao typedef enum { 467ce81151cSLikun Gao AVFS_TEMP_COLD = 0, 468ce81151cSLikun Gao AVFS_TEMP_HOT, 469ce81151cSLikun Gao AVFS_TEMP_COUNT, 470ce81151cSLikun Gao } AVFS_TEMP_e; 471ce81151cSLikun Gao 472ce81151cSLikun Gao typedef enum { 473ce81151cSLikun Gao AVFS_D_G, 474ce81151cSLikun Gao AVFS_D_M_B, 475ce81151cSLikun Gao AVFS_D_M_S, 476ce81151cSLikun Gao AVFS_D_COUNT, 477ce81151cSLikun Gao } AVFS_D_e; 478ce81151cSLikun Gao 479ce81151cSLikun Gao typedef enum { 480ce81151cSLikun Gao UCLK_DIV_BY_1 = 0, 481ce81151cSLikun Gao UCLK_DIV_BY_2, 482ce81151cSLikun Gao UCLK_DIV_BY_4, 483ce81151cSLikun Gao UCLK_DIV_BY_8, 484ce81151cSLikun Gao } UCLK_DIV_e; 485ce81151cSLikun Gao 486ce81151cSLikun Gao typedef enum { 487ce81151cSLikun Gao GPIO_INT_POLARITY_ACTIVE_LOW = 0, 488ce81151cSLikun Gao GPIO_INT_POLARITY_ACTIVE_HIGH, 489ce81151cSLikun Gao } GpioIntPolarity_e; 490ce81151cSLikun Gao 491ce81151cSLikun Gao typedef enum { 492ce81151cSLikun Gao PWR_CONFIG_TDP = 0, 493ce81151cSLikun Gao PWR_CONFIG_TGP, 494ce81151cSLikun Gao PWR_CONFIG_TCP_ESTIMATED, 495ce81151cSLikun Gao PWR_CONFIG_TCP_MEASURED, 496ce81151cSLikun Gao } PwrConfig_e; 497ce81151cSLikun Gao 498ce81151cSLikun Gao typedef struct { 499ce81151cSLikun Gao uint8_t Padding; 500ce81151cSLikun Gao uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 501ce81151cSLikun Gao uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 502ce81151cSLikun Gao uint8_t CalculateFopt; // Indication whether FW should calculate Fopt or use values below. Reference FOPT_CALC_e 503ce81151cSLikun Gao LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 504ce81151cSLikun Gao uint32_t Padding3[3]; 505ce81151cSLikun Gao uint16_t Padding4; 506ce81151cSLikun Gao uint16_t FoptimalDc; //Foptimal frequency in DC power mode. 507ce81151cSLikun Gao uint16_t FoptimalAc; //Foptimal frequency in AC power mode. 508ce81151cSLikun Gao uint16_t Padding2; 509ce81151cSLikun Gao } DpmDescriptor_t; 510ce81151cSLikun Gao 511ce81151cSLikun Gao typedef enum { 512ce81151cSLikun Gao PPT_THROTTLER_PPT0, 513ce81151cSLikun Gao PPT_THROTTLER_PPT1, 514ce81151cSLikun Gao PPT_THROTTLER_PPT2, 515ce81151cSLikun Gao PPT_THROTTLER_PPT3, 516ce81151cSLikun Gao PPT_THROTTLER_COUNT 517ce81151cSLikun Gao } PPT_THROTTLER_e; 518ce81151cSLikun Gao 519ce81151cSLikun Gao typedef enum { 520ce81151cSLikun Gao TEMP_EDGE, 521ce81151cSLikun Gao TEMP_HOTSPOT, 522ce81151cSLikun Gao TEMP_HOTSPOT_G, 523ce81151cSLikun Gao TEMP_HOTSPOT_M, 524ce81151cSLikun Gao TEMP_MEM, 525ce81151cSLikun Gao TEMP_VR_GFX, 526ce81151cSLikun Gao TEMP_VR_MEM0, 527ce81151cSLikun Gao TEMP_VR_MEM1, 528*2bce0f9bSEvan Quan TEMP_VR_SOC, 529ce81151cSLikun Gao TEMP_VR_U, 530ce81151cSLikun Gao TEMP_LIQUID0, 531ce81151cSLikun Gao TEMP_LIQUID1, 532ce81151cSLikun Gao TEMP_PLX, 533ce81151cSLikun Gao TEMP_COUNT, 534ce81151cSLikun Gao } TEMP_e; 535ce81151cSLikun Gao 536ce81151cSLikun Gao typedef enum { 537ce81151cSLikun Gao TDC_THROTTLER_GFX, 538ce81151cSLikun Gao TDC_THROTTLER_SOC, 539ce81151cSLikun Gao TDC_THROTTLER_U, 540ce81151cSLikun Gao TDC_THROTTLER_COUNT 541ce81151cSLikun Gao } TDC_THROTTLER_e; 542ce81151cSLikun Gao 543ce81151cSLikun Gao typedef enum { 544ce81151cSLikun Gao SVI_PLANE_GFX, 545ce81151cSLikun Gao SVI_PLANE_SOC, 546ce81151cSLikun Gao SVI_PLANE_VMEMP, 547ce81151cSLikun Gao SVI_PLANE_VDDIO_MEM, 548ce81151cSLikun Gao SVI_PLANE_U, 549ce81151cSLikun Gao SVI_PLANE_COUNT, 550ce81151cSLikun Gao } SVI_PLANE_e; 551ce81151cSLikun Gao 552ce81151cSLikun Gao typedef enum { 553ce81151cSLikun Gao PMFW_VOLT_PLANE_GFX, 554ce81151cSLikun Gao PMFW_VOLT_PLANE_SOC, 555ce81151cSLikun Gao PMFW_VOLT_PLANE_COUNT 556ce81151cSLikun Gao } PMFW_VOLT_PLANE_e; 557ce81151cSLikun Gao 558ce81151cSLikun Gao typedef enum { 559ce81151cSLikun Gao CUSTOMER_VARIANT_ROW, 560ce81151cSLikun Gao CUSTOMER_VARIANT_FALCON, 561ce81151cSLikun Gao CUSTOMER_VARIANT_COUNT, 562ce81151cSLikun Gao } CUSTOMER_VARIANT_e; 563ce81151cSLikun Gao 564ce81151cSLikun Gao typedef enum { 565ce81151cSLikun Gao POWER_SOURCE_AC, 566ce81151cSLikun Gao POWER_SOURCE_DC, 567ce81151cSLikun Gao POWER_SOURCE_COUNT, 568ce81151cSLikun Gao } POWER_SOURCE_e; 569ce81151cSLikun Gao 570ce81151cSLikun Gao typedef enum { 571ce81151cSLikun Gao MEM_VENDOR_SAMSUNG, 572ce81151cSLikun Gao MEM_VENDOR_INFINEON, 573ce81151cSLikun Gao MEM_VENDOR_ELPIDA, 574ce81151cSLikun Gao MEM_VENDOR_ETRON, 575ce81151cSLikun Gao MEM_VENDOR_NANYA, 576ce81151cSLikun Gao MEM_VENDOR_HYNIX, 577ce81151cSLikun Gao MEM_VENDOR_MOSEL, 578ce81151cSLikun Gao MEM_VENDOR_WINBOND, 579ce81151cSLikun Gao MEM_VENDOR_ESMT, 580ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER0, 581ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER1, 582ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER2, 583ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER3, 584ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER4, 585ce81151cSLikun Gao MEM_VENDOR_PLACEHOLDER5, 586ce81151cSLikun Gao MEM_VENDOR_MICRON, 587ce81151cSLikun Gao MEM_VENDOR_COUNT, 588ce81151cSLikun Gao } MEM_VENDOR_e; 589ce81151cSLikun Gao 590ce81151cSLikun Gao typedef enum { 591ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_CTL_ZONE0, 592ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_CTL_ZONE1, 593ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_CTL_ZONE2, 594ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_CTL_ZONE3, 595ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_CTL_ZONE4, 596ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0, 597ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0, 598ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1, 599ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1, 600ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2, 601ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2, 602ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3, 603ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3, 604ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4, 605ce81151cSLikun Gao PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4, 606ce81151cSLikun Gao PP_GRTAVFS_HW_ZONE0_VF, 607ce81151cSLikun Gao PP_GRTAVFS_HW_ZONE1_VF1, 608ce81151cSLikun Gao PP_GRTAVFS_HW_ZONE2_VF2, 609ce81151cSLikun Gao PP_GRTAVFS_HW_ZONE3_VF3, 610ce81151cSLikun Gao PP_GRTAVFS_HW_VOLTAGE_GB, 611ce81151cSLikun Gao PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0, 612ce81151cSLikun Gao PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1, 613ce81151cSLikun Gao PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2, 614ce81151cSLikun Gao PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3, 615ce81151cSLikun Gao PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4, 616ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_0, 617ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_1, 618ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_2, 619ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_3, 620ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_4, 621ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_5, 622ce81151cSLikun Gao PP_GRTAVFS_HW_RESERVED_6, 623ce81151cSLikun Gao PP_GRTAVFS_HW_FUSE_COUNT, 624ce81151cSLikun Gao } PP_GRTAVFS_HW_FUSE_e; 625ce81151cSLikun Gao 626ce81151cSLikun Gao typedef enum { 627ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0, 628ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0, 629ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0, 630ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0, 631ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0, 632ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0, 633ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0, 634ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0, 635ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0, 636ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1, 637ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2, 638ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3, 639ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4, 640ce81151cSLikun Gao PP_GRTAVFS_FW_COMMON_FUSE_COUNT, 641ce81151cSLikun Gao } PP_GRTAVFS_FW_COMMON_FUSE_e; 642ce81151cSLikun Gao 643ce81151cSLikun Gao typedef enum { 644ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1, 645ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0, 646ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1, 647ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2, 648ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3, 649ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4, 650ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1, 651ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0, 652ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1, 653ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2, 654ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3, 655ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4, 656ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY, 657ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY, 658ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0, 659ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1, 660ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2, 661ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3, 662ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4, 663ce81151cSLikun Gao PP_GRTAVFS_FW_SEP_FUSE_COUNT, 664ce81151cSLikun Gao } PP_GRTAVFS_FW_SEP_FUSE_e; 665ce81151cSLikun Gao 666ce81151cSLikun Gao #define PP_NUM_RTAVFS_PWL_ZONES 5 667ce81151cSLikun Gao 668ce81151cSLikun Gao 669ce81151cSLikun Gao 670ce81151cSLikun Gao // VBIOS or PPLIB configures telemetry slope and offset. Only slope expected to be set for SVI3 671ce81151cSLikun Gao // Slope Q1.7, Offset Q1.2 672ce81151cSLikun Gao typedef struct { 673ce81151cSLikun Gao int8_t Offset; // in Amps 674ce81151cSLikun Gao uint8_t Padding; 675ce81151cSLikun Gao uint16_t MaxCurrent; // in Amps 676ce81151cSLikun Gao } SviTelemetryScale_t; 677ce81151cSLikun Gao 678ce81151cSLikun Gao #define PP_NUM_OD_VF_CURVE_POINTS PP_NUM_RTAVFS_PWL_ZONES + 1 679ce81151cSLikun Gao 6807e5632cdSKenneth Feng typedef enum { 6817e5632cdSKenneth Feng FAN_MODE_AUTO = 0, 6827e5632cdSKenneth Feng FAN_MODE_MANUAL_LINEAR, 6837e5632cdSKenneth Feng } FanMode_e; 684ce81151cSLikun Gao 685ce81151cSLikun Gao typedef struct { 686ce81151cSLikun Gao uint32_t FeatureCtrlMask; 687ce81151cSLikun Gao 688ce81151cSLikun Gao //Voltage control 689ce81151cSLikun Gao int16_t VoltageOffsetPerZoneBoundary[PP_NUM_OD_VF_CURVE_POINTS]; 6907e5632cdSKenneth Feng uint16_t VddGfxVmax; // in mV 6917e5632cdSKenneth Feng 6927e5632cdSKenneth Feng uint8_t IdlePwrSavingFeaturesCtrl; 6937e5632cdSKenneth Feng uint8_t RuntimePwrSavingFeaturesCtrl; 694ce81151cSLikun Gao 695ce81151cSLikun Gao //Frequency changes 6961c65e548SEvan Quan int16_t GfxclkFmin; // MHz 6971c65e548SEvan Quan int16_t GfxclkFmax; // MHz 698ce81151cSLikun Gao uint16_t UclkFmin; // MHz 699ce81151cSLikun Gao uint16_t UclkFmax; // MHz 700ce81151cSLikun Gao 701ce81151cSLikun Gao //PPT 702ce81151cSLikun Gao int16_t Ppt; // % 7037e5632cdSKenneth Feng int16_t Tdc; 704ce81151cSLikun Gao 705ce81151cSLikun Gao //Fan control 706ce81151cSLikun Gao uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS]; 707ce81151cSLikun Gao uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS]; 708ce81151cSLikun Gao uint16_t FanMinimumPwm; 7091c65e548SEvan Quan uint16_t AcousticTargetRpmThreshold; 7101c65e548SEvan Quan uint16_t AcousticLimitRpmThreshold; 711ce81151cSLikun Gao uint16_t FanTargetTemperature; // Degree Celcius 712ce81151cSLikun Gao uint8_t FanZeroRpmEnable; 713ce81151cSLikun Gao uint8_t FanZeroRpmStopTemp; 714ce81151cSLikun Gao uint8_t FanMode; 7151c65e548SEvan Quan uint8_t MaxOpTemp; 716ce81151cSLikun Gao 717ce81151cSLikun Gao uint32_t Spare[13]; 718ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround 719ce81151cSLikun Gao } OverDriveTable_t; 720ce81151cSLikun Gao 721ce81151cSLikun Gao typedef struct { 722ce81151cSLikun Gao OverDriveTable_t OverDriveTable; 723ce81151cSLikun Gao 724ce81151cSLikun Gao } OverDriveTableExternal_t; 725ce81151cSLikun Gao 726ce81151cSLikun Gao typedef struct { 727ce81151cSLikun Gao uint32_t FeatureCtrlMask; 728ce81151cSLikun Gao 729ce81151cSLikun Gao int16_t VoltageOffsetPerZoneBoundary; 7307e5632cdSKenneth Feng uint16_t VddGfxVmax; // in mV 731ce81151cSLikun Gao 7327e5632cdSKenneth Feng uint8_t IdlePwrSavingFeaturesCtrl; 7337e5632cdSKenneth Feng uint8_t RuntimePwrSavingFeaturesCtrl; 7347e5632cdSKenneth Feng 7357e5632cdSKenneth Feng int16_t GfxclkFmin; // MHz 7367e5632cdSKenneth Feng int16_t GfxclkFmax; // MHz 737ce81151cSLikun Gao uint16_t UclkFmin; // MHz 738ce81151cSLikun Gao uint16_t UclkFmax; // MHz 739ce81151cSLikun Gao 740ce81151cSLikun Gao //PPT 741ce81151cSLikun Gao int16_t Ppt; // % 7427e5632cdSKenneth Feng int16_t Tdc; 743ce81151cSLikun Gao 744ce81151cSLikun Gao uint8_t FanLinearPwmPoints; 745ce81151cSLikun Gao uint8_t FanLinearTempPoints; 746ce81151cSLikun Gao uint16_t FanMinimumPwm; 7471c65e548SEvan Quan uint16_t AcousticTargetRpmThreshold; 7481c65e548SEvan Quan uint16_t AcousticLimitRpmThreshold; 749ce81151cSLikun Gao uint16_t FanTargetTemperature; // Degree Celcius 750ce81151cSLikun Gao uint8_t FanZeroRpmEnable; 751ce81151cSLikun Gao uint8_t FanZeroRpmStopTemp; 752ce81151cSLikun Gao uint8_t FanMode; 7531c65e548SEvan Quan uint8_t MaxOpTemp; 754ce81151cSLikun Gao 755ce81151cSLikun Gao uint32_t Spare[13]; 756ce81151cSLikun Gao 757ce81151cSLikun Gao } OverDriveLimits_t; 758ce81151cSLikun Gao 759ce81151cSLikun Gao 760ce81151cSLikun Gao typedef enum { 761ce81151cSLikun Gao BOARD_GPIO_SMUIO_0, 762ce81151cSLikun Gao BOARD_GPIO_SMUIO_1, 763ce81151cSLikun Gao BOARD_GPIO_SMUIO_2, 764ce81151cSLikun Gao BOARD_GPIO_SMUIO_3, 765ce81151cSLikun Gao BOARD_GPIO_SMUIO_4, 766ce81151cSLikun Gao BOARD_GPIO_SMUIO_5, 767ce81151cSLikun Gao BOARD_GPIO_SMUIO_6, 768ce81151cSLikun Gao BOARD_GPIO_SMUIO_7, 769ce81151cSLikun Gao BOARD_GPIO_SMUIO_8, 770ce81151cSLikun Gao BOARD_GPIO_SMUIO_9, 771ce81151cSLikun Gao BOARD_GPIO_SMUIO_10, 772ce81151cSLikun Gao BOARD_GPIO_SMUIO_11, 773ce81151cSLikun Gao BOARD_GPIO_SMUIO_12, 774ce81151cSLikun Gao BOARD_GPIO_SMUIO_13, 775ce81151cSLikun Gao BOARD_GPIO_SMUIO_14, 776ce81151cSLikun Gao BOARD_GPIO_SMUIO_15, 777ce81151cSLikun Gao BOARD_GPIO_SMUIO_16, 778ce81151cSLikun Gao BOARD_GPIO_SMUIO_17, 779ce81151cSLikun Gao BOARD_GPIO_SMUIO_18, 780ce81151cSLikun Gao BOARD_GPIO_SMUIO_19, 781ce81151cSLikun Gao BOARD_GPIO_SMUIO_20, 782ce81151cSLikun Gao BOARD_GPIO_SMUIO_21, 783ce81151cSLikun Gao BOARD_GPIO_SMUIO_22, 784ce81151cSLikun Gao BOARD_GPIO_SMUIO_23, 785ce81151cSLikun Gao BOARD_GPIO_SMUIO_24, 786ce81151cSLikun Gao BOARD_GPIO_SMUIO_25, 787ce81151cSLikun Gao BOARD_GPIO_SMUIO_26, 788ce81151cSLikun Gao BOARD_GPIO_SMUIO_27, 789ce81151cSLikun Gao BOARD_GPIO_SMUIO_28, 790ce81151cSLikun Gao BOARD_GPIO_SMUIO_29, 791ce81151cSLikun Gao BOARD_GPIO_SMUIO_30, 792ce81151cSLikun Gao BOARD_GPIO_SMUIO_31, 793ce81151cSLikun Gao MAX_BOARD_GPIO_SMUIO_NUM, 794ce81151cSLikun Gao BOARD_GPIO_DC_GEN_A, 795ce81151cSLikun Gao BOARD_GPIO_DC_GEN_B, 796ce81151cSLikun Gao BOARD_GPIO_DC_GEN_C, 797ce81151cSLikun Gao BOARD_GPIO_DC_GEN_D, 798ce81151cSLikun Gao BOARD_GPIO_DC_GEN_E, 799ce81151cSLikun Gao BOARD_GPIO_DC_GEN_F, 800ce81151cSLikun Gao BOARD_GPIO_DC_GEN_G, 801ce81151cSLikun Gao BOARD_GPIO_DC_GENLK_CLK, 802ce81151cSLikun Gao BOARD_GPIO_DC_GENLK_VSYNC, 803ce81151cSLikun Gao BOARD_GPIO_DC_SWAPLOCK_A, 804ce81151cSLikun Gao BOARD_GPIO_DC_SWAPLOCK_B, 805ce81151cSLikun Gao } BOARD_GPIO_TYPE_e; 806ce81151cSLikun Gao 807ce81151cSLikun Gao #define INVALID_BOARD_GPIO 0xFF 808ce81151cSLikun Gao 809ce81151cSLikun Gao 810ce81151cSLikun Gao typedef struct { 811ce81151cSLikun Gao //PLL 0 812ce81151cSLikun Gao uint16_t InitGfxclk_bypass; 813ce81151cSLikun Gao uint16_t InitSocclk; 814ce81151cSLikun Gao uint16_t InitMp0clk; 815ce81151cSLikun Gao uint16_t InitMpioclk; 816ce81151cSLikun Gao uint16_t InitSmnclk; 817ce81151cSLikun Gao uint16_t InitUcpclk; 818ce81151cSLikun Gao uint16_t InitCsrclk; 819ce81151cSLikun Gao //PLL 1 820ce81151cSLikun Gao 821ce81151cSLikun Gao uint16_t InitDprefclk; 822ce81151cSLikun Gao uint16_t InitDcfclk; 823ce81151cSLikun Gao uint16_t InitDtbclk; 824ce81151cSLikun Gao //PLL 2 825ce81151cSLikun Gao uint16_t InitDclk; //assume same DCLK/VCLK for both instances 826ce81151cSLikun Gao uint16_t InitVclk; 827ce81151cSLikun Gao // PLL 3 828ce81151cSLikun Gao uint16_t InitUsbdfsclk; 829ce81151cSLikun Gao uint16_t InitMp1clk; 830ce81151cSLikun Gao uint16_t InitLclk; 831ce81151cSLikun Gao uint16_t InitBaco400clk_bypass; 832ce81151cSLikun Gao uint16_t InitBaco1200clk_bypass; 833ce81151cSLikun Gao uint16_t InitBaco700clk_bypass; 834ce81151cSLikun Gao // PLL 4 835ce81151cSLikun Gao uint16_t InitFclk; 836ce81151cSLikun Gao // PLL 5 837ce81151cSLikun Gao uint16_t InitGfxclk_clkb; 838ce81151cSLikun Gao 839ce81151cSLikun Gao //PLL 6 840ce81151cSLikun Gao uint8_t InitUclkDPMState; // =0,1,2,3, frequency from FreqTableUclk 841ce81151cSLikun Gao 842ce81151cSLikun Gao uint8_t Padding[3]; 843ce81151cSLikun Gao 844ce81151cSLikun Gao uint32_t InitVcoFreqPll0; 845ce81151cSLikun Gao uint32_t InitVcoFreqPll1; 846ce81151cSLikun Gao uint32_t InitVcoFreqPll2; 847ce81151cSLikun Gao uint32_t InitVcoFreqPll3; 848ce81151cSLikun Gao uint32_t InitVcoFreqPll4; 849ce81151cSLikun Gao uint32_t InitVcoFreqPll5; 850ce81151cSLikun Gao uint32_t InitVcoFreqPll6; 851ce81151cSLikun Gao 852ce81151cSLikun Gao //encoding will change depending on SVI2/SVI3 853ce81151cSLikun Gao uint16_t InitGfx; // In mV(Q2) , should be 0? 854ce81151cSLikun Gao uint16_t InitSoc; // In mV(Q2) 855ce81151cSLikun Gao uint16_t InitU; // In Mv(Q2) 856ce81151cSLikun Gao 857ce81151cSLikun Gao uint16_t Padding2; 858ce81151cSLikun Gao 859ce81151cSLikun Gao uint32_t Spare[8]; 860ce81151cSLikun Gao 861ce81151cSLikun Gao } BootValues_t; 862ce81151cSLikun Gao 863ce81151cSLikun Gao 864ce81151cSLikun Gao typedef struct { 865ce81151cSLikun Gao uint16_t Power[PPT_THROTTLER_COUNT][POWER_SOURCE_COUNT]; // Watts 866ce81151cSLikun Gao uint16_t Tdc[TDC_THROTTLER_COUNT]; // Amps 867ce81151cSLikun Gao 868ce81151cSLikun Gao uint16_t Temperature[TEMP_COUNT]; // Celsius 869ce81151cSLikun Gao 870ce81151cSLikun Gao uint8_t PwmLimitMin; 871ce81151cSLikun Gao uint8_t PwmLimitMax; 872ce81151cSLikun Gao uint8_t FanTargetTemperature; 873ce81151cSLikun Gao uint8_t Spare1[1]; 874ce81151cSLikun Gao 875ce81151cSLikun Gao uint16_t AcousticTargetRpmThresholdMin; 876ce81151cSLikun Gao uint16_t AcousticTargetRpmThresholdMax; 877ce81151cSLikun Gao 878ce81151cSLikun Gao uint16_t AcousticLimitRpmThresholdMin; 879ce81151cSLikun Gao uint16_t AcousticLimitRpmThresholdMax; 880ce81151cSLikun Gao 881ce81151cSLikun Gao uint16_t PccLimitMin; 882ce81151cSLikun Gao uint16_t PccLimitMax; 883ce81151cSLikun Gao 884ce81151cSLikun Gao uint16_t FanStopTempMin; 885ce81151cSLikun Gao uint16_t FanStopTempMax; 886ce81151cSLikun Gao uint16_t FanStartTempMin; 887ce81151cSLikun Gao uint16_t FanStartTempMax; 888ce81151cSLikun Gao 8897e5632cdSKenneth Feng uint16_t PowerMinPpt0[POWER_SOURCE_COUNT]; 8907e5632cdSKenneth Feng uint32_t Spare[11]; 891ce81151cSLikun Gao 892ce81151cSLikun Gao } MsgLimits_t; 893ce81151cSLikun Gao 894ce81151cSLikun Gao typedef struct { 895ce81151cSLikun Gao uint16_t BaseClockAc; 896ce81151cSLikun Gao uint16_t GameClockAc; 897ce81151cSLikun Gao uint16_t BoostClockAc; 898ce81151cSLikun Gao uint16_t BaseClockDc; 899ce81151cSLikun Gao uint16_t GameClockDc; 900ce81151cSLikun Gao uint16_t BoostClockDc; 901ce81151cSLikun Gao 902ce81151cSLikun Gao uint32_t Reserved[4]; 903ce81151cSLikun Gao } DriverReportedClocks_t; 904ce81151cSLikun Gao 905ce81151cSLikun Gao typedef struct { 906ce81151cSLikun Gao uint8_t DcBtcEnabled; 907ce81151cSLikun Gao uint8_t Padding[3]; 908ce81151cSLikun Gao 909ce81151cSLikun Gao uint16_t DcTol; // mV Q2 910ce81151cSLikun Gao uint16_t DcBtcGb; // mV Q2 911ce81151cSLikun Gao 912ce81151cSLikun Gao uint16_t DcBtcMin; // mV Q2 913ce81151cSLikun Gao uint16_t DcBtcMax; // mV Q2 914ce81151cSLikun Gao 915ce81151cSLikun Gao LinearInt_t DcBtcGbScalar; 916ce81151cSLikun Gao 917ce81151cSLikun Gao } AvfsDcBtcParams_t; 918ce81151cSLikun Gao 919ce81151cSLikun Gao typedef struct { 920ce81151cSLikun Gao uint16_t AvfsTemp[AVFS_TEMP_COUNT]; //in degrees C 921ce81151cSLikun Gao uint16_t VftFMin; // in MHz 922ce81151cSLikun Gao uint16_t VInversion; // in mV Q2 923ce81151cSLikun Gao QuadraticInt_t qVft[AVFS_TEMP_COUNT]; 924ce81151cSLikun Gao QuadraticInt_t qAvfsGb; 925ce81151cSLikun Gao QuadraticInt_t qAvfsGb2; 926ce81151cSLikun Gao } AvfsFuseOverride_t; 927ce81151cSLikun Gao 928ce81151cSLikun Gao typedef struct { 929ce81151cSLikun Gao // SECTION: Version 930ce81151cSLikun Gao 931ce81151cSLikun Gao uint32_t Version; // should be unique to each SKU(i.e if any value changes in below structure then this value must be different) 932ce81151cSLikun Gao 933ce81151cSLikun Gao // SECTION: Feature Control 934ce81151cSLikun Gao uint32_t FeaturesToRun[NUM_FEATURES / 32]; // Features that PMFW will attempt to enable. Use FEATURE_*_BIT as mapping 935ce81151cSLikun Gao 936ce81151cSLikun Gao // SECTION: Miscellaneous Configuration 937ce81151cSLikun Gao uint8_t TotalPowerConfig; // Determines how PMFW calculates the power. Use defines from PwrConfig_e 938ce81151cSLikun Gao uint8_t CustomerVariant; //To specify if this PPTable is intended for a particular customer. Use defines from CUSTOMER_VARIANT_e 939ce81151cSLikun Gao uint8_t MemoryTemperatureTypeMask; // Bit mapping indicating which methods of memory temperature reading are enabled. Use defines from MEM_TEMP_*BIT 940ce81151cSLikun Gao uint8_t SmartShiftVersion; // Determine what SmartShift feature version is supported Use defines from SMARTSHIFT_VERSION_e 941ce81151cSLikun Gao 942ce81151cSLikun Gao // SECTION: Infrastructure Limits 943ce81151cSLikun Gao uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in AC mode. Multiple limits supported 944ce81151cSLikun Gao uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in DC mode. Multiple limits supported 945ce81151cSLikun Gao 946ce81151cSLikun Gao uint16_t SocketPowerLimitSmartShift2; // In Watts. Power limit used SmartShift 947ce81151cSLikun Gao 948ce81151cSLikun Gao //if set to 1, SocketPowerLimitAc and SocketPowerLimitDc will be interpreted as legacy programs(i.e absolute power). If 0, all except index 0 will be scalars 949ce81151cSLikun Gao //relative index 0 950ce81151cSLikun Gao uint8_t EnableLegacyPptLimit; 951ce81151cSLikun Gao uint8_t UseInputTelemetry; //applicable to SVI3 only and only to be set if VRs support 952ce81151cSLikun Gao uint8_t SmartShiftMinReportedPptinDcs; //minimum possible active power consumption for this SKU. Used for SmartShift power reporting 953ce81151cSLikun Gao 954ce81151cSLikun Gao uint8_t PaddingPpt[1]; 955ce81151cSLikun Gao 956ce81151cSLikun Gao uint16_t VrTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with VR regulator maximum temperature 957ce81151cSLikun Gao 958ce81151cSLikun Gao uint16_t PlatformTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with platform maximum temperature per VR current rail 959ce81151cSLikun Gao 960ce81151cSLikun Gao uint16_t TemperatureLimit[TEMP_COUNT]; // In degrees Celsius. Temperature limit associated with each input 961ce81151cSLikun Gao 962ce81151cSLikun Gao uint16_t HwCtfTempLimit; // In degrees Celsius. Temperature above which HW will trigger CTF. Consumed by VBIOS only 963ce81151cSLikun Gao 964ce81151cSLikun Gao uint16_t PaddingInfra; 965ce81151cSLikun Gao 966ce81151cSLikun Gao // Per year normalized Vmax state failure rates (sum of the two domains divided by life time in years) 967ce81151cSLikun Gao uint32_t FitControllerFailureRateLimit; //in IEEE float 968ce81151cSLikun Gao //Expected GFX Duty Cycle at Vmax. 969ce81151cSLikun Gao uint32_t FitControllerGfxDutyCycle; // in IEEE float 970ce81151cSLikun Gao //Expected SOC Duty Cycle at Vmax. 971ce81151cSLikun Gao uint32_t FitControllerSocDutyCycle; // in IEEE float 972ce81151cSLikun Gao 973ce81151cSLikun Gao //This offset will be deducted from the controller output to before it goes through the SOC Vset limiter block. 974ce81151cSLikun Gao uint32_t FitControllerSocOffset; //in IEEE float 975ce81151cSLikun Gao 976ce81151cSLikun Gao uint32_t GfxApccPlusResidencyLimit; // Percentage value. Used by APCC+ controller to control PCC residency to some value 977ce81151cSLikun Gao 978ce81151cSLikun Gao // SECTION: Throttler settings 979ce81151cSLikun Gao uint32_t ThrottlerControlMask; // See THROTTLER_*_BIT for mapping 980ce81151cSLikun Gao 981ce81151cSLikun Gao // SECTION: FW DSTATE Settings 982ce81151cSLikun Gao uint32_t FwDStateMask; // See FW_DSTATE_*_BIT for mapping 983ce81151cSLikun Gao 984ce81151cSLikun Gao // SECTION: Voltage Control Parameters 985ce81151cSLikun Gao uint16_t UlvVoltageOffset[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2). ULV offset used in either GFX_ULV or SOC_ULV(part of FW_DSTATE) 986ce81151cSLikun Gao 987ce81151cSLikun Gao uint16_t UlvVoltageOffsetU; // In mV(Q2). ULV offset used in either U_ULV(part of FW_DSTATE) 988ce81151cSLikun Gao uint16_t DeepUlvVoltageOffsetSoc; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC as part of FW_DSTATE 989ce81151cSLikun Gao 990ce81151cSLikun Gao // Voltage Limits 991ce81151cSLikun Gao uint16_t DefaultMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage without FIT controller enabled 992ce81151cSLikun Gao uint16_t BoostMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage with FIT controller enabled 993ce81151cSLikun Gao 994ce81151cSLikun Gao //Vmin Optimizations 995ce81151cSLikun Gao int16_t VminTempHystersis[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature hysteresis for switching between low/high temperature values for Vmin 996ce81151cSLikun Gao int16_t VminTempThreshold[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature threshold for switching between low/high temperature values for Vmin 997ce81151cSLikun Gao uint16_t Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at hot. 998ce81151cSLikun Gao uint16_t Vmin_Cold_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at cold. 999ce81151cSLikun Gao uint16_t Vmin_Hot_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at hot. 1000ce81151cSLikun Gao uint16_t Vmin_Cold_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at cold. 1001ce81151cSLikun Gao uint16_t Vmin_Aging_Offset[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Worst-case aging margin 100225dfc8faSEvan Quan uint16_t Spare_Vmin_Plat_Offset_Hot[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Hot 100325dfc8faSEvan Quan uint16_t Spare_Vmin_Plat_Offset_Cold[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Cold 1004ce81151cSLikun Gao 1005ce81151cSLikun Gao //This is a fixed/minimum VMIN aging degradation offset which is applied at T0. This reflects the minimum amount of aging already accounted for. 1006ce81151cSLikun Gao uint16_t VcBtcFixedVminAgingOffset[PMFW_VOLT_PLANE_COUNT]; 1007ce81151cSLikun Gao //Linear offset or GB term to account for mis-correlation between PSM and Vmin shift trends across parts. 1008ce81151cSLikun Gao uint16_t VcBtcVmin2PsmDegrationGb[PMFW_VOLT_PLANE_COUNT]; 1009ce81151cSLikun Gao //Scalar coefficient of the PSM aging degradation function 1010ce81151cSLikun Gao uint32_t VcBtcPsmA[PMFW_VOLT_PLANE_COUNT]; // A_PSM 1011ce81151cSLikun Gao //Exponential coefficient of the PSM aging degradation function 1012ce81151cSLikun Gao uint32_t VcBtcPsmB[PMFW_VOLT_PLANE_COUNT]; // B_PSM 1013ce81151cSLikun Gao //Scalar coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 1014ce81151cSLikun Gao uint32_t VcBtcVminA[PMFW_VOLT_PLANE_COUNT]; // A_VMIN 1015ce81151cSLikun Gao //Exponential coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 1016ce81151cSLikun Gao uint32_t VcBtcVminB[PMFW_VOLT_PLANE_COUNT]; // B_VMIN 1017ce81151cSLikun Gao 1018ce81151cSLikun Gao uint8_t PerPartVminEnabled[PMFW_VOLT_PLANE_COUNT]; 1019ce81151cSLikun Gao uint8_t VcBtcEnabled[PMFW_VOLT_PLANE_COUNT]; 1020ce81151cSLikun Gao 1021ce81151cSLikun Gao uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 1022ce81151cSLikun Gao uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 1023ce81151cSLikun Gao 10241c65e548SEvan Quan QuadraticInt_t Vmin_droop; 10251c65e548SEvan Quan uint32_t SpareVmin[9]; 1026ce81151cSLikun Gao 1027ce81151cSLikun Gao 1028ce81151cSLikun Gao //SECTION: DPM Configuration 1 1029ce81151cSLikun Gao DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 1030ce81151cSLikun Gao 1031ce81151cSLikun Gao uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1032ce81151cSLikun Gao uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1033ce81151cSLikun Gao uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1034ce81151cSLikun Gao uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1035ce81151cSLikun Gao uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1036ce81151cSLikun Gao uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1037ce81151cSLikun Gao uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1038ce81151cSLikun Gao uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1039ce81151cSLikun Gao uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1040ce81151cSLikun Gao uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1041ce81151cSLikun Gao uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1042ce81151cSLikun Gao 1043ce81151cSLikun Gao uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1044ce81151cSLikun Gao 1045ce81151cSLikun Gao // SECTION: DPM Configuration 2 1046ce81151cSLikun Gao uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 1047ce81151cSLikun Gao uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 1048ce81151cSLikun Gao 1049ce81151cSLikun Gao uint8_t GfxclkSpare[2]; 1050ce81151cSLikun Gao uint16_t GfxclkFreqCap; 1051ce81151cSLikun Gao 1052ce81151cSLikun Gao //GFX Idle Power Settings 1053ce81151cSLikun Gao uint16_t GfxclkFgfxoffEntry; // in Mhz 1054ce81151cSLikun Gao uint16_t GfxclkFgfxoffExitImu; // in Mhz 1055ce81151cSLikun Gao uint16_t GfxclkFgfxoffExitRlc; // in Mhz 1056ce81151cSLikun Gao uint16_t GfxclkThrottleClock; //Used primarily in DCS 1057ce81151cSLikun Gao uint8_t EnableGfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages 1058ce81151cSLikun Gao uint8_t GfxIdlePadding; 1059ce81151cSLikun Gao 1060ce81151cSLikun Gao uint8_t SmsRepairWRCKClkDivEn; 1061ce81151cSLikun Gao uint8_t SmsRepairWRCKClkDivVal; 1062ce81151cSLikun Gao uint8_t GfxOffEntryEarlyMGCGEn; 1063ce81151cSLikun Gao uint8_t GfxOffEntryForceCGCGEn; 1064ce81151cSLikun Gao uint8_t GfxOffEntryForceCGCGDelayEn; 1065ce81151cSLikun Gao uint8_t GfxOffEntryForceCGCGDelayVal; // in microseconds 1066ce81151cSLikun Gao 1067ce81151cSLikun Gao uint16_t GfxclkFreqGfxUlv; // in MHz 1068ce81151cSLikun Gao uint8_t GfxIdlePadding2[2]; 1069ce81151cSLikun Gao 1070cbe07c98SEvan Quan uint32_t GfxOffEntryHysteresis; 1071cbe07c98SEvan Quan uint32_t GfxoffSpare[15]; 1072ce81151cSLikun Gao 1073ce81151cSLikun Gao // GFX GPO 10747e5632cdSKenneth Feng uint32_t DfllBtcMasterScalerM; 10757e5632cdSKenneth Feng int32_t DfllBtcMasterScalerB; 10767e5632cdSKenneth Feng uint32_t DfllBtcSlaveScalerM; 10777e5632cdSKenneth Feng int32_t DfllBtcSlaveScalerB; 10787e5632cdSKenneth Feng 10797e5632cdSKenneth Feng uint32_t DfllPccAsWaitCtrl; //GDFLL_AS_WAIT_CTRL_PCC register value to be passed to RLC msg 10807e5632cdSKenneth Feng uint32_t DfllPccAsStepCtrl; //GDFLL_AS_STEP_CTRL_PCC register value to be passed to RLC msg 10817e5632cdSKenneth Feng 10827e5632cdSKenneth Feng uint32_t DfllL2FrequencyBoostM; //Unitless (float) 10837e5632cdSKenneth Feng uint32_t DfllL2FrequencyBoostB; //In MHz (integer) 10847e5632cdSKenneth Feng uint32_t GfxGpoSpare[8]; 1085ce81151cSLikun Gao 1086ce81151cSLikun Gao // GFX DCS 1087ce81151cSLikun Gao 1088ce81151cSLikun Gao uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase 1089ce81151cSLikun Gao uint16_t PaddingDcs; 1090ce81151cSLikun Gao 1091ce81151cSLikun Gao uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase 1092ce81151cSLikun Gao uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. 1093ce81151cSLikun Gao 1094ce81151cSLikun Gao uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS. 1095ce81151cSLikun Gao 1096ce81151cSLikun Gao uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. 1097ce81151cSLikun Gao uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin. 1098ce81151cSLikun Gao 1099ce81151cSLikun Gao 1100ce81151cSLikun Gao uint32_t DcsSpare[16]; 1101ce81151cSLikun Gao 1102ce81151cSLikun Gao // UCLK section 1103ce81151cSLikun Gao uint8_t UseStrobeModeOptimizations; //Set to indicate that FW should use strobe mode optimizations 1104ce81151cSLikun Gao uint8_t PaddingMem[3]; 1105ce81151cSLikun Gao 1106ce81151cSLikun Gao uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 1107ce81151cSLikun Gao uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 1108ce81151cSLikun Gao 1109ce81151cSLikun Gao uint16_t MemVmempVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1110ce81151cSLikun Gao uint16_t MemVddioVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1111ce81151cSLikun Gao 1112ce81151cSLikun Gao //FCLK Section 1113ce81151cSLikun Gao 1114ce81151cSLikun Gao uint8_t FclkDpmUPstates[NUM_FCLK_DPM_LEVELS]; // U P-state ID associated with each FCLK DPM state. 1115ce81151cSLikun Gao uint16_t FclkDpmVddU[NUM_FCLK_DPM_LEVELS]; // mV(Q2) Vset U voltage associated with each FCLK DPM state. 1116ce81151cSLikun Gao uint16_t FclkDpmUSpeed[NUM_FCLK_DPM_LEVELS]; //U speed associated with each FCLK DPM state 1117ce81151cSLikun Gao uint16_t FclkDpmDisallowPstateFreq; //Frequency which FW will target when indicated that display config cannot support P-state. Set to 0 use FW calculated value 1118ce81151cSLikun Gao uint16_t PaddingFclk; 1119ce81151cSLikun Gao 1120ce81151cSLikun Gao // Link DPM Settings 1121ce81151cSLikun Gao uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 1122ce81151cSLikun Gao uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 1123ce81151cSLikun Gao uint16_t LclkFreq[NUM_LINK_LEVELS]; 1124ce81151cSLikun Gao 1125ce81151cSLikun Gao // SECTION: Fan Control 1126ce81151cSLikun Gao uint16_t FanStopTemp[TEMP_COUNT]; //Celsius 1127ce81151cSLikun Gao uint16_t FanStartTemp[TEMP_COUNT]; //Celsius 1128ce81151cSLikun Gao 1129ce81151cSLikun Gao uint16_t FanGain[TEMP_COUNT]; 1130ce81151cSLikun Gao uint16_t FanGainPadding; 1131ce81151cSLikun Gao 1132ce81151cSLikun Gao uint16_t FanPwmMin; 1133ce81151cSLikun Gao uint16_t AcousticTargetRpmThreshold; 1134ce81151cSLikun Gao uint16_t AcousticLimitRpmThreshold; 1135ce81151cSLikun Gao uint16_t FanMaximumRpm; 1136ce81151cSLikun Gao uint16_t MGpuAcousticLimitRpmThreshold; 1137ce81151cSLikun Gao uint16_t FanTargetGfxclk; 1138ce81151cSLikun Gao uint32_t TempInputSelectMask; 1139ce81151cSLikun Gao uint8_t FanZeroRpmEnable; 1140ce81151cSLikun Gao uint8_t FanTachEdgePerRev; 1141ce81151cSLikun Gao uint16_t FanTargetTemperature[TEMP_COUNT]; 1142ce81151cSLikun Gao 1143ce81151cSLikun Gao // The following are AFC override parameters. Leave at 0 to use FW defaults. 1144ce81151cSLikun Gao int16_t FuzzyFan_ErrorSetDelta; 1145ce81151cSLikun Gao int16_t FuzzyFan_ErrorRateSetDelta; 1146ce81151cSLikun Gao int16_t FuzzyFan_PwmSetDelta; 1147ce81151cSLikun Gao uint16_t FuzzyFan_Reserved; 1148ce81151cSLikun Gao 1149ce81151cSLikun Gao uint16_t FwCtfLimit[TEMP_COUNT]; 1150ce81151cSLikun Gao 1151ce81151cSLikun Gao uint16_t IntakeTempEnableRPM; 1152ce81151cSLikun Gao int16_t IntakeTempOffsetTemp; 1153ce81151cSLikun Gao uint16_t IntakeTempReleaseTemp; 1154ce81151cSLikun Gao uint16_t IntakeTempHighIntakeAcousticLimit; 1155ce81151cSLikun Gao uint16_t IntakeTempAcouticLimitReleaseRate; 1156ce81151cSLikun Gao 11577e5632cdSKenneth Feng int16_t FanAbnormalTempLimitOffset; 1158ce81151cSLikun Gao uint16_t FanStalledTriggerRpm; 11597e5632cdSKenneth Feng uint16_t FanAbnormalTriggerRpmCoeff; 11607e5632cdSKenneth Feng uint16_t FanAbnormalDetectionEnable; 1161ce81151cSLikun Gao 11627e5632cdSKenneth Feng uint8_t FanIntakeSensorSupport; 11637e5632cdSKenneth Feng uint8_t FanIntakePadding[3]; 11647e5632cdSKenneth Feng uint32_t FanSpare[13]; 1165ce81151cSLikun Gao 1166ce81151cSLikun Gao // SECTION: VDD_GFX AVFS 1167ce81151cSLikun Gao 1168ce81151cSLikun Gao uint8_t OverrideGfxAvfsFuses; 1169ce81151cSLikun Gao uint8_t GfxAvfsPadding[3]; 1170ce81151cSLikun Gao 1171ce81151cSLikun Gao uint32_t L2HwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; //see fusedoc for encoding 1172ce81151cSLikun Gao uint32_t SeHwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; 1173ce81151cSLikun Gao 1174ce81151cSLikun Gao uint32_t CommonRtAvfs[PP_GRTAVFS_FW_COMMON_FUSE_COUNT]; 1175ce81151cSLikun Gao 1176ce81151cSLikun Gao uint32_t L2FwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1177ce81151cSLikun Gao uint32_t SeFwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1178ce81151cSLikun Gao 1179ce81151cSLikun Gao uint32_t Droop_PWL_F[PP_NUM_RTAVFS_PWL_ZONES]; 1180ce81151cSLikun Gao uint32_t Droop_PWL_a[PP_NUM_RTAVFS_PWL_ZONES]; 1181ce81151cSLikun Gao uint32_t Droop_PWL_b[PP_NUM_RTAVFS_PWL_ZONES]; 1182ce81151cSLikun Gao uint32_t Droop_PWL_c[PP_NUM_RTAVFS_PWL_ZONES]; 1183ce81151cSLikun Gao 1184ce81151cSLikun Gao uint32_t Static_PWL_Offset[PP_NUM_RTAVFS_PWL_ZONES]; 1185ce81151cSLikun Gao 1186ce81151cSLikun Gao uint32_t dGbV_dT_vmin; 1187ce81151cSLikun Gao uint32_t dGbV_dT_vmax; 1188ce81151cSLikun Gao 1189ce81151cSLikun Gao //Unused: PMFW-9370 1190ce81151cSLikun Gao uint32_t V2F_vmin_range_low; 1191ce81151cSLikun Gao uint32_t V2F_vmin_range_high; 1192ce81151cSLikun Gao uint32_t V2F_vmax_range_low; 1193ce81151cSLikun Gao uint32_t V2F_vmax_range_high; 1194ce81151cSLikun Gao 1195ce81151cSLikun Gao AvfsDcBtcParams_t DcBtcGfxParams; 1196ce81151cSLikun Gao 1197ce81151cSLikun Gao uint32_t GfxAvfsSpare[32]; 1198ce81151cSLikun Gao 1199ce81151cSLikun Gao //SECTION: VDD_SOC AVFS 1200ce81151cSLikun Gao 1201ce81151cSLikun Gao uint8_t OverrideSocAvfsFuses; 1202ce81151cSLikun Gao uint8_t MinSocAvfsRevision; 1203ce81151cSLikun Gao uint8_t SocAvfsPadding[2]; 1204ce81151cSLikun Gao 1205ce81151cSLikun Gao AvfsFuseOverride_t SocAvfsFuseOverride[AVFS_D_COUNT]; 1206ce81151cSLikun Gao 1207ce81151cSLikun Gao DroopInt_t dBtcGbSoc[AVFS_D_COUNT]; // GHz->V BtcGb 1208ce81151cSLikun Gao 1209ce81151cSLikun Gao LinearInt_t qAgingGb[AVFS_D_COUNT]; // GHz->V 1210ce81151cSLikun Gao 1211ce81151cSLikun Gao QuadraticInt_t qStaticVoltageOffset[AVFS_D_COUNT]; // GHz->V 1212ce81151cSLikun Gao 1213ce81151cSLikun Gao AvfsDcBtcParams_t DcBtcSocParams[AVFS_D_COUNT]; 1214ce81151cSLikun Gao 1215ce81151cSLikun Gao uint32_t SocAvfsSpare[32]; 1216ce81151cSLikun Gao 1217ce81151cSLikun Gao //SECTION: Boot clock and voltage values 1218ce81151cSLikun Gao BootValues_t BootValues; 1219ce81151cSLikun Gao 1220ce81151cSLikun Gao //SECTION: Driver Reported Clocks 1221ce81151cSLikun Gao DriverReportedClocks_t DriverReportedClocks; 1222ce81151cSLikun Gao 1223ce81151cSLikun Gao //SECTION: Message Limits 1224ce81151cSLikun Gao MsgLimits_t MsgLimits; 1225ce81151cSLikun Gao 1226ce81151cSLikun Gao //SECTION: OverDrive Limits 1227ce81151cSLikun Gao OverDriveLimits_t OverDriveLimitsMin; 1228ce81151cSLikun Gao OverDriveLimits_t OverDriveLimitsBasicMax; 1229ce81151cSLikun Gao uint32_t reserved[22]; 1230ce81151cSLikun Gao 1231ce81151cSLikun Gao // SECTION: Advanced Options 1232ce81151cSLikun Gao uint32_t DebugOverrides; 1233ce81151cSLikun Gao 1234da1acbb1SEvan Quan // Section: Total Board Power idle vs active coefficients 1235da1acbb1SEvan Quan uint8_t TotalBoardPowerSupport; 1236da1acbb1SEvan Quan uint8_t TotalBoardPowerPadding[3]; 1237da1acbb1SEvan Quan 1238da1acbb1SEvan Quan int16_t TotalIdleBoardPowerM; 1239da1acbb1SEvan Quan int16_t TotalIdleBoardPowerB; 1240da1acbb1SEvan Quan int16_t TotalBoardPowerM; 1241da1acbb1SEvan Quan int16_t TotalBoardPowerB; 1242da1acbb1SEvan Quan 12437e5632cdSKenneth Feng //PMFW-11158 12447e5632cdSKenneth Feng QuadraticInt_t qFeffCoeffGameClock[POWER_SOURCE_COUNT]; 12457e5632cdSKenneth Feng QuadraticInt_t qFeffCoeffBaseClock[POWER_SOURCE_COUNT]; 12467e5632cdSKenneth Feng QuadraticInt_t qFeffCoeffBoostClock[POWER_SOURCE_COUNT]; 12477e5632cdSKenneth Feng 1248ce81151cSLikun Gao // SECTION: Sku Reserved 12497e5632cdSKenneth Feng uint32_t Spare[43]; 1250ce81151cSLikun Gao 1251ce81151cSLikun Gao // Padding for MMHUB - do not modify this 1252ce81151cSLikun Gao uint32_t MmHubPadding[8]; 1253ce81151cSLikun Gao 1254ce81151cSLikun Gao } SkuTable_t; 1255ce81151cSLikun Gao 1256ce81151cSLikun Gao typedef struct { 1257ce81151cSLikun Gao // SECTION: Version 1258ce81151cSLikun Gao uint32_t Version; //should be unique to each board type 1259ce81151cSLikun Gao 1260ce81151cSLikun Gao 1261ce81151cSLikun Gao // SECTION: I2C Control 1262ce81151cSLikun Gao I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 1263ce81151cSLikun Gao 1264ce81151cSLikun Gao // SECTION: SVI2 Board Parameters 1265ce81151cSLikun Gao uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 1266ce81151cSLikun Gao uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 1267ce81151cSLikun Gao uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 1268ce81151cSLikun Gao uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 1269ce81151cSLikun Gao 1270ce81151cSLikun Gao uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1271ce81151cSLikun Gao uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1272ce81151cSLikun Gao uint8_t VmempUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1273ce81151cSLikun Gao uint8_t VddioUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1274ce81151cSLikun Gao 1275ce81151cSLikun Gao //SECTION SVI3 Board Parameters 1276ce81151cSLikun Gao uint8_t SlaveAddrMapping[SVI_PLANE_COUNT]; 1277ce81151cSLikun Gao uint8_t VrPsiSupport[SVI_PLANE_COUNT]; 1278ce81151cSLikun Gao 1279ce81151cSLikun Gao uint8_t PaddingPsi[SVI_PLANE_COUNT]; 1280ce81151cSLikun Gao uint8_t EnablePsi6[SVI_PLANE_COUNT]; // only applicable in SVI3 1281ce81151cSLikun Gao 1282ce81151cSLikun Gao // SECTION: Voltage Regulator Settings 1283ce81151cSLikun Gao SviTelemetryScale_t SviTelemetryScale[SVI_PLANE_COUNT]; 1284ce81151cSLikun Gao uint32_t VoltageTelemetryRatio[SVI_PLANE_COUNT]; // This is used for VDDIO Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 1285ce81151cSLikun Gao 1286ce81151cSLikun Gao uint8_t DownSlewRateVr[SVI_PLANE_COUNT]; 1287ce81151cSLikun Gao 1288ce81151cSLikun Gao // SECTION: GPIO Settings 1289ce81151cSLikun Gao 1290ce81151cSLikun Gao uint8_t LedOffGpio; 1291ce81151cSLikun Gao uint8_t FanOffGpio; 1292ce81151cSLikun Gao uint8_t GfxVrPowerStageOffGpio; 1293ce81151cSLikun Gao 1294ce81151cSLikun Gao uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 1295ce81151cSLikun Gao uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 1296ce81151cSLikun Gao uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 1297ce81151cSLikun Gao uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 1298ce81151cSLikun Gao 1299ce81151cSLikun Gao uint8_t GthrGpio; // GPIO pin configured for GTHR Event 1300ce81151cSLikun Gao uint8_t GthrPolarity; // replace GPIO polarity for GTHR 1301ce81151cSLikun Gao 1302ce81151cSLikun Gao // LED Display Settings 1303ce81151cSLikun Gao uint8_t LedPin0; // GPIO number for LedPin[0] 1304ce81151cSLikun Gao uint8_t LedPin1; // GPIO number for LedPin[1] 1305ce81151cSLikun Gao uint8_t LedPin2; // GPIO number for LedPin[2] 1306ce81151cSLikun Gao uint8_t LedEnableMask; 1307ce81151cSLikun Gao 1308ce81151cSLikun Gao uint8_t LedPcie; // GPIO number for PCIE results 1309ce81151cSLikun Gao uint8_t LedError; // GPIO number for Error Cases 1310ce81151cSLikun Gao 1311ce81151cSLikun Gao // SECTION: Clock Spread Spectrum 1312ce81151cSLikun Gao 1313ce81151cSLikun Gao // UCLK Spread Spectrum 1314da1acbb1SEvan Quan uint8_t UclkTrainingModeSpreadPercent; 1315da1acbb1SEvan Quan uint8_t UclkSpreadPadding; 1316ce81151cSLikun Gao uint16_t UclkSpreadFreq; // kHz 1317ce81151cSLikun Gao 1318ce81151cSLikun Gao // UCLK Spread Spectrum 1319ce81151cSLikun Gao uint8_t UclkSpreadPercent[MEM_VENDOR_COUNT]; 1320ce81151cSLikun Gao 1321ce81151cSLikun Gao // FCLK Spread Spectrum 1322ce81151cSLikun Gao uint8_t FclkSpreadPadding; 1323ce81151cSLikun Gao uint8_t FclkSpreadPercent; // Q4.4 1324ce81151cSLikun Gao uint16_t FclkSpreadFreq; // kHz 1325ce81151cSLikun Gao 1326ce81151cSLikun Gao // Section: Memory Config 1327ce81151cSLikun Gao uint8_t DramWidth; // Width of interface to the channel for each DRAM module. See DRAM_BIT_WIDTH_TYPE_e 1328da1acbb1SEvan Quan uint8_t PaddingMem1[7]; 1329ce81151cSLikun Gao 1330ce81151cSLikun Gao // SECTION: UMC feature flags 1331ce81151cSLikun Gao uint8_t HsrEnabled; 1332ce81151cSLikun Gao uint8_t VddqOffEnabled; 1333ce81151cSLikun Gao uint8_t PaddingUmcFlags[2]; 1334ce81151cSLikun Gao 1335ce81151cSLikun Gao uint32_t PostVoltageSetBacoDelay; // in microseconds. Amount of time FW will wait after power good is established or PSI0 command is issued 1336ce81151cSLikun Gao uint32_t BacoEntryDelay; // in milliseconds. Amount of time FW will wait to trigger BACO entry after receiving entry notification from OS 1337ce81151cSLikun Gao 13387e5632cdSKenneth Feng uint8_t FuseWritePowerMuxPresent; 13397e5632cdSKenneth Feng uint8_t FuseWritePadding[3]; 13407e5632cdSKenneth Feng 1341ce81151cSLikun Gao // SECTION: Board Reserved 13427e5632cdSKenneth Feng uint32_t BoardSpare[63]; 1343ce81151cSLikun Gao 1344ce81151cSLikun Gao // SECTION: Structure Padding 1345ce81151cSLikun Gao 1346ce81151cSLikun Gao // Padding for MMHUB - do not modify this 1347ce81151cSLikun Gao uint32_t MmHubPadding[8]; 1348ce81151cSLikun Gao } BoardTable_t; 1349ce81151cSLikun Gao 1350ce81151cSLikun Gao typedef struct { 1351ce81151cSLikun Gao SkuTable_t SkuTable; 1352ce81151cSLikun Gao BoardTable_t BoardTable; 1353ce81151cSLikun Gao } PPTable_t; 1354ce81151cSLikun Gao 1355ce81151cSLikun Gao typedef struct { 1356ce81151cSLikun Gao // Time constant parameters for clock averages in ms 1357ce81151cSLikun Gao uint16_t GfxclkAverageLpfTau; 1358ce81151cSLikun Gao uint16_t FclkAverageLpfTau; 1359ce81151cSLikun Gao uint16_t UclkAverageLpfTau; 1360ce81151cSLikun Gao uint16_t GfxActivityLpfTau; 1361ce81151cSLikun Gao uint16_t UclkActivityLpfTau; 1362ce81151cSLikun Gao uint16_t SocketPowerLpfTau; 1363ce81151cSLikun Gao uint16_t VcnClkAverageLpfTau; 1364ce81151cSLikun Gao uint16_t VcnUsageAverageLpfTau; 1365ce81151cSLikun Gao } DriverSmuConfig_t; 1366ce81151cSLikun Gao 1367ce81151cSLikun Gao typedef struct { 1368ce81151cSLikun Gao DriverSmuConfig_t DriverSmuConfig; 1369ce81151cSLikun Gao 1370ce81151cSLikun Gao uint32_t Spare[8]; 1371ce81151cSLikun Gao // Padding - ignore 1372ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1373ce81151cSLikun Gao } DriverSmuConfigExternal_t; 1374ce81151cSLikun Gao 1375ce81151cSLikun Gao 1376ce81151cSLikun Gao typedef struct { 1377ce81151cSLikun Gao 1378ce81151cSLikun Gao uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1379ce81151cSLikun Gao uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1380ce81151cSLikun Gao uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1381ce81151cSLikun Gao uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1382ce81151cSLikun Gao uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1383ce81151cSLikun Gao uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1384ce81151cSLikun Gao uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1385ce81151cSLikun Gao uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1386ce81151cSLikun Gao uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1387ce81151cSLikun Gao uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1388ce81151cSLikun Gao uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1389ce81151cSLikun Gao 1390ce81151cSLikun Gao uint16_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1391ce81151cSLikun Gao 1392ce81151cSLikun Gao uint16_t Padding; 1393ce81151cSLikun Gao 1394ce81151cSLikun Gao uint32_t Spare[32]; 1395ce81151cSLikun Gao 1396ce81151cSLikun Gao // Padding - ignore 1397ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1398ce81151cSLikun Gao 1399ce81151cSLikun Gao } DriverInfoTable_t; 1400ce81151cSLikun Gao 1401ce81151cSLikun Gao typedef struct { 1402ce81151cSLikun Gao uint32_t CurrClock[PPCLK_COUNT]; 1403ce81151cSLikun Gao 1404ce81151cSLikun Gao uint16_t AverageGfxclkFrequencyTarget; 1405ce81151cSLikun Gao uint16_t AverageGfxclkFrequencyPreDs; 1406ce81151cSLikun Gao uint16_t AverageGfxclkFrequencyPostDs; 1407ce81151cSLikun Gao uint16_t AverageFclkFrequencyPreDs; 1408ce81151cSLikun Gao uint16_t AverageFclkFrequencyPostDs; 1409ce81151cSLikun Gao uint16_t AverageMemclkFrequencyPreDs ; // this is scaled to actual memory clock 1410ce81151cSLikun Gao uint16_t AverageMemclkFrequencyPostDs ; // this is scaled to actual memory clock 1411ce81151cSLikun Gao uint16_t AverageVclk0Frequency ; 1412ce81151cSLikun Gao uint16_t AverageDclk0Frequency ; 1413ce81151cSLikun Gao uint16_t AverageVclk1Frequency ; 1414ce81151cSLikun Gao uint16_t AverageDclk1Frequency ; 141566f54992SEvan Quan uint16_t PCIeBusy; 141666f54992SEvan Quan uint16_t dGPU_W_MAX; 141766f54992SEvan Quan uint16_t padding; 141866f54992SEvan Quan 141966f54992SEvan Quan uint32_t MetricsCounter; 1420ce81151cSLikun Gao 1421ce81151cSLikun Gao uint16_t AvgVoltage[SVI_PLANE_COUNT]; 142266f54992SEvan Quan uint16_t AvgCurrent[SVI_PLANE_COUNT]; 1423ce81151cSLikun Gao 1424ce81151cSLikun Gao uint16_t AverageGfxActivity ; 1425ce81151cSLikun Gao uint16_t AverageUclkActivity ; 1426ce81151cSLikun Gao uint16_t Vcn0ActivityPercentage ; 1427ce81151cSLikun Gao uint16_t Vcn1ActivityPercentage ; 1428ce81151cSLikun Gao 1429ce81151cSLikun Gao uint32_t EnergyAccumulator; 1430ce81151cSLikun Gao uint16_t AverageSocketPower; 1431da1acbb1SEvan Quan uint16_t AverageTotalBoardPower; 1432da1acbb1SEvan Quan 1433ce81151cSLikun Gao uint16_t AvgTemperature[TEMP_COUNT]; 14347e5632cdSKenneth Feng uint16_t AvgTemperatureFanIntake; 1435ce81151cSLikun Gao 1436ce81151cSLikun Gao uint8_t PcieRate ; 1437ce81151cSLikun Gao uint8_t PcieWidth ; 1438ce81151cSLikun Gao 1439ce81151cSLikun Gao uint8_t AvgFanPwm; 1440ce81151cSLikun Gao uint8_t Padding[1]; 1441ce81151cSLikun Gao uint16_t AvgFanRpm; 1442ce81151cSLikun Gao 1443ce81151cSLikun Gao 1444ce81151cSLikun Gao uint8_t ThrottlingPercentage[THROTTLER_COUNT]; 1445ce81151cSLikun Gao 1446ce81151cSLikun Gao //metrics for D3hot entry/exit and driver ARM msgs 1447ce81151cSLikun Gao uint32_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; 1448ce81151cSLikun Gao uint32_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT]; 1449ce81151cSLikun Gao uint32_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT]; 1450ce81151cSLikun Gao 1451ce81151cSLikun Gao uint16_t ApuSTAPMSmartShiftLimit; 1452ce81151cSLikun Gao uint16_t ApuSTAPMLimit; 1453ce81151cSLikun Gao uint16_t AvgApuSocketPower; 1454ce81151cSLikun Gao 1455ce81151cSLikun Gao uint16_t AverageUclkActivity_MAX; 1456ce81151cSLikun Gao 1457ce81151cSLikun Gao uint32_t PublicSerialNumberLower; 1458ce81151cSLikun Gao uint32_t PublicSerialNumberUpper; 1459ce81151cSLikun Gao 1460ce81151cSLikun Gao } SmuMetrics_t; 1461ce81151cSLikun Gao 1462ce81151cSLikun Gao typedef struct { 1463ce81151cSLikun Gao SmuMetrics_t SmuMetrics; 1464ce81151cSLikun Gao uint32_t Spare[30]; 1465ce81151cSLikun Gao 1466ce81151cSLikun Gao // Padding - ignore 1467ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1468ce81151cSLikun Gao } SmuMetricsExternal_t; 1469ce81151cSLikun Gao 1470ce81151cSLikun Gao typedef struct { 1471ce81151cSLikun Gao uint8_t WmSetting; 1472ce81151cSLikun Gao uint8_t Flags; 1473ce81151cSLikun Gao uint8_t Padding[2]; 1474ce81151cSLikun Gao 1475ce81151cSLikun Gao } WatermarkRowGeneric_t; 1476ce81151cSLikun Gao 1477ce81151cSLikun Gao #define NUM_WM_RANGES 4 1478ce81151cSLikun Gao 1479ce81151cSLikun Gao typedef enum { 1480ce81151cSLikun Gao WATERMARKS_CLOCK_RANGE = 0, 1481ce81151cSLikun Gao WATERMARKS_DUMMY_PSTATE, 1482ce81151cSLikun Gao WATERMARKS_MALL, 1483ce81151cSLikun Gao WATERMARKS_COUNT, 1484ce81151cSLikun Gao } WATERMARKS_FLAGS_e; 1485ce81151cSLikun Gao 1486ce81151cSLikun Gao typedef struct { 1487ce81151cSLikun Gao // Watermarks 1488ce81151cSLikun Gao WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES]; 1489ce81151cSLikun Gao } Watermarks_t; 1490ce81151cSLikun Gao 1491ce81151cSLikun Gao typedef struct { 1492ce81151cSLikun Gao Watermarks_t Watermarks; 1493ce81151cSLikun Gao uint32_t Spare[16]; 1494ce81151cSLikun Gao 1495ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1496ce81151cSLikun Gao } WatermarksExternal_t; 1497ce81151cSLikun Gao 1498ce81151cSLikun Gao typedef struct { 1499ce81151cSLikun Gao uint16_t avgPsmCount[214]; 1500ce81151cSLikun Gao uint16_t minPsmCount[214]; 1501ce81151cSLikun Gao float avgPsmVoltage[214]; 1502ce81151cSLikun Gao float minPsmVoltage[214]; 1503ce81151cSLikun Gao } AvfsDebugTable_t; 1504ce81151cSLikun Gao 1505ce81151cSLikun Gao typedef struct { 1506ce81151cSLikun Gao AvfsDebugTable_t AvfsDebugTable; 1507ce81151cSLikun Gao 1508ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1509ce81151cSLikun Gao } AvfsDebugTableExternal_t; 1510ce81151cSLikun Gao 1511ce81151cSLikun Gao 1512ce81151cSLikun Gao typedef struct { 1513ce81151cSLikun Gao uint8_t Gfx_ActiveHystLimit; 1514ce81151cSLikun Gao uint8_t Gfx_IdleHystLimit; 1515ce81151cSLikun Gao uint8_t Gfx_FPS; 1516ce81151cSLikun Gao uint8_t Gfx_MinActiveFreqType; 1517ce81151cSLikun Gao uint8_t Gfx_BoosterFreqType; 1518ce81151cSLikun Gao uint8_t PaddingGfx; 1519ce81151cSLikun Gao uint16_t Gfx_MinActiveFreq; // MHz 1520ce81151cSLikun Gao uint16_t Gfx_BoosterFreq; // MHz 1521ce81151cSLikun Gao uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms 1522ce81151cSLikun Gao uint32_t Gfx_PD_Data_limit_a; // Q16 1523ce81151cSLikun Gao uint32_t Gfx_PD_Data_limit_b; // Q16 1524ce81151cSLikun Gao uint32_t Gfx_PD_Data_limit_c; // Q16 1525ce81151cSLikun Gao uint32_t Gfx_PD_Data_error_coeff; // Q16 1526ce81151cSLikun Gao uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 1527ce81151cSLikun Gao 1528ce81151cSLikun Gao uint8_t Fclk_ActiveHystLimit; 1529ce81151cSLikun Gao uint8_t Fclk_IdleHystLimit; 1530ce81151cSLikun Gao uint8_t Fclk_FPS; 1531ce81151cSLikun Gao uint8_t Fclk_MinActiveFreqType; 1532ce81151cSLikun Gao uint8_t Fclk_BoosterFreqType; 1533ce81151cSLikun Gao uint8_t PaddingFclk; 1534ce81151cSLikun Gao uint16_t Fclk_MinActiveFreq; // MHz 1535ce81151cSLikun Gao uint16_t Fclk_BoosterFreq; // MHz 1536ce81151cSLikun Gao uint16_t Fclk_PD_Data_time_constant; // Time constant of PD controller in ms 1537ce81151cSLikun Gao uint32_t Fclk_PD_Data_limit_a; // Q16 1538ce81151cSLikun Gao uint32_t Fclk_PD_Data_limit_b; // Q16 1539ce81151cSLikun Gao uint32_t Fclk_PD_Data_limit_c; // Q16 1540ce81151cSLikun Gao uint32_t Fclk_PD_Data_error_coeff; // Q16 1541ce81151cSLikun Gao uint32_t Fclk_PD_Data_error_rate_coeff; // Q16 1542ce81151cSLikun Gao 1543ce81151cSLikun Gao uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16 1544ce81151cSLikun Gao uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS]; 1545ce81151cSLikun Gao uint8_t Mem_DownHystLimit[NUM_UCLK_DPM_LEVELS]; 1546ce81151cSLikun Gao uint16_t Mem_Fps; 1547ce81151cSLikun Gao uint8_t padding[2]; 1548ce81151cSLikun Gao 1549ce81151cSLikun Gao } DpmActivityMonitorCoeffInt_t; 1550ce81151cSLikun Gao 1551ce81151cSLikun Gao 1552ce81151cSLikun Gao typedef struct { 1553ce81151cSLikun Gao DpmActivityMonitorCoeffInt_t DpmActivityMonitorCoeffInt; 1554ce81151cSLikun Gao uint32_t MmHubPadding[8]; // SMU internal use 1555ce81151cSLikun Gao } DpmActivityMonitorCoeffIntExternal_t; 1556ce81151cSLikun Gao 1557ce81151cSLikun Gao 1558ce81151cSLikun Gao 1559ce81151cSLikun Gao // Workload bits 1560ce81151cSLikun Gao #define WORKLOAD_PPLIB_DEFAULT_BIT 0 1561ce81151cSLikun Gao #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 1562ce81151cSLikun Gao #define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 1563ce81151cSLikun Gao #define WORKLOAD_PPLIB_VIDEO_BIT 3 1564ce81151cSLikun Gao #define WORKLOAD_PPLIB_VR_BIT 4 1565ce81151cSLikun Gao #define WORKLOAD_PPLIB_COMPUTE_BIT 5 1566ce81151cSLikun Gao #define WORKLOAD_PPLIB_CUSTOM_BIT 6 1567ce81151cSLikun Gao #define WORKLOAD_PPLIB_WINDOW_3D_BIT 7 1568ce81151cSLikun Gao #define WORKLOAD_PPLIB_COUNT 8 1569ce81151cSLikun Gao 1570ce81151cSLikun Gao 1571ce81151cSLikun Gao // These defines are used with the following messages: 1572ce81151cSLikun Gao // SMC_MSG_TransferTableDram2Smu 1573ce81151cSLikun Gao // SMC_MSG_TransferTableSmu2Dram 1574ce81151cSLikun Gao 1575ce81151cSLikun Gao // Table transfer status 1576ce81151cSLikun Gao #define TABLE_TRANSFER_OK 0x0 1577ce81151cSLikun Gao #define TABLE_TRANSFER_FAILED 0xFF 1578ce81151cSLikun Gao #define TABLE_TRANSFER_PENDING 0xAB 1579ce81151cSLikun Gao 1580ce81151cSLikun Gao // Table types 1581ce81151cSLikun Gao #define TABLE_PPTABLE 0 1582ce81151cSLikun Gao #define TABLE_COMBO_PPTABLE 1 1583ce81151cSLikun Gao #define TABLE_WATERMARKS 2 1584ce81151cSLikun Gao #define TABLE_AVFS_PSM_DEBUG 3 1585ce81151cSLikun Gao #define TABLE_PMSTATUSLOG 4 1586ce81151cSLikun Gao #define TABLE_SMU_METRICS 5 1587ce81151cSLikun Gao #define TABLE_DRIVER_SMU_CONFIG 6 1588ce81151cSLikun Gao #define TABLE_ACTIVITY_MONITOR_COEFF 7 1589ce81151cSLikun Gao #define TABLE_OVERDRIVE 8 1590ce81151cSLikun Gao #define TABLE_I2C_COMMANDS 9 1591ce81151cSLikun Gao #define TABLE_DRIVER_INFO 10 1592ce81151cSLikun Gao #define TABLE_ECCINFO 11 1593ce81151cSLikun Gao #define TABLE_COUNT 12 1594ce81151cSLikun Gao 1595ce81151cSLikun Gao //IH Interupt ID 1596ce81151cSLikun Gao #define IH_INTERRUPT_ID_TO_DRIVER 0xFE 1597ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_BACO 0x2 1598ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_AC 0x3 1599ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_DC 0x4 1600ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 0x5 1601ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 0x6 1602ce81151cSLikun Gao #define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING 0x7 16037e5632cdSKenneth Feng #define IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL 0x8 16047e5632cdSKenneth Feng #define IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY 0x9 1605ce81151cSLikun Gao 1606ce81151cSLikun Gao #endif 1607