1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef SMU13_DRIVER_IF_ALDEBARAN_H 25 #define SMU13_DRIVER_IF_ALDEBARAN_H 26 27 #define NUM_VCLK_DPM_LEVELS 8 28 #define NUM_DCLK_DPM_LEVELS 8 29 #define NUM_SOCCLK_DPM_LEVELS 8 30 #define NUM_LCLK_DPM_LEVELS 8 31 #define NUM_UCLK_DPM_LEVELS 4 32 #define NUM_FCLK_DPM_LEVELS 8 33 #define NUM_XGMI_DPM_LEVELS 4 34 35 // Feature Control Defines 36 #define FEATURE_DATA_CALCULATIONS 0 37 #define FEATURE_DPM_GFXCLK_BIT 1 38 #define FEATURE_DPM_UCLK_BIT 2 39 #define FEATURE_DPM_SOCCLK_BIT 3 40 #define FEATURE_DPM_FCLK_BIT 4 41 #define FEATURE_DPM_LCLK_BIT 5 42 #define FEATURE_DPM_XGMI_BIT 6 43 #define FEATURE_DS_GFXCLK_BIT 7 44 #define FEATURE_DS_SOCCLK_BIT 8 45 #define FEATURE_DS_LCLK_BIT 9 46 #define FEATURE_DS_FCLK_BIT 10 47 #define FEATURE_DS_UCLK_BIT 11 48 #define FEATURE_GFX_SS_BIT 12 49 #define FEATURE_DPM_VCN_BIT 13 50 #define FEATURE_RSMU_SMN_CG_BIT 14 51 #define FEATURE_WAFL_CG_BIT 15 52 #define FEATURE_PPT_BIT 16 53 #define FEATURE_TDC_BIT 17 54 #define FEATURE_APCC_PLUS_BIT 18 55 #define FEATURE_APCC_DFLL_BIT 19 56 #define FEATURE_FW_CTF_BIT 20 57 #define FEATURE_THERMAL_BIT 21 58 #define FEATURE_OUT_OF_BAND_MONITOR_BIT 22 59 #define FEATURE_SPARE_23_BIT 23 60 #define FEATURE_XGMI_PER_LINK_PWR_DWN 24 61 #define FEATURE_DF_CSTATE 25 62 #define FEATURE_FUSE_CG_BIT 26 63 #define FEATURE_MP1_CG_BIT 27 64 #define FEATURE_SMUIO_CG_BIT 28 65 #define FEATURE_THM_CG_BIT 29 66 #define FEATURE_CLK_CG_BIT 30 67 #define FEATURE_EDC_BIT 31 68 #define FEATURE_SPARE_32_BIT 32 69 #define FEATURE_SPARE_33_BIT 33 70 #define FEATURE_SPARE_34_BIT 34 71 #define FEATURE_SPARE_35_BIT 35 72 #define FEATURE_SPARE_36_BIT 36 73 #define FEATURE_SPARE_37_BIT 37 74 #define FEATURE_SPARE_38_BIT 38 75 #define FEATURE_SPARE_39_BIT 39 76 #define FEATURE_SPARE_40_BIT 40 77 #define FEATURE_SPARE_41_BIT 41 78 #define FEATURE_SPARE_42_BIT 42 79 #define FEATURE_SPARE_43_BIT 43 80 #define FEATURE_SPARE_44_BIT 44 81 #define FEATURE_SPARE_45_BIT 45 82 #define FEATURE_SPARE_46_BIT 46 83 #define FEATURE_SPARE_47_BIT 47 84 #define FEATURE_SPARE_48_BIT 48 85 #define FEATURE_SPARE_49_BIT 49 86 #define FEATURE_SPARE_50_BIT 50 87 #define FEATURE_SPARE_51_BIT 51 88 #define FEATURE_SPARE_52_BIT 52 89 #define FEATURE_SPARE_53_BIT 53 90 #define FEATURE_SPARE_54_BIT 54 91 #define FEATURE_SPARE_55_BIT 55 92 #define FEATURE_SPARE_56_BIT 56 93 #define FEATURE_SPARE_57_BIT 57 94 #define FEATURE_SPARE_58_BIT 58 95 #define FEATURE_SPARE_59_BIT 59 96 #define FEATURE_SPARE_60_BIT 60 97 #define FEATURE_SPARE_61_BIT 61 98 #define FEATURE_SPARE_62_BIT 62 99 #define FEATURE_SPARE_63_BIT 63 100 101 #define NUM_FEATURES 64 102 103 // I2C Config Bit Defines 104 #define I2C_CONTROLLER_ENABLED 1 105 #define I2C_CONTROLLER_DISABLED 0 106 107 // Throttler Status Bits. 108 // These are aligned with the out of band monitor alarm bits for common throttlers 109 #define THROTTLER_PPT0_BIT 0 110 #define THROTTLER_PPT1_BIT 1 111 #define THROTTLER_TDC_GFX_BIT 2 112 #define THROTTLER_TDC_SOC_BIT 3 113 #define THROTTLER_TDC_HBM_BIT 4 114 #define THROTTLER_SPARE_5 5 115 #define THROTTLER_TEMP_GPU_BIT 6 116 #define THROTTLER_TEMP_MEM_BIT 7 117 #define THORTTLER_SPARE_8 8 118 #define THORTTLER_SPARE_9 9 119 #define THORTTLER_SPARE_10 10 120 #define THROTTLER_TEMP_VR_GFX_BIT 11 121 #define THROTTLER_TEMP_VR_SOC_BIT 12 122 #define THROTTLER_TEMP_VR_MEM_BIT 13 123 #define THORTTLER_SPARE_14 14 124 #define THORTTLER_SPARE_15 15 125 #define THORTTLER_SPARE_16 16 126 #define THORTTLER_SPARE_17 17 127 #define THORTTLER_SPARE_18 18 128 #define THROTTLER_APCC_BIT 19 129 130 // Table transfer status 131 #define TABLE_TRANSFER_OK 0x0 132 #define TABLE_TRANSFER_FAILED 0xFF 133 #define TABLE_TRANSFER_PENDING 0xAB 134 135 //I2C Interface 136 #define NUM_I2C_CONTROLLERS 8 137 138 #define I2C_CONTROLLER_ENABLED 1 139 #define I2C_CONTROLLER_DISABLED 0 140 141 #define MAX_SW_I2C_COMMANDS 24 142 143 #define ALDEBARAN_UMC_CHANNEL_NUM 32 144 145 typedef enum { 146 I2C_CONTROLLER_PORT_0, //CKSVII2C0 147 I2C_CONTROLLER_PORT_1, //CKSVII2C1 148 I2C_CONTROLLER_PORT_COUNT, 149 } I2cControllerPort_e; 150 151 typedef enum { 152 I2C_CONTROLLER_THROTTLER_TYPE_NONE, 153 I2C_CONTROLLER_THROTTLER_VR_GFX0, 154 I2C_CONTROLLER_THROTTLER_VR_GFX1, 155 I2C_CONTROLLER_THROTTLER_VR_SOC, 156 I2C_CONTROLLER_THROTTLER_VR_MEM, 157 I2C_CONTROLLER_THROTTLER_COUNT, 158 } I2cControllerThrottler_e; 159 160 typedef enum { 161 I2C_CONTROLLER_PROTOCOL_VR_MP2855, 162 I2C_CONTROLLER_PROTOCOL_COUNT, 163 } I2cControllerProtocol_e; 164 165 typedef struct { 166 uint8_t Enabled; 167 uint8_t Speed; 168 uint8_t SlaveAddress; 169 uint8_t ControllerPort; 170 uint8_t ThermalThrotter; 171 uint8_t I2cProtocol; 172 uint8_t PaddingConfig[2]; 173 } I2cControllerConfig_t; 174 175 typedef enum { 176 I2C_PORT_SVD_SCL, 177 I2C_PORT_GPIO, 178 } I2cPort_e; 179 180 typedef enum { 181 I2C_SPEED_FAST_50K, //50 Kbits/s 182 I2C_SPEED_FAST_100K, //100 Kbits/s 183 I2C_SPEED_FAST_400K, //400 Kbits/s 184 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 185 I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 186 I2C_SPEED_HIGH_2M, //2.3 Mbits/s 187 I2C_SPEED_COUNT, 188 } I2cSpeed_e; 189 190 typedef enum { 191 I2C_CMD_READ, 192 I2C_CMD_WRITE, 193 I2C_CMD_COUNT, 194 } I2cCmdType_e; 195 196 #define CMDCONFIG_STOP_BIT 0 197 #define CMDCONFIG_RESTART_BIT 1 198 #define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write 199 200 #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 201 #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 202 #define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT) 203 204 typedef struct { 205 uint8_t ReadWriteData; //Return data for read. Data to send for write 206 uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write 207 } SwI2cCmd_t; //SW I2C Command Table 208 209 typedef struct { 210 uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 211 uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select 212 uint8_t SlaveAddress; //Slave address of device 213 uint8_t NumCmds; //Number of commands 214 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 215 } SwI2cRequest_t; // SW I2C Request Table 216 217 typedef struct { 218 SwI2cRequest_t SwI2cRequest; 219 uint32_t Spare[8]; 220 uint32_t MmHubPadding[8]; // SMU internal use 221 } SwI2cRequestExternal_t; 222 223 typedef struct { 224 uint32_t a; // store in IEEE float format in this variable 225 uint32_t b; // store in IEEE float format in this variable 226 uint32_t c; // store in IEEE float format in this variable 227 } QuadraticInt_t; 228 229 typedef struct { 230 uint32_t m; // store in IEEE float format in this variable 231 uint32_t b; // store in IEEE float format in this variable 232 } LinearInt_t; 233 234 typedef enum { 235 GFXCLK_SOURCE_PLL, 236 GFXCLK_SOURCE_DFLL, 237 GFXCLK_SOURCE_COUNT, 238 } GfxclkSrc_e; 239 240 typedef enum { 241 PPCLK_GFXCLK, 242 PPCLK_VCLK, 243 PPCLK_DCLK, 244 PPCLK_SOCCLK, 245 PPCLK_UCLK, 246 PPCLK_FCLK, 247 PPCLK_LCLK, 248 PPCLK_COUNT, 249 } PPCLK_e; 250 251 typedef enum { 252 GPIO_INT_POLARITY_ACTIVE_LOW, 253 GPIO_INT_POLARITY_ACTIVE_HIGH, 254 } GpioIntPolarity_e; 255 256 //PPSMC_MSG_SetUclkDpmMode 257 typedef enum { 258 UCLK_DPM_MODE_BANDWIDTH, 259 UCLK_DPM_MODE_LATENCY, 260 } UCLK_DPM_MODE_e; 261 262 typedef struct { 263 uint8_t StartupLevel; 264 uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 265 uint16_t SsFmin; // Fmin for SS curve. If SS curve is selected, will use V@SSFmin for F <= Fmin 266 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 267 QuadraticInt_t SsCurve; // Slow-slow curve (GHz->V) 268 } DpmDescriptor_t; 269 270 typedef struct { 271 uint32_t Version; 272 273 // SECTION: Feature Enablement 274 uint32_t FeaturesToRun[2]; 275 276 // SECTION: Infrastructure Limits 277 uint16_t PptLimit; // Watts 278 uint16_t TdcLimitGfx; // Amps 279 uint16_t TdcLimitSoc; // Amps 280 uint16_t TdcLimitHbm; // Amps 281 uint16_t ThotspotLimit; // Celcius 282 uint16_t TmemLimit; // Celcius 283 uint16_t Tvr_gfxLimit; // Celcius 284 uint16_t Tvr_memLimit; // Celcius 285 uint16_t Tvr_socLimit; // Celcius 286 uint16_t PaddingLimit; 287 288 // SECTION: Voltage Control Parameters 289 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX 290 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC 291 292 //SECTION: DPM Config 1 293 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 294 295 uint8_t DidTableVclk[NUM_VCLK_DPM_LEVELS]; //PPCLK_VCLK 296 uint8_t DidTableDclk[NUM_DCLK_DPM_LEVELS]; //PPCLK_DCLK 297 uint8_t DidTableSocclk[NUM_SOCCLK_DPM_LEVELS]; //PPCLK_SOCCLK 298 uint8_t DidTableLclk[NUM_LCLK_DPM_LEVELS]; //PPCLK_LCLK 299 uint32_t FidTableFclk[NUM_FCLK_DPM_LEVELS]; //PPCLK_FCLK 300 uint8_t DidTableFclk[NUM_FCLK_DPM_LEVELS]; //PPCLK_FCLK 301 uint32_t FidTableUclk[NUM_UCLK_DPM_LEVELS]; //PPCLK_UCLK 302 uint8_t DidTableUclk[NUM_UCLK_DPM_LEVELS]; //PPCLK_UCLK 303 304 uint32_t StartupFidPll0; //GFXAVFSCLK, SOCCLK, MP0CLK, MPIOCLK, DXIOCLK 305 uint32_t StartupFidPll4; //VCLK, DCLK, WAFLCLK 306 uint32_t StartupFidPll5; //SMNCLK, MP1CLK, LCLK 307 308 uint8_t StartupSmnclkDid; 309 uint8_t StartupMp0clkDid; 310 uint8_t StartupMp1clkDid; 311 uint8_t StartupWaflclkDid; 312 uint8_t StartupGfxavfsclkDid; 313 uint8_t StartupMpioclkDid; 314 uint8_t StartupDxioclkDid; 315 uint8_t spare123; 316 317 uint8_t StartupVidGpu0Svi0Plane0; //VDDCR_GFX0 318 uint8_t StartupVidGpu0Svi0Plane1; //VDDCR_SOC 319 uint8_t StartupVidGpu0Svi1Plane0; //VDDCR_HBM 320 uint8_t StartupVidGpu0Svi1Plane1; //UNUSED [0 = plane is not used and should not be programmed] 321 322 uint8_t StartupVidGpu1Svi0Plane0; //VDDCR_GFX1 323 uint8_t StartupVidGpu1Svi0Plane1; //UNUSED [0 = plane is not used and should not be programmed] 324 uint8_t StartupVidGpu1Svi1Plane0; //UNUSED [0 = plane is not used and should not be programmed] 325 uint8_t StartupVidGpu1Svi1Plane1; //UNUSED [0 = plane is not used and should not be programmed] 326 327 // GFXCLK DPM 328 uint16_t GfxclkFmax; // In MHz 329 uint16_t GfxclkFmin; // In MHz 330 uint16_t GfxclkFidle; // In MHz 331 uint16_t GfxclkFinit; // In MHz 332 uint8_t GfxclkSource; // GfxclkSrc_e [0 = PLL, 1 = DFLL] 333 uint8_t spare1[2]; 334 uint8_t StartupGfxclkDid; 335 uint32_t StartupGfxclkFid; 336 337 // SECTION: AVFS 338 uint16_t GFX_Guardband_Freq[8]; // MHz [unsigned] 339 int16_t GFX_Guardband_Voltage_Cold[8]; // mV [signed] 340 int16_t GFX_Guardband_Voltage_Mid[8]; // mV [signed] 341 int16_t GFX_Guardband_Voltage_Hot[8]; // mV [signed] 342 343 uint16_t SOC_Guardband_Freq[8]; // MHz [unsigned] 344 int16_t SOC_Guardband_Voltage_Cold[8]; // mV [signed] 345 int16_t SOC_Guardband_Voltage_Mid[8]; // mV [signed] 346 int16_t SOC_Guardband_Voltage_Hot[8]; // mV [signed] 347 348 // VDDCR_GFX BTC 349 uint16_t DcBtcEnabled; 350 int16_t DcBtcMin; // mV [signed] 351 int16_t DcBtcMax; // mV [signed] 352 int16_t DcBtcGb; // mV [signed] 353 354 // SECTION: XGMI 355 uint8_t XgmiLinkSpeed[NUM_XGMI_DPM_LEVELS]; //Gbps [EX: 32 = 32Gbps] 356 uint8_t XgmiLinkWidth[NUM_XGMI_DPM_LEVELS]; //Width [EX: 16 = x16] 357 uint8_t XgmiStartupLevel; 358 uint8_t spare12[3]; 359 360 // GFX Vmin 361 uint16_t GFX_PPVmin_Enabled; 362 uint16_t GFX_Vmin_Plat_Offset_Hot; // mV 363 uint16_t GFX_Vmin_Plat_Offset_Cold; // mV 364 uint16_t GFX_Vmin_Hot_T0; // mV 365 uint16_t GFX_Vmin_Cold_T0; // mV 366 uint16_t GFX_Vmin_Hot_Eol; // mV 367 uint16_t GFX_Vmin_Cold_Eol; // mV 368 uint16_t GFX_Vmin_Aging_Offset; // mV 369 uint16_t GFX_Vmin_Temperature_Hot; // 'C 370 uint16_t GFX_Vmin_Temperature_Cold; // 'C 371 372 // SOC Vmin 373 uint16_t SOC_PPVmin_Enabled; 374 uint16_t SOC_Vmin_Plat_Offset_Hot; // mV 375 uint16_t SOC_Vmin_Plat_Offset_Cold; // mV 376 uint16_t SOC_Vmin_Hot_T0; // mV 377 uint16_t SOC_Vmin_Cold_T0; // mV 378 uint16_t SOC_Vmin_Hot_Eol; // mV 379 uint16_t SOC_Vmin_Cold_Eol; // mV 380 uint16_t SOC_Vmin_Aging_Offset; // mV 381 uint16_t SOC_Vmin_Temperature_Hot; // 'C 382 uint16_t SOC_Vmin_Temperature_Cold; // 'C 383 384 // APCC Settings 385 uint32_t ApccPlusResidencyLimit; //PCC residency % (0-100) 386 387 // Determinism 388 uint16_t DeterminismVoltageOffset; //mV 389 uint16_t spare22; 390 391 // reserved 392 uint32_t spare3[14]; 393 394 // SECTION: BOARD PARAMETERS 395 // Telemetry Settings 396 uint16_t GfxMaxCurrent; // in Amps 397 int8_t GfxOffset; // in Amps 398 uint8_t Padding_TelemetryGfx; 399 400 uint16_t SocMaxCurrent; // in Amps 401 int8_t SocOffset; // in Amps 402 uint8_t Padding_TelemetrySoc; 403 404 uint16_t MemMaxCurrent; // in Amps 405 int8_t MemOffset; // in Amps 406 uint8_t Padding_TelemetryMem; 407 408 uint16_t BoardMaxCurrent; // in Amps 409 int8_t BoardOffset; // in Amps 410 uint8_t Padding_TelemetryBoardInput; 411 412 // Platform input telemetry voltage coefficient 413 uint32_t BoardVoltageCoeffA; // decode by /1000 414 uint32_t BoardVoltageCoeffB; // decode by /1000 415 416 // GPIO Settings 417 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 418 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 419 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 420 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 421 422 // UCLK Spread Spectrum 423 uint8_t UclkSpreadEnabled; // on or off 424 uint8_t UclkSpreadPercent; // Q4.4 425 uint16_t UclkSpreadFreq; // kHz 426 427 // FCLK Spread Spectrum 428 uint8_t FclkSpreadEnabled; // on or off 429 uint8_t FclkSpreadPercent; // Q4.4 430 uint16_t FclkSpreadFreq; // kHz 431 432 // I2C Controller Structure 433 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 434 435 // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence 436 uint8_t GpioI2cScl; // Serial Clock 437 uint8_t GpioI2cSda; // Serial Data 438 uint16_t spare5; 439 440 uint16_t XgmiMaxCurrent; // in Amps 441 int8_t XgmiOffset; // in Amps 442 uint8_t Padding_TelemetryXgmi; 443 444 uint16_t EdcPowerLimit; 445 uint16_t spare6; 446 447 //reserved 448 uint32_t reserved[14]; 449 450 } PPTable_t; 451 452 typedef struct { 453 // Time constant parameters for clock averages in ms 454 uint16_t GfxclkAverageLpfTau; 455 uint16_t SocclkAverageLpfTau; 456 uint16_t UclkAverageLpfTau; 457 uint16_t GfxActivityLpfTau; 458 uint16_t UclkActivityLpfTau; 459 460 uint16_t SocketPowerLpfTau; 461 462 uint32_t Spare[8]; 463 // Padding - ignore 464 uint32_t MmHubPadding[8]; // SMU internal use 465 } DriverSmuConfig_t; 466 467 typedef struct { 468 uint16_t CurrClock[PPCLK_COUNT]; 469 uint16_t Padding1 ; 470 uint16_t AverageGfxclkFrequency; 471 uint16_t AverageSocclkFrequency; 472 uint16_t AverageUclkFrequency ; 473 uint16_t AverageGfxActivity ; 474 uint16_t AverageUclkActivity ; 475 uint8_t CurrSocVoltageOffset ; 476 uint8_t CurrGfxVoltageOffset ; 477 uint8_t CurrMemVidOffset ; 478 uint8_t Padding8 ; 479 uint16_t AverageSocketPower ; 480 uint16_t TemperatureEdge ; 481 uint16_t TemperatureHotspot ; 482 uint16_t TemperatureHBM ; // Max 483 uint16_t TemperatureVrGfx ; 484 uint16_t TemperatureVrSoc ; 485 uint16_t TemperatureVrMem ; 486 uint32_t ThrottlerStatus ; 487 488 uint32_t PublicSerialNumLower32; 489 uint32_t PublicSerialNumUpper32; 490 uint16_t TemperatureAllHBM[4] ; 491 uint32_t GfxBusyAcc ; 492 uint32_t DramBusyAcc ; 493 uint32_t EnergyAcc64bitLow ; //15.259uJ resolution 494 uint32_t EnergyAcc64bitHigh ; 495 uint32_t TimeStampLow ; //10ns resolution 496 uint32_t TimeStampHigh ; 497 498 // Padding - ignore 499 uint32_t MmHubPadding[8]; // SMU internal use 500 } SmuMetrics_t; 501 502 503 typedef struct { 504 uint16_t avgPsmCount[76]; 505 uint16_t minPsmCount[76]; 506 float avgPsmVoltage[76]; 507 float minPsmVoltage[76]; 508 509 uint32_t MmHubPadding[8]; // SMU internal use 510 } AvfsDebugTable_t; 511 512 typedef struct { 513 uint64_t mca_umc_status; 514 uint64_t mca_umc_addr; 515 uint16_t ce_count_lo_chip; 516 uint16_t ce_count_hi_chip; 517 518 uint32_t eccPadding; 519 } EccInfo_t; 520 521 typedef struct { 522 uint64_t mca_umc_status; 523 uint64_t mca_umc_addr; 524 525 uint16_t ce_count_lo_chip; 526 uint16_t ce_count_hi_chip; 527 528 uint32_t eccPadding; 529 530 uint64_t mca_ceumc_addr; 531 } EccInfo_V2_t; 532 533 typedef struct { 534 union { 535 EccInfo_t EccInfo[ALDEBARAN_UMC_CHANNEL_NUM]; 536 EccInfo_V2_t EccInfo_V2[ALDEBARAN_UMC_CHANNEL_NUM]; 537 }; 538 } EccInfoTable_t; 539 540 // These defines are used with the following messages: 541 // SMC_MSG_TransferTableDram2Smu 542 // SMC_MSG_TransferTableSmu2Dram 543 #define TABLE_PPTABLE 0 544 #define TABLE_AVFS_PSM_DEBUG 1 545 #define TABLE_AVFS_FUSE_OVERRIDE 2 546 #define TABLE_PMSTATUSLOG 3 547 #define TABLE_SMU_METRICS 4 548 #define TABLE_DRIVER_SMU_CONFIG 5 549 #define TABLE_I2C_COMMANDS 6 550 #define TABLE_ECCINFO 7 551 #define TABLE_COUNT 8 552 553 #endif 554