1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __SMU11_DRIVER_IF_SIENNA_CICHLID_H__ 25 #define __SMU11_DRIVER_IF_SIENNA_CICHLID_H__ 26 27 // *** IMPORTANT *** 28 // SMU TEAM: Always increment the interface version if 29 // any structure is changed in this file 30 #define SMU11_DRIVER_IF_VERSION 0x40 31 32 #define PPTABLE_Sienna_Cichlid_SMU_VERSION 7 33 34 #define NUM_GFXCLK_DPM_LEVELS 16 35 #define NUM_SMNCLK_DPM_LEVELS 2 36 #define NUM_SOCCLK_DPM_LEVELS 8 37 #define NUM_MP0CLK_DPM_LEVELS 2 38 #define NUM_DCLK_DPM_LEVELS 8 39 #define NUM_VCLK_DPM_LEVELS 8 40 #define NUM_DCEFCLK_DPM_LEVELS 8 41 #define NUM_PHYCLK_DPM_LEVELS 8 42 #define NUM_DISPCLK_DPM_LEVELS 8 43 #define NUM_PIXCLK_DPM_LEVELS 8 44 #define NUM_DTBCLK_DPM_LEVELS 8 45 #define NUM_UCLK_DPM_LEVELS 4 46 #define NUM_MP1CLK_DPM_LEVELS 2 47 #define NUM_LINK_LEVELS 2 48 #define NUM_FCLK_DPM_LEVELS 8 49 #define NUM_XGMI_LEVELS 2 50 #define NUM_XGMI_PSTATE_LEVELS 4 51 #define NUM_OD_FAN_MAX_POINTS 6 52 53 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1) 54 #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1) 55 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1) 56 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1) 57 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1) 58 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1) 59 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1) 60 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1) 61 #define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1) 62 #define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1) 63 #define MAX_DTBCLK_DPM_LEVEL (NUM_DTBCLK_DPM_LEVELS - 1) 64 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) 65 #define MAX_MP1CLK_DPM_LEVEL (NUM_MP1CLK_DPM_LEVELS - 1) 66 #define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1) 67 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1) 68 69 //Gemini Modes 70 #define PPSMC_GeminiModeNone 0 //Single GPU board 71 #define PPSMC_GeminiModeMaster 1 //Master GPU on a Gemini board 72 #define PPSMC_GeminiModeSlave 2 //Slave GPU on a Gemini board 73 74 // Feature Control Defines 75 // DPM 76 #define FEATURE_DPM_PREFETCHER_BIT 0 77 #define FEATURE_DPM_GFXCLK_BIT 1 78 #define FEATURE_DPM_GFX_GPO_BIT 2 79 #define FEATURE_DPM_UCLK_BIT 3 80 #define FEATURE_DPM_FCLK_BIT 4 81 #define FEATURE_DPM_SOCCLK_BIT 5 82 #define FEATURE_DPM_MP0CLK_BIT 6 83 #define FEATURE_DPM_LINK_BIT 7 84 #define FEATURE_DPM_DCEFCLK_BIT 8 85 #define FEATURE_DPM_XGMI_BIT 9 86 #define FEATURE_MEM_VDDCI_SCALING_BIT 10 87 #define FEATURE_MEM_MVDD_SCALING_BIT 11 88 89 //Idle 90 #define FEATURE_DS_GFXCLK_BIT 12 91 #define FEATURE_DS_SOCCLK_BIT 13 92 #define FEATURE_DS_FCLK_BIT 14 93 #define FEATURE_DS_LCLK_BIT 15 94 #define FEATURE_DS_DCEFCLK_BIT 16 95 #define FEATURE_DS_UCLK_BIT 17 96 #define FEATURE_GFX_ULV_BIT 18 97 #define FEATURE_FW_DSTATE_BIT 19 98 #define FEATURE_GFXOFF_BIT 20 99 #define FEATURE_BACO_BIT 21 100 #define FEATURE_MM_DPM_PG_BIT 22 101 #define FEATURE_SPARE_23_BIT 23 102 //Throttler/Response 103 #define FEATURE_PPT_BIT 24 104 #define FEATURE_TDC_BIT 25 105 #define FEATURE_APCC_PLUS_BIT 26 106 #define FEATURE_GTHR_BIT 27 107 #define FEATURE_ACDC_BIT 28 108 #define FEATURE_VR0HOT_BIT 29 109 #define FEATURE_VR1HOT_BIT 30 110 #define FEATURE_FW_CTF_BIT 31 111 #define FEATURE_FAN_CONTROL_BIT 32 112 #define FEATURE_THERMAL_BIT 33 113 #define FEATURE_GFX_DCS_BIT 34 114 //VF 115 #define FEATURE_RM_BIT 35 116 #define FEATURE_LED_DISPLAY_BIT 36 117 //Other 118 #define FEATURE_GFX_SS_BIT 37 119 #define FEATURE_OUT_OF_BAND_MONITOR_BIT 38 120 #define FEATURE_TEMP_DEPENDENT_VMIN_BIT 39 121 122 #define FEATURE_MMHUB_PG_BIT 40 123 #define FEATURE_ATHUB_PG_BIT 41 124 #define FEATURE_APCC_DFLL_BIT 42 125 #define FEATURE_DF_SUPERV_BIT 43 126 #define FEATURE_RSMU_SMN_CG_BIT 44 127 #define FEATURE_DF_CSTATE_BIT 45 128 #define FEATURE_2_STEP_PSTATE_BIT 46 129 #define FEATURE_SMNCLK_DPM_BIT 47 130 #define FEATURE_PERLINK_GMIDOWN_BIT 48 131 #define FEATURE_GFX_EDC_BIT 49 132 #define FEATURE_GFX_PER_PART_VMIN_BIT 50 133 #define FEATURE_SMART_SHIFT_BIT 51 134 #define FEATURE_APT_BIT 52 135 #define FEATURE_SPARE_53_BIT 53 136 #define FEATURE_SPARE_54_BIT 54 137 #define FEATURE_SPARE_55_BIT 55 138 #define FEATURE_SPARE_56_BIT 56 139 #define FEATURE_SPARE_57_BIT 57 140 #define FEATURE_SPARE_58_BIT 58 141 #define FEATURE_SPARE_59_BIT 59 142 #define FEATURE_SPARE_60_BIT 60 143 #define FEATURE_SPARE_61_BIT 61 144 #define FEATURE_SPARE_62_BIT 62 145 #define FEATURE_SPARE_63_BIT 63 146 #define NUM_FEATURES 64 147 148 //For use with feature control messages 149 typedef enum { 150 FEATURE_PWR_ALL, 151 FEATURE_PWR_S5, 152 FEATURE_PWR_BACO, 153 FEATURE_PWR_SOC, 154 FEATURE_PWR_GFX, 155 FEATURE_PWR_DOMAIN_COUNT, 156 } FEATURE_PWR_DOMAIN_e; 157 158 159 // Debug Overrides Bitmask 160 #define DPM_OVERRIDE_DISABLE_FCLK_PID 0x00000001 161 #define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000002 162 #define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000004 163 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_FCLK 0x00000008 164 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_FCLK 0x00000010 165 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_SOCCLK 0x00000020 166 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_UCLK 0x00000040 167 #define DPM_OVERRIDE_DISABLE_VOLT_LINK_DCE_FCLK 0x00000080 168 #define DPM_OVERRIDE_DISABLE_VOLT_LINK_MP0_SOCCLK 0x00000100 169 #define DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN 0x00000200 170 #define DPM_OVERRIDE_DISABLE_MEMORY_TEMPERATURE_READ 0x00000400 171 #define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCEFCLK 0x00000800 172 #define DPM_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x00001000 173 #define DPM_OVERRIDE_DISABLE_VCN_PG 0x00002000 174 #define DPM_OVERRIDE_DISABLE_FMAX_VMAX 0x00004000 175 #define DPM_OVERRIDE_ENABLE_eGPU_USB_WA 0x00008000 176 177 // VR Mapping Bit Defines 178 #define VR_MAPPING_VR_SELECT_MASK 0x01 179 #define VR_MAPPING_VR_SELECT_SHIFT 0x00 180 181 #define VR_MAPPING_PLANE_SELECT_MASK 0x02 182 #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 183 184 // PSI Bit Defines 185 #define PSI_SEL_VR0_PLANE0_PSI0 0x01 186 #define PSI_SEL_VR0_PLANE0_PSI1 0x02 187 #define PSI_SEL_VR0_PLANE1_PSI0 0x04 188 #define PSI_SEL_VR0_PLANE1_PSI1 0x08 189 #define PSI_SEL_VR1_PLANE0_PSI0 0x10 190 #define PSI_SEL_VR1_PLANE0_PSI1 0x20 191 #define PSI_SEL_VR1_PLANE1_PSI0 0x40 192 #define PSI_SEL_VR1_PLANE1_PSI1 0x80 193 194 // Throttler Control/Status Bits 195 #define THROTTLER_PADDING_BIT 0 196 #define THROTTLER_TEMP_EDGE_BIT 1 197 #define THROTTLER_TEMP_HOTSPOT_BIT 2 198 #define THROTTLER_TEMP_MEM_BIT 3 199 #define THROTTLER_TEMP_VR_GFX_BIT 4 200 #define THROTTLER_TEMP_VR_MEM0_BIT 5 201 #define THROTTLER_TEMP_VR_MEM1_BIT 6 202 #define THROTTLER_TEMP_VR_SOC_BIT 7 203 #define THROTTLER_TEMP_LIQUID0_BIT 8 204 #define THROTTLER_TEMP_LIQUID1_BIT 9 205 #define THROTTLER_TEMP_PLX_BIT 10 206 #define THROTTLER_TDC_GFX_BIT 11 207 #define THROTTLER_TDC_SOC_BIT 12 208 #define THROTTLER_PPT0_BIT 13 209 #define THROTTLER_PPT1_BIT 14 210 #define THROTTLER_PPT2_BIT 15 211 #define THROTTLER_PPT3_BIT 16 212 #define THROTTLER_FIT_BIT 17 213 #define THROTTLER_PPM_BIT 18 214 #define THROTTLER_APCC_BIT 19 215 #define THROTTLER_COUNT 20 216 217 // FW DState Features Control Bits 218 // FW DState Features Control Bits 219 #define FW_DSTATE_SOC_ULV_BIT 0 220 #define FW_DSTATE_G6_HSR_BIT 1 221 #define FW_DSTATE_G6_PHY_VDDCI_OFF_BIT 2 222 #define FW_DSTATE_MP0_DS_BIT 3 223 #define FW_DSTATE_SMN_DS_BIT 4 224 #define FW_DSTATE_MP1_DS_BIT 5 225 #define FW_DSTATE_MP1_WHISPER_MODE_BIT 6 226 #define FW_DSTATE_SOC_LIV_MIN_BIT 7 227 #define FW_DSTATE_SOC_PLL_PWRDN_BIT 8 228 #define FW_DSTATE_MEM_PLL_PWRDN_BIT 9 229 #define FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT 10 230 #define FW_DSTATE_MEM_PSI_BIT 11 231 #define FW_DSTATE_HSR_NON_STROBE_BIT 12 232 #define FW_DSTATE_MP0_ENTER_WFI_BIT 13 233 234 #define FW_DSTATE_SOC_ULV_MASK (1 << FW_DSTATE_SOC_ULV_BIT ) 235 #define FW_DSTATE_G6_HSR_MASK (1 << FW_DSTATE_G6_HSR_BIT ) 236 #define FW_DSTATE_G6_PHY_VDDCI_OFF_MASK (1 << FW_DSTATE_G6_PHY_VDDCI_OFF_BIT ) 237 #define FW_DSTATE_MP1_DS_MASK (1 << FW_DSTATE_MP1_DS_BIT ) 238 #define FW_DSTATE_MP0_DS_MASK (1 << FW_DSTATE_MP0_DS_BIT ) 239 #define FW_DSTATE_SMN_DS_MASK (1 << FW_DSTATE_SMN_DS_BIT ) 240 #define FW_DSTATE_MP1_WHISPER_MODE_MASK (1 << FW_DSTATE_MP1_WHISPER_MODE_BIT ) 241 #define FW_DSTATE_SOC_LIV_MIN_MASK (1 << FW_DSTATE_SOC_LIV_MIN_BIT ) 242 #define FW_DSTATE_SOC_PLL_PWRDN_MASK (1 << FW_DSTATE_SOC_PLL_PWRDN_BIT ) 243 #define FW_DSTATE_MEM_PLL_PWRDN_MASK (1 << FW_DSTATE_MEM_PLL_PWRDN_BIT ) 244 #define FW_DSTATE_OPTIMIZE_MALL_REFRESH_MASK (1 << FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT ) 245 #define FW_DSTATE_MEM_PSI_MASK (1 << FW_DSTATE_MEM_PSI_BIT ) 246 #define FW_DSTATE_HSR_NON_STROBE_MASK (1 << FW_DSTATE_HSR_NON_STROBE_BIT ) 247 #define FW_DSTATE_MP0_ENTER_WFI_MASK (1 << FW_DSTATE_MP0_ENTER_WFI_BIT ) 248 249 // GFX GPO Feature Contains PACE and DEM sub features 250 #define GFX_GPO_PACE_BIT 0 251 #define GFX_GPO_DEM_BIT 1 252 253 #define GFX_GPO_PACE_MASK (1 << GFX_GPO_PACE_BIT) 254 #define GFX_GPO_DEM_MASK (1 << GFX_GPO_DEM_BIT ) 255 256 #define GPO_UPDATE_REQ_UCLKDPM_MASK 0x1 257 #define GPO_UPDATE_REQ_FCLKDPM_MASK 0x2 258 #define GPO_UPDATE_REQ_MALLHIT_MASK 0x4 259 260 261 //LED Display Mask & Control Bits 262 #define LED_DISPLAY_GFX_DPM_BIT 0 263 #define LED_DISPLAY_PCIE_BIT 1 264 #define LED_DISPLAY_ERROR_BIT 2 265 266 //RLC Pace Table total number of levels 267 #define RLC_PACE_TABLE_NUM_LEVELS 16 268 #define SIENNA_CICHLID_UMC_CHANNEL_NUM 16 269 270 typedef struct { 271 uint64_t mca_umc_status; 272 uint64_t mca_umc_addr; 273 274 uint16_t ce_count_lo_chip; 275 uint16_t ce_count_hi_chip; 276 277 uint32_t eccPadding; 278 } EccInfo_t; 279 280 typedef struct { 281 EccInfo_t EccInfo[SIENNA_CICHLID_UMC_CHANNEL_NUM]; 282 } EccInfoTable_t; 283 284 typedef enum { 285 DRAM_BIT_WIDTH_DISABLED = 0, 286 DRAM_BIT_WIDTH_X_8, 287 DRAM_BIT_WIDTH_X_16, 288 DRAM_BIT_WIDTH_X_32, 289 DRAM_BIT_WIDTH_X_64, // NOT USED. 290 DRAM_BIT_WIDTH_X_128, 291 DRAM_BIT_WIDTH_COUNT, 292 } DRAM_BIT_WIDTH_TYPE_e; 293 294 //I2C Interface 295 #define NUM_I2C_CONTROLLERS 16 296 297 #define I2C_CONTROLLER_ENABLED 1 298 #define I2C_CONTROLLER_DISABLED 0 299 300 #define MAX_SW_I2C_COMMANDS 24 301 302 303 typedef enum { 304 I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0 305 I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1 306 I2C_CONTROLLER_PORT_COUNT, 307 } I2cControllerPort_e; 308 309 typedef enum { 310 I2C_CONTROLLER_NAME_VR_GFX = 0, 311 I2C_CONTROLLER_NAME_VR_SOC, 312 I2C_CONTROLLER_NAME_VR_VDDCI, 313 I2C_CONTROLLER_NAME_VR_MVDD, 314 I2C_CONTROLLER_NAME_LIQUID0, 315 I2C_CONTROLLER_NAME_LIQUID1, 316 I2C_CONTROLLER_NAME_PLX, 317 I2C_CONTROLLER_NAME_OTHER, 318 I2C_CONTROLLER_NAME_COUNT, 319 } I2cControllerName_e; 320 321 typedef enum { 322 I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 323 I2C_CONTROLLER_THROTTLER_VR_GFX, 324 I2C_CONTROLLER_THROTTLER_VR_SOC, 325 I2C_CONTROLLER_THROTTLER_VR_VDDCI, 326 I2C_CONTROLLER_THROTTLER_VR_MVDD, 327 I2C_CONTROLLER_THROTTLER_LIQUID0, 328 I2C_CONTROLLER_THROTTLER_LIQUID1, 329 I2C_CONTROLLER_THROTTLER_PLX, 330 I2C_CONTROLLER_THROTTLER_INA3221, 331 I2C_CONTROLLER_THROTTLER_COUNT, 332 } I2cControllerThrottler_e; 333 334 typedef enum { 335 I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5, 336 I2C_CONTROLLER_PROTOCOL_VR_IR35217, 337 I2C_CONTROLLER_PROTOCOL_TMP_TMP102A, 338 I2C_CONTROLLER_PROTOCOL_INA3221, 339 I2C_CONTROLLER_PROTOCOL_COUNT, 340 } I2cControllerProtocol_e; 341 342 typedef struct { 343 uint8_t Enabled; 344 uint8_t Speed; 345 uint8_t SlaveAddress; 346 uint8_t ControllerPort; 347 uint8_t ControllerName; 348 uint8_t ThermalThrotter; 349 uint8_t I2cProtocol; 350 uint8_t PaddingConfig; 351 } I2cControllerConfig_t; 352 353 typedef enum { 354 I2C_PORT_SVD_SCL = 0, 355 I2C_PORT_GPIO, 356 } I2cPort_e; 357 358 typedef enum { 359 I2C_SPEED_FAST_50K = 0, //50 Kbits/s 360 I2C_SPEED_FAST_100K, //100 Kbits/s 361 I2C_SPEED_FAST_400K, //400 Kbits/s 362 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 363 I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 364 I2C_SPEED_HIGH_2M, //2.3 Mbits/s 365 I2C_SPEED_COUNT, 366 } I2cSpeed_e; 367 368 typedef enum { 369 I2C_CMD_READ = 0, 370 I2C_CMD_WRITE, 371 I2C_CMD_COUNT, 372 } I2cCmdType_e; 373 374 typedef enum { 375 FAN_MODE_AUTO = 0, 376 FAN_MODE_MANUAL_LINEAR, 377 } FanMode_e; 378 379 #define CMDCONFIG_STOP_BIT 0 380 #define CMDCONFIG_RESTART_BIT 1 381 #define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write 382 383 #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 384 #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 385 #define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT) 386 387 typedef struct { 388 uint8_t ReadWriteData; //Return data for read. Data to send for write 389 uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write 390 } SwI2cCmd_t; //SW I2C Command Table 391 392 typedef struct { 393 uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 394 uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select 395 uint8_t SlaveAddress; //Slave address of device 396 uint8_t NumCmds; //Number of commands 397 398 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 399 } SwI2cRequest_t; // SW I2C Request Table 400 401 typedef struct { 402 SwI2cRequest_t SwI2cRequest; 403 404 uint32_t Spare[8]; 405 uint32_t MmHubPadding[8]; // SMU internal use 406 } SwI2cRequestExternal_t; 407 408 //D3HOT sequences 409 typedef enum { 410 BACO_SEQUENCE, 411 MSR_SEQUENCE, 412 BAMACO_SEQUENCE, 413 ULPS_SEQUENCE, 414 D3HOT_SEQUENCE_COUNT, 415 } D3HOTSequence_e; 416 417 //THis is aligned with RSMU PGFSM Register Mapping 418 typedef enum { 419 PG_DYNAMIC_MODE = 0, 420 PG_STATIC_MODE, 421 } PowerGatingMode_e; 422 423 //This is aligned with RSMU PGFSM Register Mapping 424 typedef enum { 425 PG_POWER_DOWN = 0, 426 PG_POWER_UP, 427 } PowerGatingSettings_e; 428 429 typedef struct { 430 uint32_t a; // store in IEEE float format in this variable 431 uint32_t b; // store in IEEE float format in this variable 432 uint32_t c; // store in IEEE float format in this variable 433 } QuadraticInt_t; 434 435 typedef struct { 436 uint32_t a; // store in fixed point, [31:20] signed integer, [19:0] fractional bits 437 uint32_t b; // store in fixed point, [31:20] signed integer, [19:0] fractional bits 438 uint32_t c; // store in fixed point, [31:20] signed integer, [19:0] fractional bits 439 } QuadraticFixedPoint_t; 440 441 typedef struct { 442 uint32_t m; // store in IEEE float format in this variable 443 uint32_t b; // store in IEEE float format in this variable 444 } LinearInt_t; 445 446 typedef struct { 447 uint32_t a; // store in IEEE float format in this variable 448 uint32_t b; // store in IEEE float format in this variable 449 uint32_t c; // store in IEEE float format in this variable 450 } DroopInt_t; 451 452 //Piecewise linear droop model, Sienna_Cichlid currently used only for GFX DFLL 453 #define NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS 5 454 typedef enum { 455 PIECEWISE_LINEAR_FUSED_MODEL = 0, 456 PIECEWISE_LINEAR_PP_MODEL, 457 QUADRATIC_PP_MODEL, 458 PERPART_PIECEWISE_LINEAR_PP_MODEL, 459 } DfllDroopModelSelect_e; 460 461 typedef struct { 462 uint32_t Fset[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //in GHz, store in IEEE float format 463 uint32_t Vdroop[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //in V , store in IEEE float format 464 }PiecewiseLinearDroopInt_t; 465 466 typedef enum { 467 GFXCLK_SOURCE_PLL = 0, 468 GFXCLK_SOURCE_DFLL, 469 GFXCLK_SOURCE_COUNT, 470 } GFXCLK_SOURCE_e; 471 472 //Only Clks that have DPM descriptors are listed here 473 typedef enum { 474 PPCLK_GFXCLK = 0, 475 PPCLK_SOCCLK, 476 PPCLK_UCLK, 477 PPCLK_FCLK, 478 PPCLK_DCLK_0, 479 PPCLK_VCLK_0, 480 PPCLK_DCLK_1, 481 PPCLK_VCLK_1, 482 PPCLK_DCEFCLK, 483 PPCLK_DISPCLK, 484 PPCLK_PIXCLK, 485 PPCLK_PHYCLK, 486 PPCLK_DTBCLK, 487 PPCLK_COUNT, 488 } PPCLK_e; 489 490 typedef enum { 491 VOLTAGE_MODE_AVFS = 0, 492 VOLTAGE_MODE_AVFS_SS, 493 VOLTAGE_MODE_SS, 494 VOLTAGE_MODE_COUNT, 495 } VOLTAGE_MODE_e; 496 497 498 typedef enum { 499 AVFS_VOLTAGE_GFX = 0, 500 AVFS_VOLTAGE_SOC, 501 AVFS_VOLTAGE_COUNT, 502 } AVFS_VOLTAGE_TYPE_e; 503 504 typedef enum { 505 UCLK_DIV_BY_1 = 0, 506 UCLK_DIV_BY_2, 507 UCLK_DIV_BY_4, 508 UCLK_DIV_BY_8, 509 } UCLK_DIV_e; 510 511 typedef enum { 512 GPIO_INT_POLARITY_ACTIVE_LOW = 0, 513 GPIO_INT_POLARITY_ACTIVE_HIGH, 514 } GpioIntPolarity_e; 515 516 typedef enum { 517 PWR_CONFIG_TDP = 0, 518 PWR_CONFIG_TGP, 519 PWR_CONFIG_TCP_ESTIMATED, 520 PWR_CONFIG_TCP_MEASURED, 521 } PwrConfig_e; 522 523 typedef enum { 524 XGMI_LINK_RATE_2 = 2, // 2Gbps 525 XGMI_LINK_RATE_4 = 4, // 4Gbps 526 XGMI_LINK_RATE_8 = 8, // 8Gbps 527 XGMI_LINK_RATE_12 = 12, // 12Gbps 528 XGMI_LINK_RATE_16 = 16, // 16Gbps 529 XGMI_LINK_RATE_17 = 17, // 17Gbps 530 XGMI_LINK_RATE_18 = 18, // 18Gbps 531 XGMI_LINK_RATE_19 = 19, // 19Gbps 532 XGMI_LINK_RATE_20 = 20, // 20Gbps 533 XGMI_LINK_RATE_21 = 21, // 21Gbps 534 XGMI_LINK_RATE_22 = 22, // 22Gbps 535 XGMI_LINK_RATE_23 = 23, // 23Gbps 536 XGMI_LINK_RATE_24 = 24, // 24Gbps 537 XGMI_LINK_RATE_25 = 25, // 25Gbps 538 XGMI_LINK_RATE_COUNT 539 } XGMI_LINK_RATE_e; 540 541 typedef enum { 542 XGMI_LINK_WIDTH_1 = 0, // x1 543 XGMI_LINK_WIDTH_2, // x2 544 XGMI_LINK_WIDTH_4, // x4 545 XGMI_LINK_WIDTH_8, // x8 546 XGMI_LINK_WIDTH_9, // x9 547 XGMI_LINK_WIDTH_16, // x16 548 XGMI_LINK_WIDTH_COUNT 549 } XGMI_LINK_WIDTH_e; 550 551 typedef struct { 552 uint8_t VoltageMode; // 0 - AVFS only, 1- min(AVFS,SS), 2-SS only 553 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 554 uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 555 uint8_t Padding; 556 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 557 QuadraticInt_t SsCurve; // Slow-slow curve (GHz->V) 558 uint16_t SsFmin; // Fmin for SS curve. If SS curve is selected, will use V@SSFmin for F <= Fmin 559 uint16_t Padding16; 560 } DpmDescriptor_t; 561 562 typedef enum { 563 PPT_THROTTLER_PPT0, 564 PPT_THROTTLER_PPT1, 565 PPT_THROTTLER_PPT2, 566 PPT_THROTTLER_PPT3, 567 PPT_THROTTLER_COUNT 568 } PPT_THROTTLER_e; 569 570 typedef enum { 571 TEMP_EDGE, 572 TEMP_HOTSPOT, 573 TEMP_MEM, 574 TEMP_VR_GFX, 575 TEMP_VR_MEM0, 576 TEMP_VR_MEM1, 577 TEMP_VR_SOC, 578 TEMP_LIQUID0, 579 TEMP_LIQUID1, 580 TEMP_PLX, 581 TEMP_COUNT, 582 } TEMP_e; 583 584 typedef enum { 585 TDC_THROTTLER_GFX, 586 TDC_THROTTLER_SOC, 587 TDC_THROTTLER_COUNT 588 } TDC_THROTTLER_e; 589 590 typedef enum { 591 CUSTOMER_VARIANT_ROW, 592 CUSTOMER_VARIANT_FALCON, 593 CUSTOMER_VARIANT_COUNT, 594 } CUSTOMER_VARIANT_e; 595 596 // Used for 2-step UCLK DPM change workaround 597 typedef struct { 598 uint16_t Fmin; 599 uint16_t Fmax; 600 } UclkDpmChangeRange_t; 601 602 typedef struct { 603 // MAJOR SECTION: SKU PARAMETERS 604 605 uint32_t Version; 606 607 // SECTION: Feature Enablement 608 uint32_t FeaturesToRun[NUM_FEATURES / 32]; 609 610 // SECTION: Infrastructure Limits 611 uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // Watts 612 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 613 uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // Watts 614 uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 615 616 uint16_t TdcLimit[TDC_THROTTLER_COUNT]; // Amps 617 uint16_t TdcLimitTau[TDC_THROTTLER_COUNT]; // Time constant of LPF in ms 618 619 uint16_t TemperatureLimit[TEMP_COUNT]; // Celcius 620 621 uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime) 622 623 // SECTION: Power Configuration 624 uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured. Use defines from PwrConfig_e 625 uint8_t TotalPowerPadding[3]; 626 627 // SECTION: APCC Settings 628 uint32_t ApccPlusResidencyLimit; 629 630 //SECTION: SMNCLK DPM 631 uint16_t SmnclkDpmFreq [NUM_SMNCLK_DPM_LEVELS]; // in MHz 632 uint16_t SmnclkDpmVoltage [NUM_SMNCLK_DPM_LEVELS]; // mV(Q2) 633 634 uint32_t PaddingAPCC; 635 uint16_t PerPartDroopVsetGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //In mV(Q2) 636 uint16_t PaddingPerPartDroop; 637 638 // SECTION: Throttler settings 639 uint32_t ThrottlerControlMask; // See Throtter masks defines 640 641 // SECTION: FW DSTATE Settings 642 uint32_t FwDStateMask; // See FW DState masks defines 643 644 // SECTION: ULV Settings 645 uint16_t UlvVoltageOffsetSoc; // In mV(Q2) 646 uint16_t UlvVoltageOffsetGfx; // In mV(Q2) 647 648 uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode 649 uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode 650 651 uint16_t SocLIVmin; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC 652 uint16_t PaddingLIVmin; 653 654 uint8_t GceaLinkMgrIdleThreshold; //Set by SMU FW during enablment of GFXOFF. Controls delay for GFX SDP port disconnection during idle events 655 uint8_t paddingRlcUlvParams[3]; 656 657 // SECTION: Voltage Control Parameters 658 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX 659 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC 660 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX 661 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC 662 663 uint16_t LoadLineResistanceGfx; // In mOhms with 8 fractional bits 664 uint16_t LoadLineResistanceSoc; // In mOhms with 8 fractional bits 665 666 // SECTION: Temperature Dependent Vmin 667 uint16_t VDDGFX_TVmin; //Celcius 668 uint16_t VDDSOC_TVmin; //Celcius 669 uint16_t VDDGFX_Vmin_HiTemp; // mV Q2 670 uint16_t VDDGFX_Vmin_LoTemp; // mV Q2 671 uint16_t VDDSOC_Vmin_HiTemp; // mV Q2 672 uint16_t VDDSOC_Vmin_LoTemp; // mV Q2 673 674 uint16_t VDDGFX_TVminHystersis; // Celcius 675 uint16_t VDDSOC_TVminHystersis; // Celcius 676 677 //SECTION: DPM Config 1 678 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 679 680 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 681 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 682 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 683 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 684 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 685 uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ]; // In MHz 686 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 687 uint16_t FreqTablePixclk [NUM_PIXCLK_DPM_LEVELS ]; // In MHz 688 uint16_t FreqTablePhyclk [NUM_PHYCLK_DPM_LEVELS ]; // In MHz 689 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 690 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 691 uint32_t Paddingclks; 692 693 DroopInt_t PerPartDroopModelGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //GHz ->Vstore in IEEE float format 694 695 uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 696 697 uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 698 699 // Used for MALL performance boost 700 uint16_t FclkBoostFreq; // In Mhz 701 uint16_t FclkParamPadding; 702 703 // SECTION: DPM Config 2 704 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 705 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 706 uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 707 uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 708 // GFXCLK DPM 709 uint16_t GfxclkFgfxoffEntry; // in Mhz 710 uint16_t GfxclkFinit; // in Mhz 711 uint16_t GfxclkFidle; // in MHz 712 uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL 713 uint8_t GfxclkPadding; 714 715 // GFX GPO 716 uint8_t GfxGpoSubFeatureMask; // bit 0 = PACE, bit 1 = DEM 717 uint8_t GfxGpoEnabledWorkPolicyMask; //Any policy that GPO can be enabled 718 uint8_t GfxGpoDisabledWorkPolicyMask; //Any policy that GPO can be disabled 719 uint8_t GfxGpoPadding[1]; 720 uint32_t GfxGpoVotingAllow; //For indicating which feature changes should result in a GPO table recalculation 721 722 uint32_t GfxGpoPadding32[4]; 723 724 uint16_t GfxDcsFopt; // Optimal GFXCLK for DCS in Mhz 725 uint16_t GfxDcsFclkFopt; // Optimal FCLK for DCS in Mhz 726 uint16_t GfxDcsUclkFopt; // Optimal UCLK for DCS in Mhz 727 728 uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase 729 730 uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase 731 uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. 732 733 uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS. 734 735 uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. 736 uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin. 737 738 uint32_t DcsParamPadding[5]; 739 740 uint16_t FlopsPerByteTable[RLC_PACE_TABLE_NUM_LEVELS]; // Q8.8 741 742 // UCLK section 743 uint8_t LowestUclkReservedForUlv; // Set this to 1 if UCLK DPM0 is reserved for ULV-mode only 744 uint8_t PaddingMem[3]; 745 746 uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 747 748 // Used for 2-Step UCLK change workaround 749 UclkDpmChangeRange_t UclkDpmSrcFreqRange; // In Mhz 750 UclkDpmChangeRange_t UclkDpmTargFreqRange; // In Mhz 751 uint16_t UclkDpmMidstepFreq; // In Mhz 752 uint16_t UclkMidstepPadding; 753 754 // Link DPM Settings 755 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 756 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 757 uint16_t LclkFreq[NUM_LINK_LEVELS]; 758 759 // SECTION: Fan Control 760 uint16_t FanStopTemp; //Celcius 761 uint16_t FanStartTemp; //Celcius 762 763 uint16_t FanGain[TEMP_COUNT]; 764 765 uint16_t FanPwmMin; 766 uint16_t FanAcousticLimitRpm; 767 uint16_t FanThrottlingRpm; 768 uint16_t FanMaximumRpm; 769 uint16_t MGpuFanBoostLimitRpm; 770 uint16_t FanTargetTemperature; 771 uint16_t FanTargetGfxclk; 772 uint16_t FanPadding16; 773 uint8_t FanTempInputSelect; 774 uint8_t FanPadding; 775 uint8_t FanZeroRpmEnable; 776 uint8_t FanTachEdgePerRev; 777 778 // The following are AFC override parameters. Leave at 0 to use FW defaults. 779 int16_t FuzzyFan_ErrorSetDelta; 780 int16_t FuzzyFan_ErrorRateSetDelta; 781 int16_t FuzzyFan_PwmSetDelta; 782 uint16_t FuzzyFan_Reserved; 783 784 // SECTION: AVFS 785 // Overrides 786 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 787 uint8_t dBtcGbGfxDfllModelSelect; //0 -> fused piece-wise model, 1 -> piece-wise linear(PPTable), 2 -> quadratic model(PPTable) 788 uint8_t Padding8_Avfs; 789 790 QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve 791 DroopInt_t dBtcGbGfxPll; // GHz->V BtcGb 792 DroopInt_t dBtcGbGfxDfll; // GHz->V BtcGb 793 DroopInt_t dBtcGbSoc; // GHz->V BtcGb 794 LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V 795 796 PiecewiseLinearDroopInt_t PiecewiseLinearDroopIntGfxDfll; //GHz ->Vstore in IEEE float format 797 798 QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V 799 800 uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2 801 802 uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT]; 803 uint8_t Padding8_GfxBtc[2]; 804 805 uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; // mV Q2 806 uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT]; // mV Q2 807 808 uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT]; // mV Q2 809 810 // SECTION: XGMI 811 uint8_t XgmiDpmPstates[NUM_XGMI_LEVELS]; // 2 DPM states, high and low. 0-P0, 1-P1, 2-P2, 3-P3. 812 uint8_t XgmiDpmSpare[2]; 813 814 // SECTION: Advanced Options 815 uint32_t DebugOverrides; 816 QuadraticInt_t ReservedEquation0; 817 QuadraticInt_t ReservedEquation1; 818 QuadraticInt_t ReservedEquation2; 819 QuadraticInt_t ReservedEquation3; 820 821 // SECTION: Sku Reserved 822 uint8_t CustomerVariant; 823 824 //VC BTC parameters are only applicable to VDD_GFX domain 825 uint8_t VcBtcEnabled; 826 uint16_t VcBtcVminT0; // T0_VMIN 827 uint16_t VcBtcFixedVminAgingOffset; // FIXED_VMIN_AGING_OFFSET 828 uint16_t VcBtcVmin2PsmDegrationGb; // VMIN_TO_PSM_DEGRADATION_GB 829 uint32_t VcBtcPsmA; // A_PSM 830 uint32_t VcBtcPsmB; // B_PSM 831 uint32_t VcBtcVminA; // A_VMIN 832 uint32_t VcBtcVminB; // B_VMIN 833 834 //GPIO Board feature 835 uint16_t LedGpio; //GeneriA GPIO flag used to control the radeon LEDs 836 uint16_t GfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages 837 838 uint32_t SkuReserved[8]; 839 840 841 // MAJOR SECTION: BOARD PARAMETERS 842 843 //SECTION: Gaming Clocks 844 uint32_t GamingClk[6]; 845 846 // SECTION: I2C Control 847 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 848 849 uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1 850 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1 851 uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off 852 uint8_t I2cSpare[1]; 853 854 // SECTION: SVI2 Board Parameters 855 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 856 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 857 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 858 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 859 860 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 861 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 862 uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 863 uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 864 865 // SECTION: Telemetry Settings 866 uint16_t GfxMaxCurrent; // in Amps 867 int8_t GfxOffset; // in Amps 868 uint8_t Padding_TelemetryGfx; 869 870 uint16_t SocMaxCurrent; // in Amps 871 int8_t SocOffset; // in Amps 872 uint8_t Padding_TelemetrySoc; 873 874 uint16_t Mem0MaxCurrent; // in Amps 875 int8_t Mem0Offset; // in Amps 876 uint8_t Padding_TelemetryMem0; 877 878 uint16_t Mem1MaxCurrent; // in Amps 879 int8_t Mem1Offset; // in Amps 880 uint8_t Padding_TelemetryMem1; 881 882 uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 883 884 // SECTION: GPIO Settings 885 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 886 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 887 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 888 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 889 890 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 891 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 892 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 893 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 894 895 // LED Display Settings 896 uint8_t LedPin0; // GPIO number for LedPin[0] 897 uint8_t LedPin1; // GPIO number for LedPin[1] 898 uint8_t LedPin2; // GPIO number for LedPin[2] 899 uint8_t LedEnableMask; 900 901 uint8_t LedPcie; // GPIO number for PCIE results 902 uint8_t LedError; // GPIO number for Error Cases 903 uint8_t LedSpare1[2]; 904 905 // SECTION: Clock Spread Spectrum 906 907 // GFXCLK PLL Spread Spectrum 908 uint8_t PllGfxclkSpreadEnabled; // on or off 909 uint8_t PllGfxclkSpreadPercent; // Q4.4 910 uint16_t PllGfxclkSpreadFreq; // kHz 911 912 // GFXCLK DFLL Spread Spectrum 913 uint8_t DfllGfxclkSpreadEnabled; // on or off 914 uint8_t DfllGfxclkSpreadPercent; // Q4.4 915 uint16_t DfllGfxclkSpreadFreq; // kHz 916 917 // UCLK Spread Spectrum 918 uint16_t UclkSpreadPadding; 919 uint16_t UclkSpreadFreq; // kHz 920 921 // FCLK Spread Spectrum 922 uint8_t FclkSpreadEnabled; // on or off 923 uint8_t FclkSpreadPercent; // Q4.4 924 uint16_t FclkSpreadFreq; // kHz 925 926 // Section: Memory Config 927 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. 928 929 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines 930 uint8_t PaddingMem1[3]; 931 932 // Section: Total Board Power 933 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 934 uint16_t BoardPowerPadding; 935 936 // SECTION: XGMI Training 937 uint8_t XgmiLinkSpeed [NUM_XGMI_PSTATE_LEVELS]; 938 uint8_t XgmiLinkWidth [NUM_XGMI_PSTATE_LEVELS]; 939 940 uint16_t XgmiFclkFreq [NUM_XGMI_PSTATE_LEVELS]; 941 uint16_t XgmiSocVoltage [NUM_XGMI_PSTATE_LEVELS]; 942 943 // SECTION: UMC feature flags 944 uint8_t HsrEnabled; 945 uint8_t VddqOffEnabled; 946 uint8_t PaddingUmcFlags[2]; 947 948 // UCLK Spread Spectrum 949 uint8_t UclkSpreadPercent[16]; 950 951 // SECTION: Board Reserved 952 uint32_t BoardReserved[11]; 953 954 // SECTION: Structure Padding 955 956 // Padding for MMHUB - do not modify this 957 uint32_t MmHubPadding[8]; // SMU internal use 958 959 } PPTable_t; 960 961 typedef struct { 962 // MAJOR SECTION: SKU PARAMETERS 963 964 uint32_t Version; 965 966 // SECTION: Feature Enablement 967 uint32_t FeaturesToRun[NUM_FEATURES / 32]; 968 969 // SECTION: Infrastructure Limits 970 uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // Watts 971 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 972 uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // Watts 973 uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 974 975 uint16_t TdcLimit[TDC_THROTTLER_COUNT]; // Amps 976 uint16_t TdcLimitTau[TDC_THROTTLER_COUNT]; // Time constant of LPF in ms 977 978 uint16_t TemperatureLimit[TEMP_COUNT]; // Celcius 979 980 uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime) 981 982 // SECTION: Power Configuration 983 uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured. Use defines from PwrConfig_e 984 uint8_t TotalPowerPadding[3]; 985 986 // SECTION: APCC Settings 987 uint32_t ApccPlusResidencyLimit; 988 989 //SECTION: SMNCLK DPM 990 uint16_t SmnclkDpmFreq [NUM_SMNCLK_DPM_LEVELS]; // in MHz 991 uint16_t SmnclkDpmVoltage [NUM_SMNCLK_DPM_LEVELS]; // mV(Q2) 992 993 uint32_t PaddingAPCC; 994 uint16_t PerPartDroopVsetGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //In mV(Q2) 995 uint16_t PaddingPerPartDroop; 996 997 // SECTION: Throttler settings 998 uint32_t ThrottlerControlMask; // See Throtter masks defines 999 1000 // SECTION: FW DSTATE Settings 1001 uint32_t FwDStateMask; // See FW DState masks defines 1002 1003 // SECTION: ULV Settings 1004 uint16_t UlvVoltageOffsetSoc; // In mV(Q2) 1005 uint16_t UlvVoltageOffsetGfx; // In mV(Q2) 1006 1007 uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode 1008 uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode 1009 1010 uint16_t SocLIVmin; 1011 uint16_t SocLIVminoffset; 1012 1013 uint8_t GceaLinkMgrIdleThreshold; //Set by SMU FW during enablment of GFXOFF. Controls delay for GFX SDP port disconnection during idle events 1014 uint8_t paddingRlcUlvParams[3]; 1015 1016 // SECTION: Voltage Control Parameters 1017 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX 1018 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC 1019 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX 1020 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC 1021 1022 uint16_t LoadLineResistanceGfx; // In mOhms with 8 fractional bits 1023 uint16_t LoadLineResistanceSoc; // In mOhms with 8 fractional bits 1024 1025 // SECTION: Temperature Dependent Vmin 1026 uint16_t VDDGFX_TVmin; //Celcius 1027 uint16_t VDDSOC_TVmin; //Celcius 1028 uint16_t VDDGFX_Vmin_HiTemp; // mV Q2 1029 uint16_t VDDGFX_Vmin_LoTemp; // mV Q2 1030 uint16_t VDDSOC_Vmin_HiTemp; // mV Q2 1031 uint16_t VDDSOC_Vmin_LoTemp; // mV Q2 1032 1033 uint16_t VDDGFX_TVminHystersis; // Celcius 1034 uint16_t VDDSOC_TVminHystersis; // Celcius 1035 1036 //SECTION: DPM Config 1 1037 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 1038 1039 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1040 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1041 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1042 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1043 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1044 uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ]; // In MHz 1045 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1046 uint16_t FreqTablePixclk [NUM_PIXCLK_DPM_LEVELS ]; // In MHz 1047 uint16_t FreqTablePhyclk [NUM_PHYCLK_DPM_LEVELS ]; // In MHz 1048 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1049 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1050 uint32_t Paddingclks; 1051 1052 DroopInt_t PerPartDroopModelGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //GHz ->Vstore in IEEE float format 1053 1054 uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1055 1056 uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 1057 1058 // Used for MALL performance boost 1059 uint16_t FclkBoostFreq; // In Mhz 1060 uint16_t FclkParamPadding; 1061 1062 // SECTION: DPM Config 2 1063 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 1064 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 1065 uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1066 uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1067 // GFXCLK DPM 1068 uint16_t GfxclkFgfxoffEntry; // in Mhz 1069 uint16_t GfxclkFinit; // in Mhz 1070 uint16_t GfxclkFidle; // in MHz 1071 uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL 1072 uint8_t GfxclkPadding; 1073 1074 // GFX GPO 1075 uint8_t GfxGpoSubFeatureMask; // bit 0 = PACE, bit 1 = DEM 1076 uint8_t GfxGpoEnabledWorkPolicyMask; //Any policy that GPO can be enabled 1077 uint8_t GfxGpoDisabledWorkPolicyMask; //Any policy that GPO can be disabled 1078 uint8_t GfxGpoPadding[1]; 1079 uint32_t GfxGpoVotingAllow; //For indicating which feature changes should result in a GPO table recalculation 1080 1081 uint32_t GfxGpoPadding32[4]; 1082 1083 uint16_t GfxDcsFopt; // Optimal GFXCLK for DCS in Mhz 1084 uint16_t GfxDcsFclkFopt; // Optimal FCLK for DCS in Mhz 1085 uint16_t GfxDcsUclkFopt; // Optimal UCLK for DCS in Mhz 1086 1087 uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase 1088 1089 uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase 1090 uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. 1091 1092 uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS. 1093 1094 uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. 1095 uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin. 1096 1097 uint32_t DcsParamPadding[5]; 1098 1099 uint16_t FlopsPerByteTable[RLC_PACE_TABLE_NUM_LEVELS]; // Q8.8 1100 1101 // UCLK section 1102 uint8_t LowestUclkReservedForUlv; // Set this to 1 if UCLK DPM0 is reserved for ULV-mode only 1103 uint8_t PaddingMem[3]; 1104 1105 uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 1106 1107 // Used for 2-Step UCLK change workaround 1108 UclkDpmChangeRange_t UclkDpmSrcFreqRange; // In Mhz 1109 UclkDpmChangeRange_t UclkDpmTargFreqRange; // In Mhz 1110 uint16_t UclkDpmMidstepFreq; // In Mhz 1111 uint16_t UclkMidstepPadding; 1112 1113 // Link DPM Settings 1114 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 1115 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 1116 uint16_t LclkFreq[NUM_LINK_LEVELS]; 1117 1118 // SECTION: Fan Control 1119 uint16_t FanStopTemp; //Celcius 1120 uint16_t FanStartTemp; //Celcius 1121 1122 uint16_t FanGain[TEMP_COUNT]; 1123 1124 uint16_t FanPwmMin; 1125 uint16_t FanAcousticLimitRpm; 1126 uint16_t FanThrottlingRpm; 1127 uint16_t FanMaximumRpm; 1128 uint16_t MGpuFanBoostLimitRpm; 1129 uint16_t FanTargetTemperature; 1130 uint16_t FanTargetGfxclk; 1131 uint16_t FanPadding16; 1132 uint8_t FanTempInputSelect; 1133 uint8_t FanPadding; 1134 uint8_t FanZeroRpmEnable; 1135 uint8_t FanTachEdgePerRev; 1136 1137 // The following are AFC override parameters. Leave at 0 to use FW defaults. 1138 int16_t FuzzyFan_ErrorSetDelta; 1139 int16_t FuzzyFan_ErrorRateSetDelta; 1140 int16_t FuzzyFan_PwmSetDelta; 1141 uint16_t FuzzyFan_Reserved; 1142 1143 // SECTION: AVFS 1144 // Overrides 1145 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 1146 uint8_t dBtcGbGfxDfllModelSelect; //0 -> fused piece-wise model, 1 -> piece-wise linear(PPTable), 2 -> quadratic model(PPTable) 1147 uint8_t Padding8_Avfs; 1148 1149 QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve 1150 DroopInt_t dBtcGbGfxPll; // GHz->V BtcGb 1151 DroopInt_t dBtcGbGfxDfll; // GHz->V BtcGb 1152 DroopInt_t dBtcGbSoc; // GHz->V BtcGb 1153 LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V 1154 1155 PiecewiseLinearDroopInt_t PiecewiseLinearDroopIntGfxDfll; //GHz ->Vstore in IEEE float format 1156 1157 QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V 1158 1159 uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2 1160 1161 uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT]; 1162 uint8_t Padding8_GfxBtc[2]; 1163 1164 uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; // mV Q2 1165 uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT]; // mV Q2 1166 1167 uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT]; // mV Q2 1168 1169 // SECTION: XGMI 1170 uint8_t XgmiDpmPstates[NUM_XGMI_LEVELS]; // 2 DPM states, high and low. 0-P0, 1-P1, 2-P2, 3-P3. 1171 uint8_t XgmiDpmSpare[2]; 1172 1173 // SECTION: Advanced Options 1174 uint32_t DebugOverrides; 1175 QuadraticInt_t ReservedEquation0; 1176 QuadraticInt_t ReservedEquation1; 1177 QuadraticInt_t ReservedEquation2; 1178 QuadraticInt_t ReservedEquation3; 1179 1180 // SECTION: Sku Reserved 1181 uint8_t CustomerVariant; 1182 1183 //VC BTC parameters are only applicable to VDD_GFX domain 1184 uint8_t VcBtcEnabled; 1185 uint16_t VcBtcVminT0; // T0_VMIN 1186 uint16_t VcBtcFixedVminAgingOffset; // FIXED_VMIN_AGING_OFFSET 1187 uint16_t VcBtcVmin2PsmDegrationGb; // VMIN_TO_PSM_DEGRADATION_GB 1188 uint32_t VcBtcPsmA; // A_PSM 1189 uint32_t VcBtcPsmB; // B_PSM 1190 uint32_t VcBtcVminA; // A_VMIN 1191 uint32_t VcBtcVminB; // B_VMIN 1192 1193 //GPIO Board feature 1194 uint16_t LedGpio; //GeneriA GPIO flag used to control the radeon LEDs 1195 uint16_t GfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages 1196 1197 uint32_t SkuReserved[63]; 1198 1199 1200 1201 // MAJOR SECTION: BOARD PARAMETERS 1202 1203 //SECTION: Gaming Clocks 1204 uint32_t GamingClk[6]; 1205 1206 // SECTION: I2C Control 1207 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 1208 1209 uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1 1210 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1 1211 uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off 1212 uint8_t I2cSpare[1]; 1213 1214 // SECTION: SVI2 Board Parameters 1215 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 1216 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 1217 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 1218 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 1219 1220 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1221 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1222 uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1223 uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1224 1225 // SECTION: Telemetry Settings 1226 uint16_t GfxMaxCurrent; // in Amps 1227 int8_t GfxOffset; // in Amps 1228 uint8_t Padding_TelemetryGfx; 1229 1230 uint16_t SocMaxCurrent; // in Amps 1231 int8_t SocOffset; // in Amps 1232 uint8_t Padding_TelemetrySoc; 1233 1234 uint16_t Mem0MaxCurrent; // in Amps 1235 int8_t Mem0Offset; // in Amps 1236 uint8_t Padding_TelemetryMem0; 1237 1238 uint16_t Mem1MaxCurrent; // in Amps 1239 int8_t Mem1Offset; // in Amps 1240 uint8_t Padding_TelemetryMem1; 1241 1242 uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 1243 1244 // SECTION: GPIO Settings 1245 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 1246 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 1247 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 1248 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 1249 1250 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 1251 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 1252 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 1253 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 1254 1255 // LED Display Settings 1256 uint8_t LedPin0; // GPIO number for LedPin[0] 1257 uint8_t LedPin1; // GPIO number for LedPin[1] 1258 uint8_t LedPin2; // GPIO number for LedPin[2] 1259 uint8_t LedEnableMask; 1260 1261 uint8_t LedPcie; // GPIO number for PCIE results 1262 uint8_t LedError; // GPIO number for Error Cases 1263 uint8_t LedSpare1[2]; 1264 1265 // SECTION: Clock Spread Spectrum 1266 1267 // GFXCLK PLL Spread Spectrum 1268 uint8_t PllGfxclkSpreadEnabled; // on or off 1269 uint8_t PllGfxclkSpreadPercent; // Q4.4 1270 uint16_t PllGfxclkSpreadFreq; // kHz 1271 1272 // GFXCLK DFLL Spread Spectrum 1273 uint8_t DfllGfxclkSpreadEnabled; // on or off 1274 uint8_t DfllGfxclkSpreadPercent; // Q4.4 1275 uint16_t DfllGfxclkSpreadFreq; // kHz 1276 1277 // UCLK Spread Spectrum 1278 uint16_t UclkSpreadPadding; 1279 uint16_t UclkSpreadFreq; // kHz 1280 1281 // FCLK Spread Spectrum 1282 uint8_t FclkSpreadEnabled; // on or off 1283 uint8_t FclkSpreadPercent; // Q4.4 1284 uint16_t FclkSpreadFreq; // kHz 1285 1286 // Section: Memory Config 1287 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. 1288 1289 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines 1290 uint8_t PaddingMem1[3]; 1291 1292 // Section: Total Board Power 1293 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 1294 uint16_t BoardPowerPadding; 1295 1296 // SECTION: XGMI Training 1297 uint8_t XgmiLinkSpeed [NUM_XGMI_PSTATE_LEVELS]; 1298 uint8_t XgmiLinkWidth [NUM_XGMI_PSTATE_LEVELS]; 1299 1300 uint16_t XgmiFclkFreq [NUM_XGMI_PSTATE_LEVELS]; 1301 uint16_t XgmiSocVoltage [NUM_XGMI_PSTATE_LEVELS]; 1302 1303 // SECTION: UMC feature flags 1304 uint8_t HsrEnabled; 1305 uint8_t VddqOffEnabled; 1306 uint8_t PaddingUmcFlags[2]; 1307 1308 // UCLK Spread Spectrum 1309 uint8_t UclkSpreadPercent[16]; 1310 1311 // SECTION: Board Reserved 1312 uint32_t BoardReserved[11]; 1313 1314 // SECTION: Structure Padding 1315 1316 // Padding for MMHUB - do not modify this 1317 uint32_t MmHubPadding[8]; // SMU internal use 1318 1319 1320 } PPTable_beige_goby_t; 1321 1322 typedef struct { 1323 // Time constant parameters for clock averages in ms 1324 uint16_t GfxclkAverageLpfTau; 1325 uint16_t FclkAverageLpfTau; 1326 uint16_t UclkAverageLpfTau; 1327 uint16_t GfxActivityLpfTau; 1328 uint16_t UclkActivityLpfTau; 1329 uint16_t SocketPowerLpfTau; 1330 uint16_t VcnClkAverageLpfTau; 1331 uint16_t padding16; 1332 } DriverSmuConfig_t; 1333 1334 typedef struct { 1335 DriverSmuConfig_t DriverSmuConfig; 1336 1337 uint32_t Spare[7]; 1338 // Padding - ignore 1339 uint32_t MmHubPadding[8]; // SMU internal use 1340 } DriverSmuConfigExternal_t; 1341 1342 typedef struct { 1343 uint16_t GfxclkFmin; // MHz 1344 uint16_t GfxclkFmax; // MHz 1345 QuadraticInt_t CustomGfxVfCurve; // a: mV/MHz^2, b: mv/MHz, c: mV 1346 uint16_t CustomCurveFmin; // MHz 1347 uint16_t UclkFmin; // MHz 1348 uint16_t UclkFmax; // MHz 1349 int16_t OverDrivePct; // % 1350 uint16_t FanMaximumRpm; 1351 uint16_t FanMinimumPwm; 1352 uint16_t FanAcousticLimitRpm; 1353 uint16_t FanTargetTemperature; // Degree Celcius 1354 uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS]; 1355 uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS]; 1356 uint16_t MaxOpTemp; // Degree Celcius 1357 int16_t VddGfxOffset; // in mV 1358 uint8_t FanZeroRpmEnable; 1359 uint8_t FanZeroRpmStopTemp; 1360 uint8_t FanMode; 1361 uint8_t Padding[1]; 1362 } OverDriveTable_t; 1363 1364 typedef struct { 1365 OverDriveTable_t OverDriveTable; 1366 uint32_t Spare[8]; 1367 1368 uint32_t MmHubPadding[8]; // SMU internal use 1369 } OverDriveTableExternal_t; 1370 1371 typedef struct { 1372 uint32_t CurrClock[PPCLK_COUNT]; 1373 1374 uint16_t AverageGfxclkFrequencyPreDs; 1375 uint16_t AverageGfxclkFrequencyPostDs; 1376 uint16_t AverageFclkFrequencyPreDs; 1377 uint16_t AverageFclkFrequencyPostDs; 1378 uint16_t AverageUclkFrequencyPreDs ; 1379 uint16_t AverageUclkFrequencyPostDs ; 1380 1381 1382 uint16_t AverageGfxActivity ; 1383 uint16_t AverageUclkActivity ; 1384 uint8_t CurrSocVoltageOffset ; 1385 uint8_t CurrGfxVoltageOffset ; 1386 uint8_t CurrMemVidOffset ; 1387 uint8_t Padding8 ; 1388 uint16_t AverageSocketPower ; 1389 uint16_t TemperatureEdge ; 1390 uint16_t TemperatureHotspot ; 1391 uint16_t TemperatureMem ; 1392 uint16_t TemperatureVrGfx ; 1393 uint16_t TemperatureVrMem0 ; 1394 uint16_t TemperatureVrMem1 ; 1395 uint16_t TemperatureVrSoc ; 1396 uint16_t TemperatureLiquid0 ; 1397 uint16_t TemperatureLiquid1 ; 1398 uint16_t TemperaturePlx ; 1399 uint16_t Padding16 ; 1400 uint32_t ThrottlerStatus ; 1401 1402 uint8_t LinkDpmLevel; 1403 uint8_t CurrFanPwm; 1404 uint16_t CurrFanSpeed; 1405 1406 //BACO metrics, PMFW-1721 1407 //metrics for D3hot entry/exit and driver ARM msgs 1408 uint8_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; 1409 uint8_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT]; 1410 uint8_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT]; 1411 1412 //PMFW-4362 1413 uint32_t EnergyAccumulator; 1414 uint16_t AverageVclk0Frequency ; 1415 uint16_t AverageDclk0Frequency ; 1416 uint16_t AverageVclk1Frequency ; 1417 uint16_t AverageDclk1Frequency ; 1418 uint16_t VcnActivityPercentage ; //place holder, David N. to provide full sequence 1419 uint8_t PcieRate ; 1420 uint8_t PcieWidth ; 1421 uint16_t AverageGfxclkFrequencyTarget; 1422 uint16_t Padding16_2; 1423 1424 } SmuMetrics_t; 1425 1426 typedef struct { 1427 uint32_t CurrClock[PPCLK_COUNT]; 1428 1429 uint16_t AverageGfxclkFrequencyPreDs; 1430 uint16_t AverageGfxclkFrequencyPostDs; 1431 uint16_t AverageFclkFrequencyPreDs; 1432 uint16_t AverageFclkFrequencyPostDs; 1433 uint16_t AverageUclkFrequencyPreDs ; 1434 uint16_t AverageUclkFrequencyPostDs ; 1435 1436 1437 uint16_t AverageGfxActivity ; 1438 uint16_t AverageUclkActivity ; 1439 uint8_t CurrSocVoltageOffset ; 1440 uint8_t CurrGfxVoltageOffset ; 1441 uint8_t CurrMemVidOffset ; 1442 uint8_t Padding8 ; 1443 uint16_t AverageSocketPower ; 1444 uint16_t TemperatureEdge ; 1445 uint16_t TemperatureHotspot ; 1446 uint16_t TemperatureMem ; 1447 uint16_t TemperatureVrGfx ; 1448 uint16_t TemperatureVrMem0 ; 1449 uint16_t TemperatureVrMem1 ; 1450 uint16_t TemperatureVrSoc ; 1451 uint16_t TemperatureLiquid0 ; 1452 uint16_t TemperatureLiquid1 ; 1453 uint16_t TemperaturePlx ; 1454 uint16_t Padding16 ; 1455 uint32_t AccCnt ; 1456 uint8_t ThrottlingPercentage[THROTTLER_COUNT]; 1457 1458 1459 uint8_t LinkDpmLevel; 1460 uint8_t CurrFanPwm; 1461 uint16_t CurrFanSpeed; 1462 1463 //BACO metrics, PMFW-1721 1464 //metrics for D3hot entry/exit and driver ARM msgs 1465 uint8_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; 1466 uint8_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT]; 1467 uint8_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT]; 1468 1469 //PMFW-4362 1470 uint32_t EnergyAccumulator; 1471 uint16_t AverageVclk0Frequency ; 1472 uint16_t AverageDclk0Frequency ; 1473 uint16_t AverageVclk1Frequency ; 1474 uint16_t AverageDclk1Frequency ; 1475 uint16_t VcnActivityPercentage ; //place holder, David N. to provide full sequence 1476 uint8_t PcieRate ; 1477 uint8_t PcieWidth ; 1478 uint16_t AverageGfxclkFrequencyTarget; 1479 uint16_t Padding16_2; 1480 1481 } SmuMetrics_V2_t; 1482 1483 typedef struct { 1484 uint32_t CurrClock[PPCLK_COUNT]; 1485 1486 uint16_t AverageGfxclkFrequencyPreDs; 1487 uint16_t AverageGfxclkFrequencyPostDs; 1488 uint16_t AverageFclkFrequencyPreDs; 1489 uint16_t AverageFclkFrequencyPostDs; 1490 uint16_t AverageUclkFrequencyPreDs; 1491 uint16_t AverageUclkFrequencyPostDs; 1492 1493 1494 uint16_t AverageGfxActivity; 1495 uint16_t AverageUclkActivity; 1496 uint8_t CurrSocVoltageOffset; 1497 uint8_t CurrGfxVoltageOffset; 1498 uint8_t CurrMemVidOffset; 1499 uint8_t Padding8; 1500 uint16_t AverageSocketPower; 1501 uint16_t TemperatureEdge; 1502 uint16_t TemperatureHotspot; 1503 uint16_t TemperatureMem; 1504 uint16_t TemperatureVrGfx; 1505 uint16_t TemperatureVrMem0; 1506 uint16_t TemperatureVrMem1; 1507 uint16_t TemperatureVrSoc; 1508 uint16_t TemperatureLiquid0; 1509 uint16_t TemperatureLiquid1; 1510 uint16_t TemperaturePlx; 1511 uint16_t Padding16; 1512 uint32_t AccCnt; 1513 uint8_t ThrottlingPercentage[THROTTLER_COUNT]; 1514 1515 1516 uint8_t LinkDpmLevel; 1517 uint8_t CurrFanPwm; 1518 uint16_t CurrFanSpeed; 1519 1520 //BACO metrics, PMFW-1721 1521 //metrics for D3hot entry/exit and driver ARM msgs 1522 uint8_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; 1523 uint8_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT]; 1524 uint8_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT]; 1525 1526 //PMFW-4362 1527 uint32_t EnergyAccumulator; 1528 uint16_t AverageVclk0Frequency; 1529 uint16_t AverageDclk0Frequency; 1530 uint16_t AverageVclk1Frequency; 1531 uint16_t AverageDclk1Frequency; 1532 uint16_t VcnUsagePercentage0; 1533 uint16_t VcnUsagePercentage1; 1534 uint8_t PcieRate; 1535 uint8_t PcieWidth; 1536 uint16_t AverageGfxclkFrequencyTarget; 1537 1538 } SmuMetrics_V3_t; 1539 1540 typedef struct { 1541 union { 1542 SmuMetrics_t SmuMetrics; 1543 SmuMetrics_V2_t SmuMetrics_V2; 1544 SmuMetrics_V3_t SmuMetrics_V3; 1545 }; 1546 uint32_t Spare[1]; 1547 1548 // Padding - ignore 1549 uint32_t MmHubPadding[8]; // SMU internal use 1550 } SmuMetricsExternal_t; 1551 1552 typedef struct { 1553 uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz) 1554 uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz) 1555 uint16_t MinUclk; 1556 uint16_t MaxUclk; 1557 1558 uint8_t WmSetting; 1559 uint8_t Flags; 1560 uint8_t Padding[2]; 1561 1562 } WatermarkRowGeneric_t; 1563 1564 #define NUM_WM_RANGES 4 1565 1566 typedef enum { 1567 WM_SOCCLK = 0, 1568 WM_DCEFCLK, 1569 WM_COUNT, 1570 } WM_CLOCK_e; 1571 1572 typedef enum { 1573 WATERMARKS_CLOCK_RANGE = 0, 1574 WATERMARKS_DUMMY_PSTATE, 1575 WATERMARKS_MALL, 1576 WATERMARKS_COUNT, 1577 } WATERMARKS_FLAGS_e; 1578 1579 typedef struct { 1580 // Watermarks 1581 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; 1582 } Watermarks_t; 1583 1584 typedef struct { 1585 Watermarks_t Watermarks; 1586 1587 uint32_t MmHubPadding[8]; // SMU internal use 1588 } WatermarksExternal_t; 1589 1590 typedef struct { 1591 uint16_t avgPsmCount[67]; 1592 uint16_t minPsmCount[67]; 1593 float avgPsmVoltage[67]; 1594 float minPsmVoltage[67]; 1595 } AvfsDebugTable_t; 1596 1597 typedef struct { 1598 AvfsDebugTable_t AvfsDebugTable; 1599 1600 uint32_t MmHubPadding[8]; // SMU internal use 1601 } AvfsDebugTableExternal_t; 1602 1603 typedef struct { 1604 uint8_t AvfsVersion; 1605 uint8_t Padding; 1606 1607 uint8_t AvfsEn[AVFS_VOLTAGE_COUNT]; 1608 1609 uint8_t OverrideVFT[AVFS_VOLTAGE_COUNT]; 1610 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 1611 1612 uint8_t OverrideTemperatures[AVFS_VOLTAGE_COUNT]; 1613 uint8_t OverrideVInversion[AVFS_VOLTAGE_COUNT]; 1614 uint8_t OverrideP2V[AVFS_VOLTAGE_COUNT]; 1615 uint8_t OverrideP2VCharzFreq[AVFS_VOLTAGE_COUNT]; 1616 1617 int32_t VFT0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1618 int32_t VFT0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1619 int32_t VFT0_b[AVFS_VOLTAGE_COUNT]; // Q32 1620 1621 int32_t VFT1_m1[AVFS_VOLTAGE_COUNT]; // Q8.16 1622 int32_t VFT1_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1623 int32_t VFT1_b[AVFS_VOLTAGE_COUNT]; // Q32 1624 1625 int32_t VFT2_m1[AVFS_VOLTAGE_COUNT]; // Q8.16 1626 int32_t VFT2_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1627 int32_t VFT2_b[AVFS_VOLTAGE_COUNT]; // Q32 1628 1629 int32_t AvfsGb0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1630 int32_t AvfsGb0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1631 int32_t AvfsGb0_b[AVFS_VOLTAGE_COUNT]; // Q32 1632 1633 int32_t AcBtcGb_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1634 int32_t AcBtcGb_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1635 int32_t AcBtcGb_b[AVFS_VOLTAGE_COUNT]; // Q32 1636 1637 uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT]; 1638 uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT]; 1639 uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT]; 1640 1641 uint32_t VInversion[AVFS_VOLTAGE_COUNT]; // in mV with 2 fractional bits 1642 1643 1644 int32_t P2V_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1645 int32_t P2V_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1646 int32_t P2V_b[AVFS_VOLTAGE_COUNT]; // Q32 1647 1648 uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; // in 10KHz units 1649 1650 uint32_t EnabledAvfsModules[3]; //Sienna_Cichlid - 67 AVFS modules 1651 } AvfsFuseOverride_t; 1652 1653 typedef struct { 1654 AvfsFuseOverride_t AvfsFuseOverride; 1655 1656 uint32_t MmHubPadding[8]; // SMU internal use 1657 } AvfsFuseOverrideExternal_t; 1658 1659 typedef struct { 1660 uint8_t Gfx_ActiveHystLimit; 1661 uint8_t Gfx_IdleHystLimit; 1662 uint8_t Gfx_FPS; 1663 uint8_t Gfx_MinActiveFreqType; 1664 uint8_t Gfx_BoosterFreqType; 1665 uint8_t Gfx_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 1666 uint16_t Gfx_MinActiveFreq; // MHz 1667 uint16_t Gfx_BoosterFreq; // MHz 1668 uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms 1669 uint32_t Gfx_PD_Data_limit_a; // Q16 1670 uint32_t Gfx_PD_Data_limit_b; // Q16 1671 uint32_t Gfx_PD_Data_limit_c; // Q16 1672 uint32_t Gfx_PD_Data_error_coeff; // Q16 1673 uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 1674 1675 uint8_t Fclk_ActiveHystLimit; 1676 uint8_t Fclk_IdleHystLimit; 1677 uint8_t Fclk_FPS; 1678 uint8_t Fclk_MinActiveFreqType; 1679 uint8_t Fclk_BoosterFreqType; 1680 uint8_t Fclk_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 1681 uint16_t Fclk_MinActiveFreq; // MHz 1682 uint16_t Fclk_BoosterFreq; // MHz 1683 uint16_t Fclk_PD_Data_time_constant; // Time constant of PD controller in ms 1684 uint32_t Fclk_PD_Data_limit_a; // Q16 1685 uint32_t Fclk_PD_Data_limit_b; // Q16 1686 uint32_t Fclk_PD_Data_limit_c; // Q16 1687 uint32_t Fclk_PD_Data_error_coeff; // Q16 1688 uint32_t Fclk_PD_Data_error_rate_coeff; // Q16 1689 1690 uint8_t Mem_ActiveHystLimit; 1691 uint8_t Mem_IdleHystLimit; 1692 uint8_t Mem_FPS; 1693 uint8_t Mem_MinActiveFreqType; 1694 uint8_t Mem_BoosterFreqType; 1695 uint8_t Mem_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 1696 uint16_t Mem_MinActiveFreq; // MHz 1697 uint16_t Mem_BoosterFreq; // MHz 1698 uint16_t Mem_PD_Data_time_constant; // Time constant of PD controller in ms 1699 uint32_t Mem_PD_Data_limit_a; // Q16 1700 uint32_t Mem_PD_Data_limit_b; // Q16 1701 uint32_t Mem_PD_Data_limit_c; // Q16 1702 uint32_t Mem_PD_Data_error_coeff; // Q16 1703 uint32_t Mem_PD_Data_error_rate_coeff; // Q16 1704 1705 uint32_t Mem_UpThreshold_Limit; // Q16 1706 uint8_t Mem_UpHystLimit; 1707 uint8_t Mem_DownHystLimit; 1708 uint16_t Mem_Fps; 1709 1710 } DpmActivityMonitorCoeffInt_t; 1711 1712 1713 typedef struct { 1714 DpmActivityMonitorCoeffInt_t DpmActivityMonitorCoeffInt; 1715 uint32_t MmHubPadding[8]; // SMU internal use 1716 } DpmActivityMonitorCoeffIntExternal_t; 1717 1718 // Workload bits 1719 #define WORKLOAD_PPLIB_DEFAULT_BIT 0 1720 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 1721 #define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 1722 #define WORKLOAD_PPLIB_VIDEO_BIT 3 1723 #define WORKLOAD_PPLIB_VR_BIT 4 1724 #define WORKLOAD_PPLIB_COMPUTE_BIT 5 1725 #define WORKLOAD_PPLIB_CUSTOM_BIT 6 1726 #define WORKLOAD_PPLIB_W3D_BIT 7 1727 #define WORKLOAD_PPLIB_COUNT 8 1728 1729 1730 // These defines are used with the following messages: 1731 // SMC_MSG_TransferTableDram2Smu 1732 // SMC_MSG_TransferTableSmu2Dram 1733 1734 // Table transfer status 1735 #define TABLE_TRANSFER_OK 0x0 1736 #define TABLE_TRANSFER_FAILED 0xFF 1737 1738 // Table types 1739 #define TABLE_PPTABLE 0 1740 #define TABLE_WATERMARKS 1 1741 #define TABLE_AVFS_PSM_DEBUG 2 1742 #define TABLE_AVFS_FUSE_OVERRIDE 3 1743 #define TABLE_PMSTATUSLOG 4 1744 #define TABLE_SMU_METRICS 5 1745 #define TABLE_DRIVER_SMU_CONFIG 6 1746 #define TABLE_ACTIVITY_MONITOR_COEFF 7 1747 #define TABLE_OVERDRIVE 8 1748 #define TABLE_I2C_COMMANDS 9 1749 #define TABLE_PACE 10 1750 #define TABLE_ECCINFO 11 1751 #define TABLE_COUNT 12 1752 1753 typedef struct { 1754 float FlopsPerByteTable[RLC_PACE_TABLE_NUM_LEVELS]; 1755 } RlcPaceFlopsPerByteOverride_t; 1756 1757 typedef struct { 1758 RlcPaceFlopsPerByteOverride_t RlcPaceFlopsPerByteOverride; 1759 1760 uint32_t MmHubPadding[8]; // SMU internal use 1761 } RlcPaceFlopsPerByteOverrideExternal_t; 1762 1763 // These defines are used with the SMC_MSG_SetUclkFastSwitch message. 1764 #define UCLK_SWITCH_SLOW 0 1765 #define UCLK_SWITCH_FAST 1 1766 #define UCLK_SWITCH_DUMMY 2 1767 #endif 1768