1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef SMU11_DRIVER_IF_ARCTURUS_H 25 #define SMU11_DRIVER_IF_ARCTURUS_H 26 27 // *** IMPORTANT *** 28 // SMU TEAM: Always increment the interface version if 29 // any structure is changed in this file 30 //#define SMU11_DRIVER_IF_VERSION 0x09 31 32 #define PPTABLE_ARCTURUS_SMU_VERSION 4 33 34 #define NUM_GFXCLK_DPM_LEVELS 16 35 #define NUM_VCLK_DPM_LEVELS 8 36 #define NUM_DCLK_DPM_LEVELS 8 37 #define NUM_MP0CLK_DPM_LEVELS 2 38 #define NUM_SOCCLK_DPM_LEVELS 8 39 #define NUM_UCLK_DPM_LEVELS 4 40 #define NUM_FCLK_DPM_LEVELS 8 41 #define NUM_XGMI_LEVELS 2 42 #define NUM_XGMI_PSTATE_LEVELS 4 43 44 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1) 45 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1) 46 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1) 47 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1) 48 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1) 49 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) 50 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1) 51 #define MAX_XGMI_LEVEL (NUM_XGMI_LEVELS - 1) 52 #define MAX_XGMI_PSTATE_LEVEL (NUM_XGMI_PSTATE_LEVELS - 1) 53 54 // Feature Control Defines 55 // DPM 56 #define FEATURE_DPM_PREFETCHER_BIT 0 57 #define FEATURE_DPM_GFXCLK_BIT 1 58 #define FEATURE_DPM_UCLK_BIT 2 59 #define FEATURE_DPM_SOCCLK_BIT 3 60 #define FEATURE_DPM_FCLK_BIT 4 61 #define FEATURE_DPM_MP0CLK_BIT 5 62 #define FEATURE_DPM_XGMI_BIT 6 63 // Idle 64 #define FEATURE_DS_GFXCLK_BIT 7 65 #define FEATURE_DS_SOCCLK_BIT 8 66 #define FEATURE_DS_LCLK_BIT 9 67 #define FEATURE_DS_FCLK_BIT 10 68 #define FEATURE_DS_UCLK_BIT 11 69 #define FEATURE_GFX_ULV_BIT 12 70 #define FEATURE_DPM_VCN_BIT 13 71 #define FEATURE_RSMU_SMN_CG_BIT 14 72 #define FEATURE_WAFL_CG_BIT 15 73 // Throttler/Response 74 #define FEATURE_PPT_BIT 16 75 #define FEATURE_TDC_BIT 17 76 #define FEATURE_APCC_PLUS_BIT 18 77 #define FEATURE_VR0HOT_BIT 19 78 #define FEATURE_VR1HOT_BIT 20 79 #define FEATURE_FW_CTF_BIT 21 80 #define FEATURE_FAN_CONTROL_BIT 22 81 #define FEATURE_THERMAL_BIT 23 82 // Other 83 #define FEATURE_OUT_OF_BAND_MONITOR_BIT 24 84 #define FEATURE_TEMP_DEPENDENT_VMIN_BIT 25 85 #define FEATURE_PER_PART_VMIN_BIT 26 86 87 #define FEATURE_SPARE_27_BIT 27 88 #define FEATURE_SPARE_28_BIT 28 89 #define FEATURE_SPARE_29_BIT 29 90 #define FEATURE_SPARE_30_BIT 30 91 #define FEATURE_SPARE_31_BIT 31 92 #define FEATURE_SPARE_32_BIT 32 93 #define FEATURE_SPARE_33_BIT 33 94 #define FEATURE_SPARE_34_BIT 34 95 #define FEATURE_SPARE_35_BIT 35 96 #define FEATURE_SPARE_36_BIT 36 97 #define FEATURE_SPARE_37_BIT 37 98 #define FEATURE_SPARE_38_BIT 38 99 #define FEATURE_SPARE_39_BIT 39 100 #define FEATURE_SPARE_40_BIT 40 101 #define FEATURE_SPARE_41_BIT 41 102 #define FEATURE_SPARE_42_BIT 42 103 #define FEATURE_SPARE_43_BIT 43 104 #define FEATURE_SPARE_44_BIT 44 105 #define FEATURE_SPARE_45_BIT 45 106 #define FEATURE_SPARE_46_BIT 46 107 #define FEATURE_SPARE_47_BIT 47 108 #define FEATURE_SPARE_48_BIT 48 109 #define FEATURE_SPARE_49_BIT 49 110 #define FEATURE_SPARE_50_BIT 50 111 #define FEATURE_SPARE_51_BIT 51 112 #define FEATURE_SPARE_52_BIT 52 113 #define FEATURE_SPARE_53_BIT 53 114 #define FEATURE_SPARE_54_BIT 54 115 #define FEATURE_SPARE_55_BIT 55 116 #define FEATURE_SPARE_56_BIT 56 117 #define FEATURE_SPARE_57_BIT 57 118 #define FEATURE_SPARE_58_BIT 58 119 #define FEATURE_SPARE_59_BIT 59 120 #define FEATURE_SPARE_60_BIT 60 121 #define FEATURE_SPARE_61_BIT 61 122 #define FEATURE_SPARE_62_BIT 62 123 #define FEATURE_SPARE_63_BIT 63 124 125 #define NUM_FEATURES 64 126 127 128 #define FEATURE_DPM_PREFETCHER_MASK (1 << FEATURE_DPM_PREFETCHER_BIT ) 129 #define FEATURE_DPM_GFXCLK_MASK (1 << FEATURE_DPM_GFXCLK_BIT ) 130 #define FEATURE_DPM_UCLK_MASK (1 << FEATURE_DPM_UCLK_BIT ) 131 #define FEATURE_DPM_SOCCLK_MASK (1 << FEATURE_DPM_SOCCLK_BIT ) 132 #define FEATURE_DPM_FCLK_MASK (1 << FEATURE_DPM_FCLK_BIT ) 133 #define FEATURE_DPM_MP0CLK_MASK (1 << FEATURE_DPM_MP0CLK_BIT ) 134 #define FEATURE_DPM_XGMI_MASK (1 << FEATURE_DPM_XGMI_BIT ) 135 136 #define FEATURE_DS_GFXCLK_MASK (1 << FEATURE_DS_GFXCLK_BIT ) 137 #define FEATURE_DS_SOCCLK_MASK (1 << FEATURE_DS_SOCCLK_BIT ) 138 #define FEATURE_DS_LCLK_MASK (1 << FEATURE_DS_LCLK_BIT ) 139 #define FEATURE_DS_FCLK_MASK (1 << FEATURE_DS_FCLK_BIT ) 140 #define FEATURE_DS_UCLK_MASK (1 << FEATURE_DS_UCLK_BIT ) 141 #define FEATURE_GFX_ULV_MASK (1 << FEATURE_GFX_ULV_BIT ) 142 #define FEATURE_DPM_VCN_MASK (1 << FEATURE_DPM_VCN_BIT ) 143 #define FEATURE_RSMU_SMN_CG_MASK (1 << FEATURE_RSMU_SMN_CG_BIT ) 144 #define FEATURE_WAFL_CG_MASK (1 << FEATURE_WAFL_CG_BIT ) 145 146 #define FEATURE_PPT_MASK (1 << FEATURE_PPT_BIT ) 147 #define FEATURE_TDC_MASK (1 << FEATURE_TDC_BIT ) 148 #define FEATURE_APCC_PLUS_MASK (1 << FEATURE_APCC_PLUS_BIT ) 149 #define FEATURE_VR0HOT_MASK (1 << FEATURE_VR0HOT_BIT ) 150 #define FEATURE_VR1HOT_MASK (1 << FEATURE_VR1HOT_BIT ) 151 #define FEATURE_FW_CTF_MASK (1 << FEATURE_FW_CTF_BIT ) 152 #define FEATURE_FAN_CONTROL_MASK (1 << FEATURE_FAN_CONTROL_BIT ) 153 #define FEATURE_THERMAL_MASK (1 << FEATURE_THERMAL_BIT ) 154 155 #define FEATURE_OUT_OF_BAND_MONITOR_MASK (1 << FEATURE_OUT_OF_BAND_MONITOR_BIT ) 156 #define FEATURE_TEMP_DEPENDENT_VMIN_MASK (1 << FEATURE_TEMP_DEPENDENT_VMIN_BIT ) 157 #define FEATURE_PER_PART_VMIN_MASK (1 << FEATURE_PER_PART_VMIN_BIT ) 158 159 160 //FIXME need updating 161 // Debug Overrides Bitmask 162 #define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000001 163 #define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000002 164 165 // I2C Config Bit Defines 166 #define I2C_CONTROLLER_ENABLED 1 167 #define I2C_CONTROLLER_DISABLED 0 168 169 // VR Mapping Bit Defines 170 #define VR_MAPPING_VR_SELECT_MASK 0x01 171 #define VR_MAPPING_VR_SELECT_SHIFT 0x00 172 173 #define VR_MAPPING_PLANE_SELECT_MASK 0x02 174 #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 175 176 // PSI Bit Defines 177 #define PSI_SEL_VR0_PLANE0_PSI0 0x01 178 #define PSI_SEL_VR0_PLANE0_PSI1 0x02 179 #define PSI_SEL_VR0_PLANE1_PSI0 0x04 180 #define PSI_SEL_VR0_PLANE1_PSI1 0x08 181 #define PSI_SEL_VR1_PLANE0_PSI0 0x10 182 #define PSI_SEL_VR1_PLANE0_PSI1 0x20 183 #define PSI_SEL_VR1_PLANE1_PSI0 0x40 184 #define PSI_SEL_VR1_PLANE1_PSI1 0x80 185 186 // Throttler Control/Status Bits 187 #define THROTTLER_PADDING_BIT 0 188 #define THROTTLER_TEMP_EDGE_BIT 1 189 #define THROTTLER_TEMP_HOTSPOT_BIT 2 190 #define THROTTLER_TEMP_MEM_BIT 3 191 #define THROTTLER_TEMP_VR_GFX_BIT 4 192 #define THROTTLER_TEMP_VR_MEM_BIT 5 193 #define THROTTLER_TEMP_VR_SOC_BIT 6 194 #define THROTTLER_TDC_GFX_BIT 7 195 #define THROTTLER_TDC_SOC_BIT 8 196 #define THROTTLER_PPT0_BIT 9 197 #define THROTTLER_PPT1_BIT 10 198 #define THROTTLER_PPT2_BIT 11 199 #define THROTTLER_PPT3_BIT 12 200 #define THROTTLER_PPM_BIT 13 201 #define THROTTLER_FIT_BIT 14 202 #define THROTTLER_APCC_BIT 15 203 #define THROTTLER_VRHOT0_BIT 16 204 #define THROTTLER_VRHOT1_BIT 17 205 206 // Table transfer status 207 #define TABLE_TRANSFER_OK 0x0 208 #define TABLE_TRANSFER_FAILED 0xFF 209 #define TABLE_TRANSFER_PENDING 0xAB 210 211 // Workload bits 212 #define WORKLOAD_PPLIB_DEFAULT_BIT 0 213 #define WORKLOAD_PPLIB_POWER_SAVING_BIT 1 214 #define WORKLOAD_PPLIB_VIDEO_BIT 2 215 #define WORKLOAD_PPLIB_COMPUTE_BIT 3 216 #define WORKLOAD_PPLIB_CUSTOM_BIT 4 217 #define WORKLOAD_PPLIB_COUNT 5 218 219 //XGMI performance states 220 #define XGMI_STATE_D0 1 221 #define XGMI_STATE_D3 0 222 223 #define NUM_I2C_CONTROLLERS 8 224 225 #define I2C_CONTROLLER_ENABLED 1 226 #define I2C_CONTROLLER_DISABLED 0 227 228 #define MAX_SW_I2C_COMMANDS 8 229 230 typedef enum { 231 I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0 232 I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1 233 I2C_CONTROLLER_PORT_COUNT, 234 } I2cControllerPort_e; 235 236 typedef enum { 237 I2C_CONTROLLER_NAME_VR_GFX = 0, 238 I2C_CONTROLLER_NAME_VR_SOC, 239 I2C_CONTROLLER_NAME_VR_MEM, 240 I2C_CONTROLLER_NAME_SPARE, 241 I2C_CONTROLLER_NAME_COUNT, 242 } I2cControllerName_e; 243 244 typedef enum { 245 I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 246 I2C_CONTROLLER_THROTTLER_VR_GFX, 247 I2C_CONTROLLER_THROTTLER_VR_SOC, 248 I2C_CONTROLLER_THROTTLER_VR_MEM, 249 I2C_CONTROLLER_THROTTLER_COUNT, 250 } I2cControllerThrottler_e; 251 252 typedef enum { 253 I2C_CONTROLLER_PROTOCOL_VR_0, 254 I2C_CONTROLLER_PROTOCOL_VR_1, 255 I2C_CONTROLLER_PROTOCOL_TMP_0, 256 I2C_CONTROLLER_PROTOCOL_TMP_1, 257 I2C_CONTROLLER_PROTOCOL_SPARE_0, 258 I2C_CONTROLLER_PROTOCOL_SPARE_1, 259 I2C_CONTROLLER_PROTOCOL_COUNT, 260 } I2cControllerProtocol_e; 261 262 typedef struct { 263 uint8_t Enabled; 264 uint8_t Speed; 265 uint8_t Padding[2]; 266 uint32_t SlaveAddress; 267 uint8_t ControllerPort; 268 uint8_t ControllerName; 269 uint8_t ThermalThrotter; 270 uint8_t I2cProtocol; 271 } I2cControllerConfig_t; 272 273 typedef enum { 274 I2C_PORT_SVD_SCL = 0, 275 I2C_PORT_GPIO, 276 } I2cPort_e; 277 278 typedef enum { 279 I2C_SPEED_FAST_50K = 0, //50 Kbits/s 280 I2C_SPEED_FAST_100K, //100 Kbits/s 281 I2C_SPEED_FAST_400K, //400 Kbits/s 282 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 283 I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 284 I2C_SPEED_HIGH_2M, //2.3 Mbits/s 285 I2C_SPEED_COUNT, 286 } I2cSpeed_e; 287 288 typedef enum { 289 I2C_CMD_READ = 0, 290 I2C_CMD_WRITE, 291 I2C_CMD_COUNT, 292 } I2cCmdType_e; 293 294 #define CMDCONFIG_STOP_BIT 0 295 #define CMDCONFIG_RESTART_BIT 1 296 297 #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 298 #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 299 300 typedef struct { 301 uint8_t RegisterAddr; ////only valid for write, ignored for read 302 uint8_t Cmd; //Read(0) or Write(1) 303 uint8_t Data; //Return data for read. Data to send for write 304 uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command 305 } SwI2cCmd_t; //SW I2C Command Table 306 307 typedef struct { 308 uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 309 uint8_t I2CSpeed; //Slow(0) or Fast(1) 310 uint16_t SlaveAddress; 311 uint8_t NumCmds; //Number of commands 312 uint8_t Padding[3]; 313 314 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 315 316 uint32_t MmHubPadding[8]; // SMU internal use 317 318 } SwI2cRequest_t; // SW I2C Request Table 319 320 //D3HOT sequences 321 typedef enum { 322 BACO_SEQUENCE, 323 MSR_SEQUENCE, 324 BAMACO_SEQUENCE, 325 ULPS_SEQUENCE, 326 D3HOT_SEQUENCE_COUNT, 327 }D3HOTSequence_e; 328 329 //THis is aligned with RSMU PGFSM Register Mapping 330 typedef enum { 331 PG_DYNAMIC_MODE = 0, 332 PG_STATIC_MODE, 333 } PowerGatingMode_e; 334 335 //This is aligned with RSMU PGFSM Register Mapping 336 typedef enum { 337 PG_POWER_DOWN = 0, 338 PG_POWER_UP, 339 } PowerGatingSettings_e; 340 341 typedef struct { 342 uint32_t a; // store in IEEE float format in this variable 343 uint32_t b; // store in IEEE float format in this variable 344 uint32_t c; // store in IEEE float format in this variable 345 } QuadraticInt_t; 346 347 typedef struct { 348 uint32_t m; // store in IEEE float format in this variable 349 uint32_t b; // store in IEEE float format in this variable 350 } LinearInt_t; 351 352 typedef struct { 353 uint32_t a; // store in IEEE float format in this variable 354 uint32_t b; // store in IEEE float format in this variable 355 uint32_t c; // store in IEEE float format in this variable 356 } DroopInt_t; 357 358 typedef enum { 359 GFXCLK_SOURCE_PLL = 0, 360 GFXCLK_SOURCE_AFLL, 361 GFXCLK_SOURCE_COUNT, 362 } GfxclkSrc_e; 363 364 typedef enum { 365 PPCLK_GFXCLK, 366 PPCLK_VCLK, 367 PPCLK_DCLK, 368 PPCLK_SOCCLK, 369 PPCLK_UCLK, 370 PPCLK_FCLK, 371 PPCLK_COUNT, 372 } PPCLK_e; 373 374 typedef enum { 375 POWER_SOURCE_AC, 376 POWER_SOURCE_DC, 377 POWER_SOURCE_COUNT, 378 } POWER_SOURCE_e; 379 380 typedef enum { 381 TEMP_EDGE, 382 TEMP_HOTSPOT, 383 TEMP_MEM, 384 TEMP_VR_GFX, 385 TEMP_VR_SOC, 386 TEMP_VR_MEM, 387 TEMP_COUNT 388 } TEMP_TYPE_e; 389 390 typedef enum { 391 PPT_THROTTLER_PPT0, 392 PPT_THROTTLER_PPT1, 393 PPT_THROTTLER_PPT2, 394 PPT_THROTTLER_PPT3, 395 PPT_THROTTLER_COUNT 396 } PPT_THROTTLER_e; 397 398 typedef enum { 399 VOLTAGE_MODE_AVFS = 0, 400 VOLTAGE_MODE_AVFS_SS, 401 VOLTAGE_MODE_SS, 402 VOLTAGE_MODE_COUNT, 403 } VOLTAGE_MODE_e; 404 405 typedef enum { 406 AVFS_VOLTAGE_GFX = 0, 407 AVFS_VOLTAGE_SOC, 408 AVFS_VOLTAGE_COUNT, 409 } AVFS_VOLTAGE_TYPE_e; 410 411 typedef enum { 412 GPIO_INT_POLARITY_ACTIVE_LOW = 0, 413 GPIO_INT_POLARITY_ACTIVE_HIGH, 414 } GpioIntPolarity_e; 415 416 typedef enum { 417 MEMORY_TYPE_GDDR6 = 0, 418 MEMORY_TYPE_HBM, 419 } MemoryType_e; 420 421 typedef enum { 422 PWR_CONFIG_TDP = 0, 423 PWR_CONFIG_TGP, 424 PWR_CONFIG_TCP_ESTIMATED, 425 PWR_CONFIG_TCP_MEASURED, 426 } PwrConfig_e; 427 428 typedef enum { 429 XGMI_LINK_RATE_2 = 2, // 2Gbps 430 XGMI_LINK_RATE_4 = 4, // 4Gbps 431 XGMI_LINK_RATE_8 = 8, // 8Gbps 432 XGMI_LINK_RATE_12 = 12, // 12Gbps 433 XGMI_LINK_RATE_16 = 16, // 16Gbps 434 XGMI_LINK_RATE_17 = 17, // 17Gbps 435 XGMI_LINK_RATE_18 = 18, // 18Gbps 436 XGMI_LINK_RATE_19 = 19, // 19Gbps 437 XGMI_LINK_RATE_20 = 20, // 20Gbps 438 XGMI_LINK_RATE_21 = 21, // 21Gbps 439 XGMI_LINK_RATE_22 = 22, // 22Gbps 440 XGMI_LINK_RATE_23 = 23, // 23Gbps 441 XGMI_LINK_RATE_24 = 24, // 24Gbps 442 XGMI_LINK_RATE_25 = 25, // 25Gbps 443 XGMI_LINK_RATE_COUNT 444 } XGMI_LINK_RATE_e; 445 446 typedef enum { 447 XGMI_LINK_WIDTH_1 = 1, // x1 448 XGMI_LINK_WIDTH_2 = 2, // x2 449 XGMI_LINK_WIDTH_4 = 4, // x4 450 XGMI_LINK_WIDTH_8 = 8, // x8 451 XGMI_LINK_WIDTH_9 = 9, // x9 452 XGMI_LINK_WIDTH_16 = 16, // x16 453 XGMI_LINK_WIDTH_COUNT 454 } XGMI_LINK_WIDTH_e; 455 456 typedef struct { 457 uint8_t VoltageMode; // 0 - AVFS only, 1- min(AVFS,SS), 2-SS only 458 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 459 uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 460 uint8_t padding; 461 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 462 QuadraticInt_t SsCurve; // Slow-slow curve (GHz->V) 463 uint16_t SsFmin; // Fmin for SS curve. If SS curve is selected, will use V@SSFmin for F <= Fmin 464 uint16_t Padding16; 465 } DpmDescriptor_t; 466 467 typedef struct { 468 uint32_t Version; 469 470 // SECTION: Feature Enablement 471 uint32_t FeaturesToRun[2]; 472 473 // SECTION: Infrastructure Limits 474 uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; 475 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; 476 uint16_t TdcLimitSoc; // Amps 477 uint16_t TdcLimitSocTau; // Time constant of LPF in ms 478 uint16_t TdcLimitGfx; // Amps 479 uint16_t TdcLimitGfxTau; // Time constant of LPF in ms 480 481 uint16_t TedgeLimit; // Celcius 482 uint16_t ThotspotLimit; // Celcius 483 uint16_t TmemLimit; // Celcius 484 uint16_t Tvr_gfxLimit; // Celcius 485 uint16_t Tvr_memLimit; // Celcius 486 uint16_t Tvr_socLimit; // Celcius 487 uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime) 488 489 uint16_t PpmPowerLimit; // Switch this this power limit when temperature is above PpmTempThreshold 490 uint16_t PpmTemperatureThreshold; 491 492 // SECTION: Throttler settings 493 uint32_t ThrottlerControlMask; // See Throtter masks defines 494 495 // SECTION: ULV Settings 496 uint16_t UlvVoltageOffsetGfx; // In mV(Q2) 497 uint16_t UlvPadding; // Padding 498 499 uint8_t UlvGfxclkBypass; // 1 to turn off/bypass Gfxclk during ULV, 0 to leave Gfxclk on during ULV 500 uint8_t Padding234[3]; 501 502 // SECTION: Voltage Control Parameters 503 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX 504 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC 505 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX 506 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC 507 508 uint16_t LoadLineResistanceGfx; // In mOhms with 8 fractional bits 509 uint16_t LoadLineResistanceSoc; // In mOhms with 8 fractional bits 510 511 //SECTION: DPM Config 1 512 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 513 514 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 515 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 516 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 517 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 518 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 519 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 520 521 uint32_t Paddingclks[16]; 522 523 // SECTION: DPM Config 2 524 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 525 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 526 527 // GFXCLK DPM 528 uint16_t GfxclkFidle; // In MHz 529 uint16_t GfxclkSlewRate; // for PLL babystepping??? 530 uint8_t Padding567[4]; 531 uint16_t GfxclkDsMaxFreq; // In MHz 532 uint8_t GfxclkSource; // 0 = PLL, 1 = AFLL 533 uint8_t Padding456; 534 535 // GFXCLK Thermal DPM (formerly 'Boost' Settings) 536 uint16_t EnableTdpm; 537 uint16_t TdpmHighHystTemperature; 538 uint16_t TdpmLowHystTemperature; 539 uint16_t GfxclkFreqHighTempLimit; // High limit on GFXCLK when temperature is high, for reliability. 540 541 // SECTION: Fan Control 542 uint16_t FanStopTemp; //Celcius 543 uint16_t FanStartTemp; //Celcius 544 545 uint16_t FanGainEdge; 546 uint16_t FanGainHotspot; 547 uint16_t FanGainVrGfx; 548 uint16_t FanGainVrSoc; 549 uint16_t FanGainVrMem; 550 uint16_t FanGainHbm; 551 uint16_t FanPwmMin; 552 uint16_t FanAcousticLimitRpm; 553 uint16_t FanThrottlingRpm; 554 uint16_t FanMaximumRpm; 555 uint16_t FanTargetTemperature; 556 uint16_t FanTargetGfxclk; 557 uint8_t FanZeroRpmEnable; 558 uint8_t FanTachEdgePerRev; 559 uint8_t FanTempInputSelect; 560 uint8_t padding8_Fan; 561 562 // The following are AFC override parameters. Leave at 0 to use FW defaults. 563 int16_t FuzzyFan_ErrorSetDelta; 564 int16_t FuzzyFan_ErrorRateSetDelta; 565 int16_t FuzzyFan_PwmSetDelta; 566 uint16_t FuzzyFan_Reserved; 567 568 569 // SECTION: AVFS 570 // Overrides 571 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 572 uint8_t Padding8_Avfs[2]; 573 574 QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve 575 DroopInt_t dBtcGbGfxPll; // GHz->V BtcGb 576 DroopInt_t dBtcGbGfxAfll; // GHz->V BtcGb 577 DroopInt_t dBtcGbSoc; // GHz->V BtcGb 578 LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V 579 580 QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V 581 582 uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2 583 584 uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT]; 585 uint8_t Padding8_GfxBtc[2]; 586 587 uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; // mV Q2 588 uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT]; // mV Q2 589 590 uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT]; // mV Q2 591 592 // SECTION: XGMI 593 uint8_t XgmiDpmPstates[NUM_XGMI_LEVELS]; // 2 DPM states, high and low. 0-P0, 1-P1, 2-P2, 3-P3. 594 uint8_t XgmiDpmSpare[2]; 595 596 // Temperature Dependent Vmin 597 uint16_t VDDGFX_TVmin; //Celcius 598 uint16_t VDDSOC_TVmin; //Celcius 599 uint16_t VDDGFX_Vmin_HiTemp; // mV Q2 600 uint16_t VDDGFX_Vmin_LoTemp; // mV Q2 601 uint16_t VDDSOC_Vmin_HiTemp; // mV Q2 602 uint16_t VDDSOC_Vmin_LoTemp; // mV Q2 603 604 uint16_t VDDGFX_TVminHystersis; // Celcius 605 uint16_t VDDSOC_TVminHystersis; // Celcius 606 607 608 // SECTION: Advanced Options 609 uint32_t DebugOverrides; 610 QuadraticInt_t ReservedEquation0; 611 QuadraticInt_t ReservedEquation1; 612 QuadraticInt_t ReservedEquation2; 613 QuadraticInt_t ReservedEquation3; 614 615 uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode 616 uint16_t PaddingUlv; // Padding 617 618 // Total Power configuration, use defines from PwrConfig_e 619 uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured 620 uint8_t TotalPowerSpare1; 621 uint16_t TotalPowerSpare2; 622 623 // APCC Settings 624 uint16_t PccThresholdLow; 625 uint16_t PccThresholdHigh; 626 uint32_t PaddingAPCC[6]; //FIXME pending SPEC 627 628 // OOB Settings 629 uint16_t BasePerformanceCardPower; 630 uint16_t MaxPerformanceCardPower; 631 uint16_t BasePerformanceFrequencyCap; //In Mhz 632 uint16_t MaxPerformanceFrequencyCap; //In Mhz 633 634 // Per-Part Vmin 635 uint16_t VDDGFX_VminLow; // mv Q2 636 uint16_t VDDGFX_TVminLow; //Celcius 637 uint16_t VDDGFX_VminLow_HiTemp; // mv Q2 638 uint16_t VDDGFX_VminLow_LoTemp; // mv Q2 639 640 // SECTION: Reserved 641 uint32_t Reserved[7]; 642 643 // SECTION: BOARD PARAMETERS 644 645 // SVI2 Board Parameters 646 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 647 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 648 649 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 650 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 651 uint8_t VddMemVrMapping; // Use VR_MAPPING* bitfields 652 uint8_t BoardVrMapping; // Use VR_MAPPING* bitfields 653 654 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 655 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN) 656 uint8_t Padding8_V[2]; 657 658 // Telemetry Settings 659 uint16_t GfxMaxCurrent; // in Amps 660 int8_t GfxOffset; // in Amps 661 uint8_t Padding_TelemetryGfx; 662 663 uint16_t SocMaxCurrent; // in Amps 664 int8_t SocOffset; // in Amps 665 uint8_t Padding_TelemetrySoc; 666 667 uint16_t MemMaxCurrent; // in Amps 668 int8_t MemOffset; // in Amps 669 uint8_t Padding_TelemetryMem; 670 671 uint16_t BoardMaxCurrent; // in Amps 672 int8_t BoardOffset; // in Amps 673 uint8_t Padding_TelemetryBoardInput; 674 675 // GPIO Settings 676 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 677 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 678 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 679 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 680 681 // GFXCLK PLL Spread Spectrum 682 uint8_t PllGfxclkSpreadEnabled; // on or off 683 uint8_t PllGfxclkSpreadPercent; // Q4.4 684 uint16_t PllGfxclkSpreadFreq; // kHz 685 686 // UCLK Spread Spectrum 687 uint8_t UclkSpreadEnabled; // on or off 688 uint8_t UclkSpreadPercent; // Q4.4 689 uint16_t UclkSpreadFreq; // kHz 690 691 // FCLK Spread Spectrum 692 uint8_t FclkSpreadEnabled; // on or off 693 uint8_t FclkSpreadPercent; // Q4.4 694 uint16_t FclkSpreadFreq; // kHz 695 696 // GFXCLK Fll Spread Spectrum 697 uint8_t FllGfxclkSpreadEnabled; // on or off 698 uint8_t FllGfxclkSpreadPercent; // Q4.4 699 uint16_t FllGfxclkSpreadFreq; // kHz 700 701 // I2C Controller Structure 702 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 703 704 // Memory section 705 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. 706 707 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines 708 uint8_t PaddingMem[3]; 709 710 // Total board power 711 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 712 uint16_t BoardPadding; 713 714 // SECTION: XGMI Training 715 uint8_t XgmiLinkSpeed [NUM_XGMI_PSTATE_LEVELS]; 716 uint8_t XgmiLinkWidth [NUM_XGMI_PSTATE_LEVELS]; 717 718 uint16_t XgmiFclkFreq [NUM_XGMI_PSTATE_LEVELS]; 719 uint16_t XgmiSocVoltage [NUM_XGMI_PSTATE_LEVELS]; 720 721 // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence 722 uint8_t GpioI2cScl; // Serial Clock 723 uint8_t GpioI2cSda; // Serial Data 724 uint16_t GpioPadding; 725 726 // Platform input telemetry voltage coefficient 727 uint32_t BoardVoltageCoeffA; // decode by /1000 728 uint32_t BoardVoltageCoeffB; // decode by /1000 729 730 uint32_t BoardReserved[7]; 731 732 // Padding for MMHUB - do not modify this 733 uint32_t MmHubPadding[8]; // SMU internal use 734 735 } PPTable_t; 736 737 typedef struct { 738 // Time constant parameters for clock averages in ms 739 uint16_t GfxclkAverageLpfTau; 740 uint16_t SocclkAverageLpfTau; 741 uint16_t UclkAverageLpfTau; 742 uint16_t GfxActivityLpfTau; 743 uint16_t UclkActivityLpfTau; 744 745 uint16_t SocketPowerLpfTau; 746 747 uint16_t VcnClkAverageLpfTau; 748 uint16_t padding16; 749 750 // Padding - ignore 751 uint32_t MmHubPadding[8]; // SMU internal use 752 } DriverSmuConfig_t; 753 754 typedef struct { 755 uint16_t CurrClock[PPCLK_COUNT]; 756 uint16_t AverageGfxclkFrequency; 757 uint16_t AverageSocclkFrequency; 758 uint16_t AverageUclkFrequency ; 759 uint16_t AverageGfxActivity ; 760 uint16_t AverageUclkActivity ; 761 uint8_t CurrSocVoltageOffset ; 762 uint8_t CurrGfxVoltageOffset ; 763 uint8_t CurrMemVidOffset ; 764 uint8_t Padding8 ; 765 uint16_t AverageSocketPower ; 766 uint16_t TemperatureEdge ; 767 uint16_t TemperatureHotspot ; 768 uint16_t TemperatureHBM ; 769 uint16_t TemperatureVrGfx ; 770 uint16_t TemperatureVrSoc ; 771 uint16_t TemperatureVrMem ; 772 uint32_t ThrottlerStatus ; 773 774 uint16_t CurrFanSpeed ; 775 uint16_t AverageVclkFrequency ; 776 uint16_t AverageDclkFrequency ; 777 uint16_t VcnActivityPercentage ; 778 uint32_t EnergyAccumulator ; 779 780 uint32_t Padding[2]; 781 782 // Padding - ignore 783 uint32_t MmHubPadding[8]; // SMU internal use 784 } SmuMetrics_t; 785 786 787 typedef struct { 788 uint16_t avgPsmCount[75]; 789 uint16_t minPsmCount[75]; 790 float avgPsmVoltage[75]; 791 float minPsmVoltage[75]; 792 793 uint32_t MmHubPadding[8]; // SMU internal use 794 } AvfsDebugTable_t; 795 796 typedef struct { 797 uint8_t AvfsVersion; 798 uint8_t Padding; 799 uint8_t AvfsEn[AVFS_VOLTAGE_COUNT]; 800 801 uint8_t OverrideVFT[AVFS_VOLTAGE_COUNT]; 802 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 803 804 uint8_t OverrideTemperatures[AVFS_VOLTAGE_COUNT]; 805 uint8_t OverrideVInversion[AVFS_VOLTAGE_COUNT]; 806 uint8_t OverrideP2V[AVFS_VOLTAGE_COUNT]; 807 uint8_t OverrideP2VCharzFreq[AVFS_VOLTAGE_COUNT]; 808 809 int32_t VFT0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 810 int32_t VFT0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 811 int32_t VFT0_b[AVFS_VOLTAGE_COUNT]; // Q32 812 813 int32_t VFT1_m1[AVFS_VOLTAGE_COUNT]; // Q8.16 814 int32_t VFT1_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 815 int32_t VFT1_b[AVFS_VOLTAGE_COUNT]; // Q32 816 817 int32_t VFT2_m1[AVFS_VOLTAGE_COUNT]; // Q8.16 818 int32_t VFT2_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 819 int32_t VFT2_b[AVFS_VOLTAGE_COUNT]; // Q32 820 821 int32_t AvfsGb0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 822 int32_t AvfsGb0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 823 int32_t AvfsGb0_b[AVFS_VOLTAGE_COUNT]; // Q32 824 825 int32_t AcBtcGb_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 826 int32_t AcBtcGb_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 827 int32_t AcBtcGb_b[AVFS_VOLTAGE_COUNT]; // Q32 828 829 uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT]; 830 uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT]; 831 uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT]; 832 833 uint32_t VInversion[AVFS_VOLTAGE_COUNT]; // in mV with 2 fractional bits 834 835 836 int32_t P2V_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 837 int32_t P2V_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 838 int32_t P2V_b[AVFS_VOLTAGE_COUNT]; // Q32 839 840 uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; // in 10KHz units 841 842 uint32_t EnabledAvfsModules[3]; 843 844 uint32_t MmHubPadding[8]; // SMU internal use 845 } AvfsFuseOverride_t; 846 847 typedef struct { 848 uint8_t Gfx_ActiveHystLimit; 849 uint8_t Gfx_IdleHystLimit; 850 uint8_t Gfx_FPS; 851 uint8_t Gfx_MinActiveFreqType; 852 uint8_t Gfx_BoosterFreqType; 853 uint8_t Gfx_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 854 uint8_t Gfx_UseRlcBusy; 855 uint8_t PaddingGfx[3]; 856 uint16_t Gfx_MinActiveFreq; // MHz 857 uint16_t Gfx_BoosterFreq; // MHz 858 uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms 859 uint32_t Gfx_PD_Data_limit_a; // Q16 860 uint32_t Gfx_PD_Data_limit_b; // Q16 861 uint32_t Gfx_PD_Data_limit_c; // Q16 862 uint32_t Gfx_PD_Data_error_coeff; // Q16 863 uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 864 865 uint8_t Mem_ActiveHystLimit; 866 uint8_t Mem_IdleHystLimit; 867 uint8_t Mem_FPS; 868 uint8_t Mem_MinActiveFreqType; 869 uint8_t Mem_BoosterFreqType; 870 uint8_t Mem_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 871 uint8_t Mem_UseRlcBusy; 872 uint8_t PaddingMem[3]; 873 uint16_t Mem_MinActiveFreq; // MHz 874 uint16_t Mem_BoosterFreq; // MHz 875 uint16_t Mem_PD_Data_time_constant; // Time constant of PD controller in ms 876 uint32_t Mem_PD_Data_limit_a; // Q16 877 uint32_t Mem_PD_Data_limit_b; // Q16 878 uint32_t Mem_PD_Data_limit_c; // Q16 879 uint32_t Mem_PD_Data_error_coeff; // Q16 880 uint32_t Mem_PD_Data_error_rate_coeff; // Q16 881 882 uint32_t Mem_UpThreshold_Limit; // Q16 883 uint8_t Mem_UpHystLimit; 884 uint8_t Mem_DownHystLimit; 885 uint16_t Mem_Fps; 886 887 uint32_t BusyThreshold; // Q16 888 uint32_t BusyHyst; 889 uint32_t IdleHyst; 890 891 uint32_t MmHubPadding[8]; // SMU internal use 892 } DpmActivityMonitorCoeffInt_t; 893 894 // These defines are used with the following messages: 895 // SMC_MSG_TransferTableDram2Smu 896 // SMC_MSG_TransferTableSmu2Dram 897 #define TABLE_PPTABLE 0 898 #define TABLE_AVFS 1 899 #define TABLE_AVFS_PSM_DEBUG 2 900 #define TABLE_AVFS_FUSE_OVERRIDE 3 901 #define TABLE_PMSTATUSLOG 4 902 #define TABLE_SMU_METRICS 5 903 #define TABLE_DRIVER_SMU_CONFIG 6 904 #define TABLE_OVERDRIVE 7 905 #define TABLE_WAFL_XGMI_TOPOLOGY 8 906 #define TABLE_I2C_COMMANDS 9 907 #define TABLE_ACTIVITY_MONITOR_COEFF 10 908 #define TABLE_COUNT 11 909 910 // These defines are used with the SMC_MSG_SetUclkFastSwitch message. 911 typedef enum { 912 DF_SWITCH_TYPE_FAST = 0, 913 DF_SWITCH_TYPE_SLOW, 914 DF_SWITCH_TYPE_COUNT, 915 } DF_SWITCH_TYPE_e; 916 917 typedef enum { 918 DRAM_BIT_WIDTH_DISABLED = 0, 919 DRAM_BIT_WIDTH_X_8, 920 DRAM_BIT_WIDTH_X_16, 921 DRAM_BIT_WIDTH_X_32, 922 DRAM_BIT_WIDTH_X_64, // NOT USED. 923 DRAM_BIT_WIDTH_X_128, 924 DRAM_BIT_WIDTH_COUNT, 925 } DRAM_BIT_WIDTH_TYPE_e; 926 927 #define REMOVE_FMAX_MARGIN_BIT 0x0 928 #define REMOVE_DCTOL_MARGIN_BIT 0x1 929 #define REMOVE_PLATFORM_MARGIN_BIT 0x2 930 931 #endif 932