1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #ifndef __AMDGPU_SMU_H__ 23 #define __AMDGPU_SMU_H__ 24 25 #include "amdgpu.h" 26 #include "kgd_pp_interface.h" 27 #include "dm_pp_interface.h" 28 #include "dm_pp_smu.h" 29 #include "smu_types.h" 30 #include "linux/firmware.h" 31 32 #define SMU_THERMAL_MINIMUM_ALERT_TEMP 0 33 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255 34 #define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000 35 #define SMU_FW_NAME_LEN 0x24 36 37 #define SMU_DPM_USER_PROFILE_RESTORE (1 << 0) 38 #define SMU_CUSTOM_FAN_SPEED_RPM (1 << 1) 39 #define SMU_CUSTOM_FAN_SPEED_PWM (1 << 2) 40 41 // Power Throttlers 42 #define SMU_THROTTLER_PPT0_BIT 0 43 #define SMU_THROTTLER_PPT1_BIT 1 44 #define SMU_THROTTLER_PPT2_BIT 2 45 #define SMU_THROTTLER_PPT3_BIT 3 46 #define SMU_THROTTLER_SPL_BIT 4 47 #define SMU_THROTTLER_FPPT_BIT 5 48 #define SMU_THROTTLER_SPPT_BIT 6 49 #define SMU_THROTTLER_SPPT_APU_BIT 7 50 51 // Current Throttlers 52 #define SMU_THROTTLER_TDC_GFX_BIT 16 53 #define SMU_THROTTLER_TDC_SOC_BIT 17 54 #define SMU_THROTTLER_TDC_MEM_BIT 18 55 #define SMU_THROTTLER_TDC_VDD_BIT 19 56 #define SMU_THROTTLER_TDC_CVIP_BIT 20 57 #define SMU_THROTTLER_EDC_CPU_BIT 21 58 #define SMU_THROTTLER_EDC_GFX_BIT 22 59 #define SMU_THROTTLER_APCC_BIT 23 60 61 // Temperature 62 #define SMU_THROTTLER_TEMP_GPU_BIT 32 63 #define SMU_THROTTLER_TEMP_CORE_BIT 33 64 #define SMU_THROTTLER_TEMP_MEM_BIT 34 65 #define SMU_THROTTLER_TEMP_EDGE_BIT 35 66 #define SMU_THROTTLER_TEMP_HOTSPOT_BIT 36 67 #define SMU_THROTTLER_TEMP_SOC_BIT 37 68 #define SMU_THROTTLER_TEMP_VR_GFX_BIT 38 69 #define SMU_THROTTLER_TEMP_VR_SOC_BIT 39 70 #define SMU_THROTTLER_TEMP_VR_MEM0_BIT 40 71 #define SMU_THROTTLER_TEMP_VR_MEM1_BIT 41 72 #define SMU_THROTTLER_TEMP_LIQUID0_BIT 42 73 #define SMU_THROTTLER_TEMP_LIQUID1_BIT 43 74 #define SMU_THROTTLER_VRHOT0_BIT 44 75 #define SMU_THROTTLER_VRHOT1_BIT 45 76 #define SMU_THROTTLER_PROCHOT_CPU_BIT 46 77 #define SMU_THROTTLER_PROCHOT_GFX_BIT 47 78 79 // Other 80 #define SMU_THROTTLER_PPM_BIT 56 81 #define SMU_THROTTLER_FIT_BIT 57 82 83 struct smu_hw_power_state { 84 unsigned int magic; 85 }; 86 87 struct smu_power_state; 88 89 enum smu_state_ui_label { 90 SMU_STATE_UI_LABEL_NONE, 91 SMU_STATE_UI_LABEL_BATTERY, 92 SMU_STATE_UI_TABEL_MIDDLE_LOW, 93 SMU_STATE_UI_LABEL_BALLANCED, 94 SMU_STATE_UI_LABEL_MIDDLE_HIGHT, 95 SMU_STATE_UI_LABEL_PERFORMANCE, 96 SMU_STATE_UI_LABEL_BACO, 97 }; 98 99 enum smu_state_classification_flag { 100 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001, 101 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002, 102 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004, 103 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008, 104 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010, 105 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020, 106 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040, 107 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080, 108 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100, 109 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200, 110 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400, 111 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800, 112 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000, 113 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000, 114 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000, 115 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000, 116 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000, 117 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000, 118 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000, 119 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000, 120 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000, 121 }; 122 123 struct smu_state_classification_block { 124 enum smu_state_ui_label ui_label; 125 enum smu_state_classification_flag flags; 126 int bios_index; 127 bool temporary_state; 128 bool to_be_deleted; 129 }; 130 131 struct smu_state_pcie_block { 132 unsigned int lanes; 133 }; 134 135 enum smu_refreshrate_source { 136 SMU_REFRESHRATE_SOURCE_EDID, 137 SMU_REFRESHRATE_SOURCE_EXPLICIT 138 }; 139 140 struct smu_state_display_block { 141 bool disable_frame_modulation; 142 bool limit_refreshrate; 143 enum smu_refreshrate_source refreshrate_source; 144 int explicit_refreshrate; 145 int edid_refreshrate_index; 146 bool enable_vari_bright; 147 }; 148 149 struct smu_state_memory_block { 150 bool dll_off; 151 uint8_t m3arb; 152 uint8_t unused[3]; 153 }; 154 155 struct smu_state_software_algorithm_block { 156 bool disable_load_balancing; 157 bool enable_sleep_for_timestamps; 158 }; 159 160 struct smu_temperature_range { 161 int min; 162 int max; 163 int edge_emergency_max; 164 int hotspot_min; 165 int hotspot_crit_max; 166 int hotspot_emergency_max; 167 int mem_min; 168 int mem_crit_max; 169 int mem_emergency_max; 170 int software_shutdown_temp; 171 int software_shutdown_temp_offset; 172 }; 173 174 struct smu_state_validation_block { 175 bool single_display_only; 176 bool disallow_on_dc; 177 uint8_t supported_power_levels; 178 }; 179 180 struct smu_uvd_clocks { 181 uint32_t vclk; 182 uint32_t dclk; 183 }; 184 185 /** 186 * Structure to hold a SMU Power State. 187 */ 188 struct smu_power_state { 189 uint32_t id; 190 struct list_head ordered_list; 191 struct list_head all_states_list; 192 193 struct smu_state_classification_block classification; 194 struct smu_state_validation_block validation; 195 struct smu_state_pcie_block pcie; 196 struct smu_state_display_block display; 197 struct smu_state_memory_block memory; 198 struct smu_state_software_algorithm_block software; 199 struct smu_uvd_clocks uvd_clocks; 200 struct smu_hw_power_state hardware; 201 }; 202 203 enum smu_power_src_type 204 { 205 SMU_POWER_SOURCE_AC, 206 SMU_POWER_SOURCE_DC, 207 SMU_POWER_SOURCE_COUNT, 208 }; 209 210 enum smu_ppt_limit_type 211 { 212 SMU_DEFAULT_PPT_LIMIT = 0, 213 SMU_FAST_PPT_LIMIT, 214 }; 215 216 enum smu_ppt_limit_level 217 { 218 SMU_PPT_LIMIT_MIN = -1, 219 SMU_PPT_LIMIT_CURRENT, 220 SMU_PPT_LIMIT_DEFAULT, 221 SMU_PPT_LIMIT_MAX, 222 }; 223 224 enum smu_memory_pool_size 225 { 226 SMU_MEMORY_POOL_SIZE_ZERO = 0, 227 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000, 228 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000, 229 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000, 230 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000, 231 }; 232 233 struct smu_user_dpm_profile { 234 uint32_t fan_mode; 235 uint32_t power_limit; 236 uint32_t fan_speed_pwm; 237 uint32_t fan_speed_rpm; 238 uint32_t flags; 239 uint32_t user_od; 240 241 /* user clock state information */ 242 uint32_t clk_mask[SMU_CLK_COUNT]; 243 uint32_t clk_dependency; 244 }; 245 246 #define SMU_TABLE_INIT(tables, table_id, s, a, d) \ 247 do { \ 248 tables[table_id].size = s; \ 249 tables[table_id].align = a; \ 250 tables[table_id].domain = d; \ 251 } while (0) 252 253 struct smu_table { 254 uint64_t size; 255 uint32_t align; 256 uint8_t domain; 257 uint64_t mc_address; 258 void *cpu_addr; 259 struct amdgpu_bo *bo; 260 }; 261 262 enum smu_perf_level_designation { 263 PERF_LEVEL_ACTIVITY, 264 PERF_LEVEL_POWER_CONTAINMENT, 265 }; 266 267 struct smu_performance_level { 268 uint32_t core_clock; 269 uint32_t memory_clock; 270 uint32_t vddc; 271 uint32_t vddci; 272 uint32_t non_local_mem_freq; 273 uint32_t non_local_mem_width; 274 }; 275 276 struct smu_clock_info { 277 uint32_t min_mem_clk; 278 uint32_t max_mem_clk; 279 uint32_t min_eng_clk; 280 uint32_t max_eng_clk; 281 uint32_t min_bus_bandwidth; 282 uint32_t max_bus_bandwidth; 283 }; 284 285 struct smu_bios_boot_up_values 286 { 287 uint32_t revision; 288 uint32_t gfxclk; 289 uint32_t uclk; 290 uint32_t socclk; 291 uint32_t dcefclk; 292 uint32_t eclk; 293 uint32_t vclk; 294 uint32_t dclk; 295 uint16_t vddc; 296 uint16_t vddci; 297 uint16_t mvddc; 298 uint16_t vdd_gfx; 299 uint8_t cooling_id; 300 uint32_t pp_table_id; 301 uint32_t format_revision; 302 uint32_t content_revision; 303 uint32_t fclk; 304 uint32_t lclk; 305 uint32_t firmware_caps; 306 }; 307 308 enum smu_table_id 309 { 310 SMU_TABLE_PPTABLE = 0, 311 SMU_TABLE_WATERMARKS, 312 SMU_TABLE_CUSTOM_DPM, 313 SMU_TABLE_DPMCLOCKS, 314 SMU_TABLE_AVFS, 315 SMU_TABLE_AVFS_PSM_DEBUG, 316 SMU_TABLE_AVFS_FUSE_OVERRIDE, 317 SMU_TABLE_PMSTATUSLOG, 318 SMU_TABLE_SMU_METRICS, 319 SMU_TABLE_DRIVER_SMU_CONFIG, 320 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 321 SMU_TABLE_OVERDRIVE, 322 SMU_TABLE_I2C_COMMANDS, 323 SMU_TABLE_PACE, 324 SMU_TABLE_ECCINFO, 325 SMU_TABLE_COMBO_PPTABLE, 326 SMU_TABLE_COUNT, 327 }; 328 329 struct smu_table_context 330 { 331 void *power_play_table; 332 uint32_t power_play_table_size; 333 void *hardcode_pptable; 334 unsigned long metrics_time; 335 void *metrics_table; 336 void *clocks_table; 337 void *watermarks_table; 338 339 void *max_sustainable_clocks; 340 struct smu_bios_boot_up_values boot_values; 341 void *driver_pptable; 342 void *combo_pptable; 343 void *ecc_table; 344 void *driver_smu_config_table; 345 struct smu_table tables[SMU_TABLE_COUNT]; 346 /* 347 * The driver table is just a staging buffer for 348 * uploading/downloading content from the SMU. 349 * 350 * And the table_id for SMU_MSG_TransferTableSmu2Dram/ 351 * SMU_MSG_TransferTableDram2Smu instructs SMU 352 * which content driver is interested. 353 */ 354 struct smu_table driver_table; 355 struct smu_table memory_pool; 356 struct smu_table dummy_read_1_table; 357 uint8_t thermal_controller_type; 358 359 void *overdrive_table; 360 void *boot_overdrive_table; 361 void *user_overdrive_table; 362 363 uint32_t gpu_metrics_table_size; 364 void *gpu_metrics_table; 365 }; 366 367 struct smu_dpm_context { 368 uint32_t dpm_context_size; 369 void *dpm_context; 370 void *golden_dpm_context; 371 enum amd_dpm_forced_level dpm_level; 372 enum amd_dpm_forced_level saved_dpm_level; 373 enum amd_dpm_forced_level requested_dpm_level; 374 struct smu_power_state *dpm_request_power_state; 375 struct smu_power_state *dpm_current_power_state; 376 struct mclock_latency_table *mclk_latency_table; 377 }; 378 379 struct smu_power_gate { 380 bool uvd_gated; 381 bool vce_gated; 382 atomic_t vcn_gated; 383 atomic_t jpeg_gated; 384 }; 385 386 struct smu_power_context { 387 void *power_context; 388 uint32_t power_context_size; 389 struct smu_power_gate power_gate; 390 }; 391 392 #define SMU_FEATURE_MAX (64) 393 struct smu_feature 394 { 395 uint32_t feature_num; 396 DECLARE_BITMAP(supported, SMU_FEATURE_MAX); 397 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX); 398 }; 399 400 struct smu_clocks { 401 uint32_t engine_clock; 402 uint32_t memory_clock; 403 uint32_t bus_bandwidth; 404 uint32_t engine_clock_in_sr; 405 uint32_t dcef_clock; 406 uint32_t dcef_clock_in_sr; 407 }; 408 409 #define MAX_REGULAR_DPM_NUM 16 410 struct mclk_latency_entries { 411 uint32_t frequency; 412 uint32_t latency; 413 }; 414 struct mclock_latency_table { 415 uint32_t count; 416 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM]; 417 }; 418 419 enum smu_reset_mode 420 { 421 SMU_RESET_MODE_0, 422 SMU_RESET_MODE_1, 423 SMU_RESET_MODE_2, 424 }; 425 426 enum smu_baco_state 427 { 428 SMU_BACO_STATE_ENTER = 0, 429 SMU_BACO_STATE_EXIT, 430 }; 431 432 struct smu_baco_context 433 { 434 uint32_t state; 435 bool platform_support; 436 bool maco_support; 437 }; 438 439 struct smu_freq_info { 440 uint32_t min; 441 uint32_t max; 442 uint32_t freq_level; 443 }; 444 445 struct pstates_clk_freq { 446 uint32_t min; 447 uint32_t standard; 448 uint32_t peak; 449 struct smu_freq_info custom; 450 struct smu_freq_info curr; 451 }; 452 453 struct smu_umd_pstate_table { 454 struct pstates_clk_freq gfxclk_pstate; 455 struct pstates_clk_freq socclk_pstate; 456 struct pstates_clk_freq uclk_pstate; 457 struct pstates_clk_freq vclk_pstate; 458 struct pstates_clk_freq dclk_pstate; 459 struct pstates_clk_freq fclk_pstate; 460 }; 461 462 struct cmn2asic_msg_mapping { 463 int valid_mapping; 464 int map_to; 465 int valid_in_vf; 466 }; 467 468 struct cmn2asic_mapping { 469 int valid_mapping; 470 int map_to; 471 }; 472 473 struct stb_context { 474 uint32_t stb_buf_size; 475 bool enabled; 476 spinlock_t lock; 477 }; 478 479 #define WORKLOAD_POLICY_MAX 7 480 481 struct smu_context 482 { 483 struct amdgpu_device *adev; 484 struct amdgpu_irq_src irq_source; 485 486 const struct pptable_funcs *ppt_funcs; 487 const struct cmn2asic_msg_mapping *message_map; 488 const struct cmn2asic_mapping *clock_map; 489 const struct cmn2asic_mapping *feature_map; 490 const struct cmn2asic_mapping *table_map; 491 const struct cmn2asic_mapping *pwr_src_map; 492 const struct cmn2asic_mapping *workload_map; 493 struct mutex message_lock; 494 uint64_t pool_size; 495 496 struct smu_table_context smu_table; 497 struct smu_dpm_context smu_dpm; 498 struct smu_power_context smu_power; 499 struct smu_feature smu_feature; 500 struct amd_pp_display_configuration *display_config; 501 struct smu_baco_context smu_baco; 502 struct smu_temperature_range thermal_range; 503 void *od_settings; 504 505 struct smu_umd_pstate_table pstate_table; 506 uint32_t pstate_sclk; 507 uint32_t pstate_mclk; 508 509 bool od_enabled; 510 uint32_t current_power_limit; 511 uint32_t default_power_limit; 512 uint32_t max_power_limit; 513 514 /* soft pptable */ 515 uint32_t ppt_offset_bytes; 516 uint32_t ppt_size_bytes; 517 uint8_t *ppt_start_addr; 518 519 bool support_power_containment; 520 bool disable_watermark; 521 522 #define WATERMARKS_EXIST (1 << 0) 523 #define WATERMARKS_LOADED (1 << 1) 524 uint32_t watermarks_bitmap; 525 uint32_t hard_min_uclk_req_from_dal; 526 bool disable_uclk_switch; 527 528 uint32_t workload_mask; 529 uint32_t workload_prority[WORKLOAD_POLICY_MAX]; 530 uint32_t workload_setting[WORKLOAD_POLICY_MAX]; 531 uint32_t power_profile_mode; 532 uint32_t default_power_profile_mode; 533 bool pm_enabled; 534 bool is_apu; 535 536 uint32_t smc_driver_if_version; 537 uint32_t smc_fw_if_version; 538 uint32_t smc_fw_version; 539 540 bool uploading_custom_pp_table; 541 bool dc_controlled_by_gpio; 542 543 struct work_struct throttling_logging_work; 544 atomic64_t throttle_int_counter; 545 struct work_struct interrupt_work; 546 547 unsigned fan_max_rpm; 548 unsigned manual_fan_speed_pwm; 549 550 uint32_t gfx_default_hard_min_freq; 551 uint32_t gfx_default_soft_max_freq; 552 uint32_t gfx_actual_hard_min_freq; 553 uint32_t gfx_actual_soft_max_freq; 554 555 /* APU only */ 556 uint32_t cpu_default_soft_min_freq; 557 uint32_t cpu_default_soft_max_freq; 558 uint32_t cpu_actual_soft_min_freq; 559 uint32_t cpu_actual_soft_max_freq; 560 uint32_t cpu_core_id_select; 561 uint16_t cpu_core_num; 562 563 struct smu_user_dpm_profile user_dpm_profile; 564 565 struct stb_context stb_context; 566 567 struct firmware pptable_firmware; 568 569 u32 param_reg; 570 u32 msg_reg; 571 u32 resp_reg; 572 573 u32 debug_param_reg; 574 u32 debug_msg_reg; 575 u32 debug_resp_reg; 576 }; 577 578 struct i2c_adapter; 579 580 /** 581 * struct pptable_funcs - Callbacks used to interact with the SMU. 582 */ 583 struct pptable_funcs { 584 /** 585 * @run_btc: Calibrate voltage/frequency curve to fit the system's 586 * power delivery and voltage margins. Required for adaptive 587 * voltage frequency scaling (AVFS). 588 */ 589 int (*run_btc)(struct smu_context *smu); 590 591 /** 592 * @get_allowed_feature_mask: Get allowed feature mask. 593 * &feature_mask: Array to store feature mask. 594 * &num: Elements in &feature_mask. 595 */ 596 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); 597 598 /** 599 * @get_current_power_state: Get the current power state. 600 * 601 * Return: Current power state on success, negative errno on failure. 602 */ 603 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu); 604 605 /** 606 * @set_default_dpm_table: Retrieve the default overdrive settings from 607 * the SMU. 608 */ 609 int (*set_default_dpm_table)(struct smu_context *smu); 610 611 int (*set_power_state)(struct smu_context *smu); 612 613 /** 614 * @populate_umd_state_clk: Populate the UMD power state table with 615 * defaults. 616 */ 617 int (*populate_umd_state_clk)(struct smu_context *smu); 618 619 /** 620 * @print_clk_levels: Print DPM clock levels for a clock domain 621 * to buffer. Star current level. 622 * 623 * Used for sysfs interfaces. 624 * Return: Number of characters written to the buffer 625 */ 626 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf); 627 628 /** 629 * @emit_clk_levels: Print DPM clock levels for a clock domain 630 * to buffer using sysfs_emit_at. Star current level. 631 * 632 * Used for sysfs interfaces. 633 * &buf: sysfs buffer 634 * &offset: offset within buffer to start printing, which is updated by the 635 * function. 636 * 637 * Return: 0 on Success or Negative to indicate an error occurred. 638 */ 639 int (*emit_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf, int *offset); 640 641 /** 642 * @force_clk_levels: Set a range of allowed DPM levels for a clock 643 * domain. 644 * &clk_type: Clock domain. 645 * &mask: Range of allowed DPM levels. 646 */ 647 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask); 648 649 /** 650 * @od_edit_dpm_table: Edit the custom overdrive DPM table. 651 * &type: Type of edit. 652 * &input: Edit parameters. 653 * &size: Size of &input. 654 */ 655 int (*od_edit_dpm_table)(struct smu_context *smu, 656 enum PP_OD_DPM_TABLE_COMMAND type, 657 long *input, uint32_t size); 658 659 /** 660 * @restore_user_od_settings: Restore the user customized 661 * OD settings on S3/S4/Runpm resume. 662 */ 663 int (*restore_user_od_settings)(struct smu_context *smu); 664 665 /** 666 * @get_clock_by_type_with_latency: Get the speed and latency of a clock 667 * domain. 668 */ 669 int (*get_clock_by_type_with_latency)(struct smu_context *smu, 670 enum smu_clk_type clk_type, 671 struct 672 pp_clock_levels_with_latency 673 *clocks); 674 /** 675 * @get_clock_by_type_with_voltage: Get the speed and voltage of a clock 676 * domain. 677 */ 678 int (*get_clock_by_type_with_voltage)(struct smu_context *smu, 679 enum amd_pp_clock_type type, 680 struct 681 pp_clock_levels_with_voltage 682 *clocks); 683 684 /** 685 * @get_power_profile_mode: Print all power profile modes to 686 * buffer. Star current mode. 687 */ 688 int (*get_power_profile_mode)(struct smu_context *smu, char *buf); 689 690 /** 691 * @set_power_profile_mode: Set a power profile mode. Also used to 692 * create/set custom power profile modes. 693 * &input: Power profile mode parameters. 694 * &size: Size of &input. 695 */ 696 int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size); 697 698 /** 699 * @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power 700 * management. 701 */ 702 int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable); 703 704 /** 705 * @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power 706 * management. 707 */ 708 int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable); 709 710 /** 711 * @set_gfx_power_up_by_imu: Enable GFX engine with IMU 712 */ 713 int (*set_gfx_power_up_by_imu)(struct smu_context *smu); 714 715 /** 716 * @read_sensor: Read data from a sensor. 717 * &sensor: Sensor to read data from. 718 * &data: Sensor reading. 719 * &size: Size of &data. 720 */ 721 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor, 722 void *data, uint32_t *size); 723 724 /** 725 * @get_apu_thermal_limit: get apu core limit from smu 726 * &limit: current limit temperature in millidegrees Celsius 727 */ 728 int (*get_apu_thermal_limit)(struct smu_context *smu, uint32_t *limit); 729 730 /** 731 * @set_apu_thermal_limit: update all controllers with new limit 732 * &limit: limit temperature to be setted, in millidegrees Celsius 733 */ 734 int (*set_apu_thermal_limit)(struct smu_context *smu, uint32_t limit); 735 736 /** 737 * @pre_display_config_changed: Prepare GPU for a display configuration 738 * change. 739 * 740 * Disable display tracking and pin memory clock speed to maximum. Used 741 * in display component synchronization. 742 */ 743 int (*pre_display_config_changed)(struct smu_context *smu); 744 745 /** 746 * @display_config_changed: Notify the SMU of the current display 747 * configuration. 748 * 749 * Allows SMU to properly track blanking periods for memory clock 750 * adjustment. Used in display component synchronization. 751 */ 752 int (*display_config_changed)(struct smu_context *smu); 753 754 int (*apply_clocks_adjust_rules)(struct smu_context *smu); 755 756 /** 757 * @notify_smc_display_config: Applies display requirements to the 758 * current power state. 759 * 760 * Optimize deep sleep DCEFclk and mclk for the current display 761 * configuration. Used in display component synchronization. 762 */ 763 int (*notify_smc_display_config)(struct smu_context *smu); 764 765 /** 766 * @is_dpm_running: Check if DPM is running. 767 * 768 * Return: True if DPM is running, false otherwise. 769 */ 770 bool (*is_dpm_running)(struct smu_context *smu); 771 772 /** 773 * @get_fan_speed_pwm: Get the current fan speed in PWM. 774 */ 775 int (*get_fan_speed_pwm)(struct smu_context *smu, uint32_t *speed); 776 777 /** 778 * @get_fan_speed_rpm: Get the current fan speed in rpm. 779 */ 780 int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed); 781 782 /** 783 * @set_watermarks_table: Configure and upload the watermarks tables to 784 * the SMU. 785 */ 786 int (*set_watermarks_table)(struct smu_context *smu, 787 struct pp_smu_wm_range_sets *clock_ranges); 788 789 /** 790 * @get_thermal_temperature_range: Get safe thermal limits in Celcius. 791 */ 792 int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range); 793 794 /** 795 * @get_uclk_dpm_states: Get memory clock DPM levels in kHz. 796 * &clocks_in_khz: Array of DPM levels. 797 * &num_states: Elements in &clocks_in_khz. 798 */ 799 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states); 800 801 /** 802 * @set_default_od_settings: Set the overdrive tables to defaults. 803 */ 804 int (*set_default_od_settings)(struct smu_context *smu); 805 806 /** 807 * @set_performance_level: Set a performance level. 808 */ 809 int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level); 810 811 /** 812 * @display_disable_memory_clock_switch: Enable/disable dynamic memory 813 * clock switching. 814 * 815 * Disabling this feature forces memory clock speed to maximum. 816 * Enabling sets the minimum memory clock capable of driving the 817 * current display configuration. 818 */ 819 int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch); 820 821 /** 822 * @dump_pptable: Print the power play table to the system log. 823 */ 824 void (*dump_pptable)(struct smu_context *smu); 825 826 /** 827 * @get_power_limit: Get the device's power limits. 828 */ 829 int (*get_power_limit)(struct smu_context *smu, 830 uint32_t *current_power_limit, 831 uint32_t *default_power_limit, 832 uint32_t *max_power_limit); 833 834 /** 835 * @get_ppt_limit: Get the device's ppt limits. 836 */ 837 int (*get_ppt_limit)(struct smu_context *smu, uint32_t *ppt_limit, 838 enum smu_ppt_limit_type limit_type, enum smu_ppt_limit_level limit_level); 839 840 /** 841 * @set_df_cstate: Set data fabric cstate. 842 */ 843 int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state); 844 845 /** 846 * @allow_xgmi_power_down: Enable/disable external global memory 847 * interconnect power down. 848 */ 849 int (*allow_xgmi_power_down)(struct smu_context *smu, bool en); 850 851 /** 852 * @update_pcie_parameters: Update and upload the system's PCIe 853 * capabilites to the SMU. 854 * &pcie_gen_cap: Maximum allowed PCIe generation. 855 * &pcie_width_cap: Maximum allowed PCIe width. 856 */ 857 int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap); 858 859 /** 860 * @i2c_init: Initialize i2c. 861 * 862 * The i2c bus is used internally by the SMU voltage regulators and 863 * other devices. The i2c's EEPROM also stores bad page tables on boards 864 * with ECC. 865 */ 866 int (*i2c_init)(struct smu_context *smu); 867 868 /** 869 * @i2c_fini: Tear down i2c. 870 */ 871 void (*i2c_fini)(struct smu_context *smu); 872 873 /** 874 * @get_unique_id: Get the GPU's unique id. Used for asset tracking. 875 */ 876 void (*get_unique_id)(struct smu_context *smu); 877 878 /** 879 * @get_dpm_clock_table: Get a copy of the DPM clock table. 880 * 881 * Used by display component in bandwidth and watermark calculations. 882 */ 883 int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table); 884 885 /** 886 * @init_microcode: Request the SMU's firmware from the kernel. 887 */ 888 int (*init_microcode)(struct smu_context *smu); 889 890 /** 891 * @load_microcode: Load firmware onto the SMU. 892 */ 893 int (*load_microcode)(struct smu_context *smu); 894 895 /** 896 * @fini_microcode: Release the SMU's firmware. 897 */ 898 void (*fini_microcode)(struct smu_context *smu); 899 900 /** 901 * @init_smc_tables: Initialize the SMU tables. 902 */ 903 int (*init_smc_tables)(struct smu_context *smu); 904 905 /** 906 * @fini_smc_tables: Release the SMU tables. 907 */ 908 int (*fini_smc_tables)(struct smu_context *smu); 909 910 /** 911 * @init_power: Initialize the power gate table context. 912 */ 913 int (*init_power)(struct smu_context *smu); 914 915 /** 916 * @fini_power: Release the power gate table context. 917 */ 918 int (*fini_power)(struct smu_context *smu); 919 920 /** 921 * @check_fw_status: Check the SMU's firmware status. 922 * 923 * Return: Zero if check passes, negative errno on failure. 924 */ 925 int (*check_fw_status)(struct smu_context *smu); 926 927 /** 928 * @set_mp1_state: put SMU into a correct state for comming 929 * resume from runpm or gpu reset. 930 */ 931 int (*set_mp1_state)(struct smu_context *smu, 932 enum pp_mp1_state mp1_state); 933 934 /** 935 * @setup_pptable: Initialize the power play table and populate it with 936 * default values. 937 */ 938 int (*setup_pptable)(struct smu_context *smu); 939 940 /** 941 * @get_vbios_bootup_values: Get default boot values from the VBIOS. 942 */ 943 int (*get_vbios_bootup_values)(struct smu_context *smu); 944 945 /** 946 * @check_fw_version: Print driver and SMU interface versions to the 947 * system log. 948 * 949 * Interface mismatch is not a critical failure. 950 */ 951 int (*check_fw_version)(struct smu_context *smu); 952 953 /** 954 * @powergate_sdma: Power up/down system direct memory access. 955 */ 956 int (*powergate_sdma)(struct smu_context *smu, bool gate); 957 958 /** 959 * @set_gfx_cgpg: Enable/disable graphics engine course grain power 960 * gating. 961 */ 962 int (*set_gfx_cgpg)(struct smu_context *smu, bool enable); 963 964 /** 965 * @write_pptable: Write the power play table to the SMU. 966 */ 967 int (*write_pptable)(struct smu_context *smu); 968 969 /** 970 * @set_driver_table_location: Send the location of the driver table to 971 * the SMU. 972 */ 973 int (*set_driver_table_location)(struct smu_context *smu); 974 975 /** 976 * @set_tool_table_location: Send the location of the tool table to the 977 * SMU. 978 */ 979 int (*set_tool_table_location)(struct smu_context *smu); 980 981 /** 982 * @notify_memory_pool_location: Send the location of the memory pool to 983 * the SMU. 984 */ 985 int (*notify_memory_pool_location)(struct smu_context *smu); 986 987 /** 988 * @system_features_control: Enable/disable all SMU features. 989 */ 990 int (*system_features_control)(struct smu_context *smu, bool en); 991 992 /** 993 * @send_smc_msg_with_param: Send a message with a parameter to the SMU. 994 * &msg: Type of message. 995 * ¶m: Message parameter. 996 * &read_arg: SMU response (optional). 997 */ 998 int (*send_smc_msg_with_param)(struct smu_context *smu, 999 enum smu_message_type msg, uint32_t param, uint32_t *read_arg); 1000 1001 /** 1002 * @send_smc_msg: Send a message to the SMU. 1003 * &msg: Type of message. 1004 * &read_arg: SMU response (optional). 1005 */ 1006 int (*send_smc_msg)(struct smu_context *smu, 1007 enum smu_message_type msg, 1008 uint32_t *read_arg); 1009 1010 /** 1011 * @init_display_count: Notify the SMU of the number of display 1012 * components in current display configuration. 1013 */ 1014 int (*init_display_count)(struct smu_context *smu, uint32_t count); 1015 1016 /** 1017 * @set_allowed_mask: Notify the SMU of the features currently allowed 1018 * by the driver. 1019 */ 1020 int (*set_allowed_mask)(struct smu_context *smu); 1021 1022 /** 1023 * @get_enabled_mask: Get a mask of features that are currently enabled 1024 * on the SMU. 1025 * &feature_mask: Enabled feature mask. 1026 */ 1027 int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask); 1028 1029 /** 1030 * @feature_is_enabled: Test if a feature is enabled. 1031 * 1032 * Return: One if enabled, zero if disabled. 1033 */ 1034 int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask); 1035 1036 /** 1037 * @disable_all_features_with_exception: Disable all features with 1038 * exception to those in &mask. 1039 */ 1040 int (*disable_all_features_with_exception)(struct smu_context *smu, 1041 enum smu_feature_mask mask); 1042 1043 /** 1044 * @notify_display_change: Enable fast memory clock switching. 1045 * 1046 * Allows for fine grained memory clock switching but has more stringent 1047 * timing requirements. 1048 */ 1049 int (*notify_display_change)(struct smu_context *smu); 1050 1051 /** 1052 * @set_power_limit: Set power limit in watts. 1053 */ 1054 int (*set_power_limit)(struct smu_context *smu, 1055 enum smu_ppt_limit_type limit_type, 1056 uint32_t limit); 1057 1058 /** 1059 * @init_max_sustainable_clocks: Populate max sustainable clock speed 1060 * table with values from the SMU. 1061 */ 1062 int (*init_max_sustainable_clocks)(struct smu_context *smu); 1063 1064 /** 1065 * @enable_thermal_alert: Enable thermal alert interrupts. 1066 */ 1067 int (*enable_thermal_alert)(struct smu_context *smu); 1068 1069 /** 1070 * @disable_thermal_alert: Disable thermal alert interrupts. 1071 */ 1072 int (*disable_thermal_alert)(struct smu_context *smu); 1073 1074 /** 1075 * @set_min_dcef_deep_sleep: Set a minimum display fabric deep sleep 1076 * clock speed in MHz. 1077 */ 1078 int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk); 1079 1080 /** 1081 * @display_clock_voltage_request: Set a hard minimum frequency 1082 * for a clock domain. 1083 */ 1084 int (*display_clock_voltage_request)(struct smu_context *smu, struct 1085 pp_display_clock_request 1086 *clock_req); 1087 1088 /** 1089 * @get_fan_control_mode: Get the current fan control mode. 1090 */ 1091 uint32_t (*get_fan_control_mode)(struct smu_context *smu); 1092 1093 /** 1094 * @set_fan_control_mode: Set the fan control mode. 1095 */ 1096 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode); 1097 1098 /** 1099 * @set_fan_speed_pwm: Set a static fan speed in PWM. 1100 */ 1101 int (*set_fan_speed_pwm)(struct smu_context *smu, uint32_t speed); 1102 1103 /** 1104 * @set_fan_speed_rpm: Set a static fan speed in rpm. 1105 */ 1106 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed); 1107 1108 /** 1109 * @set_xgmi_pstate: Set inter-chip global memory interconnect pstate. 1110 * &pstate: Pstate to set. D0 if Nonzero, D3 otherwise. 1111 */ 1112 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate); 1113 1114 /** 1115 * @gfx_off_control: Enable/disable graphics engine poweroff. 1116 */ 1117 int (*gfx_off_control)(struct smu_context *smu, bool enable); 1118 1119 1120 /** 1121 * @get_gfx_off_status: Get graphics engine poweroff status. 1122 * 1123 * Return: 1124 * 0 - GFXOFF(default). 1125 * 1 - Transition out of GFX State. 1126 * 2 - Not in GFXOFF. 1127 * 3 - Transition into GFXOFF. 1128 */ 1129 uint32_t (*get_gfx_off_status)(struct smu_context *smu); 1130 1131 /** 1132 * @gfx_off_entrycount: total GFXOFF entry count at the time of 1133 * query since system power-up 1134 */ 1135 u32 (*get_gfx_off_entrycount)(struct smu_context *smu, uint64_t *entrycount); 1136 1137 /** 1138 * @set_gfx_off_residency: set 1 to start logging, 0 to stop logging 1139 */ 1140 u32 (*set_gfx_off_residency)(struct smu_context *smu, bool start); 1141 1142 /** 1143 * @get_gfx_off_residency: Average GFXOFF residency % during the logging interval 1144 */ 1145 u32 (*get_gfx_off_residency)(struct smu_context *smu, uint32_t *residency); 1146 1147 /** 1148 * @register_irq_handler: Register interupt request handlers. 1149 */ 1150 int (*register_irq_handler)(struct smu_context *smu); 1151 1152 /** 1153 * @set_azalia_d3_pme: Wake the audio decode engine from d3 sleep. 1154 */ 1155 int (*set_azalia_d3_pme)(struct smu_context *smu); 1156 1157 /** 1158 * @get_max_sustainable_clocks_by_dc: Get a copy of the max sustainable 1159 * clock speeds table. 1160 * 1161 * Provides a way for the display component (DC) to get the max 1162 * sustainable clocks from the SMU. 1163 */ 1164 int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks); 1165 1166 /** 1167 * @baco_is_support: Check if GPU supports BACO (Bus Active, Chip Off). 1168 */ 1169 bool (*baco_is_support)(struct smu_context *smu); 1170 1171 /** 1172 * @baco_get_state: Get the current BACO state. 1173 * 1174 * Return: Current BACO state. 1175 */ 1176 enum smu_baco_state (*baco_get_state)(struct smu_context *smu); 1177 1178 /** 1179 * @baco_set_state: Enter/exit BACO. 1180 */ 1181 int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state); 1182 1183 /** 1184 * @baco_enter: Enter BACO. 1185 */ 1186 int (*baco_enter)(struct smu_context *smu); 1187 1188 /** 1189 * @baco_exit: Exit Baco. 1190 */ 1191 int (*baco_exit)(struct smu_context *smu); 1192 1193 /** 1194 * @mode1_reset_is_support: Check if GPU supports mode1 reset. 1195 */ 1196 bool (*mode1_reset_is_support)(struct smu_context *smu); 1197 /** 1198 * @mode2_reset_is_support: Check if GPU supports mode2 reset. 1199 */ 1200 bool (*mode2_reset_is_support)(struct smu_context *smu); 1201 1202 /** 1203 * @mode1_reset: Perform mode1 reset. 1204 * 1205 * Complete GPU reset. 1206 */ 1207 int (*mode1_reset)(struct smu_context *smu); 1208 1209 /** 1210 * @mode2_reset: Perform mode2 reset. 1211 * 1212 * Mode2 reset generally does not reset as many IPs as mode1 reset. The 1213 * IPs reset varies by asic. 1214 */ 1215 int (*mode2_reset)(struct smu_context *smu); 1216 /* for gfx feature enablement after mode2 reset */ 1217 int (*enable_gfx_features)(struct smu_context *smu); 1218 1219 /** 1220 * @get_dpm_ultimate_freq: Get the hard frequency range of a clock 1221 * domain in MHz. 1222 */ 1223 int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); 1224 1225 /** 1226 * @set_soft_freq_limited_range: Set the soft frequency range of a clock 1227 * domain in MHz. 1228 */ 1229 int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max); 1230 1231 /** 1232 * @set_power_source: Notify the SMU of the current power source. 1233 */ 1234 int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src); 1235 1236 /** 1237 * @log_thermal_throttling_event: Print a thermal throttling warning to 1238 * the system's log. 1239 */ 1240 void (*log_thermal_throttling_event)(struct smu_context *smu); 1241 1242 /** 1243 * @get_pp_feature_mask: Print a human readable table of enabled 1244 * features to buffer. 1245 */ 1246 size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf); 1247 1248 /** 1249 * @set_pp_feature_mask: Request the SMU enable/disable features to 1250 * match those enabled in &new_mask. 1251 */ 1252 int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask); 1253 1254 /** 1255 * @get_gpu_metrics: Get a copy of the GPU metrics table from the SMU. 1256 * 1257 * Return: Size of &table 1258 */ 1259 ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table); 1260 1261 /** 1262 * @enable_mgpu_fan_boost: Enable multi-GPU fan boost. 1263 */ 1264 int (*enable_mgpu_fan_boost)(struct smu_context *smu); 1265 1266 /** 1267 * @gfx_ulv_control: Enable/disable ultra low voltage. 1268 */ 1269 int (*gfx_ulv_control)(struct smu_context *smu, bool enablement); 1270 1271 /** 1272 * @deep_sleep_control: Enable/disable deep sleep. 1273 */ 1274 int (*deep_sleep_control)(struct smu_context *smu, bool enablement); 1275 1276 /** 1277 * @get_fan_parameters: Get fan parameters. 1278 * 1279 * Get maximum fan speed from the power play table. 1280 */ 1281 int (*get_fan_parameters)(struct smu_context *smu); 1282 1283 /** 1284 * @post_init: Helper function for asic specific workarounds. 1285 */ 1286 int (*post_init)(struct smu_context *smu); 1287 1288 /** 1289 * @interrupt_work: Work task scheduled from SMU interrupt handler. 1290 */ 1291 void (*interrupt_work)(struct smu_context *smu); 1292 1293 /** 1294 * @gpo_control: Enable/disable graphics power optimization if supported. 1295 */ 1296 int (*gpo_control)(struct smu_context *smu, bool enablement); 1297 1298 /** 1299 * @gfx_state_change_set: Send the current graphics state to the SMU. 1300 */ 1301 int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state); 1302 1303 /** 1304 * @set_fine_grain_gfx_freq_parameters: Set fine grain graphics clock 1305 * parameters to defaults. 1306 */ 1307 int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu); 1308 1309 /** 1310 * @smu_handle_passthrough_sbr: Send message to SMU about special handling for SBR. 1311 */ 1312 int (*smu_handle_passthrough_sbr)(struct smu_context *smu, bool enable); 1313 1314 /** 1315 * @wait_for_event: Wait for events from SMU. 1316 */ 1317 int (*wait_for_event)(struct smu_context *smu, 1318 enum smu_event_type event, uint64_t event_arg); 1319 1320 /** 1321 * @sned_hbm_bad_pages_num: message SMU to update bad page number 1322 * of SMUBUS table. 1323 */ 1324 int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size); 1325 1326 /** 1327 * @get_ecc_table: message SMU to get ECC INFO table. 1328 */ 1329 ssize_t (*get_ecc_info)(struct smu_context *smu, void *table); 1330 1331 1332 /** 1333 * @stb_collect_info: Collects Smart Trace Buffers data. 1334 */ 1335 int (*stb_collect_info)(struct smu_context *smu, void *buf, uint32_t size); 1336 1337 /** 1338 * @get_default_config_table_settings: Get the ASIC default DriverSmuConfig table settings. 1339 */ 1340 int (*get_default_config_table_settings)(struct smu_context *smu, struct config_table_setting *table); 1341 1342 /** 1343 * @set_config_table: Apply the input DriverSmuConfig table settings. 1344 */ 1345 int (*set_config_table)(struct smu_context *smu, struct config_table_setting *table); 1346 1347 /** 1348 * @sned_hbm_bad_channel_flag: message SMU to update bad channel info 1349 * of SMUBUS table. 1350 */ 1351 int (*send_hbm_bad_channel_flag)(struct smu_context *smu, uint32_t size); 1352 1353 /** 1354 * @init_pptable_microcode: Prepare the pptable microcode to upload via PSP 1355 */ 1356 int (*init_pptable_microcode)(struct smu_context *smu); 1357 }; 1358 1359 typedef enum { 1360 METRICS_CURR_GFXCLK, 1361 METRICS_CURR_SOCCLK, 1362 METRICS_CURR_UCLK, 1363 METRICS_CURR_VCLK, 1364 METRICS_CURR_VCLK1, 1365 METRICS_CURR_DCLK, 1366 METRICS_CURR_DCLK1, 1367 METRICS_CURR_FCLK, 1368 METRICS_CURR_DCEFCLK, 1369 METRICS_AVERAGE_CPUCLK, 1370 METRICS_AVERAGE_GFXCLK, 1371 METRICS_AVERAGE_SOCCLK, 1372 METRICS_AVERAGE_FCLK, 1373 METRICS_AVERAGE_UCLK, 1374 METRICS_AVERAGE_VCLK, 1375 METRICS_AVERAGE_DCLK, 1376 METRICS_AVERAGE_VCLK1, 1377 METRICS_AVERAGE_DCLK1, 1378 METRICS_AVERAGE_GFXACTIVITY, 1379 METRICS_AVERAGE_MEMACTIVITY, 1380 METRICS_AVERAGE_VCNACTIVITY, 1381 METRICS_AVERAGE_SOCKETPOWER, 1382 METRICS_TEMPERATURE_EDGE, 1383 METRICS_TEMPERATURE_HOTSPOT, 1384 METRICS_TEMPERATURE_MEM, 1385 METRICS_TEMPERATURE_VRGFX, 1386 METRICS_TEMPERATURE_VRSOC, 1387 METRICS_TEMPERATURE_VRMEM, 1388 METRICS_THROTTLER_STATUS, 1389 METRICS_CURR_FANSPEED, 1390 METRICS_VOLTAGE_VDDSOC, 1391 METRICS_VOLTAGE_VDDGFX, 1392 METRICS_SS_APU_SHARE, 1393 METRICS_SS_DGPU_SHARE, 1394 METRICS_UNIQUE_ID_UPPER32, 1395 METRICS_UNIQUE_ID_LOWER32, 1396 METRICS_PCIE_RATE, 1397 METRICS_PCIE_WIDTH, 1398 METRICS_CURR_FANPWM, 1399 } MetricsMember_t; 1400 1401 enum smu_cmn2asic_mapping_type { 1402 CMN2ASIC_MAPPING_MSG, 1403 CMN2ASIC_MAPPING_CLK, 1404 CMN2ASIC_MAPPING_FEATURE, 1405 CMN2ASIC_MAPPING_TABLE, 1406 CMN2ASIC_MAPPING_PWR, 1407 CMN2ASIC_MAPPING_WORKLOAD, 1408 }; 1409 1410 enum smu_baco_seq { 1411 BACO_SEQ_BACO = 0, 1412 BACO_SEQ_MSR, 1413 BACO_SEQ_BAMACO, 1414 BACO_SEQ_ULPS, 1415 BACO_SEQ_COUNT, 1416 }; 1417 1418 #define MSG_MAP(msg, index, valid_in_vf) \ 1419 [SMU_MSG_##msg] = {1, (index), (valid_in_vf)} 1420 1421 #define CLK_MAP(clk, index) \ 1422 [SMU_##clk] = {1, (index)} 1423 1424 #define FEA_MAP(fea) \ 1425 [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT} 1426 1427 #define FEA_MAP_REVERSE(fea) \ 1428 [SMU_FEATURE_DPM_##fea##_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1429 1430 #define FEA_MAP_HALF_REVERSE(fea) \ 1431 [SMU_FEATURE_DPM_##fea##CLK_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1432 1433 #define TAB_MAP(tab) \ 1434 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1435 1436 #define TAB_MAP_VALID(tab) \ 1437 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1438 1439 #define TAB_MAP_INVALID(tab) \ 1440 [SMU_TABLE_##tab] = {0, TABLE_##tab} 1441 1442 #define PWR_MAP(tab) \ 1443 [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab} 1444 1445 #define WORKLOAD_MAP(profile, workload) \ 1446 [profile] = {1, (workload)} 1447 1448 /** 1449 * smu_memcpy_trailing - Copy the end of one structure into the middle of another 1450 * 1451 * @dst: Pointer to destination struct 1452 * @first_dst_member: The member name in @dst where the overwrite begins 1453 * @last_dst_member: The member name in @dst where the overwrite ends after 1454 * @src: Pointer to the source struct 1455 * @first_src_member: The member name in @src where the copy begins 1456 * 1457 */ 1458 #define smu_memcpy_trailing(dst, first_dst_member, last_dst_member, \ 1459 src, first_src_member) \ 1460 ({ \ 1461 size_t __src_offset = offsetof(typeof(*(src)), first_src_member); \ 1462 size_t __src_size = sizeof(*(src)) - __src_offset; \ 1463 size_t __dst_offset = offsetof(typeof(*(dst)), first_dst_member); \ 1464 size_t __dst_size = offsetofend(typeof(*(dst)), last_dst_member) - \ 1465 __dst_offset; \ 1466 BUILD_BUG_ON(__src_size != __dst_size); \ 1467 __builtin_memcpy((u8 *)(dst) + __dst_offset, \ 1468 (u8 *)(src) + __src_offset, \ 1469 __dst_size); \ 1470 }) 1471 1472 #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4) 1473 int smu_get_power_limit(void *handle, 1474 uint32_t *limit, 1475 enum pp_power_limit_level pp_limit_level, 1476 enum pp_power_type pp_power_type); 1477 1478 bool smu_mode1_reset_is_support(struct smu_context *smu); 1479 bool smu_mode2_reset_is_support(struct smu_context *smu); 1480 int smu_mode1_reset(struct smu_context *smu); 1481 1482 extern const struct amd_ip_funcs smu_ip_funcs; 1483 1484 bool is_support_sw_smu(struct amdgpu_device *adev); 1485 bool is_support_cclk_dpm(struct amdgpu_device *adev); 1486 int smu_write_watermarks_table(struct smu_context *smu); 1487 1488 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1489 uint32_t *min, uint32_t *max); 1490 1491 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1492 uint32_t min, uint32_t max); 1493 1494 int smu_set_gfx_power_up_by_imu(struct smu_context *smu); 1495 1496 int smu_set_ac_dc(struct smu_context *smu); 1497 1498 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en); 1499 1500 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value); 1501 1502 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value); 1503 1504 int smu_set_residency_gfxoff(struct smu_context *smu, bool value); 1505 1506 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value); 1507 1508 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable); 1509 1510 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 1511 uint64_t event_arg); 1512 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc); 1513 int smu_stb_collect_info(struct smu_context *smu, void *buff, uint32_t size); 1514 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev); 1515 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size); 1516 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size); 1517 #endif 1518 #endif 1519