1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #ifndef __AMDGPU_SMU_H__ 23 #define __AMDGPU_SMU_H__ 24 25 #include "amdgpu.h" 26 #include "kgd_pp_interface.h" 27 #include "dm_pp_interface.h" 28 #include "dm_pp_smu.h" 29 #include "smu_types.h" 30 31 #define SMU_THERMAL_MINIMUM_ALERT_TEMP 0 32 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255 33 #define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000 34 #define SMU_FW_NAME_LEN 0x24 35 36 #define SMU_DPM_USER_PROFILE_RESTORE (1 << 0) 37 #define SMU_CUSTOM_FAN_SPEED_RPM (1 << 1) 38 #define SMU_CUSTOM_FAN_SPEED_PWM (1 << 2) 39 40 // Power Throttlers 41 #define SMU_THROTTLER_PPT0_BIT 0 42 #define SMU_THROTTLER_PPT1_BIT 1 43 #define SMU_THROTTLER_PPT2_BIT 2 44 #define SMU_THROTTLER_PPT3_BIT 3 45 #define SMU_THROTTLER_SPL_BIT 4 46 #define SMU_THROTTLER_FPPT_BIT 5 47 #define SMU_THROTTLER_SPPT_BIT 6 48 #define SMU_THROTTLER_SPPT_APU_BIT 7 49 50 // Current Throttlers 51 #define SMU_THROTTLER_TDC_GFX_BIT 16 52 #define SMU_THROTTLER_TDC_SOC_BIT 17 53 #define SMU_THROTTLER_TDC_MEM_BIT 18 54 #define SMU_THROTTLER_TDC_VDD_BIT 19 55 #define SMU_THROTTLER_TDC_CVIP_BIT 20 56 #define SMU_THROTTLER_EDC_CPU_BIT 21 57 #define SMU_THROTTLER_EDC_GFX_BIT 22 58 #define SMU_THROTTLER_APCC_BIT 23 59 60 // Temperature 61 #define SMU_THROTTLER_TEMP_GPU_BIT 32 62 #define SMU_THROTTLER_TEMP_CORE_BIT 33 63 #define SMU_THROTTLER_TEMP_MEM_BIT 34 64 #define SMU_THROTTLER_TEMP_EDGE_BIT 35 65 #define SMU_THROTTLER_TEMP_HOTSPOT_BIT 36 66 #define SMU_THROTTLER_TEMP_SOC_BIT 37 67 #define SMU_THROTTLER_TEMP_VR_GFX_BIT 38 68 #define SMU_THROTTLER_TEMP_VR_SOC_BIT 39 69 #define SMU_THROTTLER_TEMP_VR_MEM0_BIT 40 70 #define SMU_THROTTLER_TEMP_VR_MEM1_BIT 41 71 #define SMU_THROTTLER_TEMP_LIQUID0_BIT 42 72 #define SMU_THROTTLER_TEMP_LIQUID1_BIT 43 73 #define SMU_THROTTLER_VRHOT0_BIT 44 74 #define SMU_THROTTLER_VRHOT1_BIT 45 75 #define SMU_THROTTLER_PROCHOT_CPU_BIT 46 76 #define SMU_THROTTLER_PROCHOT_GFX_BIT 47 77 78 // Other 79 #define SMU_THROTTLER_PPM_BIT 56 80 #define SMU_THROTTLER_FIT_BIT 57 81 82 struct smu_hw_power_state { 83 unsigned int magic; 84 }; 85 86 struct smu_power_state; 87 88 enum smu_state_ui_label { 89 SMU_STATE_UI_LABEL_NONE, 90 SMU_STATE_UI_LABEL_BATTERY, 91 SMU_STATE_UI_TABEL_MIDDLE_LOW, 92 SMU_STATE_UI_LABEL_BALLANCED, 93 SMU_STATE_UI_LABEL_MIDDLE_HIGHT, 94 SMU_STATE_UI_LABEL_PERFORMANCE, 95 SMU_STATE_UI_LABEL_BACO, 96 }; 97 98 enum smu_state_classification_flag { 99 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001, 100 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002, 101 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004, 102 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008, 103 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010, 104 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020, 105 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040, 106 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080, 107 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100, 108 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200, 109 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400, 110 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800, 111 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000, 112 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000, 113 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000, 114 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000, 115 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000, 116 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000, 117 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000, 118 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000, 119 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000, 120 }; 121 122 struct smu_state_classification_block { 123 enum smu_state_ui_label ui_label; 124 enum smu_state_classification_flag flags; 125 int bios_index; 126 bool temporary_state; 127 bool to_be_deleted; 128 }; 129 130 struct smu_state_pcie_block { 131 unsigned int lanes; 132 }; 133 134 enum smu_refreshrate_source { 135 SMU_REFRESHRATE_SOURCE_EDID, 136 SMU_REFRESHRATE_SOURCE_EXPLICIT 137 }; 138 139 struct smu_state_display_block { 140 bool disable_frame_modulation; 141 bool limit_refreshrate; 142 enum smu_refreshrate_source refreshrate_source; 143 int explicit_refreshrate; 144 int edid_refreshrate_index; 145 bool enable_vari_bright; 146 }; 147 148 struct smu_state_memory_block { 149 bool dll_off; 150 uint8_t m3arb; 151 uint8_t unused[3]; 152 }; 153 154 struct smu_state_software_algorithm_block { 155 bool disable_load_balancing; 156 bool enable_sleep_for_timestamps; 157 }; 158 159 struct smu_temperature_range { 160 int min; 161 int max; 162 int edge_emergency_max; 163 int hotspot_min; 164 int hotspot_crit_max; 165 int hotspot_emergency_max; 166 int mem_min; 167 int mem_crit_max; 168 int mem_emergency_max; 169 int software_shutdown_temp; 170 }; 171 172 struct smu_state_validation_block { 173 bool single_display_only; 174 bool disallow_on_dc; 175 uint8_t supported_power_levels; 176 }; 177 178 struct smu_uvd_clocks { 179 uint32_t vclk; 180 uint32_t dclk; 181 }; 182 183 /** 184 * Structure to hold a SMU Power State. 185 */ 186 struct smu_power_state { 187 uint32_t id; 188 struct list_head ordered_list; 189 struct list_head all_states_list; 190 191 struct smu_state_classification_block classification; 192 struct smu_state_validation_block validation; 193 struct smu_state_pcie_block pcie; 194 struct smu_state_display_block display; 195 struct smu_state_memory_block memory; 196 struct smu_state_software_algorithm_block software; 197 struct smu_uvd_clocks uvd_clocks; 198 struct smu_hw_power_state hardware; 199 }; 200 201 enum smu_power_src_type 202 { 203 SMU_POWER_SOURCE_AC, 204 SMU_POWER_SOURCE_DC, 205 SMU_POWER_SOURCE_COUNT, 206 }; 207 208 enum smu_ppt_limit_type 209 { 210 SMU_DEFAULT_PPT_LIMIT = 0, 211 SMU_FAST_PPT_LIMIT, 212 }; 213 214 enum smu_ppt_limit_level 215 { 216 SMU_PPT_LIMIT_MIN = -1, 217 SMU_PPT_LIMIT_CURRENT, 218 SMU_PPT_LIMIT_DEFAULT, 219 SMU_PPT_LIMIT_MAX, 220 }; 221 222 enum smu_memory_pool_size 223 { 224 SMU_MEMORY_POOL_SIZE_ZERO = 0, 225 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000, 226 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000, 227 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000, 228 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000, 229 }; 230 231 struct smu_user_dpm_profile { 232 uint32_t fan_mode; 233 uint32_t power_limit; 234 uint32_t fan_speed_pwm; 235 uint32_t fan_speed_rpm; 236 uint32_t flags; 237 uint32_t user_od; 238 239 /* user clock state information */ 240 uint32_t clk_mask[SMU_CLK_COUNT]; 241 uint32_t clk_dependency; 242 }; 243 244 #define SMU_TABLE_INIT(tables, table_id, s, a, d) \ 245 do { \ 246 tables[table_id].size = s; \ 247 tables[table_id].align = a; \ 248 tables[table_id].domain = d; \ 249 } while (0) 250 251 struct smu_table { 252 uint64_t size; 253 uint32_t align; 254 uint8_t domain; 255 uint64_t mc_address; 256 void *cpu_addr; 257 struct amdgpu_bo *bo; 258 }; 259 260 enum smu_perf_level_designation { 261 PERF_LEVEL_ACTIVITY, 262 PERF_LEVEL_POWER_CONTAINMENT, 263 }; 264 265 struct smu_performance_level { 266 uint32_t core_clock; 267 uint32_t memory_clock; 268 uint32_t vddc; 269 uint32_t vddci; 270 uint32_t non_local_mem_freq; 271 uint32_t non_local_mem_width; 272 }; 273 274 struct smu_clock_info { 275 uint32_t min_mem_clk; 276 uint32_t max_mem_clk; 277 uint32_t min_eng_clk; 278 uint32_t max_eng_clk; 279 uint32_t min_bus_bandwidth; 280 uint32_t max_bus_bandwidth; 281 }; 282 283 struct smu_bios_boot_up_values 284 { 285 uint32_t revision; 286 uint32_t gfxclk; 287 uint32_t uclk; 288 uint32_t socclk; 289 uint32_t dcefclk; 290 uint32_t eclk; 291 uint32_t vclk; 292 uint32_t dclk; 293 uint16_t vddc; 294 uint16_t vddci; 295 uint16_t mvddc; 296 uint16_t vdd_gfx; 297 uint8_t cooling_id; 298 uint32_t pp_table_id; 299 uint32_t format_revision; 300 uint32_t content_revision; 301 uint32_t fclk; 302 uint32_t lclk; 303 uint32_t firmware_caps; 304 }; 305 306 enum smu_table_id 307 { 308 SMU_TABLE_PPTABLE = 0, 309 SMU_TABLE_WATERMARKS, 310 SMU_TABLE_CUSTOM_DPM, 311 SMU_TABLE_DPMCLOCKS, 312 SMU_TABLE_AVFS, 313 SMU_TABLE_AVFS_PSM_DEBUG, 314 SMU_TABLE_AVFS_FUSE_OVERRIDE, 315 SMU_TABLE_PMSTATUSLOG, 316 SMU_TABLE_SMU_METRICS, 317 SMU_TABLE_DRIVER_SMU_CONFIG, 318 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 319 SMU_TABLE_OVERDRIVE, 320 SMU_TABLE_I2C_COMMANDS, 321 SMU_TABLE_PACE, 322 SMU_TABLE_ECCINFO, 323 SMU_TABLE_COUNT, 324 }; 325 326 struct smu_table_context 327 { 328 void *power_play_table; 329 uint32_t power_play_table_size; 330 void *hardcode_pptable; 331 unsigned long metrics_time; 332 void *metrics_table; 333 void *clocks_table; 334 void *watermarks_table; 335 336 void *max_sustainable_clocks; 337 struct smu_bios_boot_up_values boot_values; 338 void *driver_pptable; 339 void *ecc_table; 340 void *driver_smu_config_table; 341 struct smu_table tables[SMU_TABLE_COUNT]; 342 /* 343 * The driver table is just a staging buffer for 344 * uploading/downloading content from the SMU. 345 * 346 * And the table_id for SMU_MSG_TransferTableSmu2Dram/ 347 * SMU_MSG_TransferTableDram2Smu instructs SMU 348 * which content driver is interested. 349 */ 350 struct smu_table driver_table; 351 struct smu_table memory_pool; 352 struct smu_table dummy_read_1_table; 353 uint8_t thermal_controller_type; 354 355 void *overdrive_table; 356 void *boot_overdrive_table; 357 void *user_overdrive_table; 358 359 uint32_t gpu_metrics_table_size; 360 void *gpu_metrics_table; 361 }; 362 363 struct smu_dpm_context { 364 uint32_t dpm_context_size; 365 void *dpm_context; 366 void *golden_dpm_context; 367 enum amd_dpm_forced_level dpm_level; 368 enum amd_dpm_forced_level saved_dpm_level; 369 enum amd_dpm_forced_level requested_dpm_level; 370 struct smu_power_state *dpm_request_power_state; 371 struct smu_power_state *dpm_current_power_state; 372 struct mclock_latency_table *mclk_latency_table; 373 }; 374 375 struct smu_power_gate { 376 bool uvd_gated; 377 bool vce_gated; 378 atomic_t vcn_gated; 379 atomic_t jpeg_gated; 380 }; 381 382 struct smu_power_context { 383 void *power_context; 384 uint32_t power_context_size; 385 struct smu_power_gate power_gate; 386 }; 387 388 #define SMU_FEATURE_MAX (64) 389 struct smu_feature 390 { 391 uint32_t feature_num; 392 DECLARE_BITMAP(supported, SMU_FEATURE_MAX); 393 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX); 394 }; 395 396 struct smu_clocks { 397 uint32_t engine_clock; 398 uint32_t memory_clock; 399 uint32_t bus_bandwidth; 400 uint32_t engine_clock_in_sr; 401 uint32_t dcef_clock; 402 uint32_t dcef_clock_in_sr; 403 }; 404 405 #define MAX_REGULAR_DPM_NUM 16 406 struct mclk_latency_entries { 407 uint32_t frequency; 408 uint32_t latency; 409 }; 410 struct mclock_latency_table { 411 uint32_t count; 412 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM]; 413 }; 414 415 enum smu_reset_mode 416 { 417 SMU_RESET_MODE_0, 418 SMU_RESET_MODE_1, 419 SMU_RESET_MODE_2, 420 }; 421 422 enum smu_baco_state 423 { 424 SMU_BACO_STATE_ENTER = 0, 425 SMU_BACO_STATE_EXIT, 426 }; 427 428 struct smu_baco_context 429 { 430 uint32_t state; 431 bool platform_support; 432 }; 433 434 struct smu_freq_info { 435 uint32_t min; 436 uint32_t max; 437 uint32_t freq_level; 438 }; 439 440 struct pstates_clk_freq { 441 uint32_t min; 442 uint32_t standard; 443 uint32_t peak; 444 struct smu_freq_info custom; 445 struct smu_freq_info curr; 446 }; 447 448 struct smu_umd_pstate_table { 449 struct pstates_clk_freq gfxclk_pstate; 450 struct pstates_clk_freq socclk_pstate; 451 struct pstates_clk_freq uclk_pstate; 452 struct pstates_clk_freq vclk_pstate; 453 struct pstates_clk_freq dclk_pstate; 454 }; 455 456 struct cmn2asic_msg_mapping { 457 int valid_mapping; 458 int map_to; 459 int valid_in_vf; 460 }; 461 462 struct cmn2asic_mapping { 463 int valid_mapping; 464 int map_to; 465 }; 466 467 struct stb_context { 468 uint32_t stb_buf_size; 469 bool enabled; 470 spinlock_t lock; 471 }; 472 473 #define WORKLOAD_POLICY_MAX 7 474 475 struct smu_context 476 { 477 struct amdgpu_device *adev; 478 struct amdgpu_irq_src irq_source; 479 480 const struct pptable_funcs *ppt_funcs; 481 const struct cmn2asic_msg_mapping *message_map; 482 const struct cmn2asic_mapping *clock_map; 483 const struct cmn2asic_mapping *feature_map; 484 const struct cmn2asic_mapping *table_map; 485 const struct cmn2asic_mapping *pwr_src_map; 486 const struct cmn2asic_mapping *workload_map; 487 struct mutex message_lock; 488 uint64_t pool_size; 489 490 struct smu_table_context smu_table; 491 struct smu_dpm_context smu_dpm; 492 struct smu_power_context smu_power; 493 struct smu_feature smu_feature; 494 struct amd_pp_display_configuration *display_config; 495 struct smu_baco_context smu_baco; 496 struct smu_temperature_range thermal_range; 497 void *od_settings; 498 499 struct smu_umd_pstate_table pstate_table; 500 uint32_t pstate_sclk; 501 uint32_t pstate_mclk; 502 503 bool od_enabled; 504 uint32_t current_power_limit; 505 uint32_t default_power_limit; 506 uint32_t max_power_limit; 507 508 /* soft pptable */ 509 uint32_t ppt_offset_bytes; 510 uint32_t ppt_size_bytes; 511 uint8_t *ppt_start_addr; 512 513 bool support_power_containment; 514 bool disable_watermark; 515 516 #define WATERMARKS_EXIST (1 << 0) 517 #define WATERMARKS_LOADED (1 << 1) 518 uint32_t watermarks_bitmap; 519 uint32_t hard_min_uclk_req_from_dal; 520 bool disable_uclk_switch; 521 522 uint32_t workload_mask; 523 uint32_t workload_prority[WORKLOAD_POLICY_MAX]; 524 uint32_t workload_setting[WORKLOAD_POLICY_MAX]; 525 uint32_t power_profile_mode; 526 uint32_t default_power_profile_mode; 527 bool pm_enabled; 528 bool is_apu; 529 530 uint32_t smc_driver_if_version; 531 uint32_t smc_fw_if_version; 532 uint32_t smc_fw_version; 533 534 bool uploading_custom_pp_table; 535 bool dc_controlled_by_gpio; 536 537 struct work_struct throttling_logging_work; 538 atomic64_t throttle_int_counter; 539 struct work_struct interrupt_work; 540 541 unsigned fan_max_rpm; 542 unsigned manual_fan_speed_pwm; 543 544 uint32_t gfx_default_hard_min_freq; 545 uint32_t gfx_default_soft_max_freq; 546 uint32_t gfx_actual_hard_min_freq; 547 uint32_t gfx_actual_soft_max_freq; 548 549 /* APU only */ 550 uint32_t cpu_default_soft_min_freq; 551 uint32_t cpu_default_soft_max_freq; 552 uint32_t cpu_actual_soft_min_freq; 553 uint32_t cpu_actual_soft_max_freq; 554 uint32_t cpu_core_id_select; 555 uint16_t cpu_core_num; 556 557 struct smu_user_dpm_profile user_dpm_profile; 558 559 struct stb_context stb_context; 560 }; 561 562 struct i2c_adapter; 563 564 /** 565 * struct pptable_funcs - Callbacks used to interact with the SMU. 566 */ 567 struct pptable_funcs { 568 /** 569 * @run_btc: Calibrate voltage/frequency curve to fit the system's 570 * power delivery and voltage margins. Required for adaptive 571 * voltage frequency scaling (AVFS). 572 */ 573 int (*run_btc)(struct smu_context *smu); 574 575 /** 576 * @get_allowed_feature_mask: Get allowed feature mask. 577 * &feature_mask: Array to store feature mask. 578 * &num: Elements in &feature_mask. 579 */ 580 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); 581 582 /** 583 * @get_current_power_state: Get the current power state. 584 * 585 * Return: Current power state on success, negative errno on failure. 586 */ 587 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu); 588 589 /** 590 * @set_default_dpm_table: Retrieve the default overdrive settings from 591 * the SMU. 592 */ 593 int (*set_default_dpm_table)(struct smu_context *smu); 594 595 int (*set_power_state)(struct smu_context *smu); 596 597 /** 598 * @populate_umd_state_clk: Populate the UMD power state table with 599 * defaults. 600 */ 601 int (*populate_umd_state_clk)(struct smu_context *smu); 602 603 /** 604 * @print_clk_levels: Print DPM clock levels for a clock domain 605 * to buffer. Star current level. 606 * 607 * Used for sysfs interfaces. 608 * Return: Number of characters written to the buffer 609 */ 610 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf); 611 612 /** 613 * @emit_clk_levels: Print DPM clock levels for a clock domain 614 * to buffer using sysfs_emit_at. Star current level. 615 * 616 * Used for sysfs interfaces. 617 * &buf: sysfs buffer 618 * &offset: offset within buffer to start printing, which is updated by the 619 * function. 620 * 621 * Return: 0 on Success or Negative to indicate an error occurred. 622 */ 623 int (*emit_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf, int *offset); 624 625 /** 626 * @force_clk_levels: Set a range of allowed DPM levels for a clock 627 * domain. 628 * &clk_type: Clock domain. 629 * &mask: Range of allowed DPM levels. 630 */ 631 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask); 632 633 /** 634 * @od_edit_dpm_table: Edit the custom overdrive DPM table. 635 * &type: Type of edit. 636 * &input: Edit parameters. 637 * &size: Size of &input. 638 */ 639 int (*od_edit_dpm_table)(struct smu_context *smu, 640 enum PP_OD_DPM_TABLE_COMMAND type, 641 long *input, uint32_t size); 642 643 /** 644 * @restore_user_od_settings: Restore the user customized 645 * OD settings on S3/S4/Runpm resume. 646 */ 647 int (*restore_user_od_settings)(struct smu_context *smu); 648 649 /** 650 * @get_clock_by_type_with_latency: Get the speed and latency of a clock 651 * domain. 652 */ 653 int (*get_clock_by_type_with_latency)(struct smu_context *smu, 654 enum smu_clk_type clk_type, 655 struct 656 pp_clock_levels_with_latency 657 *clocks); 658 /** 659 * @get_clock_by_type_with_voltage: Get the speed and voltage of a clock 660 * domain. 661 */ 662 int (*get_clock_by_type_with_voltage)(struct smu_context *smu, 663 enum amd_pp_clock_type type, 664 struct 665 pp_clock_levels_with_voltage 666 *clocks); 667 668 /** 669 * @get_power_profile_mode: Print all power profile modes to 670 * buffer. Star current mode. 671 */ 672 int (*get_power_profile_mode)(struct smu_context *smu, char *buf); 673 674 /** 675 * @set_power_profile_mode: Set a power profile mode. Also used to 676 * create/set custom power profile modes. 677 * &input: Power profile mode parameters. 678 * &size: Size of &input. 679 */ 680 int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size); 681 682 /** 683 * @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power 684 * management. 685 */ 686 int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable); 687 688 /** 689 * @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power 690 * management. 691 */ 692 int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable); 693 694 /** 695 * @read_sensor: Read data from a sensor. 696 * &sensor: Sensor to read data from. 697 * &data: Sensor reading. 698 * &size: Size of &data. 699 */ 700 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor, 701 void *data, uint32_t *size); 702 703 /** 704 * @pre_display_config_changed: Prepare GPU for a display configuration 705 * change. 706 * 707 * Disable display tracking and pin memory clock speed to maximum. Used 708 * in display component synchronization. 709 */ 710 int (*pre_display_config_changed)(struct smu_context *smu); 711 712 /** 713 * @display_config_changed: Notify the SMU of the current display 714 * configuration. 715 * 716 * Allows SMU to properly track blanking periods for memory clock 717 * adjustment. Used in display component synchronization. 718 */ 719 int (*display_config_changed)(struct smu_context *smu); 720 721 int (*apply_clocks_adjust_rules)(struct smu_context *smu); 722 723 /** 724 * @notify_smc_display_config: Applies display requirements to the 725 * current power state. 726 * 727 * Optimize deep sleep DCEFclk and mclk for the current display 728 * configuration. Used in display component synchronization. 729 */ 730 int (*notify_smc_display_config)(struct smu_context *smu); 731 732 /** 733 * @is_dpm_running: Check if DPM is running. 734 * 735 * Return: True if DPM is running, false otherwise. 736 */ 737 bool (*is_dpm_running)(struct smu_context *smu); 738 739 /** 740 * @get_fan_speed_pwm: Get the current fan speed in PWM. 741 */ 742 int (*get_fan_speed_pwm)(struct smu_context *smu, uint32_t *speed); 743 744 /** 745 * @get_fan_speed_rpm: Get the current fan speed in rpm. 746 */ 747 int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed); 748 749 /** 750 * @set_watermarks_table: Configure and upload the watermarks tables to 751 * the SMU. 752 */ 753 int (*set_watermarks_table)(struct smu_context *smu, 754 struct pp_smu_wm_range_sets *clock_ranges); 755 756 /** 757 * @get_thermal_temperature_range: Get safe thermal limits in Celcius. 758 */ 759 int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range); 760 761 /** 762 * @get_uclk_dpm_states: Get memory clock DPM levels in kHz. 763 * &clocks_in_khz: Array of DPM levels. 764 * &num_states: Elements in &clocks_in_khz. 765 */ 766 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states); 767 768 /** 769 * @set_default_od_settings: Set the overdrive tables to defaults. 770 */ 771 int (*set_default_od_settings)(struct smu_context *smu); 772 773 /** 774 * @set_performance_level: Set a performance level. 775 */ 776 int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level); 777 778 /** 779 * @display_disable_memory_clock_switch: Enable/disable dynamic memory 780 * clock switching. 781 * 782 * Disabling this feature forces memory clock speed to maximum. 783 * Enabling sets the minimum memory clock capable of driving the 784 * current display configuration. 785 */ 786 int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch); 787 788 /** 789 * @dump_pptable: Print the power play table to the system log. 790 */ 791 void (*dump_pptable)(struct smu_context *smu); 792 793 /** 794 * @get_power_limit: Get the device's power limits. 795 */ 796 int (*get_power_limit)(struct smu_context *smu, 797 uint32_t *current_power_limit, 798 uint32_t *default_power_limit, 799 uint32_t *max_power_limit); 800 801 /** 802 * @get_ppt_limit: Get the device's ppt limits. 803 */ 804 int (*get_ppt_limit)(struct smu_context *smu, uint32_t *ppt_limit, 805 enum smu_ppt_limit_type limit_type, enum smu_ppt_limit_level limit_level); 806 807 /** 808 * @set_df_cstate: Set data fabric cstate. 809 */ 810 int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state); 811 812 /** 813 * @allow_xgmi_power_down: Enable/disable external global memory 814 * interconnect power down. 815 */ 816 int (*allow_xgmi_power_down)(struct smu_context *smu, bool en); 817 818 /** 819 * @update_pcie_parameters: Update and upload the system's PCIe 820 * capabilites to the SMU. 821 * &pcie_gen_cap: Maximum allowed PCIe generation. 822 * &pcie_width_cap: Maximum allowed PCIe width. 823 */ 824 int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap); 825 826 /** 827 * @i2c_init: Initialize i2c. 828 * 829 * The i2c bus is used internally by the SMU voltage regulators and 830 * other devices. The i2c's EEPROM also stores bad page tables on boards 831 * with ECC. 832 */ 833 int (*i2c_init)(struct smu_context *smu); 834 835 /** 836 * @i2c_fini: Tear down i2c. 837 */ 838 void (*i2c_fini)(struct smu_context *smu); 839 840 /** 841 * @get_unique_id: Get the GPU's unique id. Used for asset tracking. 842 */ 843 void (*get_unique_id)(struct smu_context *smu); 844 845 /** 846 * @get_dpm_clock_table: Get a copy of the DPM clock table. 847 * 848 * Used by display component in bandwidth and watermark calculations. 849 */ 850 int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table); 851 852 /** 853 * @init_microcode: Request the SMU's firmware from the kernel. 854 */ 855 int (*init_microcode)(struct smu_context *smu); 856 857 /** 858 * @load_microcode: Load firmware onto the SMU. 859 */ 860 int (*load_microcode)(struct smu_context *smu); 861 862 /** 863 * @fini_microcode: Release the SMU's firmware. 864 */ 865 void (*fini_microcode)(struct smu_context *smu); 866 867 /** 868 * @init_smc_tables: Initialize the SMU tables. 869 */ 870 int (*init_smc_tables)(struct smu_context *smu); 871 872 /** 873 * @fini_smc_tables: Release the SMU tables. 874 */ 875 int (*fini_smc_tables)(struct smu_context *smu); 876 877 /** 878 * @init_power: Initialize the power gate table context. 879 */ 880 int (*init_power)(struct smu_context *smu); 881 882 /** 883 * @fini_power: Release the power gate table context. 884 */ 885 int (*fini_power)(struct smu_context *smu); 886 887 /** 888 * @check_fw_status: Check the SMU's firmware status. 889 * 890 * Return: Zero if check passes, negative errno on failure. 891 */ 892 int (*check_fw_status)(struct smu_context *smu); 893 894 /** 895 * @set_mp1_state: put SMU into a correct state for comming 896 * resume from runpm or gpu reset. 897 */ 898 int (*set_mp1_state)(struct smu_context *smu, 899 enum pp_mp1_state mp1_state); 900 901 /** 902 * @setup_pptable: Initialize the power play table and populate it with 903 * default values. 904 */ 905 int (*setup_pptable)(struct smu_context *smu); 906 907 /** 908 * @get_vbios_bootup_values: Get default boot values from the VBIOS. 909 */ 910 int (*get_vbios_bootup_values)(struct smu_context *smu); 911 912 /** 913 * @check_fw_version: Print driver and SMU interface versions to the 914 * system log. 915 * 916 * Interface mismatch is not a critical failure. 917 */ 918 int (*check_fw_version)(struct smu_context *smu); 919 920 /** 921 * @powergate_sdma: Power up/down system direct memory access. 922 */ 923 int (*powergate_sdma)(struct smu_context *smu, bool gate); 924 925 /** 926 * @set_gfx_cgpg: Enable/disable graphics engine course grain power 927 * gating. 928 */ 929 int (*set_gfx_cgpg)(struct smu_context *smu, bool enable); 930 931 /** 932 * @write_pptable: Write the power play table to the SMU. 933 */ 934 int (*write_pptable)(struct smu_context *smu); 935 936 /** 937 * @set_driver_table_location: Send the location of the driver table to 938 * the SMU. 939 */ 940 int (*set_driver_table_location)(struct smu_context *smu); 941 942 /** 943 * @set_tool_table_location: Send the location of the tool table to the 944 * SMU. 945 */ 946 int (*set_tool_table_location)(struct smu_context *smu); 947 948 /** 949 * @notify_memory_pool_location: Send the location of the memory pool to 950 * the SMU. 951 */ 952 int (*notify_memory_pool_location)(struct smu_context *smu); 953 954 /** 955 * @system_features_control: Enable/disable all SMU features. 956 */ 957 int (*system_features_control)(struct smu_context *smu, bool en); 958 959 /** 960 * @send_smc_msg_with_param: Send a message with a parameter to the SMU. 961 * &msg: Type of message. 962 * ¶m: Message parameter. 963 * &read_arg: SMU response (optional). 964 */ 965 int (*send_smc_msg_with_param)(struct smu_context *smu, 966 enum smu_message_type msg, uint32_t param, uint32_t *read_arg); 967 968 /** 969 * @send_smc_msg: Send a message to the SMU. 970 * &msg: Type of message. 971 * &read_arg: SMU response (optional). 972 */ 973 int (*send_smc_msg)(struct smu_context *smu, 974 enum smu_message_type msg, 975 uint32_t *read_arg); 976 977 /** 978 * @init_display_count: Notify the SMU of the number of display 979 * components in current display configuration. 980 */ 981 int (*init_display_count)(struct smu_context *smu, uint32_t count); 982 983 /** 984 * @set_allowed_mask: Notify the SMU of the features currently allowed 985 * by the driver. 986 */ 987 int (*set_allowed_mask)(struct smu_context *smu); 988 989 /** 990 * @get_enabled_mask: Get a mask of features that are currently enabled 991 * on the SMU. 992 * &feature_mask: Enabled feature mask. 993 */ 994 int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask); 995 996 /** 997 * @feature_is_enabled: Test if a feature is enabled. 998 * 999 * Return: One if enabled, zero if disabled. 1000 */ 1001 int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask); 1002 1003 /** 1004 * @disable_all_features_with_exception: Disable all features with 1005 * exception to those in &mask. 1006 */ 1007 int (*disable_all_features_with_exception)(struct smu_context *smu, 1008 enum smu_feature_mask mask); 1009 1010 /** 1011 * @notify_display_change: Enable fast memory clock switching. 1012 * 1013 * Allows for fine grained memory clock switching but has more stringent 1014 * timing requirements. 1015 */ 1016 int (*notify_display_change)(struct smu_context *smu); 1017 1018 /** 1019 * @set_power_limit: Set power limit in watts. 1020 */ 1021 int (*set_power_limit)(struct smu_context *smu, 1022 enum smu_ppt_limit_type limit_type, 1023 uint32_t limit); 1024 1025 /** 1026 * @init_max_sustainable_clocks: Populate max sustainable clock speed 1027 * table with values from the SMU. 1028 */ 1029 int (*init_max_sustainable_clocks)(struct smu_context *smu); 1030 1031 /** 1032 * @enable_thermal_alert: Enable thermal alert interrupts. 1033 */ 1034 int (*enable_thermal_alert)(struct smu_context *smu); 1035 1036 /** 1037 * @disable_thermal_alert: Disable thermal alert interrupts. 1038 */ 1039 int (*disable_thermal_alert)(struct smu_context *smu); 1040 1041 /** 1042 * @set_min_dcef_deep_sleep: Set a minimum display fabric deep sleep 1043 * clock speed in MHz. 1044 */ 1045 int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk); 1046 1047 /** 1048 * @display_clock_voltage_request: Set a hard minimum frequency 1049 * for a clock domain. 1050 */ 1051 int (*display_clock_voltage_request)(struct smu_context *smu, struct 1052 pp_display_clock_request 1053 *clock_req); 1054 1055 /** 1056 * @get_fan_control_mode: Get the current fan control mode. 1057 */ 1058 uint32_t (*get_fan_control_mode)(struct smu_context *smu); 1059 1060 /** 1061 * @set_fan_control_mode: Set the fan control mode. 1062 */ 1063 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode); 1064 1065 /** 1066 * @set_fan_speed_pwm: Set a static fan speed in PWM. 1067 */ 1068 int (*set_fan_speed_pwm)(struct smu_context *smu, uint32_t speed); 1069 1070 /** 1071 * @set_fan_speed_rpm: Set a static fan speed in rpm. 1072 */ 1073 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed); 1074 1075 /** 1076 * @set_xgmi_pstate: Set inter-chip global memory interconnect pstate. 1077 * &pstate: Pstate to set. D0 if Nonzero, D3 otherwise. 1078 */ 1079 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate); 1080 1081 /** 1082 * @gfx_off_control: Enable/disable graphics engine poweroff. 1083 */ 1084 int (*gfx_off_control)(struct smu_context *smu, bool enable); 1085 1086 1087 /** 1088 * @get_gfx_off_status: Get graphics engine poweroff status. 1089 * 1090 * Return: 1091 * 0 - GFXOFF(default). 1092 * 1 - Transition out of GFX State. 1093 * 2 - Not in GFXOFF. 1094 * 3 - Transition into GFXOFF. 1095 */ 1096 uint32_t (*get_gfx_off_status)(struct smu_context *smu); 1097 1098 /** 1099 * @register_irq_handler: Register interupt request handlers. 1100 */ 1101 int (*register_irq_handler)(struct smu_context *smu); 1102 1103 /** 1104 * @set_azalia_d3_pme: Wake the audio decode engine from d3 sleep. 1105 */ 1106 int (*set_azalia_d3_pme)(struct smu_context *smu); 1107 1108 /** 1109 * @get_max_sustainable_clocks_by_dc: Get a copy of the max sustainable 1110 * clock speeds table. 1111 * 1112 * Provides a way for the display component (DC) to get the max 1113 * sustainable clocks from the SMU. 1114 */ 1115 int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks); 1116 1117 /** 1118 * @baco_is_support: Check if GPU supports BACO (Bus Active, Chip Off). 1119 */ 1120 bool (*baco_is_support)(struct smu_context *smu); 1121 1122 /** 1123 * @baco_get_state: Get the current BACO state. 1124 * 1125 * Return: Current BACO state. 1126 */ 1127 enum smu_baco_state (*baco_get_state)(struct smu_context *smu); 1128 1129 /** 1130 * @baco_set_state: Enter/exit BACO. 1131 */ 1132 int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state); 1133 1134 /** 1135 * @baco_enter: Enter BACO. 1136 */ 1137 int (*baco_enter)(struct smu_context *smu); 1138 1139 /** 1140 * @baco_exit: Exit Baco. 1141 */ 1142 int (*baco_exit)(struct smu_context *smu); 1143 1144 /** 1145 * @mode1_reset_is_support: Check if GPU supports mode1 reset. 1146 */ 1147 bool (*mode1_reset_is_support)(struct smu_context *smu); 1148 /** 1149 * @mode2_reset_is_support: Check if GPU supports mode2 reset. 1150 */ 1151 bool (*mode2_reset_is_support)(struct smu_context *smu); 1152 1153 /** 1154 * @mode1_reset: Perform mode1 reset. 1155 * 1156 * Complete GPU reset. 1157 */ 1158 int (*mode1_reset)(struct smu_context *smu); 1159 1160 /** 1161 * @mode2_reset: Perform mode2 reset. 1162 * 1163 * Mode2 reset generally does not reset as many IPs as mode1 reset. The 1164 * IPs reset varies by asic. 1165 */ 1166 int (*mode2_reset)(struct smu_context *smu); 1167 1168 /** 1169 * @get_dpm_ultimate_freq: Get the hard frequency range of a clock 1170 * domain in MHz. 1171 */ 1172 int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); 1173 1174 /** 1175 * @set_soft_freq_limited_range: Set the soft frequency range of a clock 1176 * domain in MHz. 1177 */ 1178 int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max); 1179 1180 /** 1181 * @set_power_source: Notify the SMU of the current power source. 1182 */ 1183 int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src); 1184 1185 /** 1186 * @log_thermal_throttling_event: Print a thermal throttling warning to 1187 * the system's log. 1188 */ 1189 void (*log_thermal_throttling_event)(struct smu_context *smu); 1190 1191 /** 1192 * @get_pp_feature_mask: Print a human readable table of enabled 1193 * features to buffer. 1194 */ 1195 size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf); 1196 1197 /** 1198 * @set_pp_feature_mask: Request the SMU enable/disable features to 1199 * match those enabled in &new_mask. 1200 */ 1201 int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask); 1202 1203 /** 1204 * @get_gpu_metrics: Get a copy of the GPU metrics table from the SMU. 1205 * 1206 * Return: Size of &table 1207 */ 1208 ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table); 1209 1210 /** 1211 * @enable_mgpu_fan_boost: Enable multi-GPU fan boost. 1212 */ 1213 int (*enable_mgpu_fan_boost)(struct smu_context *smu); 1214 1215 /** 1216 * @gfx_ulv_control: Enable/disable ultra low voltage. 1217 */ 1218 int (*gfx_ulv_control)(struct smu_context *smu, bool enablement); 1219 1220 /** 1221 * @deep_sleep_control: Enable/disable deep sleep. 1222 */ 1223 int (*deep_sleep_control)(struct smu_context *smu, bool enablement); 1224 1225 /** 1226 * @get_fan_parameters: Get fan parameters. 1227 * 1228 * Get maximum fan speed from the power play table. 1229 */ 1230 int (*get_fan_parameters)(struct smu_context *smu); 1231 1232 /** 1233 * @post_init: Helper function for asic specific workarounds. 1234 */ 1235 int (*post_init)(struct smu_context *smu); 1236 1237 /** 1238 * @interrupt_work: Work task scheduled from SMU interrupt handler. 1239 */ 1240 void (*interrupt_work)(struct smu_context *smu); 1241 1242 /** 1243 * @gpo_control: Enable/disable graphics power optimization if supported. 1244 */ 1245 int (*gpo_control)(struct smu_context *smu, bool enablement); 1246 1247 /** 1248 * @gfx_state_change_set: Send the current graphics state to the SMU. 1249 */ 1250 int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state); 1251 1252 /** 1253 * @set_fine_grain_gfx_freq_parameters: Set fine grain graphics clock 1254 * parameters to defaults. 1255 */ 1256 int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu); 1257 1258 /** 1259 * @smu_handle_passthrough_sbr: Send message to SMU about special handling for SBR. 1260 */ 1261 int (*smu_handle_passthrough_sbr)(struct smu_context *smu, bool enable); 1262 1263 /** 1264 * @wait_for_event: Wait for events from SMU. 1265 */ 1266 int (*wait_for_event)(struct smu_context *smu, 1267 enum smu_event_type event, uint64_t event_arg); 1268 1269 /** 1270 * @sned_hbm_bad_pages_num: message SMU to update bad page number 1271 * of SMUBUS table. 1272 */ 1273 int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size); 1274 1275 /** 1276 * @get_ecc_table: message SMU to get ECC INFO table. 1277 */ 1278 ssize_t (*get_ecc_info)(struct smu_context *smu, void *table); 1279 1280 1281 /** 1282 * @stb_collect_info: Collects Smart Trace Buffers data. 1283 */ 1284 int (*stb_collect_info)(struct smu_context *smu, void *buf, uint32_t size); 1285 1286 /** 1287 * @get_default_config_table_settings: Get the ASIC default DriverSmuConfig table settings. 1288 */ 1289 int (*get_default_config_table_settings)(struct smu_context *smu, struct config_table_setting *table); 1290 1291 /** 1292 * @set_config_table: Apply the input DriverSmuConfig table settings. 1293 */ 1294 int (*set_config_table)(struct smu_context *smu, struct config_table_setting *table); 1295 1296 /** 1297 * @sned_hbm_bad_channel_flag: message SMU to update bad channel info 1298 * of SMUBUS table. 1299 */ 1300 int (*send_hbm_bad_channel_flag)(struct smu_context *smu, uint32_t size); 1301 }; 1302 1303 typedef enum { 1304 METRICS_CURR_GFXCLK, 1305 METRICS_CURR_SOCCLK, 1306 METRICS_CURR_UCLK, 1307 METRICS_CURR_VCLK, 1308 METRICS_CURR_VCLK1, 1309 METRICS_CURR_DCLK, 1310 METRICS_CURR_DCLK1, 1311 METRICS_CURR_FCLK, 1312 METRICS_CURR_DCEFCLK, 1313 METRICS_AVERAGE_CPUCLK, 1314 METRICS_AVERAGE_GFXCLK, 1315 METRICS_AVERAGE_SOCCLK, 1316 METRICS_AVERAGE_FCLK, 1317 METRICS_AVERAGE_UCLK, 1318 METRICS_AVERAGE_VCLK, 1319 METRICS_AVERAGE_DCLK, 1320 METRICS_AVERAGE_GFXACTIVITY, 1321 METRICS_AVERAGE_MEMACTIVITY, 1322 METRICS_AVERAGE_VCNACTIVITY, 1323 METRICS_AVERAGE_SOCKETPOWER, 1324 METRICS_TEMPERATURE_EDGE, 1325 METRICS_TEMPERATURE_HOTSPOT, 1326 METRICS_TEMPERATURE_MEM, 1327 METRICS_TEMPERATURE_VRGFX, 1328 METRICS_TEMPERATURE_VRSOC, 1329 METRICS_TEMPERATURE_VRMEM, 1330 METRICS_THROTTLER_STATUS, 1331 METRICS_CURR_FANSPEED, 1332 METRICS_VOLTAGE_VDDSOC, 1333 METRICS_VOLTAGE_VDDGFX, 1334 METRICS_SS_APU_SHARE, 1335 METRICS_SS_DGPU_SHARE, 1336 } MetricsMember_t; 1337 1338 enum smu_cmn2asic_mapping_type { 1339 CMN2ASIC_MAPPING_MSG, 1340 CMN2ASIC_MAPPING_CLK, 1341 CMN2ASIC_MAPPING_FEATURE, 1342 CMN2ASIC_MAPPING_TABLE, 1343 CMN2ASIC_MAPPING_PWR, 1344 CMN2ASIC_MAPPING_WORKLOAD, 1345 }; 1346 1347 #define MSG_MAP(msg, index, valid_in_vf) \ 1348 [SMU_MSG_##msg] = {1, (index), (valid_in_vf)} 1349 1350 #define CLK_MAP(clk, index) \ 1351 [SMU_##clk] = {1, (index)} 1352 1353 #define FEA_MAP(fea) \ 1354 [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT} 1355 1356 #define FEA_MAP_REVERSE(fea) \ 1357 [SMU_FEATURE_DPM_##fea##_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1358 1359 #define FEA_MAP_HALF_REVERSE(fea) \ 1360 [SMU_FEATURE_DPM_##fea##CLK_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1361 1362 #define TAB_MAP(tab) \ 1363 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1364 1365 #define TAB_MAP_VALID(tab) \ 1366 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1367 1368 #define TAB_MAP_INVALID(tab) \ 1369 [SMU_TABLE_##tab] = {0, TABLE_##tab} 1370 1371 #define PWR_MAP(tab) \ 1372 [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab} 1373 1374 #define WORKLOAD_MAP(profile, workload) \ 1375 [profile] = {1, (workload)} 1376 1377 /** 1378 * smu_memcpy_trailing - Copy the end of one structure into the middle of another 1379 * 1380 * @dst: Pointer to destination struct 1381 * @first_dst_member: The member name in @dst where the overwrite begins 1382 * @last_dst_member: The member name in @dst where the overwrite ends after 1383 * @src: Pointer to the source struct 1384 * @first_src_member: The member name in @src where the copy begins 1385 * 1386 */ 1387 #define smu_memcpy_trailing(dst, first_dst_member, last_dst_member, \ 1388 src, first_src_member) \ 1389 ({ \ 1390 size_t __src_offset = offsetof(typeof(*(src)), first_src_member); \ 1391 size_t __src_size = sizeof(*(src)) - __src_offset; \ 1392 size_t __dst_offset = offsetof(typeof(*(dst)), first_dst_member); \ 1393 size_t __dst_size = offsetofend(typeof(*(dst)), last_dst_member) - \ 1394 __dst_offset; \ 1395 BUILD_BUG_ON(__src_size != __dst_size); \ 1396 __builtin_memcpy((u8 *)(dst) + __dst_offset, \ 1397 (u8 *)(src) + __src_offset, \ 1398 __dst_size); \ 1399 }) 1400 1401 #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4) 1402 int smu_get_power_limit(void *handle, 1403 uint32_t *limit, 1404 enum pp_power_limit_level pp_limit_level, 1405 enum pp_power_type pp_power_type); 1406 1407 bool smu_mode1_reset_is_support(struct smu_context *smu); 1408 bool smu_mode2_reset_is_support(struct smu_context *smu); 1409 int smu_mode1_reset(struct smu_context *smu); 1410 1411 extern const struct amd_ip_funcs smu_ip_funcs; 1412 1413 bool is_support_sw_smu(struct amdgpu_device *adev); 1414 bool is_support_cclk_dpm(struct amdgpu_device *adev); 1415 int smu_write_watermarks_table(struct smu_context *smu); 1416 1417 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1418 uint32_t *min, uint32_t *max); 1419 1420 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1421 uint32_t min, uint32_t max); 1422 1423 int smu_set_ac_dc(struct smu_context *smu); 1424 1425 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en); 1426 1427 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value); 1428 1429 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable); 1430 1431 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 1432 uint64_t event_arg); 1433 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc); 1434 int smu_stb_collect_info(struct smu_context *smu, void *buff, uint32_t size); 1435 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev); 1436 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size); 1437 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size); 1438 #endif 1439 #endif 1440