1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 #ifndef __AMDGPU_SMU_H__
23 #define __AMDGPU_SMU_H__
24 
25 #include "amdgpu.h"
26 #include "kgd_pp_interface.h"
27 #include "dm_pp_interface.h"
28 #include "dm_pp_smu.h"
29 #include "smu_types.h"
30 #include "linux/firmware.h"
31 
32 #define SMU_THERMAL_MINIMUM_ALERT_TEMP		0
33 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP		255
34 #define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES	1000
35 #define SMU_FW_NAME_LEN			0x24
36 
37 #define SMU_DPM_USER_PROFILE_RESTORE (1 << 0)
38 #define SMU_CUSTOM_FAN_SPEED_RPM     (1 << 1)
39 #define SMU_CUSTOM_FAN_SPEED_PWM     (1 << 2)
40 
41 // Power Throttlers
42 #define SMU_THROTTLER_PPT0_BIT			0
43 #define SMU_THROTTLER_PPT1_BIT			1
44 #define SMU_THROTTLER_PPT2_BIT			2
45 #define SMU_THROTTLER_PPT3_BIT			3
46 #define SMU_THROTTLER_SPL_BIT			4
47 #define SMU_THROTTLER_FPPT_BIT			5
48 #define SMU_THROTTLER_SPPT_BIT			6
49 #define SMU_THROTTLER_SPPT_APU_BIT		7
50 
51 // Current Throttlers
52 #define SMU_THROTTLER_TDC_GFX_BIT		16
53 #define SMU_THROTTLER_TDC_SOC_BIT		17
54 #define SMU_THROTTLER_TDC_MEM_BIT		18
55 #define SMU_THROTTLER_TDC_VDD_BIT		19
56 #define SMU_THROTTLER_TDC_CVIP_BIT		20
57 #define SMU_THROTTLER_EDC_CPU_BIT		21
58 #define SMU_THROTTLER_EDC_GFX_BIT		22
59 #define SMU_THROTTLER_APCC_BIT			23
60 
61 // Temperature
62 #define SMU_THROTTLER_TEMP_GPU_BIT		32
63 #define SMU_THROTTLER_TEMP_CORE_BIT		33
64 #define SMU_THROTTLER_TEMP_MEM_BIT		34
65 #define SMU_THROTTLER_TEMP_EDGE_BIT		35
66 #define SMU_THROTTLER_TEMP_HOTSPOT_BIT		36
67 #define SMU_THROTTLER_TEMP_SOC_BIT		37
68 #define SMU_THROTTLER_TEMP_VR_GFX_BIT		38
69 #define SMU_THROTTLER_TEMP_VR_SOC_BIT		39
70 #define SMU_THROTTLER_TEMP_VR_MEM0_BIT		40
71 #define SMU_THROTTLER_TEMP_VR_MEM1_BIT		41
72 #define SMU_THROTTLER_TEMP_LIQUID0_BIT		42
73 #define SMU_THROTTLER_TEMP_LIQUID1_BIT		43
74 #define SMU_THROTTLER_VRHOT0_BIT		44
75 #define SMU_THROTTLER_VRHOT1_BIT		45
76 #define SMU_THROTTLER_PROCHOT_CPU_BIT		46
77 #define SMU_THROTTLER_PROCHOT_GFX_BIT		47
78 
79 // Other
80 #define SMU_THROTTLER_PPM_BIT			56
81 #define SMU_THROTTLER_FIT_BIT			57
82 
83 struct smu_hw_power_state {
84 	unsigned int magic;
85 };
86 
87 struct smu_power_state;
88 
89 enum smu_state_ui_label {
90 	SMU_STATE_UI_LABEL_NONE,
91 	SMU_STATE_UI_LABEL_BATTERY,
92 	SMU_STATE_UI_TABEL_MIDDLE_LOW,
93 	SMU_STATE_UI_LABEL_BALLANCED,
94 	SMU_STATE_UI_LABEL_MIDDLE_HIGHT,
95 	SMU_STATE_UI_LABEL_PERFORMANCE,
96 	SMU_STATE_UI_LABEL_BACO,
97 };
98 
99 enum smu_state_classification_flag {
100 	SMU_STATE_CLASSIFICATION_FLAG_BOOT                     = 0x0001,
101 	SMU_STATE_CLASSIFICATION_FLAG_THERMAL                  = 0x0002,
102 	SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE      = 0x0004,
103 	SMU_STATE_CLASSIFICATION_FLAG_RESET                    = 0x0008,
104 	SMU_STATE_CLASSIFICATION_FLAG_FORCED                   = 0x0010,
105 	SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE      = 0x0020,
106 	SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE      = 0x0040,
107 	SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE           = 0x0080,
108 	SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE   = 0x0100,
109 	SMU_STATE_CLASSIFICATION_FLAG_UVD                      = 0x0200,
110 	SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW       = 0x0400,
111 	SMU_STATE_CLASSIFICATION_FLAG_ACPI                     = 0x0800,
112 	SMU_STATE_CLASSIFICATION_FLAG_HD2                      = 0x1000,
113 	SMU_STATE_CLASSIFICATION_FLAG_UVD_HD                   = 0x2000,
114 	SMU_STATE_CLASSIFICATION_FLAG_UVD_SD                   = 0x4000,
115 	SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE      = 0x8000,
116 	SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE   = 0x10000,
117 	SMU_STATE_CLASSIFICATION_FLAG_BACO                     = 0x20000,
118 	SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2      = 0x40000,
119 	SMU_STATE_CLASSIFICATION_FLAG_ULV                      = 0x80000,
120 	SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC                  = 0x100000,
121 };
122 
123 struct smu_state_classification_block {
124 	enum smu_state_ui_label         ui_label;
125 	enum smu_state_classification_flag  flags;
126 	int                          bios_index;
127 	bool                      temporary_state;
128 	bool                      to_be_deleted;
129 };
130 
131 struct smu_state_pcie_block {
132 	unsigned int lanes;
133 };
134 
135 enum smu_refreshrate_source {
136 	SMU_REFRESHRATE_SOURCE_EDID,
137 	SMU_REFRESHRATE_SOURCE_EXPLICIT
138 };
139 
140 struct smu_state_display_block {
141 	bool              disable_frame_modulation;
142 	bool              limit_refreshrate;
143 	enum smu_refreshrate_source refreshrate_source;
144 	int                  explicit_refreshrate;
145 	int                  edid_refreshrate_index;
146 	bool              enable_vari_bright;
147 };
148 
149 struct smu_state_memory_block {
150 	bool              dll_off;
151 	uint8_t                 m3arb;
152 	uint8_t                 unused[3];
153 };
154 
155 struct smu_state_software_algorithm_block {
156 	bool disable_load_balancing;
157 	bool enable_sleep_for_timestamps;
158 };
159 
160 struct smu_temperature_range {
161 	int min;
162 	int max;
163 	int edge_emergency_max;
164 	int hotspot_min;
165 	int hotspot_crit_max;
166 	int hotspot_emergency_max;
167 	int mem_min;
168 	int mem_crit_max;
169 	int mem_emergency_max;
170 	int software_shutdown_temp;
171 };
172 
173 struct smu_state_validation_block {
174 	bool single_display_only;
175 	bool disallow_on_dc;
176 	uint8_t supported_power_levels;
177 };
178 
179 struct smu_uvd_clocks {
180 	uint32_t vclk;
181 	uint32_t dclk;
182 };
183 
184 /**
185 * Structure to hold a SMU Power State.
186 */
187 struct smu_power_state {
188 	uint32_t                                      id;
189 	struct list_head                              ordered_list;
190 	struct list_head                              all_states_list;
191 
192 	struct smu_state_classification_block         classification;
193 	struct smu_state_validation_block             validation;
194 	struct smu_state_pcie_block                   pcie;
195 	struct smu_state_display_block                display;
196 	struct smu_state_memory_block                 memory;
197 	struct smu_state_software_algorithm_block     software;
198 	struct smu_uvd_clocks                         uvd_clocks;
199 	struct smu_hw_power_state                     hardware;
200 };
201 
202 enum smu_power_src_type
203 {
204 	SMU_POWER_SOURCE_AC,
205 	SMU_POWER_SOURCE_DC,
206 	SMU_POWER_SOURCE_COUNT,
207 };
208 
209 enum smu_ppt_limit_type
210 {
211 	SMU_DEFAULT_PPT_LIMIT = 0,
212 	SMU_FAST_PPT_LIMIT,
213 };
214 
215 enum smu_ppt_limit_level
216 {
217 	SMU_PPT_LIMIT_MIN = -1,
218 	SMU_PPT_LIMIT_CURRENT,
219 	SMU_PPT_LIMIT_DEFAULT,
220 	SMU_PPT_LIMIT_MAX,
221 };
222 
223 enum smu_memory_pool_size
224 {
225     SMU_MEMORY_POOL_SIZE_ZERO   = 0,
226     SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000,
227     SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000,
228     SMU_MEMORY_POOL_SIZE_1_GB   = 0x40000000,
229     SMU_MEMORY_POOL_SIZE_2_GB   = 0x80000000,
230 };
231 
232 struct smu_user_dpm_profile {
233 	uint32_t fan_mode;
234 	uint32_t power_limit;
235 	uint32_t fan_speed_pwm;
236 	uint32_t fan_speed_rpm;
237 	uint32_t flags;
238 	uint32_t user_od;
239 
240 	/* user clock state information */
241 	uint32_t clk_mask[SMU_CLK_COUNT];
242 	uint32_t clk_dependency;
243 };
244 
245 #define SMU_TABLE_INIT(tables, table_id, s, a, d)	\
246 	do {						\
247 		tables[table_id].size = s;		\
248 		tables[table_id].align = a;		\
249 		tables[table_id].domain = d;		\
250 	} while (0)
251 
252 struct smu_table {
253 	uint64_t size;
254 	uint32_t align;
255 	uint8_t domain;
256 	uint64_t mc_address;
257 	void *cpu_addr;
258 	struct amdgpu_bo *bo;
259 };
260 
261 enum smu_perf_level_designation {
262 	PERF_LEVEL_ACTIVITY,
263 	PERF_LEVEL_POWER_CONTAINMENT,
264 };
265 
266 struct smu_performance_level {
267 	uint32_t core_clock;
268 	uint32_t memory_clock;
269 	uint32_t vddc;
270 	uint32_t vddci;
271 	uint32_t non_local_mem_freq;
272 	uint32_t non_local_mem_width;
273 };
274 
275 struct smu_clock_info {
276 	uint32_t min_mem_clk;
277 	uint32_t max_mem_clk;
278 	uint32_t min_eng_clk;
279 	uint32_t max_eng_clk;
280 	uint32_t min_bus_bandwidth;
281 	uint32_t max_bus_bandwidth;
282 };
283 
284 struct smu_bios_boot_up_values
285 {
286 	uint32_t			revision;
287 	uint32_t			gfxclk;
288 	uint32_t			uclk;
289 	uint32_t			socclk;
290 	uint32_t			dcefclk;
291 	uint32_t			eclk;
292 	uint32_t			vclk;
293 	uint32_t			dclk;
294 	uint16_t			vddc;
295 	uint16_t			vddci;
296 	uint16_t			mvddc;
297 	uint16_t			vdd_gfx;
298 	uint8_t				cooling_id;
299 	uint32_t			pp_table_id;
300 	uint32_t			format_revision;
301 	uint32_t			content_revision;
302 	uint32_t			fclk;
303 	uint32_t			lclk;
304 	uint32_t			firmware_caps;
305 };
306 
307 enum smu_table_id
308 {
309 	SMU_TABLE_PPTABLE = 0,
310 	SMU_TABLE_WATERMARKS,
311 	SMU_TABLE_CUSTOM_DPM,
312 	SMU_TABLE_DPMCLOCKS,
313 	SMU_TABLE_AVFS,
314 	SMU_TABLE_AVFS_PSM_DEBUG,
315 	SMU_TABLE_AVFS_FUSE_OVERRIDE,
316 	SMU_TABLE_PMSTATUSLOG,
317 	SMU_TABLE_SMU_METRICS,
318 	SMU_TABLE_DRIVER_SMU_CONFIG,
319 	SMU_TABLE_ACTIVITY_MONITOR_COEFF,
320 	SMU_TABLE_OVERDRIVE,
321 	SMU_TABLE_I2C_COMMANDS,
322 	SMU_TABLE_PACE,
323 	SMU_TABLE_ECCINFO,
324 	SMU_TABLE_COMBO_PPTABLE,
325 	SMU_TABLE_COUNT,
326 };
327 
328 struct smu_table_context
329 {
330 	void				*power_play_table;
331 	uint32_t			power_play_table_size;
332 	void				*hardcode_pptable;
333 	unsigned long			metrics_time;
334 	void				*metrics_table;
335 	void				*clocks_table;
336 	void				*watermarks_table;
337 
338 	void				*max_sustainable_clocks;
339 	struct smu_bios_boot_up_values	boot_values;
340 	void				*driver_pptable;
341 	void				*combo_pptable;
342 	void                            *ecc_table;
343 	void				*driver_smu_config_table;
344 	struct smu_table		tables[SMU_TABLE_COUNT];
345 	/*
346 	 * The driver table is just a staging buffer for
347 	 * uploading/downloading content from the SMU.
348 	 *
349 	 * And the table_id for SMU_MSG_TransferTableSmu2Dram/
350 	 * SMU_MSG_TransferTableDram2Smu instructs SMU
351 	 * which content driver is interested.
352 	 */
353 	struct smu_table		driver_table;
354 	struct smu_table		memory_pool;
355 	struct smu_table		dummy_read_1_table;
356 	uint8_t                         thermal_controller_type;
357 
358 	void				*overdrive_table;
359 	void                            *boot_overdrive_table;
360 	void				*user_overdrive_table;
361 
362 	uint32_t			gpu_metrics_table_size;
363 	void				*gpu_metrics_table;
364 };
365 
366 struct smu_dpm_context {
367 	uint32_t dpm_context_size;
368 	void *dpm_context;
369 	void *golden_dpm_context;
370 	enum amd_dpm_forced_level dpm_level;
371 	enum amd_dpm_forced_level saved_dpm_level;
372 	enum amd_dpm_forced_level requested_dpm_level;
373 	struct smu_power_state *dpm_request_power_state;
374 	struct smu_power_state *dpm_current_power_state;
375 	struct mclock_latency_table *mclk_latency_table;
376 };
377 
378 struct smu_power_gate {
379 	bool uvd_gated;
380 	bool vce_gated;
381 	atomic_t vcn_gated;
382 	atomic_t jpeg_gated;
383 };
384 
385 struct smu_power_context {
386 	void *power_context;
387 	uint32_t power_context_size;
388 	struct smu_power_gate power_gate;
389 };
390 
391 #define SMU_FEATURE_MAX	(64)
392 struct smu_feature
393 {
394 	uint32_t feature_num;
395 	DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
396 	DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
397 };
398 
399 struct smu_clocks {
400 	uint32_t engine_clock;
401 	uint32_t memory_clock;
402 	uint32_t bus_bandwidth;
403 	uint32_t engine_clock_in_sr;
404 	uint32_t dcef_clock;
405 	uint32_t dcef_clock_in_sr;
406 };
407 
408 #define MAX_REGULAR_DPM_NUM 16
409 struct mclk_latency_entries {
410 	uint32_t  frequency;
411 	uint32_t  latency;
412 };
413 struct mclock_latency_table {
414 	uint32_t  count;
415 	struct mclk_latency_entries  entries[MAX_REGULAR_DPM_NUM];
416 };
417 
418 enum smu_reset_mode
419 {
420     SMU_RESET_MODE_0,
421     SMU_RESET_MODE_1,
422     SMU_RESET_MODE_2,
423 };
424 
425 enum smu_baco_state
426 {
427 	SMU_BACO_STATE_ENTER = 0,
428 	SMU_BACO_STATE_EXIT,
429 };
430 
431 struct smu_baco_context
432 {
433 	uint32_t state;
434 	bool platform_support;
435 	bool maco_support;
436 };
437 
438 struct smu_freq_info {
439 	uint32_t min;
440 	uint32_t max;
441 	uint32_t freq_level;
442 };
443 
444 struct pstates_clk_freq {
445 	uint32_t			min;
446 	uint32_t			standard;
447 	uint32_t			peak;
448 	struct smu_freq_info		custom;
449 	struct smu_freq_info		curr;
450 };
451 
452 struct smu_umd_pstate_table {
453 	struct pstates_clk_freq		gfxclk_pstate;
454 	struct pstates_clk_freq		socclk_pstate;
455 	struct pstates_clk_freq		uclk_pstate;
456 	struct pstates_clk_freq		vclk_pstate;
457 	struct pstates_clk_freq		dclk_pstate;
458 	struct pstates_clk_freq		fclk_pstate;
459 };
460 
461 struct cmn2asic_msg_mapping {
462 	int	valid_mapping;
463 	int	map_to;
464 	int	valid_in_vf;
465 };
466 
467 struct cmn2asic_mapping {
468 	int	valid_mapping;
469 	int	map_to;
470 };
471 
472 struct stb_context {
473 	uint32_t stb_buf_size;
474 	bool enabled;
475 	spinlock_t lock;
476 };
477 
478 #define WORKLOAD_POLICY_MAX 7
479 
480 struct smu_context
481 {
482 	struct amdgpu_device            *adev;
483 	struct amdgpu_irq_src		irq_source;
484 
485 	const struct pptable_funcs	*ppt_funcs;
486 	const struct cmn2asic_msg_mapping	*message_map;
487 	const struct cmn2asic_mapping	*clock_map;
488 	const struct cmn2asic_mapping	*feature_map;
489 	const struct cmn2asic_mapping	*table_map;
490 	const struct cmn2asic_mapping	*pwr_src_map;
491 	const struct cmn2asic_mapping	*workload_map;
492 	struct mutex			message_lock;
493 	uint64_t pool_size;
494 
495 	struct smu_table_context	smu_table;
496 	struct smu_dpm_context		smu_dpm;
497 	struct smu_power_context	smu_power;
498 	struct smu_feature		smu_feature;
499 	struct amd_pp_display_configuration  *display_config;
500 	struct smu_baco_context		smu_baco;
501 	struct smu_temperature_range	thermal_range;
502 	void *od_settings;
503 
504 	struct smu_umd_pstate_table	pstate_table;
505 	uint32_t pstate_sclk;
506 	uint32_t pstate_mclk;
507 
508 	bool od_enabled;
509 	uint32_t current_power_limit;
510 	uint32_t default_power_limit;
511 	uint32_t max_power_limit;
512 
513 	/* soft pptable */
514 	uint32_t ppt_offset_bytes;
515 	uint32_t ppt_size_bytes;
516 	uint8_t  *ppt_start_addr;
517 
518 	bool support_power_containment;
519 	bool disable_watermark;
520 
521 #define WATERMARKS_EXIST	(1 << 0)
522 #define WATERMARKS_LOADED	(1 << 1)
523 	uint32_t watermarks_bitmap;
524 	uint32_t hard_min_uclk_req_from_dal;
525 	bool disable_uclk_switch;
526 
527 	uint32_t workload_mask;
528 	uint32_t workload_prority[WORKLOAD_POLICY_MAX];
529 	uint32_t workload_setting[WORKLOAD_POLICY_MAX];
530 	uint32_t power_profile_mode;
531 	uint32_t default_power_profile_mode;
532 	bool pm_enabled;
533 	bool is_apu;
534 
535 	uint32_t smc_driver_if_version;
536 	uint32_t smc_fw_if_version;
537 	uint32_t smc_fw_version;
538 
539 	bool uploading_custom_pp_table;
540 	bool dc_controlled_by_gpio;
541 
542 	struct work_struct throttling_logging_work;
543 	atomic64_t throttle_int_counter;
544 	struct work_struct interrupt_work;
545 
546 	unsigned fan_max_rpm;
547 	unsigned manual_fan_speed_pwm;
548 
549 	uint32_t gfx_default_hard_min_freq;
550 	uint32_t gfx_default_soft_max_freq;
551 	uint32_t gfx_actual_hard_min_freq;
552 	uint32_t gfx_actual_soft_max_freq;
553 
554 	/* APU only */
555 	uint32_t cpu_default_soft_min_freq;
556 	uint32_t cpu_default_soft_max_freq;
557 	uint32_t cpu_actual_soft_min_freq;
558 	uint32_t cpu_actual_soft_max_freq;
559 	uint32_t cpu_core_id_select;
560 	uint16_t cpu_core_num;
561 
562 	struct smu_user_dpm_profile user_dpm_profile;
563 
564 	struct stb_context stb_context;
565 
566 	struct firmware pptable_firmware;
567 
568 	u32 param_reg;
569 	u32 msg_reg;
570 	u32 resp_reg;
571 };
572 
573 struct i2c_adapter;
574 
575 /**
576  * struct pptable_funcs - Callbacks used to interact with the SMU.
577  */
578 struct pptable_funcs {
579 	/**
580 	 * @run_btc: Calibrate voltage/frequency curve to fit the system's
581 	 *           power delivery and voltage margins. Required for adaptive
582 	 *           voltage frequency scaling (AVFS).
583 	 */
584 	int (*run_btc)(struct smu_context *smu);
585 
586 	/**
587 	 * @get_allowed_feature_mask: Get allowed feature mask.
588 	 * &feature_mask: Array to store feature mask.
589 	 * &num: Elements in &feature_mask.
590 	 */
591 	int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
592 
593 	/**
594 	 * @get_current_power_state: Get the current power state.
595 	 *
596 	 * Return: Current power state on success, negative errno on failure.
597 	 */
598 	enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu);
599 
600 	/**
601 	 * @set_default_dpm_table: Retrieve the default overdrive settings from
602 	 *                         the SMU.
603 	 */
604 	int (*set_default_dpm_table)(struct smu_context *smu);
605 
606 	int (*set_power_state)(struct smu_context *smu);
607 
608 	/**
609 	 * @populate_umd_state_clk: Populate the UMD power state table with
610 	 *                          defaults.
611 	 */
612 	int (*populate_umd_state_clk)(struct smu_context *smu);
613 
614 	/**
615 	 * @print_clk_levels: Print DPM clock levels for a clock domain
616 	 *                    to buffer. Star current level.
617 	 *
618 	 * Used for sysfs interfaces.
619 	 * Return: Number of characters written to the buffer
620 	 */
621 	int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
622 
623 	/**
624 	 * @emit_clk_levels: Print DPM clock levels for a clock domain
625 	 *                    to buffer using sysfs_emit_at. Star current level.
626 	 *
627 	 * Used for sysfs interfaces.
628 	 * &buf: sysfs buffer
629 	 * &offset: offset within buffer to start printing, which is updated by the
630 	 * function.
631 	 *
632 	 * Return: 0 on Success or Negative to indicate an error occurred.
633 	 */
634 	int (*emit_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf, int *offset);
635 
636 	/**
637 	 * @force_clk_levels: Set a range of allowed DPM levels for a clock
638 	 *                    domain.
639 	 * &clk_type: Clock domain.
640 	 * &mask: Range of allowed DPM levels.
641 	 */
642 	int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
643 
644 	/**
645 	 * @od_edit_dpm_table: Edit the custom overdrive DPM table.
646 	 * &type: Type of edit.
647 	 * &input: Edit parameters.
648 	 * &size: Size of &input.
649 	 */
650 	int (*od_edit_dpm_table)(struct smu_context *smu,
651 				 enum PP_OD_DPM_TABLE_COMMAND type,
652 				 long *input, uint32_t size);
653 
654 	/**
655 	 * @restore_user_od_settings: Restore the user customized
656 	 *                            OD settings on S3/S4/Runpm resume.
657 	 */
658 	int (*restore_user_od_settings)(struct smu_context *smu);
659 
660 	/**
661 	 * @get_clock_by_type_with_latency: Get the speed and latency of a clock
662 	 *                                  domain.
663 	 */
664 	int (*get_clock_by_type_with_latency)(struct smu_context *smu,
665 					      enum smu_clk_type clk_type,
666 					      struct
667 					      pp_clock_levels_with_latency
668 					      *clocks);
669 	/**
670 	 * @get_clock_by_type_with_voltage: Get the speed and voltage of a clock
671 	 *                                  domain.
672 	 */
673 	int (*get_clock_by_type_with_voltage)(struct smu_context *smu,
674 					      enum amd_pp_clock_type type,
675 					      struct
676 					      pp_clock_levels_with_voltage
677 					      *clocks);
678 
679 	/**
680 	 * @get_power_profile_mode: Print all power profile modes to
681 	 *                          buffer. Star current mode.
682 	 */
683 	int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
684 
685 	/**
686 	 * @set_power_profile_mode: Set a power profile mode. Also used to
687 	 *                          create/set custom power profile modes.
688 	 * &input: Power profile mode parameters.
689 	 * &size: Size of &input.
690 	 */
691 	int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
692 
693 	/**
694 	 * @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power
695 	 *                      management.
696 	 */
697 	int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable);
698 
699 	/**
700 	 * @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power
701 	 *                       management.
702 	 */
703 	int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable);
704 
705 	/**
706 	 * @set_gfx_power_up_by_imu: Enable GFX engine with IMU
707 	 */
708 	int (*set_gfx_power_up_by_imu)(struct smu_context *smu);
709 
710 	/**
711 	 * @read_sensor: Read data from a sensor.
712 	 * &sensor: Sensor to read data from.
713 	 * &data: Sensor reading.
714 	 * &size: Size of &data.
715 	 */
716 	int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
717 			   void *data, uint32_t *size);
718 
719 	/**
720 	 * @pre_display_config_changed: Prepare GPU for a display configuration
721 	 *                              change.
722 	 *
723 	 * Disable display tracking and pin memory clock speed to maximum. Used
724 	 * in display component synchronization.
725 	 */
726 	int (*pre_display_config_changed)(struct smu_context *smu);
727 
728 	/**
729 	 * @display_config_changed: Notify the SMU of the current display
730 	 *                          configuration.
731 	 *
732 	 * Allows SMU to properly track blanking periods for memory clock
733 	 * adjustment. Used in display component synchronization.
734 	 */
735 	int (*display_config_changed)(struct smu_context *smu);
736 
737 	int (*apply_clocks_adjust_rules)(struct smu_context *smu);
738 
739 	/**
740 	 * @notify_smc_display_config: Applies display requirements to the
741 	 *                             current power state.
742 	 *
743 	 * Optimize deep sleep DCEFclk and mclk for the current display
744 	 * configuration. Used in display component synchronization.
745 	 */
746 	int (*notify_smc_display_config)(struct smu_context *smu);
747 
748 	/**
749 	 * @is_dpm_running: Check if DPM is running.
750 	 *
751 	 * Return: True if DPM is running, false otherwise.
752 	 */
753 	bool (*is_dpm_running)(struct smu_context *smu);
754 
755 	/**
756 	 * @get_fan_speed_pwm: Get the current fan speed in PWM.
757 	 */
758 	int (*get_fan_speed_pwm)(struct smu_context *smu, uint32_t *speed);
759 
760 	/**
761 	 * @get_fan_speed_rpm: Get the current fan speed in rpm.
762 	 */
763 	int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
764 
765 	/**
766 	 * @set_watermarks_table: Configure and upload the watermarks tables to
767 	 *                        the SMU.
768 	 */
769 	int (*set_watermarks_table)(struct smu_context *smu,
770 				    struct pp_smu_wm_range_sets *clock_ranges);
771 
772 	/**
773 	 * @get_thermal_temperature_range: Get safe thermal limits in Celcius.
774 	 */
775 	int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range);
776 
777 	/**
778 	 * @get_uclk_dpm_states: Get memory clock DPM levels in kHz.
779 	 * &clocks_in_khz: Array of DPM levels.
780 	 * &num_states: Elements in &clocks_in_khz.
781 	 */
782 	int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
783 
784 	/**
785 	 * @set_default_od_settings: Set the overdrive tables to defaults.
786 	 */
787 	int (*set_default_od_settings)(struct smu_context *smu);
788 
789 	/**
790 	 * @set_performance_level: Set a performance level.
791 	 */
792 	int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
793 
794 	/**
795 	 * @display_disable_memory_clock_switch: Enable/disable dynamic memory
796 	 *                                       clock switching.
797 	 *
798 	 * Disabling this feature forces memory clock speed to maximum.
799 	 * Enabling sets the minimum memory clock capable of driving the
800 	 * current display configuration.
801 	 */
802 	int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch);
803 
804 	/**
805 	 * @dump_pptable: Print the power play table to the system log.
806 	 */
807 	void (*dump_pptable)(struct smu_context *smu);
808 
809 	/**
810 	 * @get_power_limit: Get the device's power limits.
811 	 */
812 	int (*get_power_limit)(struct smu_context *smu,
813 			       uint32_t *current_power_limit,
814 			       uint32_t *default_power_limit,
815 			       uint32_t *max_power_limit);
816 
817 	/**
818 	 * @get_ppt_limit: Get the device's ppt limits.
819 	 */
820 	int (*get_ppt_limit)(struct smu_context *smu, uint32_t *ppt_limit,
821 			enum smu_ppt_limit_type limit_type, enum smu_ppt_limit_level limit_level);
822 
823 	/**
824 	 * @set_df_cstate: Set data fabric cstate.
825 	 */
826 	int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
827 
828 	/**
829 	 * @allow_xgmi_power_down: Enable/disable external global memory
830 	 *                         interconnect power down.
831 	 */
832 	int (*allow_xgmi_power_down)(struct smu_context *smu, bool en);
833 
834 	/**
835 	 * @update_pcie_parameters: Update and upload the system's PCIe
836 	 *                          capabilites to the SMU.
837 	 * &pcie_gen_cap: Maximum allowed PCIe generation.
838 	 * &pcie_width_cap: Maximum allowed PCIe width.
839 	 */
840 	int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap);
841 
842 	/**
843 	 * @i2c_init: Initialize i2c.
844 	 *
845 	 * The i2c bus is used internally by the SMU voltage regulators and
846 	 * other devices. The i2c's EEPROM also stores bad page tables on boards
847 	 * with ECC.
848 	 */
849 	int (*i2c_init)(struct smu_context *smu);
850 
851 	/**
852 	 * @i2c_fini: Tear down i2c.
853 	 */
854 	void (*i2c_fini)(struct smu_context *smu);
855 
856 	/**
857 	 * @get_unique_id: Get the GPU's unique id. Used for asset tracking.
858 	 */
859 	void (*get_unique_id)(struct smu_context *smu);
860 
861 	/**
862 	 * @get_dpm_clock_table: Get a copy of the DPM clock table.
863 	 *
864 	 * Used by display component in bandwidth and watermark calculations.
865 	 */
866 	int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table);
867 
868 	/**
869 	 * @init_microcode: Request the SMU's firmware from the kernel.
870 	 */
871 	int (*init_microcode)(struct smu_context *smu);
872 
873 	/**
874 	 * @load_microcode: Load firmware onto the SMU.
875 	 */
876 	int (*load_microcode)(struct smu_context *smu);
877 
878 	/**
879 	 * @fini_microcode: Release the SMU's firmware.
880 	 */
881 	void (*fini_microcode)(struct smu_context *smu);
882 
883 	/**
884 	 * @init_smc_tables: Initialize the SMU tables.
885 	 */
886 	int (*init_smc_tables)(struct smu_context *smu);
887 
888 	/**
889 	 * @fini_smc_tables: Release the SMU tables.
890 	 */
891 	int (*fini_smc_tables)(struct smu_context *smu);
892 
893 	/**
894 	 * @init_power: Initialize the power gate table context.
895 	 */
896 	int (*init_power)(struct smu_context *smu);
897 
898 	/**
899 	 * @fini_power: Release the power gate table context.
900 	 */
901 	int (*fini_power)(struct smu_context *smu);
902 
903 	/**
904 	 * @check_fw_status: Check the SMU's firmware status.
905 	 *
906 	 * Return: Zero if check passes, negative errno on failure.
907 	 */
908 	int (*check_fw_status)(struct smu_context *smu);
909 
910 	/**
911 	 * @set_mp1_state: put SMU into a correct state for comming
912 	 *                 resume from runpm or gpu reset.
913 	 */
914 	int (*set_mp1_state)(struct smu_context *smu,
915 			     enum pp_mp1_state mp1_state);
916 
917 	/**
918 	 * @setup_pptable: Initialize the power play table and populate it with
919 	 *                 default values.
920 	 */
921 	int (*setup_pptable)(struct smu_context *smu);
922 
923 	/**
924 	 * @get_vbios_bootup_values: Get default boot values from the VBIOS.
925 	 */
926 	int (*get_vbios_bootup_values)(struct smu_context *smu);
927 
928 	/**
929 	 * @check_fw_version: Print driver and SMU interface versions to the
930 	 *                    system log.
931 	 *
932 	 * Interface mismatch is not a critical failure.
933 	 */
934 	int (*check_fw_version)(struct smu_context *smu);
935 
936 	/**
937 	 * @powergate_sdma: Power up/down system direct memory access.
938 	 */
939 	int (*powergate_sdma)(struct smu_context *smu, bool gate);
940 
941 	/**
942 	 * @set_gfx_cgpg: Enable/disable graphics engine course grain power
943 	 *                gating.
944 	 */
945 	int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);
946 
947 	/**
948 	 * @write_pptable: Write the power play table to the SMU.
949 	 */
950 	int (*write_pptable)(struct smu_context *smu);
951 
952 	/**
953 	 * @set_driver_table_location: Send the location of the driver table to
954 	 *                             the SMU.
955 	 */
956 	int (*set_driver_table_location)(struct smu_context *smu);
957 
958 	/**
959 	 * @set_tool_table_location: Send the location of the tool table to the
960 	 *                           SMU.
961 	 */
962 	int (*set_tool_table_location)(struct smu_context *smu);
963 
964 	/**
965 	 * @notify_memory_pool_location: Send the location of the memory pool to
966 	 *                               the SMU.
967 	 */
968 	int (*notify_memory_pool_location)(struct smu_context *smu);
969 
970 	/**
971 	 * @system_features_control: Enable/disable all SMU features.
972 	 */
973 	int (*system_features_control)(struct smu_context *smu, bool en);
974 
975 	/**
976 	 * @send_smc_msg_with_param: Send a message with a parameter to the SMU.
977 	 * &msg: Type of message.
978 	 * &param: Message parameter.
979 	 * &read_arg: SMU response (optional).
980 	 */
981 	int (*send_smc_msg_with_param)(struct smu_context *smu,
982 				       enum smu_message_type msg, uint32_t param, uint32_t *read_arg);
983 
984 	/**
985 	 * @send_smc_msg: Send a message to the SMU.
986 	 * &msg: Type of message.
987 	 * &read_arg: SMU response (optional).
988 	 */
989 	int (*send_smc_msg)(struct smu_context *smu,
990 			    enum smu_message_type msg,
991 			    uint32_t *read_arg);
992 
993 	/**
994 	 * @init_display_count: Notify the SMU of the number of display
995 	 *                      components in current display configuration.
996 	 */
997 	int (*init_display_count)(struct smu_context *smu, uint32_t count);
998 
999 	/**
1000 	 * @set_allowed_mask: Notify the SMU of the features currently allowed
1001 	 *                    by the driver.
1002 	 */
1003 	int (*set_allowed_mask)(struct smu_context *smu);
1004 
1005 	/**
1006 	 * @get_enabled_mask: Get a mask of features that are currently enabled
1007 	 *                    on the SMU.
1008 	 * &feature_mask: Enabled feature mask.
1009 	 */
1010 	int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask);
1011 
1012 	/**
1013 	 * @feature_is_enabled: Test if a feature is enabled.
1014 	 *
1015 	 * Return: One if enabled, zero if disabled.
1016 	 */
1017 	int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask);
1018 
1019 	/**
1020 	 * @disable_all_features_with_exception: Disable all features with
1021 	 *                                       exception to those in &mask.
1022 	 */
1023 	int (*disable_all_features_with_exception)(struct smu_context *smu,
1024 						   enum smu_feature_mask mask);
1025 
1026 	/**
1027 	 * @notify_display_change: Enable fast memory clock switching.
1028 	 *
1029 	 * Allows for fine grained memory clock switching but has more stringent
1030 	 * timing requirements.
1031 	 */
1032 	int (*notify_display_change)(struct smu_context *smu);
1033 
1034 	/**
1035 	 * @set_power_limit: Set power limit in watts.
1036 	 */
1037 	int (*set_power_limit)(struct smu_context *smu,
1038 			       enum smu_ppt_limit_type limit_type,
1039 			       uint32_t limit);
1040 
1041 	/**
1042 	 * @init_max_sustainable_clocks: Populate max sustainable clock speed
1043 	 *                               table with values from the SMU.
1044 	 */
1045 	int (*init_max_sustainable_clocks)(struct smu_context *smu);
1046 
1047 	/**
1048 	 * @enable_thermal_alert: Enable thermal alert interrupts.
1049 	 */
1050 	int (*enable_thermal_alert)(struct smu_context *smu);
1051 
1052 	/**
1053 	 * @disable_thermal_alert: Disable thermal alert interrupts.
1054 	 */
1055 	int (*disable_thermal_alert)(struct smu_context *smu);
1056 
1057 	/**
1058 	 * @set_min_dcef_deep_sleep: Set a minimum display fabric deep sleep
1059 	 *                           clock speed in MHz.
1060 	 */
1061 	int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk);
1062 
1063 	/**
1064 	 * @display_clock_voltage_request: Set a hard minimum frequency
1065 	 * for a clock domain.
1066 	 */
1067 	int (*display_clock_voltage_request)(struct smu_context *smu, struct
1068 					     pp_display_clock_request
1069 					     *clock_req);
1070 
1071 	/**
1072 	 * @get_fan_control_mode: Get the current fan control mode.
1073 	 */
1074 	uint32_t (*get_fan_control_mode)(struct smu_context *smu);
1075 
1076 	/**
1077 	 * @set_fan_control_mode: Set the fan control mode.
1078 	 */
1079 	int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
1080 
1081 	/**
1082 	 * @set_fan_speed_pwm: Set a static fan speed in PWM.
1083 	 */
1084 	int (*set_fan_speed_pwm)(struct smu_context *smu, uint32_t speed);
1085 
1086 	/**
1087 	 * @set_fan_speed_rpm: Set a static fan speed in rpm.
1088 	 */
1089 	int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
1090 
1091 	/**
1092 	 * @set_xgmi_pstate: Set inter-chip global memory interconnect pstate.
1093 	 * &pstate: Pstate to set. D0 if Nonzero, D3 otherwise.
1094 	 */
1095 	int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate);
1096 
1097 	/**
1098 	 * @gfx_off_control: Enable/disable graphics engine poweroff.
1099 	 */
1100 	int (*gfx_off_control)(struct smu_context *smu, bool enable);
1101 
1102 
1103 	/**
1104 	 * @get_gfx_off_status: Get graphics engine poweroff status.
1105 	 *
1106 	 * Return:
1107 	 * 0 - GFXOFF(default).
1108 	 * 1 - Transition out of GFX State.
1109 	 * 2 - Not in GFXOFF.
1110 	 * 3 - Transition into GFXOFF.
1111 	 */
1112 	uint32_t (*get_gfx_off_status)(struct smu_context *smu);
1113 
1114 	/**
1115 	 * @register_irq_handler: Register interupt request handlers.
1116 	 */
1117 	int (*register_irq_handler)(struct smu_context *smu);
1118 
1119 	/**
1120 	 * @set_azalia_d3_pme: Wake the audio decode engine from d3 sleep.
1121 	 */
1122 	int (*set_azalia_d3_pme)(struct smu_context *smu);
1123 
1124 	/**
1125 	 * @get_max_sustainable_clocks_by_dc: Get a copy of the max sustainable
1126 	 *                                    clock speeds table.
1127 	 *
1128 	 * Provides a way for the display component (DC) to get the max
1129 	 * sustainable clocks from the SMU.
1130 	 */
1131 	int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks);
1132 
1133 	/**
1134 	 * @baco_is_support: Check if GPU supports BACO (Bus Active, Chip Off).
1135 	 */
1136 	bool (*baco_is_support)(struct smu_context *smu);
1137 
1138 	/**
1139 	 * @baco_get_state: Get the current BACO state.
1140 	 *
1141 	 * Return: Current BACO state.
1142 	 */
1143 	enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
1144 
1145 	/**
1146 	 * @baco_set_state: Enter/exit BACO.
1147 	 */
1148 	int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);
1149 
1150 	/**
1151 	 * @baco_enter: Enter BACO.
1152 	 */
1153 	int (*baco_enter)(struct smu_context *smu);
1154 
1155 	/**
1156 	 * @baco_exit: Exit Baco.
1157 	 */
1158 	int (*baco_exit)(struct smu_context *smu);
1159 
1160 	/**
1161 	 * @mode1_reset_is_support: Check if GPU supports mode1 reset.
1162 	 */
1163 	bool (*mode1_reset_is_support)(struct smu_context *smu);
1164 	/**
1165 	 * @mode2_reset_is_support: Check if GPU supports mode2 reset.
1166 	 */
1167 	bool (*mode2_reset_is_support)(struct smu_context *smu);
1168 
1169 	/**
1170 	 * @mode1_reset: Perform mode1 reset.
1171 	 *
1172 	 * Complete GPU reset.
1173 	 */
1174 	int (*mode1_reset)(struct smu_context *smu);
1175 
1176 	/**
1177 	 * @mode2_reset: Perform mode2 reset.
1178 	 *
1179 	 * Mode2 reset generally does not reset as many IPs as mode1 reset. The
1180 	 * IPs reset varies by asic.
1181 	 */
1182 	int (*mode2_reset)(struct smu_context *smu);
1183 
1184 	/**
1185 	 * @get_dpm_ultimate_freq: Get the hard frequency range of a clock
1186 	 *                         domain in MHz.
1187 	 */
1188 	int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
1189 
1190 	/**
1191 	 * @set_soft_freq_limited_range: Set the soft frequency range of a clock
1192 	 *                               domain in MHz.
1193 	 */
1194 	int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);
1195 
1196 	/**
1197 	 * @set_power_source: Notify the SMU of the current power source.
1198 	 */
1199 	int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src);
1200 
1201 	/**
1202 	 * @log_thermal_throttling_event: Print a thermal throttling warning to
1203 	 *                                the system's log.
1204 	 */
1205 	void (*log_thermal_throttling_event)(struct smu_context *smu);
1206 
1207 	/**
1208 	 * @get_pp_feature_mask: Print a human readable table of enabled
1209 	 *                       features to buffer.
1210 	 */
1211 	size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf);
1212 
1213 	/**
1214 	 * @set_pp_feature_mask: Request the SMU enable/disable features to
1215 	 *                       match those enabled in &new_mask.
1216 	 */
1217 	int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask);
1218 
1219 	/**
1220 	 * @get_gpu_metrics: Get a copy of the GPU metrics table from the SMU.
1221 	 *
1222 	 * Return: Size of &table
1223 	 */
1224 	ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table);
1225 
1226 	/**
1227 	 * @enable_mgpu_fan_boost: Enable multi-GPU fan boost.
1228 	 */
1229 	int (*enable_mgpu_fan_boost)(struct smu_context *smu);
1230 
1231 	/**
1232 	 * @gfx_ulv_control: Enable/disable ultra low voltage.
1233 	 */
1234 	int (*gfx_ulv_control)(struct smu_context *smu, bool enablement);
1235 
1236 	/**
1237 	 * @deep_sleep_control: Enable/disable deep sleep.
1238 	 */
1239 	int (*deep_sleep_control)(struct smu_context *smu, bool enablement);
1240 
1241 	/**
1242 	 * @get_fan_parameters: Get fan parameters.
1243 	 *
1244 	 * Get maximum fan speed from the power play table.
1245 	 */
1246 	int (*get_fan_parameters)(struct smu_context *smu);
1247 
1248 	/**
1249 	 * @post_init: Helper function for asic specific workarounds.
1250 	 */
1251 	int (*post_init)(struct smu_context *smu);
1252 
1253 	/**
1254 	 * @interrupt_work: Work task scheduled from SMU interrupt handler.
1255 	 */
1256 	void (*interrupt_work)(struct smu_context *smu);
1257 
1258 	/**
1259 	 * @gpo_control: Enable/disable graphics power optimization if supported.
1260 	 */
1261 	int (*gpo_control)(struct smu_context *smu, bool enablement);
1262 
1263 	/**
1264 	 * @gfx_state_change_set: Send the current graphics state to the SMU.
1265 	 */
1266 	int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state);
1267 
1268 	/**
1269 	 * @set_fine_grain_gfx_freq_parameters: Set fine grain graphics clock
1270 	 *                                      parameters to defaults.
1271 	 */
1272 	int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu);
1273 
1274 	/**
1275 	 * @smu_handle_passthrough_sbr:  Send message to SMU about special handling for SBR.
1276 	 */
1277 	int (*smu_handle_passthrough_sbr)(struct smu_context *smu, bool enable);
1278 
1279 	/**
1280 	 * @wait_for_event:  Wait for events from SMU.
1281 	 */
1282 	int (*wait_for_event)(struct smu_context *smu,
1283 			      enum smu_event_type event, uint64_t event_arg);
1284 
1285 	/**
1286 	 * @sned_hbm_bad_pages_num:  message SMU to update bad page number
1287 	 *										of SMUBUS table.
1288 	 */
1289 	int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size);
1290 
1291 	/**
1292 	 * @get_ecc_table:  message SMU to get ECC INFO table.
1293 	 */
1294 	ssize_t (*get_ecc_info)(struct smu_context *smu, void *table);
1295 
1296 
1297 	/**
1298 	 * @stb_collect_info: Collects Smart Trace Buffers data.
1299 	 */
1300 	int (*stb_collect_info)(struct smu_context *smu, void *buf, uint32_t size);
1301 
1302 	/**
1303 	 * @get_default_config_table_settings: Get the ASIC default DriverSmuConfig table settings.
1304 	 */
1305 	int (*get_default_config_table_settings)(struct smu_context *smu, struct config_table_setting *table);
1306 
1307 	/**
1308 	 * @set_config_table: Apply the input DriverSmuConfig table settings.
1309 	 */
1310 	int (*set_config_table)(struct smu_context *smu, struct config_table_setting *table);
1311 
1312 	/**
1313 	 * @sned_hbm_bad_channel_flag:  message SMU to update bad channel info
1314 	 *										of SMUBUS table.
1315 	 */
1316 	int (*send_hbm_bad_channel_flag)(struct smu_context *smu, uint32_t size);
1317 
1318 	/**
1319 	 * @init_pptable_microcode: Prepare the pptable microcode to upload via PSP
1320 	 */
1321 	int (*init_pptable_microcode)(struct smu_context *smu);
1322 };
1323 
1324 typedef enum {
1325 	METRICS_CURR_GFXCLK,
1326 	METRICS_CURR_SOCCLK,
1327 	METRICS_CURR_UCLK,
1328 	METRICS_CURR_VCLK,
1329 	METRICS_CURR_VCLK1,
1330 	METRICS_CURR_DCLK,
1331 	METRICS_CURR_DCLK1,
1332 	METRICS_CURR_FCLK,
1333 	METRICS_CURR_DCEFCLK,
1334 	METRICS_AVERAGE_CPUCLK,
1335 	METRICS_AVERAGE_GFXCLK,
1336 	METRICS_AVERAGE_SOCCLK,
1337 	METRICS_AVERAGE_FCLK,
1338 	METRICS_AVERAGE_UCLK,
1339 	METRICS_AVERAGE_VCLK,
1340 	METRICS_AVERAGE_DCLK,
1341 	METRICS_AVERAGE_VCLK1,
1342 	METRICS_AVERAGE_DCLK1,
1343 	METRICS_AVERAGE_GFXACTIVITY,
1344 	METRICS_AVERAGE_MEMACTIVITY,
1345 	METRICS_AVERAGE_VCNACTIVITY,
1346 	METRICS_AVERAGE_SOCKETPOWER,
1347 	METRICS_TEMPERATURE_EDGE,
1348 	METRICS_TEMPERATURE_HOTSPOT,
1349 	METRICS_TEMPERATURE_MEM,
1350 	METRICS_TEMPERATURE_VRGFX,
1351 	METRICS_TEMPERATURE_VRSOC,
1352 	METRICS_TEMPERATURE_VRMEM,
1353 	METRICS_THROTTLER_STATUS,
1354 	METRICS_CURR_FANSPEED,
1355 	METRICS_VOLTAGE_VDDSOC,
1356 	METRICS_VOLTAGE_VDDGFX,
1357 	METRICS_SS_APU_SHARE,
1358 	METRICS_SS_DGPU_SHARE,
1359 	METRICS_UNIQUE_ID_UPPER32,
1360 	METRICS_UNIQUE_ID_LOWER32,
1361 	METRICS_PCIE_RATE,
1362 	METRICS_PCIE_WIDTH,
1363 	METRICS_CURR_FANPWM,
1364 } MetricsMember_t;
1365 
1366 enum smu_cmn2asic_mapping_type {
1367 	CMN2ASIC_MAPPING_MSG,
1368 	CMN2ASIC_MAPPING_CLK,
1369 	CMN2ASIC_MAPPING_FEATURE,
1370 	CMN2ASIC_MAPPING_TABLE,
1371 	CMN2ASIC_MAPPING_PWR,
1372 	CMN2ASIC_MAPPING_WORKLOAD,
1373 };
1374 
1375 #define MSG_MAP(msg, index, valid_in_vf) \
1376 	[SMU_MSG_##msg] = {1, (index), (valid_in_vf)}
1377 
1378 #define CLK_MAP(clk, index) \
1379 	[SMU_##clk] = {1, (index)}
1380 
1381 #define FEA_MAP(fea) \
1382 	[SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT}
1383 
1384 #define FEA_MAP_REVERSE(fea) \
1385 	[SMU_FEATURE_DPM_##fea##_BIT] = {1, FEATURE_##fea##_DPM_BIT}
1386 
1387 #define FEA_MAP_HALF_REVERSE(fea) \
1388 	[SMU_FEATURE_DPM_##fea##CLK_BIT] = {1, FEATURE_##fea##_DPM_BIT}
1389 
1390 #define TAB_MAP(tab) \
1391 	[SMU_TABLE_##tab] = {1, TABLE_##tab}
1392 
1393 #define TAB_MAP_VALID(tab) \
1394 	[SMU_TABLE_##tab] = {1, TABLE_##tab}
1395 
1396 #define TAB_MAP_INVALID(tab) \
1397 	[SMU_TABLE_##tab] = {0, TABLE_##tab}
1398 
1399 #define PWR_MAP(tab) \
1400 	[SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab}
1401 
1402 #define WORKLOAD_MAP(profile, workload) \
1403 	[profile] = {1, (workload)}
1404 
1405 /**
1406  * smu_memcpy_trailing - Copy the end of one structure into the middle of another
1407  *
1408  * @dst: Pointer to destination struct
1409  * @first_dst_member: The member name in @dst where the overwrite begins
1410  * @last_dst_member: The member name in @dst where the overwrite ends after
1411  * @src: Pointer to the source struct
1412  * @first_src_member: The member name in @src where the copy begins
1413  *
1414  */
1415 #define smu_memcpy_trailing(dst, first_dst_member, last_dst_member,	   \
1416 			    src, first_src_member)			   \
1417 ({									   \
1418 	size_t __src_offset = offsetof(typeof(*(src)), first_src_member);  \
1419 	size_t __src_size = sizeof(*(src)) - __src_offset;		   \
1420 	size_t __dst_offset = offsetof(typeof(*(dst)), first_dst_member);  \
1421 	size_t __dst_size = offsetofend(typeof(*(dst)), last_dst_member) - \
1422 			    __dst_offset;				   \
1423 	BUILD_BUG_ON(__src_size != __dst_size);				   \
1424 	__builtin_memcpy((u8 *)(dst) + __dst_offset,			   \
1425 			 (u8 *)(src) + __src_offset,			   \
1426 			 __dst_size);					   \
1427 })
1428 
1429 #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4)
1430 int smu_get_power_limit(void *handle,
1431 			uint32_t *limit,
1432 			enum pp_power_limit_level pp_limit_level,
1433 			enum pp_power_type pp_power_type);
1434 
1435 bool smu_mode1_reset_is_support(struct smu_context *smu);
1436 bool smu_mode2_reset_is_support(struct smu_context *smu);
1437 int smu_mode1_reset(struct smu_context *smu);
1438 
1439 extern const struct amd_ip_funcs smu_ip_funcs;
1440 
1441 bool is_support_sw_smu(struct amdgpu_device *adev);
1442 bool is_support_cclk_dpm(struct amdgpu_device *adev);
1443 int smu_write_watermarks_table(struct smu_context *smu);
1444 
1445 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
1446 			   uint32_t *min, uint32_t *max);
1447 
1448 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
1449 			    uint32_t min, uint32_t max);
1450 
1451 int smu_set_gfx_power_up_by_imu(struct smu_context *smu);
1452 
1453 int smu_set_ac_dc(struct smu_context *smu);
1454 
1455 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en);
1456 
1457 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value);
1458 
1459 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable);
1460 
1461 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1462 		       uint64_t event_arg);
1463 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc);
1464 int smu_stb_collect_info(struct smu_context *smu, void *buff, uint32_t size);
1465 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev);
1466 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size);
1467 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size);
1468 #endif
1469 #endif
1470