1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "aldebaran_ppt.h" 38 #include "yellow_carp_ppt.h" 39 #include "cyan_skillfish_ppt.h" 40 #include "smu_v13_0_0_ppt.h" 41 #include "smu_v13_0_5_ppt.h" 42 #include "amd_pcie.h" 43 44 /* 45 * DO NOT use these for err/warn/info/debug messages. 46 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 47 * They are more MGPU friendly. 48 */ 49 #undef pr_err 50 #undef pr_warn 51 #undef pr_info 52 #undef pr_debug 53 54 static const struct amd_pm_funcs swsmu_pm_funcs; 55 static int smu_force_smuclk_levels(struct smu_context *smu, 56 enum smu_clk_type clk_type, 57 uint32_t mask); 58 static int smu_handle_task(struct smu_context *smu, 59 enum amd_dpm_forced_level level, 60 enum amd_pp_task task_id); 61 static int smu_reset(struct smu_context *smu); 62 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 63 static int smu_set_fan_control_mode(void *handle, u32 value); 64 static int smu_set_power_limit(void *handle, uint32_t limit); 65 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 66 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 67 68 static int smu_sys_get_pp_feature_mask(void *handle, 69 char *buf) 70 { 71 struct smu_context *smu = handle; 72 73 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 74 return -EOPNOTSUPP; 75 76 return smu_get_pp_feature_mask(smu, buf); 77 } 78 79 static int smu_sys_set_pp_feature_mask(void *handle, 80 uint64_t new_mask) 81 { 82 struct smu_context *smu = handle; 83 84 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 85 return -EOPNOTSUPP; 86 87 return smu_set_pp_feature_mask(smu, new_mask); 88 } 89 90 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 91 { 92 if (!smu->ppt_funcs->get_gfx_off_status) 93 return -EINVAL; 94 95 *value = smu_get_gfx_off_status(smu); 96 97 return 0; 98 } 99 100 int smu_set_soft_freq_range(struct smu_context *smu, 101 enum smu_clk_type clk_type, 102 uint32_t min, 103 uint32_t max) 104 { 105 int ret = 0; 106 107 if (smu->ppt_funcs->set_soft_freq_limited_range) 108 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 109 clk_type, 110 min, 111 max); 112 113 return ret; 114 } 115 116 int smu_get_dpm_freq_range(struct smu_context *smu, 117 enum smu_clk_type clk_type, 118 uint32_t *min, 119 uint32_t *max) 120 { 121 int ret = -ENOTSUPP; 122 123 if (!min && !max) 124 return -EINVAL; 125 126 if (smu->ppt_funcs->get_dpm_ultimate_freq) 127 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 128 clk_type, 129 min, 130 max); 131 132 return ret; 133 } 134 135 static u32 smu_get_mclk(void *handle, bool low) 136 { 137 struct smu_context *smu = handle; 138 uint32_t clk_freq; 139 int ret = 0; 140 141 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 142 low ? &clk_freq : NULL, 143 !low ? &clk_freq : NULL); 144 if (ret) 145 return 0; 146 return clk_freq * 100; 147 } 148 149 static u32 smu_get_sclk(void *handle, bool low) 150 { 151 struct smu_context *smu = handle; 152 uint32_t clk_freq; 153 int ret = 0; 154 155 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 156 low ? &clk_freq : NULL, 157 !low ? &clk_freq : NULL); 158 if (ret) 159 return 0; 160 return clk_freq * 100; 161 } 162 163 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 164 bool enable) 165 { 166 struct smu_power_context *smu_power = &smu->smu_power; 167 struct smu_power_gate *power_gate = &smu_power->power_gate; 168 int ret = 0; 169 170 if (!smu->ppt_funcs->dpm_set_vcn_enable) 171 return 0; 172 173 if (atomic_read(&power_gate->vcn_gated) ^ enable) 174 return 0; 175 176 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 177 if (!ret) 178 atomic_set(&power_gate->vcn_gated, !enable); 179 180 return ret; 181 } 182 183 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 184 bool enable) 185 { 186 struct smu_power_context *smu_power = &smu->smu_power; 187 struct smu_power_gate *power_gate = &smu_power->power_gate; 188 int ret = 0; 189 190 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 191 return 0; 192 193 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 194 return 0; 195 196 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 197 if (!ret) 198 atomic_set(&power_gate->jpeg_gated, !enable); 199 200 return ret; 201 } 202 203 /** 204 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 205 * 206 * @handle: smu_context pointer 207 * @block_type: the IP block to power gate/ungate 208 * @gate: to power gate if true, ungate otherwise 209 * 210 * This API uses no smu->mutex lock protection due to: 211 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 212 * This is guarded to be race condition free by the caller. 213 * 2. Or get called on user setting request of power_dpm_force_performance_level. 214 * Under this case, the smu->mutex lock protection is already enforced on 215 * the parent API smu_force_performance_level of the call path. 216 */ 217 static int smu_dpm_set_power_gate(void *handle, 218 uint32_t block_type, 219 bool gate) 220 { 221 struct smu_context *smu = handle; 222 int ret = 0; 223 224 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 225 dev_WARN(smu->adev->dev, 226 "SMU uninitialized but power %s requested for %u!\n", 227 gate ? "gate" : "ungate", block_type); 228 return -EOPNOTSUPP; 229 } 230 231 switch (block_type) { 232 /* 233 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 234 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 235 */ 236 case AMD_IP_BLOCK_TYPE_UVD: 237 case AMD_IP_BLOCK_TYPE_VCN: 238 ret = smu_dpm_set_vcn_enable(smu, !gate); 239 if (ret) 240 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 241 gate ? "gate" : "ungate"); 242 break; 243 case AMD_IP_BLOCK_TYPE_GFX: 244 ret = smu_gfx_off_control(smu, gate); 245 if (ret) 246 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 247 gate ? "enable" : "disable"); 248 break; 249 case AMD_IP_BLOCK_TYPE_SDMA: 250 ret = smu_powergate_sdma(smu, gate); 251 if (ret) 252 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 253 gate ? "gate" : "ungate"); 254 break; 255 case AMD_IP_BLOCK_TYPE_JPEG: 256 ret = smu_dpm_set_jpeg_enable(smu, !gate); 257 if (ret) 258 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 259 gate ? "gate" : "ungate"); 260 break; 261 default: 262 dev_err(smu->adev->dev, "Unsupported block type!\n"); 263 return -EINVAL; 264 } 265 266 return ret; 267 } 268 269 /** 270 * smu_set_user_clk_dependencies - set user profile clock dependencies 271 * 272 * @smu: smu_context pointer 273 * @clk: enum smu_clk_type type 274 * 275 * Enable/Disable the clock dependency for the @clk type. 276 */ 277 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 278 { 279 if (smu->adev->in_suspend) 280 return; 281 282 if (clk == SMU_MCLK) { 283 smu->user_dpm_profile.clk_dependency = 0; 284 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 285 } else if (clk == SMU_FCLK) { 286 /* MCLK takes precedence over FCLK */ 287 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 288 return; 289 290 smu->user_dpm_profile.clk_dependency = 0; 291 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 292 } else if (clk == SMU_SOCCLK) { 293 /* MCLK takes precedence over SOCCLK */ 294 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 295 return; 296 297 smu->user_dpm_profile.clk_dependency = 0; 298 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 299 } else 300 /* Add clk dependencies here, if any */ 301 return; 302 } 303 304 /** 305 * smu_restore_dpm_user_profile - reinstate user dpm profile 306 * 307 * @smu: smu_context pointer 308 * 309 * Restore the saved user power configurations include power limit, 310 * clock frequencies, fan control mode and fan speed. 311 */ 312 static void smu_restore_dpm_user_profile(struct smu_context *smu) 313 { 314 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 315 int ret = 0; 316 317 if (!smu->adev->in_suspend) 318 return; 319 320 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 321 return; 322 323 /* Enable restore flag */ 324 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 325 326 /* set the user dpm power limit */ 327 if (smu->user_dpm_profile.power_limit) { 328 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 329 if (ret) 330 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 331 } 332 333 /* set the user dpm clock configurations */ 334 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 335 enum smu_clk_type clk_type; 336 337 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 338 /* 339 * Iterate over smu clk type and force the saved user clk 340 * configs, skip if clock dependency is enabled 341 */ 342 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 343 smu->user_dpm_profile.clk_mask[clk_type]) { 344 ret = smu_force_smuclk_levels(smu, clk_type, 345 smu->user_dpm_profile.clk_mask[clk_type]); 346 if (ret) 347 dev_err(smu->adev->dev, 348 "Failed to set clock type = %d\n", clk_type); 349 } 350 } 351 } 352 353 /* set the user dpm fan configurations */ 354 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 355 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 356 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 357 if (ret != -EOPNOTSUPP) { 358 smu->user_dpm_profile.fan_speed_pwm = 0; 359 smu->user_dpm_profile.fan_speed_rpm = 0; 360 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 361 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 362 } 363 364 if (smu->user_dpm_profile.fan_speed_pwm) { 365 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 366 if (ret != -EOPNOTSUPP) 367 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 368 } 369 370 if (smu->user_dpm_profile.fan_speed_rpm) { 371 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 372 if (ret != -EOPNOTSUPP) 373 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 374 } 375 } 376 377 /* Restore user customized OD settings */ 378 if (smu->user_dpm_profile.user_od) { 379 if (smu->ppt_funcs->restore_user_od_settings) { 380 ret = smu->ppt_funcs->restore_user_od_settings(smu); 381 if (ret) 382 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 383 } 384 } 385 386 /* Disable restore flag */ 387 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 388 } 389 390 static int smu_get_power_num_states(void *handle, 391 struct pp_states_info *state_info) 392 { 393 if (!state_info) 394 return -EINVAL; 395 396 /* not support power state */ 397 memset(state_info, 0, sizeof(struct pp_states_info)); 398 state_info->nums = 1; 399 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 400 401 return 0; 402 } 403 404 bool is_support_sw_smu(struct amdgpu_device *adev) 405 { 406 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 407 if (adev->asic_type == CHIP_VEGA20) 408 return false; 409 410 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0)) 411 return true; 412 413 return false; 414 } 415 416 bool is_support_cclk_dpm(struct amdgpu_device *adev) 417 { 418 struct smu_context *smu = adev->powerplay.pp_handle; 419 420 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 421 return false; 422 423 return true; 424 } 425 426 427 static int smu_sys_get_pp_table(void *handle, 428 char **table) 429 { 430 struct smu_context *smu = handle; 431 struct smu_table_context *smu_table = &smu->smu_table; 432 433 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 434 return -EOPNOTSUPP; 435 436 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 437 return -EINVAL; 438 439 if (smu_table->hardcode_pptable) 440 *table = smu_table->hardcode_pptable; 441 else 442 *table = smu_table->power_play_table; 443 444 return smu_table->power_play_table_size; 445 } 446 447 static int smu_sys_set_pp_table(void *handle, 448 const char *buf, 449 size_t size) 450 { 451 struct smu_context *smu = handle; 452 struct smu_table_context *smu_table = &smu->smu_table; 453 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 454 int ret = 0; 455 456 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 457 return -EOPNOTSUPP; 458 459 if (header->usStructureSize != size) { 460 dev_err(smu->adev->dev, "pp table size not matched !\n"); 461 return -EIO; 462 } 463 464 if (!smu_table->hardcode_pptable) { 465 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 466 if (!smu_table->hardcode_pptable) 467 return -ENOMEM; 468 } 469 470 memcpy(smu_table->hardcode_pptable, buf, size); 471 smu_table->power_play_table = smu_table->hardcode_pptable; 472 smu_table->power_play_table_size = size; 473 474 /* 475 * Special hw_fini action(for Navi1x, the DPMs disablement will be 476 * skipped) may be needed for custom pptable uploading. 477 */ 478 smu->uploading_custom_pp_table = true; 479 480 ret = smu_reset(smu); 481 if (ret) 482 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 483 484 smu->uploading_custom_pp_table = false; 485 486 return ret; 487 } 488 489 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 490 { 491 struct smu_feature *feature = &smu->smu_feature; 492 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 493 int ret = 0; 494 495 /* 496 * With SCPM enabled, the allowed featuremasks setting(via 497 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 498 * That means there is no way to let PMFW knows the settings below. 499 * Thus, we just assume all the features are allowed under 500 * such scenario. 501 */ 502 if (smu->adev->scpm_enabled) { 503 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 504 return 0; 505 } 506 507 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 508 509 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 510 SMU_FEATURE_MAX/32); 511 if (ret) 512 return ret; 513 514 bitmap_or(feature->allowed, feature->allowed, 515 (unsigned long *)allowed_feature_mask, 516 feature->feature_num); 517 518 return ret; 519 } 520 521 static int smu_set_funcs(struct amdgpu_device *adev) 522 { 523 struct smu_context *smu = adev->powerplay.pp_handle; 524 525 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 526 smu->od_enabled = true; 527 528 switch (adev->ip_versions[MP1_HWIP][0]) { 529 case IP_VERSION(11, 0, 0): 530 case IP_VERSION(11, 0, 5): 531 case IP_VERSION(11, 0, 9): 532 navi10_set_ppt_funcs(smu); 533 break; 534 case IP_VERSION(11, 0, 7): 535 case IP_VERSION(11, 0, 11): 536 case IP_VERSION(11, 0, 12): 537 case IP_VERSION(11, 0, 13): 538 sienna_cichlid_set_ppt_funcs(smu); 539 break; 540 case IP_VERSION(12, 0, 0): 541 case IP_VERSION(12, 0, 1): 542 renoir_set_ppt_funcs(smu); 543 break; 544 case IP_VERSION(11, 5, 0): 545 vangogh_set_ppt_funcs(smu); 546 break; 547 case IP_VERSION(13, 0, 1): 548 case IP_VERSION(13, 0, 3): 549 case IP_VERSION(13, 0, 8): 550 yellow_carp_set_ppt_funcs(smu); 551 break; 552 case IP_VERSION(13, 0, 5): 553 smu_v13_0_5_set_ppt_funcs(smu); 554 break; 555 case IP_VERSION(11, 0, 8): 556 cyan_skillfish_set_ppt_funcs(smu); 557 break; 558 case IP_VERSION(11, 0, 2): 559 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 560 arcturus_set_ppt_funcs(smu); 561 /* OD is not supported on Arcturus */ 562 smu->od_enabled =false; 563 break; 564 case IP_VERSION(13, 0, 2): 565 aldebaran_set_ppt_funcs(smu); 566 /* Enable pp_od_clk_voltage node */ 567 smu->od_enabled = true; 568 break; 569 case IP_VERSION(13, 0, 0): 570 smu_v13_0_0_set_ppt_funcs(smu); 571 break; 572 default: 573 return -EINVAL; 574 } 575 576 return 0; 577 } 578 579 static int smu_early_init(void *handle) 580 { 581 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 582 struct smu_context *smu; 583 584 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 585 if (!smu) 586 return -ENOMEM; 587 588 smu->adev = adev; 589 smu->pm_enabled = !!amdgpu_dpm; 590 smu->is_apu = false; 591 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 592 smu->smu_baco.platform_support = false; 593 smu->user_dpm_profile.fan_mode = -1; 594 595 adev->powerplay.pp_handle = smu; 596 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 597 598 return smu_set_funcs(adev); 599 } 600 601 static int smu_set_default_dpm_table(struct smu_context *smu) 602 { 603 struct smu_power_context *smu_power = &smu->smu_power; 604 struct smu_power_gate *power_gate = &smu_power->power_gate; 605 int vcn_gate, jpeg_gate; 606 int ret = 0; 607 608 if (!smu->ppt_funcs->set_default_dpm_table) 609 return 0; 610 611 vcn_gate = atomic_read(&power_gate->vcn_gated); 612 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 613 614 ret = smu_dpm_set_vcn_enable(smu, true); 615 if (ret) 616 return ret; 617 618 ret = smu_dpm_set_jpeg_enable(smu, true); 619 if (ret) 620 goto err_out; 621 622 ret = smu->ppt_funcs->set_default_dpm_table(smu); 623 if (ret) 624 dev_err(smu->adev->dev, 625 "Failed to setup default dpm clock tables!\n"); 626 627 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 628 err_out: 629 smu_dpm_set_vcn_enable(smu, !vcn_gate); 630 return ret; 631 } 632 633 static int smu_apply_default_config_table_settings(struct smu_context *smu) 634 { 635 struct amdgpu_device *adev = smu->adev; 636 int ret = 0; 637 638 ret = smu_get_default_config_table_settings(smu, 639 &adev->pm.config_table); 640 if (ret) 641 return ret; 642 643 return smu_set_config_table(smu, &adev->pm.config_table); 644 } 645 646 static int smu_late_init(void *handle) 647 { 648 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 649 struct smu_context *smu = adev->powerplay.pp_handle; 650 int ret = 0; 651 652 smu_set_fine_grain_gfx_freq_parameters(smu); 653 654 if (!smu->pm_enabled) 655 return 0; 656 657 ret = smu_post_init(smu); 658 if (ret) { 659 dev_err(adev->dev, "Failed to post smu init!\n"); 660 return ret; 661 } 662 663 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || 664 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) 665 return 0; 666 667 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 668 ret = smu_set_default_od_settings(smu); 669 if (ret) { 670 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 671 return ret; 672 } 673 } 674 675 ret = smu_populate_umd_state_clk(smu); 676 if (ret) { 677 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 678 return ret; 679 } 680 681 ret = smu_get_asic_power_limits(smu, 682 &smu->current_power_limit, 683 &smu->default_power_limit, 684 &smu->max_power_limit); 685 if (ret) { 686 dev_err(adev->dev, "Failed to get asic power limits!\n"); 687 return ret; 688 } 689 690 if (!amdgpu_sriov_vf(adev)) 691 smu_get_unique_id(smu); 692 693 smu_get_fan_parameters(smu); 694 695 smu_handle_task(smu, 696 smu->smu_dpm.dpm_level, 697 AMD_PP_TASK_COMPLETE_INIT); 698 699 ret = smu_apply_default_config_table_settings(smu); 700 if (ret && (ret != -EOPNOTSUPP)) { 701 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 702 return ret; 703 } 704 705 smu_restore_dpm_user_profile(smu); 706 707 return 0; 708 } 709 710 static int smu_init_fb_allocations(struct smu_context *smu) 711 { 712 struct amdgpu_device *adev = smu->adev; 713 struct smu_table_context *smu_table = &smu->smu_table; 714 struct smu_table *tables = smu_table->tables; 715 struct smu_table *driver_table = &(smu_table->driver_table); 716 uint32_t max_table_size = 0; 717 int ret, i; 718 719 /* VRAM allocation for tool table */ 720 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 721 ret = amdgpu_bo_create_kernel(adev, 722 tables[SMU_TABLE_PMSTATUSLOG].size, 723 tables[SMU_TABLE_PMSTATUSLOG].align, 724 tables[SMU_TABLE_PMSTATUSLOG].domain, 725 &tables[SMU_TABLE_PMSTATUSLOG].bo, 726 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 727 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 728 if (ret) { 729 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 730 return ret; 731 } 732 } 733 734 /* VRAM allocation for driver table */ 735 for (i = 0; i < SMU_TABLE_COUNT; i++) { 736 if (tables[i].size == 0) 737 continue; 738 739 if (i == SMU_TABLE_PMSTATUSLOG) 740 continue; 741 742 if (max_table_size < tables[i].size) 743 max_table_size = tables[i].size; 744 } 745 746 driver_table->size = max_table_size; 747 driver_table->align = PAGE_SIZE; 748 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 749 750 ret = amdgpu_bo_create_kernel(adev, 751 driver_table->size, 752 driver_table->align, 753 driver_table->domain, 754 &driver_table->bo, 755 &driver_table->mc_address, 756 &driver_table->cpu_addr); 757 if (ret) { 758 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 759 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 760 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 761 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 762 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 763 } 764 765 return ret; 766 } 767 768 static int smu_fini_fb_allocations(struct smu_context *smu) 769 { 770 struct smu_table_context *smu_table = &smu->smu_table; 771 struct smu_table *tables = smu_table->tables; 772 struct smu_table *driver_table = &(smu_table->driver_table); 773 774 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 775 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 776 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 777 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 778 779 amdgpu_bo_free_kernel(&driver_table->bo, 780 &driver_table->mc_address, 781 &driver_table->cpu_addr); 782 783 return 0; 784 } 785 786 /** 787 * smu_alloc_memory_pool - allocate memory pool in the system memory 788 * 789 * @smu: amdgpu_device pointer 790 * 791 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 792 * and DramLogSetDramAddr can notify it changed. 793 * 794 * Returns 0 on success, error on failure. 795 */ 796 static int smu_alloc_memory_pool(struct smu_context *smu) 797 { 798 struct amdgpu_device *adev = smu->adev; 799 struct smu_table_context *smu_table = &smu->smu_table; 800 struct smu_table *memory_pool = &smu_table->memory_pool; 801 uint64_t pool_size = smu->pool_size; 802 int ret = 0; 803 804 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 805 return ret; 806 807 memory_pool->size = pool_size; 808 memory_pool->align = PAGE_SIZE; 809 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 810 811 switch (pool_size) { 812 case SMU_MEMORY_POOL_SIZE_256_MB: 813 case SMU_MEMORY_POOL_SIZE_512_MB: 814 case SMU_MEMORY_POOL_SIZE_1_GB: 815 case SMU_MEMORY_POOL_SIZE_2_GB: 816 ret = amdgpu_bo_create_kernel(adev, 817 memory_pool->size, 818 memory_pool->align, 819 memory_pool->domain, 820 &memory_pool->bo, 821 &memory_pool->mc_address, 822 &memory_pool->cpu_addr); 823 if (ret) 824 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 825 break; 826 default: 827 break; 828 } 829 830 return ret; 831 } 832 833 static int smu_free_memory_pool(struct smu_context *smu) 834 { 835 struct smu_table_context *smu_table = &smu->smu_table; 836 struct smu_table *memory_pool = &smu_table->memory_pool; 837 838 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 839 return 0; 840 841 amdgpu_bo_free_kernel(&memory_pool->bo, 842 &memory_pool->mc_address, 843 &memory_pool->cpu_addr); 844 845 memset(memory_pool, 0, sizeof(struct smu_table)); 846 847 return 0; 848 } 849 850 static int smu_alloc_dummy_read_table(struct smu_context *smu) 851 { 852 struct smu_table_context *smu_table = &smu->smu_table; 853 struct smu_table *dummy_read_1_table = 854 &smu_table->dummy_read_1_table; 855 struct amdgpu_device *adev = smu->adev; 856 int ret = 0; 857 858 dummy_read_1_table->size = 0x40000; 859 dummy_read_1_table->align = PAGE_SIZE; 860 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 861 862 ret = amdgpu_bo_create_kernel(adev, 863 dummy_read_1_table->size, 864 dummy_read_1_table->align, 865 dummy_read_1_table->domain, 866 &dummy_read_1_table->bo, 867 &dummy_read_1_table->mc_address, 868 &dummy_read_1_table->cpu_addr); 869 if (ret) 870 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 871 872 return ret; 873 } 874 875 static void smu_free_dummy_read_table(struct smu_context *smu) 876 { 877 struct smu_table_context *smu_table = &smu->smu_table; 878 struct smu_table *dummy_read_1_table = 879 &smu_table->dummy_read_1_table; 880 881 882 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 883 &dummy_read_1_table->mc_address, 884 &dummy_read_1_table->cpu_addr); 885 886 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 887 } 888 889 static int smu_smc_table_sw_init(struct smu_context *smu) 890 { 891 int ret; 892 893 /** 894 * Create smu_table structure, and init smc tables such as 895 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 896 */ 897 ret = smu_init_smc_tables(smu); 898 if (ret) { 899 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 900 return ret; 901 } 902 903 /** 904 * Create smu_power_context structure, and allocate smu_dpm_context and 905 * context size to fill the smu_power_context data. 906 */ 907 ret = smu_init_power(smu); 908 if (ret) { 909 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 910 return ret; 911 } 912 913 /* 914 * allocate vram bos to store smc table contents. 915 */ 916 ret = smu_init_fb_allocations(smu); 917 if (ret) 918 return ret; 919 920 ret = smu_alloc_memory_pool(smu); 921 if (ret) 922 return ret; 923 924 ret = smu_alloc_dummy_read_table(smu); 925 if (ret) 926 return ret; 927 928 ret = smu_i2c_init(smu); 929 if (ret) 930 return ret; 931 932 return 0; 933 } 934 935 static int smu_smc_table_sw_fini(struct smu_context *smu) 936 { 937 int ret; 938 939 smu_i2c_fini(smu); 940 941 smu_free_dummy_read_table(smu); 942 943 ret = smu_free_memory_pool(smu); 944 if (ret) 945 return ret; 946 947 ret = smu_fini_fb_allocations(smu); 948 if (ret) 949 return ret; 950 951 ret = smu_fini_power(smu); 952 if (ret) { 953 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 954 return ret; 955 } 956 957 ret = smu_fini_smc_tables(smu); 958 if (ret) { 959 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 960 return ret; 961 } 962 963 return 0; 964 } 965 966 static void smu_throttling_logging_work_fn(struct work_struct *work) 967 { 968 struct smu_context *smu = container_of(work, struct smu_context, 969 throttling_logging_work); 970 971 smu_log_thermal_throttling(smu); 972 } 973 974 static void smu_interrupt_work_fn(struct work_struct *work) 975 { 976 struct smu_context *smu = container_of(work, struct smu_context, 977 interrupt_work); 978 979 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 980 smu->ppt_funcs->interrupt_work(smu); 981 } 982 983 static int smu_sw_init(void *handle) 984 { 985 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 986 struct smu_context *smu = adev->powerplay.pp_handle; 987 int ret; 988 989 smu->pool_size = adev->pm.smu_prv_buffer_size; 990 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 991 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 992 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 993 994 mutex_init(&smu->message_lock); 995 996 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 997 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 998 atomic64_set(&smu->throttle_int_counter, 0); 999 smu->watermarks_bitmap = 0; 1000 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1001 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1002 1003 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1004 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1005 1006 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1007 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1008 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1009 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1010 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1011 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1012 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1013 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1014 1015 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1016 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1017 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1018 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1019 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1020 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1021 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1022 smu->display_config = &adev->pm.pm_display_cfg; 1023 1024 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1025 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1026 1027 ret = smu_init_microcode(smu); 1028 if (ret) { 1029 dev_err(adev->dev, "Failed to load smu firmware!\n"); 1030 return ret; 1031 } 1032 1033 ret = smu_smc_table_sw_init(smu); 1034 if (ret) { 1035 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1036 return ret; 1037 } 1038 1039 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1040 ret = smu_get_vbios_bootup_values(smu); 1041 if (ret) { 1042 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1043 return ret; 1044 } 1045 1046 ret = smu_init_pptable_microcode(smu); 1047 if (ret) { 1048 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1049 return ret; 1050 } 1051 1052 ret = smu_register_irq_handler(smu); 1053 if (ret) { 1054 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1055 return ret; 1056 } 1057 1058 /* If there is no way to query fan control mode, fan control is not supported */ 1059 if (!smu->ppt_funcs->get_fan_control_mode) 1060 smu->adev->pm.no_fan = true; 1061 1062 return 0; 1063 } 1064 1065 static int smu_sw_fini(void *handle) 1066 { 1067 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1068 struct smu_context *smu = adev->powerplay.pp_handle; 1069 int ret; 1070 1071 ret = smu_smc_table_sw_fini(smu); 1072 if (ret) { 1073 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1074 return ret; 1075 } 1076 1077 smu_fini_microcode(smu); 1078 1079 return 0; 1080 } 1081 1082 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1083 { 1084 struct amdgpu_device *adev = smu->adev; 1085 struct smu_temperature_range *range = 1086 &smu->thermal_range; 1087 int ret = 0; 1088 1089 if (!smu->ppt_funcs->get_thermal_temperature_range) 1090 return 0; 1091 1092 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1093 if (ret) 1094 return ret; 1095 1096 adev->pm.dpm.thermal.min_temp = range->min; 1097 adev->pm.dpm.thermal.max_temp = range->max; 1098 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1099 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1100 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1101 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1102 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1103 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1104 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1105 1106 return ret; 1107 } 1108 1109 static int smu_smc_hw_setup(struct smu_context *smu) 1110 { 1111 struct smu_feature *feature = &smu->smu_feature; 1112 struct amdgpu_device *adev = smu->adev; 1113 uint32_t pcie_gen = 0, pcie_width = 0; 1114 uint64_t features_supported; 1115 int ret = 0; 1116 1117 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1118 dev_info(adev->dev, "dpm has been enabled\n"); 1119 /* this is needed specifically */ 1120 switch (adev->ip_versions[MP1_HWIP][0]) { 1121 case IP_VERSION(11, 0, 7): 1122 case IP_VERSION(11, 0, 11): 1123 case IP_VERSION(11, 5, 0): 1124 case IP_VERSION(11, 0, 12): 1125 ret = smu_system_features_control(smu, true); 1126 if (ret) 1127 dev_err(adev->dev, "Failed system features control!\n"); 1128 break; 1129 default: 1130 break; 1131 } 1132 return ret; 1133 } 1134 1135 ret = smu_init_display_count(smu, 0); 1136 if (ret) { 1137 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1138 return ret; 1139 } 1140 1141 ret = smu_set_driver_table_location(smu); 1142 if (ret) { 1143 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1144 return ret; 1145 } 1146 1147 /* 1148 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1149 */ 1150 ret = smu_set_tool_table_location(smu); 1151 if (ret) { 1152 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1153 return ret; 1154 } 1155 1156 /* 1157 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1158 * pool location. 1159 */ 1160 ret = smu_notify_memory_pool_location(smu); 1161 if (ret) { 1162 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1163 return ret; 1164 } 1165 1166 ret = smu_setup_pptable(smu); 1167 if (ret) { 1168 dev_err(adev->dev, "Failed to setup pptable!\n"); 1169 return ret; 1170 } 1171 1172 /* smu_dump_pptable(smu); */ 1173 1174 /* 1175 * With SCPM enabled, PSP is responsible for the PPTable transferring 1176 * (to SMU). Driver involvement is not needed and permitted. 1177 */ 1178 if (!adev->scpm_enabled) { 1179 /* 1180 * Copy pptable bo in the vram to smc with SMU MSGs such as 1181 * SetDriverDramAddr and TransferTableDram2Smu. 1182 */ 1183 ret = smu_write_pptable(smu); 1184 if (ret) { 1185 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1186 return ret; 1187 } 1188 } 1189 1190 /* issue Run*Btc msg */ 1191 ret = smu_run_btc(smu); 1192 if (ret) 1193 return ret; 1194 1195 /* 1196 * With SCPM enabled, these actions(and relevant messages) are 1197 * not needed and permitted. 1198 */ 1199 if (!adev->scpm_enabled) { 1200 ret = smu_feature_set_allowed_mask(smu); 1201 if (ret) { 1202 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1203 return ret; 1204 } 1205 } 1206 1207 ret = smu_system_features_control(smu, true); 1208 if (ret) { 1209 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1210 return ret; 1211 } 1212 1213 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1214 if (ret) { 1215 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1216 return ret; 1217 } 1218 bitmap_copy(feature->supported, 1219 (unsigned long *)&features_supported, 1220 feature->feature_num); 1221 1222 if (!smu_is_dpm_running(smu)) 1223 dev_info(adev->dev, "dpm has been disabled\n"); 1224 1225 /* 1226 * Set initialized values (get from vbios) to dpm tables context such as 1227 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1228 * type of clks. 1229 */ 1230 ret = smu_set_default_dpm_table(smu); 1231 if (ret) { 1232 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1233 return ret; 1234 } 1235 1236 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1237 pcie_gen = 3; 1238 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1239 pcie_gen = 2; 1240 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1241 pcie_gen = 1; 1242 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1243 pcie_gen = 0; 1244 1245 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1246 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1247 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1248 */ 1249 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1250 pcie_width = 6; 1251 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1252 pcie_width = 5; 1253 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1254 pcie_width = 4; 1255 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1256 pcie_width = 3; 1257 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1258 pcie_width = 2; 1259 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1260 pcie_width = 1; 1261 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1262 if (ret) { 1263 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1264 return ret; 1265 } 1266 1267 ret = smu_get_thermal_temperature_range(smu); 1268 if (ret) { 1269 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1270 return ret; 1271 } 1272 1273 ret = smu_enable_thermal_alert(smu); 1274 if (ret) { 1275 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1276 return ret; 1277 } 1278 1279 ret = smu_notify_display_change(smu); 1280 if (ret) { 1281 dev_err(adev->dev, "Failed to notify display change!\n"); 1282 return ret; 1283 } 1284 1285 /* 1286 * Set min deep sleep dce fclk with bootup value from vbios via 1287 * SetMinDeepSleepDcefclk MSG. 1288 */ 1289 ret = smu_set_min_dcef_deep_sleep(smu, 1290 smu->smu_table.boot_values.dcefclk / 100); 1291 1292 return ret; 1293 } 1294 1295 static int smu_start_smc_engine(struct smu_context *smu) 1296 { 1297 struct amdgpu_device *adev = smu->adev; 1298 int ret = 0; 1299 1300 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1301 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) { 1302 if (smu->ppt_funcs->load_microcode) { 1303 ret = smu->ppt_funcs->load_microcode(smu); 1304 if (ret) 1305 return ret; 1306 } 1307 } 1308 } 1309 1310 if (smu->ppt_funcs->check_fw_status) { 1311 ret = smu->ppt_funcs->check_fw_status(smu); 1312 if (ret) { 1313 dev_err(adev->dev, "SMC is not ready\n"); 1314 return ret; 1315 } 1316 } 1317 1318 /* 1319 * Send msg GetDriverIfVersion to check if the return value is equal 1320 * with DRIVER_IF_VERSION of smc header. 1321 */ 1322 ret = smu_check_fw_version(smu); 1323 if (ret) 1324 return ret; 1325 1326 return ret; 1327 } 1328 1329 static int smu_hw_init(void *handle) 1330 { 1331 int ret; 1332 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1333 struct smu_context *smu = adev->powerplay.pp_handle; 1334 1335 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1336 smu->pm_enabled = false; 1337 return 0; 1338 } 1339 1340 ret = smu_start_smc_engine(smu); 1341 if (ret) { 1342 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1343 return ret; 1344 } 1345 1346 if (smu->is_apu) { 1347 smu_dpm_set_vcn_enable(smu, true); 1348 smu_dpm_set_jpeg_enable(smu, true); 1349 smu_set_gfx_cgpg(smu, true); 1350 } 1351 1352 if (!smu->pm_enabled) 1353 return 0; 1354 1355 ret = smu_get_driver_allowed_feature_mask(smu); 1356 if (ret) 1357 return ret; 1358 1359 ret = smu_smc_hw_setup(smu); 1360 if (ret) { 1361 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1362 return ret; 1363 } 1364 1365 /* 1366 * Move maximum sustainable clock retrieving here considering 1367 * 1. It is not needed on resume(from S3). 1368 * 2. DAL settings come between .hw_init and .late_init of SMU. 1369 * And DAL needs to know the maximum sustainable clocks. Thus 1370 * it cannot be put in .late_init(). 1371 */ 1372 ret = smu_init_max_sustainable_clocks(smu); 1373 if (ret) { 1374 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1375 return ret; 1376 } 1377 1378 adev->pm.dpm_enabled = true; 1379 1380 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1381 1382 return 0; 1383 } 1384 1385 static int smu_disable_dpms(struct smu_context *smu) 1386 { 1387 struct amdgpu_device *adev = smu->adev; 1388 int ret = 0; 1389 /* 1390 * TODO: (adev->in_suspend && !adev->in_s0ix) is added to pair 1391 * the workaround which always reset the asic in suspend. 1392 * It's likely that workaround will be dropped in the future. 1393 * Then the change here should be dropped together. 1394 */ 1395 bool use_baco = !smu->is_apu && 1396 (((amdgpu_in_reset(adev) || (adev->in_suspend && !adev->in_s0ix)) && 1397 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1398 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1399 1400 /* 1401 * For custom pptable uploading, skip the DPM features 1402 * disable process on Navi1x ASICs. 1403 * - As the gfx related features are under control of 1404 * RLC on those ASICs. RLC reinitialization will be 1405 * needed to reenable them. That will cost much more 1406 * efforts. 1407 * 1408 * - SMU firmware can handle the DPM reenablement 1409 * properly. 1410 */ 1411 if (smu->uploading_custom_pp_table) { 1412 switch (adev->ip_versions[MP1_HWIP][0]) { 1413 case IP_VERSION(11, 0, 0): 1414 case IP_VERSION(11, 0, 5): 1415 case IP_VERSION(11, 0, 9): 1416 case IP_VERSION(11, 0, 7): 1417 case IP_VERSION(11, 0, 11): 1418 case IP_VERSION(11, 5, 0): 1419 case IP_VERSION(11, 0, 12): 1420 case IP_VERSION(11, 0, 13): 1421 return 0; 1422 default: 1423 break; 1424 } 1425 } 1426 1427 /* 1428 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1429 * on BACO in. Driver involvement is unnecessary. 1430 */ 1431 if (use_baco) { 1432 switch (adev->ip_versions[MP1_HWIP][0]) { 1433 case IP_VERSION(11, 0, 7): 1434 case IP_VERSION(11, 0, 0): 1435 case IP_VERSION(11, 0, 5): 1436 case IP_VERSION(11, 0, 9): 1437 return 0; 1438 default: 1439 break; 1440 } 1441 } 1442 1443 /* 1444 * For gpu reset, runpm and hibernation through BACO, 1445 * BACO feature has to be kept enabled. 1446 */ 1447 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1448 ret = smu_disable_all_features_with_exception(smu, 1449 SMU_FEATURE_BACO_BIT); 1450 if (ret) 1451 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1452 } else { 1453 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1454 if (!adev->scpm_enabled) { 1455 ret = smu_system_features_control(smu, false); 1456 if (ret) 1457 dev_err(adev->dev, "Failed to disable smu features.\n"); 1458 } 1459 } 1460 1461 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) && 1462 adev->gfx.rlc.funcs->stop) 1463 adev->gfx.rlc.funcs->stop(adev); 1464 1465 return ret; 1466 } 1467 1468 static int smu_smc_hw_cleanup(struct smu_context *smu) 1469 { 1470 struct amdgpu_device *adev = smu->adev; 1471 int ret = 0; 1472 1473 cancel_work_sync(&smu->throttling_logging_work); 1474 cancel_work_sync(&smu->interrupt_work); 1475 1476 ret = smu_disable_thermal_alert(smu); 1477 if (ret) { 1478 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1479 return ret; 1480 } 1481 1482 ret = smu_disable_dpms(smu); 1483 if (ret) { 1484 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1485 return ret; 1486 } 1487 1488 return 0; 1489 } 1490 1491 static int smu_hw_fini(void *handle) 1492 { 1493 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1494 struct smu_context *smu = adev->powerplay.pp_handle; 1495 1496 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1497 return 0; 1498 1499 smu_dpm_set_vcn_enable(smu, false); 1500 smu_dpm_set_jpeg_enable(smu, false); 1501 1502 adev->vcn.cur_state = AMD_PG_STATE_GATE; 1503 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 1504 1505 if (!smu->pm_enabled) 1506 return 0; 1507 1508 adev->pm.dpm_enabled = false; 1509 1510 return smu_smc_hw_cleanup(smu); 1511 } 1512 1513 static void smu_late_fini(void *handle) 1514 { 1515 struct amdgpu_device *adev = handle; 1516 struct smu_context *smu = adev->powerplay.pp_handle; 1517 1518 kfree(smu); 1519 } 1520 1521 static int smu_reset(struct smu_context *smu) 1522 { 1523 struct amdgpu_device *adev = smu->adev; 1524 int ret; 1525 1526 ret = smu_hw_fini(adev); 1527 if (ret) 1528 return ret; 1529 1530 ret = smu_hw_init(adev); 1531 if (ret) 1532 return ret; 1533 1534 ret = smu_late_init(adev); 1535 if (ret) 1536 return ret; 1537 1538 return 0; 1539 } 1540 1541 static int smu_suspend(void *handle) 1542 { 1543 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1544 struct smu_context *smu = adev->powerplay.pp_handle; 1545 int ret; 1546 1547 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1548 return 0; 1549 1550 if (!smu->pm_enabled) 1551 return 0; 1552 1553 adev->pm.dpm_enabled = false; 1554 1555 ret = smu_smc_hw_cleanup(smu); 1556 if (ret) 1557 return ret; 1558 1559 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1560 1561 smu_set_gfx_cgpg(smu, false); 1562 1563 return 0; 1564 } 1565 1566 static int smu_resume(void *handle) 1567 { 1568 int ret; 1569 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1570 struct smu_context *smu = adev->powerplay.pp_handle; 1571 1572 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1573 return 0; 1574 1575 if (!smu->pm_enabled) 1576 return 0; 1577 1578 dev_info(adev->dev, "SMU is resuming...\n"); 1579 1580 ret = smu_start_smc_engine(smu); 1581 if (ret) { 1582 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1583 return ret; 1584 } 1585 1586 ret = smu_smc_hw_setup(smu); 1587 if (ret) { 1588 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1589 return ret; 1590 } 1591 1592 smu_set_gfx_cgpg(smu, true); 1593 1594 smu->disable_uclk_switch = 0; 1595 1596 adev->pm.dpm_enabled = true; 1597 1598 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1599 1600 return 0; 1601 } 1602 1603 static int smu_display_configuration_change(void *handle, 1604 const struct amd_pp_display_configuration *display_config) 1605 { 1606 struct smu_context *smu = handle; 1607 int index = 0; 1608 int num_of_active_display = 0; 1609 1610 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1611 return -EOPNOTSUPP; 1612 1613 if (!display_config) 1614 return -EINVAL; 1615 1616 smu_set_min_dcef_deep_sleep(smu, 1617 display_config->min_dcef_deep_sleep_set_clk / 100); 1618 1619 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1620 if (display_config->displays[index].controller_id != 0) 1621 num_of_active_display++; 1622 } 1623 1624 return 0; 1625 } 1626 1627 static int smu_set_clockgating_state(void *handle, 1628 enum amd_clockgating_state state) 1629 { 1630 return 0; 1631 } 1632 1633 static int smu_set_powergating_state(void *handle, 1634 enum amd_powergating_state state) 1635 { 1636 return 0; 1637 } 1638 1639 static int smu_enable_umd_pstate(void *handle, 1640 enum amd_dpm_forced_level *level) 1641 { 1642 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1643 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1644 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1645 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1646 1647 struct smu_context *smu = (struct smu_context*)(handle); 1648 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1649 1650 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1651 return -EINVAL; 1652 1653 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1654 /* enter umd pstate, save current level, disable gfx cg*/ 1655 if (*level & profile_mode_mask) { 1656 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1657 smu_gpo_control(smu, false); 1658 smu_gfx_ulv_control(smu, false); 1659 smu_deep_sleep_control(smu, false); 1660 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1661 } 1662 } else { 1663 /* exit umd pstate, restore level, enable gfx cg*/ 1664 if (!(*level & profile_mode_mask)) { 1665 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1666 *level = smu_dpm_ctx->saved_dpm_level; 1667 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1668 smu_deep_sleep_control(smu, true); 1669 smu_gfx_ulv_control(smu, true); 1670 smu_gpo_control(smu, true); 1671 } 1672 } 1673 1674 return 0; 1675 } 1676 1677 static int smu_bump_power_profile_mode(struct smu_context *smu, 1678 long *param, 1679 uint32_t param_size) 1680 { 1681 int ret = 0; 1682 1683 if (smu->ppt_funcs->set_power_profile_mode) 1684 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1685 1686 return ret; 1687 } 1688 1689 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1690 enum amd_dpm_forced_level level, 1691 bool skip_display_settings) 1692 { 1693 int ret = 0; 1694 int index = 0; 1695 long workload; 1696 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1697 1698 if (!skip_display_settings) { 1699 ret = smu_display_config_changed(smu); 1700 if (ret) { 1701 dev_err(smu->adev->dev, "Failed to change display config!"); 1702 return ret; 1703 } 1704 } 1705 1706 ret = smu_apply_clocks_adjust_rules(smu); 1707 if (ret) { 1708 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1709 return ret; 1710 } 1711 1712 if (!skip_display_settings) { 1713 ret = smu_notify_smc_display_config(smu); 1714 if (ret) { 1715 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1716 return ret; 1717 } 1718 } 1719 1720 if (smu_dpm_ctx->dpm_level != level) { 1721 ret = smu_asic_set_performance_level(smu, level); 1722 if (ret) { 1723 dev_err(smu->adev->dev, "Failed to set performance level!"); 1724 return ret; 1725 } 1726 1727 /* update the saved copy */ 1728 smu_dpm_ctx->dpm_level = level; 1729 } 1730 1731 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1732 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1733 index = fls(smu->workload_mask); 1734 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1735 workload = smu->workload_setting[index]; 1736 1737 if (smu->power_profile_mode != workload) 1738 smu_bump_power_profile_mode(smu, &workload, 0); 1739 } 1740 1741 return ret; 1742 } 1743 1744 static int smu_handle_task(struct smu_context *smu, 1745 enum amd_dpm_forced_level level, 1746 enum amd_pp_task task_id) 1747 { 1748 int ret = 0; 1749 1750 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1751 return -EOPNOTSUPP; 1752 1753 switch (task_id) { 1754 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1755 ret = smu_pre_display_config_changed(smu); 1756 if (ret) 1757 return ret; 1758 ret = smu_adjust_power_state_dynamic(smu, level, false); 1759 break; 1760 case AMD_PP_TASK_COMPLETE_INIT: 1761 case AMD_PP_TASK_READJUST_POWER_STATE: 1762 ret = smu_adjust_power_state_dynamic(smu, level, true); 1763 break; 1764 default: 1765 break; 1766 } 1767 1768 return ret; 1769 } 1770 1771 static int smu_handle_dpm_task(void *handle, 1772 enum amd_pp_task task_id, 1773 enum amd_pm_state_type *user_state) 1774 { 1775 struct smu_context *smu = handle; 1776 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1777 1778 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 1779 1780 } 1781 1782 static int smu_switch_power_profile(void *handle, 1783 enum PP_SMC_POWER_PROFILE type, 1784 bool en) 1785 { 1786 struct smu_context *smu = handle; 1787 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1788 long workload; 1789 uint32_t index; 1790 1791 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1792 return -EOPNOTSUPP; 1793 1794 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1795 return -EINVAL; 1796 1797 if (!en) { 1798 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1799 index = fls(smu->workload_mask); 1800 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1801 workload = smu->workload_setting[index]; 1802 } else { 1803 smu->workload_mask |= (1 << smu->workload_prority[type]); 1804 index = fls(smu->workload_mask); 1805 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1806 workload = smu->workload_setting[index]; 1807 } 1808 1809 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1810 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1811 smu_bump_power_profile_mode(smu, &workload, 0); 1812 1813 return 0; 1814 } 1815 1816 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 1817 { 1818 struct smu_context *smu = handle; 1819 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1820 1821 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1822 return -EOPNOTSUPP; 1823 1824 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1825 return -EINVAL; 1826 1827 return smu_dpm_ctx->dpm_level; 1828 } 1829 1830 static int smu_force_performance_level(void *handle, 1831 enum amd_dpm_forced_level level) 1832 { 1833 struct smu_context *smu = handle; 1834 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1835 int ret = 0; 1836 1837 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1838 return -EOPNOTSUPP; 1839 1840 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1841 return -EINVAL; 1842 1843 ret = smu_enable_umd_pstate(smu, &level); 1844 if (ret) 1845 return ret; 1846 1847 ret = smu_handle_task(smu, level, 1848 AMD_PP_TASK_READJUST_POWER_STATE); 1849 1850 /* reset user dpm clock state */ 1851 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1852 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 1853 smu->user_dpm_profile.clk_dependency = 0; 1854 } 1855 1856 return ret; 1857 } 1858 1859 static int smu_set_display_count(void *handle, uint32_t count) 1860 { 1861 struct smu_context *smu = handle; 1862 1863 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1864 return -EOPNOTSUPP; 1865 1866 return smu_init_display_count(smu, count); 1867 } 1868 1869 static int smu_force_smuclk_levels(struct smu_context *smu, 1870 enum smu_clk_type clk_type, 1871 uint32_t mask) 1872 { 1873 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1874 int ret = 0; 1875 1876 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1877 return -EOPNOTSUPP; 1878 1879 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1880 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1881 return -EINVAL; 1882 } 1883 1884 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 1885 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1886 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 1887 smu->user_dpm_profile.clk_mask[clk_type] = mask; 1888 smu_set_user_clk_dependencies(smu, clk_type); 1889 } 1890 } 1891 1892 return ret; 1893 } 1894 1895 static int smu_force_ppclk_levels(void *handle, 1896 enum pp_clock_type type, 1897 uint32_t mask) 1898 { 1899 struct smu_context *smu = handle; 1900 enum smu_clk_type clk_type; 1901 1902 switch (type) { 1903 case PP_SCLK: 1904 clk_type = SMU_SCLK; break; 1905 case PP_MCLK: 1906 clk_type = SMU_MCLK; break; 1907 case PP_PCIE: 1908 clk_type = SMU_PCIE; break; 1909 case PP_SOCCLK: 1910 clk_type = SMU_SOCCLK; break; 1911 case PP_FCLK: 1912 clk_type = SMU_FCLK; break; 1913 case PP_DCEFCLK: 1914 clk_type = SMU_DCEFCLK; break; 1915 case PP_VCLK: 1916 clk_type = SMU_VCLK; break; 1917 case PP_DCLK: 1918 clk_type = SMU_DCLK; break; 1919 case OD_SCLK: 1920 clk_type = SMU_OD_SCLK; break; 1921 case OD_MCLK: 1922 clk_type = SMU_OD_MCLK; break; 1923 case OD_VDDC_CURVE: 1924 clk_type = SMU_OD_VDDC_CURVE; break; 1925 case OD_RANGE: 1926 clk_type = SMU_OD_RANGE; break; 1927 default: 1928 return -EINVAL; 1929 } 1930 1931 return smu_force_smuclk_levels(smu, clk_type, mask); 1932 } 1933 1934 /* 1935 * On system suspending or resetting, the dpm_enabled 1936 * flag will be cleared. So that those SMU services which 1937 * are not supported will be gated. 1938 * However, the mp1 state setting should still be granted 1939 * even if the dpm_enabled cleared. 1940 */ 1941 static int smu_set_mp1_state(void *handle, 1942 enum pp_mp1_state mp1_state) 1943 { 1944 struct smu_context *smu = handle; 1945 int ret = 0; 1946 1947 if (!smu->pm_enabled) 1948 return -EOPNOTSUPP; 1949 1950 if (smu->ppt_funcs && 1951 smu->ppt_funcs->set_mp1_state) 1952 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 1953 1954 return ret; 1955 } 1956 1957 static int smu_set_df_cstate(void *handle, 1958 enum pp_df_cstate state) 1959 { 1960 struct smu_context *smu = handle; 1961 int ret = 0; 1962 1963 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1964 return -EOPNOTSUPP; 1965 1966 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 1967 return 0; 1968 1969 ret = smu->ppt_funcs->set_df_cstate(smu, state); 1970 if (ret) 1971 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 1972 1973 return ret; 1974 } 1975 1976 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 1977 { 1978 int ret = 0; 1979 1980 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1981 return -EOPNOTSUPP; 1982 1983 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 1984 return 0; 1985 1986 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 1987 if (ret) 1988 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 1989 1990 return ret; 1991 } 1992 1993 int smu_write_watermarks_table(struct smu_context *smu) 1994 { 1995 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1996 return -EOPNOTSUPP; 1997 1998 return smu_set_watermarks_table(smu, NULL); 1999 } 2000 2001 static int smu_set_watermarks_for_clock_ranges(void *handle, 2002 struct pp_smu_wm_range_sets *clock_ranges) 2003 { 2004 struct smu_context *smu = handle; 2005 2006 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2007 return -EOPNOTSUPP; 2008 2009 if (smu->disable_watermark) 2010 return 0; 2011 2012 return smu_set_watermarks_table(smu, clock_ranges); 2013 } 2014 2015 int smu_set_ac_dc(struct smu_context *smu) 2016 { 2017 int ret = 0; 2018 2019 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2020 return -EOPNOTSUPP; 2021 2022 /* controlled by firmware */ 2023 if (smu->dc_controlled_by_gpio) 2024 return 0; 2025 2026 ret = smu_set_power_source(smu, 2027 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2028 SMU_POWER_SOURCE_DC); 2029 if (ret) 2030 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2031 smu->adev->pm.ac_power ? "AC" : "DC"); 2032 2033 return ret; 2034 } 2035 2036 const struct amd_ip_funcs smu_ip_funcs = { 2037 .name = "smu", 2038 .early_init = smu_early_init, 2039 .late_init = smu_late_init, 2040 .sw_init = smu_sw_init, 2041 .sw_fini = smu_sw_fini, 2042 .hw_init = smu_hw_init, 2043 .hw_fini = smu_hw_fini, 2044 .late_fini = smu_late_fini, 2045 .suspend = smu_suspend, 2046 .resume = smu_resume, 2047 .is_idle = NULL, 2048 .check_soft_reset = NULL, 2049 .wait_for_idle = NULL, 2050 .soft_reset = NULL, 2051 .set_clockgating_state = smu_set_clockgating_state, 2052 .set_powergating_state = smu_set_powergating_state, 2053 }; 2054 2055 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 2056 { 2057 .type = AMD_IP_BLOCK_TYPE_SMC, 2058 .major = 11, 2059 .minor = 0, 2060 .rev = 0, 2061 .funcs = &smu_ip_funcs, 2062 }; 2063 2064 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 2065 { 2066 .type = AMD_IP_BLOCK_TYPE_SMC, 2067 .major = 12, 2068 .minor = 0, 2069 .rev = 0, 2070 .funcs = &smu_ip_funcs, 2071 }; 2072 2073 const struct amdgpu_ip_block_version smu_v13_0_ip_block = 2074 { 2075 .type = AMD_IP_BLOCK_TYPE_SMC, 2076 .major = 13, 2077 .minor = 0, 2078 .rev = 0, 2079 .funcs = &smu_ip_funcs, 2080 }; 2081 2082 static int smu_load_microcode(void *handle) 2083 { 2084 struct smu_context *smu = handle; 2085 struct amdgpu_device *adev = smu->adev; 2086 int ret = 0; 2087 2088 if (!smu->pm_enabled) 2089 return -EOPNOTSUPP; 2090 2091 /* This should be used for non PSP loading */ 2092 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2093 return 0; 2094 2095 if (smu->ppt_funcs->load_microcode) { 2096 ret = smu->ppt_funcs->load_microcode(smu); 2097 if (ret) { 2098 dev_err(adev->dev, "Load microcode failed\n"); 2099 return ret; 2100 } 2101 } 2102 2103 if (smu->ppt_funcs->check_fw_status) { 2104 ret = smu->ppt_funcs->check_fw_status(smu); 2105 if (ret) { 2106 dev_err(adev->dev, "SMC is not ready\n"); 2107 return ret; 2108 } 2109 } 2110 2111 return ret; 2112 } 2113 2114 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2115 { 2116 int ret = 0; 2117 2118 if (smu->ppt_funcs->set_gfx_cgpg) 2119 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2120 2121 return ret; 2122 } 2123 2124 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2125 { 2126 struct smu_context *smu = handle; 2127 int ret = 0; 2128 2129 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2130 return -EOPNOTSUPP; 2131 2132 if (!smu->ppt_funcs->set_fan_speed_rpm) 2133 return -EOPNOTSUPP; 2134 2135 if (speed == U32_MAX) 2136 return -EINVAL; 2137 2138 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2139 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2140 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2141 smu->user_dpm_profile.fan_speed_rpm = speed; 2142 2143 /* Override custom PWM setting as they cannot co-exist */ 2144 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2145 smu->user_dpm_profile.fan_speed_pwm = 0; 2146 } 2147 2148 return ret; 2149 } 2150 2151 /** 2152 * smu_get_power_limit - Request one of the SMU Power Limits 2153 * 2154 * @handle: pointer to smu context 2155 * @limit: requested limit is written back to this variable 2156 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2157 * @pp_power_type: &pp_power_type type of power 2158 * Return: 0 on success, <0 on error 2159 * 2160 */ 2161 int smu_get_power_limit(void *handle, 2162 uint32_t *limit, 2163 enum pp_power_limit_level pp_limit_level, 2164 enum pp_power_type pp_power_type) 2165 { 2166 struct smu_context *smu = handle; 2167 struct amdgpu_device *adev = smu->adev; 2168 enum smu_ppt_limit_level limit_level; 2169 uint32_t limit_type; 2170 int ret = 0; 2171 2172 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2173 return -EOPNOTSUPP; 2174 2175 switch(pp_power_type) { 2176 case PP_PWR_TYPE_SUSTAINED: 2177 limit_type = SMU_DEFAULT_PPT_LIMIT; 2178 break; 2179 case PP_PWR_TYPE_FAST: 2180 limit_type = SMU_FAST_PPT_LIMIT; 2181 break; 2182 default: 2183 return -EOPNOTSUPP; 2184 break; 2185 } 2186 2187 switch(pp_limit_level){ 2188 case PP_PWR_LIMIT_CURRENT: 2189 limit_level = SMU_PPT_LIMIT_CURRENT; 2190 break; 2191 case PP_PWR_LIMIT_DEFAULT: 2192 limit_level = SMU_PPT_LIMIT_DEFAULT; 2193 break; 2194 case PP_PWR_LIMIT_MAX: 2195 limit_level = SMU_PPT_LIMIT_MAX; 2196 break; 2197 case PP_PWR_LIMIT_MIN: 2198 default: 2199 return -EOPNOTSUPP; 2200 break; 2201 } 2202 2203 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2204 if (smu->ppt_funcs->get_ppt_limit) 2205 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2206 } else { 2207 switch (limit_level) { 2208 case SMU_PPT_LIMIT_CURRENT: 2209 switch (adev->ip_versions[MP1_HWIP][0]) { 2210 case IP_VERSION(13, 0, 2): 2211 case IP_VERSION(11, 0, 7): 2212 case IP_VERSION(11, 0, 11): 2213 case IP_VERSION(11, 0, 12): 2214 case IP_VERSION(11, 0, 13): 2215 ret = smu_get_asic_power_limits(smu, 2216 &smu->current_power_limit, 2217 NULL, 2218 NULL); 2219 break; 2220 default: 2221 break; 2222 } 2223 *limit = smu->current_power_limit; 2224 break; 2225 case SMU_PPT_LIMIT_DEFAULT: 2226 *limit = smu->default_power_limit; 2227 break; 2228 case SMU_PPT_LIMIT_MAX: 2229 *limit = smu->max_power_limit; 2230 break; 2231 default: 2232 break; 2233 } 2234 } 2235 2236 return ret; 2237 } 2238 2239 static int smu_set_power_limit(void *handle, uint32_t limit) 2240 { 2241 struct smu_context *smu = handle; 2242 uint32_t limit_type = limit >> 24; 2243 int ret = 0; 2244 2245 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2246 return -EOPNOTSUPP; 2247 2248 limit &= (1<<24)-1; 2249 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2250 if (smu->ppt_funcs->set_power_limit) 2251 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2252 2253 if (limit > smu->max_power_limit) { 2254 dev_err(smu->adev->dev, 2255 "New power limit (%d) is over the max allowed %d\n", 2256 limit, smu->max_power_limit); 2257 return -EINVAL; 2258 } 2259 2260 if (!limit) 2261 limit = smu->current_power_limit; 2262 2263 if (smu->ppt_funcs->set_power_limit) { 2264 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2265 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2266 smu->user_dpm_profile.power_limit = limit; 2267 } 2268 2269 return ret; 2270 } 2271 2272 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2273 { 2274 int ret = 0; 2275 2276 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2277 return -EOPNOTSUPP; 2278 2279 if (smu->ppt_funcs->print_clk_levels) 2280 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2281 2282 return ret; 2283 } 2284 2285 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2286 { 2287 enum smu_clk_type clk_type; 2288 2289 switch (type) { 2290 case PP_SCLK: 2291 clk_type = SMU_SCLK; break; 2292 case PP_MCLK: 2293 clk_type = SMU_MCLK; break; 2294 case PP_PCIE: 2295 clk_type = SMU_PCIE; break; 2296 case PP_SOCCLK: 2297 clk_type = SMU_SOCCLK; break; 2298 case PP_FCLK: 2299 clk_type = SMU_FCLK; break; 2300 case PP_DCEFCLK: 2301 clk_type = SMU_DCEFCLK; break; 2302 case PP_VCLK: 2303 clk_type = SMU_VCLK; break; 2304 case PP_DCLK: 2305 clk_type = SMU_DCLK; break; 2306 case OD_SCLK: 2307 clk_type = SMU_OD_SCLK; break; 2308 case OD_MCLK: 2309 clk_type = SMU_OD_MCLK; break; 2310 case OD_VDDC_CURVE: 2311 clk_type = SMU_OD_VDDC_CURVE; break; 2312 case OD_RANGE: 2313 clk_type = SMU_OD_RANGE; break; 2314 case OD_VDDGFX_OFFSET: 2315 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2316 case OD_CCLK: 2317 clk_type = SMU_OD_CCLK; break; 2318 default: 2319 clk_type = SMU_CLK_COUNT; break; 2320 } 2321 2322 return clk_type; 2323 } 2324 2325 static int smu_print_ppclk_levels(void *handle, 2326 enum pp_clock_type type, 2327 char *buf) 2328 { 2329 struct smu_context *smu = handle; 2330 enum smu_clk_type clk_type; 2331 2332 clk_type = smu_convert_to_smuclk(type); 2333 if (clk_type == SMU_CLK_COUNT) 2334 return -EINVAL; 2335 2336 return smu_print_smuclk_levels(smu, clk_type, buf); 2337 } 2338 2339 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2340 { 2341 struct smu_context *smu = handle; 2342 enum smu_clk_type clk_type; 2343 2344 clk_type = smu_convert_to_smuclk(type); 2345 if (clk_type == SMU_CLK_COUNT) 2346 return -EINVAL; 2347 2348 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2349 return -EOPNOTSUPP; 2350 2351 if (!smu->ppt_funcs->emit_clk_levels) 2352 return -ENOENT; 2353 2354 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2355 2356 } 2357 2358 static int smu_od_edit_dpm_table(void *handle, 2359 enum PP_OD_DPM_TABLE_COMMAND type, 2360 long *input, uint32_t size) 2361 { 2362 struct smu_context *smu = handle; 2363 int ret = 0; 2364 2365 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2366 return -EOPNOTSUPP; 2367 2368 if (smu->ppt_funcs->od_edit_dpm_table) { 2369 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2370 } 2371 2372 return ret; 2373 } 2374 2375 static int smu_read_sensor(void *handle, 2376 int sensor, 2377 void *data, 2378 int *size_arg) 2379 { 2380 struct smu_context *smu = handle; 2381 struct smu_umd_pstate_table *pstate_table = 2382 &smu->pstate_table; 2383 int ret = 0; 2384 uint32_t *size, size_val; 2385 2386 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2387 return -EOPNOTSUPP; 2388 2389 if (!data || !size_arg) 2390 return -EINVAL; 2391 2392 size_val = *size_arg; 2393 size = &size_val; 2394 2395 if (smu->ppt_funcs->read_sensor) 2396 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2397 goto unlock; 2398 2399 switch (sensor) { 2400 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2401 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2402 *size = 4; 2403 break; 2404 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2405 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2406 *size = 4; 2407 break; 2408 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2409 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2410 *size = 8; 2411 break; 2412 case AMDGPU_PP_SENSOR_UVD_POWER: 2413 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2414 *size = 4; 2415 break; 2416 case AMDGPU_PP_SENSOR_VCE_POWER: 2417 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2418 *size = 4; 2419 break; 2420 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2421 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2422 *size = 4; 2423 break; 2424 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2425 *(uint32_t *)data = 0; 2426 *size = 4; 2427 break; 2428 default: 2429 *size = 0; 2430 ret = -EOPNOTSUPP; 2431 break; 2432 } 2433 2434 unlock: 2435 // assign uint32_t to int 2436 *size_arg = size_val; 2437 2438 return ret; 2439 } 2440 2441 static int smu_get_power_profile_mode(void *handle, char *buf) 2442 { 2443 struct smu_context *smu = handle; 2444 2445 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2446 !smu->ppt_funcs->get_power_profile_mode) 2447 return -EOPNOTSUPP; 2448 if (!buf) 2449 return -EINVAL; 2450 2451 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 2452 } 2453 2454 static int smu_set_power_profile_mode(void *handle, 2455 long *param, 2456 uint32_t param_size) 2457 { 2458 struct smu_context *smu = handle; 2459 2460 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2461 !smu->ppt_funcs->set_power_profile_mode) 2462 return -EOPNOTSUPP; 2463 2464 return smu_bump_power_profile_mode(smu, param, param_size); 2465 } 2466 2467 2468 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 2469 { 2470 struct smu_context *smu = handle; 2471 2472 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2473 return -EOPNOTSUPP; 2474 2475 if (!smu->ppt_funcs->get_fan_control_mode) 2476 return -EOPNOTSUPP; 2477 2478 if (!fan_mode) 2479 return -EINVAL; 2480 2481 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 2482 2483 return 0; 2484 } 2485 2486 static int smu_set_fan_control_mode(void *handle, u32 value) 2487 { 2488 struct smu_context *smu = handle; 2489 int ret = 0; 2490 2491 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2492 return -EOPNOTSUPP; 2493 2494 if (!smu->ppt_funcs->set_fan_control_mode) 2495 return -EOPNOTSUPP; 2496 2497 if (value == U32_MAX) 2498 return -EINVAL; 2499 2500 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2501 if (ret) 2502 goto out; 2503 2504 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2505 smu->user_dpm_profile.fan_mode = value; 2506 2507 /* reset user dpm fan speed */ 2508 if (value != AMD_FAN_CTRL_MANUAL) { 2509 smu->user_dpm_profile.fan_speed_pwm = 0; 2510 smu->user_dpm_profile.fan_speed_rpm = 0; 2511 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 2512 } 2513 } 2514 2515 out: 2516 return ret; 2517 } 2518 2519 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 2520 { 2521 struct smu_context *smu = handle; 2522 int ret = 0; 2523 2524 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2525 return -EOPNOTSUPP; 2526 2527 if (!smu->ppt_funcs->get_fan_speed_pwm) 2528 return -EOPNOTSUPP; 2529 2530 if (!speed) 2531 return -EINVAL; 2532 2533 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 2534 2535 return ret; 2536 } 2537 2538 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 2539 { 2540 struct smu_context *smu = handle; 2541 int ret = 0; 2542 2543 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2544 return -EOPNOTSUPP; 2545 2546 if (!smu->ppt_funcs->set_fan_speed_pwm) 2547 return -EOPNOTSUPP; 2548 2549 if (speed == U32_MAX) 2550 return -EINVAL; 2551 2552 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 2553 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2554 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 2555 smu->user_dpm_profile.fan_speed_pwm = speed; 2556 2557 /* Override custom RPM setting as they cannot co-exist */ 2558 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 2559 smu->user_dpm_profile.fan_speed_rpm = 0; 2560 } 2561 2562 return ret; 2563 } 2564 2565 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2566 { 2567 struct smu_context *smu = handle; 2568 int ret = 0; 2569 2570 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2571 return -EOPNOTSUPP; 2572 2573 if (!smu->ppt_funcs->get_fan_speed_rpm) 2574 return -EOPNOTSUPP; 2575 2576 if (!speed) 2577 return -EINVAL; 2578 2579 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 2580 2581 return ret; 2582 } 2583 2584 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 2585 { 2586 struct smu_context *smu = handle; 2587 2588 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2589 return -EOPNOTSUPP; 2590 2591 return smu_set_min_dcef_deep_sleep(smu, clk); 2592 } 2593 2594 static int smu_get_clock_by_type_with_latency(void *handle, 2595 enum amd_pp_clock_type type, 2596 struct pp_clock_levels_with_latency *clocks) 2597 { 2598 struct smu_context *smu = handle; 2599 enum smu_clk_type clk_type; 2600 int ret = 0; 2601 2602 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2603 return -EOPNOTSUPP; 2604 2605 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 2606 switch (type) { 2607 case amd_pp_sys_clock: 2608 clk_type = SMU_GFXCLK; 2609 break; 2610 case amd_pp_mem_clock: 2611 clk_type = SMU_MCLK; 2612 break; 2613 case amd_pp_dcef_clock: 2614 clk_type = SMU_DCEFCLK; 2615 break; 2616 case amd_pp_disp_clock: 2617 clk_type = SMU_DISPCLK; 2618 break; 2619 default: 2620 dev_err(smu->adev->dev, "Invalid clock type!\n"); 2621 return -EINVAL; 2622 } 2623 2624 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2625 } 2626 2627 return ret; 2628 } 2629 2630 static int smu_display_clock_voltage_request(void *handle, 2631 struct pp_display_clock_request *clock_req) 2632 { 2633 struct smu_context *smu = handle; 2634 int ret = 0; 2635 2636 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2637 return -EOPNOTSUPP; 2638 2639 if (smu->ppt_funcs->display_clock_voltage_request) 2640 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2641 2642 return ret; 2643 } 2644 2645 2646 static int smu_display_disable_memory_clock_switch(void *handle, 2647 bool disable_memory_clock_switch) 2648 { 2649 struct smu_context *smu = handle; 2650 int ret = -EINVAL; 2651 2652 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2653 return -EOPNOTSUPP; 2654 2655 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2656 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2657 2658 return ret; 2659 } 2660 2661 static int smu_set_xgmi_pstate(void *handle, 2662 uint32_t pstate) 2663 { 2664 struct smu_context *smu = handle; 2665 int ret = 0; 2666 2667 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2668 return -EOPNOTSUPP; 2669 2670 if (smu->ppt_funcs->set_xgmi_pstate) 2671 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2672 2673 if(ret) 2674 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2675 2676 return ret; 2677 } 2678 2679 static int smu_get_baco_capability(void *handle, bool *cap) 2680 { 2681 struct smu_context *smu = handle; 2682 2683 *cap = false; 2684 2685 if (!smu->pm_enabled) 2686 return 0; 2687 2688 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2689 *cap = smu->ppt_funcs->baco_is_support(smu); 2690 2691 return 0; 2692 } 2693 2694 static int smu_baco_set_state(void *handle, int state) 2695 { 2696 struct smu_context *smu = handle; 2697 int ret = 0; 2698 2699 if (!smu->pm_enabled) 2700 return -EOPNOTSUPP; 2701 2702 if (state == 0) { 2703 if (smu->ppt_funcs->baco_exit) 2704 ret = smu->ppt_funcs->baco_exit(smu); 2705 } else if (state == 1) { 2706 if (smu->ppt_funcs->baco_enter) 2707 ret = smu->ppt_funcs->baco_enter(smu); 2708 } else { 2709 return -EINVAL; 2710 } 2711 2712 if (ret) 2713 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 2714 (state)?"enter":"exit"); 2715 2716 return ret; 2717 } 2718 2719 bool smu_mode1_reset_is_support(struct smu_context *smu) 2720 { 2721 bool ret = false; 2722 2723 if (!smu->pm_enabled) 2724 return false; 2725 2726 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2727 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2728 2729 return ret; 2730 } 2731 2732 bool smu_mode2_reset_is_support(struct smu_context *smu) 2733 { 2734 bool ret = false; 2735 2736 if (!smu->pm_enabled) 2737 return false; 2738 2739 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 2740 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 2741 2742 return ret; 2743 } 2744 2745 int smu_mode1_reset(struct smu_context *smu) 2746 { 2747 int ret = 0; 2748 2749 if (!smu->pm_enabled) 2750 return -EOPNOTSUPP; 2751 2752 if (smu->ppt_funcs->mode1_reset) 2753 ret = smu->ppt_funcs->mode1_reset(smu); 2754 2755 return ret; 2756 } 2757 2758 static int smu_mode2_reset(void *handle) 2759 { 2760 struct smu_context *smu = handle; 2761 int ret = 0; 2762 2763 if (!smu->pm_enabled) 2764 return -EOPNOTSUPP; 2765 2766 if (smu->ppt_funcs->mode2_reset) 2767 ret = smu->ppt_funcs->mode2_reset(smu); 2768 2769 if (ret) 2770 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2771 2772 return ret; 2773 } 2774 2775 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 2776 struct pp_smu_nv_clock_table *max_clocks) 2777 { 2778 struct smu_context *smu = handle; 2779 int ret = 0; 2780 2781 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2782 return -EOPNOTSUPP; 2783 2784 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2785 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2786 2787 return ret; 2788 } 2789 2790 static int smu_get_uclk_dpm_states(void *handle, 2791 unsigned int *clock_values_in_khz, 2792 unsigned int *num_states) 2793 { 2794 struct smu_context *smu = handle; 2795 int ret = 0; 2796 2797 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2798 return -EOPNOTSUPP; 2799 2800 if (smu->ppt_funcs->get_uclk_dpm_states) 2801 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2802 2803 return ret; 2804 } 2805 2806 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 2807 { 2808 struct smu_context *smu = handle; 2809 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2810 2811 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2812 return -EOPNOTSUPP; 2813 2814 if (smu->ppt_funcs->get_current_power_state) 2815 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2816 2817 return pm_state; 2818 } 2819 2820 static int smu_get_dpm_clock_table(void *handle, 2821 struct dpm_clocks *clock_table) 2822 { 2823 struct smu_context *smu = handle; 2824 int ret = 0; 2825 2826 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2827 return -EOPNOTSUPP; 2828 2829 if (smu->ppt_funcs->get_dpm_clock_table) 2830 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 2831 2832 return ret; 2833 } 2834 2835 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 2836 { 2837 struct smu_context *smu = handle; 2838 2839 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2840 return -EOPNOTSUPP; 2841 2842 if (!smu->ppt_funcs->get_gpu_metrics) 2843 return -EOPNOTSUPP; 2844 2845 return smu->ppt_funcs->get_gpu_metrics(smu, table); 2846 } 2847 2848 static int smu_enable_mgpu_fan_boost(void *handle) 2849 { 2850 struct smu_context *smu = handle; 2851 int ret = 0; 2852 2853 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2854 return -EOPNOTSUPP; 2855 2856 if (smu->ppt_funcs->enable_mgpu_fan_boost) 2857 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 2858 2859 return ret; 2860 } 2861 2862 static int smu_gfx_state_change_set(void *handle, 2863 uint32_t state) 2864 { 2865 struct smu_context *smu = handle; 2866 int ret = 0; 2867 2868 if (smu->ppt_funcs->gfx_state_change_set) 2869 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 2870 2871 return ret; 2872 } 2873 2874 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 2875 { 2876 int ret = 0; 2877 2878 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 2879 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 2880 2881 return ret; 2882 } 2883 2884 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 2885 { 2886 int ret = -EOPNOTSUPP; 2887 2888 if (smu->ppt_funcs && 2889 smu->ppt_funcs->get_ecc_info) 2890 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 2891 2892 return ret; 2893 2894 } 2895 2896 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 2897 { 2898 struct smu_context *smu = handle; 2899 struct smu_table_context *smu_table = &smu->smu_table; 2900 struct smu_table *memory_pool = &smu_table->memory_pool; 2901 2902 if (!addr || !size) 2903 return -EINVAL; 2904 2905 *addr = NULL; 2906 *size = 0; 2907 if (memory_pool->bo) { 2908 *addr = memory_pool->cpu_addr; 2909 *size = memory_pool->size; 2910 } 2911 2912 return 0; 2913 } 2914 2915 static const struct amd_pm_funcs swsmu_pm_funcs = { 2916 /* export for sysfs */ 2917 .set_fan_control_mode = smu_set_fan_control_mode, 2918 .get_fan_control_mode = smu_get_fan_control_mode, 2919 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 2920 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 2921 .force_clock_level = smu_force_ppclk_levels, 2922 .print_clock_levels = smu_print_ppclk_levels, 2923 .emit_clock_levels = smu_emit_ppclk_levels, 2924 .force_performance_level = smu_force_performance_level, 2925 .read_sensor = smu_read_sensor, 2926 .get_performance_level = smu_get_performance_level, 2927 .get_current_power_state = smu_get_current_power_state, 2928 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 2929 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 2930 .get_pp_num_states = smu_get_power_num_states, 2931 .get_pp_table = smu_sys_get_pp_table, 2932 .set_pp_table = smu_sys_set_pp_table, 2933 .switch_power_profile = smu_switch_power_profile, 2934 /* export to amdgpu */ 2935 .dispatch_tasks = smu_handle_dpm_task, 2936 .load_firmware = smu_load_microcode, 2937 .set_powergating_by_smu = smu_dpm_set_power_gate, 2938 .set_power_limit = smu_set_power_limit, 2939 .get_power_limit = smu_get_power_limit, 2940 .get_power_profile_mode = smu_get_power_profile_mode, 2941 .set_power_profile_mode = smu_set_power_profile_mode, 2942 .odn_edit_dpm_table = smu_od_edit_dpm_table, 2943 .set_mp1_state = smu_set_mp1_state, 2944 .gfx_state_change_set = smu_gfx_state_change_set, 2945 /* export to DC */ 2946 .get_sclk = smu_get_sclk, 2947 .get_mclk = smu_get_mclk, 2948 .display_configuration_change = smu_display_configuration_change, 2949 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 2950 .display_clock_voltage_request = smu_display_clock_voltage_request, 2951 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 2952 .set_active_display_count = smu_set_display_count, 2953 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 2954 .get_asic_baco_capability = smu_get_baco_capability, 2955 .set_asic_baco_state = smu_baco_set_state, 2956 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 2957 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 2958 .asic_reset_mode_2 = smu_mode2_reset, 2959 .set_df_cstate = smu_set_df_cstate, 2960 .set_xgmi_pstate = smu_set_xgmi_pstate, 2961 .get_gpu_metrics = smu_sys_get_gpu_metrics, 2962 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 2963 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 2964 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 2965 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 2966 .get_dpm_clock_table = smu_get_dpm_clock_table, 2967 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 2968 }; 2969 2970 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 2971 uint64_t event_arg) 2972 { 2973 int ret = -EINVAL; 2974 2975 if (smu->ppt_funcs->wait_for_event) 2976 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 2977 2978 return ret; 2979 } 2980 2981 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 2982 { 2983 2984 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 2985 return -EOPNOTSUPP; 2986 2987 /* Confirm the buffer allocated is of correct size */ 2988 if (size != smu->stb_context.stb_buf_size) 2989 return -EINVAL; 2990 2991 /* 2992 * No need to lock smu mutex as we access STB directly through MMIO 2993 * and not going through SMU messaging route (for now at least). 2994 * For registers access rely on implementation internal locking. 2995 */ 2996 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 2997 } 2998 2999 #if defined(CONFIG_DEBUG_FS) 3000 3001 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3002 { 3003 struct amdgpu_device *adev = filp->f_inode->i_private; 3004 struct smu_context *smu = adev->powerplay.pp_handle; 3005 unsigned char *buf; 3006 int r; 3007 3008 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3009 if (!buf) 3010 return -ENOMEM; 3011 3012 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3013 if (r) 3014 goto out; 3015 3016 filp->private_data = buf; 3017 3018 return 0; 3019 3020 out: 3021 kvfree(buf); 3022 return r; 3023 } 3024 3025 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3026 loff_t *pos) 3027 { 3028 struct amdgpu_device *adev = filp->f_inode->i_private; 3029 struct smu_context *smu = adev->powerplay.pp_handle; 3030 3031 3032 if (!filp->private_data) 3033 return -EINVAL; 3034 3035 return simple_read_from_buffer(buf, 3036 size, 3037 pos, filp->private_data, 3038 smu->stb_context.stb_buf_size); 3039 } 3040 3041 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3042 { 3043 kvfree(filp->private_data); 3044 filp->private_data = NULL; 3045 3046 return 0; 3047 } 3048 3049 /* 3050 * We have to define not only read method but also 3051 * open and release because .read takes up to PAGE_SIZE 3052 * data each time so and so is invoked multiple times. 3053 * We allocate the STB buffer in .open and release it 3054 * in .release 3055 */ 3056 static const struct file_operations smu_stb_debugfs_fops = { 3057 .owner = THIS_MODULE, 3058 .open = smu_stb_debugfs_open, 3059 .read = smu_stb_debugfs_read, 3060 .release = smu_stb_debugfs_release, 3061 .llseek = default_llseek, 3062 }; 3063 3064 #endif 3065 3066 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3067 { 3068 #if defined(CONFIG_DEBUG_FS) 3069 3070 struct smu_context *smu = adev->powerplay.pp_handle; 3071 3072 if (!smu || (!smu->stb_context.stb_buf_size)) 3073 return; 3074 3075 debugfs_create_file_size("amdgpu_smu_stb_dump", 3076 S_IRUSR, 3077 adev_to_drm(adev)->primary->debugfs_root, 3078 adev, 3079 &smu_stb_debugfs_fops, 3080 smu->stb_context.stb_buf_size); 3081 #endif 3082 } 3083 3084 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3085 { 3086 int ret = 0; 3087 3088 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3089 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3090 3091 return ret; 3092 } 3093 3094 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3095 { 3096 int ret = 0; 3097 3098 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3099 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3100 3101 return ret; 3102 } 3103