1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "aldebaran_ppt.h" 38 #include "yellow_carp_ppt.h" 39 #include "cyan_skillfish_ppt.h" 40 #include "smu_v13_0_0_ppt.h" 41 #include "smu_v13_0_4_ppt.h" 42 #include "smu_v13_0_5_ppt.h" 43 #include "smu_v13_0_6_ppt.h" 44 #include "smu_v13_0_7_ppt.h" 45 #include "amd_pcie.h" 46 47 /* 48 * DO NOT use these for err/warn/info/debug messages. 49 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 50 * They are more MGPU friendly. 51 */ 52 #undef pr_err 53 #undef pr_warn 54 #undef pr_info 55 #undef pr_debug 56 57 static const struct amd_pm_funcs swsmu_pm_funcs; 58 static int smu_force_smuclk_levels(struct smu_context *smu, 59 enum smu_clk_type clk_type, 60 uint32_t mask); 61 static int smu_handle_task(struct smu_context *smu, 62 enum amd_dpm_forced_level level, 63 enum amd_pp_task task_id); 64 static int smu_reset(struct smu_context *smu); 65 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 66 static int smu_set_fan_control_mode(void *handle, u32 value); 67 static int smu_set_power_limit(void *handle, uint32_t limit); 68 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 69 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 70 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 71 72 static int smu_sys_get_pp_feature_mask(void *handle, 73 char *buf) 74 { 75 struct smu_context *smu = handle; 76 77 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 78 return -EOPNOTSUPP; 79 80 return smu_get_pp_feature_mask(smu, buf); 81 } 82 83 static int smu_sys_set_pp_feature_mask(void *handle, 84 uint64_t new_mask) 85 { 86 struct smu_context *smu = handle; 87 88 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 89 return -EOPNOTSUPP; 90 91 return smu_set_pp_feature_mask(smu, new_mask); 92 } 93 94 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 95 { 96 if (!smu->ppt_funcs->set_gfx_off_residency) 97 return -EINVAL; 98 99 return smu_set_gfx_off_residency(smu, value); 100 } 101 102 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 103 { 104 if (!smu->ppt_funcs->get_gfx_off_residency) 105 return -EINVAL; 106 107 return smu_get_gfx_off_residency(smu, value); 108 } 109 110 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 111 { 112 if (!smu->ppt_funcs->get_gfx_off_entrycount) 113 return -EINVAL; 114 115 return smu_get_gfx_off_entrycount(smu, value); 116 } 117 118 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 119 { 120 if (!smu->ppt_funcs->get_gfx_off_status) 121 return -EINVAL; 122 123 *value = smu_get_gfx_off_status(smu); 124 125 return 0; 126 } 127 128 int smu_set_soft_freq_range(struct smu_context *smu, 129 enum smu_clk_type clk_type, 130 uint32_t min, 131 uint32_t max) 132 { 133 int ret = 0; 134 135 if (smu->ppt_funcs->set_soft_freq_limited_range) 136 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 137 clk_type, 138 min, 139 max); 140 141 return ret; 142 } 143 144 int smu_get_dpm_freq_range(struct smu_context *smu, 145 enum smu_clk_type clk_type, 146 uint32_t *min, 147 uint32_t *max) 148 { 149 int ret = -ENOTSUPP; 150 151 if (!min && !max) 152 return -EINVAL; 153 154 if (smu->ppt_funcs->get_dpm_ultimate_freq) 155 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 156 clk_type, 157 min, 158 max); 159 160 return ret; 161 } 162 163 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 164 { 165 int ret = 0; 166 struct amdgpu_device *adev = smu->adev; 167 168 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 169 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 170 if (ret) 171 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 172 } 173 return ret; 174 } 175 176 static u32 smu_get_mclk(void *handle, bool low) 177 { 178 struct smu_context *smu = handle; 179 uint32_t clk_freq; 180 int ret = 0; 181 182 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 183 low ? &clk_freq : NULL, 184 !low ? &clk_freq : NULL); 185 if (ret) 186 return 0; 187 return clk_freq * 100; 188 } 189 190 static u32 smu_get_sclk(void *handle, bool low) 191 { 192 struct smu_context *smu = handle; 193 uint32_t clk_freq; 194 int ret = 0; 195 196 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 197 low ? &clk_freq : NULL, 198 !low ? &clk_freq : NULL); 199 if (ret) 200 return 0; 201 return clk_freq * 100; 202 } 203 204 static int smu_set_gfx_imu_enable(struct smu_context *smu) 205 { 206 struct amdgpu_device *adev = smu->adev; 207 208 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 209 return 0; 210 211 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 212 return 0; 213 214 return smu_set_gfx_power_up_by_imu(smu); 215 } 216 217 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 218 bool enable) 219 { 220 struct smu_power_context *smu_power = &smu->smu_power; 221 struct smu_power_gate *power_gate = &smu_power->power_gate; 222 int ret = 0; 223 224 if (!smu->ppt_funcs->dpm_set_vcn_enable) 225 return 0; 226 227 if (atomic_read(&power_gate->vcn_gated) ^ enable) 228 return 0; 229 230 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 231 if (!ret) 232 atomic_set(&power_gate->vcn_gated, !enable); 233 234 return ret; 235 } 236 237 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 238 bool enable) 239 { 240 struct smu_power_context *smu_power = &smu->smu_power; 241 struct smu_power_gate *power_gate = &smu_power->power_gate; 242 int ret = 0; 243 244 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 245 return 0; 246 247 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 248 return 0; 249 250 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 251 if (!ret) 252 atomic_set(&power_gate->jpeg_gated, !enable); 253 254 return ret; 255 } 256 257 /** 258 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 259 * 260 * @handle: smu_context pointer 261 * @block_type: the IP block to power gate/ungate 262 * @gate: to power gate if true, ungate otherwise 263 * 264 * This API uses no smu->mutex lock protection due to: 265 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 266 * This is guarded to be race condition free by the caller. 267 * 2. Or get called on user setting request of power_dpm_force_performance_level. 268 * Under this case, the smu->mutex lock protection is already enforced on 269 * the parent API smu_force_performance_level of the call path. 270 */ 271 static int smu_dpm_set_power_gate(void *handle, 272 uint32_t block_type, 273 bool gate) 274 { 275 struct smu_context *smu = handle; 276 int ret = 0; 277 278 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 279 dev_WARN(smu->adev->dev, 280 "SMU uninitialized but power %s requested for %u!\n", 281 gate ? "gate" : "ungate", block_type); 282 return -EOPNOTSUPP; 283 } 284 285 switch (block_type) { 286 /* 287 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 288 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 289 */ 290 case AMD_IP_BLOCK_TYPE_UVD: 291 case AMD_IP_BLOCK_TYPE_VCN: 292 ret = smu_dpm_set_vcn_enable(smu, !gate); 293 if (ret) 294 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 295 gate ? "gate" : "ungate"); 296 break; 297 case AMD_IP_BLOCK_TYPE_GFX: 298 ret = smu_gfx_off_control(smu, gate); 299 if (ret) 300 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 301 gate ? "enable" : "disable"); 302 break; 303 case AMD_IP_BLOCK_TYPE_SDMA: 304 ret = smu_powergate_sdma(smu, gate); 305 if (ret) 306 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 307 gate ? "gate" : "ungate"); 308 break; 309 case AMD_IP_BLOCK_TYPE_JPEG: 310 ret = smu_dpm_set_jpeg_enable(smu, !gate); 311 if (ret) 312 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 313 gate ? "gate" : "ungate"); 314 break; 315 default: 316 dev_err(smu->adev->dev, "Unsupported block type!\n"); 317 return -EINVAL; 318 } 319 320 return ret; 321 } 322 323 /** 324 * smu_set_user_clk_dependencies - set user profile clock dependencies 325 * 326 * @smu: smu_context pointer 327 * @clk: enum smu_clk_type type 328 * 329 * Enable/Disable the clock dependency for the @clk type. 330 */ 331 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 332 { 333 if (smu->adev->in_suspend) 334 return; 335 336 if (clk == SMU_MCLK) { 337 smu->user_dpm_profile.clk_dependency = 0; 338 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 339 } else if (clk == SMU_FCLK) { 340 /* MCLK takes precedence over FCLK */ 341 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 342 return; 343 344 smu->user_dpm_profile.clk_dependency = 0; 345 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 346 } else if (clk == SMU_SOCCLK) { 347 /* MCLK takes precedence over SOCCLK */ 348 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 349 return; 350 351 smu->user_dpm_profile.clk_dependency = 0; 352 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 353 } else 354 /* Add clk dependencies here, if any */ 355 return; 356 } 357 358 /** 359 * smu_restore_dpm_user_profile - reinstate user dpm profile 360 * 361 * @smu: smu_context pointer 362 * 363 * Restore the saved user power configurations include power limit, 364 * clock frequencies, fan control mode and fan speed. 365 */ 366 static void smu_restore_dpm_user_profile(struct smu_context *smu) 367 { 368 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 369 int ret = 0; 370 371 if (!smu->adev->in_suspend) 372 return; 373 374 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 375 return; 376 377 /* Enable restore flag */ 378 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 379 380 /* set the user dpm power limit */ 381 if (smu->user_dpm_profile.power_limit) { 382 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 383 if (ret) 384 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 385 } 386 387 /* set the user dpm clock configurations */ 388 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 389 enum smu_clk_type clk_type; 390 391 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 392 /* 393 * Iterate over smu clk type and force the saved user clk 394 * configs, skip if clock dependency is enabled 395 */ 396 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 397 smu->user_dpm_profile.clk_mask[clk_type]) { 398 ret = smu_force_smuclk_levels(smu, clk_type, 399 smu->user_dpm_profile.clk_mask[clk_type]); 400 if (ret) 401 dev_err(smu->adev->dev, 402 "Failed to set clock type = %d\n", clk_type); 403 } 404 } 405 } 406 407 /* set the user dpm fan configurations */ 408 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 409 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 410 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 411 if (ret != -EOPNOTSUPP) { 412 smu->user_dpm_profile.fan_speed_pwm = 0; 413 smu->user_dpm_profile.fan_speed_rpm = 0; 414 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 415 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 416 } 417 418 if (smu->user_dpm_profile.fan_speed_pwm) { 419 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 420 if (ret != -EOPNOTSUPP) 421 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 422 } 423 424 if (smu->user_dpm_profile.fan_speed_rpm) { 425 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 426 if (ret != -EOPNOTSUPP) 427 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 428 } 429 } 430 431 /* Restore user customized OD settings */ 432 if (smu->user_dpm_profile.user_od) { 433 if (smu->ppt_funcs->restore_user_od_settings) { 434 ret = smu->ppt_funcs->restore_user_od_settings(smu); 435 if (ret) 436 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 437 } 438 } 439 440 /* Disable restore flag */ 441 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 442 } 443 444 static int smu_get_power_num_states(void *handle, 445 struct pp_states_info *state_info) 446 { 447 if (!state_info) 448 return -EINVAL; 449 450 /* not support power state */ 451 memset(state_info, 0, sizeof(struct pp_states_info)); 452 state_info->nums = 1; 453 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 454 455 return 0; 456 } 457 458 bool is_support_sw_smu(struct amdgpu_device *adev) 459 { 460 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 461 if (adev->asic_type == CHIP_VEGA20) 462 return false; 463 464 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0)) 465 return true; 466 467 return false; 468 } 469 470 bool is_support_cclk_dpm(struct amdgpu_device *adev) 471 { 472 struct smu_context *smu = adev->powerplay.pp_handle; 473 474 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 475 return false; 476 477 return true; 478 } 479 480 481 static int smu_sys_get_pp_table(void *handle, 482 char **table) 483 { 484 struct smu_context *smu = handle; 485 struct smu_table_context *smu_table = &smu->smu_table; 486 487 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 488 return -EOPNOTSUPP; 489 490 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 491 return -EINVAL; 492 493 if (smu_table->hardcode_pptable) 494 *table = smu_table->hardcode_pptable; 495 else 496 *table = smu_table->power_play_table; 497 498 return smu_table->power_play_table_size; 499 } 500 501 static int smu_sys_set_pp_table(void *handle, 502 const char *buf, 503 size_t size) 504 { 505 struct smu_context *smu = handle; 506 struct smu_table_context *smu_table = &smu->smu_table; 507 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 508 int ret = 0; 509 510 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 511 return -EOPNOTSUPP; 512 513 if (header->usStructureSize != size) { 514 dev_err(smu->adev->dev, "pp table size not matched !\n"); 515 return -EIO; 516 } 517 518 if (!smu_table->hardcode_pptable) { 519 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 520 if (!smu_table->hardcode_pptable) 521 return -ENOMEM; 522 } 523 524 memcpy(smu_table->hardcode_pptable, buf, size); 525 smu_table->power_play_table = smu_table->hardcode_pptable; 526 smu_table->power_play_table_size = size; 527 528 /* 529 * Special hw_fini action(for Navi1x, the DPMs disablement will be 530 * skipped) may be needed for custom pptable uploading. 531 */ 532 smu->uploading_custom_pp_table = true; 533 534 ret = smu_reset(smu); 535 if (ret) 536 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 537 538 smu->uploading_custom_pp_table = false; 539 540 return ret; 541 } 542 543 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 544 { 545 struct smu_feature *feature = &smu->smu_feature; 546 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 547 int ret = 0; 548 549 /* 550 * With SCPM enabled, the allowed featuremasks setting(via 551 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 552 * That means there is no way to let PMFW knows the settings below. 553 * Thus, we just assume all the features are allowed under 554 * such scenario. 555 */ 556 if (smu->adev->scpm_enabled) { 557 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 558 return 0; 559 } 560 561 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 562 563 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 564 SMU_FEATURE_MAX/32); 565 if (ret) 566 return ret; 567 568 bitmap_or(feature->allowed, feature->allowed, 569 (unsigned long *)allowed_feature_mask, 570 feature->feature_num); 571 572 return ret; 573 } 574 575 static int smu_set_funcs(struct amdgpu_device *adev) 576 { 577 struct smu_context *smu = adev->powerplay.pp_handle; 578 579 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 580 smu->od_enabled = true; 581 582 switch (adev->ip_versions[MP1_HWIP][0]) { 583 case IP_VERSION(11, 0, 0): 584 case IP_VERSION(11, 0, 5): 585 case IP_VERSION(11, 0, 9): 586 navi10_set_ppt_funcs(smu); 587 break; 588 case IP_VERSION(11, 0, 7): 589 case IP_VERSION(11, 0, 11): 590 case IP_VERSION(11, 0, 12): 591 case IP_VERSION(11, 0, 13): 592 sienna_cichlid_set_ppt_funcs(smu); 593 break; 594 case IP_VERSION(12, 0, 0): 595 case IP_VERSION(12, 0, 1): 596 renoir_set_ppt_funcs(smu); 597 break; 598 case IP_VERSION(11, 5, 0): 599 vangogh_set_ppt_funcs(smu); 600 break; 601 case IP_VERSION(13, 0, 1): 602 case IP_VERSION(13, 0, 3): 603 case IP_VERSION(13, 0, 8): 604 yellow_carp_set_ppt_funcs(smu); 605 break; 606 case IP_VERSION(13, 0, 4): 607 case IP_VERSION(13, 0, 11): 608 smu_v13_0_4_set_ppt_funcs(smu); 609 break; 610 case IP_VERSION(13, 0, 5): 611 smu_v13_0_5_set_ppt_funcs(smu); 612 break; 613 case IP_VERSION(11, 0, 8): 614 cyan_skillfish_set_ppt_funcs(smu); 615 break; 616 case IP_VERSION(11, 0, 2): 617 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 618 arcturus_set_ppt_funcs(smu); 619 /* OD is not supported on Arcturus */ 620 smu->od_enabled =false; 621 break; 622 case IP_VERSION(13, 0, 2): 623 aldebaran_set_ppt_funcs(smu); 624 /* Enable pp_od_clk_voltage node */ 625 smu->od_enabled = true; 626 break; 627 case IP_VERSION(13, 0, 0): 628 case IP_VERSION(13, 0, 10): 629 smu_v13_0_0_set_ppt_funcs(smu); 630 break; 631 case IP_VERSION(13, 0, 6): 632 smu_v13_0_6_set_ppt_funcs(smu); 633 /* Enable pp_od_clk_voltage node */ 634 smu->od_enabled = true; 635 break; 636 case IP_VERSION(13, 0, 7): 637 smu_v13_0_7_set_ppt_funcs(smu); 638 break; 639 default: 640 return -EINVAL; 641 } 642 643 return 0; 644 } 645 646 static int smu_early_init(void *handle) 647 { 648 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 649 struct smu_context *smu; 650 int r; 651 652 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 653 if (!smu) 654 return -ENOMEM; 655 656 smu->adev = adev; 657 smu->pm_enabled = !!amdgpu_dpm; 658 smu->is_apu = false; 659 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 660 smu->smu_baco.platform_support = false; 661 smu->user_dpm_profile.fan_mode = -1; 662 663 mutex_init(&smu->message_lock); 664 665 adev->powerplay.pp_handle = smu; 666 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 667 668 r = smu_set_funcs(adev); 669 if (r) 670 return r; 671 return smu_init_microcode(smu); 672 } 673 674 static int smu_set_default_dpm_table(struct smu_context *smu) 675 { 676 struct smu_power_context *smu_power = &smu->smu_power; 677 struct smu_power_gate *power_gate = &smu_power->power_gate; 678 int vcn_gate, jpeg_gate; 679 int ret = 0; 680 681 if (!smu->ppt_funcs->set_default_dpm_table) 682 return 0; 683 684 vcn_gate = atomic_read(&power_gate->vcn_gated); 685 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 686 687 ret = smu_dpm_set_vcn_enable(smu, true); 688 if (ret) 689 return ret; 690 691 ret = smu_dpm_set_jpeg_enable(smu, true); 692 if (ret) 693 goto err_out; 694 695 ret = smu->ppt_funcs->set_default_dpm_table(smu); 696 if (ret) 697 dev_err(smu->adev->dev, 698 "Failed to setup default dpm clock tables!\n"); 699 700 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 701 err_out: 702 smu_dpm_set_vcn_enable(smu, !vcn_gate); 703 return ret; 704 } 705 706 static int smu_apply_default_config_table_settings(struct smu_context *smu) 707 { 708 struct amdgpu_device *adev = smu->adev; 709 int ret = 0; 710 711 ret = smu_get_default_config_table_settings(smu, 712 &adev->pm.config_table); 713 if (ret) 714 return ret; 715 716 return smu_set_config_table(smu, &adev->pm.config_table); 717 } 718 719 static int smu_late_init(void *handle) 720 { 721 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 722 struct smu_context *smu = adev->powerplay.pp_handle; 723 int ret = 0; 724 725 smu_set_fine_grain_gfx_freq_parameters(smu); 726 727 if (!smu->pm_enabled) 728 return 0; 729 730 ret = smu_post_init(smu); 731 if (ret) { 732 dev_err(adev->dev, "Failed to post smu init!\n"); 733 return ret; 734 } 735 736 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || 737 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) 738 return 0; 739 740 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 741 ret = smu_set_default_od_settings(smu); 742 if (ret) { 743 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 744 return ret; 745 } 746 } 747 748 ret = smu_populate_umd_state_clk(smu); 749 if (ret) { 750 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 751 return ret; 752 } 753 754 ret = smu_get_asic_power_limits(smu, 755 &smu->current_power_limit, 756 &smu->default_power_limit, 757 &smu->max_power_limit); 758 if (ret) { 759 dev_err(adev->dev, "Failed to get asic power limits!\n"); 760 return ret; 761 } 762 763 if (!amdgpu_sriov_vf(adev)) 764 smu_get_unique_id(smu); 765 766 smu_get_fan_parameters(smu); 767 768 smu_handle_task(smu, 769 smu->smu_dpm.dpm_level, 770 AMD_PP_TASK_COMPLETE_INIT); 771 772 ret = smu_apply_default_config_table_settings(smu); 773 if (ret && (ret != -EOPNOTSUPP)) { 774 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 775 return ret; 776 } 777 778 smu_restore_dpm_user_profile(smu); 779 780 return 0; 781 } 782 783 static int smu_init_fb_allocations(struct smu_context *smu) 784 { 785 struct amdgpu_device *adev = smu->adev; 786 struct smu_table_context *smu_table = &smu->smu_table; 787 struct smu_table *tables = smu_table->tables; 788 struct smu_table *driver_table = &(smu_table->driver_table); 789 uint32_t max_table_size = 0; 790 int ret, i; 791 792 /* VRAM allocation for tool table */ 793 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 794 ret = amdgpu_bo_create_kernel(adev, 795 tables[SMU_TABLE_PMSTATUSLOG].size, 796 tables[SMU_TABLE_PMSTATUSLOG].align, 797 tables[SMU_TABLE_PMSTATUSLOG].domain, 798 &tables[SMU_TABLE_PMSTATUSLOG].bo, 799 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 800 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 801 if (ret) { 802 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 803 return ret; 804 } 805 } 806 807 /* VRAM allocation for driver table */ 808 for (i = 0; i < SMU_TABLE_COUNT; i++) { 809 if (tables[i].size == 0) 810 continue; 811 812 if (i == SMU_TABLE_PMSTATUSLOG) 813 continue; 814 815 if (max_table_size < tables[i].size) 816 max_table_size = tables[i].size; 817 } 818 819 driver_table->size = max_table_size; 820 driver_table->align = PAGE_SIZE; 821 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 822 823 ret = amdgpu_bo_create_kernel(adev, 824 driver_table->size, 825 driver_table->align, 826 driver_table->domain, 827 &driver_table->bo, 828 &driver_table->mc_address, 829 &driver_table->cpu_addr); 830 if (ret) { 831 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 832 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 833 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 834 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 835 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 836 } 837 838 return ret; 839 } 840 841 static int smu_fini_fb_allocations(struct smu_context *smu) 842 { 843 struct smu_table_context *smu_table = &smu->smu_table; 844 struct smu_table *tables = smu_table->tables; 845 struct smu_table *driver_table = &(smu_table->driver_table); 846 847 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 848 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 849 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 850 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 851 852 amdgpu_bo_free_kernel(&driver_table->bo, 853 &driver_table->mc_address, 854 &driver_table->cpu_addr); 855 856 return 0; 857 } 858 859 /** 860 * smu_alloc_memory_pool - allocate memory pool in the system memory 861 * 862 * @smu: amdgpu_device pointer 863 * 864 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 865 * and DramLogSetDramAddr can notify it changed. 866 * 867 * Returns 0 on success, error on failure. 868 */ 869 static int smu_alloc_memory_pool(struct smu_context *smu) 870 { 871 struct amdgpu_device *adev = smu->adev; 872 struct smu_table_context *smu_table = &smu->smu_table; 873 struct smu_table *memory_pool = &smu_table->memory_pool; 874 uint64_t pool_size = smu->pool_size; 875 int ret = 0; 876 877 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 878 return ret; 879 880 memory_pool->size = pool_size; 881 memory_pool->align = PAGE_SIZE; 882 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 883 884 switch (pool_size) { 885 case SMU_MEMORY_POOL_SIZE_256_MB: 886 case SMU_MEMORY_POOL_SIZE_512_MB: 887 case SMU_MEMORY_POOL_SIZE_1_GB: 888 case SMU_MEMORY_POOL_SIZE_2_GB: 889 ret = amdgpu_bo_create_kernel(adev, 890 memory_pool->size, 891 memory_pool->align, 892 memory_pool->domain, 893 &memory_pool->bo, 894 &memory_pool->mc_address, 895 &memory_pool->cpu_addr); 896 if (ret) 897 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 898 break; 899 default: 900 break; 901 } 902 903 return ret; 904 } 905 906 static int smu_free_memory_pool(struct smu_context *smu) 907 { 908 struct smu_table_context *smu_table = &smu->smu_table; 909 struct smu_table *memory_pool = &smu_table->memory_pool; 910 911 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 912 return 0; 913 914 amdgpu_bo_free_kernel(&memory_pool->bo, 915 &memory_pool->mc_address, 916 &memory_pool->cpu_addr); 917 918 memset(memory_pool, 0, sizeof(struct smu_table)); 919 920 return 0; 921 } 922 923 static int smu_alloc_dummy_read_table(struct smu_context *smu) 924 { 925 struct smu_table_context *smu_table = &smu->smu_table; 926 struct smu_table *dummy_read_1_table = 927 &smu_table->dummy_read_1_table; 928 struct amdgpu_device *adev = smu->adev; 929 int ret = 0; 930 931 if (!dummy_read_1_table->size) 932 return 0; 933 934 ret = amdgpu_bo_create_kernel(adev, 935 dummy_read_1_table->size, 936 dummy_read_1_table->align, 937 dummy_read_1_table->domain, 938 &dummy_read_1_table->bo, 939 &dummy_read_1_table->mc_address, 940 &dummy_read_1_table->cpu_addr); 941 if (ret) 942 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 943 944 return ret; 945 } 946 947 static void smu_free_dummy_read_table(struct smu_context *smu) 948 { 949 struct smu_table_context *smu_table = &smu->smu_table; 950 struct smu_table *dummy_read_1_table = 951 &smu_table->dummy_read_1_table; 952 953 954 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 955 &dummy_read_1_table->mc_address, 956 &dummy_read_1_table->cpu_addr); 957 958 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 959 } 960 961 static int smu_smc_table_sw_init(struct smu_context *smu) 962 { 963 int ret; 964 965 /** 966 * Create smu_table structure, and init smc tables such as 967 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 968 */ 969 ret = smu_init_smc_tables(smu); 970 if (ret) { 971 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 972 return ret; 973 } 974 975 /** 976 * Create smu_power_context structure, and allocate smu_dpm_context and 977 * context size to fill the smu_power_context data. 978 */ 979 ret = smu_init_power(smu); 980 if (ret) { 981 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 982 return ret; 983 } 984 985 /* 986 * allocate vram bos to store smc table contents. 987 */ 988 ret = smu_init_fb_allocations(smu); 989 if (ret) 990 return ret; 991 992 ret = smu_alloc_memory_pool(smu); 993 if (ret) 994 return ret; 995 996 ret = smu_alloc_dummy_read_table(smu); 997 if (ret) 998 return ret; 999 1000 ret = smu_i2c_init(smu); 1001 if (ret) 1002 return ret; 1003 1004 return 0; 1005 } 1006 1007 static int smu_smc_table_sw_fini(struct smu_context *smu) 1008 { 1009 int ret; 1010 1011 smu_i2c_fini(smu); 1012 1013 smu_free_dummy_read_table(smu); 1014 1015 ret = smu_free_memory_pool(smu); 1016 if (ret) 1017 return ret; 1018 1019 ret = smu_fini_fb_allocations(smu); 1020 if (ret) 1021 return ret; 1022 1023 ret = smu_fini_power(smu); 1024 if (ret) { 1025 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1026 return ret; 1027 } 1028 1029 ret = smu_fini_smc_tables(smu); 1030 if (ret) { 1031 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1032 return ret; 1033 } 1034 1035 return 0; 1036 } 1037 1038 static void smu_throttling_logging_work_fn(struct work_struct *work) 1039 { 1040 struct smu_context *smu = container_of(work, struct smu_context, 1041 throttling_logging_work); 1042 1043 smu_log_thermal_throttling(smu); 1044 } 1045 1046 static void smu_interrupt_work_fn(struct work_struct *work) 1047 { 1048 struct smu_context *smu = container_of(work, struct smu_context, 1049 interrupt_work); 1050 1051 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1052 smu->ppt_funcs->interrupt_work(smu); 1053 } 1054 1055 static int smu_sw_init(void *handle) 1056 { 1057 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1058 struct smu_context *smu = adev->powerplay.pp_handle; 1059 int ret; 1060 1061 smu->pool_size = adev->pm.smu_prv_buffer_size; 1062 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1063 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1064 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1065 1066 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1067 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1068 atomic64_set(&smu->throttle_int_counter, 0); 1069 smu->watermarks_bitmap = 0; 1070 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1071 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1072 1073 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1074 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1075 1076 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1077 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1078 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1079 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1080 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1081 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1082 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1083 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1084 1085 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1086 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1087 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1088 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1089 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1090 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1091 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1092 smu->display_config = &adev->pm.pm_display_cfg; 1093 1094 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1095 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1096 1097 ret = smu_smc_table_sw_init(smu); 1098 if (ret) { 1099 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1100 return ret; 1101 } 1102 1103 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1104 ret = smu_get_vbios_bootup_values(smu); 1105 if (ret) { 1106 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1107 return ret; 1108 } 1109 1110 ret = smu_init_pptable_microcode(smu); 1111 if (ret) { 1112 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1113 return ret; 1114 } 1115 1116 ret = smu_register_irq_handler(smu); 1117 if (ret) { 1118 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1119 return ret; 1120 } 1121 1122 /* If there is no way to query fan control mode, fan control is not supported */ 1123 if (!smu->ppt_funcs->get_fan_control_mode) 1124 smu->adev->pm.no_fan = true; 1125 1126 return 0; 1127 } 1128 1129 static int smu_sw_fini(void *handle) 1130 { 1131 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1132 struct smu_context *smu = adev->powerplay.pp_handle; 1133 int ret; 1134 1135 ret = smu_smc_table_sw_fini(smu); 1136 if (ret) { 1137 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1138 return ret; 1139 } 1140 1141 smu_fini_microcode(smu); 1142 1143 return 0; 1144 } 1145 1146 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1147 { 1148 struct amdgpu_device *adev = smu->adev; 1149 struct smu_temperature_range *range = 1150 &smu->thermal_range; 1151 int ret = 0; 1152 1153 if (!smu->ppt_funcs->get_thermal_temperature_range) 1154 return 0; 1155 1156 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1157 if (ret) 1158 return ret; 1159 1160 adev->pm.dpm.thermal.min_temp = range->min; 1161 adev->pm.dpm.thermal.max_temp = range->max; 1162 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1163 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1164 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1165 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1166 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1167 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1168 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1169 1170 return ret; 1171 } 1172 1173 static int smu_smc_hw_setup(struct smu_context *smu) 1174 { 1175 struct smu_feature *feature = &smu->smu_feature; 1176 struct amdgpu_device *adev = smu->adev; 1177 uint32_t pcie_gen = 0, pcie_width = 0; 1178 uint64_t features_supported; 1179 int ret = 0; 1180 1181 switch (adev->ip_versions[MP1_HWIP][0]) { 1182 case IP_VERSION(11, 0, 7): 1183 case IP_VERSION(11, 0, 11): 1184 case IP_VERSION(11, 5, 0): 1185 case IP_VERSION(11, 0, 12): 1186 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1187 dev_info(adev->dev, "dpm has been enabled\n"); 1188 ret = smu_system_features_control(smu, true); 1189 if (ret) 1190 dev_err(adev->dev, "Failed system features control!\n"); 1191 return ret; 1192 } 1193 break; 1194 default: 1195 break; 1196 } 1197 1198 ret = smu_init_display_count(smu, 0); 1199 if (ret) { 1200 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1201 return ret; 1202 } 1203 1204 ret = smu_set_driver_table_location(smu); 1205 if (ret) { 1206 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1207 return ret; 1208 } 1209 1210 /* 1211 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1212 */ 1213 ret = smu_set_tool_table_location(smu); 1214 if (ret) { 1215 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1216 return ret; 1217 } 1218 1219 /* 1220 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1221 * pool location. 1222 */ 1223 ret = smu_notify_memory_pool_location(smu); 1224 if (ret) { 1225 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1226 return ret; 1227 } 1228 1229 /* 1230 * It is assumed the pptable used before runpm is same as 1231 * the one used afterwards. Thus, we can reuse the stored 1232 * copy and do not need to resetup the pptable again. 1233 */ 1234 if (!adev->in_runpm) { 1235 ret = smu_setup_pptable(smu); 1236 if (ret) { 1237 dev_err(adev->dev, "Failed to setup pptable!\n"); 1238 return ret; 1239 } 1240 } 1241 1242 /* smu_dump_pptable(smu); */ 1243 1244 /* 1245 * With SCPM enabled, PSP is responsible for the PPTable transferring 1246 * (to SMU). Driver involvement is not needed and permitted. 1247 */ 1248 if (!adev->scpm_enabled) { 1249 /* 1250 * Copy pptable bo in the vram to smc with SMU MSGs such as 1251 * SetDriverDramAddr and TransferTableDram2Smu. 1252 */ 1253 ret = smu_write_pptable(smu); 1254 if (ret) { 1255 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1256 return ret; 1257 } 1258 } 1259 1260 /* issue Run*Btc msg */ 1261 ret = smu_run_btc(smu); 1262 if (ret) 1263 return ret; 1264 1265 /* 1266 * With SCPM enabled, these actions(and relevant messages) are 1267 * not needed and permitted. 1268 */ 1269 if (!adev->scpm_enabled) { 1270 ret = smu_feature_set_allowed_mask(smu); 1271 if (ret) { 1272 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1273 return ret; 1274 } 1275 } 1276 1277 ret = smu_system_features_control(smu, true); 1278 if (ret) { 1279 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1280 return ret; 1281 } 1282 1283 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1284 if (ret) { 1285 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1286 return ret; 1287 } 1288 bitmap_copy(feature->supported, 1289 (unsigned long *)&features_supported, 1290 feature->feature_num); 1291 1292 if (!smu_is_dpm_running(smu)) 1293 dev_info(adev->dev, "dpm has been disabled\n"); 1294 1295 /* 1296 * Set initialized values (get from vbios) to dpm tables context such as 1297 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1298 * type of clks. 1299 */ 1300 ret = smu_set_default_dpm_table(smu); 1301 if (ret) { 1302 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1303 return ret; 1304 } 1305 1306 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1307 pcie_gen = 3; 1308 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1309 pcie_gen = 2; 1310 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1311 pcie_gen = 1; 1312 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1313 pcie_gen = 0; 1314 1315 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1316 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1317 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1318 */ 1319 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1320 pcie_width = 6; 1321 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1322 pcie_width = 5; 1323 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1324 pcie_width = 4; 1325 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1326 pcie_width = 3; 1327 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1328 pcie_width = 2; 1329 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1330 pcie_width = 1; 1331 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1332 if (ret) { 1333 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1334 return ret; 1335 } 1336 1337 ret = smu_get_thermal_temperature_range(smu); 1338 if (ret) { 1339 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1340 return ret; 1341 } 1342 1343 ret = smu_enable_thermal_alert(smu); 1344 if (ret) { 1345 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1346 return ret; 1347 } 1348 1349 ret = smu_notify_display_change(smu); 1350 if (ret) { 1351 dev_err(adev->dev, "Failed to notify display change!\n"); 1352 return ret; 1353 } 1354 1355 /* 1356 * Set min deep sleep dce fclk with bootup value from vbios via 1357 * SetMinDeepSleepDcefclk MSG. 1358 */ 1359 ret = smu_set_min_dcef_deep_sleep(smu, 1360 smu->smu_table.boot_values.dcefclk / 100); 1361 1362 return ret; 1363 } 1364 1365 static int smu_start_smc_engine(struct smu_context *smu) 1366 { 1367 struct amdgpu_device *adev = smu->adev; 1368 int ret = 0; 1369 1370 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1371 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) { 1372 if (smu->ppt_funcs->load_microcode) { 1373 ret = smu->ppt_funcs->load_microcode(smu); 1374 if (ret) 1375 return ret; 1376 } 1377 } 1378 } 1379 1380 if (smu->ppt_funcs->check_fw_status) { 1381 ret = smu->ppt_funcs->check_fw_status(smu); 1382 if (ret) { 1383 dev_err(adev->dev, "SMC is not ready\n"); 1384 return ret; 1385 } 1386 } 1387 1388 /* 1389 * Send msg GetDriverIfVersion to check if the return value is equal 1390 * with DRIVER_IF_VERSION of smc header. 1391 */ 1392 ret = smu_check_fw_version(smu); 1393 if (ret) 1394 return ret; 1395 1396 return ret; 1397 } 1398 1399 static int smu_hw_init(void *handle) 1400 { 1401 int ret; 1402 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1403 struct smu_context *smu = adev->powerplay.pp_handle; 1404 1405 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1406 smu->pm_enabled = false; 1407 return 0; 1408 } 1409 1410 ret = smu_start_smc_engine(smu); 1411 if (ret) { 1412 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1413 return ret; 1414 } 1415 1416 if (smu->is_apu) { 1417 ret = smu_set_gfx_imu_enable(smu); 1418 if (ret) 1419 return ret; 1420 smu_dpm_set_vcn_enable(smu, true); 1421 smu_dpm_set_jpeg_enable(smu, true); 1422 smu_set_gfx_cgpg(smu, true); 1423 } 1424 1425 if (!smu->pm_enabled) 1426 return 0; 1427 1428 ret = smu_get_driver_allowed_feature_mask(smu); 1429 if (ret) 1430 return ret; 1431 1432 ret = smu_smc_hw_setup(smu); 1433 if (ret) { 1434 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1435 return ret; 1436 } 1437 1438 /* 1439 * Move maximum sustainable clock retrieving here considering 1440 * 1. It is not needed on resume(from S3). 1441 * 2. DAL settings come between .hw_init and .late_init of SMU. 1442 * And DAL needs to know the maximum sustainable clocks. Thus 1443 * it cannot be put in .late_init(). 1444 */ 1445 ret = smu_init_max_sustainable_clocks(smu); 1446 if (ret) { 1447 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1448 return ret; 1449 } 1450 1451 adev->pm.dpm_enabled = true; 1452 1453 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1454 1455 return 0; 1456 } 1457 1458 static int smu_disable_dpms(struct smu_context *smu) 1459 { 1460 struct amdgpu_device *adev = smu->adev; 1461 int ret = 0; 1462 bool use_baco = !smu->is_apu && 1463 ((amdgpu_in_reset(adev) && 1464 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1465 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1466 1467 /* 1468 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1469 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1470 */ 1471 switch (adev->ip_versions[MP1_HWIP][0]) { 1472 case IP_VERSION(13, 0, 0): 1473 case IP_VERSION(13, 0, 7): 1474 case IP_VERSION(13, 0, 10): 1475 return 0; 1476 default: 1477 break; 1478 } 1479 1480 /* 1481 * For custom pptable uploading, skip the DPM features 1482 * disable process on Navi1x ASICs. 1483 * - As the gfx related features are under control of 1484 * RLC on those ASICs. RLC reinitialization will be 1485 * needed to reenable them. That will cost much more 1486 * efforts. 1487 * 1488 * - SMU firmware can handle the DPM reenablement 1489 * properly. 1490 */ 1491 if (smu->uploading_custom_pp_table) { 1492 switch (adev->ip_versions[MP1_HWIP][0]) { 1493 case IP_VERSION(11, 0, 0): 1494 case IP_VERSION(11, 0, 5): 1495 case IP_VERSION(11, 0, 9): 1496 case IP_VERSION(11, 0, 7): 1497 case IP_VERSION(11, 0, 11): 1498 case IP_VERSION(11, 5, 0): 1499 case IP_VERSION(11, 0, 12): 1500 case IP_VERSION(11, 0, 13): 1501 return 0; 1502 default: 1503 break; 1504 } 1505 } 1506 1507 /* 1508 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1509 * on BACO in. Driver involvement is unnecessary. 1510 */ 1511 if (use_baco) { 1512 switch (adev->ip_versions[MP1_HWIP][0]) { 1513 case IP_VERSION(11, 0, 7): 1514 case IP_VERSION(11, 0, 0): 1515 case IP_VERSION(11, 0, 5): 1516 case IP_VERSION(11, 0, 9): 1517 case IP_VERSION(13, 0, 7): 1518 return 0; 1519 default: 1520 break; 1521 } 1522 } 1523 1524 /* 1525 * For SMU 13.0.4/11, PMFW will handle the features disablement properly 1526 * for gpu reset case. Driver involvement is unnecessary. 1527 */ 1528 if (amdgpu_in_reset(adev)) { 1529 switch (adev->ip_versions[MP1_HWIP][0]) { 1530 case IP_VERSION(13, 0, 4): 1531 case IP_VERSION(13, 0, 11): 1532 return 0; 1533 default: 1534 break; 1535 } 1536 } 1537 1538 /* 1539 * For gpu reset, runpm and hibernation through BACO, 1540 * BACO feature has to be kept enabled. 1541 */ 1542 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1543 ret = smu_disable_all_features_with_exception(smu, 1544 SMU_FEATURE_BACO_BIT); 1545 if (ret) 1546 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1547 } else { 1548 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1549 if (!adev->scpm_enabled) { 1550 ret = smu_system_features_control(smu, false); 1551 if (ret) 1552 dev_err(adev->dev, "Failed to disable smu features.\n"); 1553 } 1554 } 1555 1556 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) && 1557 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1558 adev->gfx.rlc.funcs->stop(adev); 1559 1560 return ret; 1561 } 1562 1563 static int smu_smc_hw_cleanup(struct smu_context *smu) 1564 { 1565 struct amdgpu_device *adev = smu->adev; 1566 int ret = 0; 1567 1568 cancel_work_sync(&smu->throttling_logging_work); 1569 cancel_work_sync(&smu->interrupt_work); 1570 1571 ret = smu_disable_thermal_alert(smu); 1572 if (ret) { 1573 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1574 return ret; 1575 } 1576 1577 ret = smu_disable_dpms(smu); 1578 if (ret) { 1579 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1580 return ret; 1581 } 1582 1583 return 0; 1584 } 1585 1586 static int smu_hw_fini(void *handle) 1587 { 1588 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1589 struct smu_context *smu = adev->powerplay.pp_handle; 1590 1591 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1592 return 0; 1593 1594 smu_dpm_set_vcn_enable(smu, false); 1595 smu_dpm_set_jpeg_enable(smu, false); 1596 1597 adev->vcn.cur_state = AMD_PG_STATE_GATE; 1598 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 1599 1600 if (!smu->pm_enabled) 1601 return 0; 1602 1603 adev->pm.dpm_enabled = false; 1604 1605 return smu_smc_hw_cleanup(smu); 1606 } 1607 1608 static void smu_late_fini(void *handle) 1609 { 1610 struct amdgpu_device *adev = handle; 1611 struct smu_context *smu = adev->powerplay.pp_handle; 1612 1613 kfree(smu); 1614 } 1615 1616 static int smu_reset(struct smu_context *smu) 1617 { 1618 struct amdgpu_device *adev = smu->adev; 1619 int ret; 1620 1621 ret = smu_hw_fini(adev); 1622 if (ret) 1623 return ret; 1624 1625 ret = smu_hw_init(adev); 1626 if (ret) 1627 return ret; 1628 1629 ret = smu_late_init(adev); 1630 if (ret) 1631 return ret; 1632 1633 return 0; 1634 } 1635 1636 static int smu_suspend(void *handle) 1637 { 1638 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1639 struct smu_context *smu = adev->powerplay.pp_handle; 1640 int ret; 1641 uint64_t count; 1642 1643 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1644 return 0; 1645 1646 if (!smu->pm_enabled) 1647 return 0; 1648 1649 adev->pm.dpm_enabled = false; 1650 1651 ret = smu_smc_hw_cleanup(smu); 1652 if (ret) 1653 return ret; 1654 1655 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1656 1657 smu_set_gfx_cgpg(smu, false); 1658 1659 /* 1660 * pwfw resets entrycount when device is suspended, so we save the 1661 * last value to be used when we resume to keep it consistent 1662 */ 1663 ret = smu_get_entrycount_gfxoff(smu, &count); 1664 if (!ret) 1665 adev->gfx.gfx_off_entrycount = count; 1666 1667 return 0; 1668 } 1669 1670 static int smu_resume(void *handle) 1671 { 1672 int ret; 1673 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1674 struct smu_context *smu = adev->powerplay.pp_handle; 1675 1676 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1677 return 0; 1678 1679 if (!smu->pm_enabled) 1680 return 0; 1681 1682 dev_info(adev->dev, "SMU is resuming...\n"); 1683 1684 ret = smu_start_smc_engine(smu); 1685 if (ret) { 1686 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1687 return ret; 1688 } 1689 1690 ret = smu_smc_hw_setup(smu); 1691 if (ret) { 1692 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1693 return ret; 1694 } 1695 1696 ret = smu_set_gfx_imu_enable(smu); 1697 if (ret) 1698 return ret; 1699 1700 smu_set_gfx_cgpg(smu, true); 1701 1702 smu->disable_uclk_switch = 0; 1703 1704 adev->pm.dpm_enabled = true; 1705 1706 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1707 1708 return 0; 1709 } 1710 1711 static int smu_display_configuration_change(void *handle, 1712 const struct amd_pp_display_configuration *display_config) 1713 { 1714 struct smu_context *smu = handle; 1715 int index = 0; 1716 int num_of_active_display = 0; 1717 1718 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1719 return -EOPNOTSUPP; 1720 1721 if (!display_config) 1722 return -EINVAL; 1723 1724 smu_set_min_dcef_deep_sleep(smu, 1725 display_config->min_dcef_deep_sleep_set_clk / 100); 1726 1727 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1728 if (display_config->displays[index].controller_id != 0) 1729 num_of_active_display++; 1730 } 1731 1732 return 0; 1733 } 1734 1735 static int smu_set_clockgating_state(void *handle, 1736 enum amd_clockgating_state state) 1737 { 1738 return 0; 1739 } 1740 1741 static int smu_set_powergating_state(void *handle, 1742 enum amd_powergating_state state) 1743 { 1744 return 0; 1745 } 1746 1747 static int smu_enable_umd_pstate(void *handle, 1748 enum amd_dpm_forced_level *level) 1749 { 1750 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1751 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1752 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1753 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1754 1755 struct smu_context *smu = (struct smu_context*)(handle); 1756 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1757 1758 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1759 return -EINVAL; 1760 1761 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1762 /* enter umd pstate, save current level, disable gfx cg*/ 1763 if (*level & profile_mode_mask) { 1764 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1765 smu_gpo_control(smu, false); 1766 smu_gfx_ulv_control(smu, false); 1767 smu_deep_sleep_control(smu, false); 1768 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1769 } 1770 } else { 1771 /* exit umd pstate, restore level, enable gfx cg*/ 1772 if (!(*level & profile_mode_mask)) { 1773 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1774 *level = smu_dpm_ctx->saved_dpm_level; 1775 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1776 smu_deep_sleep_control(smu, true); 1777 smu_gfx_ulv_control(smu, true); 1778 smu_gpo_control(smu, true); 1779 } 1780 } 1781 1782 return 0; 1783 } 1784 1785 static int smu_bump_power_profile_mode(struct smu_context *smu, 1786 long *param, 1787 uint32_t param_size) 1788 { 1789 int ret = 0; 1790 1791 if (smu->ppt_funcs->set_power_profile_mode) 1792 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1793 1794 return ret; 1795 } 1796 1797 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1798 enum amd_dpm_forced_level level, 1799 bool skip_display_settings) 1800 { 1801 int ret = 0; 1802 int index = 0; 1803 long workload; 1804 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1805 1806 if (!skip_display_settings) { 1807 ret = smu_display_config_changed(smu); 1808 if (ret) { 1809 dev_err(smu->adev->dev, "Failed to change display config!"); 1810 return ret; 1811 } 1812 } 1813 1814 ret = smu_apply_clocks_adjust_rules(smu); 1815 if (ret) { 1816 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1817 return ret; 1818 } 1819 1820 if (!skip_display_settings) { 1821 ret = smu_notify_smc_display_config(smu); 1822 if (ret) { 1823 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1824 return ret; 1825 } 1826 } 1827 1828 if (smu_dpm_ctx->dpm_level != level) { 1829 ret = smu_asic_set_performance_level(smu, level); 1830 if (ret) { 1831 dev_err(smu->adev->dev, "Failed to set performance level!"); 1832 return ret; 1833 } 1834 1835 /* update the saved copy */ 1836 smu_dpm_ctx->dpm_level = level; 1837 } 1838 1839 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1840 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1841 index = fls(smu->workload_mask); 1842 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1843 workload = smu->workload_setting[index]; 1844 1845 if (smu->power_profile_mode != workload) 1846 smu_bump_power_profile_mode(smu, &workload, 0); 1847 } 1848 1849 return ret; 1850 } 1851 1852 static int smu_handle_task(struct smu_context *smu, 1853 enum amd_dpm_forced_level level, 1854 enum amd_pp_task task_id) 1855 { 1856 int ret = 0; 1857 1858 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1859 return -EOPNOTSUPP; 1860 1861 switch (task_id) { 1862 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1863 ret = smu_pre_display_config_changed(smu); 1864 if (ret) 1865 return ret; 1866 ret = smu_adjust_power_state_dynamic(smu, level, false); 1867 break; 1868 case AMD_PP_TASK_COMPLETE_INIT: 1869 case AMD_PP_TASK_READJUST_POWER_STATE: 1870 ret = smu_adjust_power_state_dynamic(smu, level, true); 1871 break; 1872 default: 1873 break; 1874 } 1875 1876 return ret; 1877 } 1878 1879 static int smu_handle_dpm_task(void *handle, 1880 enum amd_pp_task task_id, 1881 enum amd_pm_state_type *user_state) 1882 { 1883 struct smu_context *smu = handle; 1884 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1885 1886 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 1887 1888 } 1889 1890 static int smu_switch_power_profile(void *handle, 1891 enum PP_SMC_POWER_PROFILE type, 1892 bool en) 1893 { 1894 struct smu_context *smu = handle; 1895 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1896 long workload; 1897 uint32_t index; 1898 1899 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1900 return -EOPNOTSUPP; 1901 1902 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1903 return -EINVAL; 1904 1905 if (!en) { 1906 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1907 index = fls(smu->workload_mask); 1908 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1909 workload = smu->workload_setting[index]; 1910 } else { 1911 smu->workload_mask |= (1 << smu->workload_prority[type]); 1912 index = fls(smu->workload_mask); 1913 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1914 workload = smu->workload_setting[index]; 1915 } 1916 1917 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1918 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1919 smu_bump_power_profile_mode(smu, &workload, 0); 1920 1921 return 0; 1922 } 1923 1924 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 1925 { 1926 struct smu_context *smu = handle; 1927 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1928 1929 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1930 return -EOPNOTSUPP; 1931 1932 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1933 return -EINVAL; 1934 1935 return smu_dpm_ctx->dpm_level; 1936 } 1937 1938 static int smu_force_performance_level(void *handle, 1939 enum amd_dpm_forced_level level) 1940 { 1941 struct smu_context *smu = handle; 1942 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1943 int ret = 0; 1944 1945 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1946 return -EOPNOTSUPP; 1947 1948 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1949 return -EINVAL; 1950 1951 ret = smu_enable_umd_pstate(smu, &level); 1952 if (ret) 1953 return ret; 1954 1955 ret = smu_handle_task(smu, level, 1956 AMD_PP_TASK_READJUST_POWER_STATE); 1957 1958 /* reset user dpm clock state */ 1959 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1960 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 1961 smu->user_dpm_profile.clk_dependency = 0; 1962 } 1963 1964 return ret; 1965 } 1966 1967 static int smu_set_display_count(void *handle, uint32_t count) 1968 { 1969 struct smu_context *smu = handle; 1970 1971 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1972 return -EOPNOTSUPP; 1973 1974 return smu_init_display_count(smu, count); 1975 } 1976 1977 static int smu_force_smuclk_levels(struct smu_context *smu, 1978 enum smu_clk_type clk_type, 1979 uint32_t mask) 1980 { 1981 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1982 int ret = 0; 1983 1984 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1985 return -EOPNOTSUPP; 1986 1987 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1988 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1989 return -EINVAL; 1990 } 1991 1992 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 1993 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1994 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 1995 smu->user_dpm_profile.clk_mask[clk_type] = mask; 1996 smu_set_user_clk_dependencies(smu, clk_type); 1997 } 1998 } 1999 2000 return ret; 2001 } 2002 2003 static int smu_force_ppclk_levels(void *handle, 2004 enum pp_clock_type type, 2005 uint32_t mask) 2006 { 2007 struct smu_context *smu = handle; 2008 enum smu_clk_type clk_type; 2009 2010 switch (type) { 2011 case PP_SCLK: 2012 clk_type = SMU_SCLK; break; 2013 case PP_MCLK: 2014 clk_type = SMU_MCLK; break; 2015 case PP_PCIE: 2016 clk_type = SMU_PCIE; break; 2017 case PP_SOCCLK: 2018 clk_type = SMU_SOCCLK; break; 2019 case PP_FCLK: 2020 clk_type = SMU_FCLK; break; 2021 case PP_DCEFCLK: 2022 clk_type = SMU_DCEFCLK; break; 2023 case PP_VCLK: 2024 clk_type = SMU_VCLK; break; 2025 case PP_DCLK: 2026 clk_type = SMU_DCLK; break; 2027 case OD_SCLK: 2028 clk_type = SMU_OD_SCLK; break; 2029 case OD_MCLK: 2030 clk_type = SMU_OD_MCLK; break; 2031 case OD_VDDC_CURVE: 2032 clk_type = SMU_OD_VDDC_CURVE; break; 2033 case OD_RANGE: 2034 clk_type = SMU_OD_RANGE; break; 2035 default: 2036 return -EINVAL; 2037 } 2038 2039 return smu_force_smuclk_levels(smu, clk_type, mask); 2040 } 2041 2042 /* 2043 * On system suspending or resetting, the dpm_enabled 2044 * flag will be cleared. So that those SMU services which 2045 * are not supported will be gated. 2046 * However, the mp1 state setting should still be granted 2047 * even if the dpm_enabled cleared. 2048 */ 2049 static int smu_set_mp1_state(void *handle, 2050 enum pp_mp1_state mp1_state) 2051 { 2052 struct smu_context *smu = handle; 2053 int ret = 0; 2054 2055 if (!smu->pm_enabled) 2056 return -EOPNOTSUPP; 2057 2058 if (smu->ppt_funcs && 2059 smu->ppt_funcs->set_mp1_state) 2060 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2061 2062 return ret; 2063 } 2064 2065 static int smu_set_df_cstate(void *handle, 2066 enum pp_df_cstate state) 2067 { 2068 struct smu_context *smu = handle; 2069 int ret = 0; 2070 2071 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2072 return -EOPNOTSUPP; 2073 2074 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2075 return 0; 2076 2077 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2078 if (ret) 2079 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2080 2081 return ret; 2082 } 2083 2084 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 2085 { 2086 int ret = 0; 2087 2088 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2089 return -EOPNOTSUPP; 2090 2091 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 2092 return 0; 2093 2094 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 2095 if (ret) 2096 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 2097 2098 return ret; 2099 } 2100 2101 int smu_write_watermarks_table(struct smu_context *smu) 2102 { 2103 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2104 return -EOPNOTSUPP; 2105 2106 return smu_set_watermarks_table(smu, NULL); 2107 } 2108 2109 static int smu_set_watermarks_for_clock_ranges(void *handle, 2110 struct pp_smu_wm_range_sets *clock_ranges) 2111 { 2112 struct smu_context *smu = handle; 2113 2114 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2115 return -EOPNOTSUPP; 2116 2117 if (smu->disable_watermark) 2118 return 0; 2119 2120 return smu_set_watermarks_table(smu, clock_ranges); 2121 } 2122 2123 int smu_set_ac_dc(struct smu_context *smu) 2124 { 2125 int ret = 0; 2126 2127 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2128 return -EOPNOTSUPP; 2129 2130 /* controlled by firmware */ 2131 if (smu->dc_controlled_by_gpio) 2132 return 0; 2133 2134 ret = smu_set_power_source(smu, 2135 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2136 SMU_POWER_SOURCE_DC); 2137 if (ret) 2138 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2139 smu->adev->pm.ac_power ? "AC" : "DC"); 2140 2141 return ret; 2142 } 2143 2144 const struct amd_ip_funcs smu_ip_funcs = { 2145 .name = "smu", 2146 .early_init = smu_early_init, 2147 .late_init = smu_late_init, 2148 .sw_init = smu_sw_init, 2149 .sw_fini = smu_sw_fini, 2150 .hw_init = smu_hw_init, 2151 .hw_fini = smu_hw_fini, 2152 .late_fini = smu_late_fini, 2153 .suspend = smu_suspend, 2154 .resume = smu_resume, 2155 .is_idle = NULL, 2156 .check_soft_reset = NULL, 2157 .wait_for_idle = NULL, 2158 .soft_reset = NULL, 2159 .set_clockgating_state = smu_set_clockgating_state, 2160 .set_powergating_state = smu_set_powergating_state, 2161 }; 2162 2163 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 2164 { 2165 .type = AMD_IP_BLOCK_TYPE_SMC, 2166 .major = 11, 2167 .minor = 0, 2168 .rev = 0, 2169 .funcs = &smu_ip_funcs, 2170 }; 2171 2172 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 2173 { 2174 .type = AMD_IP_BLOCK_TYPE_SMC, 2175 .major = 12, 2176 .minor = 0, 2177 .rev = 0, 2178 .funcs = &smu_ip_funcs, 2179 }; 2180 2181 const struct amdgpu_ip_block_version smu_v13_0_ip_block = 2182 { 2183 .type = AMD_IP_BLOCK_TYPE_SMC, 2184 .major = 13, 2185 .minor = 0, 2186 .rev = 0, 2187 .funcs = &smu_ip_funcs, 2188 }; 2189 2190 static int smu_load_microcode(void *handle) 2191 { 2192 struct smu_context *smu = handle; 2193 struct amdgpu_device *adev = smu->adev; 2194 int ret = 0; 2195 2196 if (!smu->pm_enabled) 2197 return -EOPNOTSUPP; 2198 2199 /* This should be used for non PSP loading */ 2200 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2201 return 0; 2202 2203 if (smu->ppt_funcs->load_microcode) { 2204 ret = smu->ppt_funcs->load_microcode(smu); 2205 if (ret) { 2206 dev_err(adev->dev, "Load microcode failed\n"); 2207 return ret; 2208 } 2209 } 2210 2211 if (smu->ppt_funcs->check_fw_status) { 2212 ret = smu->ppt_funcs->check_fw_status(smu); 2213 if (ret) { 2214 dev_err(adev->dev, "SMC is not ready\n"); 2215 return ret; 2216 } 2217 } 2218 2219 return ret; 2220 } 2221 2222 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2223 { 2224 int ret = 0; 2225 2226 if (smu->ppt_funcs->set_gfx_cgpg) 2227 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2228 2229 return ret; 2230 } 2231 2232 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2233 { 2234 struct smu_context *smu = handle; 2235 int ret = 0; 2236 2237 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2238 return -EOPNOTSUPP; 2239 2240 if (!smu->ppt_funcs->set_fan_speed_rpm) 2241 return -EOPNOTSUPP; 2242 2243 if (speed == U32_MAX) 2244 return -EINVAL; 2245 2246 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2247 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2248 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2249 smu->user_dpm_profile.fan_speed_rpm = speed; 2250 2251 /* Override custom PWM setting as they cannot co-exist */ 2252 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2253 smu->user_dpm_profile.fan_speed_pwm = 0; 2254 } 2255 2256 return ret; 2257 } 2258 2259 /** 2260 * smu_get_power_limit - Request one of the SMU Power Limits 2261 * 2262 * @handle: pointer to smu context 2263 * @limit: requested limit is written back to this variable 2264 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2265 * @pp_power_type: &pp_power_type type of power 2266 * Return: 0 on success, <0 on error 2267 * 2268 */ 2269 int smu_get_power_limit(void *handle, 2270 uint32_t *limit, 2271 enum pp_power_limit_level pp_limit_level, 2272 enum pp_power_type pp_power_type) 2273 { 2274 struct smu_context *smu = handle; 2275 struct amdgpu_device *adev = smu->adev; 2276 enum smu_ppt_limit_level limit_level; 2277 uint32_t limit_type; 2278 int ret = 0; 2279 2280 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2281 return -EOPNOTSUPP; 2282 2283 switch(pp_power_type) { 2284 case PP_PWR_TYPE_SUSTAINED: 2285 limit_type = SMU_DEFAULT_PPT_LIMIT; 2286 break; 2287 case PP_PWR_TYPE_FAST: 2288 limit_type = SMU_FAST_PPT_LIMIT; 2289 break; 2290 default: 2291 return -EOPNOTSUPP; 2292 break; 2293 } 2294 2295 switch(pp_limit_level){ 2296 case PP_PWR_LIMIT_CURRENT: 2297 limit_level = SMU_PPT_LIMIT_CURRENT; 2298 break; 2299 case PP_PWR_LIMIT_DEFAULT: 2300 limit_level = SMU_PPT_LIMIT_DEFAULT; 2301 break; 2302 case PP_PWR_LIMIT_MAX: 2303 limit_level = SMU_PPT_LIMIT_MAX; 2304 break; 2305 case PP_PWR_LIMIT_MIN: 2306 default: 2307 return -EOPNOTSUPP; 2308 break; 2309 } 2310 2311 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2312 if (smu->ppt_funcs->get_ppt_limit) 2313 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2314 } else { 2315 switch (limit_level) { 2316 case SMU_PPT_LIMIT_CURRENT: 2317 switch (adev->ip_versions[MP1_HWIP][0]) { 2318 case IP_VERSION(13, 0, 2): 2319 case IP_VERSION(11, 0, 7): 2320 case IP_VERSION(11, 0, 11): 2321 case IP_VERSION(11, 0, 12): 2322 case IP_VERSION(11, 0, 13): 2323 ret = smu_get_asic_power_limits(smu, 2324 &smu->current_power_limit, 2325 NULL, 2326 NULL); 2327 break; 2328 default: 2329 break; 2330 } 2331 *limit = smu->current_power_limit; 2332 break; 2333 case SMU_PPT_LIMIT_DEFAULT: 2334 *limit = smu->default_power_limit; 2335 break; 2336 case SMU_PPT_LIMIT_MAX: 2337 *limit = smu->max_power_limit; 2338 break; 2339 default: 2340 break; 2341 } 2342 } 2343 2344 return ret; 2345 } 2346 2347 static int smu_set_power_limit(void *handle, uint32_t limit) 2348 { 2349 struct smu_context *smu = handle; 2350 uint32_t limit_type = limit >> 24; 2351 int ret = 0; 2352 2353 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2354 return -EOPNOTSUPP; 2355 2356 limit &= (1<<24)-1; 2357 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2358 if (smu->ppt_funcs->set_power_limit) 2359 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2360 2361 if (limit > smu->max_power_limit) { 2362 dev_err(smu->adev->dev, 2363 "New power limit (%d) is over the max allowed %d\n", 2364 limit, smu->max_power_limit); 2365 return -EINVAL; 2366 } 2367 2368 if (!limit) 2369 limit = smu->current_power_limit; 2370 2371 if (smu->ppt_funcs->set_power_limit) { 2372 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2373 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2374 smu->user_dpm_profile.power_limit = limit; 2375 } 2376 2377 return ret; 2378 } 2379 2380 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2381 { 2382 int ret = 0; 2383 2384 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2385 return -EOPNOTSUPP; 2386 2387 if (smu->ppt_funcs->print_clk_levels) 2388 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2389 2390 return ret; 2391 } 2392 2393 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2394 { 2395 enum smu_clk_type clk_type; 2396 2397 switch (type) { 2398 case PP_SCLK: 2399 clk_type = SMU_SCLK; break; 2400 case PP_MCLK: 2401 clk_type = SMU_MCLK; break; 2402 case PP_PCIE: 2403 clk_type = SMU_PCIE; break; 2404 case PP_SOCCLK: 2405 clk_type = SMU_SOCCLK; break; 2406 case PP_FCLK: 2407 clk_type = SMU_FCLK; break; 2408 case PP_DCEFCLK: 2409 clk_type = SMU_DCEFCLK; break; 2410 case PP_VCLK: 2411 clk_type = SMU_VCLK; break; 2412 case PP_DCLK: 2413 clk_type = SMU_DCLK; break; 2414 case OD_SCLK: 2415 clk_type = SMU_OD_SCLK; break; 2416 case OD_MCLK: 2417 clk_type = SMU_OD_MCLK; break; 2418 case OD_VDDC_CURVE: 2419 clk_type = SMU_OD_VDDC_CURVE; break; 2420 case OD_RANGE: 2421 clk_type = SMU_OD_RANGE; break; 2422 case OD_VDDGFX_OFFSET: 2423 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2424 case OD_CCLK: 2425 clk_type = SMU_OD_CCLK; break; 2426 default: 2427 clk_type = SMU_CLK_COUNT; break; 2428 } 2429 2430 return clk_type; 2431 } 2432 2433 static int smu_print_ppclk_levels(void *handle, 2434 enum pp_clock_type type, 2435 char *buf) 2436 { 2437 struct smu_context *smu = handle; 2438 enum smu_clk_type clk_type; 2439 2440 clk_type = smu_convert_to_smuclk(type); 2441 if (clk_type == SMU_CLK_COUNT) 2442 return -EINVAL; 2443 2444 return smu_print_smuclk_levels(smu, clk_type, buf); 2445 } 2446 2447 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2448 { 2449 struct smu_context *smu = handle; 2450 enum smu_clk_type clk_type; 2451 2452 clk_type = smu_convert_to_smuclk(type); 2453 if (clk_type == SMU_CLK_COUNT) 2454 return -EINVAL; 2455 2456 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2457 return -EOPNOTSUPP; 2458 2459 if (!smu->ppt_funcs->emit_clk_levels) 2460 return -ENOENT; 2461 2462 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2463 2464 } 2465 2466 static int smu_od_edit_dpm_table(void *handle, 2467 enum PP_OD_DPM_TABLE_COMMAND type, 2468 long *input, uint32_t size) 2469 { 2470 struct smu_context *smu = handle; 2471 int ret = 0; 2472 2473 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2474 return -EOPNOTSUPP; 2475 2476 if (smu->ppt_funcs->od_edit_dpm_table) { 2477 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2478 } 2479 2480 return ret; 2481 } 2482 2483 static int smu_read_sensor(void *handle, 2484 int sensor, 2485 void *data, 2486 int *size_arg) 2487 { 2488 struct smu_context *smu = handle; 2489 struct smu_umd_pstate_table *pstate_table = 2490 &smu->pstate_table; 2491 int ret = 0; 2492 uint32_t *size, size_val; 2493 2494 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2495 return -EOPNOTSUPP; 2496 2497 if (!data || !size_arg) 2498 return -EINVAL; 2499 2500 size_val = *size_arg; 2501 size = &size_val; 2502 2503 if (smu->ppt_funcs->read_sensor) 2504 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2505 goto unlock; 2506 2507 switch (sensor) { 2508 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2509 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2510 *size = 4; 2511 break; 2512 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2513 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2514 *size = 4; 2515 break; 2516 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 2517 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 2518 *size = 4; 2519 break; 2520 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 2521 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 2522 *size = 4; 2523 break; 2524 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2525 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2526 *size = 8; 2527 break; 2528 case AMDGPU_PP_SENSOR_UVD_POWER: 2529 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2530 *size = 4; 2531 break; 2532 case AMDGPU_PP_SENSOR_VCE_POWER: 2533 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2534 *size = 4; 2535 break; 2536 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2537 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2538 *size = 4; 2539 break; 2540 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2541 *(uint32_t *)data = 0; 2542 *size = 4; 2543 break; 2544 default: 2545 *size = 0; 2546 ret = -EOPNOTSUPP; 2547 break; 2548 } 2549 2550 unlock: 2551 // assign uint32_t to int 2552 *size_arg = size_val; 2553 2554 return ret; 2555 } 2556 2557 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 2558 { 2559 int ret = -EINVAL; 2560 struct smu_context *smu = handle; 2561 2562 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 2563 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 2564 2565 return ret; 2566 } 2567 2568 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 2569 { 2570 int ret = -EINVAL; 2571 struct smu_context *smu = handle; 2572 2573 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 2574 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 2575 2576 return ret; 2577 } 2578 2579 static int smu_get_power_profile_mode(void *handle, char *buf) 2580 { 2581 struct smu_context *smu = handle; 2582 2583 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2584 !smu->ppt_funcs->get_power_profile_mode) 2585 return -EOPNOTSUPP; 2586 if (!buf) 2587 return -EINVAL; 2588 2589 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 2590 } 2591 2592 static int smu_set_power_profile_mode(void *handle, 2593 long *param, 2594 uint32_t param_size) 2595 { 2596 struct smu_context *smu = handle; 2597 2598 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2599 !smu->ppt_funcs->set_power_profile_mode) 2600 return -EOPNOTSUPP; 2601 2602 return smu_bump_power_profile_mode(smu, param, param_size); 2603 } 2604 2605 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 2606 { 2607 struct smu_context *smu = handle; 2608 2609 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2610 return -EOPNOTSUPP; 2611 2612 if (!smu->ppt_funcs->get_fan_control_mode) 2613 return -EOPNOTSUPP; 2614 2615 if (!fan_mode) 2616 return -EINVAL; 2617 2618 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 2619 2620 return 0; 2621 } 2622 2623 static int smu_set_fan_control_mode(void *handle, u32 value) 2624 { 2625 struct smu_context *smu = handle; 2626 int ret = 0; 2627 2628 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2629 return -EOPNOTSUPP; 2630 2631 if (!smu->ppt_funcs->set_fan_control_mode) 2632 return -EOPNOTSUPP; 2633 2634 if (value == U32_MAX) 2635 return -EINVAL; 2636 2637 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2638 if (ret) 2639 goto out; 2640 2641 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2642 smu->user_dpm_profile.fan_mode = value; 2643 2644 /* reset user dpm fan speed */ 2645 if (value != AMD_FAN_CTRL_MANUAL) { 2646 smu->user_dpm_profile.fan_speed_pwm = 0; 2647 smu->user_dpm_profile.fan_speed_rpm = 0; 2648 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 2649 } 2650 } 2651 2652 out: 2653 return ret; 2654 } 2655 2656 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 2657 { 2658 struct smu_context *smu = handle; 2659 int ret = 0; 2660 2661 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2662 return -EOPNOTSUPP; 2663 2664 if (!smu->ppt_funcs->get_fan_speed_pwm) 2665 return -EOPNOTSUPP; 2666 2667 if (!speed) 2668 return -EINVAL; 2669 2670 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 2671 2672 return ret; 2673 } 2674 2675 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 2676 { 2677 struct smu_context *smu = handle; 2678 int ret = 0; 2679 2680 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2681 return -EOPNOTSUPP; 2682 2683 if (!smu->ppt_funcs->set_fan_speed_pwm) 2684 return -EOPNOTSUPP; 2685 2686 if (speed == U32_MAX) 2687 return -EINVAL; 2688 2689 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 2690 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2691 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 2692 smu->user_dpm_profile.fan_speed_pwm = speed; 2693 2694 /* Override custom RPM setting as they cannot co-exist */ 2695 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 2696 smu->user_dpm_profile.fan_speed_rpm = 0; 2697 } 2698 2699 return ret; 2700 } 2701 2702 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2703 { 2704 struct smu_context *smu = handle; 2705 int ret = 0; 2706 2707 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2708 return -EOPNOTSUPP; 2709 2710 if (!smu->ppt_funcs->get_fan_speed_rpm) 2711 return -EOPNOTSUPP; 2712 2713 if (!speed) 2714 return -EINVAL; 2715 2716 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 2717 2718 return ret; 2719 } 2720 2721 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 2722 { 2723 struct smu_context *smu = handle; 2724 2725 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2726 return -EOPNOTSUPP; 2727 2728 return smu_set_min_dcef_deep_sleep(smu, clk); 2729 } 2730 2731 static int smu_get_clock_by_type_with_latency(void *handle, 2732 enum amd_pp_clock_type type, 2733 struct pp_clock_levels_with_latency *clocks) 2734 { 2735 struct smu_context *smu = handle; 2736 enum smu_clk_type clk_type; 2737 int ret = 0; 2738 2739 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2740 return -EOPNOTSUPP; 2741 2742 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 2743 switch (type) { 2744 case amd_pp_sys_clock: 2745 clk_type = SMU_GFXCLK; 2746 break; 2747 case amd_pp_mem_clock: 2748 clk_type = SMU_MCLK; 2749 break; 2750 case amd_pp_dcef_clock: 2751 clk_type = SMU_DCEFCLK; 2752 break; 2753 case amd_pp_disp_clock: 2754 clk_type = SMU_DISPCLK; 2755 break; 2756 default: 2757 dev_err(smu->adev->dev, "Invalid clock type!\n"); 2758 return -EINVAL; 2759 } 2760 2761 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2762 } 2763 2764 return ret; 2765 } 2766 2767 static int smu_display_clock_voltage_request(void *handle, 2768 struct pp_display_clock_request *clock_req) 2769 { 2770 struct smu_context *smu = handle; 2771 int ret = 0; 2772 2773 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2774 return -EOPNOTSUPP; 2775 2776 if (smu->ppt_funcs->display_clock_voltage_request) 2777 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2778 2779 return ret; 2780 } 2781 2782 2783 static int smu_display_disable_memory_clock_switch(void *handle, 2784 bool disable_memory_clock_switch) 2785 { 2786 struct smu_context *smu = handle; 2787 int ret = -EINVAL; 2788 2789 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2790 return -EOPNOTSUPP; 2791 2792 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2793 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2794 2795 return ret; 2796 } 2797 2798 static int smu_set_xgmi_pstate(void *handle, 2799 uint32_t pstate) 2800 { 2801 struct smu_context *smu = handle; 2802 int ret = 0; 2803 2804 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2805 return -EOPNOTSUPP; 2806 2807 if (smu->ppt_funcs->set_xgmi_pstate) 2808 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2809 2810 if(ret) 2811 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2812 2813 return ret; 2814 } 2815 2816 static int smu_get_baco_capability(void *handle, bool *cap) 2817 { 2818 struct smu_context *smu = handle; 2819 2820 *cap = false; 2821 2822 if (!smu->pm_enabled) 2823 return 0; 2824 2825 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2826 *cap = smu->ppt_funcs->baco_is_support(smu); 2827 2828 return 0; 2829 } 2830 2831 static int smu_baco_set_state(void *handle, int state) 2832 { 2833 struct smu_context *smu = handle; 2834 int ret = 0; 2835 2836 if (!smu->pm_enabled) 2837 return -EOPNOTSUPP; 2838 2839 if (state == 0) { 2840 if (smu->ppt_funcs->baco_exit) 2841 ret = smu->ppt_funcs->baco_exit(smu); 2842 } else if (state == 1) { 2843 if (smu->ppt_funcs->baco_enter) 2844 ret = smu->ppt_funcs->baco_enter(smu); 2845 } else { 2846 return -EINVAL; 2847 } 2848 2849 if (ret) 2850 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 2851 (state)?"enter":"exit"); 2852 2853 return ret; 2854 } 2855 2856 bool smu_mode1_reset_is_support(struct smu_context *smu) 2857 { 2858 bool ret = false; 2859 2860 if (!smu->pm_enabled) 2861 return false; 2862 2863 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2864 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2865 2866 return ret; 2867 } 2868 2869 bool smu_mode2_reset_is_support(struct smu_context *smu) 2870 { 2871 bool ret = false; 2872 2873 if (!smu->pm_enabled) 2874 return false; 2875 2876 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 2877 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 2878 2879 return ret; 2880 } 2881 2882 int smu_mode1_reset(struct smu_context *smu) 2883 { 2884 int ret = 0; 2885 2886 if (!smu->pm_enabled) 2887 return -EOPNOTSUPP; 2888 2889 if (smu->ppt_funcs->mode1_reset) 2890 ret = smu->ppt_funcs->mode1_reset(smu); 2891 2892 return ret; 2893 } 2894 2895 static int smu_mode2_reset(void *handle) 2896 { 2897 struct smu_context *smu = handle; 2898 int ret = 0; 2899 2900 if (!smu->pm_enabled) 2901 return -EOPNOTSUPP; 2902 2903 if (smu->ppt_funcs->mode2_reset) 2904 ret = smu->ppt_funcs->mode2_reset(smu); 2905 2906 if (ret) 2907 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2908 2909 return ret; 2910 } 2911 2912 static int smu_enable_gfx_features(void *handle) 2913 { 2914 struct smu_context *smu = handle; 2915 int ret = 0; 2916 2917 if (!smu->pm_enabled) 2918 return -EOPNOTSUPP; 2919 2920 if (smu->ppt_funcs->enable_gfx_features) 2921 ret = smu->ppt_funcs->enable_gfx_features(smu); 2922 2923 if (ret) 2924 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 2925 2926 return ret; 2927 } 2928 2929 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 2930 struct pp_smu_nv_clock_table *max_clocks) 2931 { 2932 struct smu_context *smu = handle; 2933 int ret = 0; 2934 2935 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2936 return -EOPNOTSUPP; 2937 2938 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2939 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2940 2941 return ret; 2942 } 2943 2944 static int smu_get_uclk_dpm_states(void *handle, 2945 unsigned int *clock_values_in_khz, 2946 unsigned int *num_states) 2947 { 2948 struct smu_context *smu = handle; 2949 int ret = 0; 2950 2951 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2952 return -EOPNOTSUPP; 2953 2954 if (smu->ppt_funcs->get_uclk_dpm_states) 2955 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2956 2957 return ret; 2958 } 2959 2960 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 2961 { 2962 struct smu_context *smu = handle; 2963 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2964 2965 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2966 return -EOPNOTSUPP; 2967 2968 if (smu->ppt_funcs->get_current_power_state) 2969 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2970 2971 return pm_state; 2972 } 2973 2974 static int smu_get_dpm_clock_table(void *handle, 2975 struct dpm_clocks *clock_table) 2976 { 2977 struct smu_context *smu = handle; 2978 int ret = 0; 2979 2980 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2981 return -EOPNOTSUPP; 2982 2983 if (smu->ppt_funcs->get_dpm_clock_table) 2984 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 2985 2986 return ret; 2987 } 2988 2989 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 2990 { 2991 struct smu_context *smu = handle; 2992 2993 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2994 return -EOPNOTSUPP; 2995 2996 if (!smu->ppt_funcs->get_gpu_metrics) 2997 return -EOPNOTSUPP; 2998 2999 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3000 } 3001 3002 static int smu_enable_mgpu_fan_boost(void *handle) 3003 { 3004 struct smu_context *smu = handle; 3005 int ret = 0; 3006 3007 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3008 return -EOPNOTSUPP; 3009 3010 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3011 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3012 3013 return ret; 3014 } 3015 3016 static int smu_gfx_state_change_set(void *handle, 3017 uint32_t state) 3018 { 3019 struct smu_context *smu = handle; 3020 int ret = 0; 3021 3022 if (smu->ppt_funcs->gfx_state_change_set) 3023 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3024 3025 return ret; 3026 } 3027 3028 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3029 { 3030 int ret = 0; 3031 3032 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3033 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3034 3035 return ret; 3036 } 3037 3038 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3039 { 3040 int ret = -EOPNOTSUPP; 3041 3042 if (smu->ppt_funcs && 3043 smu->ppt_funcs->get_ecc_info) 3044 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3045 3046 return ret; 3047 3048 } 3049 3050 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3051 { 3052 struct smu_context *smu = handle; 3053 struct smu_table_context *smu_table = &smu->smu_table; 3054 struct smu_table *memory_pool = &smu_table->memory_pool; 3055 3056 if (!addr || !size) 3057 return -EINVAL; 3058 3059 *addr = NULL; 3060 *size = 0; 3061 if (memory_pool->bo) { 3062 *addr = memory_pool->cpu_addr; 3063 *size = memory_pool->size; 3064 } 3065 3066 return 0; 3067 } 3068 3069 static const struct amd_pm_funcs swsmu_pm_funcs = { 3070 /* export for sysfs */ 3071 .set_fan_control_mode = smu_set_fan_control_mode, 3072 .get_fan_control_mode = smu_get_fan_control_mode, 3073 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3074 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3075 .force_clock_level = smu_force_ppclk_levels, 3076 .print_clock_levels = smu_print_ppclk_levels, 3077 .emit_clock_levels = smu_emit_ppclk_levels, 3078 .force_performance_level = smu_force_performance_level, 3079 .read_sensor = smu_read_sensor, 3080 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3081 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3082 .get_performance_level = smu_get_performance_level, 3083 .get_current_power_state = smu_get_current_power_state, 3084 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3085 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3086 .get_pp_num_states = smu_get_power_num_states, 3087 .get_pp_table = smu_sys_get_pp_table, 3088 .set_pp_table = smu_sys_set_pp_table, 3089 .switch_power_profile = smu_switch_power_profile, 3090 /* export to amdgpu */ 3091 .dispatch_tasks = smu_handle_dpm_task, 3092 .load_firmware = smu_load_microcode, 3093 .set_powergating_by_smu = smu_dpm_set_power_gate, 3094 .set_power_limit = smu_set_power_limit, 3095 .get_power_limit = smu_get_power_limit, 3096 .get_power_profile_mode = smu_get_power_profile_mode, 3097 .set_power_profile_mode = smu_set_power_profile_mode, 3098 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3099 .set_mp1_state = smu_set_mp1_state, 3100 .gfx_state_change_set = smu_gfx_state_change_set, 3101 /* export to DC */ 3102 .get_sclk = smu_get_sclk, 3103 .get_mclk = smu_get_mclk, 3104 .display_configuration_change = smu_display_configuration_change, 3105 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3106 .display_clock_voltage_request = smu_display_clock_voltage_request, 3107 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3108 .set_active_display_count = smu_set_display_count, 3109 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3110 .get_asic_baco_capability = smu_get_baco_capability, 3111 .set_asic_baco_state = smu_baco_set_state, 3112 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3113 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3114 .asic_reset_mode_2 = smu_mode2_reset, 3115 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3116 .set_df_cstate = smu_set_df_cstate, 3117 .set_xgmi_pstate = smu_set_xgmi_pstate, 3118 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3119 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3120 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3121 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3122 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3123 .get_dpm_clock_table = smu_get_dpm_clock_table, 3124 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3125 }; 3126 3127 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3128 uint64_t event_arg) 3129 { 3130 int ret = -EINVAL; 3131 3132 if (smu->ppt_funcs->wait_for_event) 3133 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3134 3135 return ret; 3136 } 3137 3138 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3139 { 3140 3141 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3142 return -EOPNOTSUPP; 3143 3144 /* Confirm the buffer allocated is of correct size */ 3145 if (size != smu->stb_context.stb_buf_size) 3146 return -EINVAL; 3147 3148 /* 3149 * No need to lock smu mutex as we access STB directly through MMIO 3150 * and not going through SMU messaging route (for now at least). 3151 * For registers access rely on implementation internal locking. 3152 */ 3153 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3154 } 3155 3156 #if defined(CONFIG_DEBUG_FS) 3157 3158 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3159 { 3160 struct amdgpu_device *adev = filp->f_inode->i_private; 3161 struct smu_context *smu = adev->powerplay.pp_handle; 3162 unsigned char *buf; 3163 int r; 3164 3165 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3166 if (!buf) 3167 return -ENOMEM; 3168 3169 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3170 if (r) 3171 goto out; 3172 3173 filp->private_data = buf; 3174 3175 return 0; 3176 3177 out: 3178 kvfree(buf); 3179 return r; 3180 } 3181 3182 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3183 loff_t *pos) 3184 { 3185 struct amdgpu_device *adev = filp->f_inode->i_private; 3186 struct smu_context *smu = adev->powerplay.pp_handle; 3187 3188 3189 if (!filp->private_data) 3190 return -EINVAL; 3191 3192 return simple_read_from_buffer(buf, 3193 size, 3194 pos, filp->private_data, 3195 smu->stb_context.stb_buf_size); 3196 } 3197 3198 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3199 { 3200 kvfree(filp->private_data); 3201 filp->private_data = NULL; 3202 3203 return 0; 3204 } 3205 3206 /* 3207 * We have to define not only read method but also 3208 * open and release because .read takes up to PAGE_SIZE 3209 * data each time so and so is invoked multiple times. 3210 * We allocate the STB buffer in .open and release it 3211 * in .release 3212 */ 3213 static const struct file_operations smu_stb_debugfs_fops = { 3214 .owner = THIS_MODULE, 3215 .open = smu_stb_debugfs_open, 3216 .read = smu_stb_debugfs_read, 3217 .release = smu_stb_debugfs_release, 3218 .llseek = default_llseek, 3219 }; 3220 3221 #endif 3222 3223 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3224 { 3225 #if defined(CONFIG_DEBUG_FS) 3226 3227 struct smu_context *smu = adev->powerplay.pp_handle; 3228 3229 if (!smu || (!smu->stb_context.stb_buf_size)) 3230 return; 3231 3232 debugfs_create_file_size("amdgpu_smu_stb_dump", 3233 S_IRUSR, 3234 adev_to_drm(adev)->primary->debugfs_root, 3235 adev, 3236 &smu_stb_debugfs_fops, 3237 smu->stb_context.stb_buf_size); 3238 #endif 3239 } 3240 3241 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3242 { 3243 int ret = 0; 3244 3245 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3246 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3247 3248 return ret; 3249 } 3250 3251 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3252 { 3253 int ret = 0; 3254 3255 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3256 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3257 3258 return ret; 3259 } 3260