1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "amd_pcie.h" 38 39 /* 40 * DO NOT use these for err/warn/info/debug messages. 41 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 42 * They are more MGPU friendly. 43 */ 44 #undef pr_err 45 #undef pr_warn 46 #undef pr_info 47 #undef pr_debug 48 49 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf) 50 { 51 size_t size = 0; 52 53 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 54 return -EOPNOTSUPP; 55 56 mutex_lock(&smu->mutex); 57 58 size = smu_get_pp_feature_mask(smu, buf); 59 60 mutex_unlock(&smu->mutex); 61 62 return size; 63 } 64 65 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask) 66 { 67 int ret = 0; 68 69 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 70 return -EOPNOTSUPP; 71 72 mutex_lock(&smu->mutex); 73 74 ret = smu_set_pp_feature_mask(smu, new_mask); 75 76 mutex_unlock(&smu->mutex); 77 78 return ret; 79 } 80 81 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) 82 { 83 int ret = 0; 84 struct smu_context *smu = &adev->smu; 85 86 if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status) 87 *value = smu_get_gfx_off_status(smu); 88 else 89 ret = -EINVAL; 90 91 return ret; 92 } 93 94 int smu_set_soft_freq_range(struct smu_context *smu, 95 enum smu_clk_type clk_type, 96 uint32_t min, 97 uint32_t max) 98 { 99 int ret = 0; 100 101 mutex_lock(&smu->mutex); 102 103 if (smu->ppt_funcs->set_soft_freq_limited_range) 104 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 105 clk_type, 106 min, 107 max); 108 109 mutex_unlock(&smu->mutex); 110 111 return ret; 112 } 113 114 int smu_get_dpm_freq_range(struct smu_context *smu, 115 enum smu_clk_type clk_type, 116 uint32_t *min, 117 uint32_t *max) 118 { 119 int ret = 0; 120 121 if (!min && !max) 122 return -EINVAL; 123 124 mutex_lock(&smu->mutex); 125 126 if (smu->ppt_funcs->get_dpm_ultimate_freq) 127 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 128 clk_type, 129 min, 130 max); 131 132 mutex_unlock(&smu->mutex); 133 134 return ret; 135 } 136 137 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu, 138 bool enable) 139 { 140 struct smu_power_context *smu_power = &smu->smu_power; 141 struct smu_power_gate *power_gate = &smu_power->power_gate; 142 int ret = 0; 143 144 if (!smu->ppt_funcs->dpm_set_vcn_enable) 145 return 0; 146 147 if (atomic_read(&power_gate->vcn_gated) ^ enable) 148 return 0; 149 150 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 151 if (!ret) 152 atomic_set(&power_gate->vcn_gated, !enable); 153 154 return ret; 155 } 156 157 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 158 bool enable) 159 { 160 struct smu_power_context *smu_power = &smu->smu_power; 161 struct smu_power_gate *power_gate = &smu_power->power_gate; 162 int ret = 0; 163 164 mutex_lock(&power_gate->vcn_gate_lock); 165 166 ret = smu_dpm_set_vcn_enable_locked(smu, enable); 167 168 mutex_unlock(&power_gate->vcn_gate_lock); 169 170 return ret; 171 } 172 173 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu, 174 bool enable) 175 { 176 struct smu_power_context *smu_power = &smu->smu_power; 177 struct smu_power_gate *power_gate = &smu_power->power_gate; 178 int ret = 0; 179 180 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 181 return 0; 182 183 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 184 return 0; 185 186 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 187 if (!ret) 188 atomic_set(&power_gate->jpeg_gated, !enable); 189 190 return ret; 191 } 192 193 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 194 bool enable) 195 { 196 struct smu_power_context *smu_power = &smu->smu_power; 197 struct smu_power_gate *power_gate = &smu_power->power_gate; 198 int ret = 0; 199 200 mutex_lock(&power_gate->jpeg_gate_lock); 201 202 ret = smu_dpm_set_jpeg_enable_locked(smu, enable); 203 204 mutex_unlock(&power_gate->jpeg_gate_lock); 205 206 return ret; 207 } 208 209 /** 210 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 211 * 212 * @smu: smu_context pointer 213 * @block_type: the IP block to power gate/ungate 214 * @gate: to power gate if true, ungate otherwise 215 * 216 * This API uses no smu->mutex lock protection due to: 217 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 218 * This is guarded to be race condition free by the caller. 219 * 2. Or get called on user setting request of power_dpm_force_performance_level. 220 * Under this case, the smu->mutex lock protection is already enforced on 221 * the parent API smu_force_performance_level of the call path. 222 */ 223 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type, 224 bool gate) 225 { 226 int ret = 0; 227 228 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 229 return -EOPNOTSUPP; 230 231 switch (block_type) { 232 /* 233 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 234 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 235 */ 236 case AMD_IP_BLOCK_TYPE_UVD: 237 case AMD_IP_BLOCK_TYPE_VCN: 238 ret = smu_dpm_set_vcn_enable(smu, !gate); 239 if (ret) 240 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 241 gate ? "gate" : "ungate"); 242 break; 243 case AMD_IP_BLOCK_TYPE_GFX: 244 ret = smu_gfx_off_control(smu, gate); 245 if (ret) 246 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 247 gate ? "enable" : "disable"); 248 break; 249 case AMD_IP_BLOCK_TYPE_SDMA: 250 ret = smu_powergate_sdma(smu, gate); 251 if (ret) 252 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 253 gate ? "gate" : "ungate"); 254 break; 255 case AMD_IP_BLOCK_TYPE_JPEG: 256 ret = smu_dpm_set_jpeg_enable(smu, !gate); 257 if (ret) 258 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 259 gate ? "gate" : "ungate"); 260 break; 261 default: 262 dev_err(smu->adev->dev, "Unsupported block type!\n"); 263 return -EINVAL; 264 } 265 266 return ret; 267 } 268 269 int smu_get_power_num_states(struct smu_context *smu, 270 struct pp_states_info *state_info) 271 { 272 if (!state_info) 273 return -EINVAL; 274 275 /* not support power state */ 276 memset(state_info, 0, sizeof(struct pp_states_info)); 277 state_info->nums = 1; 278 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 279 280 return 0; 281 } 282 283 bool is_support_sw_smu(struct amdgpu_device *adev) 284 { 285 if (adev->asic_type >= CHIP_ARCTURUS) 286 return true; 287 288 return false; 289 } 290 291 int smu_sys_get_pp_table(struct smu_context *smu, void **table) 292 { 293 struct smu_table_context *smu_table = &smu->smu_table; 294 uint32_t powerplay_table_size; 295 296 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 297 return -EOPNOTSUPP; 298 299 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 300 return -EINVAL; 301 302 mutex_lock(&smu->mutex); 303 304 if (smu_table->hardcode_pptable) 305 *table = smu_table->hardcode_pptable; 306 else 307 *table = smu_table->power_play_table; 308 309 powerplay_table_size = smu_table->power_play_table_size; 310 311 mutex_unlock(&smu->mutex); 312 313 return powerplay_table_size; 314 } 315 316 int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size) 317 { 318 struct smu_table_context *smu_table = &smu->smu_table; 319 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 320 int ret = 0; 321 322 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 323 return -EOPNOTSUPP; 324 325 if (header->usStructureSize != size) { 326 dev_err(smu->adev->dev, "pp table size not matched !\n"); 327 return -EIO; 328 } 329 330 mutex_lock(&smu->mutex); 331 if (!smu_table->hardcode_pptable) 332 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 333 if (!smu_table->hardcode_pptable) { 334 ret = -ENOMEM; 335 goto failed; 336 } 337 338 memcpy(smu_table->hardcode_pptable, buf, size); 339 smu_table->power_play_table = smu_table->hardcode_pptable; 340 smu_table->power_play_table_size = size; 341 342 /* 343 * Special hw_fini action(for Navi1x, the DPMs disablement will be 344 * skipped) may be needed for custom pptable uploading. 345 */ 346 smu->uploading_custom_pp_table = true; 347 348 ret = smu_reset(smu); 349 if (ret) 350 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 351 352 smu->uploading_custom_pp_table = false; 353 354 failed: 355 mutex_unlock(&smu->mutex); 356 return ret; 357 } 358 359 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 360 { 361 struct smu_feature *feature = &smu->smu_feature; 362 int ret = 0; 363 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 364 365 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 366 367 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 368 SMU_FEATURE_MAX/32); 369 if (ret) 370 return ret; 371 372 bitmap_or(feature->allowed, feature->allowed, 373 (unsigned long *)allowed_feature_mask, 374 feature->feature_num); 375 376 return ret; 377 } 378 379 static int smu_set_funcs(struct amdgpu_device *adev) 380 { 381 struct smu_context *smu = &adev->smu; 382 383 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 384 smu->od_enabled = true; 385 386 switch (adev->asic_type) { 387 case CHIP_NAVI10: 388 case CHIP_NAVI14: 389 case CHIP_NAVI12: 390 navi10_set_ppt_funcs(smu); 391 break; 392 case CHIP_ARCTURUS: 393 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 394 arcturus_set_ppt_funcs(smu); 395 /* OD is not supported on Arcturus */ 396 smu->od_enabled =false; 397 break; 398 case CHIP_SIENNA_CICHLID: 399 case CHIP_NAVY_FLOUNDER: 400 case CHIP_DIMGREY_CAVEFISH: 401 sienna_cichlid_set_ppt_funcs(smu); 402 break; 403 case CHIP_RENOIR: 404 renoir_set_ppt_funcs(smu); 405 break; 406 case CHIP_VANGOGH: 407 vangogh_set_ppt_funcs(smu); 408 /* enable the OD by default to allow the fine grain tuning function */ 409 smu->od_enabled = true; 410 break; 411 default: 412 return -EINVAL; 413 } 414 415 return 0; 416 } 417 418 static int smu_early_init(void *handle) 419 { 420 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 421 struct smu_context *smu = &adev->smu; 422 423 smu->adev = adev; 424 smu->pm_enabled = !!amdgpu_dpm; 425 smu->is_apu = false; 426 mutex_init(&smu->mutex); 427 mutex_init(&smu->smu_baco.mutex); 428 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 429 smu->smu_baco.platform_support = false; 430 431 return smu_set_funcs(adev); 432 } 433 434 static int smu_set_default_dpm_table(struct smu_context *smu) 435 { 436 struct smu_power_context *smu_power = &smu->smu_power; 437 struct smu_power_gate *power_gate = &smu_power->power_gate; 438 int vcn_gate, jpeg_gate; 439 int ret = 0; 440 441 if (!smu->ppt_funcs->set_default_dpm_table) 442 return 0; 443 444 mutex_lock(&power_gate->vcn_gate_lock); 445 mutex_lock(&power_gate->jpeg_gate_lock); 446 447 vcn_gate = atomic_read(&power_gate->vcn_gated); 448 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 449 450 ret = smu_dpm_set_vcn_enable_locked(smu, true); 451 if (ret) 452 goto err0_out; 453 454 ret = smu_dpm_set_jpeg_enable_locked(smu, true); 455 if (ret) 456 goto err1_out; 457 458 ret = smu->ppt_funcs->set_default_dpm_table(smu); 459 if (ret) 460 dev_err(smu->adev->dev, 461 "Failed to setup default dpm clock tables!\n"); 462 463 smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate); 464 err1_out: 465 smu_dpm_set_vcn_enable_locked(smu, !vcn_gate); 466 err0_out: 467 mutex_unlock(&power_gate->jpeg_gate_lock); 468 mutex_unlock(&power_gate->vcn_gate_lock); 469 470 return ret; 471 } 472 473 static int smu_late_init(void *handle) 474 { 475 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 476 struct smu_context *smu = &adev->smu; 477 int ret = 0; 478 479 smu_set_fine_grain_gfx_freq_parameters(smu); 480 481 if (adev->asic_type == CHIP_VANGOGH) 482 return 0; 483 484 if (!smu->pm_enabled) 485 return 0; 486 487 ret = smu_post_init(smu); 488 if (ret) { 489 dev_err(adev->dev, "Failed to post smu init!\n"); 490 return ret; 491 } 492 493 ret = smu_set_default_od_settings(smu); 494 if (ret) { 495 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 496 return ret; 497 } 498 499 ret = smu_populate_umd_state_clk(smu); 500 if (ret) { 501 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 502 return ret; 503 } 504 505 ret = smu_get_asic_power_limits(smu); 506 if (ret) { 507 dev_err(adev->dev, "Failed to get asic power limits!\n"); 508 return ret; 509 } 510 511 smu_get_unique_id(smu); 512 513 smu_get_fan_parameters(smu); 514 515 smu_handle_task(&adev->smu, 516 smu->smu_dpm.dpm_level, 517 AMD_PP_TASK_COMPLETE_INIT, 518 false); 519 520 return 0; 521 } 522 523 static int smu_init_fb_allocations(struct smu_context *smu) 524 { 525 struct amdgpu_device *adev = smu->adev; 526 struct smu_table_context *smu_table = &smu->smu_table; 527 struct smu_table *tables = smu_table->tables; 528 struct smu_table *driver_table = &(smu_table->driver_table); 529 uint32_t max_table_size = 0; 530 int ret, i; 531 532 /* VRAM allocation for tool table */ 533 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 534 ret = amdgpu_bo_create_kernel(adev, 535 tables[SMU_TABLE_PMSTATUSLOG].size, 536 tables[SMU_TABLE_PMSTATUSLOG].align, 537 tables[SMU_TABLE_PMSTATUSLOG].domain, 538 &tables[SMU_TABLE_PMSTATUSLOG].bo, 539 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 540 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 541 if (ret) { 542 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 543 return ret; 544 } 545 } 546 547 /* VRAM allocation for driver table */ 548 for (i = 0; i < SMU_TABLE_COUNT; i++) { 549 if (tables[i].size == 0) 550 continue; 551 552 if (i == SMU_TABLE_PMSTATUSLOG) 553 continue; 554 555 if (max_table_size < tables[i].size) 556 max_table_size = tables[i].size; 557 } 558 559 driver_table->size = max_table_size; 560 driver_table->align = PAGE_SIZE; 561 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 562 563 ret = amdgpu_bo_create_kernel(adev, 564 driver_table->size, 565 driver_table->align, 566 driver_table->domain, 567 &driver_table->bo, 568 &driver_table->mc_address, 569 &driver_table->cpu_addr); 570 if (ret) { 571 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 572 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 573 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 574 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 575 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 576 } 577 578 return ret; 579 } 580 581 static int smu_fini_fb_allocations(struct smu_context *smu) 582 { 583 struct smu_table_context *smu_table = &smu->smu_table; 584 struct smu_table *tables = smu_table->tables; 585 struct smu_table *driver_table = &(smu_table->driver_table); 586 587 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 588 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 589 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 590 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 591 592 amdgpu_bo_free_kernel(&driver_table->bo, 593 &driver_table->mc_address, 594 &driver_table->cpu_addr); 595 596 return 0; 597 } 598 599 /** 600 * smu_alloc_memory_pool - allocate memory pool in the system memory 601 * 602 * @smu: amdgpu_device pointer 603 * 604 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 605 * and DramLogSetDramAddr can notify it changed. 606 * 607 * Returns 0 on success, error on failure. 608 */ 609 static int smu_alloc_memory_pool(struct smu_context *smu) 610 { 611 struct amdgpu_device *adev = smu->adev; 612 struct smu_table_context *smu_table = &smu->smu_table; 613 struct smu_table *memory_pool = &smu_table->memory_pool; 614 uint64_t pool_size = smu->pool_size; 615 int ret = 0; 616 617 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 618 return ret; 619 620 memory_pool->size = pool_size; 621 memory_pool->align = PAGE_SIZE; 622 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 623 624 switch (pool_size) { 625 case SMU_MEMORY_POOL_SIZE_256_MB: 626 case SMU_MEMORY_POOL_SIZE_512_MB: 627 case SMU_MEMORY_POOL_SIZE_1_GB: 628 case SMU_MEMORY_POOL_SIZE_2_GB: 629 ret = amdgpu_bo_create_kernel(adev, 630 memory_pool->size, 631 memory_pool->align, 632 memory_pool->domain, 633 &memory_pool->bo, 634 &memory_pool->mc_address, 635 &memory_pool->cpu_addr); 636 if (ret) 637 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 638 break; 639 default: 640 break; 641 } 642 643 return ret; 644 } 645 646 static int smu_free_memory_pool(struct smu_context *smu) 647 { 648 struct smu_table_context *smu_table = &smu->smu_table; 649 struct smu_table *memory_pool = &smu_table->memory_pool; 650 651 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 652 return 0; 653 654 amdgpu_bo_free_kernel(&memory_pool->bo, 655 &memory_pool->mc_address, 656 &memory_pool->cpu_addr); 657 658 memset(memory_pool, 0, sizeof(struct smu_table)); 659 660 return 0; 661 } 662 663 static int smu_alloc_dummy_read_table(struct smu_context *smu) 664 { 665 struct smu_table_context *smu_table = &smu->smu_table; 666 struct smu_table *dummy_read_1_table = 667 &smu_table->dummy_read_1_table; 668 struct amdgpu_device *adev = smu->adev; 669 int ret = 0; 670 671 dummy_read_1_table->size = 0x40000; 672 dummy_read_1_table->align = PAGE_SIZE; 673 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 674 675 ret = amdgpu_bo_create_kernel(adev, 676 dummy_read_1_table->size, 677 dummy_read_1_table->align, 678 dummy_read_1_table->domain, 679 &dummy_read_1_table->bo, 680 &dummy_read_1_table->mc_address, 681 &dummy_read_1_table->cpu_addr); 682 if (ret) 683 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 684 685 return ret; 686 } 687 688 static void smu_free_dummy_read_table(struct smu_context *smu) 689 { 690 struct smu_table_context *smu_table = &smu->smu_table; 691 struct smu_table *dummy_read_1_table = 692 &smu_table->dummy_read_1_table; 693 694 695 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 696 &dummy_read_1_table->mc_address, 697 &dummy_read_1_table->cpu_addr); 698 699 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 700 } 701 702 static int smu_smc_table_sw_init(struct smu_context *smu) 703 { 704 int ret; 705 706 /** 707 * Create smu_table structure, and init smc tables such as 708 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 709 */ 710 ret = smu_init_smc_tables(smu); 711 if (ret) { 712 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 713 return ret; 714 } 715 716 /** 717 * Create smu_power_context structure, and allocate smu_dpm_context and 718 * context size to fill the smu_power_context data. 719 */ 720 ret = smu_init_power(smu); 721 if (ret) { 722 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 723 return ret; 724 } 725 726 /* 727 * allocate vram bos to store smc table contents. 728 */ 729 ret = smu_init_fb_allocations(smu); 730 if (ret) 731 return ret; 732 733 ret = smu_alloc_memory_pool(smu); 734 if (ret) 735 return ret; 736 737 ret = smu_alloc_dummy_read_table(smu); 738 if (ret) 739 return ret; 740 741 ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c); 742 if (ret) 743 return ret; 744 745 return 0; 746 } 747 748 static int smu_smc_table_sw_fini(struct smu_context *smu) 749 { 750 int ret; 751 752 smu_i2c_fini(smu, &smu->adev->pm.smu_i2c); 753 754 smu_free_dummy_read_table(smu); 755 756 ret = smu_free_memory_pool(smu); 757 if (ret) 758 return ret; 759 760 ret = smu_fini_fb_allocations(smu); 761 if (ret) 762 return ret; 763 764 ret = smu_fini_power(smu); 765 if (ret) { 766 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 767 return ret; 768 } 769 770 ret = smu_fini_smc_tables(smu); 771 if (ret) { 772 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 773 return ret; 774 } 775 776 return 0; 777 } 778 779 static void smu_throttling_logging_work_fn(struct work_struct *work) 780 { 781 struct smu_context *smu = container_of(work, struct smu_context, 782 throttling_logging_work); 783 784 smu_log_thermal_throttling(smu); 785 } 786 787 static void smu_interrupt_work_fn(struct work_struct *work) 788 { 789 struct smu_context *smu = container_of(work, struct smu_context, 790 interrupt_work); 791 792 mutex_lock(&smu->mutex); 793 794 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 795 smu->ppt_funcs->interrupt_work(smu); 796 797 mutex_unlock(&smu->mutex); 798 } 799 800 static int smu_sw_init(void *handle) 801 { 802 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 803 struct smu_context *smu = &adev->smu; 804 int ret; 805 806 smu->pool_size = adev->pm.smu_prv_buffer_size; 807 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 808 mutex_init(&smu->smu_feature.mutex); 809 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 810 bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX); 811 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 812 813 mutex_init(&smu->sensor_lock); 814 mutex_init(&smu->metrics_lock); 815 mutex_init(&smu->message_lock); 816 817 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 818 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 819 atomic64_set(&smu->throttle_int_counter, 0); 820 smu->watermarks_bitmap = 0; 821 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 822 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 823 824 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 825 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 826 mutex_init(&smu->smu_power.power_gate.vcn_gate_lock); 827 mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock); 828 829 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 830 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 831 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 832 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 833 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 834 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 835 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 836 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 837 838 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 839 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 840 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 841 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 842 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 843 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 844 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 845 smu->display_config = &adev->pm.pm_display_cfg; 846 847 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 848 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 849 850 if (!amdgpu_sriov_vf(adev) || (adev->asic_type != CHIP_NAVI12)) { 851 ret = smu_init_microcode(smu); 852 if (ret) { 853 dev_err(adev->dev, "Failed to load smu firmware!\n"); 854 return ret; 855 } 856 } 857 858 ret = smu_smc_table_sw_init(smu); 859 if (ret) { 860 dev_err(adev->dev, "Failed to sw init smc table!\n"); 861 return ret; 862 } 863 864 ret = smu_register_irq_handler(smu); 865 if (ret) { 866 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 867 return ret; 868 } 869 870 return 0; 871 } 872 873 static int smu_sw_fini(void *handle) 874 { 875 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 876 struct smu_context *smu = &adev->smu; 877 int ret; 878 879 ret = smu_smc_table_sw_fini(smu); 880 if (ret) { 881 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 882 return ret; 883 } 884 885 smu_fini_microcode(smu); 886 887 return 0; 888 } 889 890 static int smu_get_thermal_temperature_range(struct smu_context *smu) 891 { 892 struct amdgpu_device *adev = smu->adev; 893 struct smu_temperature_range *range = 894 &smu->thermal_range; 895 int ret = 0; 896 897 if (!smu->ppt_funcs->get_thermal_temperature_range) 898 return 0; 899 900 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 901 if (ret) 902 return ret; 903 904 adev->pm.dpm.thermal.min_temp = range->min; 905 adev->pm.dpm.thermal.max_temp = range->max; 906 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 907 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 908 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 909 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 910 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 911 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 912 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 913 914 return ret; 915 } 916 917 static int smu_smc_hw_setup(struct smu_context *smu) 918 { 919 struct amdgpu_device *adev = smu->adev; 920 uint32_t pcie_gen = 0, pcie_width = 0; 921 int ret = 0; 922 923 if (adev->in_suspend && smu_is_dpm_running(smu)) { 924 dev_info(adev->dev, "dpm has been enabled\n"); 925 /* this is needed specifically */ 926 if ((adev->asic_type >= CHIP_SIENNA_CICHLID) && 927 (adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) 928 ret = smu_system_features_control(smu, true); 929 return ret; 930 } 931 932 ret = smu_init_display_count(smu, 0); 933 if (ret) { 934 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 935 return ret; 936 } 937 938 ret = smu_set_driver_table_location(smu); 939 if (ret) { 940 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 941 return ret; 942 } 943 944 /* 945 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 946 */ 947 ret = smu_set_tool_table_location(smu); 948 if (ret) { 949 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 950 return ret; 951 } 952 953 /* 954 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 955 * pool location. 956 */ 957 ret = smu_notify_memory_pool_location(smu); 958 if (ret) { 959 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 960 return ret; 961 } 962 963 /* smu_dump_pptable(smu); */ 964 /* 965 * Copy pptable bo in the vram to smc with SMU MSGs such as 966 * SetDriverDramAddr and TransferTableDram2Smu. 967 */ 968 ret = smu_write_pptable(smu); 969 if (ret) { 970 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 971 return ret; 972 } 973 974 /* issue Run*Btc msg */ 975 ret = smu_run_btc(smu); 976 if (ret) 977 return ret; 978 979 ret = smu_feature_set_allowed_mask(smu); 980 if (ret) { 981 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 982 return ret; 983 } 984 985 ret = smu_system_features_control(smu, true); 986 if (ret) { 987 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 988 return ret; 989 } 990 991 if (!smu_is_dpm_running(smu)) 992 dev_info(adev->dev, "dpm has been disabled\n"); 993 994 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 995 pcie_gen = 3; 996 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 997 pcie_gen = 2; 998 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 999 pcie_gen = 1; 1000 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1001 pcie_gen = 0; 1002 1003 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1004 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1005 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1006 */ 1007 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1008 pcie_width = 6; 1009 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1010 pcie_width = 5; 1011 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1012 pcie_width = 4; 1013 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1014 pcie_width = 3; 1015 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1016 pcie_width = 2; 1017 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1018 pcie_width = 1; 1019 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1020 if (ret) { 1021 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1022 return ret; 1023 } 1024 1025 ret = smu_get_thermal_temperature_range(smu); 1026 if (ret) { 1027 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1028 return ret; 1029 } 1030 1031 ret = smu_enable_thermal_alert(smu); 1032 if (ret) { 1033 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1034 return ret; 1035 } 1036 1037 /* 1038 * Set initialized values (get from vbios) to dpm tables context such as 1039 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1040 * type of clks. 1041 */ 1042 ret = smu_set_default_dpm_table(smu); 1043 if (ret) { 1044 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1045 return ret; 1046 } 1047 1048 ret = smu_notify_display_change(smu); 1049 if (ret) 1050 return ret; 1051 1052 /* 1053 * Set min deep sleep dce fclk with bootup value from vbios via 1054 * SetMinDeepSleepDcefclk MSG. 1055 */ 1056 ret = smu_set_min_dcef_deep_sleep(smu, 1057 smu->smu_table.boot_values.dcefclk / 100); 1058 if (ret) 1059 return ret; 1060 1061 return ret; 1062 } 1063 1064 static int smu_start_smc_engine(struct smu_context *smu) 1065 { 1066 struct amdgpu_device *adev = smu->adev; 1067 int ret = 0; 1068 1069 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1070 if (adev->asic_type < CHIP_NAVI10) { 1071 if (smu->ppt_funcs->load_microcode) { 1072 ret = smu->ppt_funcs->load_microcode(smu); 1073 if (ret) 1074 return ret; 1075 } 1076 } 1077 } 1078 1079 if (smu->ppt_funcs->check_fw_status) { 1080 ret = smu->ppt_funcs->check_fw_status(smu); 1081 if (ret) { 1082 dev_err(adev->dev, "SMC is not ready\n"); 1083 return ret; 1084 } 1085 } 1086 1087 /* 1088 * Send msg GetDriverIfVersion to check if the return value is equal 1089 * with DRIVER_IF_VERSION of smc header. 1090 */ 1091 ret = smu_check_fw_version(smu); 1092 if (ret) 1093 return ret; 1094 1095 return ret; 1096 } 1097 1098 static int smu_hw_init(void *handle) 1099 { 1100 int ret; 1101 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1102 struct smu_context *smu = &adev->smu; 1103 1104 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1105 smu->pm_enabled = false; 1106 return 0; 1107 } 1108 1109 ret = smu_start_smc_engine(smu); 1110 if (ret) { 1111 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1112 return ret; 1113 } 1114 1115 if (smu->is_apu) { 1116 smu_powergate_sdma(&adev->smu, false); 1117 smu_dpm_set_vcn_enable(smu, true); 1118 smu_dpm_set_jpeg_enable(smu, true); 1119 smu_set_gfx_cgpg(&adev->smu, true); 1120 } 1121 1122 if (!smu->pm_enabled) 1123 return 0; 1124 1125 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1126 ret = smu_get_vbios_bootup_values(smu); 1127 if (ret) { 1128 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1129 return ret; 1130 } 1131 1132 ret = smu_setup_pptable(smu); 1133 if (ret) { 1134 dev_err(adev->dev, "Failed to setup pptable!\n"); 1135 return ret; 1136 } 1137 1138 ret = smu_get_driver_allowed_feature_mask(smu); 1139 if (ret) 1140 return ret; 1141 1142 ret = smu_smc_hw_setup(smu); 1143 if (ret) { 1144 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1145 return ret; 1146 } 1147 1148 /* 1149 * Move maximum sustainable clock retrieving here considering 1150 * 1. It is not needed on resume(from S3). 1151 * 2. DAL settings come between .hw_init and .late_init of SMU. 1152 * And DAL needs to know the maximum sustainable clocks. Thus 1153 * it cannot be put in .late_init(). 1154 */ 1155 ret = smu_init_max_sustainable_clocks(smu); 1156 if (ret) { 1157 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1158 return ret; 1159 } 1160 1161 adev->pm.dpm_enabled = true; 1162 1163 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1164 1165 return 0; 1166 } 1167 1168 static int smu_disable_dpms(struct smu_context *smu) 1169 { 1170 struct amdgpu_device *adev = smu->adev; 1171 int ret = 0; 1172 bool use_baco = !smu->is_apu && 1173 ((amdgpu_in_reset(adev) && 1174 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1175 ((adev->in_runpm || adev->in_hibernate) && amdgpu_asic_supports_baco(adev))); 1176 1177 /* 1178 * For custom pptable uploading, skip the DPM features 1179 * disable process on Navi1x ASICs. 1180 * - As the gfx related features are under control of 1181 * RLC on those ASICs. RLC reinitialization will be 1182 * needed to reenable them. That will cost much more 1183 * efforts. 1184 * 1185 * - SMU firmware can handle the DPM reenablement 1186 * properly. 1187 */ 1188 if (smu->uploading_custom_pp_table && 1189 (adev->asic_type >= CHIP_NAVI10) && 1190 (adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) 1191 return 0; 1192 1193 /* 1194 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1195 * on BACO in. Driver involvement is unnecessary. 1196 */ 1197 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 1198 use_baco) 1199 return 0; 1200 1201 /* 1202 * For gpu reset, runpm and hibernation through BACO, 1203 * BACO feature has to be kept enabled. 1204 */ 1205 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1206 ret = smu_disable_all_features_with_exception(smu, 1207 SMU_FEATURE_BACO_BIT); 1208 if (ret) 1209 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1210 } else { 1211 ret = smu_system_features_control(smu, false); 1212 if (ret) 1213 dev_err(adev->dev, "Failed to disable smu features.\n"); 1214 } 1215 1216 if (adev->asic_type >= CHIP_NAVI10 && 1217 adev->gfx.rlc.funcs->stop) 1218 adev->gfx.rlc.funcs->stop(adev); 1219 1220 return ret; 1221 } 1222 1223 static int smu_smc_hw_cleanup(struct smu_context *smu) 1224 { 1225 struct amdgpu_device *adev = smu->adev; 1226 int ret = 0; 1227 1228 cancel_work_sync(&smu->throttling_logging_work); 1229 cancel_work_sync(&smu->interrupt_work); 1230 1231 ret = smu_disable_thermal_alert(smu); 1232 if (ret) { 1233 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1234 return ret; 1235 } 1236 1237 ret = smu_disable_dpms(smu); 1238 if (ret) { 1239 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1240 return ret; 1241 } 1242 1243 return 0; 1244 } 1245 1246 static int smu_hw_fini(void *handle) 1247 { 1248 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1249 struct smu_context *smu = &adev->smu; 1250 1251 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1252 return 0; 1253 1254 if (smu->is_apu) { 1255 smu_powergate_sdma(&adev->smu, true); 1256 smu_dpm_set_vcn_enable(smu, false); 1257 smu_dpm_set_jpeg_enable(smu, false); 1258 } 1259 1260 if (!smu->pm_enabled) 1261 return 0; 1262 1263 adev->pm.dpm_enabled = false; 1264 1265 return smu_smc_hw_cleanup(smu); 1266 } 1267 1268 int smu_reset(struct smu_context *smu) 1269 { 1270 struct amdgpu_device *adev = smu->adev; 1271 int ret; 1272 1273 amdgpu_gfx_off_ctrl(smu->adev, false); 1274 1275 ret = smu_hw_fini(adev); 1276 if (ret) 1277 return ret; 1278 1279 ret = smu_hw_init(adev); 1280 if (ret) 1281 return ret; 1282 1283 ret = smu_late_init(adev); 1284 if (ret) 1285 return ret; 1286 1287 amdgpu_gfx_off_ctrl(smu->adev, true); 1288 1289 return 0; 1290 } 1291 1292 static int smu_suspend(void *handle) 1293 { 1294 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1295 struct smu_context *smu = &adev->smu; 1296 int ret; 1297 1298 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1299 return 0; 1300 1301 if (!smu->pm_enabled) 1302 return 0; 1303 1304 adev->pm.dpm_enabled = false; 1305 1306 ret = smu_smc_hw_cleanup(smu); 1307 if (ret) 1308 return ret; 1309 1310 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1311 1312 if (smu->is_apu) 1313 smu_set_gfx_cgpg(&adev->smu, false); 1314 1315 return 0; 1316 } 1317 1318 static int smu_resume(void *handle) 1319 { 1320 int ret; 1321 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1322 struct smu_context *smu = &adev->smu; 1323 1324 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1325 return 0; 1326 1327 if (!smu->pm_enabled) 1328 return 0; 1329 1330 dev_info(adev->dev, "SMU is resuming...\n"); 1331 1332 ret = smu_start_smc_engine(smu); 1333 if (ret) { 1334 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1335 return ret; 1336 } 1337 1338 ret = smu_smc_hw_setup(smu); 1339 if (ret) { 1340 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1341 return ret; 1342 } 1343 1344 if (smu->is_apu) 1345 smu_set_gfx_cgpg(&adev->smu, true); 1346 1347 smu->disable_uclk_switch = 0; 1348 1349 adev->pm.dpm_enabled = true; 1350 1351 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1352 1353 return 0; 1354 } 1355 1356 int smu_display_configuration_change(struct smu_context *smu, 1357 const struct amd_pp_display_configuration *display_config) 1358 { 1359 int index = 0; 1360 int num_of_active_display = 0; 1361 1362 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1363 return -EOPNOTSUPP; 1364 1365 if (!display_config) 1366 return -EINVAL; 1367 1368 mutex_lock(&smu->mutex); 1369 1370 smu_set_min_dcef_deep_sleep(smu, 1371 display_config->min_dcef_deep_sleep_set_clk / 100); 1372 1373 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1374 if (display_config->displays[index].controller_id != 0) 1375 num_of_active_display++; 1376 } 1377 1378 mutex_unlock(&smu->mutex); 1379 1380 return 0; 1381 } 1382 1383 static int smu_set_clockgating_state(void *handle, 1384 enum amd_clockgating_state state) 1385 { 1386 return 0; 1387 } 1388 1389 static int smu_set_powergating_state(void *handle, 1390 enum amd_powergating_state state) 1391 { 1392 return 0; 1393 } 1394 1395 static int smu_enable_umd_pstate(void *handle, 1396 enum amd_dpm_forced_level *level) 1397 { 1398 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1399 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1400 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1401 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1402 1403 struct smu_context *smu = (struct smu_context*)(handle); 1404 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1405 1406 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1407 return -EINVAL; 1408 1409 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1410 /* enter umd pstate, save current level, disable gfx cg*/ 1411 if (*level & profile_mode_mask) { 1412 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1413 smu_dpm_ctx->enable_umd_pstate = true; 1414 smu_gpo_control(smu, false); 1415 amdgpu_device_ip_set_powergating_state(smu->adev, 1416 AMD_IP_BLOCK_TYPE_GFX, 1417 AMD_PG_STATE_UNGATE); 1418 amdgpu_device_ip_set_clockgating_state(smu->adev, 1419 AMD_IP_BLOCK_TYPE_GFX, 1420 AMD_CG_STATE_UNGATE); 1421 smu_gfx_ulv_control(smu, false); 1422 smu_deep_sleep_control(smu, false); 1423 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1424 } 1425 } else { 1426 /* exit umd pstate, restore level, enable gfx cg*/ 1427 if (!(*level & profile_mode_mask)) { 1428 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1429 *level = smu_dpm_ctx->saved_dpm_level; 1430 smu_dpm_ctx->enable_umd_pstate = false; 1431 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1432 smu_deep_sleep_control(smu, true); 1433 smu_gfx_ulv_control(smu, true); 1434 amdgpu_device_ip_set_clockgating_state(smu->adev, 1435 AMD_IP_BLOCK_TYPE_GFX, 1436 AMD_CG_STATE_GATE); 1437 amdgpu_device_ip_set_powergating_state(smu->adev, 1438 AMD_IP_BLOCK_TYPE_GFX, 1439 AMD_PG_STATE_GATE); 1440 smu_gpo_control(smu, true); 1441 } 1442 } 1443 1444 return 0; 1445 } 1446 1447 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1448 enum amd_dpm_forced_level level, 1449 bool skip_display_settings) 1450 { 1451 int ret = 0; 1452 int index = 0; 1453 long workload; 1454 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1455 1456 if (!skip_display_settings) { 1457 ret = smu_display_config_changed(smu); 1458 if (ret) { 1459 dev_err(smu->adev->dev, "Failed to change display config!"); 1460 return ret; 1461 } 1462 } 1463 1464 ret = smu_apply_clocks_adjust_rules(smu); 1465 if (ret) { 1466 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1467 return ret; 1468 } 1469 1470 if (!skip_display_settings) { 1471 ret = smu_notify_smc_display_config(smu); 1472 if (ret) { 1473 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1474 return ret; 1475 } 1476 } 1477 1478 if (smu_dpm_ctx->dpm_level != level) { 1479 ret = smu_asic_set_performance_level(smu, level); 1480 if (ret) { 1481 dev_err(smu->adev->dev, "Failed to set performance level!"); 1482 return ret; 1483 } 1484 1485 /* update the saved copy */ 1486 smu_dpm_ctx->dpm_level = level; 1487 } 1488 1489 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1490 index = fls(smu->workload_mask); 1491 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1492 workload = smu->workload_setting[index]; 1493 1494 if (smu->power_profile_mode != workload) 1495 smu_set_power_profile_mode(smu, &workload, 0, false); 1496 } 1497 1498 return ret; 1499 } 1500 1501 int smu_handle_task(struct smu_context *smu, 1502 enum amd_dpm_forced_level level, 1503 enum amd_pp_task task_id, 1504 bool lock_needed) 1505 { 1506 int ret = 0; 1507 1508 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1509 return -EOPNOTSUPP; 1510 1511 if (lock_needed) 1512 mutex_lock(&smu->mutex); 1513 1514 switch (task_id) { 1515 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1516 ret = smu_pre_display_config_changed(smu); 1517 if (ret) 1518 goto out; 1519 ret = smu_adjust_power_state_dynamic(smu, level, false); 1520 break; 1521 case AMD_PP_TASK_COMPLETE_INIT: 1522 case AMD_PP_TASK_READJUST_POWER_STATE: 1523 ret = smu_adjust_power_state_dynamic(smu, level, true); 1524 break; 1525 default: 1526 break; 1527 } 1528 1529 out: 1530 if (lock_needed) 1531 mutex_unlock(&smu->mutex); 1532 1533 return ret; 1534 } 1535 1536 int smu_switch_power_profile(struct smu_context *smu, 1537 enum PP_SMC_POWER_PROFILE type, 1538 bool en) 1539 { 1540 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1541 long workload; 1542 uint32_t index; 1543 1544 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1545 return -EOPNOTSUPP; 1546 1547 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1548 return -EINVAL; 1549 1550 mutex_lock(&smu->mutex); 1551 1552 if (!en) { 1553 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1554 index = fls(smu->workload_mask); 1555 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1556 workload = smu->workload_setting[index]; 1557 } else { 1558 smu->workload_mask |= (1 << smu->workload_prority[type]); 1559 index = fls(smu->workload_mask); 1560 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1561 workload = smu->workload_setting[index]; 1562 } 1563 1564 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1565 smu_set_power_profile_mode(smu, &workload, 0, false); 1566 1567 mutex_unlock(&smu->mutex); 1568 1569 return 0; 1570 } 1571 1572 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu) 1573 { 1574 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1575 enum amd_dpm_forced_level level; 1576 1577 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1578 return -EOPNOTSUPP; 1579 1580 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1581 return -EINVAL; 1582 1583 mutex_lock(&(smu->mutex)); 1584 level = smu_dpm_ctx->dpm_level; 1585 mutex_unlock(&(smu->mutex)); 1586 1587 return level; 1588 } 1589 1590 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level) 1591 { 1592 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1593 int ret = 0; 1594 1595 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1596 return -EOPNOTSUPP; 1597 1598 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1599 return -EINVAL; 1600 1601 mutex_lock(&smu->mutex); 1602 1603 ret = smu_enable_umd_pstate(smu, &level); 1604 if (ret) { 1605 mutex_unlock(&smu->mutex); 1606 return ret; 1607 } 1608 1609 ret = smu_handle_task(smu, level, 1610 AMD_PP_TASK_READJUST_POWER_STATE, 1611 false); 1612 1613 mutex_unlock(&smu->mutex); 1614 1615 return ret; 1616 } 1617 1618 int smu_set_display_count(struct smu_context *smu, uint32_t count) 1619 { 1620 int ret = 0; 1621 1622 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1623 return -EOPNOTSUPP; 1624 1625 mutex_lock(&smu->mutex); 1626 ret = smu_init_display_count(smu, count); 1627 mutex_unlock(&smu->mutex); 1628 1629 return ret; 1630 } 1631 1632 int smu_force_clk_levels(struct smu_context *smu, 1633 enum smu_clk_type clk_type, 1634 uint32_t mask) 1635 { 1636 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1637 int ret = 0; 1638 1639 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1640 return -EOPNOTSUPP; 1641 1642 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1643 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1644 return -EINVAL; 1645 } 1646 1647 mutex_lock(&smu->mutex); 1648 1649 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) 1650 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1651 1652 mutex_unlock(&smu->mutex); 1653 1654 return ret; 1655 } 1656 1657 /* 1658 * On system suspending or resetting, the dpm_enabled 1659 * flag will be cleared. So that those SMU services which 1660 * are not supported will be gated. 1661 * However, the mp1 state setting should still be granted 1662 * even if the dpm_enabled cleared. 1663 */ 1664 int smu_set_mp1_state(struct smu_context *smu, 1665 enum pp_mp1_state mp1_state) 1666 { 1667 uint16_t msg; 1668 int ret; 1669 1670 if (!smu->pm_enabled) 1671 return -EOPNOTSUPP; 1672 1673 mutex_lock(&smu->mutex); 1674 1675 switch (mp1_state) { 1676 case PP_MP1_STATE_SHUTDOWN: 1677 msg = SMU_MSG_PrepareMp1ForShutdown; 1678 break; 1679 case PP_MP1_STATE_UNLOAD: 1680 msg = SMU_MSG_PrepareMp1ForUnload; 1681 break; 1682 case PP_MP1_STATE_RESET: 1683 msg = SMU_MSG_PrepareMp1ForReset; 1684 break; 1685 case PP_MP1_STATE_NONE: 1686 default: 1687 mutex_unlock(&smu->mutex); 1688 return 0; 1689 } 1690 1691 ret = smu_send_smc_msg(smu, msg, NULL); 1692 /* some asics may not support those messages */ 1693 if (ret == -EINVAL) 1694 ret = 0; 1695 if (ret) 1696 dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n"); 1697 1698 mutex_unlock(&smu->mutex); 1699 1700 return ret; 1701 } 1702 1703 int smu_set_df_cstate(struct smu_context *smu, 1704 enum pp_df_cstate state) 1705 { 1706 int ret = 0; 1707 1708 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1709 return -EOPNOTSUPP; 1710 1711 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 1712 return 0; 1713 1714 mutex_lock(&smu->mutex); 1715 1716 ret = smu->ppt_funcs->set_df_cstate(smu, state); 1717 if (ret) 1718 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 1719 1720 mutex_unlock(&smu->mutex); 1721 1722 return ret; 1723 } 1724 1725 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 1726 { 1727 int ret = 0; 1728 1729 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1730 return -EOPNOTSUPP; 1731 1732 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 1733 return 0; 1734 1735 mutex_lock(&smu->mutex); 1736 1737 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 1738 if (ret) 1739 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 1740 1741 mutex_unlock(&smu->mutex); 1742 1743 return ret; 1744 } 1745 1746 int smu_write_watermarks_table(struct smu_context *smu) 1747 { 1748 int ret = 0; 1749 1750 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1751 return -EOPNOTSUPP; 1752 1753 mutex_lock(&smu->mutex); 1754 1755 ret = smu_set_watermarks_table(smu, NULL); 1756 1757 mutex_unlock(&smu->mutex); 1758 1759 return ret; 1760 } 1761 1762 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu, 1763 struct pp_smu_wm_range_sets *clock_ranges) 1764 { 1765 int ret = 0; 1766 1767 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1768 return -EOPNOTSUPP; 1769 1770 if (smu->disable_watermark) 1771 return 0; 1772 1773 mutex_lock(&smu->mutex); 1774 1775 ret = smu_set_watermarks_table(smu, clock_ranges); 1776 1777 mutex_unlock(&smu->mutex); 1778 1779 return ret; 1780 } 1781 1782 int smu_set_ac_dc(struct smu_context *smu) 1783 { 1784 int ret = 0; 1785 1786 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1787 return -EOPNOTSUPP; 1788 1789 /* controlled by firmware */ 1790 if (smu->dc_controlled_by_gpio) 1791 return 0; 1792 1793 mutex_lock(&smu->mutex); 1794 ret = smu_set_power_source(smu, 1795 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 1796 SMU_POWER_SOURCE_DC); 1797 if (ret) 1798 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 1799 smu->adev->pm.ac_power ? "AC" : "DC"); 1800 mutex_unlock(&smu->mutex); 1801 1802 return ret; 1803 } 1804 1805 const struct amd_ip_funcs smu_ip_funcs = { 1806 .name = "smu", 1807 .early_init = smu_early_init, 1808 .late_init = smu_late_init, 1809 .sw_init = smu_sw_init, 1810 .sw_fini = smu_sw_fini, 1811 .hw_init = smu_hw_init, 1812 .hw_fini = smu_hw_fini, 1813 .suspend = smu_suspend, 1814 .resume = smu_resume, 1815 .is_idle = NULL, 1816 .check_soft_reset = NULL, 1817 .wait_for_idle = NULL, 1818 .soft_reset = NULL, 1819 .set_clockgating_state = smu_set_clockgating_state, 1820 .set_powergating_state = smu_set_powergating_state, 1821 .enable_umd_pstate = smu_enable_umd_pstate, 1822 }; 1823 1824 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 1825 { 1826 .type = AMD_IP_BLOCK_TYPE_SMC, 1827 .major = 11, 1828 .minor = 0, 1829 .rev = 0, 1830 .funcs = &smu_ip_funcs, 1831 }; 1832 1833 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 1834 { 1835 .type = AMD_IP_BLOCK_TYPE_SMC, 1836 .major = 12, 1837 .minor = 0, 1838 .rev = 0, 1839 .funcs = &smu_ip_funcs, 1840 }; 1841 1842 int smu_load_microcode(struct smu_context *smu) 1843 { 1844 int ret = 0; 1845 1846 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1847 return -EOPNOTSUPP; 1848 1849 mutex_lock(&smu->mutex); 1850 1851 if (smu->ppt_funcs->load_microcode) 1852 ret = smu->ppt_funcs->load_microcode(smu); 1853 1854 mutex_unlock(&smu->mutex); 1855 1856 return ret; 1857 } 1858 1859 int smu_check_fw_status(struct smu_context *smu) 1860 { 1861 int ret = 0; 1862 1863 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1864 return -EOPNOTSUPP; 1865 1866 mutex_lock(&smu->mutex); 1867 1868 if (smu->ppt_funcs->check_fw_status) 1869 ret = smu->ppt_funcs->check_fw_status(smu); 1870 1871 mutex_unlock(&smu->mutex); 1872 1873 return ret; 1874 } 1875 1876 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 1877 { 1878 int ret = 0; 1879 1880 mutex_lock(&smu->mutex); 1881 1882 if (smu->ppt_funcs->set_gfx_cgpg) 1883 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 1884 1885 mutex_unlock(&smu->mutex); 1886 1887 return ret; 1888 } 1889 1890 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed) 1891 { 1892 int ret = 0; 1893 1894 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1895 return -EOPNOTSUPP; 1896 1897 mutex_lock(&smu->mutex); 1898 1899 if (smu->ppt_funcs->set_fan_speed_rpm) 1900 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 1901 1902 mutex_unlock(&smu->mutex); 1903 1904 return ret; 1905 } 1906 1907 int smu_get_power_limit(struct smu_context *smu, 1908 uint32_t *limit, 1909 bool max_setting) 1910 { 1911 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1912 return -EOPNOTSUPP; 1913 1914 mutex_lock(&smu->mutex); 1915 1916 *limit = (max_setting ? smu->max_power_limit : smu->current_power_limit); 1917 1918 mutex_unlock(&smu->mutex); 1919 1920 return 0; 1921 } 1922 1923 int smu_set_power_limit(struct smu_context *smu, uint32_t limit) 1924 { 1925 int ret = 0; 1926 1927 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1928 return -EOPNOTSUPP; 1929 1930 mutex_lock(&smu->mutex); 1931 1932 if (limit > smu->max_power_limit) { 1933 dev_err(smu->adev->dev, 1934 "New power limit (%d) is over the max allowed %d\n", 1935 limit, smu->max_power_limit); 1936 goto out; 1937 } 1938 1939 if (!limit) 1940 limit = smu->current_power_limit; 1941 1942 if (smu->ppt_funcs->set_power_limit) 1943 ret = smu->ppt_funcs->set_power_limit(smu, limit); 1944 1945 out: 1946 mutex_unlock(&smu->mutex); 1947 1948 return ret; 1949 } 1950 1951 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 1952 { 1953 int ret = 0; 1954 1955 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1956 return -EOPNOTSUPP; 1957 1958 mutex_lock(&smu->mutex); 1959 1960 if (smu->ppt_funcs->print_clk_levels) 1961 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 1962 1963 mutex_unlock(&smu->mutex); 1964 1965 return ret; 1966 } 1967 1968 int smu_od_edit_dpm_table(struct smu_context *smu, 1969 enum PP_OD_DPM_TABLE_COMMAND type, 1970 long *input, uint32_t size) 1971 { 1972 int ret = 0; 1973 1974 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1975 return -EOPNOTSUPP; 1976 1977 mutex_lock(&smu->mutex); 1978 1979 if (smu->ppt_funcs->od_edit_dpm_table) { 1980 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 1981 if (!ret && (type == PP_OD_COMMIT_DPM_TABLE)) 1982 ret = smu_handle_task(smu, 1983 smu->smu_dpm.dpm_level, 1984 AMD_PP_TASK_READJUST_POWER_STATE, 1985 false); 1986 } 1987 1988 mutex_unlock(&smu->mutex); 1989 1990 return ret; 1991 } 1992 1993 int smu_read_sensor(struct smu_context *smu, 1994 enum amd_pp_sensors sensor, 1995 void *data, uint32_t *size) 1996 { 1997 struct smu_umd_pstate_table *pstate_table = 1998 &smu->pstate_table; 1999 int ret = 0; 2000 2001 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2002 return -EOPNOTSUPP; 2003 2004 if (!data || !size) 2005 return -EINVAL; 2006 2007 mutex_lock(&smu->mutex); 2008 2009 if (smu->ppt_funcs->read_sensor) 2010 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2011 goto unlock; 2012 2013 switch (sensor) { 2014 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2015 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2016 *size = 4; 2017 break; 2018 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2019 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2020 *size = 4; 2021 break; 2022 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2023 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2); 2024 *size = 8; 2025 break; 2026 case AMDGPU_PP_SENSOR_UVD_POWER: 2027 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2028 *size = 4; 2029 break; 2030 case AMDGPU_PP_SENSOR_VCE_POWER: 2031 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2032 *size = 4; 2033 break; 2034 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2035 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2036 *size = 4; 2037 break; 2038 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2039 *(uint32_t *)data = 0; 2040 *size = 4; 2041 break; 2042 default: 2043 *size = 0; 2044 ret = -EOPNOTSUPP; 2045 break; 2046 } 2047 2048 unlock: 2049 mutex_unlock(&smu->mutex); 2050 2051 return ret; 2052 } 2053 2054 int smu_get_power_profile_mode(struct smu_context *smu, char *buf) 2055 { 2056 int ret = 0; 2057 2058 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2059 return -EOPNOTSUPP; 2060 2061 mutex_lock(&smu->mutex); 2062 2063 if (smu->ppt_funcs->get_power_profile_mode) 2064 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf); 2065 2066 mutex_unlock(&smu->mutex); 2067 2068 return ret; 2069 } 2070 2071 int smu_set_power_profile_mode(struct smu_context *smu, 2072 long *param, 2073 uint32_t param_size, 2074 bool lock_needed) 2075 { 2076 int ret = 0; 2077 2078 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2079 return -EOPNOTSUPP; 2080 2081 if (lock_needed) 2082 mutex_lock(&smu->mutex); 2083 2084 if (smu->ppt_funcs->set_power_profile_mode) 2085 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 2086 2087 if (lock_needed) 2088 mutex_unlock(&smu->mutex); 2089 2090 return ret; 2091 } 2092 2093 2094 int smu_get_fan_control_mode(struct smu_context *smu) 2095 { 2096 int ret = 0; 2097 2098 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2099 return -EOPNOTSUPP; 2100 2101 mutex_lock(&smu->mutex); 2102 2103 if (smu->ppt_funcs->get_fan_control_mode) 2104 ret = smu->ppt_funcs->get_fan_control_mode(smu); 2105 2106 mutex_unlock(&smu->mutex); 2107 2108 return ret; 2109 } 2110 2111 int smu_set_fan_control_mode(struct smu_context *smu, int value) 2112 { 2113 int ret = 0; 2114 2115 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2116 return -EOPNOTSUPP; 2117 2118 mutex_lock(&smu->mutex); 2119 2120 if (smu->ppt_funcs->set_fan_control_mode) 2121 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2122 2123 mutex_unlock(&smu->mutex); 2124 2125 return ret; 2126 } 2127 2128 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed) 2129 { 2130 int ret = 0; 2131 uint32_t percent; 2132 uint32_t current_rpm; 2133 2134 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2135 return -EOPNOTSUPP; 2136 2137 mutex_lock(&smu->mutex); 2138 2139 if (smu->ppt_funcs->get_fan_speed_rpm) { 2140 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, ¤t_rpm); 2141 if (!ret) { 2142 percent = current_rpm * 100 / smu->fan_max_rpm; 2143 *speed = percent > 100 ? 100 : percent; 2144 } 2145 } 2146 2147 mutex_unlock(&smu->mutex); 2148 2149 2150 return ret; 2151 } 2152 2153 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed) 2154 { 2155 int ret = 0; 2156 uint32_t rpm; 2157 2158 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2159 return -EOPNOTSUPP; 2160 2161 mutex_lock(&smu->mutex); 2162 2163 if (smu->ppt_funcs->set_fan_speed_rpm) { 2164 if (speed > 100) 2165 speed = 100; 2166 rpm = speed * smu->fan_max_rpm / 100; 2167 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, rpm); 2168 } 2169 2170 mutex_unlock(&smu->mutex); 2171 2172 return ret; 2173 } 2174 2175 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed) 2176 { 2177 int ret = 0; 2178 2179 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2180 return -EOPNOTSUPP; 2181 2182 mutex_lock(&smu->mutex); 2183 2184 if (smu->ppt_funcs->get_fan_speed_rpm) 2185 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 2186 2187 mutex_unlock(&smu->mutex); 2188 2189 return ret; 2190 } 2191 2192 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk) 2193 { 2194 int ret = 0; 2195 2196 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2197 return -EOPNOTSUPP; 2198 2199 mutex_lock(&smu->mutex); 2200 2201 ret = smu_set_min_dcef_deep_sleep(smu, clk); 2202 2203 mutex_unlock(&smu->mutex); 2204 2205 return ret; 2206 } 2207 2208 int smu_get_clock_by_type_with_latency(struct smu_context *smu, 2209 enum smu_clk_type clk_type, 2210 struct pp_clock_levels_with_latency *clocks) 2211 { 2212 int ret = 0; 2213 2214 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2215 return -EOPNOTSUPP; 2216 2217 mutex_lock(&smu->mutex); 2218 2219 if (smu->ppt_funcs->get_clock_by_type_with_latency) 2220 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2221 2222 mutex_unlock(&smu->mutex); 2223 2224 return ret; 2225 } 2226 2227 int smu_display_clock_voltage_request(struct smu_context *smu, 2228 struct pp_display_clock_request *clock_req) 2229 { 2230 int ret = 0; 2231 2232 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2233 return -EOPNOTSUPP; 2234 2235 mutex_lock(&smu->mutex); 2236 2237 if (smu->ppt_funcs->display_clock_voltage_request) 2238 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2239 2240 mutex_unlock(&smu->mutex); 2241 2242 return ret; 2243 } 2244 2245 2246 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch) 2247 { 2248 int ret = -EINVAL; 2249 2250 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2251 return -EOPNOTSUPP; 2252 2253 mutex_lock(&smu->mutex); 2254 2255 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2256 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2257 2258 mutex_unlock(&smu->mutex); 2259 2260 return ret; 2261 } 2262 2263 int smu_set_xgmi_pstate(struct smu_context *smu, 2264 uint32_t pstate) 2265 { 2266 int ret = 0; 2267 2268 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2269 return -EOPNOTSUPP; 2270 2271 mutex_lock(&smu->mutex); 2272 2273 if (smu->ppt_funcs->set_xgmi_pstate) 2274 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2275 2276 mutex_unlock(&smu->mutex); 2277 2278 if(ret) 2279 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2280 2281 return ret; 2282 } 2283 2284 int smu_set_azalia_d3_pme(struct smu_context *smu) 2285 { 2286 int ret = 0; 2287 2288 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2289 return -EOPNOTSUPP; 2290 2291 mutex_lock(&smu->mutex); 2292 2293 if (smu->ppt_funcs->set_azalia_d3_pme) 2294 ret = smu->ppt_funcs->set_azalia_d3_pme(smu); 2295 2296 mutex_unlock(&smu->mutex); 2297 2298 return ret; 2299 } 2300 2301 /* 2302 * On system suspending or resetting, the dpm_enabled 2303 * flag will be cleared. So that those SMU services which 2304 * are not supported will be gated. 2305 * 2306 * However, the baco/mode1 reset should still be granted 2307 * as they are still supported and necessary. 2308 */ 2309 bool smu_baco_is_support(struct smu_context *smu) 2310 { 2311 bool ret = false; 2312 2313 if (!smu->pm_enabled) 2314 return false; 2315 2316 mutex_lock(&smu->mutex); 2317 2318 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2319 ret = smu->ppt_funcs->baco_is_support(smu); 2320 2321 mutex_unlock(&smu->mutex); 2322 2323 return ret; 2324 } 2325 2326 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state) 2327 { 2328 if (smu->ppt_funcs->baco_get_state) 2329 return -EINVAL; 2330 2331 mutex_lock(&smu->mutex); 2332 *state = smu->ppt_funcs->baco_get_state(smu); 2333 mutex_unlock(&smu->mutex); 2334 2335 return 0; 2336 } 2337 2338 int smu_baco_enter(struct smu_context *smu) 2339 { 2340 int ret = 0; 2341 2342 if (!smu->pm_enabled) 2343 return -EOPNOTSUPP; 2344 2345 mutex_lock(&smu->mutex); 2346 2347 if (smu->ppt_funcs->baco_enter) 2348 ret = smu->ppt_funcs->baco_enter(smu); 2349 2350 mutex_unlock(&smu->mutex); 2351 2352 if (ret) 2353 dev_err(smu->adev->dev, "Failed to enter BACO state!\n"); 2354 2355 return ret; 2356 } 2357 2358 int smu_baco_exit(struct smu_context *smu) 2359 { 2360 int ret = 0; 2361 2362 if (!smu->pm_enabled) 2363 return -EOPNOTSUPP; 2364 2365 mutex_lock(&smu->mutex); 2366 2367 if (smu->ppt_funcs->baco_exit) 2368 ret = smu->ppt_funcs->baco_exit(smu); 2369 2370 mutex_unlock(&smu->mutex); 2371 2372 if (ret) 2373 dev_err(smu->adev->dev, "Failed to exit BACO state!\n"); 2374 2375 return ret; 2376 } 2377 2378 bool smu_mode1_reset_is_support(struct smu_context *smu) 2379 { 2380 bool ret = false; 2381 2382 if (!smu->pm_enabled) 2383 return false; 2384 2385 mutex_lock(&smu->mutex); 2386 2387 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2388 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2389 2390 mutex_unlock(&smu->mutex); 2391 2392 return ret; 2393 } 2394 2395 int smu_mode1_reset(struct smu_context *smu) 2396 { 2397 int ret = 0; 2398 2399 if (!smu->pm_enabled) 2400 return -EOPNOTSUPP; 2401 2402 mutex_lock(&smu->mutex); 2403 2404 if (smu->ppt_funcs->mode1_reset) 2405 ret = smu->ppt_funcs->mode1_reset(smu); 2406 2407 mutex_unlock(&smu->mutex); 2408 2409 return ret; 2410 } 2411 2412 int smu_mode2_reset(struct smu_context *smu) 2413 { 2414 int ret = 0; 2415 2416 if (!smu->pm_enabled) 2417 return -EOPNOTSUPP; 2418 2419 mutex_lock(&smu->mutex); 2420 2421 if (smu->ppt_funcs->mode2_reset) 2422 ret = smu->ppt_funcs->mode2_reset(smu); 2423 2424 mutex_unlock(&smu->mutex); 2425 2426 if (ret) 2427 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2428 2429 return ret; 2430 } 2431 2432 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu, 2433 struct pp_smu_nv_clock_table *max_clocks) 2434 { 2435 int ret = 0; 2436 2437 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2438 return -EOPNOTSUPP; 2439 2440 mutex_lock(&smu->mutex); 2441 2442 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2443 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2444 2445 mutex_unlock(&smu->mutex); 2446 2447 return ret; 2448 } 2449 2450 int smu_get_uclk_dpm_states(struct smu_context *smu, 2451 unsigned int *clock_values_in_khz, 2452 unsigned int *num_states) 2453 { 2454 int ret = 0; 2455 2456 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2457 return -EOPNOTSUPP; 2458 2459 mutex_lock(&smu->mutex); 2460 2461 if (smu->ppt_funcs->get_uclk_dpm_states) 2462 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2463 2464 mutex_unlock(&smu->mutex); 2465 2466 return ret; 2467 } 2468 2469 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu) 2470 { 2471 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2472 2473 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2474 return -EOPNOTSUPP; 2475 2476 mutex_lock(&smu->mutex); 2477 2478 if (smu->ppt_funcs->get_current_power_state) 2479 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2480 2481 mutex_unlock(&smu->mutex); 2482 2483 return pm_state; 2484 } 2485 2486 int smu_get_dpm_clock_table(struct smu_context *smu, 2487 struct dpm_clocks *clock_table) 2488 { 2489 int ret = 0; 2490 2491 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2492 return -EOPNOTSUPP; 2493 2494 mutex_lock(&smu->mutex); 2495 2496 if (smu->ppt_funcs->get_dpm_clock_table) 2497 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 2498 2499 mutex_unlock(&smu->mutex); 2500 2501 return ret; 2502 } 2503 2504 ssize_t smu_sys_get_gpu_metrics(struct smu_context *smu, 2505 void **table) 2506 { 2507 ssize_t size; 2508 2509 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2510 return -EOPNOTSUPP; 2511 2512 if (!smu->ppt_funcs->get_gpu_metrics) 2513 return -EOPNOTSUPP; 2514 2515 mutex_lock(&smu->mutex); 2516 2517 size = smu->ppt_funcs->get_gpu_metrics(smu, table); 2518 2519 mutex_unlock(&smu->mutex); 2520 2521 return size; 2522 } 2523 2524 int smu_enable_mgpu_fan_boost(struct smu_context *smu) 2525 { 2526 int ret = 0; 2527 2528 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2529 return -EOPNOTSUPP; 2530 2531 mutex_lock(&smu->mutex); 2532 2533 if (smu->ppt_funcs->enable_mgpu_fan_boost) 2534 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 2535 2536 mutex_unlock(&smu->mutex); 2537 2538 return ret; 2539 } 2540 2541 int smu_gfx_state_change_set(struct smu_context *smu, uint32_t state) 2542 { 2543 int ret = 0; 2544 2545 mutex_lock(&smu->mutex); 2546 if (smu->ppt_funcs->gfx_state_change_set) 2547 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 2548 mutex_unlock(&smu->mutex); 2549 2550 return ret; 2551 } 2552