1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "aldebaran_ppt.h" 38 #include "yellow_carp_ppt.h" 39 #include "cyan_skillfish_ppt.h" 40 #include "amd_pcie.h" 41 42 /* 43 * DO NOT use these for err/warn/info/debug messages. 44 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 45 * They are more MGPU friendly. 46 */ 47 #undef pr_err 48 #undef pr_warn 49 #undef pr_info 50 #undef pr_debug 51 52 static const struct amd_pm_funcs swsmu_pm_funcs; 53 static int smu_force_smuclk_levels(struct smu_context *smu, 54 enum smu_clk_type clk_type, 55 uint32_t mask); 56 static int smu_handle_task(struct smu_context *smu, 57 enum amd_dpm_forced_level level, 58 enum amd_pp_task task_id, 59 bool lock_needed); 60 static int smu_reset(struct smu_context *smu); 61 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 62 static int smu_set_fan_control_mode(struct smu_context *smu, int value); 63 static int smu_set_power_limit(void *handle, uint32_t limit); 64 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 65 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 66 67 static int smu_sys_get_pp_feature_mask(void *handle, 68 char *buf) 69 { 70 struct smu_context *smu = handle; 71 int size = 0; 72 73 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 74 return -EOPNOTSUPP; 75 76 mutex_lock(&smu->mutex); 77 78 size = smu_get_pp_feature_mask(smu, buf); 79 80 mutex_unlock(&smu->mutex); 81 82 return size; 83 } 84 85 static int smu_sys_set_pp_feature_mask(void *handle, 86 uint64_t new_mask) 87 { 88 struct smu_context *smu = handle; 89 int ret = 0; 90 91 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 92 return -EOPNOTSUPP; 93 94 mutex_lock(&smu->mutex); 95 96 ret = smu_set_pp_feature_mask(smu, new_mask); 97 98 mutex_unlock(&smu->mutex); 99 100 return ret; 101 } 102 103 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) 104 { 105 int ret = 0; 106 struct smu_context *smu = &adev->smu; 107 108 if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status) 109 *value = smu_get_gfx_off_status(smu); 110 else 111 ret = -EINVAL; 112 113 return ret; 114 } 115 116 int smu_set_soft_freq_range(struct smu_context *smu, 117 enum smu_clk_type clk_type, 118 uint32_t min, 119 uint32_t max) 120 { 121 int ret = 0; 122 123 mutex_lock(&smu->mutex); 124 125 if (smu->ppt_funcs->set_soft_freq_limited_range) 126 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 127 clk_type, 128 min, 129 max); 130 131 mutex_unlock(&smu->mutex); 132 133 return ret; 134 } 135 136 int smu_get_dpm_freq_range(struct smu_context *smu, 137 enum smu_clk_type clk_type, 138 uint32_t *min, 139 uint32_t *max) 140 { 141 int ret = 0; 142 143 if (!min && !max) 144 return -EINVAL; 145 146 mutex_lock(&smu->mutex); 147 148 if (smu->ppt_funcs->get_dpm_ultimate_freq) 149 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 150 clk_type, 151 min, 152 max); 153 154 mutex_unlock(&smu->mutex); 155 156 return ret; 157 } 158 159 static u32 smu_get_mclk(void *handle, bool low) 160 { 161 struct smu_context *smu = handle; 162 uint32_t clk_freq; 163 int ret = 0; 164 165 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 166 low ? &clk_freq : NULL, 167 !low ? &clk_freq : NULL); 168 if (ret) 169 return 0; 170 return clk_freq * 100; 171 } 172 173 static u32 smu_get_sclk(void *handle, bool low) 174 { 175 struct smu_context *smu = handle; 176 uint32_t clk_freq; 177 int ret = 0; 178 179 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 180 low ? &clk_freq : NULL, 181 !low ? &clk_freq : NULL); 182 if (ret) 183 return 0; 184 return clk_freq * 100; 185 } 186 187 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu, 188 bool enable) 189 { 190 struct smu_power_context *smu_power = &smu->smu_power; 191 struct smu_power_gate *power_gate = &smu_power->power_gate; 192 int ret = 0; 193 194 if (!smu->ppt_funcs->dpm_set_vcn_enable) 195 return 0; 196 197 if (atomic_read(&power_gate->vcn_gated) ^ enable) 198 return 0; 199 200 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 201 if (!ret) 202 atomic_set(&power_gate->vcn_gated, !enable); 203 204 return ret; 205 } 206 207 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 208 bool enable) 209 { 210 struct smu_power_context *smu_power = &smu->smu_power; 211 struct smu_power_gate *power_gate = &smu_power->power_gate; 212 int ret = 0; 213 214 mutex_lock(&power_gate->vcn_gate_lock); 215 216 ret = smu_dpm_set_vcn_enable_locked(smu, enable); 217 218 mutex_unlock(&power_gate->vcn_gate_lock); 219 220 return ret; 221 } 222 223 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu, 224 bool enable) 225 { 226 struct smu_power_context *smu_power = &smu->smu_power; 227 struct smu_power_gate *power_gate = &smu_power->power_gate; 228 int ret = 0; 229 230 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 231 return 0; 232 233 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 234 return 0; 235 236 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 237 if (!ret) 238 atomic_set(&power_gate->jpeg_gated, !enable); 239 240 return ret; 241 } 242 243 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 244 bool enable) 245 { 246 struct smu_power_context *smu_power = &smu->smu_power; 247 struct smu_power_gate *power_gate = &smu_power->power_gate; 248 int ret = 0; 249 250 mutex_lock(&power_gate->jpeg_gate_lock); 251 252 ret = smu_dpm_set_jpeg_enable_locked(smu, enable); 253 254 mutex_unlock(&power_gate->jpeg_gate_lock); 255 256 return ret; 257 } 258 259 /** 260 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 261 * 262 * @handle: smu_context pointer 263 * @block_type: the IP block to power gate/ungate 264 * @gate: to power gate if true, ungate otherwise 265 * 266 * This API uses no smu->mutex lock protection due to: 267 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 268 * This is guarded to be race condition free by the caller. 269 * 2. Or get called on user setting request of power_dpm_force_performance_level. 270 * Under this case, the smu->mutex lock protection is already enforced on 271 * the parent API smu_force_performance_level of the call path. 272 */ 273 static int smu_dpm_set_power_gate(void *handle, 274 uint32_t block_type, 275 bool gate) 276 { 277 struct smu_context *smu = handle; 278 int ret = 0; 279 280 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 281 return -EOPNOTSUPP; 282 283 switch (block_type) { 284 /* 285 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 286 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 287 */ 288 case AMD_IP_BLOCK_TYPE_UVD: 289 case AMD_IP_BLOCK_TYPE_VCN: 290 ret = smu_dpm_set_vcn_enable(smu, !gate); 291 if (ret) 292 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 293 gate ? "gate" : "ungate"); 294 break; 295 case AMD_IP_BLOCK_TYPE_GFX: 296 ret = smu_gfx_off_control(smu, gate); 297 if (ret) 298 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 299 gate ? "enable" : "disable"); 300 break; 301 case AMD_IP_BLOCK_TYPE_SDMA: 302 ret = smu_powergate_sdma(smu, gate); 303 if (ret) 304 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 305 gate ? "gate" : "ungate"); 306 break; 307 case AMD_IP_BLOCK_TYPE_JPEG: 308 ret = smu_dpm_set_jpeg_enable(smu, !gate); 309 if (ret) 310 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 311 gate ? "gate" : "ungate"); 312 break; 313 default: 314 dev_err(smu->adev->dev, "Unsupported block type!\n"); 315 return -EINVAL; 316 } 317 318 return ret; 319 } 320 321 /** 322 * smu_set_user_clk_dependencies - set user profile clock dependencies 323 * 324 * @smu: smu_context pointer 325 * @clk: enum smu_clk_type type 326 * 327 * Enable/Disable the clock dependency for the @clk type. 328 */ 329 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 330 { 331 if (smu->adev->in_suspend) 332 return; 333 334 if (clk == SMU_MCLK) { 335 smu->user_dpm_profile.clk_dependency = 0; 336 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 337 } else if (clk == SMU_FCLK) { 338 /* MCLK takes precedence over FCLK */ 339 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 340 return; 341 342 smu->user_dpm_profile.clk_dependency = 0; 343 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 344 } else if (clk == SMU_SOCCLK) { 345 /* MCLK takes precedence over SOCCLK */ 346 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 347 return; 348 349 smu->user_dpm_profile.clk_dependency = 0; 350 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 351 } else 352 /* Add clk dependencies here, if any */ 353 return; 354 } 355 356 /** 357 * smu_restore_dpm_user_profile - reinstate user dpm profile 358 * 359 * @smu: smu_context pointer 360 * 361 * Restore the saved user power configurations include power limit, 362 * clock frequencies, fan control mode and fan speed. 363 */ 364 static void smu_restore_dpm_user_profile(struct smu_context *smu) 365 { 366 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 367 int ret = 0; 368 369 if (!smu->adev->in_suspend) 370 return; 371 372 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 373 return; 374 375 /* Enable restore flag */ 376 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 377 378 /* set the user dpm power limit */ 379 if (smu->user_dpm_profile.power_limit) { 380 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 381 if (ret) 382 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 383 } 384 385 /* set the user dpm clock configurations */ 386 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 387 enum smu_clk_type clk_type; 388 389 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 390 /* 391 * Iterate over smu clk type and force the saved user clk 392 * configs, skip if clock dependency is enabled 393 */ 394 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 395 smu->user_dpm_profile.clk_mask[clk_type]) { 396 ret = smu_force_smuclk_levels(smu, clk_type, 397 smu->user_dpm_profile.clk_mask[clk_type]); 398 if (ret) 399 dev_err(smu->adev->dev, 400 "Failed to set clock type = %d\n", clk_type); 401 } 402 } 403 } 404 405 /* set the user dpm fan configurations */ 406 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 407 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 408 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 409 if (ret) { 410 smu->user_dpm_profile.fan_speed_pwm = 0; 411 smu->user_dpm_profile.fan_speed_rpm = 0; 412 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 413 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 414 } 415 416 if (smu->user_dpm_profile.fan_speed_pwm) { 417 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 418 if (ret) 419 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 420 } 421 422 if (smu->user_dpm_profile.fan_speed_rpm) { 423 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 424 if (ret) 425 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 426 } 427 } 428 429 /* Restore user customized OD settings */ 430 if (smu->user_dpm_profile.user_od) { 431 if (smu->ppt_funcs->restore_user_od_settings) { 432 ret = smu->ppt_funcs->restore_user_od_settings(smu); 433 if (ret) 434 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 435 } 436 } 437 438 /* Disable restore flag */ 439 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 440 } 441 442 static int smu_get_power_num_states(void *handle, 443 struct pp_states_info *state_info) 444 { 445 if (!state_info) 446 return -EINVAL; 447 448 /* not support power state */ 449 memset(state_info, 0, sizeof(struct pp_states_info)); 450 state_info->nums = 1; 451 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 452 453 return 0; 454 } 455 456 bool is_support_sw_smu(struct amdgpu_device *adev) 457 { 458 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 459 if (adev->asic_type == CHIP_VEGA20) 460 return false; 461 462 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0)) 463 return true; 464 465 return false; 466 } 467 468 bool is_support_cclk_dpm(struct amdgpu_device *adev) 469 { 470 struct smu_context *smu = &adev->smu; 471 472 if (!is_support_sw_smu(adev)) 473 return false; 474 475 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 476 return false; 477 478 return true; 479 } 480 481 482 static int smu_sys_get_pp_table(void *handle, 483 char **table) 484 { 485 struct smu_context *smu = handle; 486 struct smu_table_context *smu_table = &smu->smu_table; 487 uint32_t powerplay_table_size; 488 489 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 490 return -EOPNOTSUPP; 491 492 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 493 return -EINVAL; 494 495 mutex_lock(&smu->mutex); 496 497 if (smu_table->hardcode_pptable) 498 *table = smu_table->hardcode_pptable; 499 else 500 *table = smu_table->power_play_table; 501 502 powerplay_table_size = smu_table->power_play_table_size; 503 504 mutex_unlock(&smu->mutex); 505 506 return powerplay_table_size; 507 } 508 509 static int smu_sys_set_pp_table(void *handle, 510 const char *buf, 511 size_t size) 512 { 513 struct smu_context *smu = handle; 514 struct smu_table_context *smu_table = &smu->smu_table; 515 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 516 int ret = 0; 517 518 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 519 return -EOPNOTSUPP; 520 521 if (header->usStructureSize != size) { 522 dev_err(smu->adev->dev, "pp table size not matched !\n"); 523 return -EIO; 524 } 525 526 mutex_lock(&smu->mutex); 527 if (!smu_table->hardcode_pptable) 528 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 529 if (!smu_table->hardcode_pptable) { 530 ret = -ENOMEM; 531 goto failed; 532 } 533 534 memcpy(smu_table->hardcode_pptable, buf, size); 535 smu_table->power_play_table = smu_table->hardcode_pptable; 536 smu_table->power_play_table_size = size; 537 538 /* 539 * Special hw_fini action(for Navi1x, the DPMs disablement will be 540 * skipped) may be needed for custom pptable uploading. 541 */ 542 smu->uploading_custom_pp_table = true; 543 544 ret = smu_reset(smu); 545 if (ret) 546 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 547 548 smu->uploading_custom_pp_table = false; 549 550 failed: 551 mutex_unlock(&smu->mutex); 552 return ret; 553 } 554 555 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 556 { 557 struct smu_feature *feature = &smu->smu_feature; 558 int ret = 0; 559 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 560 561 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 562 563 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 564 SMU_FEATURE_MAX/32); 565 if (ret) 566 return ret; 567 568 bitmap_or(feature->allowed, feature->allowed, 569 (unsigned long *)allowed_feature_mask, 570 feature->feature_num); 571 572 return ret; 573 } 574 575 static int smu_set_funcs(struct amdgpu_device *adev) 576 { 577 struct smu_context *smu = &adev->smu; 578 579 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 580 smu->od_enabled = true; 581 582 switch (adev->ip_versions[MP1_HWIP][0]) { 583 case IP_VERSION(11, 0, 0): 584 case IP_VERSION(11, 0, 5): 585 case IP_VERSION(11, 0, 9): 586 navi10_set_ppt_funcs(smu); 587 break; 588 case IP_VERSION(11, 0, 7): 589 case IP_VERSION(11, 0, 11): 590 case IP_VERSION(11, 0, 12): 591 case IP_VERSION(11, 0, 13): 592 sienna_cichlid_set_ppt_funcs(smu); 593 break; 594 case IP_VERSION(12, 0, 0): 595 case IP_VERSION(12, 0, 1): 596 renoir_set_ppt_funcs(smu); 597 break; 598 case IP_VERSION(11, 5, 0): 599 vangogh_set_ppt_funcs(smu); 600 break; 601 case IP_VERSION(13, 0, 1): 602 case IP_VERSION(13, 0, 3): 603 yellow_carp_set_ppt_funcs(smu); 604 break; 605 case IP_VERSION(11, 0, 8): 606 cyan_skillfish_set_ppt_funcs(smu); 607 break; 608 case IP_VERSION(11, 0, 2): 609 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 610 arcturus_set_ppt_funcs(smu); 611 /* OD is not supported on Arcturus */ 612 smu->od_enabled =false; 613 break; 614 case IP_VERSION(13, 0, 2): 615 aldebaran_set_ppt_funcs(smu); 616 /* Enable pp_od_clk_voltage node */ 617 smu->od_enabled = true; 618 break; 619 default: 620 return -EINVAL; 621 } 622 623 return 0; 624 } 625 626 static int smu_early_init(void *handle) 627 { 628 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 629 struct smu_context *smu = &adev->smu; 630 631 smu->adev = adev; 632 smu->pm_enabled = !!amdgpu_dpm; 633 smu->is_apu = false; 634 mutex_init(&smu->mutex); 635 mutex_init(&smu->smu_baco.mutex); 636 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 637 smu->smu_baco.platform_support = false; 638 smu->user_dpm_profile.fan_mode = -1; 639 640 adev->powerplay.pp_handle = smu; 641 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 642 643 return smu_set_funcs(adev); 644 } 645 646 static int smu_set_default_dpm_table(struct smu_context *smu) 647 { 648 struct smu_power_context *smu_power = &smu->smu_power; 649 struct smu_power_gate *power_gate = &smu_power->power_gate; 650 int vcn_gate, jpeg_gate; 651 int ret = 0; 652 653 if (!smu->ppt_funcs->set_default_dpm_table) 654 return 0; 655 656 mutex_lock(&power_gate->vcn_gate_lock); 657 mutex_lock(&power_gate->jpeg_gate_lock); 658 659 vcn_gate = atomic_read(&power_gate->vcn_gated); 660 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 661 662 ret = smu_dpm_set_vcn_enable_locked(smu, true); 663 if (ret) 664 goto err0_out; 665 666 ret = smu_dpm_set_jpeg_enable_locked(smu, true); 667 if (ret) 668 goto err1_out; 669 670 ret = smu->ppt_funcs->set_default_dpm_table(smu); 671 if (ret) 672 dev_err(smu->adev->dev, 673 "Failed to setup default dpm clock tables!\n"); 674 675 smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate); 676 err1_out: 677 smu_dpm_set_vcn_enable_locked(smu, !vcn_gate); 678 err0_out: 679 mutex_unlock(&power_gate->jpeg_gate_lock); 680 mutex_unlock(&power_gate->vcn_gate_lock); 681 682 return ret; 683 } 684 685 686 static int smu_late_init(void *handle) 687 { 688 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 689 struct smu_context *smu = &adev->smu; 690 int ret = 0; 691 692 smu_set_fine_grain_gfx_freq_parameters(smu); 693 694 if (!smu->pm_enabled) 695 return 0; 696 697 ret = smu_post_init(smu); 698 if (ret) { 699 dev_err(adev->dev, "Failed to post smu init!\n"); 700 return ret; 701 } 702 703 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || 704 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) 705 return 0; 706 707 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 708 ret = smu_set_default_od_settings(smu); 709 if (ret) { 710 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 711 return ret; 712 } 713 } 714 715 ret = smu_populate_umd_state_clk(smu); 716 if (ret) { 717 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 718 return ret; 719 } 720 721 ret = smu_get_asic_power_limits(smu, 722 &smu->current_power_limit, 723 &smu->default_power_limit, 724 &smu->max_power_limit); 725 if (ret) { 726 dev_err(adev->dev, "Failed to get asic power limits!\n"); 727 return ret; 728 } 729 730 if (!amdgpu_sriov_vf(adev)) 731 smu_get_unique_id(smu); 732 733 smu_get_fan_parameters(smu); 734 735 smu_handle_task(&adev->smu, 736 smu->smu_dpm.dpm_level, 737 AMD_PP_TASK_COMPLETE_INIT, 738 false); 739 740 smu_restore_dpm_user_profile(smu); 741 742 return 0; 743 } 744 745 static int smu_init_fb_allocations(struct smu_context *smu) 746 { 747 struct amdgpu_device *adev = smu->adev; 748 struct smu_table_context *smu_table = &smu->smu_table; 749 struct smu_table *tables = smu_table->tables; 750 struct smu_table *driver_table = &(smu_table->driver_table); 751 uint32_t max_table_size = 0; 752 int ret, i; 753 754 /* VRAM allocation for tool table */ 755 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 756 ret = amdgpu_bo_create_kernel(adev, 757 tables[SMU_TABLE_PMSTATUSLOG].size, 758 tables[SMU_TABLE_PMSTATUSLOG].align, 759 tables[SMU_TABLE_PMSTATUSLOG].domain, 760 &tables[SMU_TABLE_PMSTATUSLOG].bo, 761 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 762 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 763 if (ret) { 764 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 765 return ret; 766 } 767 } 768 769 /* VRAM allocation for driver table */ 770 for (i = 0; i < SMU_TABLE_COUNT; i++) { 771 if (tables[i].size == 0) 772 continue; 773 774 if (i == SMU_TABLE_PMSTATUSLOG) 775 continue; 776 777 if (max_table_size < tables[i].size) 778 max_table_size = tables[i].size; 779 } 780 781 driver_table->size = max_table_size; 782 driver_table->align = PAGE_SIZE; 783 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 784 785 ret = amdgpu_bo_create_kernel(adev, 786 driver_table->size, 787 driver_table->align, 788 driver_table->domain, 789 &driver_table->bo, 790 &driver_table->mc_address, 791 &driver_table->cpu_addr); 792 if (ret) { 793 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 794 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 795 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 796 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 797 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 798 } 799 800 return ret; 801 } 802 803 static int smu_fini_fb_allocations(struct smu_context *smu) 804 { 805 struct smu_table_context *smu_table = &smu->smu_table; 806 struct smu_table *tables = smu_table->tables; 807 struct smu_table *driver_table = &(smu_table->driver_table); 808 809 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 810 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 811 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 812 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 813 814 amdgpu_bo_free_kernel(&driver_table->bo, 815 &driver_table->mc_address, 816 &driver_table->cpu_addr); 817 818 return 0; 819 } 820 821 /** 822 * smu_alloc_memory_pool - allocate memory pool in the system memory 823 * 824 * @smu: amdgpu_device pointer 825 * 826 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 827 * and DramLogSetDramAddr can notify it changed. 828 * 829 * Returns 0 on success, error on failure. 830 */ 831 static int smu_alloc_memory_pool(struct smu_context *smu) 832 { 833 struct amdgpu_device *adev = smu->adev; 834 struct smu_table_context *smu_table = &smu->smu_table; 835 struct smu_table *memory_pool = &smu_table->memory_pool; 836 uint64_t pool_size = smu->pool_size; 837 int ret = 0; 838 839 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 840 return ret; 841 842 memory_pool->size = pool_size; 843 memory_pool->align = PAGE_SIZE; 844 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 845 846 switch (pool_size) { 847 case SMU_MEMORY_POOL_SIZE_256_MB: 848 case SMU_MEMORY_POOL_SIZE_512_MB: 849 case SMU_MEMORY_POOL_SIZE_1_GB: 850 case SMU_MEMORY_POOL_SIZE_2_GB: 851 ret = amdgpu_bo_create_kernel(adev, 852 memory_pool->size, 853 memory_pool->align, 854 memory_pool->domain, 855 &memory_pool->bo, 856 &memory_pool->mc_address, 857 &memory_pool->cpu_addr); 858 if (ret) 859 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 860 break; 861 default: 862 break; 863 } 864 865 return ret; 866 } 867 868 static int smu_free_memory_pool(struct smu_context *smu) 869 { 870 struct smu_table_context *smu_table = &smu->smu_table; 871 struct smu_table *memory_pool = &smu_table->memory_pool; 872 873 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 874 return 0; 875 876 amdgpu_bo_free_kernel(&memory_pool->bo, 877 &memory_pool->mc_address, 878 &memory_pool->cpu_addr); 879 880 memset(memory_pool, 0, sizeof(struct smu_table)); 881 882 return 0; 883 } 884 885 static int smu_alloc_dummy_read_table(struct smu_context *smu) 886 { 887 struct smu_table_context *smu_table = &smu->smu_table; 888 struct smu_table *dummy_read_1_table = 889 &smu_table->dummy_read_1_table; 890 struct amdgpu_device *adev = smu->adev; 891 int ret = 0; 892 893 dummy_read_1_table->size = 0x40000; 894 dummy_read_1_table->align = PAGE_SIZE; 895 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 896 897 ret = amdgpu_bo_create_kernel(adev, 898 dummy_read_1_table->size, 899 dummy_read_1_table->align, 900 dummy_read_1_table->domain, 901 &dummy_read_1_table->bo, 902 &dummy_read_1_table->mc_address, 903 &dummy_read_1_table->cpu_addr); 904 if (ret) 905 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 906 907 return ret; 908 } 909 910 static void smu_free_dummy_read_table(struct smu_context *smu) 911 { 912 struct smu_table_context *smu_table = &smu->smu_table; 913 struct smu_table *dummy_read_1_table = 914 &smu_table->dummy_read_1_table; 915 916 917 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 918 &dummy_read_1_table->mc_address, 919 &dummy_read_1_table->cpu_addr); 920 921 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 922 } 923 924 static int smu_smc_table_sw_init(struct smu_context *smu) 925 { 926 int ret; 927 928 /** 929 * Create smu_table structure, and init smc tables such as 930 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 931 */ 932 ret = smu_init_smc_tables(smu); 933 if (ret) { 934 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 935 return ret; 936 } 937 938 /** 939 * Create smu_power_context structure, and allocate smu_dpm_context and 940 * context size to fill the smu_power_context data. 941 */ 942 ret = smu_init_power(smu); 943 if (ret) { 944 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 945 return ret; 946 } 947 948 /* 949 * allocate vram bos to store smc table contents. 950 */ 951 ret = smu_init_fb_allocations(smu); 952 if (ret) 953 return ret; 954 955 ret = smu_alloc_memory_pool(smu); 956 if (ret) 957 return ret; 958 959 ret = smu_alloc_dummy_read_table(smu); 960 if (ret) 961 return ret; 962 963 ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c); 964 if (ret) 965 return ret; 966 967 return 0; 968 } 969 970 static int smu_smc_table_sw_fini(struct smu_context *smu) 971 { 972 int ret; 973 974 smu_i2c_fini(smu, &smu->adev->pm.smu_i2c); 975 976 smu_free_dummy_read_table(smu); 977 978 ret = smu_free_memory_pool(smu); 979 if (ret) 980 return ret; 981 982 ret = smu_fini_fb_allocations(smu); 983 if (ret) 984 return ret; 985 986 ret = smu_fini_power(smu); 987 if (ret) { 988 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 989 return ret; 990 } 991 992 ret = smu_fini_smc_tables(smu); 993 if (ret) { 994 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 995 return ret; 996 } 997 998 return 0; 999 } 1000 1001 static void smu_throttling_logging_work_fn(struct work_struct *work) 1002 { 1003 struct smu_context *smu = container_of(work, struct smu_context, 1004 throttling_logging_work); 1005 1006 smu_log_thermal_throttling(smu); 1007 } 1008 1009 static void smu_interrupt_work_fn(struct work_struct *work) 1010 { 1011 struct smu_context *smu = container_of(work, struct smu_context, 1012 interrupt_work); 1013 1014 mutex_lock(&smu->mutex); 1015 1016 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1017 smu->ppt_funcs->interrupt_work(smu); 1018 1019 mutex_unlock(&smu->mutex); 1020 } 1021 1022 static int smu_sw_init(void *handle) 1023 { 1024 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1025 struct smu_context *smu = &adev->smu; 1026 int ret; 1027 1028 smu->pool_size = adev->pm.smu_prv_buffer_size; 1029 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1030 mutex_init(&smu->smu_feature.mutex); 1031 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1032 bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX); 1033 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1034 1035 mutex_init(&smu->sensor_lock); 1036 mutex_init(&smu->metrics_lock); 1037 mutex_init(&smu->message_lock); 1038 1039 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1040 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1041 atomic64_set(&smu->throttle_int_counter, 0); 1042 smu->watermarks_bitmap = 0; 1043 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1044 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1045 1046 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1047 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1048 mutex_init(&smu->smu_power.power_gate.vcn_gate_lock); 1049 mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock); 1050 1051 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1052 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1053 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1054 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1055 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1056 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1057 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1058 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1059 1060 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1061 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1062 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1063 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1064 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1065 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1066 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1067 smu->display_config = &adev->pm.pm_display_cfg; 1068 1069 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1070 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1071 1072 ret = smu_init_microcode(smu); 1073 if (ret) { 1074 dev_err(adev->dev, "Failed to load smu firmware!\n"); 1075 return ret; 1076 } 1077 1078 ret = smu_smc_table_sw_init(smu); 1079 if (ret) { 1080 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1081 return ret; 1082 } 1083 1084 ret = smu_register_irq_handler(smu); 1085 if (ret) { 1086 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1087 return ret; 1088 } 1089 1090 /* If there is no way to query fan control mode, fan control is not supported */ 1091 if (!smu->ppt_funcs->get_fan_control_mode) 1092 smu->adev->pm.no_fan = true; 1093 1094 return 0; 1095 } 1096 1097 static int smu_sw_fini(void *handle) 1098 { 1099 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1100 struct smu_context *smu = &adev->smu; 1101 int ret; 1102 1103 ret = smu_smc_table_sw_fini(smu); 1104 if (ret) { 1105 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1106 return ret; 1107 } 1108 1109 smu_fini_microcode(smu); 1110 1111 return 0; 1112 } 1113 1114 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1115 { 1116 struct amdgpu_device *adev = smu->adev; 1117 struct smu_temperature_range *range = 1118 &smu->thermal_range; 1119 int ret = 0; 1120 1121 if (!smu->ppt_funcs->get_thermal_temperature_range) 1122 return 0; 1123 1124 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1125 if (ret) 1126 return ret; 1127 1128 adev->pm.dpm.thermal.min_temp = range->min; 1129 adev->pm.dpm.thermal.max_temp = range->max; 1130 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1131 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1132 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1133 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1134 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1135 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1136 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1137 1138 return ret; 1139 } 1140 1141 static int smu_smc_hw_setup(struct smu_context *smu) 1142 { 1143 struct amdgpu_device *adev = smu->adev; 1144 uint32_t pcie_gen = 0, pcie_width = 0; 1145 int ret = 0; 1146 1147 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1148 dev_info(adev->dev, "dpm has been enabled\n"); 1149 /* this is needed specifically */ 1150 switch (adev->ip_versions[MP1_HWIP][0]) { 1151 case IP_VERSION(11, 0, 7): 1152 case IP_VERSION(11, 0, 11): 1153 case IP_VERSION(11, 5, 0): 1154 case IP_VERSION(11, 0, 12): 1155 ret = smu_system_features_control(smu, true); 1156 break; 1157 default: 1158 break; 1159 } 1160 return ret; 1161 } 1162 1163 ret = smu_init_display_count(smu, 0); 1164 if (ret) { 1165 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1166 return ret; 1167 } 1168 1169 ret = smu_set_driver_table_location(smu); 1170 if (ret) { 1171 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1172 return ret; 1173 } 1174 1175 /* 1176 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1177 */ 1178 ret = smu_set_tool_table_location(smu); 1179 if (ret) { 1180 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1181 return ret; 1182 } 1183 1184 /* 1185 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1186 * pool location. 1187 */ 1188 ret = smu_notify_memory_pool_location(smu); 1189 if (ret) { 1190 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1191 return ret; 1192 } 1193 1194 /* smu_dump_pptable(smu); */ 1195 /* 1196 * Copy pptable bo in the vram to smc with SMU MSGs such as 1197 * SetDriverDramAddr and TransferTableDram2Smu. 1198 */ 1199 ret = smu_write_pptable(smu); 1200 if (ret) { 1201 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1202 return ret; 1203 } 1204 1205 /* issue Run*Btc msg */ 1206 ret = smu_run_btc(smu); 1207 if (ret) 1208 return ret; 1209 1210 ret = smu_feature_set_allowed_mask(smu); 1211 if (ret) { 1212 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1213 return ret; 1214 } 1215 1216 ret = smu_system_features_control(smu, true); 1217 if (ret) { 1218 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1219 return ret; 1220 } 1221 1222 if (!smu_is_dpm_running(smu)) 1223 dev_info(adev->dev, "dpm has been disabled\n"); 1224 1225 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1226 pcie_gen = 3; 1227 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1228 pcie_gen = 2; 1229 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1230 pcie_gen = 1; 1231 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1232 pcie_gen = 0; 1233 1234 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1235 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1236 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1237 */ 1238 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1239 pcie_width = 6; 1240 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1241 pcie_width = 5; 1242 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1243 pcie_width = 4; 1244 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1245 pcie_width = 3; 1246 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1247 pcie_width = 2; 1248 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1249 pcie_width = 1; 1250 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1251 if (ret) { 1252 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1253 return ret; 1254 } 1255 1256 ret = smu_get_thermal_temperature_range(smu); 1257 if (ret) { 1258 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1259 return ret; 1260 } 1261 1262 ret = smu_enable_thermal_alert(smu); 1263 if (ret) { 1264 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1265 return ret; 1266 } 1267 1268 /* 1269 * Set initialized values (get from vbios) to dpm tables context such as 1270 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1271 * type of clks. 1272 */ 1273 ret = smu_set_default_dpm_table(smu); 1274 if (ret) { 1275 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1276 return ret; 1277 } 1278 1279 ret = smu_notify_display_change(smu); 1280 if (ret) 1281 return ret; 1282 1283 /* 1284 * Set min deep sleep dce fclk with bootup value from vbios via 1285 * SetMinDeepSleepDcefclk MSG. 1286 */ 1287 ret = smu_set_min_dcef_deep_sleep(smu, 1288 smu->smu_table.boot_values.dcefclk / 100); 1289 if (ret) 1290 return ret; 1291 1292 return ret; 1293 } 1294 1295 static int smu_start_smc_engine(struct smu_context *smu) 1296 { 1297 struct amdgpu_device *adev = smu->adev; 1298 int ret = 0; 1299 1300 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1301 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) { 1302 if (smu->ppt_funcs->load_microcode) { 1303 ret = smu->ppt_funcs->load_microcode(smu); 1304 if (ret) 1305 return ret; 1306 } 1307 } 1308 } 1309 1310 if (smu->ppt_funcs->check_fw_status) { 1311 ret = smu->ppt_funcs->check_fw_status(smu); 1312 if (ret) { 1313 dev_err(adev->dev, "SMC is not ready\n"); 1314 return ret; 1315 } 1316 } 1317 1318 /* 1319 * Send msg GetDriverIfVersion to check if the return value is equal 1320 * with DRIVER_IF_VERSION of smc header. 1321 */ 1322 ret = smu_check_fw_version(smu); 1323 if (ret) 1324 return ret; 1325 1326 return ret; 1327 } 1328 1329 static int smu_hw_init(void *handle) 1330 { 1331 int ret; 1332 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1333 struct smu_context *smu = &adev->smu; 1334 1335 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1336 smu->pm_enabled = false; 1337 return 0; 1338 } 1339 1340 ret = smu_start_smc_engine(smu); 1341 if (ret) { 1342 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1343 return ret; 1344 } 1345 1346 if (smu->is_apu) { 1347 smu_powergate_sdma(&adev->smu, false); 1348 smu_dpm_set_vcn_enable(smu, true); 1349 smu_dpm_set_jpeg_enable(smu, true); 1350 smu_set_gfx_cgpg(&adev->smu, true); 1351 } 1352 1353 if (!smu->pm_enabled) 1354 return 0; 1355 1356 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1357 ret = smu_get_vbios_bootup_values(smu); 1358 if (ret) { 1359 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1360 return ret; 1361 } 1362 1363 ret = smu_setup_pptable(smu); 1364 if (ret) { 1365 dev_err(adev->dev, "Failed to setup pptable!\n"); 1366 return ret; 1367 } 1368 1369 ret = smu_get_driver_allowed_feature_mask(smu); 1370 if (ret) 1371 return ret; 1372 1373 ret = smu_smc_hw_setup(smu); 1374 if (ret) { 1375 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1376 return ret; 1377 } 1378 1379 /* 1380 * Move maximum sustainable clock retrieving here considering 1381 * 1. It is not needed on resume(from S3). 1382 * 2. DAL settings come between .hw_init and .late_init of SMU. 1383 * And DAL needs to know the maximum sustainable clocks. Thus 1384 * it cannot be put in .late_init(). 1385 */ 1386 ret = smu_init_max_sustainable_clocks(smu); 1387 if (ret) { 1388 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1389 return ret; 1390 } 1391 1392 adev->pm.dpm_enabled = true; 1393 1394 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1395 1396 return 0; 1397 } 1398 1399 static int smu_disable_dpms(struct smu_context *smu) 1400 { 1401 struct amdgpu_device *adev = smu->adev; 1402 int ret = 0; 1403 bool use_baco = !smu->is_apu && 1404 ((amdgpu_in_reset(adev) && 1405 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1406 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1407 1408 /* 1409 * For custom pptable uploading, skip the DPM features 1410 * disable process on Navi1x ASICs. 1411 * - As the gfx related features are under control of 1412 * RLC on those ASICs. RLC reinitialization will be 1413 * needed to reenable them. That will cost much more 1414 * efforts. 1415 * 1416 * - SMU firmware can handle the DPM reenablement 1417 * properly. 1418 */ 1419 if (smu->uploading_custom_pp_table) { 1420 switch (adev->ip_versions[MP1_HWIP][0]) { 1421 case IP_VERSION(11, 0, 0): 1422 case IP_VERSION(11, 0, 5): 1423 case IP_VERSION(11, 0, 9): 1424 case IP_VERSION(11, 0, 7): 1425 case IP_VERSION(11, 0, 11): 1426 case IP_VERSION(11, 5, 0): 1427 case IP_VERSION(11, 0, 12): 1428 case IP_VERSION(11, 0, 13): 1429 return smu_disable_all_features_with_exception(smu, 1430 true, 1431 SMU_FEATURE_COUNT); 1432 default: 1433 break; 1434 } 1435 } 1436 1437 /* 1438 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1439 * on BACO in. Driver involvement is unnecessary. 1440 */ 1441 if (use_baco) { 1442 switch (adev->ip_versions[MP1_HWIP][0]) { 1443 case IP_VERSION(11, 0, 7): 1444 case IP_VERSION(11, 0, 0): 1445 case IP_VERSION(11, 0, 5): 1446 case IP_VERSION(11, 0, 9): 1447 return smu_disable_all_features_with_exception(smu, 1448 true, 1449 SMU_FEATURE_BACO_BIT); 1450 default: 1451 break; 1452 } 1453 } 1454 1455 /* 1456 * For gpu reset, runpm and hibernation through BACO, 1457 * BACO feature has to be kept enabled. 1458 */ 1459 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1460 ret = smu_disable_all_features_with_exception(smu, 1461 false, 1462 SMU_FEATURE_BACO_BIT); 1463 if (ret) 1464 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1465 } else { 1466 ret = smu_system_features_control(smu, false); 1467 if (ret) 1468 dev_err(adev->dev, "Failed to disable smu features.\n"); 1469 } 1470 1471 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) && 1472 adev->gfx.rlc.funcs->stop) 1473 adev->gfx.rlc.funcs->stop(adev); 1474 1475 return ret; 1476 } 1477 1478 static int smu_smc_hw_cleanup(struct smu_context *smu) 1479 { 1480 struct amdgpu_device *adev = smu->adev; 1481 int ret = 0; 1482 1483 cancel_work_sync(&smu->throttling_logging_work); 1484 cancel_work_sync(&smu->interrupt_work); 1485 1486 ret = smu_disable_thermal_alert(smu); 1487 if (ret) { 1488 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1489 return ret; 1490 } 1491 1492 ret = smu_disable_dpms(smu); 1493 if (ret) { 1494 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1495 return ret; 1496 } 1497 1498 return 0; 1499 } 1500 1501 static int smu_hw_fini(void *handle) 1502 { 1503 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1504 struct smu_context *smu = &adev->smu; 1505 1506 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1507 return 0; 1508 1509 if (smu->is_apu) { 1510 smu_powergate_sdma(&adev->smu, true); 1511 } 1512 1513 smu_dpm_set_vcn_enable(smu, false); 1514 smu_dpm_set_jpeg_enable(smu, false); 1515 1516 adev->vcn.cur_state = AMD_PG_STATE_GATE; 1517 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 1518 1519 if (!smu->pm_enabled) 1520 return 0; 1521 1522 adev->pm.dpm_enabled = false; 1523 1524 return smu_smc_hw_cleanup(smu); 1525 } 1526 1527 static int smu_reset(struct smu_context *smu) 1528 { 1529 struct amdgpu_device *adev = smu->adev; 1530 int ret; 1531 1532 amdgpu_gfx_off_ctrl(smu->adev, false); 1533 1534 ret = smu_hw_fini(adev); 1535 if (ret) 1536 return ret; 1537 1538 ret = smu_hw_init(adev); 1539 if (ret) 1540 return ret; 1541 1542 ret = smu_late_init(adev); 1543 if (ret) 1544 return ret; 1545 1546 amdgpu_gfx_off_ctrl(smu->adev, true); 1547 1548 return 0; 1549 } 1550 1551 static int smu_suspend(void *handle) 1552 { 1553 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1554 struct smu_context *smu = &adev->smu; 1555 int ret; 1556 1557 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1558 return 0; 1559 1560 if (!smu->pm_enabled) 1561 return 0; 1562 1563 adev->pm.dpm_enabled = false; 1564 1565 ret = smu_smc_hw_cleanup(smu); 1566 if (ret) 1567 return ret; 1568 1569 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1570 1571 /* skip CGPG when in S0ix */ 1572 if (smu->is_apu && !adev->in_s0ix) 1573 smu_set_gfx_cgpg(&adev->smu, false); 1574 1575 return 0; 1576 } 1577 1578 static int smu_resume(void *handle) 1579 { 1580 int ret; 1581 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1582 struct smu_context *smu = &adev->smu; 1583 1584 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1585 return 0; 1586 1587 if (!smu->pm_enabled) 1588 return 0; 1589 1590 dev_info(adev->dev, "SMU is resuming...\n"); 1591 1592 ret = smu_start_smc_engine(smu); 1593 if (ret) { 1594 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1595 return ret; 1596 } 1597 1598 ret = smu_smc_hw_setup(smu); 1599 if (ret) { 1600 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1601 return ret; 1602 } 1603 1604 if (smu->is_apu) 1605 smu_set_gfx_cgpg(&adev->smu, true); 1606 1607 smu->disable_uclk_switch = 0; 1608 1609 adev->pm.dpm_enabled = true; 1610 1611 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1612 1613 return 0; 1614 } 1615 1616 static int smu_display_configuration_change(void *handle, 1617 const struct amd_pp_display_configuration *display_config) 1618 { 1619 struct smu_context *smu = handle; 1620 int index = 0; 1621 int num_of_active_display = 0; 1622 1623 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1624 return -EOPNOTSUPP; 1625 1626 if (!display_config) 1627 return -EINVAL; 1628 1629 mutex_lock(&smu->mutex); 1630 1631 smu_set_min_dcef_deep_sleep(smu, 1632 display_config->min_dcef_deep_sleep_set_clk / 100); 1633 1634 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1635 if (display_config->displays[index].controller_id != 0) 1636 num_of_active_display++; 1637 } 1638 1639 mutex_unlock(&smu->mutex); 1640 1641 return 0; 1642 } 1643 1644 static int smu_set_clockgating_state(void *handle, 1645 enum amd_clockgating_state state) 1646 { 1647 return 0; 1648 } 1649 1650 static int smu_set_powergating_state(void *handle, 1651 enum amd_powergating_state state) 1652 { 1653 return 0; 1654 } 1655 1656 static int smu_enable_umd_pstate(void *handle, 1657 enum amd_dpm_forced_level *level) 1658 { 1659 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1660 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1661 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1662 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1663 1664 struct smu_context *smu = (struct smu_context*)(handle); 1665 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1666 1667 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1668 return -EINVAL; 1669 1670 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1671 /* enter umd pstate, save current level, disable gfx cg*/ 1672 if (*level & profile_mode_mask) { 1673 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1674 smu_dpm_ctx->enable_umd_pstate = true; 1675 smu_gpo_control(smu, false); 1676 amdgpu_device_ip_set_powergating_state(smu->adev, 1677 AMD_IP_BLOCK_TYPE_GFX, 1678 AMD_PG_STATE_UNGATE); 1679 amdgpu_device_ip_set_clockgating_state(smu->adev, 1680 AMD_IP_BLOCK_TYPE_GFX, 1681 AMD_CG_STATE_UNGATE); 1682 smu_gfx_ulv_control(smu, false); 1683 smu_deep_sleep_control(smu, false); 1684 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1685 } 1686 } else { 1687 /* exit umd pstate, restore level, enable gfx cg*/ 1688 if (!(*level & profile_mode_mask)) { 1689 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1690 *level = smu_dpm_ctx->saved_dpm_level; 1691 smu_dpm_ctx->enable_umd_pstate = false; 1692 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1693 smu_deep_sleep_control(smu, true); 1694 smu_gfx_ulv_control(smu, true); 1695 amdgpu_device_ip_set_clockgating_state(smu->adev, 1696 AMD_IP_BLOCK_TYPE_GFX, 1697 AMD_CG_STATE_GATE); 1698 amdgpu_device_ip_set_powergating_state(smu->adev, 1699 AMD_IP_BLOCK_TYPE_GFX, 1700 AMD_PG_STATE_GATE); 1701 smu_gpo_control(smu, true); 1702 } 1703 } 1704 1705 return 0; 1706 } 1707 1708 static int smu_bump_power_profile_mode(struct smu_context *smu, 1709 long *param, 1710 uint32_t param_size) 1711 { 1712 int ret = 0; 1713 1714 if (smu->ppt_funcs->set_power_profile_mode) 1715 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1716 1717 return ret; 1718 } 1719 1720 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1721 enum amd_dpm_forced_level level, 1722 bool skip_display_settings) 1723 { 1724 int ret = 0; 1725 int index = 0; 1726 long workload; 1727 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1728 1729 if (!skip_display_settings) { 1730 ret = smu_display_config_changed(smu); 1731 if (ret) { 1732 dev_err(smu->adev->dev, "Failed to change display config!"); 1733 return ret; 1734 } 1735 } 1736 1737 ret = smu_apply_clocks_adjust_rules(smu); 1738 if (ret) { 1739 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1740 return ret; 1741 } 1742 1743 if (!skip_display_settings) { 1744 ret = smu_notify_smc_display_config(smu); 1745 if (ret) { 1746 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1747 return ret; 1748 } 1749 } 1750 1751 if (smu_dpm_ctx->dpm_level != level) { 1752 ret = smu_asic_set_performance_level(smu, level); 1753 if (ret) { 1754 dev_err(smu->adev->dev, "Failed to set performance level!"); 1755 return ret; 1756 } 1757 1758 /* update the saved copy */ 1759 smu_dpm_ctx->dpm_level = level; 1760 } 1761 1762 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1763 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1764 index = fls(smu->workload_mask); 1765 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1766 workload = smu->workload_setting[index]; 1767 1768 if (smu->power_profile_mode != workload) 1769 smu_bump_power_profile_mode(smu, &workload, 0); 1770 } 1771 1772 return ret; 1773 } 1774 1775 static int smu_handle_task(struct smu_context *smu, 1776 enum amd_dpm_forced_level level, 1777 enum amd_pp_task task_id, 1778 bool lock_needed) 1779 { 1780 int ret = 0; 1781 1782 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1783 return -EOPNOTSUPP; 1784 1785 if (lock_needed) 1786 mutex_lock(&smu->mutex); 1787 1788 switch (task_id) { 1789 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1790 ret = smu_pre_display_config_changed(smu); 1791 if (ret) 1792 goto out; 1793 ret = smu_adjust_power_state_dynamic(smu, level, false); 1794 break; 1795 case AMD_PP_TASK_COMPLETE_INIT: 1796 case AMD_PP_TASK_READJUST_POWER_STATE: 1797 ret = smu_adjust_power_state_dynamic(smu, level, true); 1798 break; 1799 default: 1800 break; 1801 } 1802 1803 out: 1804 if (lock_needed) 1805 mutex_unlock(&smu->mutex); 1806 1807 return ret; 1808 } 1809 1810 static int smu_handle_dpm_task(void *handle, 1811 enum amd_pp_task task_id, 1812 enum amd_pm_state_type *user_state) 1813 { 1814 struct smu_context *smu = handle; 1815 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1816 1817 return smu_handle_task(smu, smu_dpm->dpm_level, task_id, true); 1818 1819 } 1820 1821 static int smu_switch_power_profile(void *handle, 1822 enum PP_SMC_POWER_PROFILE type, 1823 bool en) 1824 { 1825 struct smu_context *smu = handle; 1826 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1827 long workload; 1828 uint32_t index; 1829 1830 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1831 return -EOPNOTSUPP; 1832 1833 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1834 return -EINVAL; 1835 1836 mutex_lock(&smu->mutex); 1837 1838 if (!en) { 1839 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1840 index = fls(smu->workload_mask); 1841 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1842 workload = smu->workload_setting[index]; 1843 } else { 1844 smu->workload_mask |= (1 << smu->workload_prority[type]); 1845 index = fls(smu->workload_mask); 1846 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1847 workload = smu->workload_setting[index]; 1848 } 1849 1850 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1851 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1852 smu_bump_power_profile_mode(smu, &workload, 0); 1853 1854 mutex_unlock(&smu->mutex); 1855 1856 return 0; 1857 } 1858 1859 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 1860 { 1861 struct smu_context *smu = handle; 1862 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1863 enum amd_dpm_forced_level level; 1864 1865 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1866 return -EOPNOTSUPP; 1867 1868 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1869 return -EINVAL; 1870 1871 mutex_lock(&(smu->mutex)); 1872 level = smu_dpm_ctx->dpm_level; 1873 mutex_unlock(&(smu->mutex)); 1874 1875 return level; 1876 } 1877 1878 static int smu_force_performance_level(void *handle, 1879 enum amd_dpm_forced_level level) 1880 { 1881 struct smu_context *smu = handle; 1882 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1883 int ret = 0; 1884 1885 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1886 return -EOPNOTSUPP; 1887 1888 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1889 return -EINVAL; 1890 1891 mutex_lock(&smu->mutex); 1892 1893 ret = smu_enable_umd_pstate(smu, &level); 1894 if (ret) { 1895 mutex_unlock(&smu->mutex); 1896 return ret; 1897 } 1898 1899 ret = smu_handle_task(smu, level, 1900 AMD_PP_TASK_READJUST_POWER_STATE, 1901 false); 1902 1903 mutex_unlock(&smu->mutex); 1904 1905 /* reset user dpm clock state */ 1906 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1907 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 1908 smu->user_dpm_profile.clk_dependency = 0; 1909 } 1910 1911 return ret; 1912 } 1913 1914 static int smu_set_display_count(void *handle, uint32_t count) 1915 { 1916 struct smu_context *smu = handle; 1917 int ret = 0; 1918 1919 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1920 return -EOPNOTSUPP; 1921 1922 mutex_lock(&smu->mutex); 1923 ret = smu_init_display_count(smu, count); 1924 mutex_unlock(&smu->mutex); 1925 1926 return ret; 1927 } 1928 1929 static int smu_force_smuclk_levels(struct smu_context *smu, 1930 enum smu_clk_type clk_type, 1931 uint32_t mask) 1932 { 1933 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1934 int ret = 0; 1935 1936 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1937 return -EOPNOTSUPP; 1938 1939 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1940 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1941 return -EINVAL; 1942 } 1943 1944 mutex_lock(&smu->mutex); 1945 1946 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 1947 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1948 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 1949 smu->user_dpm_profile.clk_mask[clk_type] = mask; 1950 smu_set_user_clk_dependencies(smu, clk_type); 1951 } 1952 } 1953 1954 mutex_unlock(&smu->mutex); 1955 1956 return ret; 1957 } 1958 1959 static int smu_force_ppclk_levels(void *handle, 1960 enum pp_clock_type type, 1961 uint32_t mask) 1962 { 1963 struct smu_context *smu = handle; 1964 enum smu_clk_type clk_type; 1965 1966 switch (type) { 1967 case PP_SCLK: 1968 clk_type = SMU_SCLK; break; 1969 case PP_MCLK: 1970 clk_type = SMU_MCLK; break; 1971 case PP_PCIE: 1972 clk_type = SMU_PCIE; break; 1973 case PP_SOCCLK: 1974 clk_type = SMU_SOCCLK; break; 1975 case PP_FCLK: 1976 clk_type = SMU_FCLK; break; 1977 case PP_DCEFCLK: 1978 clk_type = SMU_DCEFCLK; break; 1979 case PP_VCLK: 1980 clk_type = SMU_VCLK; break; 1981 case PP_DCLK: 1982 clk_type = SMU_DCLK; break; 1983 case OD_SCLK: 1984 clk_type = SMU_OD_SCLK; break; 1985 case OD_MCLK: 1986 clk_type = SMU_OD_MCLK; break; 1987 case OD_VDDC_CURVE: 1988 clk_type = SMU_OD_VDDC_CURVE; break; 1989 case OD_RANGE: 1990 clk_type = SMU_OD_RANGE; break; 1991 default: 1992 return -EINVAL; 1993 } 1994 1995 return smu_force_smuclk_levels(smu, clk_type, mask); 1996 } 1997 1998 /* 1999 * On system suspending or resetting, the dpm_enabled 2000 * flag will be cleared. So that those SMU services which 2001 * are not supported will be gated. 2002 * However, the mp1 state setting should still be granted 2003 * even if the dpm_enabled cleared. 2004 */ 2005 static int smu_set_mp1_state(void *handle, 2006 enum pp_mp1_state mp1_state) 2007 { 2008 struct smu_context *smu = handle; 2009 int ret = 0; 2010 2011 if (!smu->pm_enabled) 2012 return -EOPNOTSUPP; 2013 2014 mutex_lock(&smu->mutex); 2015 2016 if (smu->ppt_funcs && 2017 smu->ppt_funcs->set_mp1_state) 2018 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2019 2020 mutex_unlock(&smu->mutex); 2021 2022 return ret; 2023 } 2024 2025 static int smu_set_df_cstate(void *handle, 2026 enum pp_df_cstate state) 2027 { 2028 struct smu_context *smu = handle; 2029 int ret = 0; 2030 2031 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2032 return -EOPNOTSUPP; 2033 2034 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2035 return 0; 2036 2037 mutex_lock(&smu->mutex); 2038 2039 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2040 if (ret) 2041 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2042 2043 mutex_unlock(&smu->mutex); 2044 2045 return ret; 2046 } 2047 2048 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 2049 { 2050 int ret = 0; 2051 2052 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2053 return -EOPNOTSUPP; 2054 2055 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 2056 return 0; 2057 2058 mutex_lock(&smu->mutex); 2059 2060 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 2061 if (ret) 2062 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 2063 2064 mutex_unlock(&smu->mutex); 2065 2066 return ret; 2067 } 2068 2069 int smu_write_watermarks_table(struct smu_context *smu) 2070 { 2071 int ret = 0; 2072 2073 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2074 return -EOPNOTSUPP; 2075 2076 mutex_lock(&smu->mutex); 2077 2078 ret = smu_set_watermarks_table(smu, NULL); 2079 2080 mutex_unlock(&smu->mutex); 2081 2082 return ret; 2083 } 2084 2085 static int smu_set_watermarks_for_clock_ranges(void *handle, 2086 struct pp_smu_wm_range_sets *clock_ranges) 2087 { 2088 struct smu_context *smu = handle; 2089 int ret = 0; 2090 2091 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2092 return -EOPNOTSUPP; 2093 2094 if (smu->disable_watermark) 2095 return 0; 2096 2097 mutex_lock(&smu->mutex); 2098 2099 ret = smu_set_watermarks_table(smu, clock_ranges); 2100 2101 mutex_unlock(&smu->mutex); 2102 2103 return ret; 2104 } 2105 2106 int smu_set_ac_dc(struct smu_context *smu) 2107 { 2108 int ret = 0; 2109 2110 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2111 return -EOPNOTSUPP; 2112 2113 /* controlled by firmware */ 2114 if (smu->dc_controlled_by_gpio) 2115 return 0; 2116 2117 mutex_lock(&smu->mutex); 2118 ret = smu_set_power_source(smu, 2119 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2120 SMU_POWER_SOURCE_DC); 2121 if (ret) 2122 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2123 smu->adev->pm.ac_power ? "AC" : "DC"); 2124 mutex_unlock(&smu->mutex); 2125 2126 return ret; 2127 } 2128 2129 const struct amd_ip_funcs smu_ip_funcs = { 2130 .name = "smu", 2131 .early_init = smu_early_init, 2132 .late_init = smu_late_init, 2133 .sw_init = smu_sw_init, 2134 .sw_fini = smu_sw_fini, 2135 .hw_init = smu_hw_init, 2136 .hw_fini = smu_hw_fini, 2137 .suspend = smu_suspend, 2138 .resume = smu_resume, 2139 .is_idle = NULL, 2140 .check_soft_reset = NULL, 2141 .wait_for_idle = NULL, 2142 .soft_reset = NULL, 2143 .set_clockgating_state = smu_set_clockgating_state, 2144 .set_powergating_state = smu_set_powergating_state, 2145 .enable_umd_pstate = smu_enable_umd_pstate, 2146 }; 2147 2148 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 2149 { 2150 .type = AMD_IP_BLOCK_TYPE_SMC, 2151 .major = 11, 2152 .minor = 0, 2153 .rev = 0, 2154 .funcs = &smu_ip_funcs, 2155 }; 2156 2157 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 2158 { 2159 .type = AMD_IP_BLOCK_TYPE_SMC, 2160 .major = 12, 2161 .minor = 0, 2162 .rev = 0, 2163 .funcs = &smu_ip_funcs, 2164 }; 2165 2166 const struct amdgpu_ip_block_version smu_v13_0_ip_block = 2167 { 2168 .type = AMD_IP_BLOCK_TYPE_SMC, 2169 .major = 13, 2170 .minor = 0, 2171 .rev = 0, 2172 .funcs = &smu_ip_funcs, 2173 }; 2174 2175 static int smu_load_microcode(void *handle) 2176 { 2177 struct smu_context *smu = handle; 2178 struct amdgpu_device *adev = smu->adev; 2179 int ret = 0; 2180 2181 if (!smu->pm_enabled) 2182 return -EOPNOTSUPP; 2183 2184 /* This should be used for non PSP loading */ 2185 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2186 return 0; 2187 2188 if (smu->ppt_funcs->load_microcode) { 2189 ret = smu->ppt_funcs->load_microcode(smu); 2190 if (ret) { 2191 dev_err(adev->dev, "Load microcode failed\n"); 2192 return ret; 2193 } 2194 } 2195 2196 if (smu->ppt_funcs->check_fw_status) { 2197 ret = smu->ppt_funcs->check_fw_status(smu); 2198 if (ret) { 2199 dev_err(adev->dev, "SMC is not ready\n"); 2200 return ret; 2201 } 2202 } 2203 2204 return ret; 2205 } 2206 2207 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2208 { 2209 int ret = 0; 2210 2211 mutex_lock(&smu->mutex); 2212 2213 if (smu->ppt_funcs->set_gfx_cgpg) 2214 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2215 2216 mutex_unlock(&smu->mutex); 2217 2218 return ret; 2219 } 2220 2221 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2222 { 2223 struct smu_context *smu = handle; 2224 int ret = 0; 2225 2226 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2227 return -EOPNOTSUPP; 2228 2229 mutex_lock(&smu->mutex); 2230 2231 if (smu->ppt_funcs->set_fan_speed_rpm) { 2232 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2233 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2234 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2235 smu->user_dpm_profile.fan_speed_rpm = speed; 2236 2237 /* Override custom PWM setting as they cannot co-exist */ 2238 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2239 smu->user_dpm_profile.fan_speed_pwm = 0; 2240 } 2241 } 2242 2243 mutex_unlock(&smu->mutex); 2244 2245 return ret; 2246 } 2247 2248 /** 2249 * smu_get_power_limit - Request one of the SMU Power Limits 2250 * 2251 * @handle: pointer to smu context 2252 * @limit: requested limit is written back to this variable 2253 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2254 * @pp_power_type: &pp_power_type type of power 2255 * Return: 0 on success, <0 on error 2256 * 2257 */ 2258 int smu_get_power_limit(void *handle, 2259 uint32_t *limit, 2260 enum pp_power_limit_level pp_limit_level, 2261 enum pp_power_type pp_power_type) 2262 { 2263 struct smu_context *smu = handle; 2264 struct amdgpu_device *adev = smu->adev; 2265 enum smu_ppt_limit_level limit_level; 2266 uint32_t limit_type; 2267 int ret = 0; 2268 2269 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2270 return -EOPNOTSUPP; 2271 2272 switch(pp_power_type) { 2273 case PP_PWR_TYPE_SUSTAINED: 2274 limit_type = SMU_DEFAULT_PPT_LIMIT; 2275 break; 2276 case PP_PWR_TYPE_FAST: 2277 limit_type = SMU_FAST_PPT_LIMIT; 2278 break; 2279 default: 2280 return -EOPNOTSUPP; 2281 break; 2282 } 2283 2284 switch(pp_limit_level){ 2285 case PP_PWR_LIMIT_CURRENT: 2286 limit_level = SMU_PPT_LIMIT_CURRENT; 2287 break; 2288 case PP_PWR_LIMIT_DEFAULT: 2289 limit_level = SMU_PPT_LIMIT_DEFAULT; 2290 break; 2291 case PP_PWR_LIMIT_MAX: 2292 limit_level = SMU_PPT_LIMIT_MAX; 2293 break; 2294 case PP_PWR_LIMIT_MIN: 2295 default: 2296 return -EOPNOTSUPP; 2297 break; 2298 } 2299 2300 mutex_lock(&smu->mutex); 2301 2302 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2303 if (smu->ppt_funcs->get_ppt_limit) 2304 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2305 } else { 2306 switch (limit_level) { 2307 case SMU_PPT_LIMIT_CURRENT: 2308 switch (adev->ip_versions[MP1_HWIP][0]) { 2309 case IP_VERSION(13, 0, 2): 2310 case IP_VERSION(11, 0, 7): 2311 case IP_VERSION(11, 0, 11): 2312 case IP_VERSION(11, 0, 12): 2313 case IP_VERSION(11, 0, 13): 2314 ret = smu_get_asic_power_limits(smu, 2315 &smu->current_power_limit, 2316 NULL, 2317 NULL); 2318 break; 2319 default: 2320 break; 2321 } 2322 *limit = smu->current_power_limit; 2323 break; 2324 case SMU_PPT_LIMIT_DEFAULT: 2325 *limit = smu->default_power_limit; 2326 break; 2327 case SMU_PPT_LIMIT_MAX: 2328 *limit = smu->max_power_limit; 2329 break; 2330 default: 2331 break; 2332 } 2333 } 2334 2335 mutex_unlock(&smu->mutex); 2336 2337 return ret; 2338 } 2339 2340 static int smu_set_power_limit(void *handle, uint32_t limit) 2341 { 2342 struct smu_context *smu = handle; 2343 uint32_t limit_type = limit >> 24; 2344 int ret = 0; 2345 2346 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2347 return -EOPNOTSUPP; 2348 2349 mutex_lock(&smu->mutex); 2350 2351 limit &= (1<<24)-1; 2352 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2353 if (smu->ppt_funcs->set_power_limit) { 2354 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2355 goto out; 2356 } 2357 2358 if (limit > smu->max_power_limit) { 2359 dev_err(smu->adev->dev, 2360 "New power limit (%d) is over the max allowed %d\n", 2361 limit, smu->max_power_limit); 2362 ret = -EINVAL; 2363 goto out; 2364 } 2365 2366 if (!limit) 2367 limit = smu->current_power_limit; 2368 2369 if (smu->ppt_funcs->set_power_limit) { 2370 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2371 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2372 smu->user_dpm_profile.power_limit = limit; 2373 } 2374 2375 out: 2376 mutex_unlock(&smu->mutex); 2377 2378 return ret; 2379 } 2380 2381 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2382 { 2383 int ret = 0; 2384 2385 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2386 return -EOPNOTSUPP; 2387 2388 mutex_lock(&smu->mutex); 2389 2390 if (smu->ppt_funcs->print_clk_levels) 2391 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2392 2393 mutex_unlock(&smu->mutex); 2394 2395 return ret; 2396 } 2397 2398 static int smu_print_ppclk_levels(void *handle, 2399 enum pp_clock_type type, 2400 char *buf) 2401 { 2402 struct smu_context *smu = handle; 2403 enum smu_clk_type clk_type; 2404 2405 switch (type) { 2406 case PP_SCLK: 2407 clk_type = SMU_SCLK; break; 2408 case PP_MCLK: 2409 clk_type = SMU_MCLK; break; 2410 case PP_PCIE: 2411 clk_type = SMU_PCIE; break; 2412 case PP_SOCCLK: 2413 clk_type = SMU_SOCCLK; break; 2414 case PP_FCLK: 2415 clk_type = SMU_FCLK; break; 2416 case PP_DCEFCLK: 2417 clk_type = SMU_DCEFCLK; break; 2418 case PP_VCLK: 2419 clk_type = SMU_VCLK; break; 2420 case PP_DCLK: 2421 clk_type = SMU_DCLK; break; 2422 case OD_SCLK: 2423 clk_type = SMU_OD_SCLK; break; 2424 case OD_MCLK: 2425 clk_type = SMU_OD_MCLK; break; 2426 case OD_VDDC_CURVE: 2427 clk_type = SMU_OD_VDDC_CURVE; break; 2428 case OD_RANGE: 2429 clk_type = SMU_OD_RANGE; break; 2430 case OD_VDDGFX_OFFSET: 2431 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2432 case OD_CCLK: 2433 clk_type = SMU_OD_CCLK; break; 2434 default: 2435 return -EINVAL; 2436 } 2437 2438 return smu_print_smuclk_levels(smu, clk_type, buf); 2439 } 2440 2441 static int smu_od_edit_dpm_table(void *handle, 2442 enum PP_OD_DPM_TABLE_COMMAND type, 2443 long *input, uint32_t size) 2444 { 2445 struct smu_context *smu = handle; 2446 int ret = 0; 2447 2448 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2449 return -EOPNOTSUPP; 2450 2451 mutex_lock(&smu->mutex); 2452 2453 if (smu->ppt_funcs->od_edit_dpm_table) { 2454 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2455 } 2456 2457 mutex_unlock(&smu->mutex); 2458 2459 return ret; 2460 } 2461 2462 static int smu_read_sensor(void *handle, 2463 int sensor, 2464 void *data, 2465 int *size_arg) 2466 { 2467 struct smu_context *smu = handle; 2468 struct smu_umd_pstate_table *pstate_table = 2469 &smu->pstate_table; 2470 int ret = 0; 2471 uint32_t *size, size_val; 2472 2473 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2474 return -EOPNOTSUPP; 2475 2476 if (!data || !size_arg) 2477 return -EINVAL; 2478 2479 size_val = *size_arg; 2480 size = &size_val; 2481 2482 mutex_lock(&smu->mutex); 2483 2484 if (smu->ppt_funcs->read_sensor) 2485 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2486 goto unlock; 2487 2488 switch (sensor) { 2489 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2490 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2491 *size = 4; 2492 break; 2493 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2494 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2495 *size = 4; 2496 break; 2497 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2498 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2); 2499 *size = 8; 2500 break; 2501 case AMDGPU_PP_SENSOR_UVD_POWER: 2502 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2503 *size = 4; 2504 break; 2505 case AMDGPU_PP_SENSOR_VCE_POWER: 2506 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2507 *size = 4; 2508 break; 2509 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2510 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2511 *size = 4; 2512 break; 2513 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2514 *(uint32_t *)data = 0; 2515 *size = 4; 2516 break; 2517 default: 2518 *size = 0; 2519 ret = -EOPNOTSUPP; 2520 break; 2521 } 2522 2523 unlock: 2524 mutex_unlock(&smu->mutex); 2525 2526 // assign uint32_t to int 2527 *size_arg = size_val; 2528 2529 return ret; 2530 } 2531 2532 static int smu_get_power_profile_mode(void *handle, char *buf) 2533 { 2534 struct smu_context *smu = handle; 2535 int ret = 0; 2536 2537 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2538 !smu->ppt_funcs->get_power_profile_mode) 2539 return -EOPNOTSUPP; 2540 if (!buf) 2541 return -EINVAL; 2542 2543 mutex_lock(&smu->mutex); 2544 2545 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf); 2546 2547 mutex_unlock(&smu->mutex); 2548 2549 return ret; 2550 } 2551 2552 static int smu_set_power_profile_mode(void *handle, 2553 long *param, 2554 uint32_t param_size) 2555 { 2556 struct smu_context *smu = handle; 2557 int ret = 0; 2558 2559 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2560 !smu->ppt_funcs->set_power_profile_mode) 2561 return -EOPNOTSUPP; 2562 2563 mutex_lock(&smu->mutex); 2564 2565 smu_bump_power_profile_mode(smu, param, param_size); 2566 2567 mutex_unlock(&smu->mutex); 2568 2569 return ret; 2570 } 2571 2572 2573 static u32 smu_get_fan_control_mode(void *handle) 2574 { 2575 struct smu_context *smu = handle; 2576 u32 ret = 0; 2577 2578 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2579 return AMD_FAN_CTRL_NONE; 2580 2581 mutex_lock(&smu->mutex); 2582 2583 if (smu->ppt_funcs->get_fan_control_mode) 2584 ret = smu->ppt_funcs->get_fan_control_mode(smu); 2585 2586 mutex_unlock(&smu->mutex); 2587 2588 return ret; 2589 } 2590 2591 static int smu_set_fan_control_mode(struct smu_context *smu, int value) 2592 { 2593 int ret = 0; 2594 2595 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2596 return -EOPNOTSUPP; 2597 2598 mutex_lock(&smu->mutex); 2599 2600 if (smu->ppt_funcs->set_fan_control_mode) { 2601 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2602 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2603 smu->user_dpm_profile.fan_mode = value; 2604 } 2605 2606 mutex_unlock(&smu->mutex); 2607 2608 /* reset user dpm fan speed */ 2609 if (!ret && value != AMD_FAN_CTRL_MANUAL && 2610 !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2611 smu->user_dpm_profile.fan_speed_pwm = 0; 2612 smu->user_dpm_profile.fan_speed_rpm = 0; 2613 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 2614 } 2615 2616 return ret; 2617 } 2618 2619 static void smu_pp_set_fan_control_mode(void *handle, u32 value) 2620 { 2621 struct smu_context *smu = handle; 2622 2623 smu_set_fan_control_mode(smu, value); 2624 } 2625 2626 2627 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 2628 { 2629 struct smu_context *smu = handle; 2630 int ret = 0; 2631 2632 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2633 return -EOPNOTSUPP; 2634 2635 mutex_lock(&smu->mutex); 2636 2637 if (smu->ppt_funcs->get_fan_speed_pwm) 2638 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 2639 2640 mutex_unlock(&smu->mutex); 2641 2642 return ret; 2643 } 2644 2645 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 2646 { 2647 struct smu_context *smu = handle; 2648 int ret = 0; 2649 2650 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2651 return -EOPNOTSUPP; 2652 2653 mutex_lock(&smu->mutex); 2654 2655 if (smu->ppt_funcs->set_fan_speed_pwm) { 2656 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 2657 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2658 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 2659 smu->user_dpm_profile.fan_speed_pwm = speed; 2660 2661 /* Override custom RPM setting as they cannot co-exist */ 2662 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 2663 smu->user_dpm_profile.fan_speed_rpm = 0; 2664 } 2665 } 2666 2667 mutex_unlock(&smu->mutex); 2668 2669 return ret; 2670 } 2671 2672 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2673 { 2674 struct smu_context *smu = handle; 2675 int ret = 0; 2676 2677 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2678 return -EOPNOTSUPP; 2679 2680 mutex_lock(&smu->mutex); 2681 2682 if (smu->ppt_funcs->get_fan_speed_rpm) 2683 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 2684 2685 mutex_unlock(&smu->mutex); 2686 2687 return ret; 2688 } 2689 2690 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 2691 { 2692 struct smu_context *smu = handle; 2693 int ret = 0; 2694 2695 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2696 return -EOPNOTSUPP; 2697 2698 mutex_lock(&smu->mutex); 2699 2700 ret = smu_set_min_dcef_deep_sleep(smu, clk); 2701 2702 mutex_unlock(&smu->mutex); 2703 2704 return ret; 2705 } 2706 2707 static int smu_get_clock_by_type_with_latency(void *handle, 2708 enum amd_pp_clock_type type, 2709 struct pp_clock_levels_with_latency *clocks) 2710 { 2711 struct smu_context *smu = handle; 2712 enum smu_clk_type clk_type; 2713 int ret = 0; 2714 2715 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2716 return -EOPNOTSUPP; 2717 2718 mutex_lock(&smu->mutex); 2719 2720 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 2721 switch (type) { 2722 case amd_pp_sys_clock: 2723 clk_type = SMU_GFXCLK; 2724 break; 2725 case amd_pp_mem_clock: 2726 clk_type = SMU_MCLK; 2727 break; 2728 case amd_pp_dcef_clock: 2729 clk_type = SMU_DCEFCLK; 2730 break; 2731 case amd_pp_disp_clock: 2732 clk_type = SMU_DISPCLK; 2733 break; 2734 default: 2735 dev_err(smu->adev->dev, "Invalid clock type!\n"); 2736 mutex_unlock(&smu->mutex); 2737 return -EINVAL; 2738 } 2739 2740 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2741 } 2742 2743 mutex_unlock(&smu->mutex); 2744 2745 return ret; 2746 } 2747 2748 static int smu_display_clock_voltage_request(void *handle, 2749 struct pp_display_clock_request *clock_req) 2750 { 2751 struct smu_context *smu = handle; 2752 int ret = 0; 2753 2754 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2755 return -EOPNOTSUPP; 2756 2757 mutex_lock(&smu->mutex); 2758 2759 if (smu->ppt_funcs->display_clock_voltage_request) 2760 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2761 2762 mutex_unlock(&smu->mutex); 2763 2764 return ret; 2765 } 2766 2767 2768 static int smu_display_disable_memory_clock_switch(void *handle, 2769 bool disable_memory_clock_switch) 2770 { 2771 struct smu_context *smu = handle; 2772 int ret = -EINVAL; 2773 2774 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2775 return -EOPNOTSUPP; 2776 2777 mutex_lock(&smu->mutex); 2778 2779 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2780 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2781 2782 mutex_unlock(&smu->mutex); 2783 2784 return ret; 2785 } 2786 2787 static int smu_set_xgmi_pstate(void *handle, 2788 uint32_t pstate) 2789 { 2790 struct smu_context *smu = handle; 2791 int ret = 0; 2792 2793 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2794 return -EOPNOTSUPP; 2795 2796 mutex_lock(&smu->mutex); 2797 2798 if (smu->ppt_funcs->set_xgmi_pstate) 2799 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2800 2801 mutex_unlock(&smu->mutex); 2802 2803 if(ret) 2804 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2805 2806 return ret; 2807 } 2808 2809 static int smu_get_baco_capability(void *handle, bool *cap) 2810 { 2811 struct smu_context *smu = handle; 2812 int ret = 0; 2813 2814 *cap = false; 2815 2816 if (!smu->pm_enabled) 2817 return 0; 2818 2819 mutex_lock(&smu->mutex); 2820 2821 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2822 *cap = smu->ppt_funcs->baco_is_support(smu); 2823 2824 mutex_unlock(&smu->mutex); 2825 2826 return ret; 2827 } 2828 2829 static int smu_baco_set_state(void *handle, int state) 2830 { 2831 struct smu_context *smu = handle; 2832 int ret = 0; 2833 2834 if (!smu->pm_enabled) 2835 return -EOPNOTSUPP; 2836 2837 if (state == 0) { 2838 mutex_lock(&smu->mutex); 2839 2840 if (smu->ppt_funcs->baco_exit) 2841 ret = smu->ppt_funcs->baco_exit(smu); 2842 2843 mutex_unlock(&smu->mutex); 2844 } else if (state == 1) { 2845 mutex_lock(&smu->mutex); 2846 2847 if (smu->ppt_funcs->baco_enter) 2848 ret = smu->ppt_funcs->baco_enter(smu); 2849 2850 mutex_unlock(&smu->mutex); 2851 2852 } else { 2853 return -EINVAL; 2854 } 2855 2856 if (ret) 2857 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 2858 (state)?"enter":"exit"); 2859 2860 return ret; 2861 } 2862 2863 bool smu_mode1_reset_is_support(struct smu_context *smu) 2864 { 2865 bool ret = false; 2866 2867 if (!smu->pm_enabled) 2868 return false; 2869 2870 mutex_lock(&smu->mutex); 2871 2872 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2873 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2874 2875 mutex_unlock(&smu->mutex); 2876 2877 return ret; 2878 } 2879 2880 bool smu_mode2_reset_is_support(struct smu_context *smu) 2881 { 2882 bool ret = false; 2883 2884 if (!smu->pm_enabled) 2885 return false; 2886 2887 mutex_lock(&smu->mutex); 2888 2889 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 2890 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 2891 2892 mutex_unlock(&smu->mutex); 2893 2894 return ret; 2895 } 2896 2897 int smu_mode1_reset(struct smu_context *smu) 2898 { 2899 int ret = 0; 2900 2901 if (!smu->pm_enabled) 2902 return -EOPNOTSUPP; 2903 2904 mutex_lock(&smu->mutex); 2905 2906 if (smu->ppt_funcs->mode1_reset) 2907 ret = smu->ppt_funcs->mode1_reset(smu); 2908 2909 mutex_unlock(&smu->mutex); 2910 2911 return ret; 2912 } 2913 2914 static int smu_mode2_reset(void *handle) 2915 { 2916 struct smu_context *smu = handle; 2917 int ret = 0; 2918 2919 if (!smu->pm_enabled) 2920 return -EOPNOTSUPP; 2921 2922 mutex_lock(&smu->mutex); 2923 2924 if (smu->ppt_funcs->mode2_reset) 2925 ret = smu->ppt_funcs->mode2_reset(smu); 2926 2927 mutex_unlock(&smu->mutex); 2928 2929 if (ret) 2930 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2931 2932 return ret; 2933 } 2934 2935 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 2936 struct pp_smu_nv_clock_table *max_clocks) 2937 { 2938 struct smu_context *smu = handle; 2939 int ret = 0; 2940 2941 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2942 return -EOPNOTSUPP; 2943 2944 mutex_lock(&smu->mutex); 2945 2946 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2947 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2948 2949 mutex_unlock(&smu->mutex); 2950 2951 return ret; 2952 } 2953 2954 static int smu_get_uclk_dpm_states(void *handle, 2955 unsigned int *clock_values_in_khz, 2956 unsigned int *num_states) 2957 { 2958 struct smu_context *smu = handle; 2959 int ret = 0; 2960 2961 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2962 return -EOPNOTSUPP; 2963 2964 mutex_lock(&smu->mutex); 2965 2966 if (smu->ppt_funcs->get_uclk_dpm_states) 2967 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2968 2969 mutex_unlock(&smu->mutex); 2970 2971 return ret; 2972 } 2973 2974 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 2975 { 2976 struct smu_context *smu = handle; 2977 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2978 2979 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2980 return -EOPNOTSUPP; 2981 2982 mutex_lock(&smu->mutex); 2983 2984 if (smu->ppt_funcs->get_current_power_state) 2985 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2986 2987 mutex_unlock(&smu->mutex); 2988 2989 return pm_state; 2990 } 2991 2992 static int smu_get_dpm_clock_table(void *handle, 2993 struct dpm_clocks *clock_table) 2994 { 2995 struct smu_context *smu = handle; 2996 int ret = 0; 2997 2998 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2999 return -EOPNOTSUPP; 3000 3001 mutex_lock(&smu->mutex); 3002 3003 if (smu->ppt_funcs->get_dpm_clock_table) 3004 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3005 3006 mutex_unlock(&smu->mutex); 3007 3008 return ret; 3009 } 3010 3011 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3012 { 3013 struct smu_context *smu = handle; 3014 ssize_t size; 3015 3016 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3017 return -EOPNOTSUPP; 3018 3019 if (!smu->ppt_funcs->get_gpu_metrics) 3020 return -EOPNOTSUPP; 3021 3022 mutex_lock(&smu->mutex); 3023 3024 size = smu->ppt_funcs->get_gpu_metrics(smu, table); 3025 3026 mutex_unlock(&smu->mutex); 3027 3028 return size; 3029 } 3030 3031 static int smu_enable_mgpu_fan_boost(void *handle) 3032 { 3033 struct smu_context *smu = handle; 3034 int ret = 0; 3035 3036 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3037 return -EOPNOTSUPP; 3038 3039 mutex_lock(&smu->mutex); 3040 3041 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3042 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3043 3044 mutex_unlock(&smu->mutex); 3045 3046 return ret; 3047 } 3048 3049 static int smu_gfx_state_change_set(void *handle, 3050 uint32_t state) 3051 { 3052 struct smu_context *smu = handle; 3053 int ret = 0; 3054 3055 mutex_lock(&smu->mutex); 3056 if (smu->ppt_funcs->gfx_state_change_set) 3057 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3058 mutex_unlock(&smu->mutex); 3059 3060 return ret; 3061 } 3062 3063 int smu_set_light_sbr(struct smu_context *smu, bool enable) 3064 { 3065 int ret = 0; 3066 3067 mutex_lock(&smu->mutex); 3068 if (smu->ppt_funcs->set_light_sbr) 3069 ret = smu->ppt_funcs->set_light_sbr(smu, enable); 3070 mutex_unlock(&smu->mutex); 3071 3072 return ret; 3073 } 3074 3075 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3076 { 3077 struct smu_context *smu = handle; 3078 struct smu_table_context *smu_table = &smu->smu_table; 3079 struct smu_table *memory_pool = &smu_table->memory_pool; 3080 3081 if (!addr || !size) 3082 return -EINVAL; 3083 3084 *addr = NULL; 3085 *size = 0; 3086 mutex_lock(&smu->mutex); 3087 if (memory_pool->bo) { 3088 *addr = memory_pool->cpu_addr; 3089 *size = memory_pool->size; 3090 } 3091 mutex_unlock(&smu->mutex); 3092 3093 return 0; 3094 } 3095 3096 static const struct amd_pm_funcs swsmu_pm_funcs = { 3097 /* export for sysfs */ 3098 .set_fan_control_mode = smu_pp_set_fan_control_mode, 3099 .get_fan_control_mode = smu_get_fan_control_mode, 3100 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3101 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3102 .force_clock_level = smu_force_ppclk_levels, 3103 .print_clock_levels = smu_print_ppclk_levels, 3104 .force_performance_level = smu_force_performance_level, 3105 .read_sensor = smu_read_sensor, 3106 .get_performance_level = smu_get_performance_level, 3107 .get_current_power_state = smu_get_current_power_state, 3108 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3109 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3110 .get_pp_num_states = smu_get_power_num_states, 3111 .get_pp_table = smu_sys_get_pp_table, 3112 .set_pp_table = smu_sys_set_pp_table, 3113 .switch_power_profile = smu_switch_power_profile, 3114 /* export to amdgpu */ 3115 .dispatch_tasks = smu_handle_dpm_task, 3116 .load_firmware = smu_load_microcode, 3117 .set_powergating_by_smu = smu_dpm_set_power_gate, 3118 .set_power_limit = smu_set_power_limit, 3119 .get_power_limit = smu_get_power_limit, 3120 .get_power_profile_mode = smu_get_power_profile_mode, 3121 .set_power_profile_mode = smu_set_power_profile_mode, 3122 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3123 .set_mp1_state = smu_set_mp1_state, 3124 .gfx_state_change_set = smu_gfx_state_change_set, 3125 /* export to DC */ 3126 .get_sclk = smu_get_sclk, 3127 .get_mclk = smu_get_mclk, 3128 .display_configuration_change = smu_display_configuration_change, 3129 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3130 .display_clock_voltage_request = smu_display_clock_voltage_request, 3131 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3132 .set_active_display_count = smu_set_display_count, 3133 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3134 .get_asic_baco_capability = smu_get_baco_capability, 3135 .set_asic_baco_state = smu_baco_set_state, 3136 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3137 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3138 .asic_reset_mode_2 = smu_mode2_reset, 3139 .set_df_cstate = smu_set_df_cstate, 3140 .set_xgmi_pstate = smu_set_xgmi_pstate, 3141 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3142 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3143 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3144 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3145 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3146 .get_dpm_clock_table = smu_get_dpm_clock_table, 3147 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3148 }; 3149 3150 int smu_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event, 3151 uint64_t event_arg) 3152 { 3153 int ret = -EINVAL; 3154 struct smu_context *smu = &adev->smu; 3155 3156 if (smu->ppt_funcs->wait_for_event) { 3157 mutex_lock(&smu->mutex); 3158 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3159 mutex_unlock(&smu->mutex); 3160 } 3161 3162 return ret; 3163 } 3164