1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "aldebaran_ppt.h" 38 #include "amd_pcie.h" 39 40 /* 41 * DO NOT use these for err/warn/info/debug messages. 42 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 43 * They are more MGPU friendly. 44 */ 45 #undef pr_err 46 #undef pr_warn 47 #undef pr_info 48 #undef pr_debug 49 50 static const struct amd_pm_funcs swsmu_pm_funcs; 51 static int smu_force_smuclk_levels(struct smu_context *smu, 52 enum smu_clk_type clk_type, 53 uint32_t mask); 54 static int smu_handle_task(struct smu_context *smu, 55 enum amd_dpm_forced_level level, 56 enum amd_pp_task task_id, 57 bool lock_needed); 58 static int smu_reset(struct smu_context *smu); 59 static int smu_set_fan_speed_percent(void *handle, u32 speed); 60 static int smu_set_fan_control_mode(struct smu_context *smu, int value); 61 static int smu_set_power_limit(void *handle, uint32_t limit); 62 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 63 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 64 65 static int smu_sys_get_pp_feature_mask(void *handle, 66 char *buf) 67 { 68 struct smu_context *smu = handle; 69 int size = 0; 70 71 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 72 return -EOPNOTSUPP; 73 74 mutex_lock(&smu->mutex); 75 76 size = smu_get_pp_feature_mask(smu, buf); 77 78 mutex_unlock(&smu->mutex); 79 80 return size; 81 } 82 83 static int smu_sys_set_pp_feature_mask(void *handle, 84 uint64_t new_mask) 85 { 86 struct smu_context *smu = handle; 87 int ret = 0; 88 89 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 90 return -EOPNOTSUPP; 91 92 mutex_lock(&smu->mutex); 93 94 ret = smu_set_pp_feature_mask(smu, new_mask); 95 96 mutex_unlock(&smu->mutex); 97 98 return ret; 99 } 100 101 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) 102 { 103 int ret = 0; 104 struct smu_context *smu = &adev->smu; 105 106 if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status) 107 *value = smu_get_gfx_off_status(smu); 108 else 109 ret = -EINVAL; 110 111 return ret; 112 } 113 114 int smu_set_soft_freq_range(struct smu_context *smu, 115 enum smu_clk_type clk_type, 116 uint32_t min, 117 uint32_t max) 118 { 119 int ret = 0; 120 121 mutex_lock(&smu->mutex); 122 123 if (smu->ppt_funcs->set_soft_freq_limited_range) 124 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 125 clk_type, 126 min, 127 max); 128 129 mutex_unlock(&smu->mutex); 130 131 return ret; 132 } 133 134 int smu_get_dpm_freq_range(struct smu_context *smu, 135 enum smu_clk_type clk_type, 136 uint32_t *min, 137 uint32_t *max) 138 { 139 int ret = 0; 140 141 if (!min && !max) 142 return -EINVAL; 143 144 mutex_lock(&smu->mutex); 145 146 if (smu->ppt_funcs->get_dpm_ultimate_freq) 147 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 148 clk_type, 149 min, 150 max); 151 152 mutex_unlock(&smu->mutex); 153 154 return ret; 155 } 156 157 static u32 smu_get_mclk(void *handle, bool low) 158 { 159 struct smu_context *smu = handle; 160 uint32_t clk_freq; 161 int ret = 0; 162 163 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 164 low ? &clk_freq : NULL, 165 !low ? &clk_freq : NULL); 166 if (ret) 167 return 0; 168 return clk_freq * 100; 169 } 170 171 static u32 smu_get_sclk(void *handle, bool low) 172 { 173 struct smu_context *smu = handle; 174 uint32_t clk_freq; 175 int ret = 0; 176 177 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 178 low ? &clk_freq : NULL, 179 !low ? &clk_freq : NULL); 180 if (ret) 181 return 0; 182 return clk_freq * 100; 183 } 184 185 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu, 186 bool enable) 187 { 188 struct smu_power_context *smu_power = &smu->smu_power; 189 struct smu_power_gate *power_gate = &smu_power->power_gate; 190 int ret = 0; 191 192 if (!smu->ppt_funcs->dpm_set_vcn_enable) 193 return 0; 194 195 if (atomic_read(&power_gate->vcn_gated) ^ enable) 196 return 0; 197 198 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 199 if (!ret) 200 atomic_set(&power_gate->vcn_gated, !enable); 201 202 return ret; 203 } 204 205 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 206 bool enable) 207 { 208 struct smu_power_context *smu_power = &smu->smu_power; 209 struct smu_power_gate *power_gate = &smu_power->power_gate; 210 int ret = 0; 211 212 mutex_lock(&power_gate->vcn_gate_lock); 213 214 ret = smu_dpm_set_vcn_enable_locked(smu, enable); 215 216 mutex_unlock(&power_gate->vcn_gate_lock); 217 218 return ret; 219 } 220 221 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu, 222 bool enable) 223 { 224 struct smu_power_context *smu_power = &smu->smu_power; 225 struct smu_power_gate *power_gate = &smu_power->power_gate; 226 int ret = 0; 227 228 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 229 return 0; 230 231 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 232 return 0; 233 234 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 235 if (!ret) 236 atomic_set(&power_gate->jpeg_gated, !enable); 237 238 return ret; 239 } 240 241 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 242 bool enable) 243 { 244 struct smu_power_context *smu_power = &smu->smu_power; 245 struct smu_power_gate *power_gate = &smu_power->power_gate; 246 int ret = 0; 247 248 mutex_lock(&power_gate->jpeg_gate_lock); 249 250 ret = smu_dpm_set_jpeg_enable_locked(smu, enable); 251 252 mutex_unlock(&power_gate->jpeg_gate_lock); 253 254 return ret; 255 } 256 257 /** 258 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 259 * 260 * @handle: smu_context pointer 261 * @block_type: the IP block to power gate/ungate 262 * @gate: to power gate if true, ungate otherwise 263 * 264 * This API uses no smu->mutex lock protection due to: 265 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 266 * This is guarded to be race condition free by the caller. 267 * 2. Or get called on user setting request of power_dpm_force_performance_level. 268 * Under this case, the smu->mutex lock protection is already enforced on 269 * the parent API smu_force_performance_level of the call path. 270 */ 271 static int smu_dpm_set_power_gate(void *handle, 272 uint32_t block_type, 273 bool gate) 274 { 275 struct smu_context *smu = handle; 276 int ret = 0; 277 278 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 279 return -EOPNOTSUPP; 280 281 switch (block_type) { 282 /* 283 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 284 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 285 */ 286 case AMD_IP_BLOCK_TYPE_UVD: 287 case AMD_IP_BLOCK_TYPE_VCN: 288 ret = smu_dpm_set_vcn_enable(smu, !gate); 289 if (ret) 290 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 291 gate ? "gate" : "ungate"); 292 break; 293 case AMD_IP_BLOCK_TYPE_GFX: 294 ret = smu_gfx_off_control(smu, gate); 295 if (ret) 296 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 297 gate ? "enable" : "disable"); 298 break; 299 case AMD_IP_BLOCK_TYPE_SDMA: 300 ret = smu_powergate_sdma(smu, gate); 301 if (ret) 302 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 303 gate ? "gate" : "ungate"); 304 break; 305 case AMD_IP_BLOCK_TYPE_JPEG: 306 ret = smu_dpm_set_jpeg_enable(smu, !gate); 307 if (ret) 308 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 309 gate ? "gate" : "ungate"); 310 break; 311 default: 312 dev_err(smu->adev->dev, "Unsupported block type!\n"); 313 return -EINVAL; 314 } 315 316 return ret; 317 } 318 319 /** 320 * smu_set_user_clk_dependencies - set user profile clock dependencies 321 * 322 * @smu: smu_context pointer 323 * @clk: enum smu_clk_type type 324 * 325 * Enable/Disable the clock dependency for the @clk type. 326 */ 327 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 328 { 329 if (smu->adev->in_suspend) 330 return; 331 332 if (clk == SMU_MCLK) { 333 smu->user_dpm_profile.clk_dependency = 0; 334 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 335 } else if (clk == SMU_FCLK) { 336 /* MCLK takes precedence over FCLK */ 337 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 338 return; 339 340 smu->user_dpm_profile.clk_dependency = 0; 341 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 342 } else if (clk == SMU_SOCCLK) { 343 /* MCLK takes precedence over SOCCLK */ 344 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 345 return; 346 347 smu->user_dpm_profile.clk_dependency = 0; 348 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 349 } else 350 /* Add clk dependencies here, if any */ 351 return; 352 } 353 354 /** 355 * smu_restore_dpm_user_profile - reinstate user dpm profile 356 * 357 * @smu: smu_context pointer 358 * 359 * Restore the saved user power configurations include power limit, 360 * clock frequencies, fan control mode and fan speed. 361 */ 362 static void smu_restore_dpm_user_profile(struct smu_context *smu) 363 { 364 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 365 int ret = 0; 366 367 if (!smu->adev->in_suspend) 368 return; 369 370 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 371 return; 372 373 /* Enable restore flag */ 374 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 375 376 /* set the user dpm power limit */ 377 if (smu->user_dpm_profile.power_limit) { 378 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 379 if (ret) 380 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 381 } 382 383 /* set the user dpm clock configurations */ 384 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 385 enum smu_clk_type clk_type; 386 387 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 388 /* 389 * Iterate over smu clk type and force the saved user clk 390 * configs, skip if clock dependency is enabled 391 */ 392 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 393 smu->user_dpm_profile.clk_mask[clk_type]) { 394 ret = smu_force_smuclk_levels(smu, clk_type, 395 smu->user_dpm_profile.clk_mask[clk_type]); 396 if (ret) 397 dev_err(smu->adev->dev, 398 "Failed to set clock type = %d\n", clk_type); 399 } 400 } 401 } 402 403 /* set the user dpm fan configurations */ 404 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL) { 405 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 406 if (ret) { 407 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 408 return; 409 } 410 411 if (!ret && smu->user_dpm_profile.fan_speed_percent) { 412 ret = smu_set_fan_speed_percent(smu, smu->user_dpm_profile.fan_speed_percent); 413 if (ret) 414 dev_err(smu->adev->dev, "Failed to set manual fan speed\n"); 415 } 416 } 417 418 /* Disable restore flag */ 419 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 420 } 421 422 static int smu_get_power_num_states(void *handle, 423 struct pp_states_info *state_info) 424 { 425 if (!state_info) 426 return -EINVAL; 427 428 /* not support power state */ 429 memset(state_info, 0, sizeof(struct pp_states_info)); 430 state_info->nums = 1; 431 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 432 433 return 0; 434 } 435 436 bool is_support_sw_smu(struct amdgpu_device *adev) 437 { 438 if (adev->asic_type >= CHIP_ARCTURUS) 439 return true; 440 441 return false; 442 } 443 444 bool is_support_cclk_dpm(struct amdgpu_device *adev) 445 { 446 struct smu_context *smu = &adev->smu; 447 448 if (!is_support_sw_smu(adev)) 449 return false; 450 451 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 452 return false; 453 454 return true; 455 } 456 457 458 static int smu_sys_get_pp_table(void *handle, 459 char **table) 460 { 461 struct smu_context *smu = handle; 462 struct smu_table_context *smu_table = &smu->smu_table; 463 uint32_t powerplay_table_size; 464 465 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 466 return -EOPNOTSUPP; 467 468 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 469 return -EINVAL; 470 471 mutex_lock(&smu->mutex); 472 473 if (smu_table->hardcode_pptable) 474 *table = smu_table->hardcode_pptable; 475 else 476 *table = smu_table->power_play_table; 477 478 powerplay_table_size = smu_table->power_play_table_size; 479 480 mutex_unlock(&smu->mutex); 481 482 return powerplay_table_size; 483 } 484 485 static int smu_sys_set_pp_table(void *handle, 486 const char *buf, 487 size_t size) 488 { 489 struct smu_context *smu = handle; 490 struct smu_table_context *smu_table = &smu->smu_table; 491 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 492 int ret = 0; 493 494 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 495 return -EOPNOTSUPP; 496 497 if (header->usStructureSize != size) { 498 dev_err(smu->adev->dev, "pp table size not matched !\n"); 499 return -EIO; 500 } 501 502 mutex_lock(&smu->mutex); 503 if (!smu_table->hardcode_pptable) 504 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 505 if (!smu_table->hardcode_pptable) { 506 ret = -ENOMEM; 507 goto failed; 508 } 509 510 memcpy(smu_table->hardcode_pptable, buf, size); 511 smu_table->power_play_table = smu_table->hardcode_pptable; 512 smu_table->power_play_table_size = size; 513 514 /* 515 * Special hw_fini action(for Navi1x, the DPMs disablement will be 516 * skipped) may be needed for custom pptable uploading. 517 */ 518 smu->uploading_custom_pp_table = true; 519 520 ret = smu_reset(smu); 521 if (ret) 522 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 523 524 smu->uploading_custom_pp_table = false; 525 526 failed: 527 mutex_unlock(&smu->mutex); 528 return ret; 529 } 530 531 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 532 { 533 struct smu_feature *feature = &smu->smu_feature; 534 int ret = 0; 535 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 536 537 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 538 539 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 540 SMU_FEATURE_MAX/32); 541 if (ret) 542 return ret; 543 544 bitmap_or(feature->allowed, feature->allowed, 545 (unsigned long *)allowed_feature_mask, 546 feature->feature_num); 547 548 return ret; 549 } 550 551 static int smu_set_funcs(struct amdgpu_device *adev) 552 { 553 struct smu_context *smu = &adev->smu; 554 555 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 556 smu->od_enabled = true; 557 558 switch (adev->asic_type) { 559 case CHIP_NAVI10: 560 case CHIP_NAVI14: 561 case CHIP_NAVI12: 562 navi10_set_ppt_funcs(smu); 563 break; 564 case CHIP_ARCTURUS: 565 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 566 arcturus_set_ppt_funcs(smu); 567 /* OD is not supported on Arcturus */ 568 smu->od_enabled =false; 569 break; 570 case CHIP_SIENNA_CICHLID: 571 case CHIP_NAVY_FLOUNDER: 572 case CHIP_DIMGREY_CAVEFISH: 573 case CHIP_BEIGE_GOBY: 574 sienna_cichlid_set_ppt_funcs(smu); 575 break; 576 case CHIP_ALDEBARAN: 577 aldebaran_set_ppt_funcs(smu); 578 /* Enable pp_od_clk_voltage node */ 579 smu->od_enabled = true; 580 break; 581 case CHIP_RENOIR: 582 renoir_set_ppt_funcs(smu); 583 break; 584 case CHIP_VANGOGH: 585 vangogh_set_ppt_funcs(smu); 586 break; 587 default: 588 return -EINVAL; 589 } 590 591 return 0; 592 } 593 594 static int smu_early_init(void *handle) 595 { 596 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 597 struct smu_context *smu = &adev->smu; 598 599 smu->adev = adev; 600 smu->pm_enabled = !!amdgpu_dpm; 601 smu->is_apu = false; 602 mutex_init(&smu->mutex); 603 mutex_init(&smu->smu_baco.mutex); 604 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 605 smu->smu_baco.platform_support = false; 606 607 adev->powerplay.pp_handle = smu; 608 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 609 610 return smu_set_funcs(adev); 611 } 612 613 static int smu_set_default_dpm_table(struct smu_context *smu) 614 { 615 struct smu_power_context *smu_power = &smu->smu_power; 616 struct smu_power_gate *power_gate = &smu_power->power_gate; 617 int vcn_gate, jpeg_gate; 618 int ret = 0; 619 620 if (!smu->ppt_funcs->set_default_dpm_table) 621 return 0; 622 623 mutex_lock(&power_gate->vcn_gate_lock); 624 mutex_lock(&power_gate->jpeg_gate_lock); 625 626 vcn_gate = atomic_read(&power_gate->vcn_gated); 627 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 628 629 ret = smu_dpm_set_vcn_enable_locked(smu, true); 630 if (ret) 631 goto err0_out; 632 633 ret = smu_dpm_set_jpeg_enable_locked(smu, true); 634 if (ret) 635 goto err1_out; 636 637 ret = smu->ppt_funcs->set_default_dpm_table(smu); 638 if (ret) 639 dev_err(smu->adev->dev, 640 "Failed to setup default dpm clock tables!\n"); 641 642 smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate); 643 err1_out: 644 smu_dpm_set_vcn_enable_locked(smu, !vcn_gate); 645 err0_out: 646 mutex_unlock(&power_gate->jpeg_gate_lock); 647 mutex_unlock(&power_gate->vcn_gate_lock); 648 649 return ret; 650 } 651 652 653 static int smu_late_init(void *handle) 654 { 655 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 656 struct smu_context *smu = &adev->smu; 657 int ret = 0; 658 659 smu_set_fine_grain_gfx_freq_parameters(smu); 660 661 if (!smu->pm_enabled) 662 return 0; 663 664 ret = smu_post_init(smu); 665 if (ret) { 666 dev_err(adev->dev, "Failed to post smu init!\n"); 667 return ret; 668 } 669 670 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 671 ret = smu_set_default_od_settings(smu); 672 if (ret) { 673 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 674 return ret; 675 } 676 } 677 678 ret = smu_populate_umd_state_clk(smu); 679 if (ret) { 680 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 681 return ret; 682 } 683 684 ret = smu_get_asic_power_limits(smu); 685 if (ret) { 686 dev_err(adev->dev, "Failed to get asic power limits!\n"); 687 return ret; 688 } 689 690 if (!amdgpu_sriov_vf(adev)) 691 smu_get_unique_id(smu); 692 693 smu_get_fan_parameters(smu); 694 695 smu_handle_task(&adev->smu, 696 smu->smu_dpm.dpm_level, 697 AMD_PP_TASK_COMPLETE_INIT, 698 false); 699 700 smu_restore_dpm_user_profile(smu); 701 702 return 0; 703 } 704 705 static int smu_init_fb_allocations(struct smu_context *smu) 706 { 707 struct amdgpu_device *adev = smu->adev; 708 struct smu_table_context *smu_table = &smu->smu_table; 709 struct smu_table *tables = smu_table->tables; 710 struct smu_table *driver_table = &(smu_table->driver_table); 711 uint32_t max_table_size = 0; 712 int ret, i; 713 714 /* VRAM allocation for tool table */ 715 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 716 ret = amdgpu_bo_create_kernel(adev, 717 tables[SMU_TABLE_PMSTATUSLOG].size, 718 tables[SMU_TABLE_PMSTATUSLOG].align, 719 tables[SMU_TABLE_PMSTATUSLOG].domain, 720 &tables[SMU_TABLE_PMSTATUSLOG].bo, 721 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 722 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 723 if (ret) { 724 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 725 return ret; 726 } 727 } 728 729 /* VRAM allocation for driver table */ 730 for (i = 0; i < SMU_TABLE_COUNT; i++) { 731 if (tables[i].size == 0) 732 continue; 733 734 if (i == SMU_TABLE_PMSTATUSLOG) 735 continue; 736 737 if (max_table_size < tables[i].size) 738 max_table_size = tables[i].size; 739 } 740 741 driver_table->size = max_table_size; 742 driver_table->align = PAGE_SIZE; 743 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 744 745 ret = amdgpu_bo_create_kernel(adev, 746 driver_table->size, 747 driver_table->align, 748 driver_table->domain, 749 &driver_table->bo, 750 &driver_table->mc_address, 751 &driver_table->cpu_addr); 752 if (ret) { 753 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 754 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 755 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 756 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 757 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 758 } 759 760 return ret; 761 } 762 763 static int smu_fini_fb_allocations(struct smu_context *smu) 764 { 765 struct smu_table_context *smu_table = &smu->smu_table; 766 struct smu_table *tables = smu_table->tables; 767 struct smu_table *driver_table = &(smu_table->driver_table); 768 769 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 770 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 771 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 772 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 773 774 amdgpu_bo_free_kernel(&driver_table->bo, 775 &driver_table->mc_address, 776 &driver_table->cpu_addr); 777 778 return 0; 779 } 780 781 /** 782 * smu_alloc_memory_pool - allocate memory pool in the system memory 783 * 784 * @smu: amdgpu_device pointer 785 * 786 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 787 * and DramLogSetDramAddr can notify it changed. 788 * 789 * Returns 0 on success, error on failure. 790 */ 791 static int smu_alloc_memory_pool(struct smu_context *smu) 792 { 793 struct amdgpu_device *adev = smu->adev; 794 struct smu_table_context *smu_table = &smu->smu_table; 795 struct smu_table *memory_pool = &smu_table->memory_pool; 796 uint64_t pool_size = smu->pool_size; 797 int ret = 0; 798 799 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 800 return ret; 801 802 memory_pool->size = pool_size; 803 memory_pool->align = PAGE_SIZE; 804 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 805 806 switch (pool_size) { 807 case SMU_MEMORY_POOL_SIZE_256_MB: 808 case SMU_MEMORY_POOL_SIZE_512_MB: 809 case SMU_MEMORY_POOL_SIZE_1_GB: 810 case SMU_MEMORY_POOL_SIZE_2_GB: 811 ret = amdgpu_bo_create_kernel(adev, 812 memory_pool->size, 813 memory_pool->align, 814 memory_pool->domain, 815 &memory_pool->bo, 816 &memory_pool->mc_address, 817 &memory_pool->cpu_addr); 818 if (ret) 819 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 820 break; 821 default: 822 break; 823 } 824 825 return ret; 826 } 827 828 static int smu_free_memory_pool(struct smu_context *smu) 829 { 830 struct smu_table_context *smu_table = &smu->smu_table; 831 struct smu_table *memory_pool = &smu_table->memory_pool; 832 833 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 834 return 0; 835 836 amdgpu_bo_free_kernel(&memory_pool->bo, 837 &memory_pool->mc_address, 838 &memory_pool->cpu_addr); 839 840 memset(memory_pool, 0, sizeof(struct smu_table)); 841 842 return 0; 843 } 844 845 static int smu_alloc_dummy_read_table(struct smu_context *smu) 846 { 847 struct smu_table_context *smu_table = &smu->smu_table; 848 struct smu_table *dummy_read_1_table = 849 &smu_table->dummy_read_1_table; 850 struct amdgpu_device *adev = smu->adev; 851 int ret = 0; 852 853 dummy_read_1_table->size = 0x40000; 854 dummy_read_1_table->align = PAGE_SIZE; 855 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 856 857 ret = amdgpu_bo_create_kernel(adev, 858 dummy_read_1_table->size, 859 dummy_read_1_table->align, 860 dummy_read_1_table->domain, 861 &dummy_read_1_table->bo, 862 &dummy_read_1_table->mc_address, 863 &dummy_read_1_table->cpu_addr); 864 if (ret) 865 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 866 867 return ret; 868 } 869 870 static void smu_free_dummy_read_table(struct smu_context *smu) 871 { 872 struct smu_table_context *smu_table = &smu->smu_table; 873 struct smu_table *dummy_read_1_table = 874 &smu_table->dummy_read_1_table; 875 876 877 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 878 &dummy_read_1_table->mc_address, 879 &dummy_read_1_table->cpu_addr); 880 881 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 882 } 883 884 static int smu_smc_table_sw_init(struct smu_context *smu) 885 { 886 int ret; 887 888 /** 889 * Create smu_table structure, and init smc tables such as 890 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 891 */ 892 ret = smu_init_smc_tables(smu); 893 if (ret) { 894 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 895 return ret; 896 } 897 898 /** 899 * Create smu_power_context structure, and allocate smu_dpm_context and 900 * context size to fill the smu_power_context data. 901 */ 902 ret = smu_init_power(smu); 903 if (ret) { 904 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 905 return ret; 906 } 907 908 /* 909 * allocate vram bos to store smc table contents. 910 */ 911 ret = smu_init_fb_allocations(smu); 912 if (ret) 913 return ret; 914 915 ret = smu_alloc_memory_pool(smu); 916 if (ret) 917 return ret; 918 919 ret = smu_alloc_dummy_read_table(smu); 920 if (ret) 921 return ret; 922 923 ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c); 924 if (ret) 925 return ret; 926 927 return 0; 928 } 929 930 static int smu_smc_table_sw_fini(struct smu_context *smu) 931 { 932 int ret; 933 934 smu_i2c_fini(smu, &smu->adev->pm.smu_i2c); 935 936 smu_free_dummy_read_table(smu); 937 938 ret = smu_free_memory_pool(smu); 939 if (ret) 940 return ret; 941 942 ret = smu_fini_fb_allocations(smu); 943 if (ret) 944 return ret; 945 946 ret = smu_fini_power(smu); 947 if (ret) { 948 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 949 return ret; 950 } 951 952 ret = smu_fini_smc_tables(smu); 953 if (ret) { 954 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 955 return ret; 956 } 957 958 return 0; 959 } 960 961 static void smu_throttling_logging_work_fn(struct work_struct *work) 962 { 963 struct smu_context *smu = container_of(work, struct smu_context, 964 throttling_logging_work); 965 966 smu_log_thermal_throttling(smu); 967 } 968 969 static void smu_interrupt_work_fn(struct work_struct *work) 970 { 971 struct smu_context *smu = container_of(work, struct smu_context, 972 interrupt_work); 973 974 mutex_lock(&smu->mutex); 975 976 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 977 smu->ppt_funcs->interrupt_work(smu); 978 979 mutex_unlock(&smu->mutex); 980 } 981 982 static int smu_sw_init(void *handle) 983 { 984 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 985 struct smu_context *smu = &adev->smu; 986 int ret; 987 988 smu->pool_size = adev->pm.smu_prv_buffer_size; 989 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 990 mutex_init(&smu->smu_feature.mutex); 991 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 992 bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX); 993 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 994 995 mutex_init(&smu->sensor_lock); 996 mutex_init(&smu->metrics_lock); 997 mutex_init(&smu->message_lock); 998 999 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1000 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1001 atomic64_set(&smu->throttle_int_counter, 0); 1002 smu->watermarks_bitmap = 0; 1003 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1004 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1005 1006 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1007 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1008 mutex_init(&smu->smu_power.power_gate.vcn_gate_lock); 1009 mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock); 1010 1011 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1012 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1013 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1014 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1015 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1016 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1017 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1018 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1019 1020 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1021 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1022 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1023 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1024 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1025 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1026 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1027 smu->display_config = &adev->pm.pm_display_cfg; 1028 1029 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1030 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1031 1032 ret = smu_init_microcode(smu); 1033 if (ret) { 1034 dev_err(adev->dev, "Failed to load smu firmware!\n"); 1035 return ret; 1036 } 1037 1038 ret = smu_smc_table_sw_init(smu); 1039 if (ret) { 1040 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1041 return ret; 1042 } 1043 1044 ret = smu_register_irq_handler(smu); 1045 if (ret) { 1046 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1047 return ret; 1048 } 1049 1050 /* If there is no way to query fan control mode, fan control is not supported */ 1051 if (!smu->ppt_funcs->get_fan_control_mode) 1052 smu->adev->pm.no_fan = true; 1053 1054 return 0; 1055 } 1056 1057 static int smu_sw_fini(void *handle) 1058 { 1059 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1060 struct smu_context *smu = &adev->smu; 1061 int ret; 1062 1063 ret = smu_smc_table_sw_fini(smu); 1064 if (ret) { 1065 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1066 return ret; 1067 } 1068 1069 smu_fini_microcode(smu); 1070 1071 return 0; 1072 } 1073 1074 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1075 { 1076 struct amdgpu_device *adev = smu->adev; 1077 struct smu_temperature_range *range = 1078 &smu->thermal_range; 1079 int ret = 0; 1080 1081 if (!smu->ppt_funcs->get_thermal_temperature_range) 1082 return 0; 1083 1084 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1085 if (ret) 1086 return ret; 1087 1088 adev->pm.dpm.thermal.min_temp = range->min; 1089 adev->pm.dpm.thermal.max_temp = range->max; 1090 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1091 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1092 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1093 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1094 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1095 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1096 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1097 1098 return ret; 1099 } 1100 1101 static int smu_smc_hw_setup(struct smu_context *smu) 1102 { 1103 struct amdgpu_device *adev = smu->adev; 1104 uint32_t pcie_gen = 0, pcie_width = 0; 1105 int ret = 0; 1106 1107 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1108 dev_info(adev->dev, "dpm has been enabled\n"); 1109 /* this is needed specifically */ 1110 if ((adev->asic_type >= CHIP_SIENNA_CICHLID) && 1111 (adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) 1112 ret = smu_system_features_control(smu, true); 1113 return ret; 1114 } 1115 1116 ret = smu_init_display_count(smu, 0); 1117 if (ret) { 1118 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1119 return ret; 1120 } 1121 1122 ret = smu_set_driver_table_location(smu); 1123 if (ret) { 1124 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1125 return ret; 1126 } 1127 1128 /* 1129 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1130 */ 1131 ret = smu_set_tool_table_location(smu); 1132 if (ret) { 1133 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1134 return ret; 1135 } 1136 1137 /* 1138 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1139 * pool location. 1140 */ 1141 ret = smu_notify_memory_pool_location(smu); 1142 if (ret) { 1143 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1144 return ret; 1145 } 1146 1147 /* smu_dump_pptable(smu); */ 1148 /* 1149 * Copy pptable bo in the vram to smc with SMU MSGs such as 1150 * SetDriverDramAddr and TransferTableDram2Smu. 1151 */ 1152 ret = smu_write_pptable(smu); 1153 if (ret) { 1154 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1155 return ret; 1156 } 1157 1158 /* issue Run*Btc msg */ 1159 ret = smu_run_btc(smu); 1160 if (ret) 1161 return ret; 1162 1163 ret = smu_feature_set_allowed_mask(smu); 1164 if (ret) { 1165 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1166 return ret; 1167 } 1168 1169 ret = smu_system_features_control(smu, true); 1170 if (ret) { 1171 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1172 return ret; 1173 } 1174 1175 if (!smu_is_dpm_running(smu)) 1176 dev_info(adev->dev, "dpm has been disabled\n"); 1177 1178 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1179 pcie_gen = 3; 1180 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1181 pcie_gen = 2; 1182 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1183 pcie_gen = 1; 1184 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1185 pcie_gen = 0; 1186 1187 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1188 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1189 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1190 */ 1191 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1192 pcie_width = 6; 1193 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1194 pcie_width = 5; 1195 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1196 pcie_width = 4; 1197 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1198 pcie_width = 3; 1199 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1200 pcie_width = 2; 1201 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1202 pcie_width = 1; 1203 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1204 if (ret) { 1205 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1206 return ret; 1207 } 1208 1209 ret = smu_get_thermal_temperature_range(smu); 1210 if (ret) { 1211 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1212 return ret; 1213 } 1214 1215 ret = smu_enable_thermal_alert(smu); 1216 if (ret) { 1217 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1218 return ret; 1219 } 1220 1221 /* 1222 * Set initialized values (get from vbios) to dpm tables context such as 1223 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1224 * type of clks. 1225 */ 1226 ret = smu_set_default_dpm_table(smu); 1227 if (ret) { 1228 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1229 return ret; 1230 } 1231 1232 ret = smu_notify_display_change(smu); 1233 if (ret) 1234 return ret; 1235 1236 /* 1237 * Set min deep sleep dce fclk with bootup value from vbios via 1238 * SetMinDeepSleepDcefclk MSG. 1239 */ 1240 ret = smu_set_min_dcef_deep_sleep(smu, 1241 smu->smu_table.boot_values.dcefclk / 100); 1242 if (ret) 1243 return ret; 1244 1245 return ret; 1246 } 1247 1248 static int smu_start_smc_engine(struct smu_context *smu) 1249 { 1250 struct amdgpu_device *adev = smu->adev; 1251 int ret = 0; 1252 1253 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1254 if (adev->asic_type < CHIP_NAVI10) { 1255 if (smu->ppt_funcs->load_microcode) { 1256 ret = smu->ppt_funcs->load_microcode(smu); 1257 if (ret) 1258 return ret; 1259 } 1260 } 1261 } 1262 1263 if (smu->ppt_funcs->check_fw_status) { 1264 ret = smu->ppt_funcs->check_fw_status(smu); 1265 if (ret) { 1266 dev_err(adev->dev, "SMC is not ready\n"); 1267 return ret; 1268 } 1269 } 1270 1271 /* 1272 * Send msg GetDriverIfVersion to check if the return value is equal 1273 * with DRIVER_IF_VERSION of smc header. 1274 */ 1275 ret = smu_check_fw_version(smu); 1276 if (ret) 1277 return ret; 1278 1279 return ret; 1280 } 1281 1282 static int smu_hw_init(void *handle) 1283 { 1284 int ret; 1285 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1286 struct smu_context *smu = &adev->smu; 1287 1288 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1289 smu->pm_enabled = false; 1290 return 0; 1291 } 1292 1293 ret = smu_start_smc_engine(smu); 1294 if (ret) { 1295 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1296 return ret; 1297 } 1298 1299 if (smu->is_apu) { 1300 smu_powergate_sdma(&adev->smu, false); 1301 smu_dpm_set_vcn_enable(smu, true); 1302 smu_dpm_set_jpeg_enable(smu, true); 1303 smu_set_gfx_cgpg(&adev->smu, true); 1304 } 1305 1306 if (!smu->pm_enabled) 1307 return 0; 1308 1309 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1310 ret = smu_get_vbios_bootup_values(smu); 1311 if (ret) { 1312 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1313 return ret; 1314 } 1315 1316 ret = smu_setup_pptable(smu); 1317 if (ret) { 1318 dev_err(adev->dev, "Failed to setup pptable!\n"); 1319 return ret; 1320 } 1321 1322 ret = smu_get_driver_allowed_feature_mask(smu); 1323 if (ret) 1324 return ret; 1325 1326 ret = smu_smc_hw_setup(smu); 1327 if (ret) { 1328 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1329 return ret; 1330 } 1331 1332 /* 1333 * Move maximum sustainable clock retrieving here considering 1334 * 1. It is not needed on resume(from S3). 1335 * 2. DAL settings come between .hw_init and .late_init of SMU. 1336 * And DAL needs to know the maximum sustainable clocks. Thus 1337 * it cannot be put in .late_init(). 1338 */ 1339 ret = smu_init_max_sustainable_clocks(smu); 1340 if (ret) { 1341 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1342 return ret; 1343 } 1344 1345 adev->pm.dpm_enabled = true; 1346 1347 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1348 1349 return 0; 1350 } 1351 1352 static int smu_disable_dpms(struct smu_context *smu) 1353 { 1354 struct amdgpu_device *adev = smu->adev; 1355 int ret = 0; 1356 bool use_baco = !smu->is_apu && 1357 ((amdgpu_in_reset(adev) && 1358 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1359 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1360 1361 /* 1362 * For custom pptable uploading, skip the DPM features 1363 * disable process on Navi1x ASICs. 1364 * - As the gfx related features are under control of 1365 * RLC on those ASICs. RLC reinitialization will be 1366 * needed to reenable them. That will cost much more 1367 * efforts. 1368 * 1369 * - SMU firmware can handle the DPM reenablement 1370 * properly. 1371 */ 1372 if (smu->uploading_custom_pp_table && 1373 (adev->asic_type >= CHIP_NAVI10) && 1374 (adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) 1375 return 0; 1376 1377 /* 1378 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1379 * on BACO in. Driver involvement is unnecessary. 1380 */ 1381 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 1382 use_baco) 1383 return 0; 1384 1385 /* 1386 * For gpu reset, runpm and hibernation through BACO, 1387 * BACO feature has to be kept enabled. 1388 */ 1389 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1390 ret = smu_disable_all_features_with_exception(smu, 1391 SMU_FEATURE_BACO_BIT); 1392 if (ret) 1393 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1394 } else { 1395 ret = smu_system_features_control(smu, false); 1396 if (ret) 1397 dev_err(adev->dev, "Failed to disable smu features.\n"); 1398 } 1399 1400 if (adev->asic_type >= CHIP_NAVI10 && 1401 adev->gfx.rlc.funcs->stop) 1402 adev->gfx.rlc.funcs->stop(adev); 1403 1404 return ret; 1405 } 1406 1407 static int smu_smc_hw_cleanup(struct smu_context *smu) 1408 { 1409 struct amdgpu_device *adev = smu->adev; 1410 int ret = 0; 1411 1412 cancel_work_sync(&smu->throttling_logging_work); 1413 cancel_work_sync(&smu->interrupt_work); 1414 1415 ret = smu_disable_thermal_alert(smu); 1416 if (ret) { 1417 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1418 return ret; 1419 } 1420 1421 ret = smu_disable_dpms(smu); 1422 if (ret) { 1423 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1424 return ret; 1425 } 1426 1427 return 0; 1428 } 1429 1430 static int smu_hw_fini(void *handle) 1431 { 1432 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1433 struct smu_context *smu = &adev->smu; 1434 1435 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1436 return 0; 1437 1438 if (smu->is_apu) { 1439 smu_powergate_sdma(&adev->smu, true); 1440 smu_dpm_set_vcn_enable(smu, false); 1441 smu_dpm_set_jpeg_enable(smu, false); 1442 } 1443 1444 if (!smu->pm_enabled) 1445 return 0; 1446 1447 adev->pm.dpm_enabled = false; 1448 1449 return smu_smc_hw_cleanup(smu); 1450 } 1451 1452 static int smu_reset(struct smu_context *smu) 1453 { 1454 struct amdgpu_device *adev = smu->adev; 1455 int ret; 1456 1457 amdgpu_gfx_off_ctrl(smu->adev, false); 1458 1459 ret = smu_hw_fini(adev); 1460 if (ret) 1461 return ret; 1462 1463 ret = smu_hw_init(adev); 1464 if (ret) 1465 return ret; 1466 1467 ret = smu_late_init(adev); 1468 if (ret) 1469 return ret; 1470 1471 amdgpu_gfx_off_ctrl(smu->adev, true); 1472 1473 return 0; 1474 } 1475 1476 static int smu_suspend(void *handle) 1477 { 1478 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1479 struct smu_context *smu = &adev->smu; 1480 int ret; 1481 1482 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1483 return 0; 1484 1485 if (!smu->pm_enabled) 1486 return 0; 1487 1488 adev->pm.dpm_enabled = false; 1489 1490 ret = smu_smc_hw_cleanup(smu); 1491 if (ret) 1492 return ret; 1493 1494 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1495 1496 /* skip CGPG when in S0ix */ 1497 if (smu->is_apu && !adev->in_s0ix) 1498 smu_set_gfx_cgpg(&adev->smu, false); 1499 1500 return 0; 1501 } 1502 1503 static int smu_resume(void *handle) 1504 { 1505 int ret; 1506 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1507 struct smu_context *smu = &adev->smu; 1508 1509 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1510 return 0; 1511 1512 if (!smu->pm_enabled) 1513 return 0; 1514 1515 dev_info(adev->dev, "SMU is resuming...\n"); 1516 1517 ret = smu_start_smc_engine(smu); 1518 if (ret) { 1519 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1520 return ret; 1521 } 1522 1523 ret = smu_smc_hw_setup(smu); 1524 if (ret) { 1525 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1526 return ret; 1527 } 1528 1529 if (smu->is_apu) 1530 smu_set_gfx_cgpg(&adev->smu, true); 1531 1532 smu->disable_uclk_switch = 0; 1533 1534 adev->pm.dpm_enabled = true; 1535 1536 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1537 1538 return 0; 1539 } 1540 1541 static int smu_display_configuration_change(void *handle, 1542 const struct amd_pp_display_configuration *display_config) 1543 { 1544 struct smu_context *smu = handle; 1545 int index = 0; 1546 int num_of_active_display = 0; 1547 1548 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1549 return -EOPNOTSUPP; 1550 1551 if (!display_config) 1552 return -EINVAL; 1553 1554 mutex_lock(&smu->mutex); 1555 1556 smu_set_min_dcef_deep_sleep(smu, 1557 display_config->min_dcef_deep_sleep_set_clk / 100); 1558 1559 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1560 if (display_config->displays[index].controller_id != 0) 1561 num_of_active_display++; 1562 } 1563 1564 mutex_unlock(&smu->mutex); 1565 1566 return 0; 1567 } 1568 1569 static int smu_set_clockgating_state(void *handle, 1570 enum amd_clockgating_state state) 1571 { 1572 return 0; 1573 } 1574 1575 static int smu_set_powergating_state(void *handle, 1576 enum amd_powergating_state state) 1577 { 1578 return 0; 1579 } 1580 1581 static int smu_enable_umd_pstate(void *handle, 1582 enum amd_dpm_forced_level *level) 1583 { 1584 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1585 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1586 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1587 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1588 1589 struct smu_context *smu = (struct smu_context*)(handle); 1590 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1591 1592 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1593 return -EINVAL; 1594 1595 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1596 /* enter umd pstate, save current level, disable gfx cg*/ 1597 if (*level & profile_mode_mask) { 1598 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1599 smu_dpm_ctx->enable_umd_pstate = true; 1600 smu_gpo_control(smu, false); 1601 amdgpu_device_ip_set_powergating_state(smu->adev, 1602 AMD_IP_BLOCK_TYPE_GFX, 1603 AMD_PG_STATE_UNGATE); 1604 amdgpu_device_ip_set_clockgating_state(smu->adev, 1605 AMD_IP_BLOCK_TYPE_GFX, 1606 AMD_CG_STATE_UNGATE); 1607 smu_gfx_ulv_control(smu, false); 1608 smu_deep_sleep_control(smu, false); 1609 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1610 } 1611 } else { 1612 /* exit umd pstate, restore level, enable gfx cg*/ 1613 if (!(*level & profile_mode_mask)) { 1614 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1615 *level = smu_dpm_ctx->saved_dpm_level; 1616 smu_dpm_ctx->enable_umd_pstate = false; 1617 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1618 smu_deep_sleep_control(smu, true); 1619 smu_gfx_ulv_control(smu, true); 1620 amdgpu_device_ip_set_clockgating_state(smu->adev, 1621 AMD_IP_BLOCK_TYPE_GFX, 1622 AMD_CG_STATE_GATE); 1623 amdgpu_device_ip_set_powergating_state(smu->adev, 1624 AMD_IP_BLOCK_TYPE_GFX, 1625 AMD_PG_STATE_GATE); 1626 smu_gpo_control(smu, true); 1627 } 1628 } 1629 1630 return 0; 1631 } 1632 1633 static int smu_bump_power_profile_mode(struct smu_context *smu, 1634 long *param, 1635 uint32_t param_size) 1636 { 1637 int ret = 0; 1638 1639 if (smu->ppt_funcs->set_power_profile_mode) 1640 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1641 1642 return ret; 1643 } 1644 1645 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1646 enum amd_dpm_forced_level level, 1647 bool skip_display_settings) 1648 { 1649 int ret = 0; 1650 int index = 0; 1651 long workload; 1652 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1653 1654 if (!skip_display_settings) { 1655 ret = smu_display_config_changed(smu); 1656 if (ret) { 1657 dev_err(smu->adev->dev, "Failed to change display config!"); 1658 return ret; 1659 } 1660 } 1661 1662 ret = smu_apply_clocks_adjust_rules(smu); 1663 if (ret) { 1664 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1665 return ret; 1666 } 1667 1668 if (!skip_display_settings) { 1669 ret = smu_notify_smc_display_config(smu); 1670 if (ret) { 1671 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1672 return ret; 1673 } 1674 } 1675 1676 if (smu_dpm_ctx->dpm_level != level) { 1677 ret = smu_asic_set_performance_level(smu, level); 1678 if (ret) { 1679 dev_err(smu->adev->dev, "Failed to set performance level!"); 1680 return ret; 1681 } 1682 1683 /* update the saved copy */ 1684 smu_dpm_ctx->dpm_level = level; 1685 } 1686 1687 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1688 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1689 index = fls(smu->workload_mask); 1690 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1691 workload = smu->workload_setting[index]; 1692 1693 if (smu->power_profile_mode != workload) 1694 smu_bump_power_profile_mode(smu, &workload, 0); 1695 } 1696 1697 return ret; 1698 } 1699 1700 static int smu_handle_task(struct smu_context *smu, 1701 enum amd_dpm_forced_level level, 1702 enum amd_pp_task task_id, 1703 bool lock_needed) 1704 { 1705 int ret = 0; 1706 1707 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1708 return -EOPNOTSUPP; 1709 1710 if (lock_needed) 1711 mutex_lock(&smu->mutex); 1712 1713 switch (task_id) { 1714 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1715 ret = smu_pre_display_config_changed(smu); 1716 if (ret) 1717 goto out; 1718 ret = smu_adjust_power_state_dynamic(smu, level, false); 1719 break; 1720 case AMD_PP_TASK_COMPLETE_INIT: 1721 case AMD_PP_TASK_READJUST_POWER_STATE: 1722 ret = smu_adjust_power_state_dynamic(smu, level, true); 1723 break; 1724 default: 1725 break; 1726 } 1727 1728 out: 1729 if (lock_needed) 1730 mutex_unlock(&smu->mutex); 1731 1732 return ret; 1733 } 1734 1735 static int smu_handle_dpm_task(void *handle, 1736 enum amd_pp_task task_id, 1737 enum amd_pm_state_type *user_state) 1738 { 1739 struct smu_context *smu = handle; 1740 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1741 1742 return smu_handle_task(smu, smu_dpm->dpm_level, task_id, true); 1743 1744 } 1745 1746 static int smu_switch_power_profile(void *handle, 1747 enum PP_SMC_POWER_PROFILE type, 1748 bool en) 1749 { 1750 struct smu_context *smu = handle; 1751 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1752 long workload; 1753 uint32_t index; 1754 1755 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1756 return -EOPNOTSUPP; 1757 1758 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1759 return -EINVAL; 1760 1761 mutex_lock(&smu->mutex); 1762 1763 if (!en) { 1764 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1765 index = fls(smu->workload_mask); 1766 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1767 workload = smu->workload_setting[index]; 1768 } else { 1769 smu->workload_mask |= (1 << smu->workload_prority[type]); 1770 index = fls(smu->workload_mask); 1771 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1772 workload = smu->workload_setting[index]; 1773 } 1774 1775 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1776 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1777 smu_bump_power_profile_mode(smu, &workload, 0); 1778 1779 mutex_unlock(&smu->mutex); 1780 1781 return 0; 1782 } 1783 1784 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 1785 { 1786 struct smu_context *smu = handle; 1787 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1788 enum amd_dpm_forced_level level; 1789 1790 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1791 return -EOPNOTSUPP; 1792 1793 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1794 return -EINVAL; 1795 1796 mutex_lock(&(smu->mutex)); 1797 level = smu_dpm_ctx->dpm_level; 1798 mutex_unlock(&(smu->mutex)); 1799 1800 return level; 1801 } 1802 1803 static int smu_force_performance_level(void *handle, 1804 enum amd_dpm_forced_level level) 1805 { 1806 struct smu_context *smu = handle; 1807 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1808 int ret = 0; 1809 1810 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1811 return -EOPNOTSUPP; 1812 1813 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1814 return -EINVAL; 1815 1816 mutex_lock(&smu->mutex); 1817 1818 ret = smu_enable_umd_pstate(smu, &level); 1819 if (ret) { 1820 mutex_unlock(&smu->mutex); 1821 return ret; 1822 } 1823 1824 ret = smu_handle_task(smu, level, 1825 AMD_PP_TASK_READJUST_POWER_STATE, 1826 false); 1827 1828 mutex_unlock(&smu->mutex); 1829 1830 /* reset user dpm clock state */ 1831 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1832 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 1833 smu->user_dpm_profile.clk_dependency = 0; 1834 } 1835 1836 return ret; 1837 } 1838 1839 static int smu_set_display_count(void *handle, uint32_t count) 1840 { 1841 struct smu_context *smu = handle; 1842 int ret = 0; 1843 1844 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1845 return -EOPNOTSUPP; 1846 1847 mutex_lock(&smu->mutex); 1848 ret = smu_init_display_count(smu, count); 1849 mutex_unlock(&smu->mutex); 1850 1851 return ret; 1852 } 1853 1854 static int smu_force_smuclk_levels(struct smu_context *smu, 1855 enum smu_clk_type clk_type, 1856 uint32_t mask) 1857 { 1858 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1859 int ret = 0; 1860 1861 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1862 return -EOPNOTSUPP; 1863 1864 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1865 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1866 return -EINVAL; 1867 } 1868 1869 mutex_lock(&smu->mutex); 1870 1871 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 1872 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1873 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 1874 smu->user_dpm_profile.clk_mask[clk_type] = mask; 1875 smu_set_user_clk_dependencies(smu, clk_type); 1876 } 1877 } 1878 1879 mutex_unlock(&smu->mutex); 1880 1881 return ret; 1882 } 1883 1884 static int smu_force_ppclk_levels(void *handle, 1885 enum pp_clock_type type, 1886 uint32_t mask) 1887 { 1888 struct smu_context *smu = handle; 1889 enum smu_clk_type clk_type; 1890 1891 switch (type) { 1892 case PP_SCLK: 1893 clk_type = SMU_SCLK; break; 1894 case PP_MCLK: 1895 clk_type = SMU_MCLK; break; 1896 case PP_PCIE: 1897 clk_type = SMU_PCIE; break; 1898 case PP_SOCCLK: 1899 clk_type = SMU_SOCCLK; break; 1900 case PP_FCLK: 1901 clk_type = SMU_FCLK; break; 1902 case PP_DCEFCLK: 1903 clk_type = SMU_DCEFCLK; break; 1904 case PP_VCLK: 1905 clk_type = SMU_VCLK; break; 1906 case PP_DCLK: 1907 clk_type = SMU_DCLK; break; 1908 case OD_SCLK: 1909 clk_type = SMU_OD_SCLK; break; 1910 case OD_MCLK: 1911 clk_type = SMU_OD_MCLK; break; 1912 case OD_VDDC_CURVE: 1913 clk_type = SMU_OD_VDDC_CURVE; break; 1914 case OD_RANGE: 1915 clk_type = SMU_OD_RANGE; break; 1916 default: 1917 return -EINVAL; 1918 } 1919 1920 return smu_force_smuclk_levels(smu, clk_type, mask); 1921 } 1922 1923 /* 1924 * On system suspending or resetting, the dpm_enabled 1925 * flag will be cleared. So that those SMU services which 1926 * are not supported will be gated. 1927 * However, the mp1 state setting should still be granted 1928 * even if the dpm_enabled cleared. 1929 */ 1930 static int smu_set_mp1_state(void *handle, 1931 enum pp_mp1_state mp1_state) 1932 { 1933 struct smu_context *smu = handle; 1934 int ret = 0; 1935 1936 if (!smu->pm_enabled) 1937 return -EOPNOTSUPP; 1938 1939 mutex_lock(&smu->mutex); 1940 1941 if (smu->ppt_funcs && 1942 smu->ppt_funcs->set_mp1_state) 1943 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 1944 1945 mutex_unlock(&smu->mutex); 1946 1947 return ret; 1948 } 1949 1950 static int smu_set_df_cstate(void *handle, 1951 enum pp_df_cstate state) 1952 { 1953 struct smu_context *smu = handle; 1954 int ret = 0; 1955 1956 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1957 return -EOPNOTSUPP; 1958 1959 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 1960 return 0; 1961 1962 mutex_lock(&smu->mutex); 1963 1964 ret = smu->ppt_funcs->set_df_cstate(smu, state); 1965 if (ret) 1966 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 1967 1968 mutex_unlock(&smu->mutex); 1969 1970 return ret; 1971 } 1972 1973 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 1974 { 1975 int ret = 0; 1976 1977 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1978 return -EOPNOTSUPP; 1979 1980 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 1981 return 0; 1982 1983 mutex_lock(&smu->mutex); 1984 1985 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 1986 if (ret) 1987 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 1988 1989 mutex_unlock(&smu->mutex); 1990 1991 return ret; 1992 } 1993 1994 int smu_write_watermarks_table(struct smu_context *smu) 1995 { 1996 int ret = 0; 1997 1998 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1999 return -EOPNOTSUPP; 2000 2001 mutex_lock(&smu->mutex); 2002 2003 ret = smu_set_watermarks_table(smu, NULL); 2004 2005 mutex_unlock(&smu->mutex); 2006 2007 return ret; 2008 } 2009 2010 static int smu_set_watermarks_for_clock_ranges(void *handle, 2011 struct pp_smu_wm_range_sets *clock_ranges) 2012 { 2013 struct smu_context *smu = handle; 2014 int ret = 0; 2015 2016 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2017 return -EOPNOTSUPP; 2018 2019 if (smu->disable_watermark) 2020 return 0; 2021 2022 mutex_lock(&smu->mutex); 2023 2024 ret = smu_set_watermarks_table(smu, clock_ranges); 2025 2026 mutex_unlock(&smu->mutex); 2027 2028 return ret; 2029 } 2030 2031 int smu_set_ac_dc(struct smu_context *smu) 2032 { 2033 int ret = 0; 2034 2035 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2036 return -EOPNOTSUPP; 2037 2038 /* controlled by firmware */ 2039 if (smu->dc_controlled_by_gpio) 2040 return 0; 2041 2042 mutex_lock(&smu->mutex); 2043 ret = smu_set_power_source(smu, 2044 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2045 SMU_POWER_SOURCE_DC); 2046 if (ret) 2047 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2048 smu->adev->pm.ac_power ? "AC" : "DC"); 2049 mutex_unlock(&smu->mutex); 2050 2051 return ret; 2052 } 2053 2054 const struct amd_ip_funcs smu_ip_funcs = { 2055 .name = "smu", 2056 .early_init = smu_early_init, 2057 .late_init = smu_late_init, 2058 .sw_init = smu_sw_init, 2059 .sw_fini = smu_sw_fini, 2060 .hw_init = smu_hw_init, 2061 .hw_fini = smu_hw_fini, 2062 .suspend = smu_suspend, 2063 .resume = smu_resume, 2064 .is_idle = NULL, 2065 .check_soft_reset = NULL, 2066 .wait_for_idle = NULL, 2067 .soft_reset = NULL, 2068 .set_clockgating_state = smu_set_clockgating_state, 2069 .set_powergating_state = smu_set_powergating_state, 2070 .enable_umd_pstate = smu_enable_umd_pstate, 2071 }; 2072 2073 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 2074 { 2075 .type = AMD_IP_BLOCK_TYPE_SMC, 2076 .major = 11, 2077 .minor = 0, 2078 .rev = 0, 2079 .funcs = &smu_ip_funcs, 2080 }; 2081 2082 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 2083 { 2084 .type = AMD_IP_BLOCK_TYPE_SMC, 2085 .major = 12, 2086 .minor = 0, 2087 .rev = 0, 2088 .funcs = &smu_ip_funcs, 2089 }; 2090 2091 const struct amdgpu_ip_block_version smu_v13_0_ip_block = 2092 { 2093 .type = AMD_IP_BLOCK_TYPE_SMC, 2094 .major = 13, 2095 .minor = 0, 2096 .rev = 0, 2097 .funcs = &smu_ip_funcs, 2098 }; 2099 2100 static int smu_load_microcode(void *handle) 2101 { 2102 struct smu_context *smu = handle; 2103 struct amdgpu_device *adev = smu->adev; 2104 int ret = 0; 2105 2106 if (!smu->pm_enabled) 2107 return -EOPNOTSUPP; 2108 2109 /* This should be used for non PSP loading */ 2110 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2111 return 0; 2112 2113 if (smu->ppt_funcs->load_microcode) { 2114 ret = smu->ppt_funcs->load_microcode(smu); 2115 if (ret) { 2116 dev_err(adev->dev, "Load microcode failed\n"); 2117 return ret; 2118 } 2119 } 2120 2121 if (smu->ppt_funcs->check_fw_status) { 2122 ret = smu->ppt_funcs->check_fw_status(smu); 2123 if (ret) { 2124 dev_err(adev->dev, "SMC is not ready\n"); 2125 return ret; 2126 } 2127 } 2128 2129 return ret; 2130 } 2131 2132 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2133 { 2134 int ret = 0; 2135 2136 mutex_lock(&smu->mutex); 2137 2138 if (smu->ppt_funcs->set_gfx_cgpg) 2139 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2140 2141 mutex_unlock(&smu->mutex); 2142 2143 return ret; 2144 } 2145 2146 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2147 { 2148 struct smu_context *smu = handle; 2149 u32 percent; 2150 int ret = 0; 2151 2152 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2153 return -EOPNOTSUPP; 2154 2155 mutex_lock(&smu->mutex); 2156 2157 if (smu->ppt_funcs->set_fan_speed_percent) { 2158 percent = speed * 100 / smu->fan_max_rpm; 2159 ret = smu->ppt_funcs->set_fan_speed_percent(smu, percent); 2160 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2161 smu->user_dpm_profile.fan_speed_percent = percent; 2162 } 2163 2164 mutex_unlock(&smu->mutex); 2165 2166 return ret; 2167 } 2168 2169 int smu_get_power_limit(struct smu_context *smu, 2170 uint32_t *limit, 2171 enum smu_ppt_limit_level limit_level) 2172 { 2173 uint32_t limit_type = *limit >> 24; 2174 int ret = 0; 2175 2176 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2177 return -EOPNOTSUPP; 2178 2179 mutex_lock(&smu->mutex); 2180 2181 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2182 if (smu->ppt_funcs->get_ppt_limit) 2183 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2184 } else { 2185 switch (limit_level) { 2186 case SMU_PPT_LIMIT_CURRENT: 2187 *limit = smu->current_power_limit; 2188 break; 2189 case SMU_PPT_LIMIT_DEFAULT: 2190 *limit = smu->default_power_limit; 2191 break; 2192 case SMU_PPT_LIMIT_MAX: 2193 *limit = smu->max_power_limit; 2194 break; 2195 default: 2196 break; 2197 } 2198 } 2199 2200 mutex_unlock(&smu->mutex); 2201 2202 return ret; 2203 } 2204 2205 static int smu_set_power_limit(void *handle, uint32_t limit) 2206 { 2207 struct smu_context *smu = handle; 2208 uint32_t limit_type = limit >> 24; 2209 int ret = 0; 2210 2211 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2212 return -EOPNOTSUPP; 2213 2214 mutex_lock(&smu->mutex); 2215 2216 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2217 if (smu->ppt_funcs->set_power_limit) { 2218 ret = smu->ppt_funcs->set_power_limit(smu, limit); 2219 goto out; 2220 } 2221 2222 if (limit > smu->max_power_limit) { 2223 dev_err(smu->adev->dev, 2224 "New power limit (%d) is over the max allowed %d\n", 2225 limit, smu->max_power_limit); 2226 ret = -EINVAL; 2227 goto out; 2228 } 2229 2230 if (!limit) 2231 limit = smu->current_power_limit; 2232 2233 if (smu->ppt_funcs->set_power_limit) { 2234 ret = smu->ppt_funcs->set_power_limit(smu, limit); 2235 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2236 smu->user_dpm_profile.power_limit = limit; 2237 } 2238 2239 out: 2240 mutex_unlock(&smu->mutex); 2241 2242 return ret; 2243 } 2244 2245 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2246 { 2247 int ret = 0; 2248 2249 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2250 return -EOPNOTSUPP; 2251 2252 mutex_lock(&smu->mutex); 2253 2254 if (smu->ppt_funcs->print_clk_levels) 2255 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2256 2257 mutex_unlock(&smu->mutex); 2258 2259 return ret; 2260 } 2261 2262 static int smu_print_ppclk_levels(void *handle, 2263 enum pp_clock_type type, 2264 char *buf) 2265 { 2266 struct smu_context *smu = handle; 2267 enum smu_clk_type clk_type; 2268 2269 switch (type) { 2270 case PP_SCLK: 2271 clk_type = SMU_SCLK; break; 2272 case PP_MCLK: 2273 clk_type = SMU_MCLK; break; 2274 case PP_PCIE: 2275 clk_type = SMU_PCIE; break; 2276 case PP_SOCCLK: 2277 clk_type = SMU_SOCCLK; break; 2278 case PP_FCLK: 2279 clk_type = SMU_FCLK; break; 2280 case PP_DCEFCLK: 2281 clk_type = SMU_DCEFCLK; break; 2282 case PP_VCLK: 2283 clk_type = SMU_VCLK; break; 2284 case PP_DCLK: 2285 clk_type = SMU_DCLK; break; 2286 case OD_SCLK: 2287 clk_type = SMU_OD_SCLK; break; 2288 case OD_MCLK: 2289 clk_type = SMU_OD_MCLK; break; 2290 case OD_VDDC_CURVE: 2291 clk_type = SMU_OD_VDDC_CURVE; break; 2292 case OD_RANGE: 2293 clk_type = SMU_OD_RANGE; break; 2294 case OD_VDDGFX_OFFSET: 2295 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2296 case OD_CCLK: 2297 clk_type = SMU_OD_CCLK; break; 2298 default: 2299 return -EINVAL; 2300 } 2301 2302 return smu_print_smuclk_levels(smu, clk_type, buf); 2303 } 2304 2305 static int smu_od_edit_dpm_table(void *handle, 2306 enum PP_OD_DPM_TABLE_COMMAND type, 2307 long *input, uint32_t size) 2308 { 2309 struct smu_context *smu = handle; 2310 int ret = 0; 2311 2312 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2313 return -EOPNOTSUPP; 2314 2315 mutex_lock(&smu->mutex); 2316 2317 if (smu->ppt_funcs->od_edit_dpm_table) { 2318 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2319 } 2320 2321 mutex_unlock(&smu->mutex); 2322 2323 return ret; 2324 } 2325 2326 static int smu_read_sensor(void *handle, 2327 int sensor, 2328 void *data, 2329 int *size_arg) 2330 { 2331 struct smu_context *smu = handle; 2332 struct smu_umd_pstate_table *pstate_table = 2333 &smu->pstate_table; 2334 int ret = 0; 2335 uint32_t *size, size_val; 2336 2337 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2338 return -EOPNOTSUPP; 2339 2340 if (!data || !size_arg) 2341 return -EINVAL; 2342 2343 size_val = *size_arg; 2344 size = &size_val; 2345 2346 mutex_lock(&smu->mutex); 2347 2348 if (smu->ppt_funcs->read_sensor) 2349 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2350 goto unlock; 2351 2352 switch (sensor) { 2353 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2354 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2355 *size = 4; 2356 break; 2357 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2358 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2359 *size = 4; 2360 break; 2361 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2362 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2); 2363 *size = 8; 2364 break; 2365 case AMDGPU_PP_SENSOR_UVD_POWER: 2366 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2367 *size = 4; 2368 break; 2369 case AMDGPU_PP_SENSOR_VCE_POWER: 2370 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2371 *size = 4; 2372 break; 2373 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2374 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2375 *size = 4; 2376 break; 2377 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2378 *(uint32_t *)data = 0; 2379 *size = 4; 2380 break; 2381 default: 2382 *size = 0; 2383 ret = -EOPNOTSUPP; 2384 break; 2385 } 2386 2387 unlock: 2388 mutex_unlock(&smu->mutex); 2389 2390 // assign uint32_t to int 2391 *size_arg = size_val; 2392 2393 return ret; 2394 } 2395 2396 static int smu_get_power_profile_mode(void *handle, char *buf) 2397 { 2398 struct smu_context *smu = handle; 2399 int ret = 0; 2400 2401 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2402 return -EOPNOTSUPP; 2403 2404 mutex_lock(&smu->mutex); 2405 2406 if (smu->ppt_funcs->get_power_profile_mode) 2407 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf); 2408 2409 mutex_unlock(&smu->mutex); 2410 2411 return ret; 2412 } 2413 2414 static int smu_set_power_profile_mode(void *handle, 2415 long *param, 2416 uint32_t param_size) 2417 { 2418 struct smu_context *smu = handle; 2419 int ret = 0; 2420 2421 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2422 return -EOPNOTSUPP; 2423 2424 mutex_lock(&smu->mutex); 2425 2426 smu_bump_power_profile_mode(smu, param, param_size); 2427 2428 mutex_unlock(&smu->mutex); 2429 2430 return ret; 2431 } 2432 2433 2434 static u32 smu_get_fan_control_mode(void *handle) 2435 { 2436 struct smu_context *smu = handle; 2437 u32 ret = 0; 2438 2439 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2440 return AMD_FAN_CTRL_NONE; 2441 2442 mutex_lock(&smu->mutex); 2443 2444 if (smu->ppt_funcs->get_fan_control_mode) 2445 ret = smu->ppt_funcs->get_fan_control_mode(smu); 2446 2447 mutex_unlock(&smu->mutex); 2448 2449 return ret; 2450 } 2451 2452 static int smu_set_fan_control_mode(struct smu_context *smu, int value) 2453 { 2454 int ret = 0; 2455 2456 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2457 return -EOPNOTSUPP; 2458 2459 mutex_lock(&smu->mutex); 2460 2461 if (smu->ppt_funcs->set_fan_control_mode) { 2462 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2463 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2464 smu->user_dpm_profile.fan_mode = value; 2465 } 2466 2467 mutex_unlock(&smu->mutex); 2468 2469 /* reset user dpm fan speed */ 2470 if (!ret && value != AMD_FAN_CTRL_MANUAL && 2471 !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2472 smu->user_dpm_profile.fan_speed_percent = 0; 2473 2474 return ret; 2475 } 2476 2477 static void smu_pp_set_fan_control_mode(void *handle, u32 value) 2478 { 2479 struct smu_context *smu = handle; 2480 2481 smu_set_fan_control_mode(smu, value); 2482 } 2483 2484 2485 static int smu_get_fan_speed_percent(void *handle, u32 *speed) 2486 { 2487 struct smu_context *smu = handle; 2488 int ret = 0; 2489 uint32_t percent; 2490 2491 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2492 return -EOPNOTSUPP; 2493 2494 mutex_lock(&smu->mutex); 2495 2496 if (smu->ppt_funcs->get_fan_speed_percent) { 2497 ret = smu->ppt_funcs->get_fan_speed_percent(smu, &percent); 2498 if (!ret) { 2499 *speed = percent > 100 ? 100 : percent; 2500 } 2501 } 2502 2503 mutex_unlock(&smu->mutex); 2504 2505 2506 return ret; 2507 } 2508 2509 static int smu_set_fan_speed_percent(void *handle, u32 speed) 2510 { 2511 struct smu_context *smu = handle; 2512 int ret = 0; 2513 2514 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2515 return -EOPNOTSUPP; 2516 2517 mutex_lock(&smu->mutex); 2518 2519 if (smu->ppt_funcs->set_fan_speed_percent) { 2520 if (speed > 100) 2521 speed = 100; 2522 ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed); 2523 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2524 smu->user_dpm_profile.fan_speed_percent = speed; 2525 } 2526 2527 mutex_unlock(&smu->mutex); 2528 2529 return ret; 2530 } 2531 2532 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2533 { 2534 struct smu_context *smu = handle; 2535 int ret = 0; 2536 u32 percent; 2537 2538 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2539 return -EOPNOTSUPP; 2540 2541 mutex_lock(&smu->mutex); 2542 2543 if (smu->ppt_funcs->get_fan_speed_percent) { 2544 ret = smu->ppt_funcs->get_fan_speed_percent(smu, &percent); 2545 *speed = percent * smu->fan_max_rpm / 100; 2546 } 2547 2548 mutex_unlock(&smu->mutex); 2549 2550 return ret; 2551 } 2552 2553 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 2554 { 2555 struct smu_context *smu = handle; 2556 int ret = 0; 2557 2558 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2559 return -EOPNOTSUPP; 2560 2561 mutex_lock(&smu->mutex); 2562 2563 ret = smu_set_min_dcef_deep_sleep(smu, clk); 2564 2565 mutex_unlock(&smu->mutex); 2566 2567 return ret; 2568 } 2569 2570 static int smu_get_clock_by_type_with_latency(void *handle, 2571 enum amd_pp_clock_type type, 2572 struct pp_clock_levels_with_latency *clocks) 2573 { 2574 struct smu_context *smu = handle; 2575 enum smu_clk_type clk_type; 2576 int ret = 0; 2577 2578 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2579 return -EOPNOTSUPP; 2580 2581 mutex_lock(&smu->mutex); 2582 2583 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 2584 switch (type) { 2585 case amd_pp_sys_clock: 2586 clk_type = SMU_GFXCLK; 2587 break; 2588 case amd_pp_mem_clock: 2589 clk_type = SMU_MCLK; 2590 break; 2591 case amd_pp_dcef_clock: 2592 clk_type = SMU_DCEFCLK; 2593 break; 2594 case amd_pp_disp_clock: 2595 clk_type = SMU_DISPCLK; 2596 break; 2597 default: 2598 dev_err(smu->adev->dev, "Invalid clock type!\n"); 2599 mutex_unlock(&smu->mutex); 2600 return -EINVAL; 2601 } 2602 2603 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2604 } 2605 2606 mutex_unlock(&smu->mutex); 2607 2608 return ret; 2609 } 2610 2611 static int smu_display_clock_voltage_request(void *handle, 2612 struct pp_display_clock_request *clock_req) 2613 { 2614 struct smu_context *smu = handle; 2615 int ret = 0; 2616 2617 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2618 return -EOPNOTSUPP; 2619 2620 mutex_lock(&smu->mutex); 2621 2622 if (smu->ppt_funcs->display_clock_voltage_request) 2623 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2624 2625 mutex_unlock(&smu->mutex); 2626 2627 return ret; 2628 } 2629 2630 2631 static int smu_display_disable_memory_clock_switch(void *handle, 2632 bool disable_memory_clock_switch) 2633 { 2634 struct smu_context *smu = handle; 2635 int ret = -EINVAL; 2636 2637 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2638 return -EOPNOTSUPP; 2639 2640 mutex_lock(&smu->mutex); 2641 2642 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2643 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2644 2645 mutex_unlock(&smu->mutex); 2646 2647 return ret; 2648 } 2649 2650 static int smu_set_xgmi_pstate(void *handle, 2651 uint32_t pstate) 2652 { 2653 struct smu_context *smu = handle; 2654 int ret = 0; 2655 2656 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2657 return -EOPNOTSUPP; 2658 2659 mutex_lock(&smu->mutex); 2660 2661 if (smu->ppt_funcs->set_xgmi_pstate) 2662 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2663 2664 mutex_unlock(&smu->mutex); 2665 2666 if(ret) 2667 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2668 2669 return ret; 2670 } 2671 2672 static int smu_get_baco_capability(void *handle, bool *cap) 2673 { 2674 struct smu_context *smu = handle; 2675 int ret = 0; 2676 2677 *cap = false; 2678 2679 if (!smu->pm_enabled) 2680 return 0; 2681 2682 mutex_lock(&smu->mutex); 2683 2684 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2685 *cap = smu->ppt_funcs->baco_is_support(smu); 2686 2687 mutex_unlock(&smu->mutex); 2688 2689 return ret; 2690 } 2691 2692 static int smu_baco_set_state(void *handle, int state) 2693 { 2694 struct smu_context *smu = handle; 2695 int ret = 0; 2696 2697 if (!smu->pm_enabled) 2698 return -EOPNOTSUPP; 2699 2700 if (state == 0) { 2701 mutex_lock(&smu->mutex); 2702 2703 if (smu->ppt_funcs->baco_exit) 2704 ret = smu->ppt_funcs->baco_exit(smu); 2705 2706 mutex_unlock(&smu->mutex); 2707 } else if (state == 1) { 2708 mutex_lock(&smu->mutex); 2709 2710 if (smu->ppt_funcs->baco_enter) 2711 ret = smu->ppt_funcs->baco_enter(smu); 2712 2713 mutex_unlock(&smu->mutex); 2714 2715 } else { 2716 return -EINVAL; 2717 } 2718 2719 if (ret) 2720 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 2721 (state)?"enter":"exit"); 2722 2723 return ret; 2724 } 2725 2726 bool smu_mode1_reset_is_support(struct smu_context *smu) 2727 { 2728 bool ret = false; 2729 2730 if (!smu->pm_enabled) 2731 return false; 2732 2733 mutex_lock(&smu->mutex); 2734 2735 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2736 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2737 2738 mutex_unlock(&smu->mutex); 2739 2740 return ret; 2741 } 2742 2743 bool smu_mode2_reset_is_support(struct smu_context *smu) 2744 { 2745 bool ret = false; 2746 2747 if (!smu->pm_enabled) 2748 return false; 2749 2750 mutex_lock(&smu->mutex); 2751 2752 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 2753 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 2754 2755 mutex_unlock(&smu->mutex); 2756 2757 return ret; 2758 } 2759 2760 int smu_mode1_reset(struct smu_context *smu) 2761 { 2762 int ret = 0; 2763 2764 if (!smu->pm_enabled) 2765 return -EOPNOTSUPP; 2766 2767 mutex_lock(&smu->mutex); 2768 2769 if (smu->ppt_funcs->mode1_reset) 2770 ret = smu->ppt_funcs->mode1_reset(smu); 2771 2772 mutex_unlock(&smu->mutex); 2773 2774 return ret; 2775 } 2776 2777 static int smu_mode2_reset(void *handle) 2778 { 2779 struct smu_context *smu = handle; 2780 int ret = 0; 2781 2782 if (!smu->pm_enabled) 2783 return -EOPNOTSUPP; 2784 2785 mutex_lock(&smu->mutex); 2786 2787 if (smu->ppt_funcs->mode2_reset) 2788 ret = smu->ppt_funcs->mode2_reset(smu); 2789 2790 mutex_unlock(&smu->mutex); 2791 2792 if (ret) 2793 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2794 2795 return ret; 2796 } 2797 2798 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 2799 struct pp_smu_nv_clock_table *max_clocks) 2800 { 2801 struct smu_context *smu = handle; 2802 int ret = 0; 2803 2804 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2805 return -EOPNOTSUPP; 2806 2807 mutex_lock(&smu->mutex); 2808 2809 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2810 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2811 2812 mutex_unlock(&smu->mutex); 2813 2814 return ret; 2815 } 2816 2817 static int smu_get_uclk_dpm_states(void *handle, 2818 unsigned int *clock_values_in_khz, 2819 unsigned int *num_states) 2820 { 2821 struct smu_context *smu = handle; 2822 int ret = 0; 2823 2824 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2825 return -EOPNOTSUPP; 2826 2827 mutex_lock(&smu->mutex); 2828 2829 if (smu->ppt_funcs->get_uclk_dpm_states) 2830 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2831 2832 mutex_unlock(&smu->mutex); 2833 2834 return ret; 2835 } 2836 2837 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 2838 { 2839 struct smu_context *smu = handle; 2840 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2841 2842 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2843 return -EOPNOTSUPP; 2844 2845 mutex_lock(&smu->mutex); 2846 2847 if (smu->ppt_funcs->get_current_power_state) 2848 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2849 2850 mutex_unlock(&smu->mutex); 2851 2852 return pm_state; 2853 } 2854 2855 static int smu_get_dpm_clock_table(void *handle, 2856 struct dpm_clocks *clock_table) 2857 { 2858 struct smu_context *smu = handle; 2859 int ret = 0; 2860 2861 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2862 return -EOPNOTSUPP; 2863 2864 mutex_lock(&smu->mutex); 2865 2866 if (smu->ppt_funcs->get_dpm_clock_table) 2867 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 2868 2869 mutex_unlock(&smu->mutex); 2870 2871 return ret; 2872 } 2873 2874 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 2875 { 2876 struct smu_context *smu = handle; 2877 ssize_t size; 2878 2879 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2880 return -EOPNOTSUPP; 2881 2882 if (!smu->ppt_funcs->get_gpu_metrics) 2883 return -EOPNOTSUPP; 2884 2885 mutex_lock(&smu->mutex); 2886 2887 size = smu->ppt_funcs->get_gpu_metrics(smu, table); 2888 2889 mutex_unlock(&smu->mutex); 2890 2891 return size; 2892 } 2893 2894 static int smu_enable_mgpu_fan_boost(void *handle) 2895 { 2896 struct smu_context *smu = handle; 2897 int ret = 0; 2898 2899 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2900 return -EOPNOTSUPP; 2901 2902 mutex_lock(&smu->mutex); 2903 2904 if (smu->ppt_funcs->enable_mgpu_fan_boost) 2905 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 2906 2907 mutex_unlock(&smu->mutex); 2908 2909 return ret; 2910 } 2911 2912 static int smu_gfx_state_change_set(void *handle, 2913 uint32_t state) 2914 { 2915 struct smu_context *smu = handle; 2916 int ret = 0; 2917 2918 mutex_lock(&smu->mutex); 2919 if (smu->ppt_funcs->gfx_state_change_set) 2920 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 2921 mutex_unlock(&smu->mutex); 2922 2923 return ret; 2924 } 2925 2926 int smu_set_light_sbr(struct smu_context *smu, bool enable) 2927 { 2928 int ret = 0; 2929 2930 mutex_lock(&smu->mutex); 2931 if (smu->ppt_funcs->set_light_sbr) 2932 ret = smu->ppt_funcs->set_light_sbr(smu, enable); 2933 mutex_unlock(&smu->mutex); 2934 2935 return ret; 2936 } 2937 2938 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 2939 { 2940 struct smu_context *smu = handle; 2941 struct smu_table_context *smu_table = &smu->smu_table; 2942 struct smu_table *memory_pool = &smu_table->memory_pool; 2943 2944 if (!addr || !size) 2945 return -EINVAL; 2946 2947 *addr = NULL; 2948 *size = 0; 2949 mutex_lock(&smu->mutex); 2950 if (memory_pool->bo) { 2951 *addr = memory_pool->cpu_addr; 2952 *size = memory_pool->size; 2953 } 2954 mutex_unlock(&smu->mutex); 2955 2956 return 0; 2957 } 2958 2959 static const struct amd_pm_funcs swsmu_pm_funcs = { 2960 /* export for sysfs */ 2961 .set_fan_control_mode = smu_pp_set_fan_control_mode, 2962 .get_fan_control_mode = smu_get_fan_control_mode, 2963 .set_fan_speed_percent = smu_set_fan_speed_percent, 2964 .get_fan_speed_percent = smu_get_fan_speed_percent, 2965 .force_performance_level = smu_force_performance_level, 2966 .read_sensor = smu_read_sensor, 2967 .get_performance_level = smu_get_performance_level, 2968 .get_current_power_state = smu_get_current_power_state, 2969 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 2970 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 2971 .get_pp_num_states = smu_get_power_num_states, 2972 .get_pp_table = smu_sys_get_pp_table, 2973 .set_pp_table = smu_sys_set_pp_table, 2974 .switch_power_profile = smu_switch_power_profile, 2975 /* export to amdgpu */ 2976 .dispatch_tasks = smu_handle_dpm_task, 2977 .set_powergating_by_smu = smu_dpm_set_power_gate, 2978 .set_power_limit = smu_set_power_limit, 2979 .odn_edit_dpm_table = smu_od_edit_dpm_table, 2980 .set_mp1_state = smu_set_mp1_state, 2981 /* export to DC */ 2982 .get_sclk = smu_get_sclk, 2983 .get_mclk = smu_get_mclk, 2984 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 2985 .get_asic_baco_capability = smu_get_baco_capability, 2986 .set_asic_baco_state = smu_baco_set_state, 2987 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 2988 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 2989 .asic_reset_mode_2 = smu_mode2_reset, 2990 .set_df_cstate = smu_set_df_cstate, 2991 .set_xgmi_pstate = smu_set_xgmi_pstate, 2992 .get_gpu_metrics = smu_sys_get_gpu_metrics, 2993 .set_power_profile_mode = smu_set_power_profile_mode, 2994 .get_power_profile_mode = smu_get_power_profile_mode, 2995 .force_clock_level = smu_force_ppclk_levels, 2996 .print_clock_levels = smu_print_ppclk_levels, 2997 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 2998 .get_dpm_clock_table = smu_get_dpm_clock_table, 2999 .display_configuration_change = smu_display_configuration_change, 3000 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3001 .display_clock_voltage_request = smu_display_clock_voltage_request, 3002 .set_active_display_count = smu_set_display_count, 3003 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3004 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3005 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3006 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3007 .load_firmware = smu_load_microcode, 3008 .gfx_state_change_set = smu_gfx_state_change_set, 3009 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3010 }; 3011 3012 int smu_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event, 3013 uint64_t event_arg) 3014 { 3015 int ret = -EINVAL; 3016 struct smu_context *smu = &adev->smu; 3017 3018 if (smu->ppt_funcs->wait_for_event) { 3019 mutex_lock(&smu->mutex); 3020 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3021 mutex_unlock(&smu->mutex); 3022 } 3023 3024 return ret; 3025 } 3026