1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "amd_pcie.h" 38 39 /* 40 * DO NOT use these for err/warn/info/debug messages. 41 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 42 * They are more MGPU friendly. 43 */ 44 #undef pr_err 45 #undef pr_warn 46 #undef pr_info 47 #undef pr_debug 48 49 static const struct amd_pm_funcs swsmu_pm_funcs; 50 static int smu_force_smuclk_levels(struct smu_context *smu, 51 enum smu_clk_type clk_type, 52 uint32_t mask); 53 54 int smu_sys_get_pp_feature_mask(void *handle, char *buf) 55 { 56 struct smu_context *smu = handle; 57 int size = 0; 58 59 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 60 return -EOPNOTSUPP; 61 62 mutex_lock(&smu->mutex); 63 64 size = smu_get_pp_feature_mask(smu, buf); 65 66 mutex_unlock(&smu->mutex); 67 68 return size; 69 } 70 71 int smu_sys_set_pp_feature_mask(void *handle, uint64_t new_mask) 72 { 73 struct smu_context *smu = handle; 74 int ret = 0; 75 76 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 77 return -EOPNOTSUPP; 78 79 mutex_lock(&smu->mutex); 80 81 ret = smu_set_pp_feature_mask(smu, new_mask); 82 83 mutex_unlock(&smu->mutex); 84 85 return ret; 86 } 87 88 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) 89 { 90 int ret = 0; 91 struct smu_context *smu = &adev->smu; 92 93 if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status) 94 *value = smu_get_gfx_off_status(smu); 95 else 96 ret = -EINVAL; 97 98 return ret; 99 } 100 101 int smu_set_soft_freq_range(struct smu_context *smu, 102 enum smu_clk_type clk_type, 103 uint32_t min, 104 uint32_t max) 105 { 106 int ret = 0; 107 108 mutex_lock(&smu->mutex); 109 110 if (smu->ppt_funcs->set_soft_freq_limited_range) 111 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 112 clk_type, 113 min, 114 max); 115 116 mutex_unlock(&smu->mutex); 117 118 return ret; 119 } 120 121 int smu_get_dpm_freq_range(struct smu_context *smu, 122 enum smu_clk_type clk_type, 123 uint32_t *min, 124 uint32_t *max) 125 { 126 int ret = 0; 127 128 if (!min && !max) 129 return -EINVAL; 130 131 mutex_lock(&smu->mutex); 132 133 if (smu->ppt_funcs->get_dpm_ultimate_freq) 134 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 135 clk_type, 136 min, 137 max); 138 139 mutex_unlock(&smu->mutex); 140 141 return ret; 142 } 143 144 u32 smu_get_mclk(void *handle, bool low) 145 { 146 struct smu_context *smu = handle; 147 uint32_t clk_freq; 148 int ret = 0; 149 150 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 151 low ? &clk_freq : NULL, 152 !low ? &clk_freq : NULL); 153 if (ret) 154 return 0; 155 return clk_freq * 100; 156 } 157 158 u32 smu_get_sclk(void *handle, bool low) 159 { 160 struct smu_context *smu = handle; 161 uint32_t clk_freq; 162 int ret = 0; 163 164 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 165 low ? &clk_freq : NULL, 166 !low ? &clk_freq : NULL); 167 if (ret) 168 return 0; 169 return clk_freq * 100; 170 } 171 172 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu, 173 bool enable) 174 { 175 struct smu_power_context *smu_power = &smu->smu_power; 176 struct smu_power_gate *power_gate = &smu_power->power_gate; 177 int ret = 0; 178 179 if (!smu->ppt_funcs->dpm_set_vcn_enable) 180 return 0; 181 182 if (atomic_read(&power_gate->vcn_gated) ^ enable) 183 return 0; 184 185 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 186 if (!ret) 187 atomic_set(&power_gate->vcn_gated, !enable); 188 189 return ret; 190 } 191 192 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 193 bool enable) 194 { 195 struct smu_power_context *smu_power = &smu->smu_power; 196 struct smu_power_gate *power_gate = &smu_power->power_gate; 197 int ret = 0; 198 199 mutex_lock(&power_gate->vcn_gate_lock); 200 201 ret = smu_dpm_set_vcn_enable_locked(smu, enable); 202 203 mutex_unlock(&power_gate->vcn_gate_lock); 204 205 return ret; 206 } 207 208 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu, 209 bool enable) 210 { 211 struct smu_power_context *smu_power = &smu->smu_power; 212 struct smu_power_gate *power_gate = &smu_power->power_gate; 213 int ret = 0; 214 215 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 216 return 0; 217 218 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 219 return 0; 220 221 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 222 if (!ret) 223 atomic_set(&power_gate->jpeg_gated, !enable); 224 225 return ret; 226 } 227 228 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 229 bool enable) 230 { 231 struct smu_power_context *smu_power = &smu->smu_power; 232 struct smu_power_gate *power_gate = &smu_power->power_gate; 233 int ret = 0; 234 235 mutex_lock(&power_gate->jpeg_gate_lock); 236 237 ret = smu_dpm_set_jpeg_enable_locked(smu, enable); 238 239 mutex_unlock(&power_gate->jpeg_gate_lock); 240 241 return ret; 242 } 243 244 /** 245 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 246 * 247 * @handle: smu_context pointer 248 * @block_type: the IP block to power gate/ungate 249 * @gate: to power gate if true, ungate otherwise 250 * 251 * This API uses no smu->mutex lock protection due to: 252 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 253 * This is guarded to be race condition free by the caller. 254 * 2. Or get called on user setting request of power_dpm_force_performance_level. 255 * Under this case, the smu->mutex lock protection is already enforced on 256 * the parent API smu_force_performance_level of the call path. 257 */ 258 int smu_dpm_set_power_gate(void *handle, uint32_t block_type, 259 bool gate) 260 { 261 struct smu_context *smu = handle; 262 int ret = 0; 263 264 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 265 return -EOPNOTSUPP; 266 267 switch (block_type) { 268 /* 269 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 270 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 271 */ 272 case AMD_IP_BLOCK_TYPE_UVD: 273 case AMD_IP_BLOCK_TYPE_VCN: 274 ret = smu_dpm_set_vcn_enable(smu, !gate); 275 if (ret) 276 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 277 gate ? "gate" : "ungate"); 278 break; 279 case AMD_IP_BLOCK_TYPE_GFX: 280 ret = smu_gfx_off_control(smu, gate); 281 if (ret) 282 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 283 gate ? "enable" : "disable"); 284 break; 285 case AMD_IP_BLOCK_TYPE_SDMA: 286 ret = smu_powergate_sdma(smu, gate); 287 if (ret) 288 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 289 gate ? "gate" : "ungate"); 290 break; 291 case AMD_IP_BLOCK_TYPE_JPEG: 292 ret = smu_dpm_set_jpeg_enable(smu, !gate); 293 if (ret) 294 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 295 gate ? "gate" : "ungate"); 296 break; 297 default: 298 dev_err(smu->adev->dev, "Unsupported block type!\n"); 299 return -EINVAL; 300 } 301 302 return ret; 303 } 304 305 /** 306 * smu_set_user_clk_dependencies - set user profile clock dependencies 307 * 308 * @smu: smu_context pointer 309 * @clk: enum smu_clk_type type 310 * 311 * Enable/Disable the clock dependency for the @clk type. 312 */ 313 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 314 { 315 if (smu->adev->in_suspend) 316 return; 317 318 if (clk == SMU_MCLK) { 319 smu->user_dpm_profile.clk_dependency = 0; 320 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 321 } else if (clk == SMU_FCLK) { 322 /* MCLK takes precedence over FCLK */ 323 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 324 return; 325 326 smu->user_dpm_profile.clk_dependency = 0; 327 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 328 } else if (clk == SMU_SOCCLK) { 329 /* MCLK takes precedence over SOCCLK */ 330 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 331 return; 332 333 smu->user_dpm_profile.clk_dependency = 0; 334 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 335 } else 336 /* Add clk dependencies here, if any */ 337 return; 338 } 339 340 /** 341 * smu_restore_dpm_user_profile - reinstate user dpm profile 342 * 343 * @smu: smu_context pointer 344 * 345 * Restore the saved user power configurations include power limit, 346 * clock frequencies, fan control mode and fan speed. 347 */ 348 static void smu_restore_dpm_user_profile(struct smu_context *smu) 349 { 350 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 351 int ret = 0; 352 353 if (!smu->adev->in_suspend) 354 return; 355 356 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 357 return; 358 359 /* Enable restore flag */ 360 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 361 362 /* set the user dpm power limit */ 363 if (smu->user_dpm_profile.power_limit) { 364 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 365 if (ret) 366 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 367 } 368 369 /* set the user dpm clock configurations */ 370 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 371 enum smu_clk_type clk_type; 372 373 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 374 /* 375 * Iterate over smu clk type and force the saved user clk 376 * configs, skip if clock dependency is enabled 377 */ 378 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 379 smu->user_dpm_profile.clk_mask[clk_type]) { 380 ret = smu_force_smuclk_levels(smu, clk_type, 381 smu->user_dpm_profile.clk_mask[clk_type]); 382 if (ret) 383 dev_err(smu->adev->dev, 384 "Failed to set clock type = %d\n", clk_type); 385 } 386 } 387 } 388 389 /* set the user dpm fan configurations */ 390 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL) { 391 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 392 if (ret) { 393 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 394 return; 395 } 396 397 if (!ret && smu->user_dpm_profile.fan_speed_percent) { 398 ret = smu_set_fan_speed_percent(smu, smu->user_dpm_profile.fan_speed_percent); 399 if (ret) 400 dev_err(smu->adev->dev, "Failed to set manual fan speed\n"); 401 } 402 } 403 404 /* Disable restore flag */ 405 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 406 } 407 408 int smu_get_power_num_states(void *handle, 409 struct pp_states_info *state_info) 410 { 411 if (!state_info) 412 return -EINVAL; 413 414 /* not support power state */ 415 memset(state_info, 0, sizeof(struct pp_states_info)); 416 state_info->nums = 1; 417 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 418 419 return 0; 420 } 421 422 bool is_support_sw_smu(struct amdgpu_device *adev) 423 { 424 if (adev->asic_type >= CHIP_ARCTURUS) 425 return true; 426 427 return false; 428 } 429 430 bool is_support_cclk_dpm(struct amdgpu_device *adev) 431 { 432 struct smu_context *smu = &adev->smu; 433 434 if (!is_support_sw_smu(adev)) 435 return false; 436 437 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 438 return false; 439 440 return true; 441 } 442 443 444 int smu_sys_get_pp_table(void *handle, char **table) 445 { 446 struct smu_context *smu = handle; 447 struct smu_table_context *smu_table = &smu->smu_table; 448 uint32_t powerplay_table_size; 449 450 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 451 return -EOPNOTSUPP; 452 453 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 454 return -EINVAL; 455 456 mutex_lock(&smu->mutex); 457 458 if (smu_table->hardcode_pptable) 459 *table = smu_table->hardcode_pptable; 460 else 461 *table = smu_table->power_play_table; 462 463 powerplay_table_size = smu_table->power_play_table_size; 464 465 mutex_unlock(&smu->mutex); 466 467 return powerplay_table_size; 468 } 469 470 int smu_sys_set_pp_table(void *handle, const char *buf, size_t size) 471 { 472 struct smu_context *smu = handle; 473 struct smu_table_context *smu_table = &smu->smu_table; 474 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 475 int ret = 0; 476 477 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 478 return -EOPNOTSUPP; 479 480 if (header->usStructureSize != size) { 481 dev_err(smu->adev->dev, "pp table size not matched !\n"); 482 return -EIO; 483 } 484 485 mutex_lock(&smu->mutex); 486 if (!smu_table->hardcode_pptable) 487 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 488 if (!smu_table->hardcode_pptable) { 489 ret = -ENOMEM; 490 goto failed; 491 } 492 493 memcpy(smu_table->hardcode_pptable, buf, size); 494 smu_table->power_play_table = smu_table->hardcode_pptable; 495 smu_table->power_play_table_size = size; 496 497 /* 498 * Special hw_fini action(for Navi1x, the DPMs disablement will be 499 * skipped) may be needed for custom pptable uploading. 500 */ 501 smu->uploading_custom_pp_table = true; 502 503 ret = smu_reset(smu); 504 if (ret) 505 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 506 507 smu->uploading_custom_pp_table = false; 508 509 failed: 510 mutex_unlock(&smu->mutex); 511 return ret; 512 } 513 514 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 515 { 516 struct smu_feature *feature = &smu->smu_feature; 517 int ret = 0; 518 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 519 520 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 521 522 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 523 SMU_FEATURE_MAX/32); 524 if (ret) 525 return ret; 526 527 bitmap_or(feature->allowed, feature->allowed, 528 (unsigned long *)allowed_feature_mask, 529 feature->feature_num); 530 531 return ret; 532 } 533 534 static int smu_set_funcs(struct amdgpu_device *adev) 535 { 536 struct smu_context *smu = &adev->smu; 537 538 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 539 smu->od_enabled = true; 540 541 switch (adev->asic_type) { 542 case CHIP_NAVI10: 543 case CHIP_NAVI14: 544 case CHIP_NAVI12: 545 navi10_set_ppt_funcs(smu); 546 break; 547 case CHIP_ARCTURUS: 548 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 549 arcturus_set_ppt_funcs(smu); 550 /* OD is not supported on Arcturus */ 551 smu->od_enabled =false; 552 break; 553 case CHIP_SIENNA_CICHLID: 554 case CHIP_NAVY_FLOUNDER: 555 case CHIP_DIMGREY_CAVEFISH: 556 sienna_cichlid_set_ppt_funcs(smu); 557 break; 558 case CHIP_RENOIR: 559 renoir_set_ppt_funcs(smu); 560 break; 561 case CHIP_VANGOGH: 562 vangogh_set_ppt_funcs(smu); 563 break; 564 default: 565 return -EINVAL; 566 } 567 568 return 0; 569 } 570 571 static int smu_early_init(void *handle) 572 { 573 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 574 struct smu_context *smu = &adev->smu; 575 576 smu->adev = adev; 577 smu->pm_enabled = !!amdgpu_dpm; 578 smu->is_apu = false; 579 mutex_init(&smu->mutex); 580 mutex_init(&smu->smu_baco.mutex); 581 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 582 smu->smu_baco.platform_support = false; 583 584 adev->powerplay.pp_handle = smu; 585 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 586 587 return smu_set_funcs(adev); 588 } 589 590 static int smu_set_default_dpm_table(struct smu_context *smu) 591 { 592 struct smu_power_context *smu_power = &smu->smu_power; 593 struct smu_power_gate *power_gate = &smu_power->power_gate; 594 int vcn_gate, jpeg_gate; 595 int ret = 0; 596 597 if (!smu->ppt_funcs->set_default_dpm_table) 598 return 0; 599 600 mutex_lock(&power_gate->vcn_gate_lock); 601 mutex_lock(&power_gate->jpeg_gate_lock); 602 603 vcn_gate = atomic_read(&power_gate->vcn_gated); 604 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 605 606 ret = smu_dpm_set_vcn_enable_locked(smu, true); 607 if (ret) 608 goto err0_out; 609 610 ret = smu_dpm_set_jpeg_enable_locked(smu, true); 611 if (ret) 612 goto err1_out; 613 614 ret = smu->ppt_funcs->set_default_dpm_table(smu); 615 if (ret) 616 dev_err(smu->adev->dev, 617 "Failed to setup default dpm clock tables!\n"); 618 619 smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate); 620 err1_out: 621 smu_dpm_set_vcn_enable_locked(smu, !vcn_gate); 622 err0_out: 623 mutex_unlock(&power_gate->jpeg_gate_lock); 624 mutex_unlock(&power_gate->vcn_gate_lock); 625 626 return ret; 627 } 628 629 static int smu_late_init(void *handle) 630 { 631 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 632 struct smu_context *smu = &adev->smu; 633 int ret = 0; 634 635 smu_set_fine_grain_gfx_freq_parameters(smu); 636 637 if (!smu->pm_enabled) 638 return 0; 639 640 ret = smu_post_init(smu); 641 if (ret) { 642 dev_err(adev->dev, "Failed to post smu init!\n"); 643 return ret; 644 } 645 646 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 647 ret = smu_set_default_od_settings(smu); 648 if (ret) { 649 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 650 return ret; 651 } 652 } 653 654 ret = smu_populate_umd_state_clk(smu); 655 if (ret) { 656 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 657 return ret; 658 } 659 660 ret = smu_get_asic_power_limits(smu); 661 if (ret) { 662 dev_err(adev->dev, "Failed to get asic power limits!\n"); 663 return ret; 664 } 665 666 smu_get_unique_id(smu); 667 668 smu_get_fan_parameters(smu); 669 670 smu_handle_task(&adev->smu, 671 smu->smu_dpm.dpm_level, 672 AMD_PP_TASK_COMPLETE_INIT, 673 false); 674 675 smu_restore_dpm_user_profile(smu); 676 677 return 0; 678 } 679 680 static int smu_init_fb_allocations(struct smu_context *smu) 681 { 682 struct amdgpu_device *adev = smu->adev; 683 struct smu_table_context *smu_table = &smu->smu_table; 684 struct smu_table *tables = smu_table->tables; 685 struct smu_table *driver_table = &(smu_table->driver_table); 686 uint32_t max_table_size = 0; 687 int ret, i; 688 689 /* VRAM allocation for tool table */ 690 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 691 ret = amdgpu_bo_create_kernel(adev, 692 tables[SMU_TABLE_PMSTATUSLOG].size, 693 tables[SMU_TABLE_PMSTATUSLOG].align, 694 tables[SMU_TABLE_PMSTATUSLOG].domain, 695 &tables[SMU_TABLE_PMSTATUSLOG].bo, 696 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 697 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 698 if (ret) { 699 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 700 return ret; 701 } 702 } 703 704 /* VRAM allocation for driver table */ 705 for (i = 0; i < SMU_TABLE_COUNT; i++) { 706 if (tables[i].size == 0) 707 continue; 708 709 if (i == SMU_TABLE_PMSTATUSLOG) 710 continue; 711 712 if (max_table_size < tables[i].size) 713 max_table_size = tables[i].size; 714 } 715 716 driver_table->size = max_table_size; 717 driver_table->align = PAGE_SIZE; 718 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 719 720 ret = amdgpu_bo_create_kernel(adev, 721 driver_table->size, 722 driver_table->align, 723 driver_table->domain, 724 &driver_table->bo, 725 &driver_table->mc_address, 726 &driver_table->cpu_addr); 727 if (ret) { 728 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 729 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 730 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 731 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 732 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 733 } 734 735 return ret; 736 } 737 738 static int smu_fini_fb_allocations(struct smu_context *smu) 739 { 740 struct smu_table_context *smu_table = &smu->smu_table; 741 struct smu_table *tables = smu_table->tables; 742 struct smu_table *driver_table = &(smu_table->driver_table); 743 744 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 745 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 746 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 747 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 748 749 amdgpu_bo_free_kernel(&driver_table->bo, 750 &driver_table->mc_address, 751 &driver_table->cpu_addr); 752 753 return 0; 754 } 755 756 /** 757 * smu_alloc_memory_pool - allocate memory pool in the system memory 758 * 759 * @smu: amdgpu_device pointer 760 * 761 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 762 * and DramLogSetDramAddr can notify it changed. 763 * 764 * Returns 0 on success, error on failure. 765 */ 766 static int smu_alloc_memory_pool(struct smu_context *smu) 767 { 768 struct amdgpu_device *adev = smu->adev; 769 struct smu_table_context *smu_table = &smu->smu_table; 770 struct smu_table *memory_pool = &smu_table->memory_pool; 771 uint64_t pool_size = smu->pool_size; 772 int ret = 0; 773 774 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 775 return ret; 776 777 memory_pool->size = pool_size; 778 memory_pool->align = PAGE_SIZE; 779 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 780 781 switch (pool_size) { 782 case SMU_MEMORY_POOL_SIZE_256_MB: 783 case SMU_MEMORY_POOL_SIZE_512_MB: 784 case SMU_MEMORY_POOL_SIZE_1_GB: 785 case SMU_MEMORY_POOL_SIZE_2_GB: 786 ret = amdgpu_bo_create_kernel(adev, 787 memory_pool->size, 788 memory_pool->align, 789 memory_pool->domain, 790 &memory_pool->bo, 791 &memory_pool->mc_address, 792 &memory_pool->cpu_addr); 793 if (ret) 794 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 795 break; 796 default: 797 break; 798 } 799 800 return ret; 801 } 802 803 static int smu_free_memory_pool(struct smu_context *smu) 804 { 805 struct smu_table_context *smu_table = &smu->smu_table; 806 struct smu_table *memory_pool = &smu_table->memory_pool; 807 808 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 809 return 0; 810 811 amdgpu_bo_free_kernel(&memory_pool->bo, 812 &memory_pool->mc_address, 813 &memory_pool->cpu_addr); 814 815 memset(memory_pool, 0, sizeof(struct smu_table)); 816 817 return 0; 818 } 819 820 static int smu_alloc_dummy_read_table(struct smu_context *smu) 821 { 822 struct smu_table_context *smu_table = &smu->smu_table; 823 struct smu_table *dummy_read_1_table = 824 &smu_table->dummy_read_1_table; 825 struct amdgpu_device *adev = smu->adev; 826 int ret = 0; 827 828 dummy_read_1_table->size = 0x40000; 829 dummy_read_1_table->align = PAGE_SIZE; 830 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 831 832 ret = amdgpu_bo_create_kernel(adev, 833 dummy_read_1_table->size, 834 dummy_read_1_table->align, 835 dummy_read_1_table->domain, 836 &dummy_read_1_table->bo, 837 &dummy_read_1_table->mc_address, 838 &dummy_read_1_table->cpu_addr); 839 if (ret) 840 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 841 842 return ret; 843 } 844 845 static void smu_free_dummy_read_table(struct smu_context *smu) 846 { 847 struct smu_table_context *smu_table = &smu->smu_table; 848 struct smu_table *dummy_read_1_table = 849 &smu_table->dummy_read_1_table; 850 851 852 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 853 &dummy_read_1_table->mc_address, 854 &dummy_read_1_table->cpu_addr); 855 856 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 857 } 858 859 static int smu_smc_table_sw_init(struct smu_context *smu) 860 { 861 int ret; 862 863 /** 864 * Create smu_table structure, and init smc tables such as 865 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 866 */ 867 ret = smu_init_smc_tables(smu); 868 if (ret) { 869 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 870 return ret; 871 } 872 873 /** 874 * Create smu_power_context structure, and allocate smu_dpm_context and 875 * context size to fill the smu_power_context data. 876 */ 877 ret = smu_init_power(smu); 878 if (ret) { 879 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 880 return ret; 881 } 882 883 /* 884 * allocate vram bos to store smc table contents. 885 */ 886 ret = smu_init_fb_allocations(smu); 887 if (ret) 888 return ret; 889 890 ret = smu_alloc_memory_pool(smu); 891 if (ret) 892 return ret; 893 894 ret = smu_alloc_dummy_read_table(smu); 895 if (ret) 896 return ret; 897 898 ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c); 899 if (ret) 900 return ret; 901 902 return 0; 903 } 904 905 static int smu_smc_table_sw_fini(struct smu_context *smu) 906 { 907 int ret; 908 909 smu_i2c_fini(smu, &smu->adev->pm.smu_i2c); 910 911 smu_free_dummy_read_table(smu); 912 913 ret = smu_free_memory_pool(smu); 914 if (ret) 915 return ret; 916 917 ret = smu_fini_fb_allocations(smu); 918 if (ret) 919 return ret; 920 921 ret = smu_fini_power(smu); 922 if (ret) { 923 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 924 return ret; 925 } 926 927 ret = smu_fini_smc_tables(smu); 928 if (ret) { 929 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 930 return ret; 931 } 932 933 return 0; 934 } 935 936 static void smu_throttling_logging_work_fn(struct work_struct *work) 937 { 938 struct smu_context *smu = container_of(work, struct smu_context, 939 throttling_logging_work); 940 941 smu_log_thermal_throttling(smu); 942 } 943 944 static void smu_interrupt_work_fn(struct work_struct *work) 945 { 946 struct smu_context *smu = container_of(work, struct smu_context, 947 interrupt_work); 948 949 mutex_lock(&smu->mutex); 950 951 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 952 smu->ppt_funcs->interrupt_work(smu); 953 954 mutex_unlock(&smu->mutex); 955 } 956 957 static int smu_sw_init(void *handle) 958 { 959 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 960 struct smu_context *smu = &adev->smu; 961 int ret; 962 963 smu->pool_size = adev->pm.smu_prv_buffer_size; 964 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 965 mutex_init(&smu->smu_feature.mutex); 966 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 967 bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX); 968 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 969 970 mutex_init(&smu->sensor_lock); 971 mutex_init(&smu->metrics_lock); 972 mutex_init(&smu->message_lock); 973 974 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 975 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 976 atomic64_set(&smu->throttle_int_counter, 0); 977 smu->watermarks_bitmap = 0; 978 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 979 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 980 981 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 982 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 983 mutex_init(&smu->smu_power.power_gate.vcn_gate_lock); 984 mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock); 985 986 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 987 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 988 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 989 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 990 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 991 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 992 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 993 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 994 995 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 996 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 997 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 998 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 999 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1000 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1001 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1002 smu->display_config = &adev->pm.pm_display_cfg; 1003 1004 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1005 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1006 1007 ret = smu_init_microcode(smu); 1008 if (ret) { 1009 dev_err(adev->dev, "Failed to load smu firmware!\n"); 1010 return ret; 1011 } 1012 1013 ret = smu_smc_table_sw_init(smu); 1014 if (ret) { 1015 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1016 return ret; 1017 } 1018 1019 ret = smu_register_irq_handler(smu); 1020 if (ret) { 1021 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1022 return ret; 1023 } 1024 1025 return 0; 1026 } 1027 1028 static int smu_sw_fini(void *handle) 1029 { 1030 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1031 struct smu_context *smu = &adev->smu; 1032 int ret; 1033 1034 ret = smu_smc_table_sw_fini(smu); 1035 if (ret) { 1036 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1037 return ret; 1038 } 1039 1040 smu_fini_microcode(smu); 1041 1042 return 0; 1043 } 1044 1045 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1046 { 1047 struct amdgpu_device *adev = smu->adev; 1048 struct smu_temperature_range *range = 1049 &smu->thermal_range; 1050 int ret = 0; 1051 1052 if (!smu->ppt_funcs->get_thermal_temperature_range) 1053 return 0; 1054 1055 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1056 if (ret) 1057 return ret; 1058 1059 adev->pm.dpm.thermal.min_temp = range->min; 1060 adev->pm.dpm.thermal.max_temp = range->max; 1061 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1062 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1063 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1064 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1065 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1066 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1067 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1068 1069 return ret; 1070 } 1071 1072 static int smu_smc_hw_setup(struct smu_context *smu) 1073 { 1074 struct amdgpu_device *adev = smu->adev; 1075 uint32_t pcie_gen = 0, pcie_width = 0; 1076 int ret = 0; 1077 1078 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1079 dev_info(adev->dev, "dpm has been enabled\n"); 1080 /* this is needed specifically */ 1081 if ((adev->asic_type >= CHIP_SIENNA_CICHLID) && 1082 (adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) 1083 ret = smu_system_features_control(smu, true); 1084 return ret; 1085 } 1086 1087 ret = smu_init_display_count(smu, 0); 1088 if (ret) { 1089 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1090 return ret; 1091 } 1092 1093 ret = smu_set_driver_table_location(smu); 1094 if (ret) { 1095 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1096 return ret; 1097 } 1098 1099 /* 1100 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1101 */ 1102 ret = smu_set_tool_table_location(smu); 1103 if (ret) { 1104 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1105 return ret; 1106 } 1107 1108 /* 1109 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1110 * pool location. 1111 */ 1112 ret = smu_notify_memory_pool_location(smu); 1113 if (ret) { 1114 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1115 return ret; 1116 } 1117 1118 /* smu_dump_pptable(smu); */ 1119 /* 1120 * Copy pptable bo in the vram to smc with SMU MSGs such as 1121 * SetDriverDramAddr and TransferTableDram2Smu. 1122 */ 1123 ret = smu_write_pptable(smu); 1124 if (ret) { 1125 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1126 return ret; 1127 } 1128 1129 /* issue Run*Btc msg */ 1130 ret = smu_run_btc(smu); 1131 if (ret) 1132 return ret; 1133 1134 ret = smu_feature_set_allowed_mask(smu); 1135 if (ret) { 1136 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1137 return ret; 1138 } 1139 1140 ret = smu_system_features_control(smu, true); 1141 if (ret) { 1142 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1143 return ret; 1144 } 1145 1146 if (!smu_is_dpm_running(smu)) 1147 dev_info(adev->dev, "dpm has been disabled\n"); 1148 1149 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1150 pcie_gen = 3; 1151 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1152 pcie_gen = 2; 1153 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1154 pcie_gen = 1; 1155 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1156 pcie_gen = 0; 1157 1158 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1159 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1160 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1161 */ 1162 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1163 pcie_width = 6; 1164 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1165 pcie_width = 5; 1166 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1167 pcie_width = 4; 1168 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1169 pcie_width = 3; 1170 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1171 pcie_width = 2; 1172 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1173 pcie_width = 1; 1174 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1175 if (ret) { 1176 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1177 return ret; 1178 } 1179 1180 ret = smu_get_thermal_temperature_range(smu); 1181 if (ret) { 1182 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1183 return ret; 1184 } 1185 1186 ret = smu_enable_thermal_alert(smu); 1187 if (ret) { 1188 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1189 return ret; 1190 } 1191 1192 /* 1193 * Set initialized values (get from vbios) to dpm tables context such as 1194 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1195 * type of clks. 1196 */ 1197 ret = smu_set_default_dpm_table(smu); 1198 if (ret) { 1199 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1200 return ret; 1201 } 1202 1203 ret = smu_notify_display_change(smu); 1204 if (ret) 1205 return ret; 1206 1207 /* 1208 * Set min deep sleep dce fclk with bootup value from vbios via 1209 * SetMinDeepSleepDcefclk MSG. 1210 */ 1211 ret = smu_set_min_dcef_deep_sleep(smu, 1212 smu->smu_table.boot_values.dcefclk / 100); 1213 if (ret) 1214 return ret; 1215 1216 return ret; 1217 } 1218 1219 static int smu_start_smc_engine(struct smu_context *smu) 1220 { 1221 struct amdgpu_device *adev = smu->adev; 1222 int ret = 0; 1223 1224 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1225 if (adev->asic_type < CHIP_NAVI10) { 1226 if (smu->ppt_funcs->load_microcode) { 1227 ret = smu->ppt_funcs->load_microcode(smu); 1228 if (ret) 1229 return ret; 1230 } 1231 } 1232 } 1233 1234 if (smu->ppt_funcs->check_fw_status) { 1235 ret = smu->ppt_funcs->check_fw_status(smu); 1236 if (ret) { 1237 dev_err(adev->dev, "SMC is not ready\n"); 1238 return ret; 1239 } 1240 } 1241 1242 /* 1243 * Send msg GetDriverIfVersion to check if the return value is equal 1244 * with DRIVER_IF_VERSION of smc header. 1245 */ 1246 ret = smu_check_fw_version(smu); 1247 if (ret) 1248 return ret; 1249 1250 return ret; 1251 } 1252 1253 static int smu_hw_init(void *handle) 1254 { 1255 int ret; 1256 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1257 struct smu_context *smu = &adev->smu; 1258 1259 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1260 smu->pm_enabled = false; 1261 return 0; 1262 } 1263 1264 ret = smu_start_smc_engine(smu); 1265 if (ret) { 1266 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1267 return ret; 1268 } 1269 1270 if (smu->is_apu) { 1271 smu_powergate_sdma(&adev->smu, false); 1272 smu_dpm_set_vcn_enable(smu, true); 1273 smu_dpm_set_jpeg_enable(smu, true); 1274 smu_set_gfx_cgpg(&adev->smu, true); 1275 } 1276 1277 if (!smu->pm_enabled) 1278 return 0; 1279 1280 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1281 ret = smu_get_vbios_bootup_values(smu); 1282 if (ret) { 1283 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1284 return ret; 1285 } 1286 1287 ret = smu_setup_pptable(smu); 1288 if (ret) { 1289 dev_err(adev->dev, "Failed to setup pptable!\n"); 1290 return ret; 1291 } 1292 1293 ret = smu_get_driver_allowed_feature_mask(smu); 1294 if (ret) 1295 return ret; 1296 1297 ret = smu_smc_hw_setup(smu); 1298 if (ret) { 1299 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1300 return ret; 1301 } 1302 1303 /* 1304 * Move maximum sustainable clock retrieving here considering 1305 * 1. It is not needed on resume(from S3). 1306 * 2. DAL settings come between .hw_init and .late_init of SMU. 1307 * And DAL needs to know the maximum sustainable clocks. Thus 1308 * it cannot be put in .late_init(). 1309 */ 1310 ret = smu_init_max_sustainable_clocks(smu); 1311 if (ret) { 1312 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1313 return ret; 1314 } 1315 1316 adev->pm.dpm_enabled = true; 1317 1318 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1319 1320 return 0; 1321 } 1322 1323 static int smu_disable_dpms(struct smu_context *smu) 1324 { 1325 struct amdgpu_device *adev = smu->adev; 1326 int ret = 0; 1327 bool use_baco = !smu->is_apu && 1328 ((amdgpu_in_reset(adev) && 1329 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1330 ((adev->in_runpm || adev->in_hibernate) && amdgpu_asic_supports_baco(adev))); 1331 1332 /* 1333 * For custom pptable uploading, skip the DPM features 1334 * disable process on Navi1x ASICs. 1335 * - As the gfx related features are under control of 1336 * RLC on those ASICs. RLC reinitialization will be 1337 * needed to reenable them. That will cost much more 1338 * efforts. 1339 * 1340 * - SMU firmware can handle the DPM reenablement 1341 * properly. 1342 */ 1343 if (smu->uploading_custom_pp_table && 1344 (adev->asic_type >= CHIP_NAVI10) && 1345 (adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) 1346 return 0; 1347 1348 /* 1349 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1350 * on BACO in. Driver involvement is unnecessary. 1351 */ 1352 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 1353 use_baco) 1354 return 0; 1355 1356 /* 1357 * For gpu reset, runpm and hibernation through BACO, 1358 * BACO feature has to be kept enabled. 1359 */ 1360 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1361 ret = smu_disable_all_features_with_exception(smu, 1362 SMU_FEATURE_BACO_BIT); 1363 if (ret) 1364 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1365 } else { 1366 ret = smu_system_features_control(smu, false); 1367 if (ret) 1368 dev_err(adev->dev, "Failed to disable smu features.\n"); 1369 } 1370 1371 if (adev->asic_type >= CHIP_NAVI10 && 1372 adev->gfx.rlc.funcs->stop) 1373 adev->gfx.rlc.funcs->stop(adev); 1374 1375 return ret; 1376 } 1377 1378 static int smu_smc_hw_cleanup(struct smu_context *smu) 1379 { 1380 struct amdgpu_device *adev = smu->adev; 1381 int ret = 0; 1382 1383 cancel_work_sync(&smu->throttling_logging_work); 1384 cancel_work_sync(&smu->interrupt_work); 1385 1386 ret = smu_disable_thermal_alert(smu); 1387 if (ret) { 1388 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1389 return ret; 1390 } 1391 1392 ret = smu_disable_dpms(smu); 1393 if (ret) { 1394 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1395 return ret; 1396 } 1397 1398 return 0; 1399 } 1400 1401 static int smu_hw_fini(void *handle) 1402 { 1403 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1404 struct smu_context *smu = &adev->smu; 1405 1406 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1407 return 0; 1408 1409 if (smu->is_apu) { 1410 smu_powergate_sdma(&adev->smu, true); 1411 smu_dpm_set_vcn_enable(smu, false); 1412 smu_dpm_set_jpeg_enable(smu, false); 1413 } 1414 1415 if (!smu->pm_enabled) 1416 return 0; 1417 1418 adev->pm.dpm_enabled = false; 1419 1420 return smu_smc_hw_cleanup(smu); 1421 } 1422 1423 int smu_reset(struct smu_context *smu) 1424 { 1425 struct amdgpu_device *adev = smu->adev; 1426 int ret; 1427 1428 amdgpu_gfx_off_ctrl(smu->adev, false); 1429 1430 ret = smu_hw_fini(adev); 1431 if (ret) 1432 return ret; 1433 1434 ret = smu_hw_init(adev); 1435 if (ret) 1436 return ret; 1437 1438 ret = smu_late_init(adev); 1439 if (ret) 1440 return ret; 1441 1442 amdgpu_gfx_off_ctrl(smu->adev, true); 1443 1444 return 0; 1445 } 1446 1447 static int smu_suspend(void *handle) 1448 { 1449 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1450 struct smu_context *smu = &adev->smu; 1451 int ret; 1452 1453 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1454 return 0; 1455 1456 if (!smu->pm_enabled) 1457 return 0; 1458 1459 adev->pm.dpm_enabled = false; 1460 1461 ret = smu_smc_hw_cleanup(smu); 1462 if (ret) 1463 return ret; 1464 1465 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1466 1467 if (smu->is_apu) 1468 smu_set_gfx_cgpg(&adev->smu, false); 1469 1470 return 0; 1471 } 1472 1473 static int smu_resume(void *handle) 1474 { 1475 int ret; 1476 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1477 struct smu_context *smu = &adev->smu; 1478 1479 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1480 return 0; 1481 1482 if (!smu->pm_enabled) 1483 return 0; 1484 1485 dev_info(adev->dev, "SMU is resuming...\n"); 1486 1487 ret = smu_start_smc_engine(smu); 1488 if (ret) { 1489 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1490 return ret; 1491 } 1492 1493 ret = smu_smc_hw_setup(smu); 1494 if (ret) { 1495 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1496 return ret; 1497 } 1498 1499 if (smu->is_apu) 1500 smu_set_gfx_cgpg(&adev->smu, true); 1501 1502 smu->disable_uclk_switch = 0; 1503 1504 adev->pm.dpm_enabled = true; 1505 1506 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1507 1508 return 0; 1509 } 1510 1511 int smu_display_configuration_change(struct smu_context *smu, 1512 const struct amd_pp_display_configuration *display_config) 1513 { 1514 int index = 0; 1515 int num_of_active_display = 0; 1516 1517 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1518 return -EOPNOTSUPP; 1519 1520 if (!display_config) 1521 return -EINVAL; 1522 1523 mutex_lock(&smu->mutex); 1524 1525 smu_set_min_dcef_deep_sleep(smu, 1526 display_config->min_dcef_deep_sleep_set_clk / 100); 1527 1528 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1529 if (display_config->displays[index].controller_id != 0) 1530 num_of_active_display++; 1531 } 1532 1533 mutex_unlock(&smu->mutex); 1534 1535 return 0; 1536 } 1537 1538 static int smu_set_clockgating_state(void *handle, 1539 enum amd_clockgating_state state) 1540 { 1541 return 0; 1542 } 1543 1544 static int smu_set_powergating_state(void *handle, 1545 enum amd_powergating_state state) 1546 { 1547 return 0; 1548 } 1549 1550 static int smu_enable_umd_pstate(void *handle, 1551 enum amd_dpm_forced_level *level) 1552 { 1553 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1554 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1555 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1556 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1557 1558 struct smu_context *smu = (struct smu_context*)(handle); 1559 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1560 1561 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1562 return -EINVAL; 1563 1564 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1565 /* enter umd pstate, save current level, disable gfx cg*/ 1566 if (*level & profile_mode_mask) { 1567 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1568 smu_dpm_ctx->enable_umd_pstate = true; 1569 smu_gpo_control(smu, false); 1570 amdgpu_device_ip_set_powergating_state(smu->adev, 1571 AMD_IP_BLOCK_TYPE_GFX, 1572 AMD_PG_STATE_UNGATE); 1573 amdgpu_device_ip_set_clockgating_state(smu->adev, 1574 AMD_IP_BLOCK_TYPE_GFX, 1575 AMD_CG_STATE_UNGATE); 1576 smu_gfx_ulv_control(smu, false); 1577 smu_deep_sleep_control(smu, false); 1578 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1579 } 1580 } else { 1581 /* exit umd pstate, restore level, enable gfx cg*/ 1582 if (!(*level & profile_mode_mask)) { 1583 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1584 *level = smu_dpm_ctx->saved_dpm_level; 1585 smu_dpm_ctx->enable_umd_pstate = false; 1586 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1587 smu_deep_sleep_control(smu, true); 1588 smu_gfx_ulv_control(smu, true); 1589 amdgpu_device_ip_set_clockgating_state(smu->adev, 1590 AMD_IP_BLOCK_TYPE_GFX, 1591 AMD_CG_STATE_GATE); 1592 amdgpu_device_ip_set_powergating_state(smu->adev, 1593 AMD_IP_BLOCK_TYPE_GFX, 1594 AMD_PG_STATE_GATE); 1595 smu_gpo_control(smu, true); 1596 } 1597 } 1598 1599 return 0; 1600 } 1601 1602 static int smu_bump_power_profile_mode(struct smu_context *smu, 1603 long *param, 1604 uint32_t param_size) 1605 { 1606 int ret = 0; 1607 1608 if (smu->ppt_funcs->set_power_profile_mode) 1609 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1610 1611 return ret; 1612 } 1613 1614 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1615 enum amd_dpm_forced_level level, 1616 bool skip_display_settings) 1617 { 1618 int ret = 0; 1619 int index = 0; 1620 long workload; 1621 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1622 1623 if (!skip_display_settings) { 1624 ret = smu_display_config_changed(smu); 1625 if (ret) { 1626 dev_err(smu->adev->dev, "Failed to change display config!"); 1627 return ret; 1628 } 1629 } 1630 1631 ret = smu_apply_clocks_adjust_rules(smu); 1632 if (ret) { 1633 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1634 return ret; 1635 } 1636 1637 if (!skip_display_settings) { 1638 ret = smu_notify_smc_display_config(smu); 1639 if (ret) { 1640 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1641 return ret; 1642 } 1643 } 1644 1645 if (smu_dpm_ctx->dpm_level != level) { 1646 ret = smu_asic_set_performance_level(smu, level); 1647 if (ret) { 1648 dev_err(smu->adev->dev, "Failed to set performance level!"); 1649 return ret; 1650 } 1651 1652 /* update the saved copy */ 1653 smu_dpm_ctx->dpm_level = level; 1654 } 1655 1656 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1657 index = fls(smu->workload_mask); 1658 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1659 workload = smu->workload_setting[index]; 1660 1661 if (smu->power_profile_mode != workload) 1662 smu_bump_power_profile_mode(smu, &workload, 0); 1663 } 1664 1665 return ret; 1666 } 1667 1668 int smu_handle_task(struct smu_context *smu, 1669 enum amd_dpm_forced_level level, 1670 enum amd_pp_task task_id, 1671 bool lock_needed) 1672 { 1673 int ret = 0; 1674 1675 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1676 return -EOPNOTSUPP; 1677 1678 if (lock_needed) 1679 mutex_lock(&smu->mutex); 1680 1681 switch (task_id) { 1682 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1683 ret = smu_pre_display_config_changed(smu); 1684 if (ret) 1685 goto out; 1686 ret = smu_adjust_power_state_dynamic(smu, level, false); 1687 break; 1688 case AMD_PP_TASK_COMPLETE_INIT: 1689 case AMD_PP_TASK_READJUST_POWER_STATE: 1690 ret = smu_adjust_power_state_dynamic(smu, level, true); 1691 break; 1692 default: 1693 break; 1694 } 1695 1696 out: 1697 if (lock_needed) 1698 mutex_unlock(&smu->mutex); 1699 1700 return ret; 1701 } 1702 1703 int smu_handle_dpm_task(void *handle, 1704 enum amd_pp_task task_id, 1705 enum amd_pm_state_type *user_state) 1706 { 1707 struct smu_context *smu = handle; 1708 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1709 1710 return smu_handle_task(smu, smu_dpm->dpm_level, task_id, true); 1711 1712 } 1713 1714 1715 int smu_switch_power_profile(void *handle, 1716 enum PP_SMC_POWER_PROFILE type, 1717 bool en) 1718 { 1719 struct smu_context *smu = handle; 1720 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1721 long workload; 1722 uint32_t index; 1723 1724 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1725 return -EOPNOTSUPP; 1726 1727 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1728 return -EINVAL; 1729 1730 mutex_lock(&smu->mutex); 1731 1732 if (!en) { 1733 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1734 index = fls(smu->workload_mask); 1735 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1736 workload = smu->workload_setting[index]; 1737 } else { 1738 smu->workload_mask |= (1 << smu->workload_prority[type]); 1739 index = fls(smu->workload_mask); 1740 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1741 workload = smu->workload_setting[index]; 1742 } 1743 1744 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1745 smu_bump_power_profile_mode(smu, &workload, 0); 1746 1747 mutex_unlock(&smu->mutex); 1748 1749 return 0; 1750 } 1751 1752 enum amd_dpm_forced_level smu_get_performance_level(void *handle) 1753 { 1754 struct smu_context *smu = handle; 1755 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1756 enum amd_dpm_forced_level level; 1757 1758 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1759 return -EOPNOTSUPP; 1760 1761 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1762 return -EINVAL; 1763 1764 mutex_lock(&(smu->mutex)); 1765 level = smu_dpm_ctx->dpm_level; 1766 mutex_unlock(&(smu->mutex)); 1767 1768 return level; 1769 } 1770 1771 int smu_force_performance_level(void *handle, enum amd_dpm_forced_level level) 1772 { 1773 struct smu_context *smu = handle; 1774 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1775 int ret = 0; 1776 1777 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1778 return -EOPNOTSUPP; 1779 1780 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1781 return -EINVAL; 1782 1783 mutex_lock(&smu->mutex); 1784 1785 ret = smu_enable_umd_pstate(smu, &level); 1786 if (ret) { 1787 mutex_unlock(&smu->mutex); 1788 return ret; 1789 } 1790 1791 ret = smu_handle_task(smu, level, 1792 AMD_PP_TASK_READJUST_POWER_STATE, 1793 false); 1794 1795 mutex_unlock(&smu->mutex); 1796 1797 /* reset user dpm clock state */ 1798 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1799 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 1800 smu->user_dpm_profile.clk_dependency = 0; 1801 } 1802 1803 return ret; 1804 } 1805 1806 int smu_set_display_count(struct smu_context *smu, uint32_t count) 1807 { 1808 int ret = 0; 1809 1810 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1811 return -EOPNOTSUPP; 1812 1813 mutex_lock(&smu->mutex); 1814 ret = smu_init_display_count(smu, count); 1815 mutex_unlock(&smu->mutex); 1816 1817 return ret; 1818 } 1819 1820 static int smu_force_smuclk_levels(struct smu_context *smu, 1821 enum smu_clk_type clk_type, 1822 uint32_t mask) 1823 { 1824 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1825 int ret = 0; 1826 1827 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1828 return -EOPNOTSUPP; 1829 1830 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1831 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1832 return -EINVAL; 1833 } 1834 1835 mutex_lock(&smu->mutex); 1836 1837 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 1838 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1839 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 1840 smu->user_dpm_profile.clk_mask[clk_type] = mask; 1841 smu_set_user_clk_dependencies(smu, clk_type); 1842 } 1843 } 1844 1845 mutex_unlock(&smu->mutex); 1846 1847 return ret; 1848 } 1849 1850 int smu_force_ppclk_levels(void *handle, enum pp_clock_type type, uint32_t mask) 1851 { 1852 struct smu_context *smu = handle; 1853 enum smu_clk_type clk_type; 1854 1855 switch (type) { 1856 case PP_SCLK: 1857 clk_type = SMU_SCLK; break; 1858 case PP_MCLK: 1859 clk_type = SMU_MCLK; break; 1860 case PP_PCIE: 1861 clk_type = SMU_PCIE; break; 1862 case PP_SOCCLK: 1863 clk_type = SMU_SOCCLK; break; 1864 case PP_FCLK: 1865 clk_type = SMU_FCLK; break; 1866 case PP_DCEFCLK: 1867 clk_type = SMU_DCEFCLK; break; 1868 case PP_VCLK: 1869 clk_type = SMU_VCLK; break; 1870 case PP_DCLK: 1871 clk_type = SMU_DCLK; break; 1872 case OD_SCLK: 1873 clk_type = SMU_OD_SCLK; break; 1874 case OD_MCLK: 1875 clk_type = SMU_OD_MCLK; break; 1876 case OD_VDDC_CURVE: 1877 clk_type = SMU_OD_VDDC_CURVE; break; 1878 case OD_RANGE: 1879 clk_type = SMU_OD_RANGE; break; 1880 default: 1881 return -EINVAL; 1882 } 1883 1884 return smu_force_smuclk_levels(smu, clk_type, mask); 1885 } 1886 1887 /* 1888 * On system suspending or resetting, the dpm_enabled 1889 * flag will be cleared. So that those SMU services which 1890 * are not supported will be gated. 1891 * However, the mp1 state setting should still be granted 1892 * even if the dpm_enabled cleared. 1893 */ 1894 int smu_set_mp1_state(void *handle, 1895 enum pp_mp1_state mp1_state) 1896 { 1897 struct smu_context *smu = handle; 1898 uint16_t msg; 1899 int ret; 1900 1901 if (!smu->pm_enabled) 1902 return -EOPNOTSUPP; 1903 1904 mutex_lock(&smu->mutex); 1905 1906 switch (mp1_state) { 1907 case PP_MP1_STATE_SHUTDOWN: 1908 msg = SMU_MSG_PrepareMp1ForShutdown; 1909 break; 1910 case PP_MP1_STATE_UNLOAD: 1911 msg = SMU_MSG_PrepareMp1ForUnload; 1912 break; 1913 case PP_MP1_STATE_RESET: 1914 msg = SMU_MSG_PrepareMp1ForReset; 1915 break; 1916 case PP_MP1_STATE_NONE: 1917 default: 1918 mutex_unlock(&smu->mutex); 1919 return 0; 1920 } 1921 1922 ret = smu_send_smc_msg(smu, msg, NULL); 1923 /* some asics may not support those messages */ 1924 if (ret == -EINVAL) 1925 ret = 0; 1926 if (ret) 1927 dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n"); 1928 1929 mutex_unlock(&smu->mutex); 1930 1931 return ret; 1932 } 1933 1934 int smu_set_df_cstate(void *handle, 1935 enum pp_df_cstate state) 1936 { 1937 struct smu_context *smu = handle; 1938 int ret = 0; 1939 1940 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1941 return -EOPNOTSUPP; 1942 1943 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 1944 return 0; 1945 1946 mutex_lock(&smu->mutex); 1947 1948 ret = smu->ppt_funcs->set_df_cstate(smu, state); 1949 if (ret) 1950 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 1951 1952 mutex_unlock(&smu->mutex); 1953 1954 return ret; 1955 } 1956 1957 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 1958 { 1959 int ret = 0; 1960 1961 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1962 return -EOPNOTSUPP; 1963 1964 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 1965 return 0; 1966 1967 mutex_lock(&smu->mutex); 1968 1969 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 1970 if (ret) 1971 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 1972 1973 mutex_unlock(&smu->mutex); 1974 1975 return ret; 1976 } 1977 1978 int smu_write_watermarks_table(struct smu_context *smu) 1979 { 1980 int ret = 0; 1981 1982 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1983 return -EOPNOTSUPP; 1984 1985 mutex_lock(&smu->mutex); 1986 1987 ret = smu_set_watermarks_table(smu, NULL); 1988 1989 mutex_unlock(&smu->mutex); 1990 1991 return ret; 1992 } 1993 1994 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu, 1995 struct pp_smu_wm_range_sets *clock_ranges) 1996 { 1997 int ret = 0; 1998 1999 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2000 return -EOPNOTSUPP; 2001 2002 if (smu->disable_watermark) 2003 return 0; 2004 2005 mutex_lock(&smu->mutex); 2006 2007 ret = smu_set_watermarks_table(smu, clock_ranges); 2008 2009 mutex_unlock(&smu->mutex); 2010 2011 return ret; 2012 } 2013 2014 int smu_set_ac_dc(struct smu_context *smu) 2015 { 2016 int ret = 0; 2017 2018 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2019 return -EOPNOTSUPP; 2020 2021 /* controlled by firmware */ 2022 if (smu->dc_controlled_by_gpio) 2023 return 0; 2024 2025 mutex_lock(&smu->mutex); 2026 ret = smu_set_power_source(smu, 2027 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2028 SMU_POWER_SOURCE_DC); 2029 if (ret) 2030 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2031 smu->adev->pm.ac_power ? "AC" : "DC"); 2032 mutex_unlock(&smu->mutex); 2033 2034 return ret; 2035 } 2036 2037 const struct amd_ip_funcs smu_ip_funcs = { 2038 .name = "smu", 2039 .early_init = smu_early_init, 2040 .late_init = smu_late_init, 2041 .sw_init = smu_sw_init, 2042 .sw_fini = smu_sw_fini, 2043 .hw_init = smu_hw_init, 2044 .hw_fini = smu_hw_fini, 2045 .suspend = smu_suspend, 2046 .resume = smu_resume, 2047 .is_idle = NULL, 2048 .check_soft_reset = NULL, 2049 .wait_for_idle = NULL, 2050 .soft_reset = NULL, 2051 .set_clockgating_state = smu_set_clockgating_state, 2052 .set_powergating_state = smu_set_powergating_state, 2053 .enable_umd_pstate = smu_enable_umd_pstate, 2054 }; 2055 2056 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 2057 { 2058 .type = AMD_IP_BLOCK_TYPE_SMC, 2059 .major = 11, 2060 .minor = 0, 2061 .rev = 0, 2062 .funcs = &smu_ip_funcs, 2063 }; 2064 2065 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 2066 { 2067 .type = AMD_IP_BLOCK_TYPE_SMC, 2068 .major = 12, 2069 .minor = 0, 2070 .rev = 0, 2071 .funcs = &smu_ip_funcs, 2072 }; 2073 2074 int smu_load_microcode(struct smu_context *smu) 2075 { 2076 int ret = 0; 2077 2078 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2079 return -EOPNOTSUPP; 2080 2081 mutex_lock(&smu->mutex); 2082 2083 if (smu->ppt_funcs->load_microcode) 2084 ret = smu->ppt_funcs->load_microcode(smu); 2085 2086 mutex_unlock(&smu->mutex); 2087 2088 return ret; 2089 } 2090 2091 int smu_check_fw_status(struct smu_context *smu) 2092 { 2093 int ret = 0; 2094 2095 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2096 return -EOPNOTSUPP; 2097 2098 mutex_lock(&smu->mutex); 2099 2100 if (smu->ppt_funcs->check_fw_status) 2101 ret = smu->ppt_funcs->check_fw_status(smu); 2102 2103 mutex_unlock(&smu->mutex); 2104 2105 return ret; 2106 } 2107 2108 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2109 { 2110 int ret = 0; 2111 2112 mutex_lock(&smu->mutex); 2113 2114 if (smu->ppt_funcs->set_gfx_cgpg) 2115 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2116 2117 mutex_unlock(&smu->mutex); 2118 2119 return ret; 2120 } 2121 2122 int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2123 { 2124 struct smu_context *smu = handle; 2125 u32 percent; 2126 int ret = 0; 2127 2128 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2129 return -EOPNOTSUPP; 2130 2131 mutex_lock(&smu->mutex); 2132 2133 if (smu->ppt_funcs->set_fan_speed_percent) { 2134 percent = speed * 100 / smu->fan_max_rpm; 2135 ret = smu->ppt_funcs->set_fan_speed_percent(smu, percent); 2136 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2137 smu->user_dpm_profile.fan_speed_percent = percent; 2138 } 2139 2140 mutex_unlock(&smu->mutex); 2141 2142 return ret; 2143 } 2144 2145 int smu_get_power_limit(struct smu_context *smu, 2146 uint32_t *limit, 2147 enum smu_ppt_limit_level limit_level) 2148 { 2149 uint32_t limit_type = *limit >> 24; 2150 int ret = 0; 2151 2152 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2153 return -EOPNOTSUPP; 2154 2155 mutex_lock(&smu->mutex); 2156 2157 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2158 if (smu->ppt_funcs->get_ppt_limit) 2159 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2160 } else { 2161 switch (limit_level) { 2162 case SMU_PPT_LIMIT_CURRENT: 2163 *limit = smu->current_power_limit; 2164 break; 2165 case SMU_PPT_LIMIT_MAX: 2166 *limit = smu->max_power_limit; 2167 break; 2168 default: 2169 break; 2170 } 2171 } 2172 2173 mutex_unlock(&smu->mutex); 2174 2175 return ret; 2176 } 2177 2178 int smu_set_power_limit(void *handle, uint32_t limit) 2179 { 2180 struct smu_context *smu = handle; 2181 uint32_t limit_type = limit >> 24; 2182 int ret = 0; 2183 2184 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2185 return -EOPNOTSUPP; 2186 2187 mutex_lock(&smu->mutex); 2188 2189 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2190 if (smu->ppt_funcs->set_power_limit) { 2191 ret = smu->ppt_funcs->set_power_limit(smu, limit); 2192 goto out; 2193 } 2194 2195 if (limit > smu->max_power_limit) { 2196 dev_err(smu->adev->dev, 2197 "New power limit (%d) is over the max allowed %d\n", 2198 limit, smu->max_power_limit); 2199 goto out; 2200 } 2201 2202 if (!limit) 2203 limit = smu->current_power_limit; 2204 2205 if (smu->ppt_funcs->set_power_limit) { 2206 ret = smu->ppt_funcs->set_power_limit(smu, limit); 2207 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2208 smu->user_dpm_profile.power_limit = limit; 2209 } 2210 2211 out: 2212 mutex_unlock(&smu->mutex); 2213 2214 return ret; 2215 } 2216 2217 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2218 { 2219 int ret = 0; 2220 2221 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2222 return -EOPNOTSUPP; 2223 2224 mutex_lock(&smu->mutex); 2225 2226 if (smu->ppt_funcs->print_clk_levels) 2227 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2228 2229 mutex_unlock(&smu->mutex); 2230 2231 return ret; 2232 } 2233 2234 int smu_print_ppclk_levels(void *handle, enum pp_clock_type type, char *buf) 2235 { 2236 struct smu_context *smu = handle; 2237 enum smu_clk_type clk_type; 2238 2239 switch (type) { 2240 case PP_SCLK: 2241 clk_type = SMU_SCLK; break; 2242 case PP_MCLK: 2243 clk_type = SMU_MCLK; break; 2244 case PP_PCIE: 2245 clk_type = SMU_PCIE; break; 2246 case PP_SOCCLK: 2247 clk_type = SMU_SOCCLK; break; 2248 case PP_FCLK: 2249 clk_type = SMU_FCLK; break; 2250 case PP_DCEFCLK: 2251 clk_type = SMU_DCEFCLK; break; 2252 case PP_VCLK: 2253 clk_type = SMU_VCLK; break; 2254 case PP_DCLK: 2255 clk_type = SMU_DCLK; break; 2256 case OD_SCLK: 2257 clk_type = SMU_OD_SCLK; break; 2258 case OD_MCLK: 2259 clk_type = SMU_OD_MCLK; break; 2260 case OD_VDDC_CURVE: 2261 clk_type = SMU_OD_VDDC_CURVE; break; 2262 case OD_RANGE: 2263 clk_type = SMU_OD_RANGE; break; 2264 case OD_VDDGFX_OFFSET: 2265 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2266 case OD_CCLK: 2267 clk_type = SMU_OD_CCLK; break; 2268 default: 2269 return -EINVAL; 2270 } 2271 2272 return smu_print_smuclk_levels(smu, clk_type, buf); 2273 } 2274 2275 int smu_od_edit_dpm_table(void *handle, 2276 enum PP_OD_DPM_TABLE_COMMAND type, 2277 long *input, uint32_t size) 2278 { 2279 struct smu_context *smu = handle; 2280 int ret = 0; 2281 2282 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2283 return -EOPNOTSUPP; 2284 2285 mutex_lock(&smu->mutex); 2286 2287 if (smu->ppt_funcs->od_edit_dpm_table) { 2288 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2289 } 2290 2291 mutex_unlock(&smu->mutex); 2292 2293 return ret; 2294 } 2295 2296 int smu_read_sensor(void *handle, int sensor, void *data, int *size_arg) 2297 { 2298 struct smu_context *smu = handle; 2299 struct smu_umd_pstate_table *pstate_table = 2300 &smu->pstate_table; 2301 int ret = 0; 2302 uint32_t *size, size_val; 2303 2304 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2305 return -EOPNOTSUPP; 2306 2307 if (!data || !size_arg) 2308 return -EINVAL; 2309 2310 size_val = *size_arg; 2311 size = &size_val; 2312 2313 mutex_lock(&smu->mutex); 2314 2315 if (smu->ppt_funcs->read_sensor) 2316 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2317 goto unlock; 2318 2319 switch (sensor) { 2320 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2321 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2322 *size = 4; 2323 break; 2324 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2325 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2326 *size = 4; 2327 break; 2328 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2329 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2); 2330 *size = 8; 2331 break; 2332 case AMDGPU_PP_SENSOR_UVD_POWER: 2333 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2334 *size = 4; 2335 break; 2336 case AMDGPU_PP_SENSOR_VCE_POWER: 2337 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2338 *size = 4; 2339 break; 2340 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2341 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2342 *size = 4; 2343 break; 2344 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2345 *(uint32_t *)data = 0; 2346 *size = 4; 2347 break; 2348 default: 2349 *size = 0; 2350 ret = -EOPNOTSUPP; 2351 break; 2352 } 2353 2354 unlock: 2355 mutex_unlock(&smu->mutex); 2356 2357 // assign uint32_t to int 2358 *size_arg = size_val; 2359 2360 return ret; 2361 } 2362 2363 int smu_get_power_profile_mode(void *handle, char *buf) 2364 { 2365 struct smu_context *smu = handle; 2366 int ret = 0; 2367 2368 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2369 return -EOPNOTSUPP; 2370 2371 mutex_lock(&smu->mutex); 2372 2373 if (smu->ppt_funcs->get_power_profile_mode) 2374 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf); 2375 2376 mutex_unlock(&smu->mutex); 2377 2378 return ret; 2379 } 2380 2381 int smu_set_power_profile_mode(void *handle, long *param, uint32_t param_size) 2382 { 2383 struct smu_context *smu = handle; 2384 int ret = 0; 2385 2386 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2387 return -EOPNOTSUPP; 2388 2389 mutex_lock(&smu->mutex); 2390 2391 smu_bump_power_profile_mode(smu, param, param_size); 2392 2393 mutex_unlock(&smu->mutex); 2394 2395 return ret; 2396 } 2397 2398 2399 u32 smu_get_fan_control_mode(void *handle) 2400 { 2401 struct smu_context *smu = handle; 2402 u32 ret = 0; 2403 2404 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2405 return AMD_FAN_CTRL_NONE; 2406 2407 mutex_lock(&smu->mutex); 2408 2409 if (smu->ppt_funcs->get_fan_control_mode) 2410 ret = smu->ppt_funcs->get_fan_control_mode(smu); 2411 2412 mutex_unlock(&smu->mutex); 2413 2414 return ret; 2415 } 2416 2417 int smu_set_fan_control_mode(struct smu_context *smu, int value) 2418 { 2419 int ret = 0; 2420 2421 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2422 return -EOPNOTSUPP; 2423 2424 mutex_lock(&smu->mutex); 2425 2426 if (smu->ppt_funcs->set_fan_control_mode) { 2427 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2428 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2429 smu->user_dpm_profile.fan_mode = value; 2430 } 2431 2432 mutex_unlock(&smu->mutex); 2433 2434 /* reset user dpm fan speed */ 2435 if (!ret && value != AMD_FAN_CTRL_MANUAL && 2436 !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2437 smu->user_dpm_profile.fan_speed_percent = 0; 2438 2439 return ret; 2440 } 2441 2442 void smu_pp_set_fan_control_mode(void *handle, u32 value) { 2443 struct smu_context *smu = handle; 2444 2445 smu_set_fan_control_mode(smu, value); 2446 } 2447 2448 2449 int smu_get_fan_speed_percent(void *handle, u32 *speed) 2450 { 2451 struct smu_context *smu = handle; 2452 int ret = 0; 2453 uint32_t percent; 2454 2455 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2456 return -EOPNOTSUPP; 2457 2458 mutex_lock(&smu->mutex); 2459 2460 if (smu->ppt_funcs->get_fan_speed_percent) { 2461 ret = smu->ppt_funcs->get_fan_speed_percent(smu, &percent); 2462 if (!ret) { 2463 *speed = percent > 100 ? 100 : percent; 2464 } 2465 } 2466 2467 mutex_unlock(&smu->mutex); 2468 2469 2470 return ret; 2471 } 2472 2473 int smu_set_fan_speed_percent(void *handle, u32 speed) 2474 { 2475 struct smu_context *smu = handle; 2476 int ret = 0; 2477 2478 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2479 return -EOPNOTSUPP; 2480 2481 mutex_lock(&smu->mutex); 2482 2483 if (smu->ppt_funcs->set_fan_speed_percent) { 2484 if (speed > 100) 2485 speed = 100; 2486 ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed); 2487 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2488 smu->user_dpm_profile.fan_speed_percent = speed; 2489 } 2490 2491 mutex_unlock(&smu->mutex); 2492 2493 return ret; 2494 } 2495 2496 int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2497 { 2498 struct smu_context *smu = handle; 2499 int ret = 0; 2500 u32 percent; 2501 2502 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2503 return -EOPNOTSUPP; 2504 2505 mutex_lock(&smu->mutex); 2506 2507 if (smu->ppt_funcs->get_fan_speed_percent) { 2508 ret = smu->ppt_funcs->get_fan_speed_percent(smu, &percent); 2509 *speed = percent * smu->fan_max_rpm / 100; 2510 } 2511 2512 mutex_unlock(&smu->mutex); 2513 2514 return ret; 2515 } 2516 2517 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk) 2518 { 2519 int ret = 0; 2520 2521 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2522 return -EOPNOTSUPP; 2523 2524 mutex_lock(&smu->mutex); 2525 2526 ret = smu_set_min_dcef_deep_sleep(smu, clk); 2527 2528 mutex_unlock(&smu->mutex); 2529 2530 return ret; 2531 } 2532 2533 int smu_get_clock_by_type_with_latency(struct smu_context *smu, 2534 enum smu_clk_type clk_type, 2535 struct pp_clock_levels_with_latency *clocks) 2536 { 2537 int ret = 0; 2538 2539 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2540 return -EOPNOTSUPP; 2541 2542 mutex_lock(&smu->mutex); 2543 2544 if (smu->ppt_funcs->get_clock_by_type_with_latency) 2545 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2546 2547 mutex_unlock(&smu->mutex); 2548 2549 return ret; 2550 } 2551 2552 int smu_display_clock_voltage_request(struct smu_context *smu, 2553 struct pp_display_clock_request *clock_req) 2554 { 2555 int ret = 0; 2556 2557 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2558 return -EOPNOTSUPP; 2559 2560 mutex_lock(&smu->mutex); 2561 2562 if (smu->ppt_funcs->display_clock_voltage_request) 2563 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2564 2565 mutex_unlock(&smu->mutex); 2566 2567 return ret; 2568 } 2569 2570 2571 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch) 2572 { 2573 int ret = -EINVAL; 2574 2575 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2576 return -EOPNOTSUPP; 2577 2578 mutex_lock(&smu->mutex); 2579 2580 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2581 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2582 2583 mutex_unlock(&smu->mutex); 2584 2585 return ret; 2586 } 2587 2588 int smu_set_xgmi_pstate(void *handle, 2589 uint32_t pstate) 2590 { 2591 struct smu_context *smu = handle; 2592 int ret = 0; 2593 2594 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2595 return -EOPNOTSUPP; 2596 2597 mutex_lock(&smu->mutex); 2598 2599 if (smu->ppt_funcs->set_xgmi_pstate) 2600 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2601 2602 mutex_unlock(&smu->mutex); 2603 2604 if(ret) 2605 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2606 2607 return ret; 2608 } 2609 2610 int smu_set_azalia_d3_pme(struct smu_context *smu) 2611 { 2612 int ret = 0; 2613 2614 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2615 return -EOPNOTSUPP; 2616 2617 mutex_lock(&smu->mutex); 2618 2619 if (smu->ppt_funcs->set_azalia_d3_pme) 2620 ret = smu->ppt_funcs->set_azalia_d3_pme(smu); 2621 2622 mutex_unlock(&smu->mutex); 2623 2624 return ret; 2625 } 2626 2627 /* 2628 * On system suspending or resetting, the dpm_enabled 2629 * flag will be cleared. So that those SMU services which 2630 * are not supported will be gated. 2631 * 2632 * However, the baco/mode1 reset should still be granted 2633 * as they are still supported and necessary. 2634 */ 2635 bool smu_baco_is_support(struct smu_context *smu) 2636 { 2637 bool ret = false; 2638 2639 if (!smu->pm_enabled) 2640 return false; 2641 2642 mutex_lock(&smu->mutex); 2643 2644 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2645 ret = smu->ppt_funcs->baco_is_support(smu); 2646 2647 mutex_unlock(&smu->mutex); 2648 2649 return ret; 2650 } 2651 2652 int smu_get_baco_capability(void *handle, bool *cap) 2653 { 2654 struct smu_context *smu = handle; 2655 int ret = 0; 2656 2657 *cap = false; 2658 2659 if (!smu->pm_enabled) 2660 return 0; 2661 2662 mutex_lock(&smu->mutex); 2663 2664 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2665 *cap = smu->ppt_funcs->baco_is_support(smu); 2666 2667 mutex_unlock(&smu->mutex); 2668 2669 return ret; 2670 } 2671 2672 2673 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state) 2674 { 2675 if (smu->ppt_funcs->baco_get_state) 2676 return -EINVAL; 2677 2678 mutex_lock(&smu->mutex); 2679 *state = smu->ppt_funcs->baco_get_state(smu); 2680 mutex_unlock(&smu->mutex); 2681 2682 return 0; 2683 } 2684 2685 int smu_baco_enter(struct smu_context *smu) 2686 { 2687 int ret = 0; 2688 2689 if (!smu->pm_enabled) 2690 return -EOPNOTSUPP; 2691 2692 mutex_lock(&smu->mutex); 2693 2694 if (smu->ppt_funcs->baco_enter) 2695 ret = smu->ppt_funcs->baco_enter(smu); 2696 2697 mutex_unlock(&smu->mutex); 2698 2699 if (ret) 2700 dev_err(smu->adev->dev, "Failed to enter BACO state!\n"); 2701 2702 return ret; 2703 } 2704 2705 int smu_baco_exit(struct smu_context *smu) 2706 { 2707 int ret = 0; 2708 2709 if (!smu->pm_enabled) 2710 return -EOPNOTSUPP; 2711 2712 mutex_lock(&smu->mutex); 2713 2714 if (smu->ppt_funcs->baco_exit) 2715 ret = smu->ppt_funcs->baco_exit(smu); 2716 2717 mutex_unlock(&smu->mutex); 2718 2719 if (ret) 2720 dev_err(smu->adev->dev, "Failed to exit BACO state!\n"); 2721 2722 return ret; 2723 } 2724 2725 int smu_baco_set_state(void *handle, int state) 2726 { 2727 struct smu_context *smu = handle; 2728 int ret = 0; 2729 2730 if (!smu->pm_enabled) 2731 return -EOPNOTSUPP; 2732 2733 if (state == 0) { 2734 mutex_lock(&smu->mutex); 2735 2736 if (smu->ppt_funcs->baco_exit) 2737 ret = smu->ppt_funcs->baco_exit(smu); 2738 2739 mutex_unlock(&smu->mutex); 2740 } else if (state == 1) { 2741 mutex_lock(&smu->mutex); 2742 2743 if (smu->ppt_funcs->baco_enter) 2744 ret = smu->ppt_funcs->baco_enter(smu); 2745 2746 mutex_unlock(&smu->mutex); 2747 2748 } else { 2749 return -EINVAL; 2750 } 2751 2752 if (ret) 2753 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 2754 (state)?"enter":"exit"); 2755 2756 return ret; 2757 } 2758 2759 bool smu_mode1_reset_is_support(struct smu_context *smu) 2760 { 2761 bool ret = false; 2762 2763 if (!smu->pm_enabled) 2764 return false; 2765 2766 mutex_lock(&smu->mutex); 2767 2768 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2769 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2770 2771 mutex_unlock(&smu->mutex); 2772 2773 return ret; 2774 } 2775 2776 int smu_mode1_reset(struct smu_context *smu) 2777 { 2778 int ret = 0; 2779 2780 if (!smu->pm_enabled) 2781 return -EOPNOTSUPP; 2782 2783 mutex_lock(&smu->mutex); 2784 2785 if (smu->ppt_funcs->mode1_reset) 2786 ret = smu->ppt_funcs->mode1_reset(smu); 2787 2788 mutex_unlock(&smu->mutex); 2789 2790 return ret; 2791 } 2792 2793 int smu_mode2_reset(void *handle) 2794 { 2795 struct smu_context *smu = handle; 2796 int ret = 0; 2797 2798 if (!smu->pm_enabled) 2799 return -EOPNOTSUPP; 2800 2801 mutex_lock(&smu->mutex); 2802 2803 if (smu->ppt_funcs->mode2_reset) 2804 ret = smu->ppt_funcs->mode2_reset(smu); 2805 2806 mutex_unlock(&smu->mutex); 2807 2808 if (ret) 2809 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2810 2811 return ret; 2812 } 2813 2814 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu, 2815 struct pp_smu_nv_clock_table *max_clocks) 2816 { 2817 int ret = 0; 2818 2819 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2820 return -EOPNOTSUPP; 2821 2822 mutex_lock(&smu->mutex); 2823 2824 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2825 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2826 2827 mutex_unlock(&smu->mutex); 2828 2829 return ret; 2830 } 2831 2832 int smu_get_uclk_dpm_states(struct smu_context *smu, 2833 unsigned int *clock_values_in_khz, 2834 unsigned int *num_states) 2835 { 2836 int ret = 0; 2837 2838 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2839 return -EOPNOTSUPP; 2840 2841 mutex_lock(&smu->mutex); 2842 2843 if (smu->ppt_funcs->get_uclk_dpm_states) 2844 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2845 2846 mutex_unlock(&smu->mutex); 2847 2848 return ret; 2849 } 2850 2851 enum amd_pm_state_type smu_get_current_power_state(void *handle) 2852 { 2853 struct smu_context *smu = handle; 2854 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2855 2856 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2857 return -EOPNOTSUPP; 2858 2859 mutex_lock(&smu->mutex); 2860 2861 if (smu->ppt_funcs->get_current_power_state) 2862 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2863 2864 mutex_unlock(&smu->mutex); 2865 2866 return pm_state; 2867 } 2868 2869 int smu_get_dpm_clock_table(struct smu_context *smu, 2870 struct dpm_clocks *clock_table) 2871 { 2872 int ret = 0; 2873 2874 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2875 return -EOPNOTSUPP; 2876 2877 mutex_lock(&smu->mutex); 2878 2879 if (smu->ppt_funcs->get_dpm_clock_table) 2880 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 2881 2882 mutex_unlock(&smu->mutex); 2883 2884 return ret; 2885 } 2886 2887 ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 2888 { 2889 struct smu_context *smu = handle; 2890 ssize_t size; 2891 2892 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2893 return -EOPNOTSUPP; 2894 2895 if (!smu->ppt_funcs->get_gpu_metrics) 2896 return -EOPNOTSUPP; 2897 2898 mutex_lock(&smu->mutex); 2899 2900 size = smu->ppt_funcs->get_gpu_metrics(smu, table); 2901 2902 mutex_unlock(&smu->mutex); 2903 2904 return size; 2905 } 2906 2907 int smu_enable_mgpu_fan_boost(void *handle) 2908 { 2909 struct smu_context *smu = handle; 2910 int ret = 0; 2911 2912 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2913 return -EOPNOTSUPP; 2914 2915 mutex_lock(&smu->mutex); 2916 2917 if (smu->ppt_funcs->enable_mgpu_fan_boost) 2918 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 2919 2920 mutex_unlock(&smu->mutex); 2921 2922 return ret; 2923 } 2924 2925 int smu_gfx_state_change_set(struct smu_context *smu, uint32_t state) 2926 { 2927 int ret = 0; 2928 2929 mutex_lock(&smu->mutex); 2930 if (smu->ppt_funcs->gfx_state_change_set) 2931 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 2932 mutex_unlock(&smu->mutex); 2933 2934 return ret; 2935 } 2936 2937 static const struct amd_pm_funcs swsmu_pm_funcs = { 2938 /* export for sysfs */ 2939 .set_fan_control_mode = smu_pp_set_fan_control_mode, 2940 .get_fan_control_mode = smu_get_fan_control_mode, 2941 .set_fan_speed_percent = smu_set_fan_speed_percent, 2942 .get_fan_speed_percent = smu_get_fan_speed_percent, 2943 .force_performance_level = smu_force_performance_level, 2944 .read_sensor = smu_read_sensor, 2945 .get_performance_level = smu_get_performance_level, 2946 .get_current_power_state = smu_get_current_power_state, 2947 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 2948 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 2949 .get_pp_num_states = smu_get_power_num_states, 2950 .get_pp_table = smu_sys_get_pp_table, 2951 .set_pp_table = smu_sys_set_pp_table, 2952 .switch_power_profile = smu_switch_power_profile, 2953 /* export to amdgpu */ 2954 .dispatch_tasks = smu_handle_dpm_task, 2955 .set_powergating_by_smu = smu_dpm_set_power_gate, 2956 .set_power_limit = smu_set_power_limit, 2957 .odn_edit_dpm_table = smu_od_edit_dpm_table, 2958 .set_mp1_state = smu_set_mp1_state, 2959 /* export to DC */ 2960 .get_sclk = smu_get_sclk, 2961 .get_mclk = smu_get_mclk, 2962 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 2963 .get_asic_baco_capability = smu_get_baco_capability, 2964 .set_asic_baco_state = smu_baco_set_state, 2965 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 2966 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 2967 .asic_reset_mode_2 = smu_mode2_reset, 2968 .set_df_cstate = smu_set_df_cstate, 2969 .set_xgmi_pstate = smu_set_xgmi_pstate, 2970 .get_gpu_metrics = smu_sys_get_gpu_metrics, 2971 .set_power_profile_mode = smu_set_power_profile_mode, 2972 .get_power_profile_mode = smu_get_power_profile_mode, 2973 .force_clock_level = smu_force_ppclk_levels, 2974 .print_clock_levels = smu_print_ppclk_levels, 2975 }; 2976