1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "aldebaran_ppt.h" 38 #include "yellow_carp_ppt.h" 39 #include "cyan_skillfish_ppt.h" 40 #include "smu_v13_0_0_ppt.h" 41 #include "smu_v13_0_4_ppt.h" 42 #include "smu_v13_0_5_ppt.h" 43 #include "smu_v13_0_6_ppt.h" 44 #include "smu_v13_0_7_ppt.h" 45 #include "amd_pcie.h" 46 47 /* 48 * DO NOT use these for err/warn/info/debug messages. 49 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 50 * They are more MGPU friendly. 51 */ 52 #undef pr_err 53 #undef pr_warn 54 #undef pr_info 55 #undef pr_debug 56 57 static const struct amd_pm_funcs swsmu_pm_funcs; 58 static int smu_force_smuclk_levels(struct smu_context *smu, 59 enum smu_clk_type clk_type, 60 uint32_t mask); 61 static int smu_handle_task(struct smu_context *smu, 62 enum amd_dpm_forced_level level, 63 enum amd_pp_task task_id); 64 static int smu_reset(struct smu_context *smu); 65 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 66 static int smu_set_fan_control_mode(void *handle, u32 value); 67 static int smu_set_power_limit(void *handle, uint32_t limit); 68 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 69 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 70 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 71 72 static int smu_sys_get_pp_feature_mask(void *handle, 73 char *buf) 74 { 75 struct smu_context *smu = handle; 76 77 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 78 return -EOPNOTSUPP; 79 80 return smu_get_pp_feature_mask(smu, buf); 81 } 82 83 static int smu_sys_set_pp_feature_mask(void *handle, 84 uint64_t new_mask) 85 { 86 struct smu_context *smu = handle; 87 88 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 89 return -EOPNOTSUPP; 90 91 return smu_set_pp_feature_mask(smu, new_mask); 92 } 93 94 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 95 { 96 if (!smu->ppt_funcs->set_gfx_off_residency) 97 return -EINVAL; 98 99 return smu_set_gfx_off_residency(smu, value); 100 } 101 102 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 103 { 104 if (!smu->ppt_funcs->get_gfx_off_residency) 105 return -EINVAL; 106 107 return smu_get_gfx_off_residency(smu, value); 108 } 109 110 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 111 { 112 if (!smu->ppt_funcs->get_gfx_off_entrycount) 113 return -EINVAL; 114 115 return smu_get_gfx_off_entrycount(smu, value); 116 } 117 118 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 119 { 120 if (!smu->ppt_funcs->get_gfx_off_status) 121 return -EINVAL; 122 123 *value = smu_get_gfx_off_status(smu); 124 125 return 0; 126 } 127 128 int smu_set_soft_freq_range(struct smu_context *smu, 129 enum smu_clk_type clk_type, 130 uint32_t min, 131 uint32_t max) 132 { 133 int ret = 0; 134 135 if (smu->ppt_funcs->set_soft_freq_limited_range) 136 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 137 clk_type, 138 min, 139 max); 140 141 return ret; 142 } 143 144 int smu_get_dpm_freq_range(struct smu_context *smu, 145 enum smu_clk_type clk_type, 146 uint32_t *min, 147 uint32_t *max) 148 { 149 int ret = -ENOTSUPP; 150 151 if (!min && !max) 152 return -EINVAL; 153 154 if (smu->ppt_funcs->get_dpm_ultimate_freq) 155 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 156 clk_type, 157 min, 158 max); 159 160 return ret; 161 } 162 163 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 164 { 165 if (!smu->ppt_funcs || !smu->ppt_funcs->set_gfx_power_up_by_imu) 166 return -EOPNOTSUPP; 167 168 return smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 169 } 170 171 static u32 smu_get_mclk(void *handle, bool low) 172 { 173 struct smu_context *smu = handle; 174 uint32_t clk_freq; 175 int ret = 0; 176 177 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 178 low ? &clk_freq : NULL, 179 !low ? &clk_freq : NULL); 180 if (ret) 181 return 0; 182 return clk_freq * 100; 183 } 184 185 static u32 smu_get_sclk(void *handle, bool low) 186 { 187 struct smu_context *smu = handle; 188 uint32_t clk_freq; 189 int ret = 0; 190 191 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 192 low ? &clk_freq : NULL, 193 !low ? &clk_freq : NULL); 194 if (ret) 195 return 0; 196 return clk_freq * 100; 197 } 198 199 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 200 bool enable) 201 { 202 struct smu_power_context *smu_power = &smu->smu_power; 203 struct smu_power_gate *power_gate = &smu_power->power_gate; 204 int ret = 0; 205 206 if (!smu->ppt_funcs->dpm_set_vcn_enable) 207 return 0; 208 209 if (atomic_read(&power_gate->vcn_gated) ^ enable) 210 return 0; 211 212 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 213 if (!ret) 214 atomic_set(&power_gate->vcn_gated, !enable); 215 216 return ret; 217 } 218 219 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 220 bool enable) 221 { 222 struct smu_power_context *smu_power = &smu->smu_power; 223 struct smu_power_gate *power_gate = &smu_power->power_gate; 224 int ret = 0; 225 226 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 227 return 0; 228 229 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 230 return 0; 231 232 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 233 if (!ret) 234 atomic_set(&power_gate->jpeg_gated, !enable); 235 236 return ret; 237 } 238 239 /** 240 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 241 * 242 * @handle: smu_context pointer 243 * @block_type: the IP block to power gate/ungate 244 * @gate: to power gate if true, ungate otherwise 245 * 246 * This API uses no smu->mutex lock protection due to: 247 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 248 * This is guarded to be race condition free by the caller. 249 * 2. Or get called on user setting request of power_dpm_force_performance_level. 250 * Under this case, the smu->mutex lock protection is already enforced on 251 * the parent API smu_force_performance_level of the call path. 252 */ 253 static int smu_dpm_set_power_gate(void *handle, 254 uint32_t block_type, 255 bool gate) 256 { 257 struct smu_context *smu = handle; 258 int ret = 0; 259 260 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 261 dev_WARN(smu->adev->dev, 262 "SMU uninitialized but power %s requested for %u!\n", 263 gate ? "gate" : "ungate", block_type); 264 return -EOPNOTSUPP; 265 } 266 267 switch (block_type) { 268 /* 269 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 270 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 271 */ 272 case AMD_IP_BLOCK_TYPE_UVD: 273 case AMD_IP_BLOCK_TYPE_VCN: 274 ret = smu_dpm_set_vcn_enable(smu, !gate); 275 if (ret) 276 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 277 gate ? "gate" : "ungate"); 278 break; 279 case AMD_IP_BLOCK_TYPE_GFX: 280 ret = smu_gfx_off_control(smu, gate); 281 if (ret) 282 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 283 gate ? "enable" : "disable"); 284 break; 285 case AMD_IP_BLOCK_TYPE_SDMA: 286 ret = smu_powergate_sdma(smu, gate); 287 if (ret) 288 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 289 gate ? "gate" : "ungate"); 290 break; 291 case AMD_IP_BLOCK_TYPE_JPEG: 292 ret = smu_dpm_set_jpeg_enable(smu, !gate); 293 if (ret) 294 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 295 gate ? "gate" : "ungate"); 296 break; 297 default: 298 dev_err(smu->adev->dev, "Unsupported block type!\n"); 299 return -EINVAL; 300 } 301 302 return ret; 303 } 304 305 /** 306 * smu_set_user_clk_dependencies - set user profile clock dependencies 307 * 308 * @smu: smu_context pointer 309 * @clk: enum smu_clk_type type 310 * 311 * Enable/Disable the clock dependency for the @clk type. 312 */ 313 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 314 { 315 if (smu->adev->in_suspend) 316 return; 317 318 if (clk == SMU_MCLK) { 319 smu->user_dpm_profile.clk_dependency = 0; 320 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 321 } else if (clk == SMU_FCLK) { 322 /* MCLK takes precedence over FCLK */ 323 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 324 return; 325 326 smu->user_dpm_profile.clk_dependency = 0; 327 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 328 } else if (clk == SMU_SOCCLK) { 329 /* MCLK takes precedence over SOCCLK */ 330 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 331 return; 332 333 smu->user_dpm_profile.clk_dependency = 0; 334 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 335 } else 336 /* Add clk dependencies here, if any */ 337 return; 338 } 339 340 /** 341 * smu_restore_dpm_user_profile - reinstate user dpm profile 342 * 343 * @smu: smu_context pointer 344 * 345 * Restore the saved user power configurations include power limit, 346 * clock frequencies, fan control mode and fan speed. 347 */ 348 static void smu_restore_dpm_user_profile(struct smu_context *smu) 349 { 350 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 351 int ret = 0; 352 353 if (!smu->adev->in_suspend) 354 return; 355 356 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 357 return; 358 359 /* Enable restore flag */ 360 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 361 362 /* set the user dpm power limit */ 363 if (smu->user_dpm_profile.power_limit) { 364 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 365 if (ret) 366 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 367 } 368 369 /* set the user dpm clock configurations */ 370 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 371 enum smu_clk_type clk_type; 372 373 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 374 /* 375 * Iterate over smu clk type and force the saved user clk 376 * configs, skip if clock dependency is enabled 377 */ 378 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 379 smu->user_dpm_profile.clk_mask[clk_type]) { 380 ret = smu_force_smuclk_levels(smu, clk_type, 381 smu->user_dpm_profile.clk_mask[clk_type]); 382 if (ret) 383 dev_err(smu->adev->dev, 384 "Failed to set clock type = %d\n", clk_type); 385 } 386 } 387 } 388 389 /* set the user dpm fan configurations */ 390 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 391 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 392 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 393 if (ret != -EOPNOTSUPP) { 394 smu->user_dpm_profile.fan_speed_pwm = 0; 395 smu->user_dpm_profile.fan_speed_rpm = 0; 396 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 397 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 398 } 399 400 if (smu->user_dpm_profile.fan_speed_pwm) { 401 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 402 if (ret != -EOPNOTSUPP) 403 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 404 } 405 406 if (smu->user_dpm_profile.fan_speed_rpm) { 407 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 408 if (ret != -EOPNOTSUPP) 409 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 410 } 411 } 412 413 /* Restore user customized OD settings */ 414 if (smu->user_dpm_profile.user_od) { 415 if (smu->ppt_funcs->restore_user_od_settings) { 416 ret = smu->ppt_funcs->restore_user_od_settings(smu); 417 if (ret) 418 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 419 } 420 } 421 422 /* Disable restore flag */ 423 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 424 } 425 426 static int smu_get_power_num_states(void *handle, 427 struct pp_states_info *state_info) 428 { 429 if (!state_info) 430 return -EINVAL; 431 432 /* not support power state */ 433 memset(state_info, 0, sizeof(struct pp_states_info)); 434 state_info->nums = 1; 435 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 436 437 return 0; 438 } 439 440 bool is_support_sw_smu(struct amdgpu_device *adev) 441 { 442 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 443 if (adev->asic_type == CHIP_VEGA20) 444 return false; 445 446 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0)) 447 return true; 448 449 return false; 450 } 451 452 bool is_support_cclk_dpm(struct amdgpu_device *adev) 453 { 454 struct smu_context *smu = adev->powerplay.pp_handle; 455 456 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 457 return false; 458 459 return true; 460 } 461 462 463 static int smu_sys_get_pp_table(void *handle, 464 char **table) 465 { 466 struct smu_context *smu = handle; 467 struct smu_table_context *smu_table = &smu->smu_table; 468 469 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 470 return -EOPNOTSUPP; 471 472 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 473 return -EINVAL; 474 475 if (smu_table->hardcode_pptable) 476 *table = smu_table->hardcode_pptable; 477 else 478 *table = smu_table->power_play_table; 479 480 return smu_table->power_play_table_size; 481 } 482 483 static int smu_sys_set_pp_table(void *handle, 484 const char *buf, 485 size_t size) 486 { 487 struct smu_context *smu = handle; 488 struct smu_table_context *smu_table = &smu->smu_table; 489 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 490 int ret = 0; 491 492 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 493 return -EOPNOTSUPP; 494 495 if (header->usStructureSize != size) { 496 dev_err(smu->adev->dev, "pp table size not matched !\n"); 497 return -EIO; 498 } 499 500 if (!smu_table->hardcode_pptable) { 501 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 502 if (!smu_table->hardcode_pptable) 503 return -ENOMEM; 504 } 505 506 memcpy(smu_table->hardcode_pptable, buf, size); 507 smu_table->power_play_table = smu_table->hardcode_pptable; 508 smu_table->power_play_table_size = size; 509 510 /* 511 * Special hw_fini action(for Navi1x, the DPMs disablement will be 512 * skipped) may be needed for custom pptable uploading. 513 */ 514 smu->uploading_custom_pp_table = true; 515 516 ret = smu_reset(smu); 517 if (ret) 518 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 519 520 smu->uploading_custom_pp_table = false; 521 522 return ret; 523 } 524 525 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 526 { 527 struct smu_feature *feature = &smu->smu_feature; 528 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 529 int ret = 0; 530 531 /* 532 * With SCPM enabled, the allowed featuremasks setting(via 533 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 534 * That means there is no way to let PMFW knows the settings below. 535 * Thus, we just assume all the features are allowed under 536 * such scenario. 537 */ 538 if (smu->adev->scpm_enabled) { 539 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 540 return 0; 541 } 542 543 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 544 545 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 546 SMU_FEATURE_MAX/32); 547 if (ret) 548 return ret; 549 550 bitmap_or(feature->allowed, feature->allowed, 551 (unsigned long *)allowed_feature_mask, 552 feature->feature_num); 553 554 return ret; 555 } 556 557 static int smu_set_funcs(struct amdgpu_device *adev) 558 { 559 struct smu_context *smu = adev->powerplay.pp_handle; 560 561 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 562 smu->od_enabled = true; 563 564 switch (adev->ip_versions[MP1_HWIP][0]) { 565 case IP_VERSION(11, 0, 0): 566 case IP_VERSION(11, 0, 5): 567 case IP_VERSION(11, 0, 9): 568 navi10_set_ppt_funcs(smu); 569 break; 570 case IP_VERSION(11, 0, 7): 571 case IP_VERSION(11, 0, 11): 572 case IP_VERSION(11, 0, 12): 573 case IP_VERSION(11, 0, 13): 574 sienna_cichlid_set_ppt_funcs(smu); 575 break; 576 case IP_VERSION(12, 0, 0): 577 case IP_VERSION(12, 0, 1): 578 renoir_set_ppt_funcs(smu); 579 break; 580 case IP_VERSION(11, 5, 0): 581 vangogh_set_ppt_funcs(smu); 582 break; 583 case IP_VERSION(13, 0, 1): 584 case IP_VERSION(13, 0, 3): 585 case IP_VERSION(13, 0, 8): 586 yellow_carp_set_ppt_funcs(smu); 587 break; 588 case IP_VERSION(13, 0, 4): 589 case IP_VERSION(13, 0, 11): 590 smu_v13_0_4_set_ppt_funcs(smu); 591 break; 592 case IP_VERSION(13, 0, 5): 593 smu_v13_0_5_set_ppt_funcs(smu); 594 break; 595 case IP_VERSION(11, 0, 8): 596 cyan_skillfish_set_ppt_funcs(smu); 597 break; 598 case IP_VERSION(11, 0, 2): 599 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 600 arcturus_set_ppt_funcs(smu); 601 /* OD is not supported on Arcturus */ 602 smu->od_enabled =false; 603 break; 604 case IP_VERSION(13, 0, 2): 605 aldebaran_set_ppt_funcs(smu); 606 /* Enable pp_od_clk_voltage node */ 607 smu->od_enabled = true; 608 break; 609 case IP_VERSION(13, 0, 0): 610 case IP_VERSION(13, 0, 10): 611 smu_v13_0_0_set_ppt_funcs(smu); 612 break; 613 case IP_VERSION(13, 0, 6): 614 smu_v13_0_6_set_ppt_funcs(smu); 615 /* Enable pp_od_clk_voltage node */ 616 smu->od_enabled = true; 617 break; 618 case IP_VERSION(13, 0, 7): 619 smu_v13_0_7_set_ppt_funcs(smu); 620 break; 621 default: 622 return -EINVAL; 623 } 624 625 return 0; 626 } 627 628 static int smu_early_init(void *handle) 629 { 630 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 631 struct smu_context *smu; 632 int r; 633 634 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 635 if (!smu) 636 return -ENOMEM; 637 638 smu->adev = adev; 639 smu->pm_enabled = !!amdgpu_dpm; 640 smu->is_apu = false; 641 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 642 smu->smu_baco.platform_support = false; 643 smu->user_dpm_profile.fan_mode = -1; 644 645 mutex_init(&smu->message_lock); 646 647 adev->powerplay.pp_handle = smu; 648 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 649 650 r = smu_set_funcs(adev); 651 if (r) 652 return r; 653 return smu_init_microcode(smu); 654 } 655 656 static int smu_set_default_dpm_table(struct smu_context *smu) 657 { 658 struct smu_power_context *smu_power = &smu->smu_power; 659 struct smu_power_gate *power_gate = &smu_power->power_gate; 660 int vcn_gate, jpeg_gate; 661 int ret = 0; 662 663 if (!smu->ppt_funcs->set_default_dpm_table) 664 return 0; 665 666 vcn_gate = atomic_read(&power_gate->vcn_gated); 667 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 668 669 ret = smu_dpm_set_vcn_enable(smu, true); 670 if (ret) 671 return ret; 672 673 ret = smu_dpm_set_jpeg_enable(smu, true); 674 if (ret) 675 goto err_out; 676 677 ret = smu->ppt_funcs->set_default_dpm_table(smu); 678 if (ret) 679 dev_err(smu->adev->dev, 680 "Failed to setup default dpm clock tables!\n"); 681 682 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 683 err_out: 684 smu_dpm_set_vcn_enable(smu, !vcn_gate); 685 return ret; 686 } 687 688 static int smu_apply_default_config_table_settings(struct smu_context *smu) 689 { 690 struct amdgpu_device *adev = smu->adev; 691 int ret = 0; 692 693 ret = smu_get_default_config_table_settings(smu, 694 &adev->pm.config_table); 695 if (ret) 696 return ret; 697 698 return smu_set_config_table(smu, &adev->pm.config_table); 699 } 700 701 static int smu_late_init(void *handle) 702 { 703 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 704 struct smu_context *smu = adev->powerplay.pp_handle; 705 int ret = 0; 706 707 smu_set_fine_grain_gfx_freq_parameters(smu); 708 709 if (!smu->pm_enabled) 710 return 0; 711 712 ret = smu_post_init(smu); 713 if (ret) { 714 dev_err(adev->dev, "Failed to post smu init!\n"); 715 return ret; 716 } 717 718 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || 719 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) 720 return 0; 721 722 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 723 ret = smu_set_default_od_settings(smu); 724 if (ret) { 725 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 726 return ret; 727 } 728 } 729 730 ret = smu_populate_umd_state_clk(smu); 731 if (ret) { 732 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 733 return ret; 734 } 735 736 ret = smu_get_asic_power_limits(smu, 737 &smu->current_power_limit, 738 &smu->default_power_limit, 739 &smu->max_power_limit); 740 if (ret) { 741 dev_err(adev->dev, "Failed to get asic power limits!\n"); 742 return ret; 743 } 744 745 if (!amdgpu_sriov_vf(adev)) 746 smu_get_unique_id(smu); 747 748 smu_get_fan_parameters(smu); 749 750 smu_handle_task(smu, 751 smu->smu_dpm.dpm_level, 752 AMD_PP_TASK_COMPLETE_INIT); 753 754 ret = smu_apply_default_config_table_settings(smu); 755 if (ret && (ret != -EOPNOTSUPP)) { 756 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 757 return ret; 758 } 759 760 smu_restore_dpm_user_profile(smu); 761 762 return 0; 763 } 764 765 static int smu_init_fb_allocations(struct smu_context *smu) 766 { 767 struct amdgpu_device *adev = smu->adev; 768 struct smu_table_context *smu_table = &smu->smu_table; 769 struct smu_table *tables = smu_table->tables; 770 struct smu_table *driver_table = &(smu_table->driver_table); 771 uint32_t max_table_size = 0; 772 int ret, i; 773 774 /* VRAM allocation for tool table */ 775 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 776 ret = amdgpu_bo_create_kernel(adev, 777 tables[SMU_TABLE_PMSTATUSLOG].size, 778 tables[SMU_TABLE_PMSTATUSLOG].align, 779 tables[SMU_TABLE_PMSTATUSLOG].domain, 780 &tables[SMU_TABLE_PMSTATUSLOG].bo, 781 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 782 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 783 if (ret) { 784 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 785 return ret; 786 } 787 } 788 789 /* VRAM allocation for driver table */ 790 for (i = 0; i < SMU_TABLE_COUNT; i++) { 791 if (tables[i].size == 0) 792 continue; 793 794 if (i == SMU_TABLE_PMSTATUSLOG) 795 continue; 796 797 if (max_table_size < tables[i].size) 798 max_table_size = tables[i].size; 799 } 800 801 driver_table->size = max_table_size; 802 driver_table->align = PAGE_SIZE; 803 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 804 805 ret = amdgpu_bo_create_kernel(adev, 806 driver_table->size, 807 driver_table->align, 808 driver_table->domain, 809 &driver_table->bo, 810 &driver_table->mc_address, 811 &driver_table->cpu_addr); 812 if (ret) { 813 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 814 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 815 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 816 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 817 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 818 } 819 820 return ret; 821 } 822 823 static int smu_fini_fb_allocations(struct smu_context *smu) 824 { 825 struct smu_table_context *smu_table = &smu->smu_table; 826 struct smu_table *tables = smu_table->tables; 827 struct smu_table *driver_table = &(smu_table->driver_table); 828 829 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 830 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 831 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 832 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 833 834 amdgpu_bo_free_kernel(&driver_table->bo, 835 &driver_table->mc_address, 836 &driver_table->cpu_addr); 837 838 return 0; 839 } 840 841 /** 842 * smu_alloc_memory_pool - allocate memory pool in the system memory 843 * 844 * @smu: amdgpu_device pointer 845 * 846 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 847 * and DramLogSetDramAddr can notify it changed. 848 * 849 * Returns 0 on success, error on failure. 850 */ 851 static int smu_alloc_memory_pool(struct smu_context *smu) 852 { 853 struct amdgpu_device *adev = smu->adev; 854 struct smu_table_context *smu_table = &smu->smu_table; 855 struct smu_table *memory_pool = &smu_table->memory_pool; 856 uint64_t pool_size = smu->pool_size; 857 int ret = 0; 858 859 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 860 return ret; 861 862 memory_pool->size = pool_size; 863 memory_pool->align = PAGE_SIZE; 864 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 865 866 switch (pool_size) { 867 case SMU_MEMORY_POOL_SIZE_256_MB: 868 case SMU_MEMORY_POOL_SIZE_512_MB: 869 case SMU_MEMORY_POOL_SIZE_1_GB: 870 case SMU_MEMORY_POOL_SIZE_2_GB: 871 ret = amdgpu_bo_create_kernel(adev, 872 memory_pool->size, 873 memory_pool->align, 874 memory_pool->domain, 875 &memory_pool->bo, 876 &memory_pool->mc_address, 877 &memory_pool->cpu_addr); 878 if (ret) 879 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 880 break; 881 default: 882 break; 883 } 884 885 return ret; 886 } 887 888 static int smu_free_memory_pool(struct smu_context *smu) 889 { 890 struct smu_table_context *smu_table = &smu->smu_table; 891 struct smu_table *memory_pool = &smu_table->memory_pool; 892 893 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 894 return 0; 895 896 amdgpu_bo_free_kernel(&memory_pool->bo, 897 &memory_pool->mc_address, 898 &memory_pool->cpu_addr); 899 900 memset(memory_pool, 0, sizeof(struct smu_table)); 901 902 return 0; 903 } 904 905 static int smu_alloc_dummy_read_table(struct smu_context *smu) 906 { 907 struct smu_table_context *smu_table = &smu->smu_table; 908 struct smu_table *dummy_read_1_table = 909 &smu_table->dummy_read_1_table; 910 struct amdgpu_device *adev = smu->adev; 911 int ret = 0; 912 913 if (!dummy_read_1_table->size) 914 return 0; 915 916 ret = amdgpu_bo_create_kernel(adev, 917 dummy_read_1_table->size, 918 dummy_read_1_table->align, 919 dummy_read_1_table->domain, 920 &dummy_read_1_table->bo, 921 &dummy_read_1_table->mc_address, 922 &dummy_read_1_table->cpu_addr); 923 if (ret) 924 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 925 926 return ret; 927 } 928 929 static void smu_free_dummy_read_table(struct smu_context *smu) 930 { 931 struct smu_table_context *smu_table = &smu->smu_table; 932 struct smu_table *dummy_read_1_table = 933 &smu_table->dummy_read_1_table; 934 935 936 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 937 &dummy_read_1_table->mc_address, 938 &dummy_read_1_table->cpu_addr); 939 940 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 941 } 942 943 static int smu_smc_table_sw_init(struct smu_context *smu) 944 { 945 int ret; 946 947 /** 948 * Create smu_table structure, and init smc tables such as 949 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 950 */ 951 ret = smu_init_smc_tables(smu); 952 if (ret) { 953 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 954 return ret; 955 } 956 957 /** 958 * Create smu_power_context structure, and allocate smu_dpm_context and 959 * context size to fill the smu_power_context data. 960 */ 961 ret = smu_init_power(smu); 962 if (ret) { 963 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 964 return ret; 965 } 966 967 /* 968 * allocate vram bos to store smc table contents. 969 */ 970 ret = smu_init_fb_allocations(smu); 971 if (ret) 972 return ret; 973 974 ret = smu_alloc_memory_pool(smu); 975 if (ret) 976 return ret; 977 978 ret = smu_alloc_dummy_read_table(smu); 979 if (ret) 980 return ret; 981 982 ret = smu_i2c_init(smu); 983 if (ret) 984 return ret; 985 986 return 0; 987 } 988 989 static int smu_smc_table_sw_fini(struct smu_context *smu) 990 { 991 int ret; 992 993 smu_i2c_fini(smu); 994 995 smu_free_dummy_read_table(smu); 996 997 ret = smu_free_memory_pool(smu); 998 if (ret) 999 return ret; 1000 1001 ret = smu_fini_fb_allocations(smu); 1002 if (ret) 1003 return ret; 1004 1005 ret = smu_fini_power(smu); 1006 if (ret) { 1007 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1008 return ret; 1009 } 1010 1011 ret = smu_fini_smc_tables(smu); 1012 if (ret) { 1013 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1014 return ret; 1015 } 1016 1017 return 0; 1018 } 1019 1020 static void smu_throttling_logging_work_fn(struct work_struct *work) 1021 { 1022 struct smu_context *smu = container_of(work, struct smu_context, 1023 throttling_logging_work); 1024 1025 smu_log_thermal_throttling(smu); 1026 } 1027 1028 static void smu_interrupt_work_fn(struct work_struct *work) 1029 { 1030 struct smu_context *smu = container_of(work, struct smu_context, 1031 interrupt_work); 1032 1033 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1034 smu->ppt_funcs->interrupt_work(smu); 1035 } 1036 1037 static int smu_sw_init(void *handle) 1038 { 1039 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1040 struct smu_context *smu = adev->powerplay.pp_handle; 1041 int ret; 1042 1043 smu->pool_size = adev->pm.smu_prv_buffer_size; 1044 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1045 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1046 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1047 1048 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1049 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1050 atomic64_set(&smu->throttle_int_counter, 0); 1051 smu->watermarks_bitmap = 0; 1052 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1053 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1054 1055 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1056 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1057 1058 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1059 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1060 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1061 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1062 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1063 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1064 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1065 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1066 1067 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1068 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1069 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1070 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1071 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1072 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1073 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1074 smu->display_config = &adev->pm.pm_display_cfg; 1075 1076 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1077 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1078 1079 ret = smu_smc_table_sw_init(smu); 1080 if (ret) { 1081 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1082 return ret; 1083 } 1084 1085 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1086 ret = smu_get_vbios_bootup_values(smu); 1087 if (ret) { 1088 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1089 return ret; 1090 } 1091 1092 ret = smu_init_pptable_microcode(smu); 1093 if (ret) { 1094 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1095 return ret; 1096 } 1097 1098 ret = smu_register_irq_handler(smu); 1099 if (ret) { 1100 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1101 return ret; 1102 } 1103 1104 /* If there is no way to query fan control mode, fan control is not supported */ 1105 if (!smu->ppt_funcs->get_fan_control_mode) 1106 smu->adev->pm.no_fan = true; 1107 1108 return 0; 1109 } 1110 1111 static int smu_sw_fini(void *handle) 1112 { 1113 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1114 struct smu_context *smu = adev->powerplay.pp_handle; 1115 int ret; 1116 1117 ret = smu_smc_table_sw_fini(smu); 1118 if (ret) { 1119 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1120 return ret; 1121 } 1122 1123 smu_fini_microcode(smu); 1124 1125 return 0; 1126 } 1127 1128 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1129 { 1130 struct amdgpu_device *adev = smu->adev; 1131 struct smu_temperature_range *range = 1132 &smu->thermal_range; 1133 int ret = 0; 1134 1135 if (!smu->ppt_funcs->get_thermal_temperature_range) 1136 return 0; 1137 1138 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1139 if (ret) 1140 return ret; 1141 1142 adev->pm.dpm.thermal.min_temp = range->min; 1143 adev->pm.dpm.thermal.max_temp = range->max; 1144 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1145 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1146 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1147 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1148 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1149 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1150 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1151 1152 return ret; 1153 } 1154 1155 static int smu_smc_hw_setup(struct smu_context *smu) 1156 { 1157 struct smu_feature *feature = &smu->smu_feature; 1158 struct amdgpu_device *adev = smu->adev; 1159 uint32_t pcie_gen = 0, pcie_width = 0; 1160 uint64_t features_supported; 1161 int ret = 0; 1162 1163 switch (adev->ip_versions[MP1_HWIP][0]) { 1164 case IP_VERSION(11, 0, 7): 1165 case IP_VERSION(11, 0, 11): 1166 case IP_VERSION(11, 5, 0): 1167 case IP_VERSION(11, 0, 12): 1168 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1169 dev_info(adev->dev, "dpm has been enabled\n"); 1170 ret = smu_system_features_control(smu, true); 1171 if (ret) 1172 dev_err(adev->dev, "Failed system features control!\n"); 1173 return ret; 1174 } 1175 break; 1176 default: 1177 break; 1178 } 1179 1180 ret = smu_init_display_count(smu, 0); 1181 if (ret) { 1182 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1183 return ret; 1184 } 1185 1186 ret = smu_set_driver_table_location(smu); 1187 if (ret) { 1188 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1189 return ret; 1190 } 1191 1192 /* 1193 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1194 */ 1195 ret = smu_set_tool_table_location(smu); 1196 if (ret) { 1197 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1198 return ret; 1199 } 1200 1201 /* 1202 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1203 * pool location. 1204 */ 1205 ret = smu_notify_memory_pool_location(smu); 1206 if (ret) { 1207 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1208 return ret; 1209 } 1210 1211 /* 1212 * It is assumed the pptable used before runpm is same as 1213 * the one used afterwards. Thus, we can reuse the stored 1214 * copy and do not need to resetup the pptable again. 1215 */ 1216 if (!adev->in_runpm) { 1217 ret = smu_setup_pptable(smu); 1218 if (ret) { 1219 dev_err(adev->dev, "Failed to setup pptable!\n"); 1220 return ret; 1221 } 1222 } 1223 1224 /* smu_dump_pptable(smu); */ 1225 1226 /* 1227 * With SCPM enabled, PSP is responsible for the PPTable transferring 1228 * (to SMU). Driver involvement is not needed and permitted. 1229 */ 1230 if (!adev->scpm_enabled) { 1231 /* 1232 * Copy pptable bo in the vram to smc with SMU MSGs such as 1233 * SetDriverDramAddr and TransferTableDram2Smu. 1234 */ 1235 ret = smu_write_pptable(smu); 1236 if (ret) { 1237 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1238 return ret; 1239 } 1240 } 1241 1242 /* issue Run*Btc msg */ 1243 ret = smu_run_btc(smu); 1244 if (ret) 1245 return ret; 1246 1247 /* 1248 * With SCPM enabled, these actions(and relevant messages) are 1249 * not needed and permitted. 1250 */ 1251 if (!adev->scpm_enabled) { 1252 ret = smu_feature_set_allowed_mask(smu); 1253 if (ret) { 1254 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1255 return ret; 1256 } 1257 } 1258 1259 ret = smu_system_features_control(smu, true); 1260 if (ret) { 1261 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1262 return ret; 1263 } 1264 1265 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1266 if (ret) { 1267 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1268 return ret; 1269 } 1270 bitmap_copy(feature->supported, 1271 (unsigned long *)&features_supported, 1272 feature->feature_num); 1273 1274 if (!smu_is_dpm_running(smu)) 1275 dev_info(adev->dev, "dpm has been disabled\n"); 1276 1277 /* 1278 * Set initialized values (get from vbios) to dpm tables context such as 1279 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1280 * type of clks. 1281 */ 1282 ret = smu_set_default_dpm_table(smu); 1283 if (ret) { 1284 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1285 return ret; 1286 } 1287 1288 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1289 pcie_gen = 3; 1290 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1291 pcie_gen = 2; 1292 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1293 pcie_gen = 1; 1294 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1295 pcie_gen = 0; 1296 1297 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1298 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1299 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1300 */ 1301 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1302 pcie_width = 6; 1303 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1304 pcie_width = 5; 1305 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1306 pcie_width = 4; 1307 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1308 pcie_width = 3; 1309 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1310 pcie_width = 2; 1311 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1312 pcie_width = 1; 1313 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1314 if (ret) { 1315 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1316 return ret; 1317 } 1318 1319 ret = smu_get_thermal_temperature_range(smu); 1320 if (ret) { 1321 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1322 return ret; 1323 } 1324 1325 ret = smu_enable_thermal_alert(smu); 1326 if (ret) { 1327 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1328 return ret; 1329 } 1330 1331 ret = smu_notify_display_change(smu); 1332 if (ret) { 1333 dev_err(adev->dev, "Failed to notify display change!\n"); 1334 return ret; 1335 } 1336 1337 /* 1338 * Set min deep sleep dce fclk with bootup value from vbios via 1339 * SetMinDeepSleepDcefclk MSG. 1340 */ 1341 ret = smu_set_min_dcef_deep_sleep(smu, 1342 smu->smu_table.boot_values.dcefclk / 100); 1343 1344 return ret; 1345 } 1346 1347 static int smu_start_smc_engine(struct smu_context *smu) 1348 { 1349 struct amdgpu_device *adev = smu->adev; 1350 int ret = 0; 1351 1352 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1353 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) { 1354 if (smu->ppt_funcs->load_microcode) { 1355 ret = smu->ppt_funcs->load_microcode(smu); 1356 if (ret) 1357 return ret; 1358 } 1359 } 1360 } 1361 1362 if (smu->ppt_funcs->check_fw_status) { 1363 ret = smu->ppt_funcs->check_fw_status(smu); 1364 if (ret) { 1365 dev_err(adev->dev, "SMC is not ready\n"); 1366 return ret; 1367 } 1368 } 1369 1370 /* 1371 * Send msg GetDriverIfVersion to check if the return value is equal 1372 * with DRIVER_IF_VERSION of smc header. 1373 */ 1374 ret = smu_check_fw_version(smu); 1375 if (ret) 1376 return ret; 1377 1378 return ret; 1379 } 1380 1381 static int smu_hw_init(void *handle) 1382 { 1383 int ret; 1384 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1385 struct smu_context *smu = adev->powerplay.pp_handle; 1386 1387 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1388 smu->pm_enabled = false; 1389 return 0; 1390 } 1391 1392 ret = smu_start_smc_engine(smu); 1393 if (ret) { 1394 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1395 return ret; 1396 } 1397 1398 if (smu->is_apu) { 1399 if ((smu->ppt_funcs->set_gfx_power_up_by_imu) && 1400 likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 1401 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 1402 if (ret) { 1403 dev_err(adev->dev, "Failed to Enable gfx imu!\n"); 1404 return ret; 1405 } 1406 } 1407 1408 smu_dpm_set_vcn_enable(smu, true); 1409 smu_dpm_set_jpeg_enable(smu, true); 1410 smu_set_gfx_cgpg(smu, true); 1411 } 1412 1413 if (!smu->pm_enabled) 1414 return 0; 1415 1416 ret = smu_get_driver_allowed_feature_mask(smu); 1417 if (ret) 1418 return ret; 1419 1420 ret = smu_smc_hw_setup(smu); 1421 if (ret) { 1422 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1423 return ret; 1424 } 1425 1426 /* 1427 * Move maximum sustainable clock retrieving here considering 1428 * 1. It is not needed on resume(from S3). 1429 * 2. DAL settings come between .hw_init and .late_init of SMU. 1430 * And DAL needs to know the maximum sustainable clocks. Thus 1431 * it cannot be put in .late_init(). 1432 */ 1433 ret = smu_init_max_sustainable_clocks(smu); 1434 if (ret) { 1435 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1436 return ret; 1437 } 1438 1439 adev->pm.dpm_enabled = true; 1440 1441 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1442 1443 return 0; 1444 } 1445 1446 static int smu_disable_dpms(struct smu_context *smu) 1447 { 1448 struct amdgpu_device *adev = smu->adev; 1449 int ret = 0; 1450 bool use_baco = !smu->is_apu && 1451 ((amdgpu_in_reset(adev) && 1452 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1453 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1454 1455 /* 1456 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1457 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1458 */ 1459 switch (adev->ip_versions[MP1_HWIP][0]) { 1460 case IP_VERSION(13, 0, 0): 1461 case IP_VERSION(13, 0, 7): 1462 case IP_VERSION(13, 0, 10): 1463 return 0; 1464 default: 1465 break; 1466 } 1467 1468 /* 1469 * For custom pptable uploading, skip the DPM features 1470 * disable process on Navi1x ASICs. 1471 * - As the gfx related features are under control of 1472 * RLC on those ASICs. RLC reinitialization will be 1473 * needed to reenable them. That will cost much more 1474 * efforts. 1475 * 1476 * - SMU firmware can handle the DPM reenablement 1477 * properly. 1478 */ 1479 if (smu->uploading_custom_pp_table) { 1480 switch (adev->ip_versions[MP1_HWIP][0]) { 1481 case IP_VERSION(11, 0, 0): 1482 case IP_VERSION(11, 0, 5): 1483 case IP_VERSION(11, 0, 9): 1484 case IP_VERSION(11, 0, 7): 1485 case IP_VERSION(11, 0, 11): 1486 case IP_VERSION(11, 5, 0): 1487 case IP_VERSION(11, 0, 12): 1488 case IP_VERSION(11, 0, 13): 1489 return 0; 1490 default: 1491 break; 1492 } 1493 } 1494 1495 /* 1496 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1497 * on BACO in. Driver involvement is unnecessary. 1498 */ 1499 if (use_baco) { 1500 switch (adev->ip_versions[MP1_HWIP][0]) { 1501 case IP_VERSION(11, 0, 7): 1502 case IP_VERSION(11, 0, 0): 1503 case IP_VERSION(11, 0, 5): 1504 case IP_VERSION(11, 0, 9): 1505 case IP_VERSION(13, 0, 7): 1506 return 0; 1507 default: 1508 break; 1509 } 1510 } 1511 1512 /* 1513 * For SMU 13.0.4/11, PMFW will handle the features disablement properly 1514 * for gpu reset case. Driver involvement is unnecessary. 1515 */ 1516 if (amdgpu_in_reset(adev)) { 1517 switch (adev->ip_versions[MP1_HWIP][0]) { 1518 case IP_VERSION(13, 0, 4): 1519 case IP_VERSION(13, 0, 11): 1520 return 0; 1521 default: 1522 break; 1523 } 1524 } 1525 1526 /* 1527 * For gpu reset, runpm and hibernation through BACO, 1528 * BACO feature has to be kept enabled. 1529 */ 1530 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1531 ret = smu_disable_all_features_with_exception(smu, 1532 SMU_FEATURE_BACO_BIT); 1533 if (ret) 1534 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1535 } else { 1536 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1537 if (!adev->scpm_enabled) { 1538 ret = smu_system_features_control(smu, false); 1539 if (ret) 1540 dev_err(adev->dev, "Failed to disable smu features.\n"); 1541 } 1542 } 1543 1544 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) && 1545 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1546 adev->gfx.rlc.funcs->stop(adev); 1547 1548 return ret; 1549 } 1550 1551 static int smu_smc_hw_cleanup(struct smu_context *smu) 1552 { 1553 struct amdgpu_device *adev = smu->adev; 1554 int ret = 0; 1555 1556 cancel_work_sync(&smu->throttling_logging_work); 1557 cancel_work_sync(&smu->interrupt_work); 1558 1559 ret = smu_disable_thermal_alert(smu); 1560 if (ret) { 1561 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1562 return ret; 1563 } 1564 1565 ret = smu_disable_dpms(smu); 1566 if (ret) { 1567 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1568 return ret; 1569 } 1570 1571 return 0; 1572 } 1573 1574 static int smu_hw_fini(void *handle) 1575 { 1576 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1577 struct smu_context *smu = adev->powerplay.pp_handle; 1578 1579 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1580 return 0; 1581 1582 smu_dpm_set_vcn_enable(smu, false); 1583 smu_dpm_set_jpeg_enable(smu, false); 1584 1585 adev->vcn.cur_state = AMD_PG_STATE_GATE; 1586 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 1587 1588 if (!smu->pm_enabled) 1589 return 0; 1590 1591 adev->pm.dpm_enabled = false; 1592 1593 return smu_smc_hw_cleanup(smu); 1594 } 1595 1596 static void smu_late_fini(void *handle) 1597 { 1598 struct amdgpu_device *adev = handle; 1599 struct smu_context *smu = adev->powerplay.pp_handle; 1600 1601 kfree(smu); 1602 } 1603 1604 static int smu_reset(struct smu_context *smu) 1605 { 1606 struct amdgpu_device *adev = smu->adev; 1607 int ret; 1608 1609 ret = smu_hw_fini(adev); 1610 if (ret) 1611 return ret; 1612 1613 ret = smu_hw_init(adev); 1614 if (ret) 1615 return ret; 1616 1617 ret = smu_late_init(adev); 1618 if (ret) 1619 return ret; 1620 1621 return 0; 1622 } 1623 1624 static int smu_suspend(void *handle) 1625 { 1626 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1627 struct smu_context *smu = adev->powerplay.pp_handle; 1628 int ret; 1629 uint64_t count; 1630 1631 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1632 return 0; 1633 1634 if (!smu->pm_enabled) 1635 return 0; 1636 1637 adev->pm.dpm_enabled = false; 1638 1639 ret = smu_smc_hw_cleanup(smu); 1640 if (ret) 1641 return ret; 1642 1643 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1644 1645 smu_set_gfx_cgpg(smu, false); 1646 1647 /* 1648 * pwfw resets entrycount when device is suspended, so we save the 1649 * last value to be used when we resume to keep it consistent 1650 */ 1651 ret = smu_get_entrycount_gfxoff(smu, &count); 1652 if (!ret) 1653 adev->gfx.gfx_off_entrycount = count; 1654 1655 return 0; 1656 } 1657 1658 static int smu_resume(void *handle) 1659 { 1660 int ret; 1661 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1662 struct smu_context *smu = adev->powerplay.pp_handle; 1663 1664 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1665 return 0; 1666 1667 if (!smu->pm_enabled) 1668 return 0; 1669 1670 dev_info(adev->dev, "SMU is resuming...\n"); 1671 1672 ret = smu_start_smc_engine(smu); 1673 if (ret) { 1674 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1675 return ret; 1676 } 1677 1678 ret = smu_smc_hw_setup(smu); 1679 if (ret) { 1680 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1681 return ret; 1682 } 1683 1684 smu_set_gfx_cgpg(smu, true); 1685 1686 smu->disable_uclk_switch = 0; 1687 1688 adev->pm.dpm_enabled = true; 1689 1690 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1691 1692 return 0; 1693 } 1694 1695 static int smu_display_configuration_change(void *handle, 1696 const struct amd_pp_display_configuration *display_config) 1697 { 1698 struct smu_context *smu = handle; 1699 int index = 0; 1700 int num_of_active_display = 0; 1701 1702 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1703 return -EOPNOTSUPP; 1704 1705 if (!display_config) 1706 return -EINVAL; 1707 1708 smu_set_min_dcef_deep_sleep(smu, 1709 display_config->min_dcef_deep_sleep_set_clk / 100); 1710 1711 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1712 if (display_config->displays[index].controller_id != 0) 1713 num_of_active_display++; 1714 } 1715 1716 return 0; 1717 } 1718 1719 static int smu_set_clockgating_state(void *handle, 1720 enum amd_clockgating_state state) 1721 { 1722 return 0; 1723 } 1724 1725 static int smu_set_powergating_state(void *handle, 1726 enum amd_powergating_state state) 1727 { 1728 return 0; 1729 } 1730 1731 static int smu_enable_umd_pstate(void *handle, 1732 enum amd_dpm_forced_level *level) 1733 { 1734 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1735 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1736 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1737 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1738 1739 struct smu_context *smu = (struct smu_context*)(handle); 1740 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1741 1742 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1743 return -EINVAL; 1744 1745 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1746 /* enter umd pstate, save current level, disable gfx cg*/ 1747 if (*level & profile_mode_mask) { 1748 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1749 smu_gpo_control(smu, false); 1750 smu_gfx_ulv_control(smu, false); 1751 smu_deep_sleep_control(smu, false); 1752 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1753 } 1754 } else { 1755 /* exit umd pstate, restore level, enable gfx cg*/ 1756 if (!(*level & profile_mode_mask)) { 1757 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1758 *level = smu_dpm_ctx->saved_dpm_level; 1759 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1760 smu_deep_sleep_control(smu, true); 1761 smu_gfx_ulv_control(smu, true); 1762 smu_gpo_control(smu, true); 1763 } 1764 } 1765 1766 return 0; 1767 } 1768 1769 static int smu_bump_power_profile_mode(struct smu_context *smu, 1770 long *param, 1771 uint32_t param_size) 1772 { 1773 int ret = 0; 1774 1775 if (smu->ppt_funcs->set_power_profile_mode) 1776 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1777 1778 return ret; 1779 } 1780 1781 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1782 enum amd_dpm_forced_level level, 1783 bool skip_display_settings) 1784 { 1785 int ret = 0; 1786 int index = 0; 1787 long workload; 1788 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1789 1790 if (!skip_display_settings) { 1791 ret = smu_display_config_changed(smu); 1792 if (ret) { 1793 dev_err(smu->adev->dev, "Failed to change display config!"); 1794 return ret; 1795 } 1796 } 1797 1798 ret = smu_apply_clocks_adjust_rules(smu); 1799 if (ret) { 1800 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1801 return ret; 1802 } 1803 1804 if (!skip_display_settings) { 1805 ret = smu_notify_smc_display_config(smu); 1806 if (ret) { 1807 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1808 return ret; 1809 } 1810 } 1811 1812 if (smu_dpm_ctx->dpm_level != level) { 1813 ret = smu_asic_set_performance_level(smu, level); 1814 if (ret) { 1815 dev_err(smu->adev->dev, "Failed to set performance level!"); 1816 return ret; 1817 } 1818 1819 /* update the saved copy */ 1820 smu_dpm_ctx->dpm_level = level; 1821 } 1822 1823 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1824 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1825 index = fls(smu->workload_mask); 1826 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1827 workload = smu->workload_setting[index]; 1828 1829 if (smu->power_profile_mode != workload) 1830 smu_bump_power_profile_mode(smu, &workload, 0); 1831 } 1832 1833 return ret; 1834 } 1835 1836 static int smu_handle_task(struct smu_context *smu, 1837 enum amd_dpm_forced_level level, 1838 enum amd_pp_task task_id) 1839 { 1840 int ret = 0; 1841 1842 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1843 return -EOPNOTSUPP; 1844 1845 switch (task_id) { 1846 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1847 ret = smu_pre_display_config_changed(smu); 1848 if (ret) 1849 return ret; 1850 ret = smu_adjust_power_state_dynamic(smu, level, false); 1851 break; 1852 case AMD_PP_TASK_COMPLETE_INIT: 1853 case AMD_PP_TASK_READJUST_POWER_STATE: 1854 ret = smu_adjust_power_state_dynamic(smu, level, true); 1855 break; 1856 default: 1857 break; 1858 } 1859 1860 return ret; 1861 } 1862 1863 static int smu_handle_dpm_task(void *handle, 1864 enum amd_pp_task task_id, 1865 enum amd_pm_state_type *user_state) 1866 { 1867 struct smu_context *smu = handle; 1868 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1869 1870 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 1871 1872 } 1873 1874 static int smu_switch_power_profile(void *handle, 1875 enum PP_SMC_POWER_PROFILE type, 1876 bool en) 1877 { 1878 struct smu_context *smu = handle; 1879 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1880 long workload; 1881 uint32_t index; 1882 1883 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1884 return -EOPNOTSUPP; 1885 1886 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1887 return -EINVAL; 1888 1889 if (!en) { 1890 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1891 index = fls(smu->workload_mask); 1892 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1893 workload = smu->workload_setting[index]; 1894 } else { 1895 smu->workload_mask |= (1 << smu->workload_prority[type]); 1896 index = fls(smu->workload_mask); 1897 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1898 workload = smu->workload_setting[index]; 1899 } 1900 1901 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1902 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1903 smu_bump_power_profile_mode(smu, &workload, 0); 1904 1905 return 0; 1906 } 1907 1908 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 1909 { 1910 struct smu_context *smu = handle; 1911 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1912 1913 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1914 return -EOPNOTSUPP; 1915 1916 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1917 return -EINVAL; 1918 1919 return smu_dpm_ctx->dpm_level; 1920 } 1921 1922 static int smu_force_performance_level(void *handle, 1923 enum amd_dpm_forced_level level) 1924 { 1925 struct smu_context *smu = handle; 1926 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1927 int ret = 0; 1928 1929 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1930 return -EOPNOTSUPP; 1931 1932 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1933 return -EINVAL; 1934 1935 ret = smu_enable_umd_pstate(smu, &level); 1936 if (ret) 1937 return ret; 1938 1939 ret = smu_handle_task(smu, level, 1940 AMD_PP_TASK_READJUST_POWER_STATE); 1941 1942 /* reset user dpm clock state */ 1943 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1944 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 1945 smu->user_dpm_profile.clk_dependency = 0; 1946 } 1947 1948 return ret; 1949 } 1950 1951 static int smu_set_display_count(void *handle, uint32_t count) 1952 { 1953 struct smu_context *smu = handle; 1954 1955 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1956 return -EOPNOTSUPP; 1957 1958 return smu_init_display_count(smu, count); 1959 } 1960 1961 static int smu_force_smuclk_levels(struct smu_context *smu, 1962 enum smu_clk_type clk_type, 1963 uint32_t mask) 1964 { 1965 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1966 int ret = 0; 1967 1968 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1969 return -EOPNOTSUPP; 1970 1971 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1972 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1973 return -EINVAL; 1974 } 1975 1976 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 1977 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1978 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 1979 smu->user_dpm_profile.clk_mask[clk_type] = mask; 1980 smu_set_user_clk_dependencies(smu, clk_type); 1981 } 1982 } 1983 1984 return ret; 1985 } 1986 1987 static int smu_force_ppclk_levels(void *handle, 1988 enum pp_clock_type type, 1989 uint32_t mask) 1990 { 1991 struct smu_context *smu = handle; 1992 enum smu_clk_type clk_type; 1993 1994 switch (type) { 1995 case PP_SCLK: 1996 clk_type = SMU_SCLK; break; 1997 case PP_MCLK: 1998 clk_type = SMU_MCLK; break; 1999 case PP_PCIE: 2000 clk_type = SMU_PCIE; break; 2001 case PP_SOCCLK: 2002 clk_type = SMU_SOCCLK; break; 2003 case PP_FCLK: 2004 clk_type = SMU_FCLK; break; 2005 case PP_DCEFCLK: 2006 clk_type = SMU_DCEFCLK; break; 2007 case PP_VCLK: 2008 clk_type = SMU_VCLK; break; 2009 case PP_DCLK: 2010 clk_type = SMU_DCLK; break; 2011 case OD_SCLK: 2012 clk_type = SMU_OD_SCLK; break; 2013 case OD_MCLK: 2014 clk_type = SMU_OD_MCLK; break; 2015 case OD_VDDC_CURVE: 2016 clk_type = SMU_OD_VDDC_CURVE; break; 2017 case OD_RANGE: 2018 clk_type = SMU_OD_RANGE; break; 2019 default: 2020 return -EINVAL; 2021 } 2022 2023 return smu_force_smuclk_levels(smu, clk_type, mask); 2024 } 2025 2026 /* 2027 * On system suspending or resetting, the dpm_enabled 2028 * flag will be cleared. So that those SMU services which 2029 * are not supported will be gated. 2030 * However, the mp1 state setting should still be granted 2031 * even if the dpm_enabled cleared. 2032 */ 2033 static int smu_set_mp1_state(void *handle, 2034 enum pp_mp1_state mp1_state) 2035 { 2036 struct smu_context *smu = handle; 2037 int ret = 0; 2038 2039 if (!smu->pm_enabled) 2040 return -EOPNOTSUPP; 2041 2042 if (smu->ppt_funcs && 2043 smu->ppt_funcs->set_mp1_state) 2044 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2045 2046 return ret; 2047 } 2048 2049 static int smu_set_df_cstate(void *handle, 2050 enum pp_df_cstate state) 2051 { 2052 struct smu_context *smu = handle; 2053 int ret = 0; 2054 2055 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2056 return -EOPNOTSUPP; 2057 2058 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2059 return 0; 2060 2061 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2062 if (ret) 2063 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2064 2065 return ret; 2066 } 2067 2068 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 2069 { 2070 int ret = 0; 2071 2072 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2073 return -EOPNOTSUPP; 2074 2075 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 2076 return 0; 2077 2078 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 2079 if (ret) 2080 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 2081 2082 return ret; 2083 } 2084 2085 int smu_write_watermarks_table(struct smu_context *smu) 2086 { 2087 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2088 return -EOPNOTSUPP; 2089 2090 return smu_set_watermarks_table(smu, NULL); 2091 } 2092 2093 static int smu_set_watermarks_for_clock_ranges(void *handle, 2094 struct pp_smu_wm_range_sets *clock_ranges) 2095 { 2096 struct smu_context *smu = handle; 2097 2098 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2099 return -EOPNOTSUPP; 2100 2101 if (smu->disable_watermark) 2102 return 0; 2103 2104 return smu_set_watermarks_table(smu, clock_ranges); 2105 } 2106 2107 int smu_set_ac_dc(struct smu_context *smu) 2108 { 2109 int ret = 0; 2110 2111 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2112 return -EOPNOTSUPP; 2113 2114 /* controlled by firmware */ 2115 if (smu->dc_controlled_by_gpio) 2116 return 0; 2117 2118 ret = smu_set_power_source(smu, 2119 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2120 SMU_POWER_SOURCE_DC); 2121 if (ret) 2122 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2123 smu->adev->pm.ac_power ? "AC" : "DC"); 2124 2125 return ret; 2126 } 2127 2128 const struct amd_ip_funcs smu_ip_funcs = { 2129 .name = "smu", 2130 .early_init = smu_early_init, 2131 .late_init = smu_late_init, 2132 .sw_init = smu_sw_init, 2133 .sw_fini = smu_sw_fini, 2134 .hw_init = smu_hw_init, 2135 .hw_fini = smu_hw_fini, 2136 .late_fini = smu_late_fini, 2137 .suspend = smu_suspend, 2138 .resume = smu_resume, 2139 .is_idle = NULL, 2140 .check_soft_reset = NULL, 2141 .wait_for_idle = NULL, 2142 .soft_reset = NULL, 2143 .set_clockgating_state = smu_set_clockgating_state, 2144 .set_powergating_state = smu_set_powergating_state, 2145 }; 2146 2147 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 2148 { 2149 .type = AMD_IP_BLOCK_TYPE_SMC, 2150 .major = 11, 2151 .minor = 0, 2152 .rev = 0, 2153 .funcs = &smu_ip_funcs, 2154 }; 2155 2156 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 2157 { 2158 .type = AMD_IP_BLOCK_TYPE_SMC, 2159 .major = 12, 2160 .minor = 0, 2161 .rev = 0, 2162 .funcs = &smu_ip_funcs, 2163 }; 2164 2165 const struct amdgpu_ip_block_version smu_v13_0_ip_block = 2166 { 2167 .type = AMD_IP_BLOCK_TYPE_SMC, 2168 .major = 13, 2169 .minor = 0, 2170 .rev = 0, 2171 .funcs = &smu_ip_funcs, 2172 }; 2173 2174 static int smu_load_microcode(void *handle) 2175 { 2176 struct smu_context *smu = handle; 2177 struct amdgpu_device *adev = smu->adev; 2178 int ret = 0; 2179 2180 if (!smu->pm_enabled) 2181 return -EOPNOTSUPP; 2182 2183 /* This should be used for non PSP loading */ 2184 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2185 return 0; 2186 2187 if (smu->ppt_funcs->load_microcode) { 2188 ret = smu->ppt_funcs->load_microcode(smu); 2189 if (ret) { 2190 dev_err(adev->dev, "Load microcode failed\n"); 2191 return ret; 2192 } 2193 } 2194 2195 if (smu->ppt_funcs->check_fw_status) { 2196 ret = smu->ppt_funcs->check_fw_status(smu); 2197 if (ret) { 2198 dev_err(adev->dev, "SMC is not ready\n"); 2199 return ret; 2200 } 2201 } 2202 2203 return ret; 2204 } 2205 2206 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2207 { 2208 int ret = 0; 2209 2210 if (smu->ppt_funcs->set_gfx_cgpg) 2211 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2212 2213 return ret; 2214 } 2215 2216 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2217 { 2218 struct smu_context *smu = handle; 2219 int ret = 0; 2220 2221 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2222 return -EOPNOTSUPP; 2223 2224 if (!smu->ppt_funcs->set_fan_speed_rpm) 2225 return -EOPNOTSUPP; 2226 2227 if (speed == U32_MAX) 2228 return -EINVAL; 2229 2230 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2231 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2232 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2233 smu->user_dpm_profile.fan_speed_rpm = speed; 2234 2235 /* Override custom PWM setting as they cannot co-exist */ 2236 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2237 smu->user_dpm_profile.fan_speed_pwm = 0; 2238 } 2239 2240 return ret; 2241 } 2242 2243 /** 2244 * smu_get_power_limit - Request one of the SMU Power Limits 2245 * 2246 * @handle: pointer to smu context 2247 * @limit: requested limit is written back to this variable 2248 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2249 * @pp_power_type: &pp_power_type type of power 2250 * Return: 0 on success, <0 on error 2251 * 2252 */ 2253 int smu_get_power_limit(void *handle, 2254 uint32_t *limit, 2255 enum pp_power_limit_level pp_limit_level, 2256 enum pp_power_type pp_power_type) 2257 { 2258 struct smu_context *smu = handle; 2259 struct amdgpu_device *adev = smu->adev; 2260 enum smu_ppt_limit_level limit_level; 2261 uint32_t limit_type; 2262 int ret = 0; 2263 2264 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2265 return -EOPNOTSUPP; 2266 2267 switch(pp_power_type) { 2268 case PP_PWR_TYPE_SUSTAINED: 2269 limit_type = SMU_DEFAULT_PPT_LIMIT; 2270 break; 2271 case PP_PWR_TYPE_FAST: 2272 limit_type = SMU_FAST_PPT_LIMIT; 2273 break; 2274 default: 2275 return -EOPNOTSUPP; 2276 break; 2277 } 2278 2279 switch(pp_limit_level){ 2280 case PP_PWR_LIMIT_CURRENT: 2281 limit_level = SMU_PPT_LIMIT_CURRENT; 2282 break; 2283 case PP_PWR_LIMIT_DEFAULT: 2284 limit_level = SMU_PPT_LIMIT_DEFAULT; 2285 break; 2286 case PP_PWR_LIMIT_MAX: 2287 limit_level = SMU_PPT_LIMIT_MAX; 2288 break; 2289 case PP_PWR_LIMIT_MIN: 2290 default: 2291 return -EOPNOTSUPP; 2292 break; 2293 } 2294 2295 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2296 if (smu->ppt_funcs->get_ppt_limit) 2297 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2298 } else { 2299 switch (limit_level) { 2300 case SMU_PPT_LIMIT_CURRENT: 2301 switch (adev->ip_versions[MP1_HWIP][0]) { 2302 case IP_VERSION(13, 0, 2): 2303 case IP_VERSION(11, 0, 7): 2304 case IP_VERSION(11, 0, 11): 2305 case IP_VERSION(11, 0, 12): 2306 case IP_VERSION(11, 0, 13): 2307 ret = smu_get_asic_power_limits(smu, 2308 &smu->current_power_limit, 2309 NULL, 2310 NULL); 2311 break; 2312 default: 2313 break; 2314 } 2315 *limit = smu->current_power_limit; 2316 break; 2317 case SMU_PPT_LIMIT_DEFAULT: 2318 *limit = smu->default_power_limit; 2319 break; 2320 case SMU_PPT_LIMIT_MAX: 2321 *limit = smu->max_power_limit; 2322 break; 2323 default: 2324 break; 2325 } 2326 } 2327 2328 return ret; 2329 } 2330 2331 static int smu_set_power_limit(void *handle, uint32_t limit) 2332 { 2333 struct smu_context *smu = handle; 2334 uint32_t limit_type = limit >> 24; 2335 int ret = 0; 2336 2337 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2338 return -EOPNOTSUPP; 2339 2340 limit &= (1<<24)-1; 2341 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2342 if (smu->ppt_funcs->set_power_limit) 2343 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2344 2345 if (limit > smu->max_power_limit) { 2346 dev_err(smu->adev->dev, 2347 "New power limit (%d) is over the max allowed %d\n", 2348 limit, smu->max_power_limit); 2349 return -EINVAL; 2350 } 2351 2352 if (!limit) 2353 limit = smu->current_power_limit; 2354 2355 if (smu->ppt_funcs->set_power_limit) { 2356 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2357 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2358 smu->user_dpm_profile.power_limit = limit; 2359 } 2360 2361 return ret; 2362 } 2363 2364 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2365 { 2366 int ret = 0; 2367 2368 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2369 return -EOPNOTSUPP; 2370 2371 if (smu->ppt_funcs->print_clk_levels) 2372 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2373 2374 return ret; 2375 } 2376 2377 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2378 { 2379 enum smu_clk_type clk_type; 2380 2381 switch (type) { 2382 case PP_SCLK: 2383 clk_type = SMU_SCLK; break; 2384 case PP_MCLK: 2385 clk_type = SMU_MCLK; break; 2386 case PP_PCIE: 2387 clk_type = SMU_PCIE; break; 2388 case PP_SOCCLK: 2389 clk_type = SMU_SOCCLK; break; 2390 case PP_FCLK: 2391 clk_type = SMU_FCLK; break; 2392 case PP_DCEFCLK: 2393 clk_type = SMU_DCEFCLK; break; 2394 case PP_VCLK: 2395 clk_type = SMU_VCLK; break; 2396 case PP_DCLK: 2397 clk_type = SMU_DCLK; break; 2398 case OD_SCLK: 2399 clk_type = SMU_OD_SCLK; break; 2400 case OD_MCLK: 2401 clk_type = SMU_OD_MCLK; break; 2402 case OD_VDDC_CURVE: 2403 clk_type = SMU_OD_VDDC_CURVE; break; 2404 case OD_RANGE: 2405 clk_type = SMU_OD_RANGE; break; 2406 case OD_VDDGFX_OFFSET: 2407 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2408 case OD_CCLK: 2409 clk_type = SMU_OD_CCLK; break; 2410 default: 2411 clk_type = SMU_CLK_COUNT; break; 2412 } 2413 2414 return clk_type; 2415 } 2416 2417 static int smu_print_ppclk_levels(void *handle, 2418 enum pp_clock_type type, 2419 char *buf) 2420 { 2421 struct smu_context *smu = handle; 2422 enum smu_clk_type clk_type; 2423 2424 clk_type = smu_convert_to_smuclk(type); 2425 if (clk_type == SMU_CLK_COUNT) 2426 return -EINVAL; 2427 2428 return smu_print_smuclk_levels(smu, clk_type, buf); 2429 } 2430 2431 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2432 { 2433 struct smu_context *smu = handle; 2434 enum smu_clk_type clk_type; 2435 2436 clk_type = smu_convert_to_smuclk(type); 2437 if (clk_type == SMU_CLK_COUNT) 2438 return -EINVAL; 2439 2440 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2441 return -EOPNOTSUPP; 2442 2443 if (!smu->ppt_funcs->emit_clk_levels) 2444 return -ENOENT; 2445 2446 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2447 2448 } 2449 2450 static int smu_od_edit_dpm_table(void *handle, 2451 enum PP_OD_DPM_TABLE_COMMAND type, 2452 long *input, uint32_t size) 2453 { 2454 struct smu_context *smu = handle; 2455 int ret = 0; 2456 2457 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2458 return -EOPNOTSUPP; 2459 2460 if (smu->ppt_funcs->od_edit_dpm_table) { 2461 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2462 } 2463 2464 return ret; 2465 } 2466 2467 static int smu_read_sensor(void *handle, 2468 int sensor, 2469 void *data, 2470 int *size_arg) 2471 { 2472 struct smu_context *smu = handle; 2473 struct smu_umd_pstate_table *pstate_table = 2474 &smu->pstate_table; 2475 int ret = 0; 2476 uint32_t *size, size_val; 2477 2478 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2479 return -EOPNOTSUPP; 2480 2481 if (!data || !size_arg) 2482 return -EINVAL; 2483 2484 size_val = *size_arg; 2485 size = &size_val; 2486 2487 if (smu->ppt_funcs->read_sensor) 2488 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2489 goto unlock; 2490 2491 switch (sensor) { 2492 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2493 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2494 *size = 4; 2495 break; 2496 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2497 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2498 *size = 4; 2499 break; 2500 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 2501 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 2502 *size = 4; 2503 break; 2504 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 2505 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 2506 *size = 4; 2507 break; 2508 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2509 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2510 *size = 8; 2511 break; 2512 case AMDGPU_PP_SENSOR_UVD_POWER: 2513 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2514 *size = 4; 2515 break; 2516 case AMDGPU_PP_SENSOR_VCE_POWER: 2517 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2518 *size = 4; 2519 break; 2520 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2521 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2522 *size = 4; 2523 break; 2524 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2525 *(uint32_t *)data = 0; 2526 *size = 4; 2527 break; 2528 default: 2529 *size = 0; 2530 ret = -EOPNOTSUPP; 2531 break; 2532 } 2533 2534 unlock: 2535 // assign uint32_t to int 2536 *size_arg = size_val; 2537 2538 return ret; 2539 } 2540 2541 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 2542 { 2543 int ret = -EINVAL; 2544 struct smu_context *smu = handle; 2545 2546 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 2547 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 2548 2549 return ret; 2550 } 2551 2552 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 2553 { 2554 int ret = -EINVAL; 2555 struct smu_context *smu = handle; 2556 2557 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 2558 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 2559 2560 return ret; 2561 } 2562 2563 static int smu_get_power_profile_mode(void *handle, char *buf) 2564 { 2565 struct smu_context *smu = handle; 2566 2567 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2568 !smu->ppt_funcs->get_power_profile_mode) 2569 return -EOPNOTSUPP; 2570 if (!buf) 2571 return -EINVAL; 2572 2573 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 2574 } 2575 2576 static int smu_set_power_profile_mode(void *handle, 2577 long *param, 2578 uint32_t param_size) 2579 { 2580 struct smu_context *smu = handle; 2581 2582 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2583 !smu->ppt_funcs->set_power_profile_mode) 2584 return -EOPNOTSUPP; 2585 2586 return smu_bump_power_profile_mode(smu, param, param_size); 2587 } 2588 2589 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 2590 { 2591 struct smu_context *smu = handle; 2592 2593 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2594 return -EOPNOTSUPP; 2595 2596 if (!smu->ppt_funcs->get_fan_control_mode) 2597 return -EOPNOTSUPP; 2598 2599 if (!fan_mode) 2600 return -EINVAL; 2601 2602 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 2603 2604 return 0; 2605 } 2606 2607 static int smu_set_fan_control_mode(void *handle, u32 value) 2608 { 2609 struct smu_context *smu = handle; 2610 int ret = 0; 2611 2612 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2613 return -EOPNOTSUPP; 2614 2615 if (!smu->ppt_funcs->set_fan_control_mode) 2616 return -EOPNOTSUPP; 2617 2618 if (value == U32_MAX) 2619 return -EINVAL; 2620 2621 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2622 if (ret) 2623 goto out; 2624 2625 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2626 smu->user_dpm_profile.fan_mode = value; 2627 2628 /* reset user dpm fan speed */ 2629 if (value != AMD_FAN_CTRL_MANUAL) { 2630 smu->user_dpm_profile.fan_speed_pwm = 0; 2631 smu->user_dpm_profile.fan_speed_rpm = 0; 2632 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 2633 } 2634 } 2635 2636 out: 2637 return ret; 2638 } 2639 2640 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 2641 { 2642 struct smu_context *smu = handle; 2643 int ret = 0; 2644 2645 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2646 return -EOPNOTSUPP; 2647 2648 if (!smu->ppt_funcs->get_fan_speed_pwm) 2649 return -EOPNOTSUPP; 2650 2651 if (!speed) 2652 return -EINVAL; 2653 2654 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 2655 2656 return ret; 2657 } 2658 2659 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 2660 { 2661 struct smu_context *smu = handle; 2662 int ret = 0; 2663 2664 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2665 return -EOPNOTSUPP; 2666 2667 if (!smu->ppt_funcs->set_fan_speed_pwm) 2668 return -EOPNOTSUPP; 2669 2670 if (speed == U32_MAX) 2671 return -EINVAL; 2672 2673 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 2674 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2675 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 2676 smu->user_dpm_profile.fan_speed_pwm = speed; 2677 2678 /* Override custom RPM setting as they cannot co-exist */ 2679 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 2680 smu->user_dpm_profile.fan_speed_rpm = 0; 2681 } 2682 2683 return ret; 2684 } 2685 2686 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2687 { 2688 struct smu_context *smu = handle; 2689 int ret = 0; 2690 2691 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2692 return -EOPNOTSUPP; 2693 2694 if (!smu->ppt_funcs->get_fan_speed_rpm) 2695 return -EOPNOTSUPP; 2696 2697 if (!speed) 2698 return -EINVAL; 2699 2700 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 2701 2702 return ret; 2703 } 2704 2705 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 2706 { 2707 struct smu_context *smu = handle; 2708 2709 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2710 return -EOPNOTSUPP; 2711 2712 return smu_set_min_dcef_deep_sleep(smu, clk); 2713 } 2714 2715 static int smu_get_clock_by_type_with_latency(void *handle, 2716 enum amd_pp_clock_type type, 2717 struct pp_clock_levels_with_latency *clocks) 2718 { 2719 struct smu_context *smu = handle; 2720 enum smu_clk_type clk_type; 2721 int ret = 0; 2722 2723 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2724 return -EOPNOTSUPP; 2725 2726 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 2727 switch (type) { 2728 case amd_pp_sys_clock: 2729 clk_type = SMU_GFXCLK; 2730 break; 2731 case amd_pp_mem_clock: 2732 clk_type = SMU_MCLK; 2733 break; 2734 case amd_pp_dcef_clock: 2735 clk_type = SMU_DCEFCLK; 2736 break; 2737 case amd_pp_disp_clock: 2738 clk_type = SMU_DISPCLK; 2739 break; 2740 default: 2741 dev_err(smu->adev->dev, "Invalid clock type!\n"); 2742 return -EINVAL; 2743 } 2744 2745 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2746 } 2747 2748 return ret; 2749 } 2750 2751 static int smu_display_clock_voltage_request(void *handle, 2752 struct pp_display_clock_request *clock_req) 2753 { 2754 struct smu_context *smu = handle; 2755 int ret = 0; 2756 2757 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2758 return -EOPNOTSUPP; 2759 2760 if (smu->ppt_funcs->display_clock_voltage_request) 2761 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2762 2763 return ret; 2764 } 2765 2766 2767 static int smu_display_disable_memory_clock_switch(void *handle, 2768 bool disable_memory_clock_switch) 2769 { 2770 struct smu_context *smu = handle; 2771 int ret = -EINVAL; 2772 2773 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2774 return -EOPNOTSUPP; 2775 2776 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2777 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2778 2779 return ret; 2780 } 2781 2782 static int smu_set_xgmi_pstate(void *handle, 2783 uint32_t pstate) 2784 { 2785 struct smu_context *smu = handle; 2786 int ret = 0; 2787 2788 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2789 return -EOPNOTSUPP; 2790 2791 if (smu->ppt_funcs->set_xgmi_pstate) 2792 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2793 2794 if(ret) 2795 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2796 2797 return ret; 2798 } 2799 2800 static int smu_get_baco_capability(void *handle, bool *cap) 2801 { 2802 struct smu_context *smu = handle; 2803 2804 *cap = false; 2805 2806 if (!smu->pm_enabled) 2807 return 0; 2808 2809 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2810 *cap = smu->ppt_funcs->baco_is_support(smu); 2811 2812 return 0; 2813 } 2814 2815 static int smu_baco_set_state(void *handle, int state) 2816 { 2817 struct smu_context *smu = handle; 2818 int ret = 0; 2819 2820 if (!smu->pm_enabled) 2821 return -EOPNOTSUPP; 2822 2823 if (state == 0) { 2824 if (smu->ppt_funcs->baco_exit) 2825 ret = smu->ppt_funcs->baco_exit(smu); 2826 } else if (state == 1) { 2827 if (smu->ppt_funcs->baco_enter) 2828 ret = smu->ppt_funcs->baco_enter(smu); 2829 } else { 2830 return -EINVAL; 2831 } 2832 2833 if (ret) 2834 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 2835 (state)?"enter":"exit"); 2836 2837 return ret; 2838 } 2839 2840 bool smu_mode1_reset_is_support(struct smu_context *smu) 2841 { 2842 bool ret = false; 2843 2844 if (!smu->pm_enabled) 2845 return false; 2846 2847 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2848 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2849 2850 return ret; 2851 } 2852 2853 bool smu_mode2_reset_is_support(struct smu_context *smu) 2854 { 2855 bool ret = false; 2856 2857 if (!smu->pm_enabled) 2858 return false; 2859 2860 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 2861 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 2862 2863 return ret; 2864 } 2865 2866 int smu_mode1_reset(struct smu_context *smu) 2867 { 2868 int ret = 0; 2869 2870 if (!smu->pm_enabled) 2871 return -EOPNOTSUPP; 2872 2873 if (smu->ppt_funcs->mode1_reset) 2874 ret = smu->ppt_funcs->mode1_reset(smu); 2875 2876 return ret; 2877 } 2878 2879 static int smu_mode2_reset(void *handle) 2880 { 2881 struct smu_context *smu = handle; 2882 int ret = 0; 2883 2884 if (!smu->pm_enabled) 2885 return -EOPNOTSUPP; 2886 2887 if (smu->ppt_funcs->mode2_reset) 2888 ret = smu->ppt_funcs->mode2_reset(smu); 2889 2890 if (ret) 2891 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2892 2893 return ret; 2894 } 2895 2896 static int smu_enable_gfx_features(void *handle) 2897 { 2898 struct smu_context *smu = handle; 2899 int ret = 0; 2900 2901 if (!smu->pm_enabled) 2902 return -EOPNOTSUPP; 2903 2904 if (smu->ppt_funcs->enable_gfx_features) 2905 ret = smu->ppt_funcs->enable_gfx_features(smu); 2906 2907 if (ret) 2908 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 2909 2910 return ret; 2911 } 2912 2913 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 2914 struct pp_smu_nv_clock_table *max_clocks) 2915 { 2916 struct smu_context *smu = handle; 2917 int ret = 0; 2918 2919 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2920 return -EOPNOTSUPP; 2921 2922 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2923 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2924 2925 return ret; 2926 } 2927 2928 static int smu_get_uclk_dpm_states(void *handle, 2929 unsigned int *clock_values_in_khz, 2930 unsigned int *num_states) 2931 { 2932 struct smu_context *smu = handle; 2933 int ret = 0; 2934 2935 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2936 return -EOPNOTSUPP; 2937 2938 if (smu->ppt_funcs->get_uclk_dpm_states) 2939 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2940 2941 return ret; 2942 } 2943 2944 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 2945 { 2946 struct smu_context *smu = handle; 2947 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2948 2949 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2950 return -EOPNOTSUPP; 2951 2952 if (smu->ppt_funcs->get_current_power_state) 2953 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2954 2955 return pm_state; 2956 } 2957 2958 static int smu_get_dpm_clock_table(void *handle, 2959 struct dpm_clocks *clock_table) 2960 { 2961 struct smu_context *smu = handle; 2962 int ret = 0; 2963 2964 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2965 return -EOPNOTSUPP; 2966 2967 if (smu->ppt_funcs->get_dpm_clock_table) 2968 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 2969 2970 return ret; 2971 } 2972 2973 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 2974 { 2975 struct smu_context *smu = handle; 2976 2977 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2978 return -EOPNOTSUPP; 2979 2980 if (!smu->ppt_funcs->get_gpu_metrics) 2981 return -EOPNOTSUPP; 2982 2983 return smu->ppt_funcs->get_gpu_metrics(smu, table); 2984 } 2985 2986 static int smu_enable_mgpu_fan_boost(void *handle) 2987 { 2988 struct smu_context *smu = handle; 2989 int ret = 0; 2990 2991 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2992 return -EOPNOTSUPP; 2993 2994 if (smu->ppt_funcs->enable_mgpu_fan_boost) 2995 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 2996 2997 return ret; 2998 } 2999 3000 static int smu_gfx_state_change_set(void *handle, 3001 uint32_t state) 3002 { 3003 struct smu_context *smu = handle; 3004 int ret = 0; 3005 3006 if (smu->ppt_funcs->gfx_state_change_set) 3007 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3008 3009 return ret; 3010 } 3011 3012 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3013 { 3014 int ret = 0; 3015 3016 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3017 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3018 3019 return ret; 3020 } 3021 3022 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3023 { 3024 int ret = -EOPNOTSUPP; 3025 3026 if (smu->ppt_funcs && 3027 smu->ppt_funcs->get_ecc_info) 3028 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3029 3030 return ret; 3031 3032 } 3033 3034 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3035 { 3036 struct smu_context *smu = handle; 3037 struct smu_table_context *smu_table = &smu->smu_table; 3038 struct smu_table *memory_pool = &smu_table->memory_pool; 3039 3040 if (!addr || !size) 3041 return -EINVAL; 3042 3043 *addr = NULL; 3044 *size = 0; 3045 if (memory_pool->bo) { 3046 *addr = memory_pool->cpu_addr; 3047 *size = memory_pool->size; 3048 } 3049 3050 return 0; 3051 } 3052 3053 static const struct amd_pm_funcs swsmu_pm_funcs = { 3054 /* export for sysfs */ 3055 .set_fan_control_mode = smu_set_fan_control_mode, 3056 .get_fan_control_mode = smu_get_fan_control_mode, 3057 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3058 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3059 .force_clock_level = smu_force_ppclk_levels, 3060 .print_clock_levels = smu_print_ppclk_levels, 3061 .emit_clock_levels = smu_emit_ppclk_levels, 3062 .force_performance_level = smu_force_performance_level, 3063 .read_sensor = smu_read_sensor, 3064 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3065 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3066 .get_performance_level = smu_get_performance_level, 3067 .get_current_power_state = smu_get_current_power_state, 3068 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3069 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3070 .get_pp_num_states = smu_get_power_num_states, 3071 .get_pp_table = smu_sys_get_pp_table, 3072 .set_pp_table = smu_sys_set_pp_table, 3073 .switch_power_profile = smu_switch_power_profile, 3074 /* export to amdgpu */ 3075 .dispatch_tasks = smu_handle_dpm_task, 3076 .load_firmware = smu_load_microcode, 3077 .set_powergating_by_smu = smu_dpm_set_power_gate, 3078 .set_power_limit = smu_set_power_limit, 3079 .get_power_limit = smu_get_power_limit, 3080 .get_power_profile_mode = smu_get_power_profile_mode, 3081 .set_power_profile_mode = smu_set_power_profile_mode, 3082 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3083 .set_mp1_state = smu_set_mp1_state, 3084 .gfx_state_change_set = smu_gfx_state_change_set, 3085 /* export to DC */ 3086 .get_sclk = smu_get_sclk, 3087 .get_mclk = smu_get_mclk, 3088 .display_configuration_change = smu_display_configuration_change, 3089 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3090 .display_clock_voltage_request = smu_display_clock_voltage_request, 3091 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3092 .set_active_display_count = smu_set_display_count, 3093 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3094 .get_asic_baco_capability = smu_get_baco_capability, 3095 .set_asic_baco_state = smu_baco_set_state, 3096 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3097 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3098 .asic_reset_mode_2 = smu_mode2_reset, 3099 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3100 .set_df_cstate = smu_set_df_cstate, 3101 .set_xgmi_pstate = smu_set_xgmi_pstate, 3102 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3103 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3104 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3105 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3106 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3107 .get_dpm_clock_table = smu_get_dpm_clock_table, 3108 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3109 }; 3110 3111 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3112 uint64_t event_arg) 3113 { 3114 int ret = -EINVAL; 3115 3116 if (smu->ppt_funcs->wait_for_event) 3117 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3118 3119 return ret; 3120 } 3121 3122 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3123 { 3124 3125 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3126 return -EOPNOTSUPP; 3127 3128 /* Confirm the buffer allocated is of correct size */ 3129 if (size != smu->stb_context.stb_buf_size) 3130 return -EINVAL; 3131 3132 /* 3133 * No need to lock smu mutex as we access STB directly through MMIO 3134 * and not going through SMU messaging route (for now at least). 3135 * For registers access rely on implementation internal locking. 3136 */ 3137 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3138 } 3139 3140 #if defined(CONFIG_DEBUG_FS) 3141 3142 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3143 { 3144 struct amdgpu_device *adev = filp->f_inode->i_private; 3145 struct smu_context *smu = adev->powerplay.pp_handle; 3146 unsigned char *buf; 3147 int r; 3148 3149 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3150 if (!buf) 3151 return -ENOMEM; 3152 3153 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3154 if (r) 3155 goto out; 3156 3157 filp->private_data = buf; 3158 3159 return 0; 3160 3161 out: 3162 kvfree(buf); 3163 return r; 3164 } 3165 3166 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3167 loff_t *pos) 3168 { 3169 struct amdgpu_device *adev = filp->f_inode->i_private; 3170 struct smu_context *smu = adev->powerplay.pp_handle; 3171 3172 3173 if (!filp->private_data) 3174 return -EINVAL; 3175 3176 return simple_read_from_buffer(buf, 3177 size, 3178 pos, filp->private_data, 3179 smu->stb_context.stb_buf_size); 3180 } 3181 3182 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3183 { 3184 kvfree(filp->private_data); 3185 filp->private_data = NULL; 3186 3187 return 0; 3188 } 3189 3190 /* 3191 * We have to define not only read method but also 3192 * open and release because .read takes up to PAGE_SIZE 3193 * data each time so and so is invoked multiple times. 3194 * We allocate the STB buffer in .open and release it 3195 * in .release 3196 */ 3197 static const struct file_operations smu_stb_debugfs_fops = { 3198 .owner = THIS_MODULE, 3199 .open = smu_stb_debugfs_open, 3200 .read = smu_stb_debugfs_read, 3201 .release = smu_stb_debugfs_release, 3202 .llseek = default_llseek, 3203 }; 3204 3205 #endif 3206 3207 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3208 { 3209 #if defined(CONFIG_DEBUG_FS) 3210 3211 struct smu_context *smu = adev->powerplay.pp_handle; 3212 3213 if (!smu || (!smu->stb_context.stb_buf_size)) 3214 return; 3215 3216 debugfs_create_file_size("amdgpu_smu_stb_dump", 3217 S_IRUSR, 3218 adev_to_drm(adev)->primary->debugfs_root, 3219 adev, 3220 &smu_stb_debugfs_fops, 3221 smu->stb_context.stb_buf_size); 3222 #endif 3223 } 3224 3225 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3226 { 3227 int ret = 0; 3228 3229 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3230 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3231 3232 return ret; 3233 } 3234 3235 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3236 { 3237 int ret = 0; 3238 3239 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3240 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3241 3242 return ret; 3243 } 3244