1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "amd_pcie.h" 38 39 /* 40 * DO NOT use these for err/warn/info/debug messages. 41 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 42 * They are more MGPU friendly. 43 */ 44 #undef pr_err 45 #undef pr_warn 46 #undef pr_info 47 #undef pr_debug 48 49 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf) 50 { 51 size_t size = 0; 52 53 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 54 return -EOPNOTSUPP; 55 56 mutex_lock(&smu->mutex); 57 58 size = smu_get_pp_feature_mask(smu, buf); 59 60 mutex_unlock(&smu->mutex); 61 62 return size; 63 } 64 65 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask) 66 { 67 int ret = 0; 68 69 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 70 return -EOPNOTSUPP; 71 72 mutex_lock(&smu->mutex); 73 74 ret = smu_set_pp_feature_mask(smu, new_mask); 75 76 mutex_unlock(&smu->mutex); 77 78 return ret; 79 } 80 81 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) 82 { 83 int ret = 0; 84 struct smu_context *smu = &adev->smu; 85 86 if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status) 87 *value = smu_get_gfx_off_status(smu); 88 else 89 ret = -EINVAL; 90 91 return ret; 92 } 93 94 int smu_set_soft_freq_range(struct smu_context *smu, 95 enum smu_clk_type clk_type, 96 uint32_t min, 97 uint32_t max) 98 { 99 int ret = 0; 100 101 mutex_lock(&smu->mutex); 102 103 if (smu->ppt_funcs->set_soft_freq_limited_range) 104 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 105 clk_type, 106 min, 107 max); 108 109 mutex_unlock(&smu->mutex); 110 111 return ret; 112 } 113 114 int smu_get_dpm_freq_range(struct smu_context *smu, 115 enum smu_clk_type clk_type, 116 uint32_t *min, 117 uint32_t *max) 118 { 119 int ret = 0; 120 121 if (!min && !max) 122 return -EINVAL; 123 124 mutex_lock(&smu->mutex); 125 126 if (smu->ppt_funcs->get_dpm_ultimate_freq) 127 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 128 clk_type, 129 min, 130 max); 131 132 mutex_unlock(&smu->mutex); 133 134 return ret; 135 } 136 137 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu, 138 bool enable) 139 { 140 struct smu_power_context *smu_power = &smu->smu_power; 141 struct smu_power_gate *power_gate = &smu_power->power_gate; 142 int ret = 0; 143 144 if (!smu->ppt_funcs->dpm_set_vcn_enable) 145 return 0; 146 147 if (atomic_read(&power_gate->vcn_gated) ^ enable) 148 return 0; 149 150 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 151 if (!ret) 152 atomic_set(&power_gate->vcn_gated, !enable); 153 154 return ret; 155 } 156 157 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 158 bool enable) 159 { 160 struct smu_power_context *smu_power = &smu->smu_power; 161 struct smu_power_gate *power_gate = &smu_power->power_gate; 162 int ret = 0; 163 164 mutex_lock(&power_gate->vcn_gate_lock); 165 166 ret = smu_dpm_set_vcn_enable_locked(smu, enable); 167 168 mutex_unlock(&power_gate->vcn_gate_lock); 169 170 return ret; 171 } 172 173 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu, 174 bool enable) 175 { 176 struct smu_power_context *smu_power = &smu->smu_power; 177 struct smu_power_gate *power_gate = &smu_power->power_gate; 178 int ret = 0; 179 180 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 181 return 0; 182 183 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 184 return 0; 185 186 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 187 if (!ret) 188 atomic_set(&power_gate->jpeg_gated, !enable); 189 190 return ret; 191 } 192 193 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 194 bool enable) 195 { 196 struct smu_power_context *smu_power = &smu->smu_power; 197 struct smu_power_gate *power_gate = &smu_power->power_gate; 198 int ret = 0; 199 200 mutex_lock(&power_gate->jpeg_gate_lock); 201 202 ret = smu_dpm_set_jpeg_enable_locked(smu, enable); 203 204 mutex_unlock(&power_gate->jpeg_gate_lock); 205 206 return ret; 207 } 208 209 /** 210 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 211 * 212 * @smu: smu_context pointer 213 * @block_type: the IP block to power gate/ungate 214 * @gate: to power gate if true, ungate otherwise 215 * 216 * This API uses no smu->mutex lock protection due to: 217 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 218 * This is guarded to be race condition free by the caller. 219 * 2. Or get called on user setting request of power_dpm_force_performance_level. 220 * Under this case, the smu->mutex lock protection is already enforced on 221 * the parent API smu_force_performance_level of the call path. 222 */ 223 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type, 224 bool gate) 225 { 226 int ret = 0; 227 228 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 229 return -EOPNOTSUPP; 230 231 switch (block_type) { 232 /* 233 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 234 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 235 */ 236 case AMD_IP_BLOCK_TYPE_UVD: 237 case AMD_IP_BLOCK_TYPE_VCN: 238 ret = smu_dpm_set_vcn_enable(smu, !gate); 239 if (ret) 240 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 241 gate ? "gate" : "ungate"); 242 break; 243 case AMD_IP_BLOCK_TYPE_GFX: 244 ret = smu_gfx_off_control(smu, gate); 245 if (ret) 246 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 247 gate ? "enable" : "disable"); 248 break; 249 case AMD_IP_BLOCK_TYPE_SDMA: 250 ret = smu_powergate_sdma(smu, gate); 251 if (ret) 252 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 253 gate ? "gate" : "ungate"); 254 break; 255 case AMD_IP_BLOCK_TYPE_JPEG: 256 ret = smu_dpm_set_jpeg_enable(smu, !gate); 257 if (ret) 258 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 259 gate ? "gate" : "ungate"); 260 break; 261 default: 262 dev_err(smu->adev->dev, "Unsupported block type!\n"); 263 return -EINVAL; 264 } 265 266 return ret; 267 } 268 269 int smu_get_power_num_states(struct smu_context *smu, 270 struct pp_states_info *state_info) 271 { 272 if (!state_info) 273 return -EINVAL; 274 275 /* not support power state */ 276 memset(state_info, 0, sizeof(struct pp_states_info)); 277 state_info->nums = 1; 278 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 279 280 return 0; 281 } 282 283 bool is_support_sw_smu(struct amdgpu_device *adev) 284 { 285 if (adev->asic_type >= CHIP_ARCTURUS) 286 return true; 287 288 return false; 289 } 290 291 int smu_sys_get_pp_table(struct smu_context *smu, void **table) 292 { 293 struct smu_table_context *smu_table = &smu->smu_table; 294 uint32_t powerplay_table_size; 295 296 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 297 return -EOPNOTSUPP; 298 299 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 300 return -EINVAL; 301 302 mutex_lock(&smu->mutex); 303 304 if (smu_table->hardcode_pptable) 305 *table = smu_table->hardcode_pptable; 306 else 307 *table = smu_table->power_play_table; 308 309 powerplay_table_size = smu_table->power_play_table_size; 310 311 mutex_unlock(&smu->mutex); 312 313 return powerplay_table_size; 314 } 315 316 int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size) 317 { 318 struct smu_table_context *smu_table = &smu->smu_table; 319 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 320 int ret = 0; 321 322 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 323 return -EOPNOTSUPP; 324 325 if (header->usStructureSize != size) { 326 dev_err(smu->adev->dev, "pp table size not matched !\n"); 327 return -EIO; 328 } 329 330 mutex_lock(&smu->mutex); 331 if (!smu_table->hardcode_pptable) 332 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 333 if (!smu_table->hardcode_pptable) { 334 ret = -ENOMEM; 335 goto failed; 336 } 337 338 memcpy(smu_table->hardcode_pptable, buf, size); 339 smu_table->power_play_table = smu_table->hardcode_pptable; 340 smu_table->power_play_table_size = size; 341 342 /* 343 * Special hw_fini action(for Navi1x, the DPMs disablement will be 344 * skipped) may be needed for custom pptable uploading. 345 */ 346 smu->uploading_custom_pp_table = true; 347 348 ret = smu_reset(smu); 349 if (ret) 350 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 351 352 smu->uploading_custom_pp_table = false; 353 354 failed: 355 mutex_unlock(&smu->mutex); 356 return ret; 357 } 358 359 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 360 { 361 struct smu_feature *feature = &smu->smu_feature; 362 int ret = 0; 363 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 364 365 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 366 367 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 368 SMU_FEATURE_MAX/32); 369 if (ret) 370 return ret; 371 372 bitmap_or(feature->allowed, feature->allowed, 373 (unsigned long *)allowed_feature_mask, 374 feature->feature_num); 375 376 return ret; 377 } 378 379 static int smu_set_funcs(struct amdgpu_device *adev) 380 { 381 struct smu_context *smu = &adev->smu; 382 383 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 384 smu->od_enabled = true; 385 386 switch (adev->asic_type) { 387 case CHIP_NAVI10: 388 case CHIP_NAVI14: 389 case CHIP_NAVI12: 390 navi10_set_ppt_funcs(smu); 391 break; 392 case CHIP_ARCTURUS: 393 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 394 arcturus_set_ppt_funcs(smu); 395 /* OD is not supported on Arcturus */ 396 smu->od_enabled =false; 397 break; 398 case CHIP_SIENNA_CICHLID: 399 case CHIP_NAVY_FLOUNDER: 400 case CHIP_DIMGREY_CAVEFISH: 401 sienna_cichlid_set_ppt_funcs(smu); 402 break; 403 case CHIP_RENOIR: 404 renoir_set_ppt_funcs(smu); 405 break; 406 case CHIP_VANGOGH: 407 vangogh_set_ppt_funcs(smu); 408 /* enable the OD by default to allow the fine grain tuning function */ 409 smu->od_enabled = true; 410 break; 411 default: 412 return -EINVAL; 413 } 414 415 return 0; 416 } 417 418 static int smu_early_init(void *handle) 419 { 420 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 421 struct smu_context *smu = &adev->smu; 422 423 smu->adev = adev; 424 smu->pm_enabled = !!amdgpu_dpm; 425 smu->is_apu = false; 426 mutex_init(&smu->mutex); 427 mutex_init(&smu->smu_baco.mutex); 428 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 429 smu->smu_baco.platform_support = false; 430 431 return smu_set_funcs(adev); 432 } 433 434 static int smu_set_default_dpm_table(struct smu_context *smu) 435 { 436 struct smu_power_context *smu_power = &smu->smu_power; 437 struct smu_power_gate *power_gate = &smu_power->power_gate; 438 int vcn_gate, jpeg_gate; 439 int ret = 0; 440 441 if (!smu->ppt_funcs->set_default_dpm_table) 442 return 0; 443 444 mutex_lock(&power_gate->vcn_gate_lock); 445 mutex_lock(&power_gate->jpeg_gate_lock); 446 447 vcn_gate = atomic_read(&power_gate->vcn_gated); 448 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 449 450 ret = smu_dpm_set_vcn_enable_locked(smu, true); 451 if (ret) 452 goto err0_out; 453 454 ret = smu_dpm_set_jpeg_enable_locked(smu, true); 455 if (ret) 456 goto err1_out; 457 458 ret = smu->ppt_funcs->set_default_dpm_table(smu); 459 if (ret) 460 dev_err(smu->adev->dev, 461 "Failed to setup default dpm clock tables!\n"); 462 463 smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate); 464 err1_out: 465 smu_dpm_set_vcn_enable_locked(smu, !vcn_gate); 466 err0_out: 467 mutex_unlock(&power_gate->jpeg_gate_lock); 468 mutex_unlock(&power_gate->vcn_gate_lock); 469 470 return ret; 471 } 472 473 static int smu_late_init(void *handle) 474 { 475 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 476 struct smu_context *smu = &adev->smu; 477 int ret = 0; 478 479 smu_set_fine_grain_gfx_freq_parameters(smu); 480 481 if (adev->asic_type == CHIP_VANGOGH) 482 return 0; 483 484 if (!smu->pm_enabled) 485 return 0; 486 487 ret = smu_post_init(smu); 488 if (ret) { 489 dev_err(adev->dev, "Failed to post smu init!\n"); 490 return ret; 491 } 492 493 ret = smu_set_default_od_settings(smu); 494 if (ret) { 495 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 496 return ret; 497 } 498 499 ret = smu_populate_umd_state_clk(smu); 500 if (ret) { 501 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 502 return ret; 503 } 504 505 ret = smu_get_asic_power_limits(smu); 506 if (ret) { 507 dev_err(adev->dev, "Failed to get asic power limits!\n"); 508 return ret; 509 } 510 511 smu_get_unique_id(smu); 512 513 smu_get_fan_parameters(smu); 514 515 smu_handle_task(&adev->smu, 516 smu->smu_dpm.dpm_level, 517 AMD_PP_TASK_COMPLETE_INIT, 518 false); 519 520 return 0; 521 } 522 523 static int smu_init_fb_allocations(struct smu_context *smu) 524 { 525 struct amdgpu_device *adev = smu->adev; 526 struct smu_table_context *smu_table = &smu->smu_table; 527 struct smu_table *tables = smu_table->tables; 528 struct smu_table *driver_table = &(smu_table->driver_table); 529 uint32_t max_table_size = 0; 530 int ret, i; 531 532 /* VRAM allocation for tool table */ 533 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 534 ret = amdgpu_bo_create_kernel(adev, 535 tables[SMU_TABLE_PMSTATUSLOG].size, 536 tables[SMU_TABLE_PMSTATUSLOG].align, 537 tables[SMU_TABLE_PMSTATUSLOG].domain, 538 &tables[SMU_TABLE_PMSTATUSLOG].bo, 539 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 540 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 541 if (ret) { 542 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 543 return ret; 544 } 545 } 546 547 /* VRAM allocation for driver table */ 548 for (i = 0; i < SMU_TABLE_COUNT; i++) { 549 if (tables[i].size == 0) 550 continue; 551 552 if (i == SMU_TABLE_PMSTATUSLOG) 553 continue; 554 555 if (max_table_size < tables[i].size) 556 max_table_size = tables[i].size; 557 } 558 559 driver_table->size = max_table_size; 560 driver_table->align = PAGE_SIZE; 561 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 562 563 ret = amdgpu_bo_create_kernel(adev, 564 driver_table->size, 565 driver_table->align, 566 driver_table->domain, 567 &driver_table->bo, 568 &driver_table->mc_address, 569 &driver_table->cpu_addr); 570 if (ret) { 571 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 572 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 573 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 574 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 575 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 576 } 577 578 return ret; 579 } 580 581 static int smu_fini_fb_allocations(struct smu_context *smu) 582 { 583 struct smu_table_context *smu_table = &smu->smu_table; 584 struct smu_table *tables = smu_table->tables; 585 struct smu_table *driver_table = &(smu_table->driver_table); 586 587 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 588 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 589 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 590 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 591 592 amdgpu_bo_free_kernel(&driver_table->bo, 593 &driver_table->mc_address, 594 &driver_table->cpu_addr); 595 596 return 0; 597 } 598 599 /** 600 * smu_alloc_memory_pool - allocate memory pool in the system memory 601 * 602 * @smu: amdgpu_device pointer 603 * 604 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 605 * and DramLogSetDramAddr can notify it changed. 606 * 607 * Returns 0 on success, error on failure. 608 */ 609 static int smu_alloc_memory_pool(struct smu_context *smu) 610 { 611 struct amdgpu_device *adev = smu->adev; 612 struct smu_table_context *smu_table = &smu->smu_table; 613 struct smu_table *memory_pool = &smu_table->memory_pool; 614 uint64_t pool_size = smu->pool_size; 615 int ret = 0; 616 617 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 618 return ret; 619 620 memory_pool->size = pool_size; 621 memory_pool->align = PAGE_SIZE; 622 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 623 624 switch (pool_size) { 625 case SMU_MEMORY_POOL_SIZE_256_MB: 626 case SMU_MEMORY_POOL_SIZE_512_MB: 627 case SMU_MEMORY_POOL_SIZE_1_GB: 628 case SMU_MEMORY_POOL_SIZE_2_GB: 629 ret = amdgpu_bo_create_kernel(adev, 630 memory_pool->size, 631 memory_pool->align, 632 memory_pool->domain, 633 &memory_pool->bo, 634 &memory_pool->mc_address, 635 &memory_pool->cpu_addr); 636 if (ret) 637 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 638 break; 639 default: 640 break; 641 } 642 643 return ret; 644 } 645 646 static int smu_free_memory_pool(struct smu_context *smu) 647 { 648 struct smu_table_context *smu_table = &smu->smu_table; 649 struct smu_table *memory_pool = &smu_table->memory_pool; 650 651 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 652 return 0; 653 654 amdgpu_bo_free_kernel(&memory_pool->bo, 655 &memory_pool->mc_address, 656 &memory_pool->cpu_addr); 657 658 memset(memory_pool, 0, sizeof(struct smu_table)); 659 660 return 0; 661 } 662 663 static int smu_alloc_dummy_read_table(struct smu_context *smu) 664 { 665 struct smu_table_context *smu_table = &smu->smu_table; 666 struct smu_table *dummy_read_1_table = 667 &smu_table->dummy_read_1_table; 668 struct amdgpu_device *adev = smu->adev; 669 int ret = 0; 670 671 dummy_read_1_table->size = 0x40000; 672 dummy_read_1_table->align = PAGE_SIZE; 673 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 674 675 ret = amdgpu_bo_create_kernel(adev, 676 dummy_read_1_table->size, 677 dummy_read_1_table->align, 678 dummy_read_1_table->domain, 679 &dummy_read_1_table->bo, 680 &dummy_read_1_table->mc_address, 681 &dummy_read_1_table->cpu_addr); 682 if (ret) 683 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 684 685 return ret; 686 } 687 688 static void smu_free_dummy_read_table(struct smu_context *smu) 689 { 690 struct smu_table_context *smu_table = &smu->smu_table; 691 struct smu_table *dummy_read_1_table = 692 &smu_table->dummy_read_1_table; 693 694 695 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 696 &dummy_read_1_table->mc_address, 697 &dummy_read_1_table->cpu_addr); 698 699 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 700 } 701 702 static int smu_smc_table_sw_init(struct smu_context *smu) 703 { 704 int ret; 705 706 /** 707 * Create smu_table structure, and init smc tables such as 708 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 709 */ 710 ret = smu_init_smc_tables(smu); 711 if (ret) { 712 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 713 return ret; 714 } 715 716 /** 717 * Create smu_power_context structure, and allocate smu_dpm_context and 718 * context size to fill the smu_power_context data. 719 */ 720 ret = smu_init_power(smu); 721 if (ret) { 722 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 723 return ret; 724 } 725 726 /* 727 * allocate vram bos to store smc table contents. 728 */ 729 ret = smu_init_fb_allocations(smu); 730 if (ret) 731 return ret; 732 733 ret = smu_alloc_memory_pool(smu); 734 if (ret) 735 return ret; 736 737 ret = smu_alloc_dummy_read_table(smu); 738 if (ret) 739 return ret; 740 741 ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c); 742 if (ret) 743 return ret; 744 745 return 0; 746 } 747 748 static int smu_smc_table_sw_fini(struct smu_context *smu) 749 { 750 int ret; 751 752 smu_i2c_fini(smu, &smu->adev->pm.smu_i2c); 753 754 smu_free_dummy_read_table(smu); 755 756 ret = smu_free_memory_pool(smu); 757 if (ret) 758 return ret; 759 760 ret = smu_fini_fb_allocations(smu); 761 if (ret) 762 return ret; 763 764 ret = smu_fini_power(smu); 765 if (ret) { 766 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 767 return ret; 768 } 769 770 ret = smu_fini_smc_tables(smu); 771 if (ret) { 772 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 773 return ret; 774 } 775 776 return 0; 777 } 778 779 static void smu_throttling_logging_work_fn(struct work_struct *work) 780 { 781 struct smu_context *smu = container_of(work, struct smu_context, 782 throttling_logging_work); 783 784 smu_log_thermal_throttling(smu); 785 } 786 787 static void smu_interrupt_work_fn(struct work_struct *work) 788 { 789 struct smu_context *smu = container_of(work, struct smu_context, 790 interrupt_work); 791 792 mutex_lock(&smu->mutex); 793 794 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 795 smu->ppt_funcs->interrupt_work(smu); 796 797 mutex_unlock(&smu->mutex); 798 } 799 800 static int smu_sw_init(void *handle) 801 { 802 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 803 struct smu_context *smu = &adev->smu; 804 int ret; 805 806 smu->pool_size = adev->pm.smu_prv_buffer_size; 807 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 808 mutex_init(&smu->smu_feature.mutex); 809 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 810 bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX); 811 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 812 813 mutex_init(&smu->sensor_lock); 814 mutex_init(&smu->metrics_lock); 815 mutex_init(&smu->message_lock); 816 817 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 818 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 819 atomic64_set(&smu->throttle_int_counter, 0); 820 smu->watermarks_bitmap = 0; 821 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 822 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 823 824 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 825 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 826 mutex_init(&smu->smu_power.power_gate.vcn_gate_lock); 827 mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock); 828 829 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 830 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 831 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 832 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 833 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 834 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 835 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 836 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 837 838 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 839 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 840 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 841 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 842 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 843 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 844 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 845 smu->display_config = &adev->pm.pm_display_cfg; 846 847 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 848 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 849 850 ret = smu_init_microcode(smu); 851 if (ret) { 852 dev_err(adev->dev, "Failed to load smu firmware!\n"); 853 return ret; 854 } 855 856 ret = smu_smc_table_sw_init(smu); 857 if (ret) { 858 dev_err(adev->dev, "Failed to sw init smc table!\n"); 859 return ret; 860 } 861 862 ret = smu_register_irq_handler(smu); 863 if (ret) { 864 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 865 return ret; 866 } 867 868 return 0; 869 } 870 871 static int smu_sw_fini(void *handle) 872 { 873 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 874 struct smu_context *smu = &adev->smu; 875 int ret; 876 877 ret = smu_smc_table_sw_fini(smu); 878 if (ret) { 879 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 880 return ret; 881 } 882 883 smu_fini_microcode(smu); 884 885 return 0; 886 } 887 888 static int smu_get_thermal_temperature_range(struct smu_context *smu) 889 { 890 struct amdgpu_device *adev = smu->adev; 891 struct smu_temperature_range *range = 892 &smu->thermal_range; 893 int ret = 0; 894 895 if (!smu->ppt_funcs->get_thermal_temperature_range) 896 return 0; 897 898 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 899 if (ret) 900 return ret; 901 902 adev->pm.dpm.thermal.min_temp = range->min; 903 adev->pm.dpm.thermal.max_temp = range->max; 904 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 905 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 906 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 907 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 908 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 909 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 910 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 911 912 return ret; 913 } 914 915 static int smu_smc_hw_setup(struct smu_context *smu) 916 { 917 struct amdgpu_device *adev = smu->adev; 918 uint32_t pcie_gen = 0, pcie_width = 0; 919 int ret = 0; 920 921 if (adev->in_suspend && smu_is_dpm_running(smu)) { 922 dev_info(adev->dev, "dpm has been enabled\n"); 923 /* this is needed specifically */ 924 if ((adev->asic_type >= CHIP_SIENNA_CICHLID) && 925 (adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) 926 ret = smu_system_features_control(smu, true); 927 return ret; 928 } 929 930 ret = smu_init_display_count(smu, 0); 931 if (ret) { 932 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 933 return ret; 934 } 935 936 ret = smu_set_driver_table_location(smu); 937 if (ret) { 938 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 939 return ret; 940 } 941 942 /* 943 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 944 */ 945 ret = smu_set_tool_table_location(smu); 946 if (ret) { 947 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 948 return ret; 949 } 950 951 /* 952 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 953 * pool location. 954 */ 955 ret = smu_notify_memory_pool_location(smu); 956 if (ret) { 957 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 958 return ret; 959 } 960 961 /* smu_dump_pptable(smu); */ 962 /* 963 * Copy pptable bo in the vram to smc with SMU MSGs such as 964 * SetDriverDramAddr and TransferTableDram2Smu. 965 */ 966 ret = smu_write_pptable(smu); 967 if (ret) { 968 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 969 return ret; 970 } 971 972 /* issue Run*Btc msg */ 973 ret = smu_run_btc(smu); 974 if (ret) 975 return ret; 976 977 ret = smu_feature_set_allowed_mask(smu); 978 if (ret) { 979 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 980 return ret; 981 } 982 983 ret = smu_system_features_control(smu, true); 984 if (ret) { 985 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 986 return ret; 987 } 988 989 if (!smu_is_dpm_running(smu)) 990 dev_info(adev->dev, "dpm has been disabled\n"); 991 992 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 993 pcie_gen = 3; 994 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 995 pcie_gen = 2; 996 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 997 pcie_gen = 1; 998 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 999 pcie_gen = 0; 1000 1001 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1002 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1003 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1004 */ 1005 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1006 pcie_width = 6; 1007 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1008 pcie_width = 5; 1009 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1010 pcie_width = 4; 1011 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1012 pcie_width = 3; 1013 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1014 pcie_width = 2; 1015 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1016 pcie_width = 1; 1017 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1018 if (ret) { 1019 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1020 return ret; 1021 } 1022 1023 ret = smu_get_thermal_temperature_range(smu); 1024 if (ret) { 1025 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1026 return ret; 1027 } 1028 1029 ret = smu_enable_thermal_alert(smu); 1030 if (ret) { 1031 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1032 return ret; 1033 } 1034 1035 /* 1036 * Set initialized values (get from vbios) to dpm tables context such as 1037 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1038 * type of clks. 1039 */ 1040 ret = smu_set_default_dpm_table(smu); 1041 if (ret) { 1042 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1043 return ret; 1044 } 1045 1046 ret = smu_notify_display_change(smu); 1047 if (ret) 1048 return ret; 1049 1050 /* 1051 * Set min deep sleep dce fclk with bootup value from vbios via 1052 * SetMinDeepSleepDcefclk MSG. 1053 */ 1054 ret = smu_set_min_dcef_deep_sleep(smu, 1055 smu->smu_table.boot_values.dcefclk / 100); 1056 if (ret) 1057 return ret; 1058 1059 return ret; 1060 } 1061 1062 static int smu_start_smc_engine(struct smu_context *smu) 1063 { 1064 struct amdgpu_device *adev = smu->adev; 1065 int ret = 0; 1066 1067 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1068 if (adev->asic_type < CHIP_NAVI10) { 1069 if (smu->ppt_funcs->load_microcode) { 1070 ret = smu->ppt_funcs->load_microcode(smu); 1071 if (ret) 1072 return ret; 1073 } 1074 } 1075 } 1076 1077 if (smu->ppt_funcs->check_fw_status) { 1078 ret = smu->ppt_funcs->check_fw_status(smu); 1079 if (ret) { 1080 dev_err(adev->dev, "SMC is not ready\n"); 1081 return ret; 1082 } 1083 } 1084 1085 /* 1086 * Send msg GetDriverIfVersion to check if the return value is equal 1087 * with DRIVER_IF_VERSION of smc header. 1088 */ 1089 ret = smu_check_fw_version(smu); 1090 if (ret) 1091 return ret; 1092 1093 return ret; 1094 } 1095 1096 static int smu_hw_init(void *handle) 1097 { 1098 int ret; 1099 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1100 struct smu_context *smu = &adev->smu; 1101 1102 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1103 smu->pm_enabled = false; 1104 return 0; 1105 } 1106 1107 ret = smu_start_smc_engine(smu); 1108 if (ret) { 1109 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1110 return ret; 1111 } 1112 1113 if (smu->is_apu) { 1114 smu_powergate_sdma(&adev->smu, false); 1115 smu_dpm_set_vcn_enable(smu, true); 1116 smu_dpm_set_jpeg_enable(smu, true); 1117 smu_set_gfx_cgpg(&adev->smu, true); 1118 } 1119 1120 if (!smu->pm_enabled) 1121 return 0; 1122 1123 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1124 ret = smu_get_vbios_bootup_values(smu); 1125 if (ret) { 1126 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1127 return ret; 1128 } 1129 1130 ret = smu_setup_pptable(smu); 1131 if (ret) { 1132 dev_err(adev->dev, "Failed to setup pptable!\n"); 1133 return ret; 1134 } 1135 1136 ret = smu_get_driver_allowed_feature_mask(smu); 1137 if (ret) 1138 return ret; 1139 1140 ret = smu_smc_hw_setup(smu); 1141 if (ret) { 1142 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1143 return ret; 1144 } 1145 1146 /* 1147 * Move maximum sustainable clock retrieving here considering 1148 * 1. It is not needed on resume(from S3). 1149 * 2. DAL settings come between .hw_init and .late_init of SMU. 1150 * And DAL needs to know the maximum sustainable clocks. Thus 1151 * it cannot be put in .late_init(). 1152 */ 1153 ret = smu_init_max_sustainable_clocks(smu); 1154 if (ret) { 1155 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1156 return ret; 1157 } 1158 1159 adev->pm.dpm_enabled = true; 1160 1161 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1162 1163 return 0; 1164 } 1165 1166 static int smu_disable_dpms(struct smu_context *smu) 1167 { 1168 struct amdgpu_device *adev = smu->adev; 1169 int ret = 0; 1170 bool use_baco = !smu->is_apu && 1171 ((amdgpu_in_reset(adev) && 1172 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1173 ((adev->in_runpm || adev->in_hibernate) && amdgpu_asic_supports_baco(adev))); 1174 1175 /* 1176 * For custom pptable uploading, skip the DPM features 1177 * disable process on Navi1x ASICs. 1178 * - As the gfx related features are under control of 1179 * RLC on those ASICs. RLC reinitialization will be 1180 * needed to reenable them. That will cost much more 1181 * efforts. 1182 * 1183 * - SMU firmware can handle the DPM reenablement 1184 * properly. 1185 */ 1186 if (smu->uploading_custom_pp_table && 1187 (adev->asic_type >= CHIP_NAVI10) && 1188 (adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) 1189 return 0; 1190 1191 /* 1192 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1193 * on BACO in. Driver involvement is unnecessary. 1194 */ 1195 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 1196 use_baco) 1197 return 0; 1198 1199 /* 1200 * For gpu reset, runpm and hibernation through BACO, 1201 * BACO feature has to be kept enabled. 1202 */ 1203 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1204 ret = smu_disable_all_features_with_exception(smu, 1205 SMU_FEATURE_BACO_BIT); 1206 if (ret) 1207 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1208 } else { 1209 ret = smu_system_features_control(smu, false); 1210 if (ret) 1211 dev_err(adev->dev, "Failed to disable smu features.\n"); 1212 } 1213 1214 if (adev->asic_type >= CHIP_NAVI10 && 1215 adev->gfx.rlc.funcs->stop) 1216 adev->gfx.rlc.funcs->stop(adev); 1217 1218 return ret; 1219 } 1220 1221 static int smu_smc_hw_cleanup(struct smu_context *smu) 1222 { 1223 struct amdgpu_device *adev = smu->adev; 1224 int ret = 0; 1225 1226 cancel_work_sync(&smu->throttling_logging_work); 1227 cancel_work_sync(&smu->interrupt_work); 1228 1229 ret = smu_disable_thermal_alert(smu); 1230 if (ret) { 1231 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1232 return ret; 1233 } 1234 1235 ret = smu_disable_dpms(smu); 1236 if (ret) { 1237 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1238 return ret; 1239 } 1240 1241 return 0; 1242 } 1243 1244 static int smu_hw_fini(void *handle) 1245 { 1246 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1247 struct smu_context *smu = &adev->smu; 1248 1249 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1250 return 0; 1251 1252 if (smu->is_apu) { 1253 smu_powergate_sdma(&adev->smu, true); 1254 smu_dpm_set_vcn_enable(smu, false); 1255 smu_dpm_set_jpeg_enable(smu, false); 1256 } 1257 1258 if (!smu->pm_enabled) 1259 return 0; 1260 1261 adev->pm.dpm_enabled = false; 1262 1263 return smu_smc_hw_cleanup(smu); 1264 } 1265 1266 int smu_reset(struct smu_context *smu) 1267 { 1268 struct amdgpu_device *adev = smu->adev; 1269 int ret; 1270 1271 amdgpu_gfx_off_ctrl(smu->adev, false); 1272 1273 ret = smu_hw_fini(adev); 1274 if (ret) 1275 return ret; 1276 1277 ret = smu_hw_init(adev); 1278 if (ret) 1279 return ret; 1280 1281 ret = smu_late_init(adev); 1282 if (ret) 1283 return ret; 1284 1285 amdgpu_gfx_off_ctrl(smu->adev, true); 1286 1287 return 0; 1288 } 1289 1290 static int smu_suspend(void *handle) 1291 { 1292 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1293 struct smu_context *smu = &adev->smu; 1294 int ret; 1295 1296 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1297 return 0; 1298 1299 if (!smu->pm_enabled) 1300 return 0; 1301 1302 adev->pm.dpm_enabled = false; 1303 1304 ret = smu_smc_hw_cleanup(smu); 1305 if (ret) 1306 return ret; 1307 1308 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1309 1310 if (smu->is_apu) 1311 smu_set_gfx_cgpg(&adev->smu, false); 1312 1313 return 0; 1314 } 1315 1316 static int smu_resume(void *handle) 1317 { 1318 int ret; 1319 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1320 struct smu_context *smu = &adev->smu; 1321 1322 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1323 return 0; 1324 1325 if (!smu->pm_enabled) 1326 return 0; 1327 1328 dev_info(adev->dev, "SMU is resuming...\n"); 1329 1330 ret = smu_start_smc_engine(smu); 1331 if (ret) { 1332 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1333 return ret; 1334 } 1335 1336 ret = smu_smc_hw_setup(smu); 1337 if (ret) { 1338 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1339 return ret; 1340 } 1341 1342 if (smu->is_apu) 1343 smu_set_gfx_cgpg(&adev->smu, true); 1344 1345 smu->disable_uclk_switch = 0; 1346 1347 adev->pm.dpm_enabled = true; 1348 1349 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1350 1351 return 0; 1352 } 1353 1354 int smu_display_configuration_change(struct smu_context *smu, 1355 const struct amd_pp_display_configuration *display_config) 1356 { 1357 int index = 0; 1358 int num_of_active_display = 0; 1359 1360 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1361 return -EOPNOTSUPP; 1362 1363 if (!display_config) 1364 return -EINVAL; 1365 1366 mutex_lock(&smu->mutex); 1367 1368 smu_set_min_dcef_deep_sleep(smu, 1369 display_config->min_dcef_deep_sleep_set_clk / 100); 1370 1371 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1372 if (display_config->displays[index].controller_id != 0) 1373 num_of_active_display++; 1374 } 1375 1376 mutex_unlock(&smu->mutex); 1377 1378 return 0; 1379 } 1380 1381 static int smu_set_clockgating_state(void *handle, 1382 enum amd_clockgating_state state) 1383 { 1384 return 0; 1385 } 1386 1387 static int smu_set_powergating_state(void *handle, 1388 enum amd_powergating_state state) 1389 { 1390 return 0; 1391 } 1392 1393 static int smu_enable_umd_pstate(void *handle, 1394 enum amd_dpm_forced_level *level) 1395 { 1396 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1397 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1398 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1399 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1400 1401 struct smu_context *smu = (struct smu_context*)(handle); 1402 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1403 1404 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1405 return -EINVAL; 1406 1407 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1408 /* enter umd pstate, save current level, disable gfx cg*/ 1409 if (*level & profile_mode_mask) { 1410 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1411 smu_dpm_ctx->enable_umd_pstate = true; 1412 smu_gpo_control(smu, false); 1413 amdgpu_device_ip_set_powergating_state(smu->adev, 1414 AMD_IP_BLOCK_TYPE_GFX, 1415 AMD_PG_STATE_UNGATE); 1416 amdgpu_device_ip_set_clockgating_state(smu->adev, 1417 AMD_IP_BLOCK_TYPE_GFX, 1418 AMD_CG_STATE_UNGATE); 1419 smu_gfx_ulv_control(smu, false); 1420 smu_deep_sleep_control(smu, false); 1421 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1422 } 1423 } else { 1424 /* exit umd pstate, restore level, enable gfx cg*/ 1425 if (!(*level & profile_mode_mask)) { 1426 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1427 *level = smu_dpm_ctx->saved_dpm_level; 1428 smu_dpm_ctx->enable_umd_pstate = false; 1429 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1430 smu_deep_sleep_control(smu, true); 1431 smu_gfx_ulv_control(smu, true); 1432 amdgpu_device_ip_set_clockgating_state(smu->adev, 1433 AMD_IP_BLOCK_TYPE_GFX, 1434 AMD_CG_STATE_GATE); 1435 amdgpu_device_ip_set_powergating_state(smu->adev, 1436 AMD_IP_BLOCK_TYPE_GFX, 1437 AMD_PG_STATE_GATE); 1438 smu_gpo_control(smu, true); 1439 } 1440 } 1441 1442 return 0; 1443 } 1444 1445 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1446 enum amd_dpm_forced_level level, 1447 bool skip_display_settings) 1448 { 1449 int ret = 0; 1450 int index = 0; 1451 long workload; 1452 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1453 1454 if (!skip_display_settings) { 1455 ret = smu_display_config_changed(smu); 1456 if (ret) { 1457 dev_err(smu->adev->dev, "Failed to change display config!"); 1458 return ret; 1459 } 1460 } 1461 1462 ret = smu_apply_clocks_adjust_rules(smu); 1463 if (ret) { 1464 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1465 return ret; 1466 } 1467 1468 if (!skip_display_settings) { 1469 ret = smu_notify_smc_display_config(smu); 1470 if (ret) { 1471 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1472 return ret; 1473 } 1474 } 1475 1476 if (smu_dpm_ctx->dpm_level != level) { 1477 ret = smu_asic_set_performance_level(smu, level); 1478 if (ret) { 1479 dev_err(smu->adev->dev, "Failed to set performance level!"); 1480 return ret; 1481 } 1482 1483 /* update the saved copy */ 1484 smu_dpm_ctx->dpm_level = level; 1485 } 1486 1487 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1488 index = fls(smu->workload_mask); 1489 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1490 workload = smu->workload_setting[index]; 1491 1492 if (smu->power_profile_mode != workload) 1493 smu_set_power_profile_mode(smu, &workload, 0, false); 1494 } 1495 1496 return ret; 1497 } 1498 1499 int smu_handle_task(struct smu_context *smu, 1500 enum amd_dpm_forced_level level, 1501 enum amd_pp_task task_id, 1502 bool lock_needed) 1503 { 1504 int ret = 0; 1505 1506 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1507 return -EOPNOTSUPP; 1508 1509 if (lock_needed) 1510 mutex_lock(&smu->mutex); 1511 1512 switch (task_id) { 1513 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1514 ret = smu_pre_display_config_changed(smu); 1515 if (ret) 1516 goto out; 1517 ret = smu_adjust_power_state_dynamic(smu, level, false); 1518 break; 1519 case AMD_PP_TASK_COMPLETE_INIT: 1520 case AMD_PP_TASK_READJUST_POWER_STATE: 1521 ret = smu_adjust_power_state_dynamic(smu, level, true); 1522 break; 1523 default: 1524 break; 1525 } 1526 1527 out: 1528 if (lock_needed) 1529 mutex_unlock(&smu->mutex); 1530 1531 return ret; 1532 } 1533 1534 int smu_switch_power_profile(struct smu_context *smu, 1535 enum PP_SMC_POWER_PROFILE type, 1536 bool en) 1537 { 1538 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1539 long workload; 1540 uint32_t index; 1541 1542 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1543 return -EOPNOTSUPP; 1544 1545 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1546 return -EINVAL; 1547 1548 mutex_lock(&smu->mutex); 1549 1550 if (!en) { 1551 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1552 index = fls(smu->workload_mask); 1553 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1554 workload = smu->workload_setting[index]; 1555 } else { 1556 smu->workload_mask |= (1 << smu->workload_prority[type]); 1557 index = fls(smu->workload_mask); 1558 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1559 workload = smu->workload_setting[index]; 1560 } 1561 1562 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1563 smu_set_power_profile_mode(smu, &workload, 0, false); 1564 1565 mutex_unlock(&smu->mutex); 1566 1567 return 0; 1568 } 1569 1570 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu) 1571 { 1572 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1573 enum amd_dpm_forced_level level; 1574 1575 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1576 return -EOPNOTSUPP; 1577 1578 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1579 return -EINVAL; 1580 1581 mutex_lock(&(smu->mutex)); 1582 level = smu_dpm_ctx->dpm_level; 1583 mutex_unlock(&(smu->mutex)); 1584 1585 return level; 1586 } 1587 1588 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level) 1589 { 1590 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1591 int ret = 0; 1592 1593 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1594 return -EOPNOTSUPP; 1595 1596 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1597 return -EINVAL; 1598 1599 mutex_lock(&smu->mutex); 1600 1601 ret = smu_enable_umd_pstate(smu, &level); 1602 if (ret) { 1603 mutex_unlock(&smu->mutex); 1604 return ret; 1605 } 1606 1607 ret = smu_handle_task(smu, level, 1608 AMD_PP_TASK_READJUST_POWER_STATE, 1609 false); 1610 1611 mutex_unlock(&smu->mutex); 1612 1613 return ret; 1614 } 1615 1616 int smu_set_display_count(struct smu_context *smu, uint32_t count) 1617 { 1618 int ret = 0; 1619 1620 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1621 return -EOPNOTSUPP; 1622 1623 mutex_lock(&smu->mutex); 1624 ret = smu_init_display_count(smu, count); 1625 mutex_unlock(&smu->mutex); 1626 1627 return ret; 1628 } 1629 1630 int smu_force_clk_levels(struct smu_context *smu, 1631 enum smu_clk_type clk_type, 1632 uint32_t mask) 1633 { 1634 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1635 int ret = 0; 1636 1637 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1638 return -EOPNOTSUPP; 1639 1640 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1641 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1642 return -EINVAL; 1643 } 1644 1645 mutex_lock(&smu->mutex); 1646 1647 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) 1648 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1649 1650 mutex_unlock(&smu->mutex); 1651 1652 return ret; 1653 } 1654 1655 /* 1656 * On system suspending or resetting, the dpm_enabled 1657 * flag will be cleared. So that those SMU services which 1658 * are not supported will be gated. 1659 * However, the mp1 state setting should still be granted 1660 * even if the dpm_enabled cleared. 1661 */ 1662 int smu_set_mp1_state(struct smu_context *smu, 1663 enum pp_mp1_state mp1_state) 1664 { 1665 uint16_t msg; 1666 int ret; 1667 1668 if (!smu->pm_enabled) 1669 return -EOPNOTSUPP; 1670 1671 mutex_lock(&smu->mutex); 1672 1673 switch (mp1_state) { 1674 case PP_MP1_STATE_SHUTDOWN: 1675 msg = SMU_MSG_PrepareMp1ForShutdown; 1676 break; 1677 case PP_MP1_STATE_UNLOAD: 1678 msg = SMU_MSG_PrepareMp1ForUnload; 1679 break; 1680 case PP_MP1_STATE_RESET: 1681 msg = SMU_MSG_PrepareMp1ForReset; 1682 break; 1683 case PP_MP1_STATE_NONE: 1684 default: 1685 mutex_unlock(&smu->mutex); 1686 return 0; 1687 } 1688 1689 ret = smu_send_smc_msg(smu, msg, NULL); 1690 /* some asics may not support those messages */ 1691 if (ret == -EINVAL) 1692 ret = 0; 1693 if (ret) 1694 dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n"); 1695 1696 mutex_unlock(&smu->mutex); 1697 1698 return ret; 1699 } 1700 1701 int smu_set_df_cstate(struct smu_context *smu, 1702 enum pp_df_cstate state) 1703 { 1704 int ret = 0; 1705 1706 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1707 return -EOPNOTSUPP; 1708 1709 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 1710 return 0; 1711 1712 mutex_lock(&smu->mutex); 1713 1714 ret = smu->ppt_funcs->set_df_cstate(smu, state); 1715 if (ret) 1716 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 1717 1718 mutex_unlock(&smu->mutex); 1719 1720 return ret; 1721 } 1722 1723 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 1724 { 1725 int ret = 0; 1726 1727 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1728 return -EOPNOTSUPP; 1729 1730 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 1731 return 0; 1732 1733 mutex_lock(&smu->mutex); 1734 1735 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 1736 if (ret) 1737 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 1738 1739 mutex_unlock(&smu->mutex); 1740 1741 return ret; 1742 } 1743 1744 int smu_write_watermarks_table(struct smu_context *smu) 1745 { 1746 int ret = 0; 1747 1748 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1749 return -EOPNOTSUPP; 1750 1751 mutex_lock(&smu->mutex); 1752 1753 ret = smu_set_watermarks_table(smu, NULL); 1754 1755 mutex_unlock(&smu->mutex); 1756 1757 return ret; 1758 } 1759 1760 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu, 1761 struct pp_smu_wm_range_sets *clock_ranges) 1762 { 1763 int ret = 0; 1764 1765 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1766 return -EOPNOTSUPP; 1767 1768 if (smu->disable_watermark) 1769 return 0; 1770 1771 mutex_lock(&smu->mutex); 1772 1773 ret = smu_set_watermarks_table(smu, clock_ranges); 1774 1775 mutex_unlock(&smu->mutex); 1776 1777 return ret; 1778 } 1779 1780 int smu_set_ac_dc(struct smu_context *smu) 1781 { 1782 int ret = 0; 1783 1784 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1785 return -EOPNOTSUPP; 1786 1787 /* controlled by firmware */ 1788 if (smu->dc_controlled_by_gpio) 1789 return 0; 1790 1791 mutex_lock(&smu->mutex); 1792 ret = smu_set_power_source(smu, 1793 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 1794 SMU_POWER_SOURCE_DC); 1795 if (ret) 1796 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 1797 smu->adev->pm.ac_power ? "AC" : "DC"); 1798 mutex_unlock(&smu->mutex); 1799 1800 return ret; 1801 } 1802 1803 const struct amd_ip_funcs smu_ip_funcs = { 1804 .name = "smu", 1805 .early_init = smu_early_init, 1806 .late_init = smu_late_init, 1807 .sw_init = smu_sw_init, 1808 .sw_fini = smu_sw_fini, 1809 .hw_init = smu_hw_init, 1810 .hw_fini = smu_hw_fini, 1811 .suspend = smu_suspend, 1812 .resume = smu_resume, 1813 .is_idle = NULL, 1814 .check_soft_reset = NULL, 1815 .wait_for_idle = NULL, 1816 .soft_reset = NULL, 1817 .set_clockgating_state = smu_set_clockgating_state, 1818 .set_powergating_state = smu_set_powergating_state, 1819 .enable_umd_pstate = smu_enable_umd_pstate, 1820 }; 1821 1822 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 1823 { 1824 .type = AMD_IP_BLOCK_TYPE_SMC, 1825 .major = 11, 1826 .minor = 0, 1827 .rev = 0, 1828 .funcs = &smu_ip_funcs, 1829 }; 1830 1831 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 1832 { 1833 .type = AMD_IP_BLOCK_TYPE_SMC, 1834 .major = 12, 1835 .minor = 0, 1836 .rev = 0, 1837 .funcs = &smu_ip_funcs, 1838 }; 1839 1840 int smu_load_microcode(struct smu_context *smu) 1841 { 1842 int ret = 0; 1843 1844 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1845 return -EOPNOTSUPP; 1846 1847 mutex_lock(&smu->mutex); 1848 1849 if (smu->ppt_funcs->load_microcode) 1850 ret = smu->ppt_funcs->load_microcode(smu); 1851 1852 mutex_unlock(&smu->mutex); 1853 1854 return ret; 1855 } 1856 1857 int smu_check_fw_status(struct smu_context *smu) 1858 { 1859 int ret = 0; 1860 1861 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1862 return -EOPNOTSUPP; 1863 1864 mutex_lock(&smu->mutex); 1865 1866 if (smu->ppt_funcs->check_fw_status) 1867 ret = smu->ppt_funcs->check_fw_status(smu); 1868 1869 mutex_unlock(&smu->mutex); 1870 1871 return ret; 1872 } 1873 1874 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 1875 { 1876 int ret = 0; 1877 1878 mutex_lock(&smu->mutex); 1879 1880 if (smu->ppt_funcs->set_gfx_cgpg) 1881 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 1882 1883 mutex_unlock(&smu->mutex); 1884 1885 return ret; 1886 } 1887 1888 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed) 1889 { 1890 int ret = 0; 1891 1892 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1893 return -EOPNOTSUPP; 1894 1895 mutex_lock(&smu->mutex); 1896 1897 if (smu->ppt_funcs->set_fan_speed_rpm) 1898 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 1899 1900 mutex_unlock(&smu->mutex); 1901 1902 return ret; 1903 } 1904 1905 int smu_get_power_limit(struct smu_context *smu, 1906 uint32_t *limit, 1907 bool max_setting) 1908 { 1909 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1910 return -EOPNOTSUPP; 1911 1912 mutex_lock(&smu->mutex); 1913 1914 *limit = (max_setting ? smu->max_power_limit : smu->current_power_limit); 1915 1916 mutex_unlock(&smu->mutex); 1917 1918 return 0; 1919 } 1920 1921 int smu_set_power_limit(struct smu_context *smu, uint32_t limit) 1922 { 1923 int ret = 0; 1924 1925 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1926 return -EOPNOTSUPP; 1927 1928 mutex_lock(&smu->mutex); 1929 1930 if (limit > smu->max_power_limit) { 1931 dev_err(smu->adev->dev, 1932 "New power limit (%d) is over the max allowed %d\n", 1933 limit, smu->max_power_limit); 1934 goto out; 1935 } 1936 1937 if (!limit) 1938 limit = smu->current_power_limit; 1939 1940 if (smu->ppt_funcs->set_power_limit) 1941 ret = smu->ppt_funcs->set_power_limit(smu, limit); 1942 1943 out: 1944 mutex_unlock(&smu->mutex); 1945 1946 return ret; 1947 } 1948 1949 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 1950 { 1951 int ret = 0; 1952 1953 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1954 return -EOPNOTSUPP; 1955 1956 mutex_lock(&smu->mutex); 1957 1958 if (smu->ppt_funcs->print_clk_levels) 1959 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 1960 1961 mutex_unlock(&smu->mutex); 1962 1963 return ret; 1964 } 1965 1966 int smu_od_edit_dpm_table(struct smu_context *smu, 1967 enum PP_OD_DPM_TABLE_COMMAND type, 1968 long *input, uint32_t size) 1969 { 1970 int ret = 0; 1971 1972 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1973 return -EOPNOTSUPP; 1974 1975 mutex_lock(&smu->mutex); 1976 1977 if (smu->ppt_funcs->od_edit_dpm_table) { 1978 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 1979 if (!ret && (type == PP_OD_COMMIT_DPM_TABLE)) 1980 ret = smu_handle_task(smu, 1981 smu->smu_dpm.dpm_level, 1982 AMD_PP_TASK_READJUST_POWER_STATE, 1983 false); 1984 } 1985 1986 mutex_unlock(&smu->mutex); 1987 1988 return ret; 1989 } 1990 1991 int smu_read_sensor(struct smu_context *smu, 1992 enum amd_pp_sensors sensor, 1993 void *data, uint32_t *size) 1994 { 1995 struct smu_umd_pstate_table *pstate_table = 1996 &smu->pstate_table; 1997 int ret = 0; 1998 1999 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2000 return -EOPNOTSUPP; 2001 2002 if (!data || !size) 2003 return -EINVAL; 2004 2005 mutex_lock(&smu->mutex); 2006 2007 if (smu->ppt_funcs->read_sensor) 2008 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2009 goto unlock; 2010 2011 switch (sensor) { 2012 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2013 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2014 *size = 4; 2015 break; 2016 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2017 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2018 *size = 4; 2019 break; 2020 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2021 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2); 2022 *size = 8; 2023 break; 2024 case AMDGPU_PP_SENSOR_UVD_POWER: 2025 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2026 *size = 4; 2027 break; 2028 case AMDGPU_PP_SENSOR_VCE_POWER: 2029 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2030 *size = 4; 2031 break; 2032 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2033 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2034 *size = 4; 2035 break; 2036 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2037 *(uint32_t *)data = 0; 2038 *size = 4; 2039 break; 2040 default: 2041 *size = 0; 2042 ret = -EOPNOTSUPP; 2043 break; 2044 } 2045 2046 unlock: 2047 mutex_unlock(&smu->mutex); 2048 2049 return ret; 2050 } 2051 2052 int smu_get_power_profile_mode(struct smu_context *smu, char *buf) 2053 { 2054 int ret = 0; 2055 2056 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2057 return -EOPNOTSUPP; 2058 2059 mutex_lock(&smu->mutex); 2060 2061 if (smu->ppt_funcs->get_power_profile_mode) 2062 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf); 2063 2064 mutex_unlock(&smu->mutex); 2065 2066 return ret; 2067 } 2068 2069 int smu_set_power_profile_mode(struct smu_context *smu, 2070 long *param, 2071 uint32_t param_size, 2072 bool lock_needed) 2073 { 2074 int ret = 0; 2075 2076 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2077 return -EOPNOTSUPP; 2078 2079 if (lock_needed) 2080 mutex_lock(&smu->mutex); 2081 2082 if (smu->ppt_funcs->set_power_profile_mode) 2083 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 2084 2085 if (lock_needed) 2086 mutex_unlock(&smu->mutex); 2087 2088 return ret; 2089 } 2090 2091 2092 int smu_get_fan_control_mode(struct smu_context *smu) 2093 { 2094 int ret = 0; 2095 2096 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2097 return -EOPNOTSUPP; 2098 2099 mutex_lock(&smu->mutex); 2100 2101 if (smu->ppt_funcs->get_fan_control_mode) 2102 ret = smu->ppt_funcs->get_fan_control_mode(smu); 2103 2104 mutex_unlock(&smu->mutex); 2105 2106 return ret; 2107 } 2108 2109 int smu_set_fan_control_mode(struct smu_context *smu, int value) 2110 { 2111 int ret = 0; 2112 2113 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2114 return -EOPNOTSUPP; 2115 2116 mutex_lock(&smu->mutex); 2117 2118 if (smu->ppt_funcs->set_fan_control_mode) 2119 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2120 2121 mutex_unlock(&smu->mutex); 2122 2123 return ret; 2124 } 2125 2126 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed) 2127 { 2128 int ret = 0; 2129 uint32_t percent; 2130 uint32_t current_rpm; 2131 2132 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2133 return -EOPNOTSUPP; 2134 2135 mutex_lock(&smu->mutex); 2136 2137 if (smu->ppt_funcs->get_fan_speed_rpm) { 2138 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, ¤t_rpm); 2139 if (!ret) { 2140 percent = current_rpm * 100 / smu->fan_max_rpm; 2141 *speed = percent > 100 ? 100 : percent; 2142 } 2143 } 2144 2145 mutex_unlock(&smu->mutex); 2146 2147 2148 return ret; 2149 } 2150 2151 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed) 2152 { 2153 int ret = 0; 2154 uint32_t rpm; 2155 2156 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2157 return -EOPNOTSUPP; 2158 2159 mutex_lock(&smu->mutex); 2160 2161 if (smu->ppt_funcs->set_fan_speed_rpm) { 2162 if (speed > 100) 2163 speed = 100; 2164 rpm = speed * smu->fan_max_rpm / 100; 2165 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, rpm); 2166 } 2167 2168 mutex_unlock(&smu->mutex); 2169 2170 return ret; 2171 } 2172 2173 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed) 2174 { 2175 int ret = 0; 2176 2177 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2178 return -EOPNOTSUPP; 2179 2180 mutex_lock(&smu->mutex); 2181 2182 if (smu->ppt_funcs->get_fan_speed_rpm) 2183 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 2184 2185 mutex_unlock(&smu->mutex); 2186 2187 return ret; 2188 } 2189 2190 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk) 2191 { 2192 int ret = 0; 2193 2194 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2195 return -EOPNOTSUPP; 2196 2197 mutex_lock(&smu->mutex); 2198 2199 ret = smu_set_min_dcef_deep_sleep(smu, clk); 2200 2201 mutex_unlock(&smu->mutex); 2202 2203 return ret; 2204 } 2205 2206 int smu_get_clock_by_type_with_latency(struct smu_context *smu, 2207 enum smu_clk_type clk_type, 2208 struct pp_clock_levels_with_latency *clocks) 2209 { 2210 int ret = 0; 2211 2212 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2213 return -EOPNOTSUPP; 2214 2215 mutex_lock(&smu->mutex); 2216 2217 if (smu->ppt_funcs->get_clock_by_type_with_latency) 2218 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2219 2220 mutex_unlock(&smu->mutex); 2221 2222 return ret; 2223 } 2224 2225 int smu_display_clock_voltage_request(struct smu_context *smu, 2226 struct pp_display_clock_request *clock_req) 2227 { 2228 int ret = 0; 2229 2230 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2231 return -EOPNOTSUPP; 2232 2233 mutex_lock(&smu->mutex); 2234 2235 if (smu->ppt_funcs->display_clock_voltage_request) 2236 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2237 2238 mutex_unlock(&smu->mutex); 2239 2240 return ret; 2241 } 2242 2243 2244 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch) 2245 { 2246 int ret = -EINVAL; 2247 2248 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2249 return -EOPNOTSUPP; 2250 2251 mutex_lock(&smu->mutex); 2252 2253 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2254 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2255 2256 mutex_unlock(&smu->mutex); 2257 2258 return ret; 2259 } 2260 2261 int smu_set_xgmi_pstate(struct smu_context *smu, 2262 uint32_t pstate) 2263 { 2264 int ret = 0; 2265 2266 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2267 return -EOPNOTSUPP; 2268 2269 mutex_lock(&smu->mutex); 2270 2271 if (smu->ppt_funcs->set_xgmi_pstate) 2272 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2273 2274 mutex_unlock(&smu->mutex); 2275 2276 if(ret) 2277 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2278 2279 return ret; 2280 } 2281 2282 int smu_set_azalia_d3_pme(struct smu_context *smu) 2283 { 2284 int ret = 0; 2285 2286 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2287 return -EOPNOTSUPP; 2288 2289 mutex_lock(&smu->mutex); 2290 2291 if (smu->ppt_funcs->set_azalia_d3_pme) 2292 ret = smu->ppt_funcs->set_azalia_d3_pme(smu); 2293 2294 mutex_unlock(&smu->mutex); 2295 2296 return ret; 2297 } 2298 2299 /* 2300 * On system suspending or resetting, the dpm_enabled 2301 * flag will be cleared. So that those SMU services which 2302 * are not supported will be gated. 2303 * 2304 * However, the baco/mode1 reset should still be granted 2305 * as they are still supported and necessary. 2306 */ 2307 bool smu_baco_is_support(struct smu_context *smu) 2308 { 2309 bool ret = false; 2310 2311 if (!smu->pm_enabled) 2312 return false; 2313 2314 mutex_lock(&smu->mutex); 2315 2316 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2317 ret = smu->ppt_funcs->baco_is_support(smu); 2318 2319 mutex_unlock(&smu->mutex); 2320 2321 return ret; 2322 } 2323 2324 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state) 2325 { 2326 if (smu->ppt_funcs->baco_get_state) 2327 return -EINVAL; 2328 2329 mutex_lock(&smu->mutex); 2330 *state = smu->ppt_funcs->baco_get_state(smu); 2331 mutex_unlock(&smu->mutex); 2332 2333 return 0; 2334 } 2335 2336 int smu_baco_enter(struct smu_context *smu) 2337 { 2338 int ret = 0; 2339 2340 if (!smu->pm_enabled) 2341 return -EOPNOTSUPP; 2342 2343 mutex_lock(&smu->mutex); 2344 2345 if (smu->ppt_funcs->baco_enter) 2346 ret = smu->ppt_funcs->baco_enter(smu); 2347 2348 mutex_unlock(&smu->mutex); 2349 2350 if (ret) 2351 dev_err(smu->adev->dev, "Failed to enter BACO state!\n"); 2352 2353 return ret; 2354 } 2355 2356 int smu_baco_exit(struct smu_context *smu) 2357 { 2358 int ret = 0; 2359 2360 if (!smu->pm_enabled) 2361 return -EOPNOTSUPP; 2362 2363 mutex_lock(&smu->mutex); 2364 2365 if (smu->ppt_funcs->baco_exit) 2366 ret = smu->ppt_funcs->baco_exit(smu); 2367 2368 mutex_unlock(&smu->mutex); 2369 2370 if (ret) 2371 dev_err(smu->adev->dev, "Failed to exit BACO state!\n"); 2372 2373 return ret; 2374 } 2375 2376 bool smu_mode1_reset_is_support(struct smu_context *smu) 2377 { 2378 bool ret = false; 2379 2380 if (!smu->pm_enabled) 2381 return false; 2382 2383 mutex_lock(&smu->mutex); 2384 2385 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2386 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2387 2388 mutex_unlock(&smu->mutex); 2389 2390 return ret; 2391 } 2392 2393 int smu_mode1_reset(struct smu_context *smu) 2394 { 2395 int ret = 0; 2396 2397 if (!smu->pm_enabled) 2398 return -EOPNOTSUPP; 2399 2400 mutex_lock(&smu->mutex); 2401 2402 if (smu->ppt_funcs->mode1_reset) 2403 ret = smu->ppt_funcs->mode1_reset(smu); 2404 2405 mutex_unlock(&smu->mutex); 2406 2407 return ret; 2408 } 2409 2410 int smu_mode2_reset(struct smu_context *smu) 2411 { 2412 int ret = 0; 2413 2414 if (!smu->pm_enabled) 2415 return -EOPNOTSUPP; 2416 2417 mutex_lock(&smu->mutex); 2418 2419 if (smu->ppt_funcs->mode2_reset) 2420 ret = smu->ppt_funcs->mode2_reset(smu); 2421 2422 mutex_unlock(&smu->mutex); 2423 2424 if (ret) 2425 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2426 2427 return ret; 2428 } 2429 2430 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu, 2431 struct pp_smu_nv_clock_table *max_clocks) 2432 { 2433 int ret = 0; 2434 2435 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2436 return -EOPNOTSUPP; 2437 2438 mutex_lock(&smu->mutex); 2439 2440 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2441 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2442 2443 mutex_unlock(&smu->mutex); 2444 2445 return ret; 2446 } 2447 2448 int smu_get_uclk_dpm_states(struct smu_context *smu, 2449 unsigned int *clock_values_in_khz, 2450 unsigned int *num_states) 2451 { 2452 int ret = 0; 2453 2454 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2455 return -EOPNOTSUPP; 2456 2457 mutex_lock(&smu->mutex); 2458 2459 if (smu->ppt_funcs->get_uclk_dpm_states) 2460 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2461 2462 mutex_unlock(&smu->mutex); 2463 2464 return ret; 2465 } 2466 2467 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu) 2468 { 2469 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2470 2471 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2472 return -EOPNOTSUPP; 2473 2474 mutex_lock(&smu->mutex); 2475 2476 if (smu->ppt_funcs->get_current_power_state) 2477 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2478 2479 mutex_unlock(&smu->mutex); 2480 2481 return pm_state; 2482 } 2483 2484 int smu_get_dpm_clock_table(struct smu_context *smu, 2485 struct dpm_clocks *clock_table) 2486 { 2487 int ret = 0; 2488 2489 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2490 return -EOPNOTSUPP; 2491 2492 mutex_lock(&smu->mutex); 2493 2494 if (smu->ppt_funcs->get_dpm_clock_table) 2495 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 2496 2497 mutex_unlock(&smu->mutex); 2498 2499 return ret; 2500 } 2501 2502 ssize_t smu_sys_get_gpu_metrics(struct smu_context *smu, 2503 void **table) 2504 { 2505 ssize_t size; 2506 2507 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2508 return -EOPNOTSUPP; 2509 2510 if (!smu->ppt_funcs->get_gpu_metrics) 2511 return -EOPNOTSUPP; 2512 2513 mutex_lock(&smu->mutex); 2514 2515 size = smu->ppt_funcs->get_gpu_metrics(smu, table); 2516 2517 mutex_unlock(&smu->mutex); 2518 2519 return size; 2520 } 2521 2522 int smu_enable_mgpu_fan_boost(struct smu_context *smu) 2523 { 2524 int ret = 0; 2525 2526 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2527 return -EOPNOTSUPP; 2528 2529 mutex_lock(&smu->mutex); 2530 2531 if (smu->ppt_funcs->enable_mgpu_fan_boost) 2532 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 2533 2534 mutex_unlock(&smu->mutex); 2535 2536 return ret; 2537 } 2538 2539 int smu_gfx_state_change_set(struct smu_context *smu, uint32_t state) 2540 { 2541 int ret = 0; 2542 2543 mutex_lock(&smu->mutex); 2544 if (smu->ppt_funcs->gfx_state_change_set) 2545 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 2546 mutex_unlock(&smu->mutex); 2547 2548 return ret; 2549 } 2550