1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "aldebaran_ppt.h" 38 #include "yellow_carp_ppt.h" 39 #include "cyan_skillfish_ppt.h" 40 #include "amd_pcie.h" 41 42 /* 43 * DO NOT use these for err/warn/info/debug messages. 44 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 45 * They are more MGPU friendly. 46 */ 47 #undef pr_err 48 #undef pr_warn 49 #undef pr_info 50 #undef pr_debug 51 52 static const struct amd_pm_funcs swsmu_pm_funcs; 53 static int smu_force_smuclk_levels(struct smu_context *smu, 54 enum smu_clk_type clk_type, 55 uint32_t mask); 56 static int smu_handle_task(struct smu_context *smu, 57 enum amd_dpm_forced_level level, 58 enum amd_pp_task task_id, 59 bool lock_needed); 60 static int smu_reset(struct smu_context *smu); 61 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 62 static int smu_set_fan_control_mode(struct smu_context *smu, int value); 63 static int smu_set_power_limit(void *handle, uint32_t limit); 64 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 65 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 66 67 static int smu_sys_get_pp_feature_mask(void *handle, 68 char *buf) 69 { 70 struct smu_context *smu = handle; 71 int size = 0; 72 73 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 74 return -EOPNOTSUPP; 75 76 mutex_lock(&smu->mutex); 77 78 size = smu_get_pp_feature_mask(smu, buf); 79 80 mutex_unlock(&smu->mutex); 81 82 return size; 83 } 84 85 static int smu_sys_set_pp_feature_mask(void *handle, 86 uint64_t new_mask) 87 { 88 struct smu_context *smu = handle; 89 int ret = 0; 90 91 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 92 return -EOPNOTSUPP; 93 94 mutex_lock(&smu->mutex); 95 96 ret = smu_set_pp_feature_mask(smu, new_mask); 97 98 mutex_unlock(&smu->mutex); 99 100 return ret; 101 } 102 103 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) 104 { 105 int ret = 0; 106 struct smu_context *smu = &adev->smu; 107 108 if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status) 109 *value = smu_get_gfx_off_status(smu); 110 else 111 ret = -EINVAL; 112 113 return ret; 114 } 115 116 int smu_set_soft_freq_range(struct smu_context *smu, 117 enum smu_clk_type clk_type, 118 uint32_t min, 119 uint32_t max) 120 { 121 int ret = 0; 122 123 mutex_lock(&smu->mutex); 124 125 if (smu->ppt_funcs->set_soft_freq_limited_range) 126 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 127 clk_type, 128 min, 129 max); 130 131 mutex_unlock(&smu->mutex); 132 133 return ret; 134 } 135 136 int smu_get_dpm_freq_range(struct smu_context *smu, 137 enum smu_clk_type clk_type, 138 uint32_t *min, 139 uint32_t *max) 140 { 141 int ret = 0; 142 143 if (!min && !max) 144 return -EINVAL; 145 146 mutex_lock(&smu->mutex); 147 148 if (smu->ppt_funcs->get_dpm_ultimate_freq) 149 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 150 clk_type, 151 min, 152 max); 153 154 mutex_unlock(&smu->mutex); 155 156 return ret; 157 } 158 159 static u32 smu_get_mclk(void *handle, bool low) 160 { 161 struct smu_context *smu = handle; 162 uint32_t clk_freq; 163 int ret = 0; 164 165 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 166 low ? &clk_freq : NULL, 167 !low ? &clk_freq : NULL); 168 if (ret) 169 return 0; 170 return clk_freq * 100; 171 } 172 173 static u32 smu_get_sclk(void *handle, bool low) 174 { 175 struct smu_context *smu = handle; 176 uint32_t clk_freq; 177 int ret = 0; 178 179 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 180 low ? &clk_freq : NULL, 181 !low ? &clk_freq : NULL); 182 if (ret) 183 return 0; 184 return clk_freq * 100; 185 } 186 187 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu, 188 bool enable) 189 { 190 struct smu_power_context *smu_power = &smu->smu_power; 191 struct smu_power_gate *power_gate = &smu_power->power_gate; 192 int ret = 0; 193 194 if (!smu->ppt_funcs->dpm_set_vcn_enable) 195 return 0; 196 197 if (atomic_read(&power_gate->vcn_gated) ^ enable) 198 return 0; 199 200 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 201 if (!ret) 202 atomic_set(&power_gate->vcn_gated, !enable); 203 204 return ret; 205 } 206 207 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 208 bool enable) 209 { 210 struct smu_power_context *smu_power = &smu->smu_power; 211 struct smu_power_gate *power_gate = &smu_power->power_gate; 212 int ret = 0; 213 214 mutex_lock(&power_gate->vcn_gate_lock); 215 216 ret = smu_dpm_set_vcn_enable_locked(smu, enable); 217 218 mutex_unlock(&power_gate->vcn_gate_lock); 219 220 return ret; 221 } 222 223 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu, 224 bool enable) 225 { 226 struct smu_power_context *smu_power = &smu->smu_power; 227 struct smu_power_gate *power_gate = &smu_power->power_gate; 228 int ret = 0; 229 230 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 231 return 0; 232 233 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 234 return 0; 235 236 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 237 if (!ret) 238 atomic_set(&power_gate->jpeg_gated, !enable); 239 240 return ret; 241 } 242 243 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 244 bool enable) 245 { 246 struct smu_power_context *smu_power = &smu->smu_power; 247 struct smu_power_gate *power_gate = &smu_power->power_gate; 248 int ret = 0; 249 250 mutex_lock(&power_gate->jpeg_gate_lock); 251 252 ret = smu_dpm_set_jpeg_enable_locked(smu, enable); 253 254 mutex_unlock(&power_gate->jpeg_gate_lock); 255 256 return ret; 257 } 258 259 /** 260 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 261 * 262 * @handle: smu_context pointer 263 * @block_type: the IP block to power gate/ungate 264 * @gate: to power gate if true, ungate otherwise 265 * 266 * This API uses no smu->mutex lock protection due to: 267 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 268 * This is guarded to be race condition free by the caller. 269 * 2. Or get called on user setting request of power_dpm_force_performance_level. 270 * Under this case, the smu->mutex lock protection is already enforced on 271 * the parent API smu_force_performance_level of the call path. 272 */ 273 static int smu_dpm_set_power_gate(void *handle, 274 uint32_t block_type, 275 bool gate) 276 { 277 struct smu_context *smu = handle; 278 int ret = 0; 279 280 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 281 dev_WARN(smu->adev->dev, 282 "SMU uninitialized but power %s requested for %u!\n", 283 gate ? "gate" : "ungate", block_type); 284 return -EOPNOTSUPP; 285 } 286 287 switch (block_type) { 288 /* 289 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 290 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 291 */ 292 case AMD_IP_BLOCK_TYPE_UVD: 293 case AMD_IP_BLOCK_TYPE_VCN: 294 ret = smu_dpm_set_vcn_enable(smu, !gate); 295 if (ret) 296 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 297 gate ? "gate" : "ungate"); 298 break; 299 case AMD_IP_BLOCK_TYPE_GFX: 300 ret = smu_gfx_off_control(smu, gate); 301 if (ret) 302 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 303 gate ? "enable" : "disable"); 304 break; 305 case AMD_IP_BLOCK_TYPE_SDMA: 306 ret = smu_powergate_sdma(smu, gate); 307 if (ret) 308 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 309 gate ? "gate" : "ungate"); 310 break; 311 case AMD_IP_BLOCK_TYPE_JPEG: 312 ret = smu_dpm_set_jpeg_enable(smu, !gate); 313 if (ret) 314 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 315 gate ? "gate" : "ungate"); 316 break; 317 default: 318 dev_err(smu->adev->dev, "Unsupported block type!\n"); 319 return -EINVAL; 320 } 321 322 return ret; 323 } 324 325 /** 326 * smu_set_user_clk_dependencies - set user profile clock dependencies 327 * 328 * @smu: smu_context pointer 329 * @clk: enum smu_clk_type type 330 * 331 * Enable/Disable the clock dependency for the @clk type. 332 */ 333 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 334 { 335 if (smu->adev->in_suspend) 336 return; 337 338 if (clk == SMU_MCLK) { 339 smu->user_dpm_profile.clk_dependency = 0; 340 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 341 } else if (clk == SMU_FCLK) { 342 /* MCLK takes precedence over FCLK */ 343 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 344 return; 345 346 smu->user_dpm_profile.clk_dependency = 0; 347 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 348 } else if (clk == SMU_SOCCLK) { 349 /* MCLK takes precedence over SOCCLK */ 350 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 351 return; 352 353 smu->user_dpm_profile.clk_dependency = 0; 354 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 355 } else 356 /* Add clk dependencies here, if any */ 357 return; 358 } 359 360 /** 361 * smu_restore_dpm_user_profile - reinstate user dpm profile 362 * 363 * @smu: smu_context pointer 364 * 365 * Restore the saved user power configurations include power limit, 366 * clock frequencies, fan control mode and fan speed. 367 */ 368 static void smu_restore_dpm_user_profile(struct smu_context *smu) 369 { 370 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 371 int ret = 0; 372 373 if (!smu->adev->in_suspend) 374 return; 375 376 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 377 return; 378 379 /* Enable restore flag */ 380 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 381 382 /* set the user dpm power limit */ 383 if (smu->user_dpm_profile.power_limit) { 384 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 385 if (ret) 386 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 387 } 388 389 /* set the user dpm clock configurations */ 390 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 391 enum smu_clk_type clk_type; 392 393 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 394 /* 395 * Iterate over smu clk type and force the saved user clk 396 * configs, skip if clock dependency is enabled 397 */ 398 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 399 smu->user_dpm_profile.clk_mask[clk_type]) { 400 ret = smu_force_smuclk_levels(smu, clk_type, 401 smu->user_dpm_profile.clk_mask[clk_type]); 402 if (ret) 403 dev_err(smu->adev->dev, 404 "Failed to set clock type = %d\n", clk_type); 405 } 406 } 407 } 408 409 /* set the user dpm fan configurations */ 410 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 411 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 412 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 413 if (ret) { 414 smu->user_dpm_profile.fan_speed_pwm = 0; 415 smu->user_dpm_profile.fan_speed_rpm = 0; 416 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 417 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 418 } 419 420 if (smu->user_dpm_profile.fan_speed_pwm) { 421 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 422 if (ret) 423 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 424 } 425 426 if (smu->user_dpm_profile.fan_speed_rpm) { 427 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 428 if (ret) 429 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 430 } 431 } 432 433 /* Restore user customized OD settings */ 434 if (smu->user_dpm_profile.user_od) { 435 if (smu->ppt_funcs->restore_user_od_settings) { 436 ret = smu->ppt_funcs->restore_user_od_settings(smu); 437 if (ret) 438 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 439 } 440 } 441 442 /* Disable restore flag */ 443 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 444 } 445 446 static int smu_get_power_num_states(void *handle, 447 struct pp_states_info *state_info) 448 { 449 if (!state_info) 450 return -EINVAL; 451 452 /* not support power state */ 453 memset(state_info, 0, sizeof(struct pp_states_info)); 454 state_info->nums = 1; 455 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 456 457 return 0; 458 } 459 460 bool is_support_sw_smu(struct amdgpu_device *adev) 461 { 462 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 463 if (adev->asic_type == CHIP_VEGA20) 464 return false; 465 466 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0)) 467 return true; 468 469 return false; 470 } 471 472 bool is_support_cclk_dpm(struct amdgpu_device *adev) 473 { 474 struct smu_context *smu = &adev->smu; 475 476 if (!is_support_sw_smu(adev)) 477 return false; 478 479 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 480 return false; 481 482 return true; 483 } 484 485 486 static int smu_sys_get_pp_table(void *handle, 487 char **table) 488 { 489 struct smu_context *smu = handle; 490 struct smu_table_context *smu_table = &smu->smu_table; 491 uint32_t powerplay_table_size; 492 493 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 494 return -EOPNOTSUPP; 495 496 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 497 return -EINVAL; 498 499 mutex_lock(&smu->mutex); 500 501 if (smu_table->hardcode_pptable) 502 *table = smu_table->hardcode_pptable; 503 else 504 *table = smu_table->power_play_table; 505 506 powerplay_table_size = smu_table->power_play_table_size; 507 508 mutex_unlock(&smu->mutex); 509 510 return powerplay_table_size; 511 } 512 513 static int smu_sys_set_pp_table(void *handle, 514 const char *buf, 515 size_t size) 516 { 517 struct smu_context *smu = handle; 518 struct smu_table_context *smu_table = &smu->smu_table; 519 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 520 int ret = 0; 521 522 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 523 return -EOPNOTSUPP; 524 525 if (header->usStructureSize != size) { 526 dev_err(smu->adev->dev, "pp table size not matched !\n"); 527 return -EIO; 528 } 529 530 mutex_lock(&smu->mutex); 531 if (!smu_table->hardcode_pptable) 532 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 533 if (!smu_table->hardcode_pptable) { 534 ret = -ENOMEM; 535 goto failed; 536 } 537 538 memcpy(smu_table->hardcode_pptable, buf, size); 539 smu_table->power_play_table = smu_table->hardcode_pptable; 540 smu_table->power_play_table_size = size; 541 542 /* 543 * Special hw_fini action(for Navi1x, the DPMs disablement will be 544 * skipped) may be needed for custom pptable uploading. 545 */ 546 smu->uploading_custom_pp_table = true; 547 548 ret = smu_reset(smu); 549 if (ret) 550 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 551 552 smu->uploading_custom_pp_table = false; 553 554 failed: 555 mutex_unlock(&smu->mutex); 556 return ret; 557 } 558 559 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 560 { 561 struct smu_feature *feature = &smu->smu_feature; 562 int ret = 0; 563 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 564 565 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 566 567 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 568 SMU_FEATURE_MAX/32); 569 if (ret) 570 return ret; 571 572 bitmap_or(feature->allowed, feature->allowed, 573 (unsigned long *)allowed_feature_mask, 574 feature->feature_num); 575 576 return ret; 577 } 578 579 static int smu_set_funcs(struct amdgpu_device *adev) 580 { 581 struct smu_context *smu = &adev->smu; 582 583 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 584 smu->od_enabled = true; 585 586 switch (adev->ip_versions[MP1_HWIP][0]) { 587 case IP_VERSION(11, 0, 0): 588 case IP_VERSION(11, 0, 5): 589 case IP_VERSION(11, 0, 9): 590 navi10_set_ppt_funcs(smu); 591 break; 592 case IP_VERSION(11, 0, 7): 593 case IP_VERSION(11, 0, 11): 594 case IP_VERSION(11, 0, 12): 595 case IP_VERSION(11, 0, 13): 596 sienna_cichlid_set_ppt_funcs(smu); 597 break; 598 case IP_VERSION(12, 0, 0): 599 case IP_VERSION(12, 0, 1): 600 renoir_set_ppt_funcs(smu); 601 break; 602 case IP_VERSION(11, 5, 0): 603 vangogh_set_ppt_funcs(smu); 604 break; 605 case IP_VERSION(13, 0, 1): 606 case IP_VERSION(13, 0, 3): 607 yellow_carp_set_ppt_funcs(smu); 608 break; 609 case IP_VERSION(11, 0, 8): 610 cyan_skillfish_set_ppt_funcs(smu); 611 break; 612 case IP_VERSION(11, 0, 2): 613 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 614 arcturus_set_ppt_funcs(smu); 615 /* OD is not supported on Arcturus */ 616 smu->od_enabled =false; 617 break; 618 case IP_VERSION(13, 0, 2): 619 aldebaran_set_ppt_funcs(smu); 620 /* Enable pp_od_clk_voltage node */ 621 smu->od_enabled = true; 622 break; 623 default: 624 return -EINVAL; 625 } 626 627 return 0; 628 } 629 630 static int smu_early_init(void *handle) 631 { 632 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 633 struct smu_context *smu = &adev->smu; 634 635 smu->adev = adev; 636 smu->pm_enabled = !!amdgpu_dpm; 637 smu->is_apu = false; 638 mutex_init(&smu->mutex); 639 mutex_init(&smu->smu_baco.mutex); 640 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 641 smu->smu_baco.platform_support = false; 642 smu->user_dpm_profile.fan_mode = -1; 643 644 adev->powerplay.pp_handle = smu; 645 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 646 647 return smu_set_funcs(adev); 648 } 649 650 static int smu_set_default_dpm_table(struct smu_context *smu) 651 { 652 struct smu_power_context *smu_power = &smu->smu_power; 653 struct smu_power_gate *power_gate = &smu_power->power_gate; 654 int vcn_gate, jpeg_gate; 655 int ret = 0; 656 657 if (!smu->ppt_funcs->set_default_dpm_table) 658 return 0; 659 660 mutex_lock(&power_gate->vcn_gate_lock); 661 mutex_lock(&power_gate->jpeg_gate_lock); 662 663 vcn_gate = atomic_read(&power_gate->vcn_gated); 664 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 665 666 ret = smu_dpm_set_vcn_enable_locked(smu, true); 667 if (ret) 668 goto err0_out; 669 670 ret = smu_dpm_set_jpeg_enable_locked(smu, true); 671 if (ret) 672 goto err1_out; 673 674 ret = smu->ppt_funcs->set_default_dpm_table(smu); 675 if (ret) 676 dev_err(smu->adev->dev, 677 "Failed to setup default dpm clock tables!\n"); 678 679 smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate); 680 err1_out: 681 smu_dpm_set_vcn_enable_locked(smu, !vcn_gate); 682 err0_out: 683 mutex_unlock(&power_gate->jpeg_gate_lock); 684 mutex_unlock(&power_gate->vcn_gate_lock); 685 686 return ret; 687 } 688 689 690 static int smu_late_init(void *handle) 691 { 692 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 693 struct smu_context *smu = &adev->smu; 694 int ret = 0; 695 696 smu_set_fine_grain_gfx_freq_parameters(smu); 697 698 if (!smu->pm_enabled) 699 return 0; 700 701 ret = smu_post_init(smu); 702 if (ret) { 703 dev_err(adev->dev, "Failed to post smu init!\n"); 704 return ret; 705 } 706 707 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || 708 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) 709 return 0; 710 711 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 712 ret = smu_set_default_od_settings(smu); 713 if (ret) { 714 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 715 return ret; 716 } 717 } 718 719 ret = smu_populate_umd_state_clk(smu); 720 if (ret) { 721 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 722 return ret; 723 } 724 725 ret = smu_get_asic_power_limits(smu, 726 &smu->current_power_limit, 727 &smu->default_power_limit, 728 &smu->max_power_limit); 729 if (ret) { 730 dev_err(adev->dev, "Failed to get asic power limits!\n"); 731 return ret; 732 } 733 734 if (!amdgpu_sriov_vf(adev)) 735 smu_get_unique_id(smu); 736 737 smu_get_fan_parameters(smu); 738 739 smu_handle_task(&adev->smu, 740 smu->smu_dpm.dpm_level, 741 AMD_PP_TASK_COMPLETE_INIT, 742 false); 743 744 smu_restore_dpm_user_profile(smu); 745 746 return 0; 747 } 748 749 static int smu_init_fb_allocations(struct smu_context *smu) 750 { 751 struct amdgpu_device *adev = smu->adev; 752 struct smu_table_context *smu_table = &smu->smu_table; 753 struct smu_table *tables = smu_table->tables; 754 struct smu_table *driver_table = &(smu_table->driver_table); 755 uint32_t max_table_size = 0; 756 int ret, i; 757 758 /* VRAM allocation for tool table */ 759 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 760 ret = amdgpu_bo_create_kernel(adev, 761 tables[SMU_TABLE_PMSTATUSLOG].size, 762 tables[SMU_TABLE_PMSTATUSLOG].align, 763 tables[SMU_TABLE_PMSTATUSLOG].domain, 764 &tables[SMU_TABLE_PMSTATUSLOG].bo, 765 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 766 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 767 if (ret) { 768 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 769 return ret; 770 } 771 } 772 773 /* VRAM allocation for driver table */ 774 for (i = 0; i < SMU_TABLE_COUNT; i++) { 775 if (tables[i].size == 0) 776 continue; 777 778 if (i == SMU_TABLE_PMSTATUSLOG) 779 continue; 780 781 if (max_table_size < tables[i].size) 782 max_table_size = tables[i].size; 783 } 784 785 driver_table->size = max_table_size; 786 driver_table->align = PAGE_SIZE; 787 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 788 789 ret = amdgpu_bo_create_kernel(adev, 790 driver_table->size, 791 driver_table->align, 792 driver_table->domain, 793 &driver_table->bo, 794 &driver_table->mc_address, 795 &driver_table->cpu_addr); 796 if (ret) { 797 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 798 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 799 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 800 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 801 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 802 } 803 804 return ret; 805 } 806 807 static int smu_fini_fb_allocations(struct smu_context *smu) 808 { 809 struct smu_table_context *smu_table = &smu->smu_table; 810 struct smu_table *tables = smu_table->tables; 811 struct smu_table *driver_table = &(smu_table->driver_table); 812 813 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 814 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 815 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 816 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 817 818 amdgpu_bo_free_kernel(&driver_table->bo, 819 &driver_table->mc_address, 820 &driver_table->cpu_addr); 821 822 return 0; 823 } 824 825 /** 826 * smu_alloc_memory_pool - allocate memory pool in the system memory 827 * 828 * @smu: amdgpu_device pointer 829 * 830 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 831 * and DramLogSetDramAddr can notify it changed. 832 * 833 * Returns 0 on success, error on failure. 834 */ 835 static int smu_alloc_memory_pool(struct smu_context *smu) 836 { 837 struct amdgpu_device *adev = smu->adev; 838 struct smu_table_context *smu_table = &smu->smu_table; 839 struct smu_table *memory_pool = &smu_table->memory_pool; 840 uint64_t pool_size = smu->pool_size; 841 int ret = 0; 842 843 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 844 return ret; 845 846 memory_pool->size = pool_size; 847 memory_pool->align = PAGE_SIZE; 848 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 849 850 switch (pool_size) { 851 case SMU_MEMORY_POOL_SIZE_256_MB: 852 case SMU_MEMORY_POOL_SIZE_512_MB: 853 case SMU_MEMORY_POOL_SIZE_1_GB: 854 case SMU_MEMORY_POOL_SIZE_2_GB: 855 ret = amdgpu_bo_create_kernel(adev, 856 memory_pool->size, 857 memory_pool->align, 858 memory_pool->domain, 859 &memory_pool->bo, 860 &memory_pool->mc_address, 861 &memory_pool->cpu_addr); 862 if (ret) 863 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 864 break; 865 default: 866 break; 867 } 868 869 return ret; 870 } 871 872 static int smu_free_memory_pool(struct smu_context *smu) 873 { 874 struct smu_table_context *smu_table = &smu->smu_table; 875 struct smu_table *memory_pool = &smu_table->memory_pool; 876 877 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 878 return 0; 879 880 amdgpu_bo_free_kernel(&memory_pool->bo, 881 &memory_pool->mc_address, 882 &memory_pool->cpu_addr); 883 884 memset(memory_pool, 0, sizeof(struct smu_table)); 885 886 return 0; 887 } 888 889 static int smu_alloc_dummy_read_table(struct smu_context *smu) 890 { 891 struct smu_table_context *smu_table = &smu->smu_table; 892 struct smu_table *dummy_read_1_table = 893 &smu_table->dummy_read_1_table; 894 struct amdgpu_device *adev = smu->adev; 895 int ret = 0; 896 897 dummy_read_1_table->size = 0x40000; 898 dummy_read_1_table->align = PAGE_SIZE; 899 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 900 901 ret = amdgpu_bo_create_kernel(adev, 902 dummy_read_1_table->size, 903 dummy_read_1_table->align, 904 dummy_read_1_table->domain, 905 &dummy_read_1_table->bo, 906 &dummy_read_1_table->mc_address, 907 &dummy_read_1_table->cpu_addr); 908 if (ret) 909 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 910 911 return ret; 912 } 913 914 static void smu_free_dummy_read_table(struct smu_context *smu) 915 { 916 struct smu_table_context *smu_table = &smu->smu_table; 917 struct smu_table *dummy_read_1_table = 918 &smu_table->dummy_read_1_table; 919 920 921 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 922 &dummy_read_1_table->mc_address, 923 &dummy_read_1_table->cpu_addr); 924 925 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 926 } 927 928 static int smu_smc_table_sw_init(struct smu_context *smu) 929 { 930 int ret; 931 932 /** 933 * Create smu_table structure, and init smc tables such as 934 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 935 */ 936 ret = smu_init_smc_tables(smu); 937 if (ret) { 938 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 939 return ret; 940 } 941 942 /** 943 * Create smu_power_context structure, and allocate smu_dpm_context and 944 * context size to fill the smu_power_context data. 945 */ 946 ret = smu_init_power(smu); 947 if (ret) { 948 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 949 return ret; 950 } 951 952 /* 953 * allocate vram bos to store smc table contents. 954 */ 955 ret = smu_init_fb_allocations(smu); 956 if (ret) 957 return ret; 958 959 ret = smu_alloc_memory_pool(smu); 960 if (ret) 961 return ret; 962 963 ret = smu_alloc_dummy_read_table(smu); 964 if (ret) 965 return ret; 966 967 ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c); 968 if (ret) 969 return ret; 970 971 return 0; 972 } 973 974 static int smu_smc_table_sw_fini(struct smu_context *smu) 975 { 976 int ret; 977 978 smu_i2c_fini(smu, &smu->adev->pm.smu_i2c); 979 980 smu_free_dummy_read_table(smu); 981 982 ret = smu_free_memory_pool(smu); 983 if (ret) 984 return ret; 985 986 ret = smu_fini_fb_allocations(smu); 987 if (ret) 988 return ret; 989 990 ret = smu_fini_power(smu); 991 if (ret) { 992 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 993 return ret; 994 } 995 996 ret = smu_fini_smc_tables(smu); 997 if (ret) { 998 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 999 return ret; 1000 } 1001 1002 return 0; 1003 } 1004 1005 static void smu_throttling_logging_work_fn(struct work_struct *work) 1006 { 1007 struct smu_context *smu = container_of(work, struct smu_context, 1008 throttling_logging_work); 1009 1010 smu_log_thermal_throttling(smu); 1011 } 1012 1013 static void smu_interrupt_work_fn(struct work_struct *work) 1014 { 1015 struct smu_context *smu = container_of(work, struct smu_context, 1016 interrupt_work); 1017 1018 mutex_lock(&smu->mutex); 1019 1020 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1021 smu->ppt_funcs->interrupt_work(smu); 1022 1023 mutex_unlock(&smu->mutex); 1024 } 1025 1026 static int smu_sw_init(void *handle) 1027 { 1028 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1029 struct smu_context *smu = &adev->smu; 1030 int ret; 1031 1032 smu->pool_size = adev->pm.smu_prv_buffer_size; 1033 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1034 mutex_init(&smu->smu_feature.mutex); 1035 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1036 bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX); 1037 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1038 1039 mutex_init(&smu->sensor_lock); 1040 mutex_init(&smu->metrics_lock); 1041 mutex_init(&smu->message_lock); 1042 1043 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1044 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1045 atomic64_set(&smu->throttle_int_counter, 0); 1046 smu->watermarks_bitmap = 0; 1047 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1048 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1049 1050 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1051 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1052 mutex_init(&smu->smu_power.power_gate.vcn_gate_lock); 1053 mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock); 1054 1055 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1056 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1057 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1058 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1059 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1060 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1061 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1062 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1063 1064 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1065 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1066 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1067 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1068 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1069 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1070 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1071 smu->display_config = &adev->pm.pm_display_cfg; 1072 1073 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1074 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1075 1076 ret = smu_init_microcode(smu); 1077 if (ret) { 1078 dev_err(adev->dev, "Failed to load smu firmware!\n"); 1079 return ret; 1080 } 1081 1082 ret = smu_smc_table_sw_init(smu); 1083 if (ret) { 1084 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1085 return ret; 1086 } 1087 1088 ret = smu_register_irq_handler(smu); 1089 if (ret) { 1090 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1091 return ret; 1092 } 1093 1094 /* If there is no way to query fan control mode, fan control is not supported */ 1095 if (!smu->ppt_funcs->get_fan_control_mode) 1096 smu->adev->pm.no_fan = true; 1097 1098 return 0; 1099 } 1100 1101 static int smu_sw_fini(void *handle) 1102 { 1103 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1104 struct smu_context *smu = &adev->smu; 1105 int ret; 1106 1107 ret = smu_smc_table_sw_fini(smu); 1108 if (ret) { 1109 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1110 return ret; 1111 } 1112 1113 smu_fini_microcode(smu); 1114 1115 return 0; 1116 } 1117 1118 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1119 { 1120 struct amdgpu_device *adev = smu->adev; 1121 struct smu_temperature_range *range = 1122 &smu->thermal_range; 1123 int ret = 0; 1124 1125 if (!smu->ppt_funcs->get_thermal_temperature_range) 1126 return 0; 1127 1128 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1129 if (ret) 1130 return ret; 1131 1132 adev->pm.dpm.thermal.min_temp = range->min; 1133 adev->pm.dpm.thermal.max_temp = range->max; 1134 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1135 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1136 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1137 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1138 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1139 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1140 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1141 1142 return ret; 1143 } 1144 1145 static int smu_smc_hw_setup(struct smu_context *smu) 1146 { 1147 struct amdgpu_device *adev = smu->adev; 1148 uint32_t pcie_gen = 0, pcie_width = 0; 1149 int ret = 0; 1150 1151 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1152 dev_info(adev->dev, "dpm has been enabled\n"); 1153 /* this is needed specifically */ 1154 switch (adev->ip_versions[MP1_HWIP][0]) { 1155 case IP_VERSION(11, 0, 7): 1156 case IP_VERSION(11, 0, 11): 1157 case IP_VERSION(11, 5, 0): 1158 case IP_VERSION(11, 0, 12): 1159 ret = smu_system_features_control(smu, true); 1160 if (ret) 1161 dev_err(adev->dev, "Failed system features control!\n"); 1162 break; 1163 default: 1164 break; 1165 } 1166 return ret; 1167 } 1168 1169 ret = smu_init_display_count(smu, 0); 1170 if (ret) { 1171 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1172 return ret; 1173 } 1174 1175 ret = smu_set_driver_table_location(smu); 1176 if (ret) { 1177 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1178 return ret; 1179 } 1180 1181 /* 1182 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1183 */ 1184 ret = smu_set_tool_table_location(smu); 1185 if (ret) { 1186 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1187 return ret; 1188 } 1189 1190 /* 1191 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1192 * pool location. 1193 */ 1194 ret = smu_notify_memory_pool_location(smu); 1195 if (ret) { 1196 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1197 return ret; 1198 } 1199 1200 /* smu_dump_pptable(smu); */ 1201 /* 1202 * Copy pptable bo in the vram to smc with SMU MSGs such as 1203 * SetDriverDramAddr and TransferTableDram2Smu. 1204 */ 1205 ret = smu_write_pptable(smu); 1206 if (ret) { 1207 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1208 return ret; 1209 } 1210 1211 /* issue Run*Btc msg */ 1212 ret = smu_run_btc(smu); 1213 if (ret) 1214 return ret; 1215 1216 ret = smu_feature_set_allowed_mask(smu); 1217 if (ret) { 1218 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1219 return ret; 1220 } 1221 1222 ret = smu_system_features_control(smu, true); 1223 if (ret) { 1224 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1225 return ret; 1226 } 1227 1228 if (!smu_is_dpm_running(smu)) 1229 dev_info(adev->dev, "dpm has been disabled\n"); 1230 1231 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1232 pcie_gen = 3; 1233 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1234 pcie_gen = 2; 1235 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1236 pcie_gen = 1; 1237 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1238 pcie_gen = 0; 1239 1240 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1241 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1242 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1243 */ 1244 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1245 pcie_width = 6; 1246 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1247 pcie_width = 5; 1248 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1249 pcie_width = 4; 1250 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1251 pcie_width = 3; 1252 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1253 pcie_width = 2; 1254 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1255 pcie_width = 1; 1256 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1257 if (ret) { 1258 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1259 return ret; 1260 } 1261 1262 ret = smu_get_thermal_temperature_range(smu); 1263 if (ret) { 1264 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1265 return ret; 1266 } 1267 1268 ret = smu_enable_thermal_alert(smu); 1269 if (ret) { 1270 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1271 return ret; 1272 } 1273 1274 /* 1275 * Set initialized values (get from vbios) to dpm tables context such as 1276 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1277 * type of clks. 1278 */ 1279 ret = smu_set_default_dpm_table(smu); 1280 if (ret) { 1281 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1282 return ret; 1283 } 1284 1285 ret = smu_notify_display_change(smu); 1286 if (ret) { 1287 dev_err(adev->dev, "Failed to notify display change!\n"); 1288 return ret; 1289 } 1290 1291 /* 1292 * Set min deep sleep dce fclk with bootup value from vbios via 1293 * SetMinDeepSleepDcefclk MSG. 1294 */ 1295 ret = smu_set_min_dcef_deep_sleep(smu, 1296 smu->smu_table.boot_values.dcefclk / 100); 1297 1298 return ret; 1299 } 1300 1301 static int smu_start_smc_engine(struct smu_context *smu) 1302 { 1303 struct amdgpu_device *adev = smu->adev; 1304 int ret = 0; 1305 1306 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1307 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) { 1308 if (smu->ppt_funcs->load_microcode) { 1309 ret = smu->ppt_funcs->load_microcode(smu); 1310 if (ret) 1311 return ret; 1312 } 1313 } 1314 } 1315 1316 if (smu->ppt_funcs->check_fw_status) { 1317 ret = smu->ppt_funcs->check_fw_status(smu); 1318 if (ret) { 1319 dev_err(adev->dev, "SMC is not ready\n"); 1320 return ret; 1321 } 1322 } 1323 1324 /* 1325 * Send msg GetDriverIfVersion to check if the return value is equal 1326 * with DRIVER_IF_VERSION of smc header. 1327 */ 1328 ret = smu_check_fw_version(smu); 1329 if (ret) 1330 return ret; 1331 1332 return ret; 1333 } 1334 1335 static int smu_hw_init(void *handle) 1336 { 1337 int ret; 1338 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1339 struct smu_context *smu = &adev->smu; 1340 1341 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1342 smu->pm_enabled = false; 1343 return 0; 1344 } 1345 1346 ret = smu_start_smc_engine(smu); 1347 if (ret) { 1348 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1349 return ret; 1350 } 1351 1352 if (smu->is_apu) { 1353 smu_dpm_set_vcn_enable(smu, true); 1354 smu_dpm_set_jpeg_enable(smu, true); 1355 smu_set_gfx_cgpg(&adev->smu, true); 1356 } 1357 1358 if (!smu->pm_enabled) 1359 return 0; 1360 1361 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1362 ret = smu_get_vbios_bootup_values(smu); 1363 if (ret) { 1364 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1365 return ret; 1366 } 1367 1368 ret = smu_setup_pptable(smu); 1369 if (ret) { 1370 dev_err(adev->dev, "Failed to setup pptable!\n"); 1371 return ret; 1372 } 1373 1374 ret = smu_get_driver_allowed_feature_mask(smu); 1375 if (ret) 1376 return ret; 1377 1378 ret = smu_smc_hw_setup(smu); 1379 if (ret) { 1380 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1381 return ret; 1382 } 1383 1384 /* 1385 * Move maximum sustainable clock retrieving here considering 1386 * 1. It is not needed on resume(from S3). 1387 * 2. DAL settings come between .hw_init and .late_init of SMU. 1388 * And DAL needs to know the maximum sustainable clocks. Thus 1389 * it cannot be put in .late_init(). 1390 */ 1391 ret = smu_init_max_sustainable_clocks(smu); 1392 if (ret) { 1393 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1394 return ret; 1395 } 1396 1397 adev->pm.dpm_enabled = true; 1398 1399 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1400 1401 return 0; 1402 } 1403 1404 static int smu_disable_dpms(struct smu_context *smu) 1405 { 1406 struct amdgpu_device *adev = smu->adev; 1407 int ret = 0; 1408 /* 1409 * TODO: (adev->in_suspend && !adev->in_s0ix) is added to pair 1410 * the workaround which always reset the asic in suspend. 1411 * It's likely that workaround will be dropped in the future. 1412 * Then the change here should be dropped together. 1413 */ 1414 bool use_baco = !smu->is_apu && 1415 (((amdgpu_in_reset(adev) || (adev->in_suspend && !adev->in_s0ix)) && 1416 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1417 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1418 1419 /* 1420 * For custom pptable uploading, skip the DPM features 1421 * disable process on Navi1x ASICs. 1422 * - As the gfx related features are under control of 1423 * RLC on those ASICs. RLC reinitialization will be 1424 * needed to reenable them. That will cost much more 1425 * efforts. 1426 * 1427 * - SMU firmware can handle the DPM reenablement 1428 * properly. 1429 */ 1430 if (smu->uploading_custom_pp_table) { 1431 switch (adev->ip_versions[MP1_HWIP][0]) { 1432 case IP_VERSION(11, 0, 0): 1433 case IP_VERSION(11, 0, 5): 1434 case IP_VERSION(11, 0, 9): 1435 case IP_VERSION(11, 0, 7): 1436 case IP_VERSION(11, 0, 11): 1437 case IP_VERSION(11, 5, 0): 1438 case IP_VERSION(11, 0, 12): 1439 case IP_VERSION(11, 0, 13): 1440 return smu_disable_all_features_with_exception(smu, 1441 true, 1442 SMU_FEATURE_COUNT); 1443 default: 1444 break; 1445 } 1446 } 1447 1448 /* 1449 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1450 * on BACO in. Driver involvement is unnecessary. 1451 */ 1452 if (use_baco) { 1453 switch (adev->ip_versions[MP1_HWIP][0]) { 1454 case IP_VERSION(11, 0, 7): 1455 case IP_VERSION(11, 0, 0): 1456 case IP_VERSION(11, 0, 5): 1457 case IP_VERSION(11, 0, 9): 1458 return smu_disable_all_features_with_exception(smu, 1459 true, 1460 SMU_FEATURE_BACO_BIT); 1461 default: 1462 break; 1463 } 1464 } 1465 1466 /* 1467 * For gpu reset, runpm and hibernation through BACO, 1468 * BACO feature has to be kept enabled. 1469 */ 1470 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1471 ret = smu_disable_all_features_with_exception(smu, 1472 false, 1473 SMU_FEATURE_BACO_BIT); 1474 if (ret) 1475 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1476 } else { 1477 ret = smu_system_features_control(smu, false); 1478 if (ret) 1479 dev_err(adev->dev, "Failed to disable smu features.\n"); 1480 } 1481 1482 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) && 1483 adev->gfx.rlc.funcs->stop) 1484 adev->gfx.rlc.funcs->stop(adev); 1485 1486 return ret; 1487 } 1488 1489 static int smu_smc_hw_cleanup(struct smu_context *smu) 1490 { 1491 struct amdgpu_device *adev = smu->adev; 1492 int ret = 0; 1493 1494 cancel_work_sync(&smu->throttling_logging_work); 1495 cancel_work_sync(&smu->interrupt_work); 1496 1497 ret = smu_disable_thermal_alert(smu); 1498 if (ret) { 1499 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1500 return ret; 1501 } 1502 1503 ret = smu_disable_dpms(smu); 1504 if (ret) { 1505 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1506 return ret; 1507 } 1508 1509 return 0; 1510 } 1511 1512 static int smu_hw_fini(void *handle) 1513 { 1514 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1515 struct smu_context *smu = &adev->smu; 1516 1517 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1518 return 0; 1519 1520 smu_dpm_set_vcn_enable(smu, false); 1521 smu_dpm_set_jpeg_enable(smu, false); 1522 1523 adev->vcn.cur_state = AMD_PG_STATE_GATE; 1524 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 1525 1526 if (!smu->pm_enabled) 1527 return 0; 1528 1529 adev->pm.dpm_enabled = false; 1530 1531 return smu_smc_hw_cleanup(smu); 1532 } 1533 1534 static int smu_reset(struct smu_context *smu) 1535 { 1536 struct amdgpu_device *adev = smu->adev; 1537 int ret; 1538 1539 amdgpu_gfx_off_ctrl(smu->adev, false); 1540 1541 ret = smu_hw_fini(adev); 1542 if (ret) 1543 return ret; 1544 1545 ret = smu_hw_init(adev); 1546 if (ret) 1547 return ret; 1548 1549 ret = smu_late_init(adev); 1550 if (ret) 1551 return ret; 1552 1553 amdgpu_gfx_off_ctrl(smu->adev, true); 1554 1555 return 0; 1556 } 1557 1558 static int smu_suspend(void *handle) 1559 { 1560 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1561 struct smu_context *smu = &adev->smu; 1562 int ret; 1563 1564 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1565 return 0; 1566 1567 if (!smu->pm_enabled) 1568 return 0; 1569 1570 adev->pm.dpm_enabled = false; 1571 1572 ret = smu_smc_hw_cleanup(smu); 1573 if (ret) 1574 return ret; 1575 1576 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1577 1578 smu_set_gfx_cgpg(&adev->smu, false); 1579 1580 return 0; 1581 } 1582 1583 static int smu_resume(void *handle) 1584 { 1585 int ret; 1586 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1587 struct smu_context *smu = &adev->smu; 1588 1589 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1590 return 0; 1591 1592 if (!smu->pm_enabled) 1593 return 0; 1594 1595 dev_info(adev->dev, "SMU is resuming...\n"); 1596 1597 ret = smu_start_smc_engine(smu); 1598 if (ret) { 1599 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1600 return ret; 1601 } 1602 1603 ret = smu_smc_hw_setup(smu); 1604 if (ret) { 1605 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1606 return ret; 1607 } 1608 1609 smu_set_gfx_cgpg(&adev->smu, true); 1610 1611 smu->disable_uclk_switch = 0; 1612 1613 adev->pm.dpm_enabled = true; 1614 1615 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1616 1617 return 0; 1618 } 1619 1620 static int smu_display_configuration_change(void *handle, 1621 const struct amd_pp_display_configuration *display_config) 1622 { 1623 struct smu_context *smu = handle; 1624 int index = 0; 1625 int num_of_active_display = 0; 1626 1627 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1628 return -EOPNOTSUPP; 1629 1630 if (!display_config) 1631 return -EINVAL; 1632 1633 mutex_lock(&smu->mutex); 1634 1635 smu_set_min_dcef_deep_sleep(smu, 1636 display_config->min_dcef_deep_sleep_set_clk / 100); 1637 1638 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1639 if (display_config->displays[index].controller_id != 0) 1640 num_of_active_display++; 1641 } 1642 1643 mutex_unlock(&smu->mutex); 1644 1645 return 0; 1646 } 1647 1648 static int smu_set_clockgating_state(void *handle, 1649 enum amd_clockgating_state state) 1650 { 1651 return 0; 1652 } 1653 1654 static int smu_set_powergating_state(void *handle, 1655 enum amd_powergating_state state) 1656 { 1657 return 0; 1658 } 1659 1660 static int smu_enable_umd_pstate(void *handle, 1661 enum amd_dpm_forced_level *level) 1662 { 1663 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1664 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1665 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1666 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1667 1668 struct smu_context *smu = (struct smu_context*)(handle); 1669 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1670 1671 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1672 return -EINVAL; 1673 1674 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1675 /* enter umd pstate, save current level, disable gfx cg*/ 1676 if (*level & profile_mode_mask) { 1677 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1678 smu_dpm_ctx->enable_umd_pstate = true; 1679 smu_gpo_control(smu, false); 1680 amdgpu_device_ip_set_powergating_state(smu->adev, 1681 AMD_IP_BLOCK_TYPE_GFX, 1682 AMD_PG_STATE_UNGATE); 1683 amdgpu_device_ip_set_clockgating_state(smu->adev, 1684 AMD_IP_BLOCK_TYPE_GFX, 1685 AMD_CG_STATE_UNGATE); 1686 smu_gfx_ulv_control(smu, false); 1687 smu_deep_sleep_control(smu, false); 1688 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1689 } 1690 } else { 1691 /* exit umd pstate, restore level, enable gfx cg*/ 1692 if (!(*level & profile_mode_mask)) { 1693 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1694 *level = smu_dpm_ctx->saved_dpm_level; 1695 smu_dpm_ctx->enable_umd_pstate = false; 1696 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1697 smu_deep_sleep_control(smu, true); 1698 smu_gfx_ulv_control(smu, true); 1699 amdgpu_device_ip_set_clockgating_state(smu->adev, 1700 AMD_IP_BLOCK_TYPE_GFX, 1701 AMD_CG_STATE_GATE); 1702 amdgpu_device_ip_set_powergating_state(smu->adev, 1703 AMD_IP_BLOCK_TYPE_GFX, 1704 AMD_PG_STATE_GATE); 1705 smu_gpo_control(smu, true); 1706 } 1707 } 1708 1709 return 0; 1710 } 1711 1712 static int smu_bump_power_profile_mode(struct smu_context *smu, 1713 long *param, 1714 uint32_t param_size) 1715 { 1716 int ret = 0; 1717 1718 if (smu->ppt_funcs->set_power_profile_mode) 1719 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1720 1721 return ret; 1722 } 1723 1724 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1725 enum amd_dpm_forced_level level, 1726 bool skip_display_settings) 1727 { 1728 int ret = 0; 1729 int index = 0; 1730 long workload; 1731 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1732 1733 if (!skip_display_settings) { 1734 ret = smu_display_config_changed(smu); 1735 if (ret) { 1736 dev_err(smu->adev->dev, "Failed to change display config!"); 1737 return ret; 1738 } 1739 } 1740 1741 ret = smu_apply_clocks_adjust_rules(smu); 1742 if (ret) { 1743 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1744 return ret; 1745 } 1746 1747 if (!skip_display_settings) { 1748 ret = smu_notify_smc_display_config(smu); 1749 if (ret) { 1750 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1751 return ret; 1752 } 1753 } 1754 1755 if (smu_dpm_ctx->dpm_level != level) { 1756 ret = smu_asic_set_performance_level(smu, level); 1757 if (ret) { 1758 dev_err(smu->adev->dev, "Failed to set performance level!"); 1759 return ret; 1760 } 1761 1762 /* update the saved copy */ 1763 smu_dpm_ctx->dpm_level = level; 1764 } 1765 1766 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1767 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1768 index = fls(smu->workload_mask); 1769 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1770 workload = smu->workload_setting[index]; 1771 1772 if (smu->power_profile_mode != workload) 1773 smu_bump_power_profile_mode(smu, &workload, 0); 1774 } 1775 1776 return ret; 1777 } 1778 1779 static int smu_handle_task(struct smu_context *smu, 1780 enum amd_dpm_forced_level level, 1781 enum amd_pp_task task_id, 1782 bool lock_needed) 1783 { 1784 int ret = 0; 1785 1786 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1787 return -EOPNOTSUPP; 1788 1789 if (lock_needed) 1790 mutex_lock(&smu->mutex); 1791 1792 switch (task_id) { 1793 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1794 ret = smu_pre_display_config_changed(smu); 1795 if (ret) 1796 goto out; 1797 ret = smu_adjust_power_state_dynamic(smu, level, false); 1798 break; 1799 case AMD_PP_TASK_COMPLETE_INIT: 1800 case AMD_PP_TASK_READJUST_POWER_STATE: 1801 ret = smu_adjust_power_state_dynamic(smu, level, true); 1802 break; 1803 default: 1804 break; 1805 } 1806 1807 out: 1808 if (lock_needed) 1809 mutex_unlock(&smu->mutex); 1810 1811 return ret; 1812 } 1813 1814 static int smu_handle_dpm_task(void *handle, 1815 enum amd_pp_task task_id, 1816 enum amd_pm_state_type *user_state) 1817 { 1818 struct smu_context *smu = handle; 1819 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1820 1821 return smu_handle_task(smu, smu_dpm->dpm_level, task_id, true); 1822 1823 } 1824 1825 static int smu_switch_power_profile(void *handle, 1826 enum PP_SMC_POWER_PROFILE type, 1827 bool en) 1828 { 1829 struct smu_context *smu = handle; 1830 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1831 long workload; 1832 uint32_t index; 1833 1834 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1835 return -EOPNOTSUPP; 1836 1837 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1838 return -EINVAL; 1839 1840 mutex_lock(&smu->mutex); 1841 1842 if (!en) { 1843 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1844 index = fls(smu->workload_mask); 1845 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1846 workload = smu->workload_setting[index]; 1847 } else { 1848 smu->workload_mask |= (1 << smu->workload_prority[type]); 1849 index = fls(smu->workload_mask); 1850 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1851 workload = smu->workload_setting[index]; 1852 } 1853 1854 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1855 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1856 smu_bump_power_profile_mode(smu, &workload, 0); 1857 1858 mutex_unlock(&smu->mutex); 1859 1860 return 0; 1861 } 1862 1863 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 1864 { 1865 struct smu_context *smu = handle; 1866 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1867 enum amd_dpm_forced_level level; 1868 1869 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1870 return -EOPNOTSUPP; 1871 1872 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1873 return -EINVAL; 1874 1875 mutex_lock(&(smu->mutex)); 1876 level = smu_dpm_ctx->dpm_level; 1877 mutex_unlock(&(smu->mutex)); 1878 1879 return level; 1880 } 1881 1882 static int smu_force_performance_level(void *handle, 1883 enum amd_dpm_forced_level level) 1884 { 1885 struct smu_context *smu = handle; 1886 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1887 int ret = 0; 1888 1889 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1890 return -EOPNOTSUPP; 1891 1892 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1893 return -EINVAL; 1894 1895 mutex_lock(&smu->mutex); 1896 1897 ret = smu_enable_umd_pstate(smu, &level); 1898 if (ret) { 1899 mutex_unlock(&smu->mutex); 1900 return ret; 1901 } 1902 1903 ret = smu_handle_task(smu, level, 1904 AMD_PP_TASK_READJUST_POWER_STATE, 1905 false); 1906 1907 mutex_unlock(&smu->mutex); 1908 1909 /* reset user dpm clock state */ 1910 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1911 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 1912 smu->user_dpm_profile.clk_dependency = 0; 1913 } 1914 1915 return ret; 1916 } 1917 1918 static int smu_set_display_count(void *handle, uint32_t count) 1919 { 1920 struct smu_context *smu = handle; 1921 int ret = 0; 1922 1923 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1924 return -EOPNOTSUPP; 1925 1926 mutex_lock(&smu->mutex); 1927 ret = smu_init_display_count(smu, count); 1928 mutex_unlock(&smu->mutex); 1929 1930 return ret; 1931 } 1932 1933 static int smu_force_smuclk_levels(struct smu_context *smu, 1934 enum smu_clk_type clk_type, 1935 uint32_t mask) 1936 { 1937 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1938 int ret = 0; 1939 1940 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1941 return -EOPNOTSUPP; 1942 1943 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1944 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1945 return -EINVAL; 1946 } 1947 1948 mutex_lock(&smu->mutex); 1949 1950 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 1951 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1952 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 1953 smu->user_dpm_profile.clk_mask[clk_type] = mask; 1954 smu_set_user_clk_dependencies(smu, clk_type); 1955 } 1956 } 1957 1958 mutex_unlock(&smu->mutex); 1959 1960 return ret; 1961 } 1962 1963 static int smu_force_ppclk_levels(void *handle, 1964 enum pp_clock_type type, 1965 uint32_t mask) 1966 { 1967 struct smu_context *smu = handle; 1968 enum smu_clk_type clk_type; 1969 1970 switch (type) { 1971 case PP_SCLK: 1972 clk_type = SMU_SCLK; break; 1973 case PP_MCLK: 1974 clk_type = SMU_MCLK; break; 1975 case PP_PCIE: 1976 clk_type = SMU_PCIE; break; 1977 case PP_SOCCLK: 1978 clk_type = SMU_SOCCLK; break; 1979 case PP_FCLK: 1980 clk_type = SMU_FCLK; break; 1981 case PP_DCEFCLK: 1982 clk_type = SMU_DCEFCLK; break; 1983 case PP_VCLK: 1984 clk_type = SMU_VCLK; break; 1985 case PP_DCLK: 1986 clk_type = SMU_DCLK; break; 1987 case OD_SCLK: 1988 clk_type = SMU_OD_SCLK; break; 1989 case OD_MCLK: 1990 clk_type = SMU_OD_MCLK; break; 1991 case OD_VDDC_CURVE: 1992 clk_type = SMU_OD_VDDC_CURVE; break; 1993 case OD_RANGE: 1994 clk_type = SMU_OD_RANGE; break; 1995 default: 1996 return -EINVAL; 1997 } 1998 1999 return smu_force_smuclk_levels(smu, clk_type, mask); 2000 } 2001 2002 /* 2003 * On system suspending or resetting, the dpm_enabled 2004 * flag will be cleared. So that those SMU services which 2005 * are not supported will be gated. 2006 * However, the mp1 state setting should still be granted 2007 * even if the dpm_enabled cleared. 2008 */ 2009 static int smu_set_mp1_state(void *handle, 2010 enum pp_mp1_state mp1_state) 2011 { 2012 struct smu_context *smu = handle; 2013 int ret = 0; 2014 2015 if (!smu->pm_enabled) 2016 return -EOPNOTSUPP; 2017 2018 mutex_lock(&smu->mutex); 2019 2020 if (smu->ppt_funcs && 2021 smu->ppt_funcs->set_mp1_state) 2022 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2023 2024 mutex_unlock(&smu->mutex); 2025 2026 return ret; 2027 } 2028 2029 static int smu_set_df_cstate(void *handle, 2030 enum pp_df_cstate state) 2031 { 2032 struct smu_context *smu = handle; 2033 int ret = 0; 2034 2035 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2036 return -EOPNOTSUPP; 2037 2038 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2039 return 0; 2040 2041 mutex_lock(&smu->mutex); 2042 2043 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2044 if (ret) 2045 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2046 2047 mutex_unlock(&smu->mutex); 2048 2049 return ret; 2050 } 2051 2052 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 2053 { 2054 int ret = 0; 2055 2056 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2057 return -EOPNOTSUPP; 2058 2059 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 2060 return 0; 2061 2062 mutex_lock(&smu->mutex); 2063 2064 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 2065 if (ret) 2066 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 2067 2068 mutex_unlock(&smu->mutex); 2069 2070 return ret; 2071 } 2072 2073 int smu_write_watermarks_table(struct smu_context *smu) 2074 { 2075 int ret = 0; 2076 2077 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2078 return -EOPNOTSUPP; 2079 2080 mutex_lock(&smu->mutex); 2081 2082 ret = smu_set_watermarks_table(smu, NULL); 2083 2084 mutex_unlock(&smu->mutex); 2085 2086 return ret; 2087 } 2088 2089 static int smu_set_watermarks_for_clock_ranges(void *handle, 2090 struct pp_smu_wm_range_sets *clock_ranges) 2091 { 2092 struct smu_context *smu = handle; 2093 int ret = 0; 2094 2095 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2096 return -EOPNOTSUPP; 2097 2098 if (smu->disable_watermark) 2099 return 0; 2100 2101 mutex_lock(&smu->mutex); 2102 2103 ret = smu_set_watermarks_table(smu, clock_ranges); 2104 2105 mutex_unlock(&smu->mutex); 2106 2107 return ret; 2108 } 2109 2110 int smu_set_ac_dc(struct smu_context *smu) 2111 { 2112 int ret = 0; 2113 2114 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2115 return -EOPNOTSUPP; 2116 2117 /* controlled by firmware */ 2118 if (smu->dc_controlled_by_gpio) 2119 return 0; 2120 2121 mutex_lock(&smu->mutex); 2122 ret = smu_set_power_source(smu, 2123 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2124 SMU_POWER_SOURCE_DC); 2125 if (ret) 2126 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2127 smu->adev->pm.ac_power ? "AC" : "DC"); 2128 mutex_unlock(&smu->mutex); 2129 2130 return ret; 2131 } 2132 2133 const struct amd_ip_funcs smu_ip_funcs = { 2134 .name = "smu", 2135 .early_init = smu_early_init, 2136 .late_init = smu_late_init, 2137 .sw_init = smu_sw_init, 2138 .sw_fini = smu_sw_fini, 2139 .hw_init = smu_hw_init, 2140 .hw_fini = smu_hw_fini, 2141 .suspend = smu_suspend, 2142 .resume = smu_resume, 2143 .is_idle = NULL, 2144 .check_soft_reset = NULL, 2145 .wait_for_idle = NULL, 2146 .soft_reset = NULL, 2147 .set_clockgating_state = smu_set_clockgating_state, 2148 .set_powergating_state = smu_set_powergating_state, 2149 .enable_umd_pstate = smu_enable_umd_pstate, 2150 }; 2151 2152 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 2153 { 2154 .type = AMD_IP_BLOCK_TYPE_SMC, 2155 .major = 11, 2156 .minor = 0, 2157 .rev = 0, 2158 .funcs = &smu_ip_funcs, 2159 }; 2160 2161 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 2162 { 2163 .type = AMD_IP_BLOCK_TYPE_SMC, 2164 .major = 12, 2165 .minor = 0, 2166 .rev = 0, 2167 .funcs = &smu_ip_funcs, 2168 }; 2169 2170 const struct amdgpu_ip_block_version smu_v13_0_ip_block = 2171 { 2172 .type = AMD_IP_BLOCK_TYPE_SMC, 2173 .major = 13, 2174 .minor = 0, 2175 .rev = 0, 2176 .funcs = &smu_ip_funcs, 2177 }; 2178 2179 static int smu_load_microcode(void *handle) 2180 { 2181 struct smu_context *smu = handle; 2182 struct amdgpu_device *adev = smu->adev; 2183 int ret = 0; 2184 2185 if (!smu->pm_enabled) 2186 return -EOPNOTSUPP; 2187 2188 /* This should be used for non PSP loading */ 2189 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2190 return 0; 2191 2192 if (smu->ppt_funcs->load_microcode) { 2193 ret = smu->ppt_funcs->load_microcode(smu); 2194 if (ret) { 2195 dev_err(adev->dev, "Load microcode failed\n"); 2196 return ret; 2197 } 2198 } 2199 2200 if (smu->ppt_funcs->check_fw_status) { 2201 ret = smu->ppt_funcs->check_fw_status(smu); 2202 if (ret) { 2203 dev_err(adev->dev, "SMC is not ready\n"); 2204 return ret; 2205 } 2206 } 2207 2208 return ret; 2209 } 2210 2211 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2212 { 2213 int ret = 0; 2214 2215 mutex_lock(&smu->mutex); 2216 2217 if (smu->ppt_funcs->set_gfx_cgpg) 2218 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2219 2220 mutex_unlock(&smu->mutex); 2221 2222 return ret; 2223 } 2224 2225 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2226 { 2227 struct smu_context *smu = handle; 2228 int ret = 0; 2229 2230 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2231 return -EOPNOTSUPP; 2232 2233 mutex_lock(&smu->mutex); 2234 2235 if (smu->ppt_funcs->set_fan_speed_rpm) { 2236 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2237 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2238 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2239 smu->user_dpm_profile.fan_speed_rpm = speed; 2240 2241 /* Override custom PWM setting as they cannot co-exist */ 2242 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2243 smu->user_dpm_profile.fan_speed_pwm = 0; 2244 } 2245 } 2246 2247 mutex_unlock(&smu->mutex); 2248 2249 return ret; 2250 } 2251 2252 /** 2253 * smu_get_power_limit - Request one of the SMU Power Limits 2254 * 2255 * @handle: pointer to smu context 2256 * @limit: requested limit is written back to this variable 2257 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2258 * @pp_power_type: &pp_power_type type of power 2259 * Return: 0 on success, <0 on error 2260 * 2261 */ 2262 int smu_get_power_limit(void *handle, 2263 uint32_t *limit, 2264 enum pp_power_limit_level pp_limit_level, 2265 enum pp_power_type pp_power_type) 2266 { 2267 struct smu_context *smu = handle; 2268 struct amdgpu_device *adev = smu->adev; 2269 enum smu_ppt_limit_level limit_level; 2270 uint32_t limit_type; 2271 int ret = 0; 2272 2273 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2274 return -EOPNOTSUPP; 2275 2276 switch(pp_power_type) { 2277 case PP_PWR_TYPE_SUSTAINED: 2278 limit_type = SMU_DEFAULT_PPT_LIMIT; 2279 break; 2280 case PP_PWR_TYPE_FAST: 2281 limit_type = SMU_FAST_PPT_LIMIT; 2282 break; 2283 default: 2284 return -EOPNOTSUPP; 2285 break; 2286 } 2287 2288 switch(pp_limit_level){ 2289 case PP_PWR_LIMIT_CURRENT: 2290 limit_level = SMU_PPT_LIMIT_CURRENT; 2291 break; 2292 case PP_PWR_LIMIT_DEFAULT: 2293 limit_level = SMU_PPT_LIMIT_DEFAULT; 2294 break; 2295 case PP_PWR_LIMIT_MAX: 2296 limit_level = SMU_PPT_LIMIT_MAX; 2297 break; 2298 case PP_PWR_LIMIT_MIN: 2299 default: 2300 return -EOPNOTSUPP; 2301 break; 2302 } 2303 2304 mutex_lock(&smu->mutex); 2305 2306 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2307 if (smu->ppt_funcs->get_ppt_limit) 2308 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2309 } else { 2310 switch (limit_level) { 2311 case SMU_PPT_LIMIT_CURRENT: 2312 switch (adev->ip_versions[MP1_HWIP][0]) { 2313 case IP_VERSION(13, 0, 2): 2314 case IP_VERSION(11, 0, 7): 2315 case IP_VERSION(11, 0, 11): 2316 case IP_VERSION(11, 0, 12): 2317 case IP_VERSION(11, 0, 13): 2318 ret = smu_get_asic_power_limits(smu, 2319 &smu->current_power_limit, 2320 NULL, 2321 NULL); 2322 break; 2323 default: 2324 break; 2325 } 2326 *limit = smu->current_power_limit; 2327 break; 2328 case SMU_PPT_LIMIT_DEFAULT: 2329 *limit = smu->default_power_limit; 2330 break; 2331 case SMU_PPT_LIMIT_MAX: 2332 *limit = smu->max_power_limit; 2333 break; 2334 default: 2335 break; 2336 } 2337 } 2338 2339 mutex_unlock(&smu->mutex); 2340 2341 return ret; 2342 } 2343 2344 static int smu_set_power_limit(void *handle, uint32_t limit) 2345 { 2346 struct smu_context *smu = handle; 2347 uint32_t limit_type = limit >> 24; 2348 int ret = 0; 2349 2350 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2351 return -EOPNOTSUPP; 2352 2353 mutex_lock(&smu->mutex); 2354 2355 limit &= (1<<24)-1; 2356 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2357 if (smu->ppt_funcs->set_power_limit) { 2358 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2359 goto out; 2360 } 2361 2362 if (limit > smu->max_power_limit) { 2363 dev_err(smu->adev->dev, 2364 "New power limit (%d) is over the max allowed %d\n", 2365 limit, smu->max_power_limit); 2366 ret = -EINVAL; 2367 goto out; 2368 } 2369 2370 if (!limit) 2371 limit = smu->current_power_limit; 2372 2373 if (smu->ppt_funcs->set_power_limit) { 2374 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2375 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2376 smu->user_dpm_profile.power_limit = limit; 2377 } 2378 2379 out: 2380 mutex_unlock(&smu->mutex); 2381 2382 return ret; 2383 } 2384 2385 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2386 { 2387 int ret = 0; 2388 2389 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2390 return -EOPNOTSUPP; 2391 2392 mutex_lock(&smu->mutex); 2393 2394 if (smu->ppt_funcs->print_clk_levels) 2395 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2396 2397 mutex_unlock(&smu->mutex); 2398 2399 return ret; 2400 } 2401 2402 static int smu_print_ppclk_levels(void *handle, 2403 enum pp_clock_type type, 2404 char *buf) 2405 { 2406 struct smu_context *smu = handle; 2407 enum smu_clk_type clk_type; 2408 2409 switch (type) { 2410 case PP_SCLK: 2411 clk_type = SMU_SCLK; break; 2412 case PP_MCLK: 2413 clk_type = SMU_MCLK; break; 2414 case PP_PCIE: 2415 clk_type = SMU_PCIE; break; 2416 case PP_SOCCLK: 2417 clk_type = SMU_SOCCLK; break; 2418 case PP_FCLK: 2419 clk_type = SMU_FCLK; break; 2420 case PP_DCEFCLK: 2421 clk_type = SMU_DCEFCLK; break; 2422 case PP_VCLK: 2423 clk_type = SMU_VCLK; break; 2424 case PP_DCLK: 2425 clk_type = SMU_DCLK; break; 2426 case OD_SCLK: 2427 clk_type = SMU_OD_SCLK; break; 2428 case OD_MCLK: 2429 clk_type = SMU_OD_MCLK; break; 2430 case OD_VDDC_CURVE: 2431 clk_type = SMU_OD_VDDC_CURVE; break; 2432 case OD_RANGE: 2433 clk_type = SMU_OD_RANGE; break; 2434 case OD_VDDGFX_OFFSET: 2435 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2436 case OD_CCLK: 2437 clk_type = SMU_OD_CCLK; break; 2438 default: 2439 return -EINVAL; 2440 } 2441 2442 return smu_print_smuclk_levels(smu, clk_type, buf); 2443 } 2444 2445 static int smu_od_edit_dpm_table(void *handle, 2446 enum PP_OD_DPM_TABLE_COMMAND type, 2447 long *input, uint32_t size) 2448 { 2449 struct smu_context *smu = handle; 2450 int ret = 0; 2451 2452 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2453 return -EOPNOTSUPP; 2454 2455 mutex_lock(&smu->mutex); 2456 2457 if (smu->ppt_funcs->od_edit_dpm_table) { 2458 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2459 } 2460 2461 mutex_unlock(&smu->mutex); 2462 2463 return ret; 2464 } 2465 2466 static int smu_read_sensor(void *handle, 2467 int sensor, 2468 void *data, 2469 int *size_arg) 2470 { 2471 struct smu_context *smu = handle; 2472 struct smu_umd_pstate_table *pstate_table = 2473 &smu->pstate_table; 2474 int ret = 0; 2475 uint32_t *size, size_val; 2476 2477 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2478 return -EOPNOTSUPP; 2479 2480 if (!data || !size_arg) 2481 return -EINVAL; 2482 2483 size_val = *size_arg; 2484 size = &size_val; 2485 2486 mutex_lock(&smu->mutex); 2487 2488 if (smu->ppt_funcs->read_sensor) 2489 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2490 goto unlock; 2491 2492 switch (sensor) { 2493 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2494 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2495 *size = 4; 2496 break; 2497 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2498 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2499 *size = 4; 2500 break; 2501 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2502 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2); 2503 *size = 8; 2504 break; 2505 case AMDGPU_PP_SENSOR_UVD_POWER: 2506 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2507 *size = 4; 2508 break; 2509 case AMDGPU_PP_SENSOR_VCE_POWER: 2510 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2511 *size = 4; 2512 break; 2513 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2514 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2515 *size = 4; 2516 break; 2517 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2518 *(uint32_t *)data = 0; 2519 *size = 4; 2520 break; 2521 default: 2522 *size = 0; 2523 ret = -EOPNOTSUPP; 2524 break; 2525 } 2526 2527 unlock: 2528 mutex_unlock(&smu->mutex); 2529 2530 // assign uint32_t to int 2531 *size_arg = size_val; 2532 2533 return ret; 2534 } 2535 2536 static int smu_get_power_profile_mode(void *handle, char *buf) 2537 { 2538 struct smu_context *smu = handle; 2539 int ret = 0; 2540 2541 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2542 !smu->ppt_funcs->get_power_profile_mode) 2543 return -EOPNOTSUPP; 2544 if (!buf) 2545 return -EINVAL; 2546 2547 mutex_lock(&smu->mutex); 2548 2549 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf); 2550 2551 mutex_unlock(&smu->mutex); 2552 2553 return ret; 2554 } 2555 2556 static int smu_set_power_profile_mode(void *handle, 2557 long *param, 2558 uint32_t param_size) 2559 { 2560 struct smu_context *smu = handle; 2561 int ret = 0; 2562 2563 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2564 !smu->ppt_funcs->set_power_profile_mode) 2565 return -EOPNOTSUPP; 2566 2567 mutex_lock(&smu->mutex); 2568 2569 smu_bump_power_profile_mode(smu, param, param_size); 2570 2571 mutex_unlock(&smu->mutex); 2572 2573 return ret; 2574 } 2575 2576 2577 static u32 smu_get_fan_control_mode(void *handle) 2578 { 2579 struct smu_context *smu = handle; 2580 u32 ret = 0; 2581 2582 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2583 return AMD_FAN_CTRL_NONE; 2584 2585 mutex_lock(&smu->mutex); 2586 2587 if (smu->ppt_funcs->get_fan_control_mode) 2588 ret = smu->ppt_funcs->get_fan_control_mode(smu); 2589 2590 mutex_unlock(&smu->mutex); 2591 2592 return ret; 2593 } 2594 2595 static int smu_set_fan_control_mode(struct smu_context *smu, int value) 2596 { 2597 int ret = 0; 2598 2599 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2600 return -EOPNOTSUPP; 2601 2602 mutex_lock(&smu->mutex); 2603 2604 if (smu->ppt_funcs->set_fan_control_mode) { 2605 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2606 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2607 smu->user_dpm_profile.fan_mode = value; 2608 } 2609 2610 mutex_unlock(&smu->mutex); 2611 2612 /* reset user dpm fan speed */ 2613 if (!ret && value != AMD_FAN_CTRL_MANUAL && 2614 !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2615 smu->user_dpm_profile.fan_speed_pwm = 0; 2616 smu->user_dpm_profile.fan_speed_rpm = 0; 2617 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 2618 } 2619 2620 return ret; 2621 } 2622 2623 static void smu_pp_set_fan_control_mode(void *handle, u32 value) 2624 { 2625 struct smu_context *smu = handle; 2626 2627 smu_set_fan_control_mode(smu, value); 2628 } 2629 2630 2631 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 2632 { 2633 struct smu_context *smu = handle; 2634 int ret = 0; 2635 2636 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2637 return -EOPNOTSUPP; 2638 2639 mutex_lock(&smu->mutex); 2640 2641 if (smu->ppt_funcs->get_fan_speed_pwm) 2642 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 2643 2644 mutex_unlock(&smu->mutex); 2645 2646 return ret; 2647 } 2648 2649 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 2650 { 2651 struct smu_context *smu = handle; 2652 int ret = 0; 2653 2654 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2655 return -EOPNOTSUPP; 2656 2657 mutex_lock(&smu->mutex); 2658 2659 if (smu->ppt_funcs->set_fan_speed_pwm) { 2660 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 2661 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2662 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 2663 smu->user_dpm_profile.fan_speed_pwm = speed; 2664 2665 /* Override custom RPM setting as they cannot co-exist */ 2666 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 2667 smu->user_dpm_profile.fan_speed_rpm = 0; 2668 } 2669 } 2670 2671 mutex_unlock(&smu->mutex); 2672 2673 return ret; 2674 } 2675 2676 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2677 { 2678 struct smu_context *smu = handle; 2679 int ret = 0; 2680 2681 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2682 return -EOPNOTSUPP; 2683 2684 mutex_lock(&smu->mutex); 2685 2686 if (smu->ppt_funcs->get_fan_speed_rpm) 2687 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 2688 2689 mutex_unlock(&smu->mutex); 2690 2691 return ret; 2692 } 2693 2694 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 2695 { 2696 struct smu_context *smu = handle; 2697 int ret = 0; 2698 2699 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2700 return -EOPNOTSUPP; 2701 2702 mutex_lock(&smu->mutex); 2703 2704 ret = smu_set_min_dcef_deep_sleep(smu, clk); 2705 2706 mutex_unlock(&smu->mutex); 2707 2708 return ret; 2709 } 2710 2711 static int smu_get_clock_by_type_with_latency(void *handle, 2712 enum amd_pp_clock_type type, 2713 struct pp_clock_levels_with_latency *clocks) 2714 { 2715 struct smu_context *smu = handle; 2716 enum smu_clk_type clk_type; 2717 int ret = 0; 2718 2719 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2720 return -EOPNOTSUPP; 2721 2722 mutex_lock(&smu->mutex); 2723 2724 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 2725 switch (type) { 2726 case amd_pp_sys_clock: 2727 clk_type = SMU_GFXCLK; 2728 break; 2729 case amd_pp_mem_clock: 2730 clk_type = SMU_MCLK; 2731 break; 2732 case amd_pp_dcef_clock: 2733 clk_type = SMU_DCEFCLK; 2734 break; 2735 case amd_pp_disp_clock: 2736 clk_type = SMU_DISPCLK; 2737 break; 2738 default: 2739 dev_err(smu->adev->dev, "Invalid clock type!\n"); 2740 mutex_unlock(&smu->mutex); 2741 return -EINVAL; 2742 } 2743 2744 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2745 } 2746 2747 mutex_unlock(&smu->mutex); 2748 2749 return ret; 2750 } 2751 2752 static int smu_display_clock_voltage_request(void *handle, 2753 struct pp_display_clock_request *clock_req) 2754 { 2755 struct smu_context *smu = handle; 2756 int ret = 0; 2757 2758 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2759 return -EOPNOTSUPP; 2760 2761 mutex_lock(&smu->mutex); 2762 2763 if (smu->ppt_funcs->display_clock_voltage_request) 2764 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2765 2766 mutex_unlock(&smu->mutex); 2767 2768 return ret; 2769 } 2770 2771 2772 static int smu_display_disable_memory_clock_switch(void *handle, 2773 bool disable_memory_clock_switch) 2774 { 2775 struct smu_context *smu = handle; 2776 int ret = -EINVAL; 2777 2778 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2779 return -EOPNOTSUPP; 2780 2781 mutex_lock(&smu->mutex); 2782 2783 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2784 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2785 2786 mutex_unlock(&smu->mutex); 2787 2788 return ret; 2789 } 2790 2791 static int smu_set_xgmi_pstate(void *handle, 2792 uint32_t pstate) 2793 { 2794 struct smu_context *smu = handle; 2795 int ret = 0; 2796 2797 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2798 return -EOPNOTSUPP; 2799 2800 mutex_lock(&smu->mutex); 2801 2802 if (smu->ppt_funcs->set_xgmi_pstate) 2803 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2804 2805 mutex_unlock(&smu->mutex); 2806 2807 if(ret) 2808 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2809 2810 return ret; 2811 } 2812 2813 static int smu_get_baco_capability(void *handle, bool *cap) 2814 { 2815 struct smu_context *smu = handle; 2816 int ret = 0; 2817 2818 *cap = false; 2819 2820 if (!smu->pm_enabled) 2821 return 0; 2822 2823 mutex_lock(&smu->mutex); 2824 2825 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2826 *cap = smu->ppt_funcs->baco_is_support(smu); 2827 2828 mutex_unlock(&smu->mutex); 2829 2830 return ret; 2831 } 2832 2833 static int smu_baco_set_state(void *handle, int state) 2834 { 2835 struct smu_context *smu = handle; 2836 int ret = 0; 2837 2838 if (!smu->pm_enabled) 2839 return -EOPNOTSUPP; 2840 2841 if (state == 0) { 2842 mutex_lock(&smu->mutex); 2843 2844 if (smu->ppt_funcs->baco_exit) 2845 ret = smu->ppt_funcs->baco_exit(smu); 2846 2847 mutex_unlock(&smu->mutex); 2848 } else if (state == 1) { 2849 mutex_lock(&smu->mutex); 2850 2851 if (smu->ppt_funcs->baco_enter) 2852 ret = smu->ppt_funcs->baco_enter(smu); 2853 2854 mutex_unlock(&smu->mutex); 2855 2856 } else { 2857 return -EINVAL; 2858 } 2859 2860 if (ret) 2861 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 2862 (state)?"enter":"exit"); 2863 2864 return ret; 2865 } 2866 2867 bool smu_mode1_reset_is_support(struct smu_context *smu) 2868 { 2869 bool ret = false; 2870 2871 if (!smu->pm_enabled) 2872 return false; 2873 2874 mutex_lock(&smu->mutex); 2875 2876 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2877 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2878 2879 mutex_unlock(&smu->mutex); 2880 2881 return ret; 2882 } 2883 2884 bool smu_mode2_reset_is_support(struct smu_context *smu) 2885 { 2886 bool ret = false; 2887 2888 if (!smu->pm_enabled) 2889 return false; 2890 2891 mutex_lock(&smu->mutex); 2892 2893 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 2894 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 2895 2896 mutex_unlock(&smu->mutex); 2897 2898 return ret; 2899 } 2900 2901 int smu_mode1_reset(struct smu_context *smu) 2902 { 2903 int ret = 0; 2904 2905 if (!smu->pm_enabled) 2906 return -EOPNOTSUPP; 2907 2908 mutex_lock(&smu->mutex); 2909 2910 if (smu->ppt_funcs->mode1_reset) 2911 ret = smu->ppt_funcs->mode1_reset(smu); 2912 2913 mutex_unlock(&smu->mutex); 2914 2915 return ret; 2916 } 2917 2918 static int smu_mode2_reset(void *handle) 2919 { 2920 struct smu_context *smu = handle; 2921 int ret = 0; 2922 2923 if (!smu->pm_enabled) 2924 return -EOPNOTSUPP; 2925 2926 mutex_lock(&smu->mutex); 2927 2928 if (smu->ppt_funcs->mode2_reset) 2929 ret = smu->ppt_funcs->mode2_reset(smu); 2930 2931 mutex_unlock(&smu->mutex); 2932 2933 if (ret) 2934 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2935 2936 return ret; 2937 } 2938 2939 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 2940 struct pp_smu_nv_clock_table *max_clocks) 2941 { 2942 struct smu_context *smu = handle; 2943 int ret = 0; 2944 2945 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2946 return -EOPNOTSUPP; 2947 2948 mutex_lock(&smu->mutex); 2949 2950 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2951 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2952 2953 mutex_unlock(&smu->mutex); 2954 2955 return ret; 2956 } 2957 2958 static int smu_get_uclk_dpm_states(void *handle, 2959 unsigned int *clock_values_in_khz, 2960 unsigned int *num_states) 2961 { 2962 struct smu_context *smu = handle; 2963 int ret = 0; 2964 2965 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2966 return -EOPNOTSUPP; 2967 2968 mutex_lock(&smu->mutex); 2969 2970 if (smu->ppt_funcs->get_uclk_dpm_states) 2971 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2972 2973 mutex_unlock(&smu->mutex); 2974 2975 return ret; 2976 } 2977 2978 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 2979 { 2980 struct smu_context *smu = handle; 2981 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2982 2983 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2984 return -EOPNOTSUPP; 2985 2986 mutex_lock(&smu->mutex); 2987 2988 if (smu->ppt_funcs->get_current_power_state) 2989 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2990 2991 mutex_unlock(&smu->mutex); 2992 2993 return pm_state; 2994 } 2995 2996 static int smu_get_dpm_clock_table(void *handle, 2997 struct dpm_clocks *clock_table) 2998 { 2999 struct smu_context *smu = handle; 3000 int ret = 0; 3001 3002 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3003 return -EOPNOTSUPP; 3004 3005 mutex_lock(&smu->mutex); 3006 3007 if (smu->ppt_funcs->get_dpm_clock_table) 3008 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3009 3010 mutex_unlock(&smu->mutex); 3011 3012 return ret; 3013 } 3014 3015 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3016 { 3017 struct smu_context *smu = handle; 3018 ssize_t size; 3019 3020 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3021 return -EOPNOTSUPP; 3022 3023 if (!smu->ppt_funcs->get_gpu_metrics) 3024 return -EOPNOTSUPP; 3025 3026 mutex_lock(&smu->mutex); 3027 3028 size = smu->ppt_funcs->get_gpu_metrics(smu, table); 3029 3030 mutex_unlock(&smu->mutex); 3031 3032 return size; 3033 } 3034 3035 static int smu_enable_mgpu_fan_boost(void *handle) 3036 { 3037 struct smu_context *smu = handle; 3038 int ret = 0; 3039 3040 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3041 return -EOPNOTSUPP; 3042 3043 mutex_lock(&smu->mutex); 3044 3045 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3046 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3047 3048 mutex_unlock(&smu->mutex); 3049 3050 return ret; 3051 } 3052 3053 static int smu_gfx_state_change_set(void *handle, 3054 uint32_t state) 3055 { 3056 struct smu_context *smu = handle; 3057 int ret = 0; 3058 3059 mutex_lock(&smu->mutex); 3060 if (smu->ppt_funcs->gfx_state_change_set) 3061 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3062 mutex_unlock(&smu->mutex); 3063 3064 return ret; 3065 } 3066 3067 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3068 { 3069 int ret = 0; 3070 3071 mutex_lock(&smu->mutex); 3072 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3073 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3074 mutex_unlock(&smu->mutex); 3075 3076 return ret; 3077 } 3078 3079 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3080 { 3081 int ret = -EOPNOTSUPP; 3082 3083 mutex_lock(&smu->mutex); 3084 if (smu->ppt_funcs && 3085 smu->ppt_funcs->get_ecc_info) 3086 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3087 mutex_unlock(&smu->mutex); 3088 3089 return ret; 3090 3091 } 3092 3093 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3094 { 3095 struct smu_context *smu = handle; 3096 struct smu_table_context *smu_table = &smu->smu_table; 3097 struct smu_table *memory_pool = &smu_table->memory_pool; 3098 3099 if (!addr || !size) 3100 return -EINVAL; 3101 3102 *addr = NULL; 3103 *size = 0; 3104 mutex_lock(&smu->mutex); 3105 if (memory_pool->bo) { 3106 *addr = memory_pool->cpu_addr; 3107 *size = memory_pool->size; 3108 } 3109 mutex_unlock(&smu->mutex); 3110 3111 return 0; 3112 } 3113 3114 static const struct amd_pm_funcs swsmu_pm_funcs = { 3115 /* export for sysfs */ 3116 .set_fan_control_mode = smu_pp_set_fan_control_mode, 3117 .get_fan_control_mode = smu_get_fan_control_mode, 3118 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3119 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3120 .force_clock_level = smu_force_ppclk_levels, 3121 .print_clock_levels = smu_print_ppclk_levels, 3122 .force_performance_level = smu_force_performance_level, 3123 .read_sensor = smu_read_sensor, 3124 .get_performance_level = smu_get_performance_level, 3125 .get_current_power_state = smu_get_current_power_state, 3126 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3127 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3128 .get_pp_num_states = smu_get_power_num_states, 3129 .get_pp_table = smu_sys_get_pp_table, 3130 .set_pp_table = smu_sys_set_pp_table, 3131 .switch_power_profile = smu_switch_power_profile, 3132 /* export to amdgpu */ 3133 .dispatch_tasks = smu_handle_dpm_task, 3134 .load_firmware = smu_load_microcode, 3135 .set_powergating_by_smu = smu_dpm_set_power_gate, 3136 .set_power_limit = smu_set_power_limit, 3137 .get_power_limit = smu_get_power_limit, 3138 .get_power_profile_mode = smu_get_power_profile_mode, 3139 .set_power_profile_mode = smu_set_power_profile_mode, 3140 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3141 .set_mp1_state = smu_set_mp1_state, 3142 .gfx_state_change_set = smu_gfx_state_change_set, 3143 /* export to DC */ 3144 .get_sclk = smu_get_sclk, 3145 .get_mclk = smu_get_mclk, 3146 .display_configuration_change = smu_display_configuration_change, 3147 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3148 .display_clock_voltage_request = smu_display_clock_voltage_request, 3149 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3150 .set_active_display_count = smu_set_display_count, 3151 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3152 .get_asic_baco_capability = smu_get_baco_capability, 3153 .set_asic_baco_state = smu_baco_set_state, 3154 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3155 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3156 .asic_reset_mode_2 = smu_mode2_reset, 3157 .set_df_cstate = smu_set_df_cstate, 3158 .set_xgmi_pstate = smu_set_xgmi_pstate, 3159 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3160 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3161 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3162 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3163 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3164 .get_dpm_clock_table = smu_get_dpm_clock_table, 3165 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3166 }; 3167 3168 int smu_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event, 3169 uint64_t event_arg) 3170 { 3171 int ret = -EINVAL; 3172 struct smu_context *smu = &adev->smu; 3173 3174 if (smu->ppt_funcs->wait_for_event) { 3175 mutex_lock(&smu->mutex); 3176 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3177 mutex_unlock(&smu->mutex); 3178 } 3179 3180 return ret; 3181 } 3182 3183 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3184 { 3185 3186 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3187 return -EOPNOTSUPP; 3188 3189 /* Confirm the buffer allocated is of correct size */ 3190 if (size != smu->stb_context.stb_buf_size) 3191 return -EINVAL; 3192 3193 /* 3194 * No need to lock smu mutex as we access STB directly through MMIO 3195 * and not going through SMU messaging route (for now at least). 3196 * For registers access rely on implementation internal locking. 3197 */ 3198 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3199 } 3200 3201 #if defined(CONFIG_DEBUG_FS) 3202 3203 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3204 { 3205 struct amdgpu_device *adev = filp->f_inode->i_private; 3206 struct smu_context *smu = &adev->smu; 3207 unsigned char *buf; 3208 int r; 3209 3210 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3211 if (!buf) 3212 return -ENOMEM; 3213 3214 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3215 if (r) 3216 goto out; 3217 3218 filp->private_data = buf; 3219 3220 return 0; 3221 3222 out: 3223 kvfree(buf); 3224 return r; 3225 } 3226 3227 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3228 loff_t *pos) 3229 { 3230 struct amdgpu_device *adev = filp->f_inode->i_private; 3231 struct smu_context *smu = &adev->smu; 3232 3233 3234 if (!filp->private_data) 3235 return -EINVAL; 3236 3237 return simple_read_from_buffer(buf, 3238 size, 3239 pos, filp->private_data, 3240 smu->stb_context.stb_buf_size); 3241 } 3242 3243 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3244 { 3245 kvfree(filp->private_data); 3246 filp->private_data = NULL; 3247 3248 return 0; 3249 } 3250 3251 /* 3252 * We have to define not only read method but also 3253 * open and release because .read takes up to PAGE_SIZE 3254 * data each time so and so is invoked multiple times. 3255 * We allocate the STB buffer in .open and release it 3256 * in .release 3257 */ 3258 static const struct file_operations smu_stb_debugfs_fops = { 3259 .owner = THIS_MODULE, 3260 .open = smu_stb_debugfs_open, 3261 .read = smu_stb_debugfs_read, 3262 .release = smu_stb_debugfs_release, 3263 .llseek = default_llseek, 3264 }; 3265 3266 #endif 3267 3268 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3269 { 3270 #if defined(CONFIG_DEBUG_FS) 3271 3272 struct smu_context *smu = &adev->smu; 3273 3274 if (!smu->stb_context.stb_buf_size) 3275 return; 3276 3277 debugfs_create_file_size("amdgpu_smu_stb_dump", 3278 S_IRUSR, 3279 adev_to_drm(adev)->primary->debugfs_root, 3280 adev, 3281 &smu_stb_debugfs_fops, 3282 smu->stb_context.stb_buf_size); 3283 #endif 3284 3285 } 3286