1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "aldebaran_ppt.h" 38 #include "yellow_carp_ppt.h" 39 #include "cyan_skillfish_ppt.h" 40 #include "smu_v13_0_0_ppt.h" 41 #include "smu_v13_0_4_ppt.h" 42 #include "smu_v13_0_5_ppt.h" 43 #include "smu_v13_0_7_ppt.h" 44 #include "amd_pcie.h" 45 46 /* 47 * DO NOT use these for err/warn/info/debug messages. 48 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 49 * They are more MGPU friendly. 50 */ 51 #undef pr_err 52 #undef pr_warn 53 #undef pr_info 54 #undef pr_debug 55 56 static const struct amd_pm_funcs swsmu_pm_funcs; 57 static int smu_force_smuclk_levels(struct smu_context *smu, 58 enum smu_clk_type clk_type, 59 uint32_t mask); 60 static int smu_handle_task(struct smu_context *smu, 61 enum amd_dpm_forced_level level, 62 enum amd_pp_task task_id); 63 static int smu_reset(struct smu_context *smu); 64 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 65 static int smu_set_fan_control_mode(void *handle, u32 value); 66 static int smu_set_power_limit(void *handle, uint32_t limit); 67 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 68 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 69 70 static int smu_sys_get_pp_feature_mask(void *handle, 71 char *buf) 72 { 73 struct smu_context *smu = handle; 74 75 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 76 return -EOPNOTSUPP; 77 78 return smu_get_pp_feature_mask(smu, buf); 79 } 80 81 static int smu_sys_set_pp_feature_mask(void *handle, 82 uint64_t new_mask) 83 { 84 struct smu_context *smu = handle; 85 86 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 87 return -EOPNOTSUPP; 88 89 return smu_set_pp_feature_mask(smu, new_mask); 90 } 91 92 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 93 { 94 if (!smu->ppt_funcs->get_gfx_off_status) 95 return -EINVAL; 96 97 *value = smu_get_gfx_off_status(smu); 98 99 return 0; 100 } 101 102 int smu_set_soft_freq_range(struct smu_context *smu, 103 enum smu_clk_type clk_type, 104 uint32_t min, 105 uint32_t max) 106 { 107 int ret = 0; 108 109 if (smu->ppt_funcs->set_soft_freq_limited_range) 110 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 111 clk_type, 112 min, 113 max); 114 115 return ret; 116 } 117 118 int smu_get_dpm_freq_range(struct smu_context *smu, 119 enum smu_clk_type clk_type, 120 uint32_t *min, 121 uint32_t *max) 122 { 123 int ret = -ENOTSUPP; 124 125 if (!min && !max) 126 return -EINVAL; 127 128 if (smu->ppt_funcs->get_dpm_ultimate_freq) 129 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 130 clk_type, 131 min, 132 max); 133 134 return ret; 135 } 136 137 static u32 smu_get_mclk(void *handle, bool low) 138 { 139 struct smu_context *smu = handle; 140 uint32_t clk_freq; 141 int ret = 0; 142 143 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 144 low ? &clk_freq : NULL, 145 !low ? &clk_freq : NULL); 146 if (ret) 147 return 0; 148 return clk_freq * 100; 149 } 150 151 static u32 smu_get_sclk(void *handle, bool low) 152 { 153 struct smu_context *smu = handle; 154 uint32_t clk_freq; 155 int ret = 0; 156 157 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 158 low ? &clk_freq : NULL, 159 !low ? &clk_freq : NULL); 160 if (ret) 161 return 0; 162 return clk_freq * 100; 163 } 164 165 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 166 bool enable) 167 { 168 struct smu_power_context *smu_power = &smu->smu_power; 169 struct smu_power_gate *power_gate = &smu_power->power_gate; 170 int ret = 0; 171 172 if (!smu->ppt_funcs->dpm_set_vcn_enable) 173 return 0; 174 175 if (atomic_read(&power_gate->vcn_gated) ^ enable) 176 return 0; 177 178 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 179 if (!ret) 180 atomic_set(&power_gate->vcn_gated, !enable); 181 182 return ret; 183 } 184 185 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 186 bool enable) 187 { 188 struct smu_power_context *smu_power = &smu->smu_power; 189 struct smu_power_gate *power_gate = &smu_power->power_gate; 190 int ret = 0; 191 192 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 193 return 0; 194 195 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 196 return 0; 197 198 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 199 if (!ret) 200 atomic_set(&power_gate->jpeg_gated, !enable); 201 202 return ret; 203 } 204 205 /** 206 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 207 * 208 * @handle: smu_context pointer 209 * @block_type: the IP block to power gate/ungate 210 * @gate: to power gate if true, ungate otherwise 211 * 212 * This API uses no smu->mutex lock protection due to: 213 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 214 * This is guarded to be race condition free by the caller. 215 * 2. Or get called on user setting request of power_dpm_force_performance_level. 216 * Under this case, the smu->mutex lock protection is already enforced on 217 * the parent API smu_force_performance_level of the call path. 218 */ 219 static int smu_dpm_set_power_gate(void *handle, 220 uint32_t block_type, 221 bool gate) 222 { 223 struct smu_context *smu = handle; 224 int ret = 0; 225 226 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 227 dev_WARN(smu->adev->dev, 228 "SMU uninitialized but power %s requested for %u!\n", 229 gate ? "gate" : "ungate", block_type); 230 return -EOPNOTSUPP; 231 } 232 233 switch (block_type) { 234 /* 235 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 236 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 237 */ 238 case AMD_IP_BLOCK_TYPE_UVD: 239 case AMD_IP_BLOCK_TYPE_VCN: 240 ret = smu_dpm_set_vcn_enable(smu, !gate); 241 if (ret) 242 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 243 gate ? "gate" : "ungate"); 244 break; 245 case AMD_IP_BLOCK_TYPE_GFX: 246 ret = smu_gfx_off_control(smu, gate); 247 if (ret) 248 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 249 gate ? "enable" : "disable"); 250 break; 251 case AMD_IP_BLOCK_TYPE_SDMA: 252 ret = smu_powergate_sdma(smu, gate); 253 if (ret) 254 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 255 gate ? "gate" : "ungate"); 256 break; 257 case AMD_IP_BLOCK_TYPE_JPEG: 258 ret = smu_dpm_set_jpeg_enable(smu, !gate); 259 if (ret) 260 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 261 gate ? "gate" : "ungate"); 262 break; 263 default: 264 dev_err(smu->adev->dev, "Unsupported block type!\n"); 265 return -EINVAL; 266 } 267 268 return ret; 269 } 270 271 /** 272 * smu_set_user_clk_dependencies - set user profile clock dependencies 273 * 274 * @smu: smu_context pointer 275 * @clk: enum smu_clk_type type 276 * 277 * Enable/Disable the clock dependency for the @clk type. 278 */ 279 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 280 { 281 if (smu->adev->in_suspend) 282 return; 283 284 if (clk == SMU_MCLK) { 285 smu->user_dpm_profile.clk_dependency = 0; 286 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 287 } else if (clk == SMU_FCLK) { 288 /* MCLK takes precedence over FCLK */ 289 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 290 return; 291 292 smu->user_dpm_profile.clk_dependency = 0; 293 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 294 } else if (clk == SMU_SOCCLK) { 295 /* MCLK takes precedence over SOCCLK */ 296 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 297 return; 298 299 smu->user_dpm_profile.clk_dependency = 0; 300 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 301 } else 302 /* Add clk dependencies here, if any */ 303 return; 304 } 305 306 /** 307 * smu_restore_dpm_user_profile - reinstate user dpm profile 308 * 309 * @smu: smu_context pointer 310 * 311 * Restore the saved user power configurations include power limit, 312 * clock frequencies, fan control mode and fan speed. 313 */ 314 static void smu_restore_dpm_user_profile(struct smu_context *smu) 315 { 316 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 317 int ret = 0; 318 319 if (!smu->adev->in_suspend) 320 return; 321 322 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 323 return; 324 325 /* Enable restore flag */ 326 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 327 328 /* set the user dpm power limit */ 329 if (smu->user_dpm_profile.power_limit) { 330 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 331 if (ret) 332 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 333 } 334 335 /* set the user dpm clock configurations */ 336 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 337 enum smu_clk_type clk_type; 338 339 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 340 /* 341 * Iterate over smu clk type and force the saved user clk 342 * configs, skip if clock dependency is enabled 343 */ 344 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 345 smu->user_dpm_profile.clk_mask[clk_type]) { 346 ret = smu_force_smuclk_levels(smu, clk_type, 347 smu->user_dpm_profile.clk_mask[clk_type]); 348 if (ret) 349 dev_err(smu->adev->dev, 350 "Failed to set clock type = %d\n", clk_type); 351 } 352 } 353 } 354 355 /* set the user dpm fan configurations */ 356 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 357 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 358 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 359 if (ret != -EOPNOTSUPP) { 360 smu->user_dpm_profile.fan_speed_pwm = 0; 361 smu->user_dpm_profile.fan_speed_rpm = 0; 362 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 363 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 364 } 365 366 if (smu->user_dpm_profile.fan_speed_pwm) { 367 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 368 if (ret != -EOPNOTSUPP) 369 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 370 } 371 372 if (smu->user_dpm_profile.fan_speed_rpm) { 373 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 374 if (ret != -EOPNOTSUPP) 375 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 376 } 377 } 378 379 /* Restore user customized OD settings */ 380 if (smu->user_dpm_profile.user_od) { 381 if (smu->ppt_funcs->restore_user_od_settings) { 382 ret = smu->ppt_funcs->restore_user_od_settings(smu); 383 if (ret) 384 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 385 } 386 } 387 388 /* Disable restore flag */ 389 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 390 } 391 392 static int smu_get_power_num_states(void *handle, 393 struct pp_states_info *state_info) 394 { 395 if (!state_info) 396 return -EINVAL; 397 398 /* not support power state */ 399 memset(state_info, 0, sizeof(struct pp_states_info)); 400 state_info->nums = 1; 401 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 402 403 return 0; 404 } 405 406 bool is_support_sw_smu(struct amdgpu_device *adev) 407 { 408 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 409 if (adev->asic_type == CHIP_VEGA20) 410 return false; 411 412 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0)) 413 return true; 414 415 return false; 416 } 417 418 bool is_support_cclk_dpm(struct amdgpu_device *adev) 419 { 420 struct smu_context *smu = adev->powerplay.pp_handle; 421 422 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 423 return false; 424 425 return true; 426 } 427 428 429 static int smu_sys_get_pp_table(void *handle, 430 char **table) 431 { 432 struct smu_context *smu = handle; 433 struct smu_table_context *smu_table = &smu->smu_table; 434 435 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 436 return -EOPNOTSUPP; 437 438 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 439 return -EINVAL; 440 441 if (smu_table->hardcode_pptable) 442 *table = smu_table->hardcode_pptable; 443 else 444 *table = smu_table->power_play_table; 445 446 return smu_table->power_play_table_size; 447 } 448 449 static int smu_sys_set_pp_table(void *handle, 450 const char *buf, 451 size_t size) 452 { 453 struct smu_context *smu = handle; 454 struct smu_table_context *smu_table = &smu->smu_table; 455 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 456 int ret = 0; 457 458 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 459 return -EOPNOTSUPP; 460 461 if (header->usStructureSize != size) { 462 dev_err(smu->adev->dev, "pp table size not matched !\n"); 463 return -EIO; 464 } 465 466 if (!smu_table->hardcode_pptable) { 467 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 468 if (!smu_table->hardcode_pptable) 469 return -ENOMEM; 470 } 471 472 memcpy(smu_table->hardcode_pptable, buf, size); 473 smu_table->power_play_table = smu_table->hardcode_pptable; 474 smu_table->power_play_table_size = size; 475 476 /* 477 * Special hw_fini action(for Navi1x, the DPMs disablement will be 478 * skipped) may be needed for custom pptable uploading. 479 */ 480 smu->uploading_custom_pp_table = true; 481 482 ret = smu_reset(smu); 483 if (ret) 484 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 485 486 smu->uploading_custom_pp_table = false; 487 488 return ret; 489 } 490 491 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 492 { 493 struct smu_feature *feature = &smu->smu_feature; 494 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 495 int ret = 0; 496 497 /* 498 * With SCPM enabled, the allowed featuremasks setting(via 499 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 500 * That means there is no way to let PMFW knows the settings below. 501 * Thus, we just assume all the features are allowed under 502 * such scenario. 503 */ 504 if (smu->adev->scpm_enabled) { 505 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 506 return 0; 507 } 508 509 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 510 511 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 512 SMU_FEATURE_MAX/32); 513 if (ret) 514 return ret; 515 516 bitmap_or(feature->allowed, feature->allowed, 517 (unsigned long *)allowed_feature_mask, 518 feature->feature_num); 519 520 return ret; 521 } 522 523 static int smu_set_funcs(struct amdgpu_device *adev) 524 { 525 struct smu_context *smu = adev->powerplay.pp_handle; 526 527 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 528 smu->od_enabled = true; 529 530 switch (adev->ip_versions[MP1_HWIP][0]) { 531 case IP_VERSION(11, 0, 0): 532 case IP_VERSION(11, 0, 5): 533 case IP_VERSION(11, 0, 9): 534 navi10_set_ppt_funcs(smu); 535 break; 536 case IP_VERSION(11, 0, 7): 537 case IP_VERSION(11, 0, 11): 538 case IP_VERSION(11, 0, 12): 539 case IP_VERSION(11, 0, 13): 540 sienna_cichlid_set_ppt_funcs(smu); 541 break; 542 case IP_VERSION(12, 0, 0): 543 case IP_VERSION(12, 0, 1): 544 renoir_set_ppt_funcs(smu); 545 break; 546 case IP_VERSION(11, 5, 0): 547 vangogh_set_ppt_funcs(smu); 548 break; 549 case IP_VERSION(13, 0, 1): 550 case IP_VERSION(13, 0, 3): 551 case IP_VERSION(13, 0, 8): 552 yellow_carp_set_ppt_funcs(smu); 553 break; 554 case IP_VERSION(13, 0, 4): 555 smu_v13_0_4_set_ppt_funcs(smu); 556 break; 557 case IP_VERSION(13, 0, 5): 558 smu_v13_0_5_set_ppt_funcs(smu); 559 break; 560 case IP_VERSION(11, 0, 8): 561 cyan_skillfish_set_ppt_funcs(smu); 562 break; 563 case IP_VERSION(11, 0, 2): 564 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 565 arcturus_set_ppt_funcs(smu); 566 /* OD is not supported on Arcturus */ 567 smu->od_enabled =false; 568 break; 569 case IP_VERSION(13, 0, 2): 570 aldebaran_set_ppt_funcs(smu); 571 /* Enable pp_od_clk_voltage node */ 572 smu->od_enabled = true; 573 break; 574 case IP_VERSION(13, 0, 0): 575 smu_v13_0_0_set_ppt_funcs(smu); 576 break; 577 case IP_VERSION(13, 0, 7): 578 smu_v13_0_7_set_ppt_funcs(smu); 579 break; 580 default: 581 return -EINVAL; 582 } 583 584 return 0; 585 } 586 587 static int smu_early_init(void *handle) 588 { 589 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 590 struct smu_context *smu; 591 592 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 593 if (!smu) 594 return -ENOMEM; 595 596 smu->adev = adev; 597 smu->pm_enabled = !!amdgpu_dpm; 598 smu->is_apu = false; 599 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 600 smu->smu_baco.platform_support = false; 601 smu->user_dpm_profile.fan_mode = -1; 602 603 mutex_init(&smu->message_lock); 604 605 adev->powerplay.pp_handle = smu; 606 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 607 608 return smu_set_funcs(adev); 609 } 610 611 static int smu_set_default_dpm_table(struct smu_context *smu) 612 { 613 struct smu_power_context *smu_power = &smu->smu_power; 614 struct smu_power_gate *power_gate = &smu_power->power_gate; 615 int vcn_gate, jpeg_gate; 616 int ret = 0; 617 618 if (!smu->ppt_funcs->set_default_dpm_table) 619 return 0; 620 621 vcn_gate = atomic_read(&power_gate->vcn_gated); 622 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 623 624 ret = smu_dpm_set_vcn_enable(smu, true); 625 if (ret) 626 return ret; 627 628 ret = smu_dpm_set_jpeg_enable(smu, true); 629 if (ret) 630 goto err_out; 631 632 ret = smu->ppt_funcs->set_default_dpm_table(smu); 633 if (ret) 634 dev_err(smu->adev->dev, 635 "Failed to setup default dpm clock tables!\n"); 636 637 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 638 err_out: 639 smu_dpm_set_vcn_enable(smu, !vcn_gate); 640 return ret; 641 } 642 643 static int smu_apply_default_config_table_settings(struct smu_context *smu) 644 { 645 struct amdgpu_device *adev = smu->adev; 646 int ret = 0; 647 648 ret = smu_get_default_config_table_settings(smu, 649 &adev->pm.config_table); 650 if (ret) 651 return ret; 652 653 return smu_set_config_table(smu, &adev->pm.config_table); 654 } 655 656 static int smu_late_init(void *handle) 657 { 658 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 659 struct smu_context *smu = adev->powerplay.pp_handle; 660 int ret = 0; 661 662 smu_set_fine_grain_gfx_freq_parameters(smu); 663 664 if (!smu->pm_enabled) 665 return 0; 666 667 ret = smu_post_init(smu); 668 if (ret) { 669 dev_err(adev->dev, "Failed to post smu init!\n"); 670 return ret; 671 } 672 673 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || 674 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) 675 return 0; 676 677 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 678 ret = smu_set_default_od_settings(smu); 679 if (ret) { 680 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 681 return ret; 682 } 683 } 684 685 ret = smu_populate_umd_state_clk(smu); 686 if (ret) { 687 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 688 return ret; 689 } 690 691 ret = smu_get_asic_power_limits(smu, 692 &smu->current_power_limit, 693 &smu->default_power_limit, 694 &smu->max_power_limit); 695 if (ret) { 696 dev_err(adev->dev, "Failed to get asic power limits!\n"); 697 return ret; 698 } 699 700 if (!amdgpu_sriov_vf(adev)) 701 smu_get_unique_id(smu); 702 703 smu_get_fan_parameters(smu); 704 705 smu_handle_task(smu, 706 smu->smu_dpm.dpm_level, 707 AMD_PP_TASK_COMPLETE_INIT); 708 709 ret = smu_apply_default_config_table_settings(smu); 710 if (ret && (ret != -EOPNOTSUPP)) { 711 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 712 return ret; 713 } 714 715 smu_restore_dpm_user_profile(smu); 716 717 return 0; 718 } 719 720 static int smu_init_fb_allocations(struct smu_context *smu) 721 { 722 struct amdgpu_device *adev = smu->adev; 723 struct smu_table_context *smu_table = &smu->smu_table; 724 struct smu_table *tables = smu_table->tables; 725 struct smu_table *driver_table = &(smu_table->driver_table); 726 uint32_t max_table_size = 0; 727 int ret, i; 728 729 /* VRAM allocation for tool table */ 730 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 731 ret = amdgpu_bo_create_kernel(adev, 732 tables[SMU_TABLE_PMSTATUSLOG].size, 733 tables[SMU_TABLE_PMSTATUSLOG].align, 734 tables[SMU_TABLE_PMSTATUSLOG].domain, 735 &tables[SMU_TABLE_PMSTATUSLOG].bo, 736 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 737 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 738 if (ret) { 739 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 740 return ret; 741 } 742 } 743 744 /* VRAM allocation for driver table */ 745 for (i = 0; i < SMU_TABLE_COUNT; i++) { 746 if (tables[i].size == 0) 747 continue; 748 749 if (i == SMU_TABLE_PMSTATUSLOG) 750 continue; 751 752 if (max_table_size < tables[i].size) 753 max_table_size = tables[i].size; 754 } 755 756 driver_table->size = max_table_size; 757 driver_table->align = PAGE_SIZE; 758 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 759 760 ret = amdgpu_bo_create_kernel(adev, 761 driver_table->size, 762 driver_table->align, 763 driver_table->domain, 764 &driver_table->bo, 765 &driver_table->mc_address, 766 &driver_table->cpu_addr); 767 if (ret) { 768 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 769 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 770 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 771 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 772 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 773 } 774 775 return ret; 776 } 777 778 static int smu_fini_fb_allocations(struct smu_context *smu) 779 { 780 struct smu_table_context *smu_table = &smu->smu_table; 781 struct smu_table *tables = smu_table->tables; 782 struct smu_table *driver_table = &(smu_table->driver_table); 783 784 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 785 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 786 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 787 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 788 789 amdgpu_bo_free_kernel(&driver_table->bo, 790 &driver_table->mc_address, 791 &driver_table->cpu_addr); 792 793 return 0; 794 } 795 796 /** 797 * smu_alloc_memory_pool - allocate memory pool in the system memory 798 * 799 * @smu: amdgpu_device pointer 800 * 801 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 802 * and DramLogSetDramAddr can notify it changed. 803 * 804 * Returns 0 on success, error on failure. 805 */ 806 static int smu_alloc_memory_pool(struct smu_context *smu) 807 { 808 struct amdgpu_device *adev = smu->adev; 809 struct smu_table_context *smu_table = &smu->smu_table; 810 struct smu_table *memory_pool = &smu_table->memory_pool; 811 uint64_t pool_size = smu->pool_size; 812 int ret = 0; 813 814 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 815 return ret; 816 817 memory_pool->size = pool_size; 818 memory_pool->align = PAGE_SIZE; 819 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 820 821 switch (pool_size) { 822 case SMU_MEMORY_POOL_SIZE_256_MB: 823 case SMU_MEMORY_POOL_SIZE_512_MB: 824 case SMU_MEMORY_POOL_SIZE_1_GB: 825 case SMU_MEMORY_POOL_SIZE_2_GB: 826 ret = amdgpu_bo_create_kernel(adev, 827 memory_pool->size, 828 memory_pool->align, 829 memory_pool->domain, 830 &memory_pool->bo, 831 &memory_pool->mc_address, 832 &memory_pool->cpu_addr); 833 if (ret) 834 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 835 break; 836 default: 837 break; 838 } 839 840 return ret; 841 } 842 843 static int smu_free_memory_pool(struct smu_context *smu) 844 { 845 struct smu_table_context *smu_table = &smu->smu_table; 846 struct smu_table *memory_pool = &smu_table->memory_pool; 847 848 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 849 return 0; 850 851 amdgpu_bo_free_kernel(&memory_pool->bo, 852 &memory_pool->mc_address, 853 &memory_pool->cpu_addr); 854 855 memset(memory_pool, 0, sizeof(struct smu_table)); 856 857 return 0; 858 } 859 860 static int smu_alloc_dummy_read_table(struct smu_context *smu) 861 { 862 struct smu_table_context *smu_table = &smu->smu_table; 863 struct smu_table *dummy_read_1_table = 864 &smu_table->dummy_read_1_table; 865 struct amdgpu_device *adev = smu->adev; 866 int ret = 0; 867 868 dummy_read_1_table->size = 0x40000; 869 dummy_read_1_table->align = PAGE_SIZE; 870 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 871 872 ret = amdgpu_bo_create_kernel(adev, 873 dummy_read_1_table->size, 874 dummy_read_1_table->align, 875 dummy_read_1_table->domain, 876 &dummy_read_1_table->bo, 877 &dummy_read_1_table->mc_address, 878 &dummy_read_1_table->cpu_addr); 879 if (ret) 880 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 881 882 return ret; 883 } 884 885 static void smu_free_dummy_read_table(struct smu_context *smu) 886 { 887 struct smu_table_context *smu_table = &smu->smu_table; 888 struct smu_table *dummy_read_1_table = 889 &smu_table->dummy_read_1_table; 890 891 892 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 893 &dummy_read_1_table->mc_address, 894 &dummy_read_1_table->cpu_addr); 895 896 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 897 } 898 899 static int smu_smc_table_sw_init(struct smu_context *smu) 900 { 901 int ret; 902 903 /** 904 * Create smu_table structure, and init smc tables such as 905 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 906 */ 907 ret = smu_init_smc_tables(smu); 908 if (ret) { 909 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 910 return ret; 911 } 912 913 /** 914 * Create smu_power_context structure, and allocate smu_dpm_context and 915 * context size to fill the smu_power_context data. 916 */ 917 ret = smu_init_power(smu); 918 if (ret) { 919 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 920 return ret; 921 } 922 923 /* 924 * allocate vram bos to store smc table contents. 925 */ 926 ret = smu_init_fb_allocations(smu); 927 if (ret) 928 return ret; 929 930 ret = smu_alloc_memory_pool(smu); 931 if (ret) 932 return ret; 933 934 ret = smu_alloc_dummy_read_table(smu); 935 if (ret) 936 return ret; 937 938 ret = smu_i2c_init(smu); 939 if (ret) 940 return ret; 941 942 return 0; 943 } 944 945 static int smu_smc_table_sw_fini(struct smu_context *smu) 946 { 947 int ret; 948 949 smu_i2c_fini(smu); 950 951 smu_free_dummy_read_table(smu); 952 953 ret = smu_free_memory_pool(smu); 954 if (ret) 955 return ret; 956 957 ret = smu_fini_fb_allocations(smu); 958 if (ret) 959 return ret; 960 961 ret = smu_fini_power(smu); 962 if (ret) { 963 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 964 return ret; 965 } 966 967 ret = smu_fini_smc_tables(smu); 968 if (ret) { 969 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 970 return ret; 971 } 972 973 return 0; 974 } 975 976 static void smu_throttling_logging_work_fn(struct work_struct *work) 977 { 978 struct smu_context *smu = container_of(work, struct smu_context, 979 throttling_logging_work); 980 981 smu_log_thermal_throttling(smu); 982 } 983 984 static void smu_interrupt_work_fn(struct work_struct *work) 985 { 986 struct smu_context *smu = container_of(work, struct smu_context, 987 interrupt_work); 988 989 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 990 smu->ppt_funcs->interrupt_work(smu); 991 } 992 993 static int smu_sw_init(void *handle) 994 { 995 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 996 struct smu_context *smu = adev->powerplay.pp_handle; 997 int ret; 998 999 smu->pool_size = adev->pm.smu_prv_buffer_size; 1000 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1001 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1002 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1003 1004 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1005 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1006 atomic64_set(&smu->throttle_int_counter, 0); 1007 smu->watermarks_bitmap = 0; 1008 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1009 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1010 1011 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1012 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1013 1014 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1015 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1016 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1017 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1018 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1019 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1020 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1021 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1022 1023 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1024 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1025 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1026 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1027 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1028 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1029 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1030 smu->display_config = &adev->pm.pm_display_cfg; 1031 1032 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1033 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1034 1035 ret = smu_init_microcode(smu); 1036 if (ret) { 1037 dev_err(adev->dev, "Failed to load smu firmware!\n"); 1038 return ret; 1039 } 1040 1041 ret = smu_smc_table_sw_init(smu); 1042 if (ret) { 1043 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1044 return ret; 1045 } 1046 1047 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1048 ret = smu_get_vbios_bootup_values(smu); 1049 if (ret) { 1050 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1051 return ret; 1052 } 1053 1054 ret = smu_init_pptable_microcode(smu); 1055 if (ret) { 1056 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1057 return ret; 1058 } 1059 1060 ret = smu_register_irq_handler(smu); 1061 if (ret) { 1062 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1063 return ret; 1064 } 1065 1066 /* If there is no way to query fan control mode, fan control is not supported */ 1067 if (!smu->ppt_funcs->get_fan_control_mode) 1068 smu->adev->pm.no_fan = true; 1069 1070 return 0; 1071 } 1072 1073 static int smu_sw_fini(void *handle) 1074 { 1075 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1076 struct smu_context *smu = adev->powerplay.pp_handle; 1077 int ret; 1078 1079 ret = smu_smc_table_sw_fini(smu); 1080 if (ret) { 1081 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1082 return ret; 1083 } 1084 1085 smu_fini_microcode(smu); 1086 1087 return 0; 1088 } 1089 1090 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1091 { 1092 struct amdgpu_device *adev = smu->adev; 1093 struct smu_temperature_range *range = 1094 &smu->thermal_range; 1095 int ret = 0; 1096 1097 if (!smu->ppt_funcs->get_thermal_temperature_range) 1098 return 0; 1099 1100 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1101 if (ret) 1102 return ret; 1103 1104 adev->pm.dpm.thermal.min_temp = range->min; 1105 adev->pm.dpm.thermal.max_temp = range->max; 1106 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1107 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1108 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1109 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1110 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1111 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1112 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1113 1114 return ret; 1115 } 1116 1117 static int smu_smc_hw_setup(struct smu_context *smu) 1118 { 1119 struct smu_feature *feature = &smu->smu_feature; 1120 struct amdgpu_device *adev = smu->adev; 1121 uint32_t pcie_gen = 0, pcie_width = 0; 1122 uint64_t features_supported; 1123 int ret = 0; 1124 1125 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1126 dev_info(adev->dev, "dpm has been enabled\n"); 1127 /* this is needed specifically */ 1128 switch (adev->ip_versions[MP1_HWIP][0]) { 1129 case IP_VERSION(11, 0, 7): 1130 case IP_VERSION(11, 0, 11): 1131 case IP_VERSION(11, 5, 0): 1132 case IP_VERSION(11, 0, 12): 1133 ret = smu_system_features_control(smu, true); 1134 if (ret) 1135 dev_err(adev->dev, "Failed system features control!\n"); 1136 break; 1137 default: 1138 break; 1139 } 1140 return ret; 1141 } 1142 1143 ret = smu_init_display_count(smu, 0); 1144 if (ret) { 1145 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1146 return ret; 1147 } 1148 1149 ret = smu_set_driver_table_location(smu); 1150 if (ret) { 1151 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1152 return ret; 1153 } 1154 1155 /* 1156 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1157 */ 1158 ret = smu_set_tool_table_location(smu); 1159 if (ret) { 1160 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1161 return ret; 1162 } 1163 1164 /* 1165 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1166 * pool location. 1167 */ 1168 ret = smu_notify_memory_pool_location(smu); 1169 if (ret) { 1170 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1171 return ret; 1172 } 1173 1174 ret = smu_setup_pptable(smu); 1175 if (ret) { 1176 dev_err(adev->dev, "Failed to setup pptable!\n"); 1177 return ret; 1178 } 1179 1180 /* smu_dump_pptable(smu); */ 1181 1182 /* 1183 * With SCPM enabled, PSP is responsible for the PPTable transferring 1184 * (to SMU). Driver involvement is not needed and permitted. 1185 */ 1186 if (!adev->scpm_enabled) { 1187 /* 1188 * Copy pptable bo in the vram to smc with SMU MSGs such as 1189 * SetDriverDramAddr and TransferTableDram2Smu. 1190 */ 1191 ret = smu_write_pptable(smu); 1192 if (ret) { 1193 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1194 return ret; 1195 } 1196 } 1197 1198 /* issue Run*Btc msg */ 1199 ret = smu_run_btc(smu); 1200 if (ret) 1201 return ret; 1202 1203 /* 1204 * With SCPM enabled, these actions(and relevant messages) are 1205 * not needed and permitted. 1206 */ 1207 if (!adev->scpm_enabled) { 1208 ret = smu_feature_set_allowed_mask(smu); 1209 if (ret) { 1210 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1211 return ret; 1212 } 1213 } 1214 1215 ret = smu_system_features_control(smu, true); 1216 if (ret) { 1217 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1218 return ret; 1219 } 1220 1221 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1222 if (ret) { 1223 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1224 return ret; 1225 } 1226 bitmap_copy(feature->supported, 1227 (unsigned long *)&features_supported, 1228 feature->feature_num); 1229 1230 if (!smu_is_dpm_running(smu)) 1231 dev_info(adev->dev, "dpm has been disabled\n"); 1232 1233 /* 1234 * Set initialized values (get from vbios) to dpm tables context such as 1235 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1236 * type of clks. 1237 */ 1238 ret = smu_set_default_dpm_table(smu); 1239 if (ret) { 1240 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1241 return ret; 1242 } 1243 1244 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1245 pcie_gen = 3; 1246 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1247 pcie_gen = 2; 1248 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1249 pcie_gen = 1; 1250 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1251 pcie_gen = 0; 1252 1253 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1254 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1255 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1256 */ 1257 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1258 pcie_width = 6; 1259 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1260 pcie_width = 5; 1261 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1262 pcie_width = 4; 1263 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1264 pcie_width = 3; 1265 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1266 pcie_width = 2; 1267 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1268 pcie_width = 1; 1269 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1270 if (ret) { 1271 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1272 return ret; 1273 } 1274 1275 ret = smu_get_thermal_temperature_range(smu); 1276 if (ret) { 1277 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1278 return ret; 1279 } 1280 1281 ret = smu_enable_thermal_alert(smu); 1282 if (ret) { 1283 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1284 return ret; 1285 } 1286 1287 ret = smu_notify_display_change(smu); 1288 if (ret) { 1289 dev_err(adev->dev, "Failed to notify display change!\n"); 1290 return ret; 1291 } 1292 1293 /* 1294 * Set min deep sleep dce fclk with bootup value from vbios via 1295 * SetMinDeepSleepDcefclk MSG. 1296 */ 1297 ret = smu_set_min_dcef_deep_sleep(smu, 1298 smu->smu_table.boot_values.dcefclk / 100); 1299 1300 return ret; 1301 } 1302 1303 static int smu_start_smc_engine(struct smu_context *smu) 1304 { 1305 struct amdgpu_device *adev = smu->adev; 1306 int ret = 0; 1307 1308 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1309 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) { 1310 if (smu->ppt_funcs->load_microcode) { 1311 ret = smu->ppt_funcs->load_microcode(smu); 1312 if (ret) 1313 return ret; 1314 } 1315 } 1316 } 1317 1318 if (smu->ppt_funcs->check_fw_status) { 1319 ret = smu->ppt_funcs->check_fw_status(smu); 1320 if (ret) { 1321 dev_err(adev->dev, "SMC is not ready\n"); 1322 return ret; 1323 } 1324 } 1325 1326 /* 1327 * Send msg GetDriverIfVersion to check if the return value is equal 1328 * with DRIVER_IF_VERSION of smc header. 1329 */ 1330 ret = smu_check_fw_version(smu); 1331 if (ret) 1332 return ret; 1333 1334 return ret; 1335 } 1336 1337 static int smu_hw_init(void *handle) 1338 { 1339 int ret; 1340 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1341 struct smu_context *smu = adev->powerplay.pp_handle; 1342 1343 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1344 smu->pm_enabled = false; 1345 return 0; 1346 } 1347 1348 ret = smu_start_smc_engine(smu); 1349 if (ret) { 1350 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1351 return ret; 1352 } 1353 1354 if (smu->is_apu) { 1355 smu_dpm_set_vcn_enable(smu, true); 1356 smu_dpm_set_jpeg_enable(smu, true); 1357 smu_set_gfx_cgpg(smu, true); 1358 } 1359 1360 if (!smu->pm_enabled) 1361 return 0; 1362 1363 ret = smu_get_driver_allowed_feature_mask(smu); 1364 if (ret) 1365 return ret; 1366 1367 ret = smu_smc_hw_setup(smu); 1368 if (ret) { 1369 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1370 return ret; 1371 } 1372 1373 /* 1374 * Move maximum sustainable clock retrieving here considering 1375 * 1. It is not needed on resume(from S3). 1376 * 2. DAL settings come between .hw_init and .late_init of SMU. 1377 * And DAL needs to know the maximum sustainable clocks. Thus 1378 * it cannot be put in .late_init(). 1379 */ 1380 ret = smu_init_max_sustainable_clocks(smu); 1381 if (ret) { 1382 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1383 return ret; 1384 } 1385 1386 adev->pm.dpm_enabled = true; 1387 1388 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1389 1390 return 0; 1391 } 1392 1393 static int smu_disable_dpms(struct smu_context *smu) 1394 { 1395 struct amdgpu_device *adev = smu->adev; 1396 int ret = 0; 1397 bool use_baco = !smu->is_apu && 1398 ((amdgpu_in_reset(adev) && 1399 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1400 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1401 1402 /* 1403 * For custom pptable uploading, skip the DPM features 1404 * disable process on Navi1x ASICs. 1405 * - As the gfx related features are under control of 1406 * RLC on those ASICs. RLC reinitialization will be 1407 * needed to reenable them. That will cost much more 1408 * efforts. 1409 * 1410 * - SMU firmware can handle the DPM reenablement 1411 * properly. 1412 */ 1413 if (smu->uploading_custom_pp_table) { 1414 switch (adev->ip_versions[MP1_HWIP][0]) { 1415 case IP_VERSION(11, 0, 0): 1416 case IP_VERSION(11, 0, 5): 1417 case IP_VERSION(11, 0, 9): 1418 case IP_VERSION(11, 0, 7): 1419 case IP_VERSION(11, 0, 11): 1420 case IP_VERSION(11, 5, 0): 1421 case IP_VERSION(11, 0, 12): 1422 case IP_VERSION(11, 0, 13): 1423 return 0; 1424 default: 1425 break; 1426 } 1427 } 1428 1429 /* 1430 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1431 * on BACO in. Driver involvement is unnecessary. 1432 */ 1433 if (use_baco) { 1434 switch (adev->ip_versions[MP1_HWIP][0]) { 1435 case IP_VERSION(11, 0, 7): 1436 case IP_VERSION(11, 0, 0): 1437 case IP_VERSION(11, 0, 5): 1438 case IP_VERSION(11, 0, 9): 1439 return 0; 1440 default: 1441 break; 1442 } 1443 } 1444 1445 /* 1446 * For gpu reset, runpm and hibernation through BACO, 1447 * BACO feature has to be kept enabled. 1448 */ 1449 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1450 ret = smu_disable_all_features_with_exception(smu, 1451 SMU_FEATURE_BACO_BIT); 1452 if (ret) 1453 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1454 } else { 1455 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1456 if (!adev->scpm_enabled) { 1457 ret = smu_system_features_control(smu, false); 1458 if (ret) 1459 dev_err(adev->dev, "Failed to disable smu features.\n"); 1460 } 1461 } 1462 1463 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) && 1464 adev->gfx.rlc.funcs->stop) 1465 adev->gfx.rlc.funcs->stop(adev); 1466 1467 return ret; 1468 } 1469 1470 static int smu_smc_hw_cleanup(struct smu_context *smu) 1471 { 1472 struct amdgpu_device *adev = smu->adev; 1473 int ret = 0; 1474 1475 cancel_work_sync(&smu->throttling_logging_work); 1476 cancel_work_sync(&smu->interrupt_work); 1477 1478 ret = smu_disable_thermal_alert(smu); 1479 if (ret) { 1480 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1481 return ret; 1482 } 1483 1484 ret = smu_disable_dpms(smu); 1485 if (ret) { 1486 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1487 return ret; 1488 } 1489 1490 return 0; 1491 } 1492 1493 static int smu_hw_fini(void *handle) 1494 { 1495 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1496 struct smu_context *smu = adev->powerplay.pp_handle; 1497 1498 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1499 return 0; 1500 1501 smu_dpm_set_vcn_enable(smu, false); 1502 smu_dpm_set_jpeg_enable(smu, false); 1503 1504 adev->vcn.cur_state = AMD_PG_STATE_GATE; 1505 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 1506 1507 if (!smu->pm_enabled) 1508 return 0; 1509 1510 adev->pm.dpm_enabled = false; 1511 1512 return smu_smc_hw_cleanup(smu); 1513 } 1514 1515 static void smu_late_fini(void *handle) 1516 { 1517 struct amdgpu_device *adev = handle; 1518 struct smu_context *smu = adev->powerplay.pp_handle; 1519 1520 kfree(smu); 1521 } 1522 1523 static int smu_reset(struct smu_context *smu) 1524 { 1525 struct amdgpu_device *adev = smu->adev; 1526 int ret; 1527 1528 ret = smu_hw_fini(adev); 1529 if (ret) 1530 return ret; 1531 1532 ret = smu_hw_init(adev); 1533 if (ret) 1534 return ret; 1535 1536 ret = smu_late_init(adev); 1537 if (ret) 1538 return ret; 1539 1540 return 0; 1541 } 1542 1543 static int smu_suspend(void *handle) 1544 { 1545 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1546 struct smu_context *smu = adev->powerplay.pp_handle; 1547 int ret; 1548 1549 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1550 return 0; 1551 1552 if (!smu->pm_enabled) 1553 return 0; 1554 1555 adev->pm.dpm_enabled = false; 1556 1557 ret = smu_smc_hw_cleanup(smu); 1558 if (ret) 1559 return ret; 1560 1561 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1562 1563 smu_set_gfx_cgpg(smu, false); 1564 1565 return 0; 1566 } 1567 1568 static int smu_resume(void *handle) 1569 { 1570 int ret; 1571 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1572 struct smu_context *smu = adev->powerplay.pp_handle; 1573 1574 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1575 return 0; 1576 1577 if (!smu->pm_enabled) 1578 return 0; 1579 1580 dev_info(adev->dev, "SMU is resuming...\n"); 1581 1582 ret = smu_start_smc_engine(smu); 1583 if (ret) { 1584 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1585 return ret; 1586 } 1587 1588 ret = smu_smc_hw_setup(smu); 1589 if (ret) { 1590 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1591 return ret; 1592 } 1593 1594 smu_set_gfx_cgpg(smu, true); 1595 1596 smu->disable_uclk_switch = 0; 1597 1598 adev->pm.dpm_enabled = true; 1599 1600 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1601 1602 return 0; 1603 } 1604 1605 static int smu_display_configuration_change(void *handle, 1606 const struct amd_pp_display_configuration *display_config) 1607 { 1608 struct smu_context *smu = handle; 1609 int index = 0; 1610 int num_of_active_display = 0; 1611 1612 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1613 return -EOPNOTSUPP; 1614 1615 if (!display_config) 1616 return -EINVAL; 1617 1618 smu_set_min_dcef_deep_sleep(smu, 1619 display_config->min_dcef_deep_sleep_set_clk / 100); 1620 1621 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1622 if (display_config->displays[index].controller_id != 0) 1623 num_of_active_display++; 1624 } 1625 1626 return 0; 1627 } 1628 1629 static int smu_set_clockgating_state(void *handle, 1630 enum amd_clockgating_state state) 1631 { 1632 return 0; 1633 } 1634 1635 static int smu_set_powergating_state(void *handle, 1636 enum amd_powergating_state state) 1637 { 1638 return 0; 1639 } 1640 1641 static int smu_enable_umd_pstate(void *handle, 1642 enum amd_dpm_forced_level *level) 1643 { 1644 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1645 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1646 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1647 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1648 1649 struct smu_context *smu = (struct smu_context*)(handle); 1650 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1651 1652 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1653 return -EINVAL; 1654 1655 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1656 /* enter umd pstate, save current level, disable gfx cg*/ 1657 if (*level & profile_mode_mask) { 1658 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1659 smu_gpo_control(smu, false); 1660 smu_gfx_ulv_control(smu, false); 1661 smu_deep_sleep_control(smu, false); 1662 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1663 } 1664 } else { 1665 /* exit umd pstate, restore level, enable gfx cg*/ 1666 if (!(*level & profile_mode_mask)) { 1667 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1668 *level = smu_dpm_ctx->saved_dpm_level; 1669 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1670 smu_deep_sleep_control(smu, true); 1671 smu_gfx_ulv_control(smu, true); 1672 smu_gpo_control(smu, true); 1673 } 1674 } 1675 1676 return 0; 1677 } 1678 1679 static int smu_bump_power_profile_mode(struct smu_context *smu, 1680 long *param, 1681 uint32_t param_size) 1682 { 1683 int ret = 0; 1684 1685 if (smu->ppt_funcs->set_power_profile_mode) 1686 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1687 1688 return ret; 1689 } 1690 1691 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1692 enum amd_dpm_forced_level level, 1693 bool skip_display_settings) 1694 { 1695 int ret = 0; 1696 int index = 0; 1697 long workload; 1698 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1699 1700 if (!skip_display_settings) { 1701 ret = smu_display_config_changed(smu); 1702 if (ret) { 1703 dev_err(smu->adev->dev, "Failed to change display config!"); 1704 return ret; 1705 } 1706 } 1707 1708 ret = smu_apply_clocks_adjust_rules(smu); 1709 if (ret) { 1710 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1711 return ret; 1712 } 1713 1714 if (!skip_display_settings) { 1715 ret = smu_notify_smc_display_config(smu); 1716 if (ret) { 1717 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1718 return ret; 1719 } 1720 } 1721 1722 if (smu_dpm_ctx->dpm_level != level) { 1723 ret = smu_asic_set_performance_level(smu, level); 1724 if (ret) { 1725 dev_err(smu->adev->dev, "Failed to set performance level!"); 1726 return ret; 1727 } 1728 1729 /* update the saved copy */ 1730 smu_dpm_ctx->dpm_level = level; 1731 } 1732 1733 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1734 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1735 index = fls(smu->workload_mask); 1736 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1737 workload = smu->workload_setting[index]; 1738 1739 if (smu->power_profile_mode != workload) 1740 smu_bump_power_profile_mode(smu, &workload, 0); 1741 } 1742 1743 return ret; 1744 } 1745 1746 static int smu_handle_task(struct smu_context *smu, 1747 enum amd_dpm_forced_level level, 1748 enum amd_pp_task task_id) 1749 { 1750 int ret = 0; 1751 1752 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1753 return -EOPNOTSUPP; 1754 1755 switch (task_id) { 1756 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1757 ret = smu_pre_display_config_changed(smu); 1758 if (ret) 1759 return ret; 1760 ret = smu_adjust_power_state_dynamic(smu, level, false); 1761 break; 1762 case AMD_PP_TASK_COMPLETE_INIT: 1763 case AMD_PP_TASK_READJUST_POWER_STATE: 1764 ret = smu_adjust_power_state_dynamic(smu, level, true); 1765 break; 1766 default: 1767 break; 1768 } 1769 1770 return ret; 1771 } 1772 1773 static int smu_handle_dpm_task(void *handle, 1774 enum amd_pp_task task_id, 1775 enum amd_pm_state_type *user_state) 1776 { 1777 struct smu_context *smu = handle; 1778 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1779 1780 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 1781 1782 } 1783 1784 static int smu_switch_power_profile(void *handle, 1785 enum PP_SMC_POWER_PROFILE type, 1786 bool en) 1787 { 1788 struct smu_context *smu = handle; 1789 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1790 long workload; 1791 uint32_t index; 1792 1793 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1794 return -EOPNOTSUPP; 1795 1796 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1797 return -EINVAL; 1798 1799 if (!en) { 1800 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1801 index = fls(smu->workload_mask); 1802 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1803 workload = smu->workload_setting[index]; 1804 } else { 1805 smu->workload_mask |= (1 << smu->workload_prority[type]); 1806 index = fls(smu->workload_mask); 1807 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1808 workload = smu->workload_setting[index]; 1809 } 1810 1811 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1812 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1813 smu_bump_power_profile_mode(smu, &workload, 0); 1814 1815 return 0; 1816 } 1817 1818 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 1819 { 1820 struct smu_context *smu = handle; 1821 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1822 1823 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1824 return -EOPNOTSUPP; 1825 1826 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1827 return -EINVAL; 1828 1829 return smu_dpm_ctx->dpm_level; 1830 } 1831 1832 static int smu_force_performance_level(void *handle, 1833 enum amd_dpm_forced_level level) 1834 { 1835 struct smu_context *smu = handle; 1836 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1837 int ret = 0; 1838 1839 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1840 return -EOPNOTSUPP; 1841 1842 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1843 return -EINVAL; 1844 1845 ret = smu_enable_umd_pstate(smu, &level); 1846 if (ret) 1847 return ret; 1848 1849 ret = smu_handle_task(smu, level, 1850 AMD_PP_TASK_READJUST_POWER_STATE); 1851 1852 /* reset user dpm clock state */ 1853 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1854 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 1855 smu->user_dpm_profile.clk_dependency = 0; 1856 } 1857 1858 return ret; 1859 } 1860 1861 static int smu_set_display_count(void *handle, uint32_t count) 1862 { 1863 struct smu_context *smu = handle; 1864 1865 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1866 return -EOPNOTSUPP; 1867 1868 return smu_init_display_count(smu, count); 1869 } 1870 1871 static int smu_force_smuclk_levels(struct smu_context *smu, 1872 enum smu_clk_type clk_type, 1873 uint32_t mask) 1874 { 1875 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1876 int ret = 0; 1877 1878 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1879 return -EOPNOTSUPP; 1880 1881 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1882 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1883 return -EINVAL; 1884 } 1885 1886 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 1887 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1888 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 1889 smu->user_dpm_profile.clk_mask[clk_type] = mask; 1890 smu_set_user_clk_dependencies(smu, clk_type); 1891 } 1892 } 1893 1894 return ret; 1895 } 1896 1897 static int smu_force_ppclk_levels(void *handle, 1898 enum pp_clock_type type, 1899 uint32_t mask) 1900 { 1901 struct smu_context *smu = handle; 1902 enum smu_clk_type clk_type; 1903 1904 switch (type) { 1905 case PP_SCLK: 1906 clk_type = SMU_SCLK; break; 1907 case PP_MCLK: 1908 clk_type = SMU_MCLK; break; 1909 case PP_PCIE: 1910 clk_type = SMU_PCIE; break; 1911 case PP_SOCCLK: 1912 clk_type = SMU_SOCCLK; break; 1913 case PP_FCLK: 1914 clk_type = SMU_FCLK; break; 1915 case PP_DCEFCLK: 1916 clk_type = SMU_DCEFCLK; break; 1917 case PP_VCLK: 1918 clk_type = SMU_VCLK; break; 1919 case PP_DCLK: 1920 clk_type = SMU_DCLK; break; 1921 case OD_SCLK: 1922 clk_type = SMU_OD_SCLK; break; 1923 case OD_MCLK: 1924 clk_type = SMU_OD_MCLK; break; 1925 case OD_VDDC_CURVE: 1926 clk_type = SMU_OD_VDDC_CURVE; break; 1927 case OD_RANGE: 1928 clk_type = SMU_OD_RANGE; break; 1929 default: 1930 return -EINVAL; 1931 } 1932 1933 return smu_force_smuclk_levels(smu, clk_type, mask); 1934 } 1935 1936 /* 1937 * On system suspending or resetting, the dpm_enabled 1938 * flag will be cleared. So that those SMU services which 1939 * are not supported will be gated. 1940 * However, the mp1 state setting should still be granted 1941 * even if the dpm_enabled cleared. 1942 */ 1943 static int smu_set_mp1_state(void *handle, 1944 enum pp_mp1_state mp1_state) 1945 { 1946 struct smu_context *smu = handle; 1947 int ret = 0; 1948 1949 if (!smu->pm_enabled) 1950 return -EOPNOTSUPP; 1951 1952 if (smu->ppt_funcs && 1953 smu->ppt_funcs->set_mp1_state) 1954 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 1955 1956 return ret; 1957 } 1958 1959 static int smu_set_df_cstate(void *handle, 1960 enum pp_df_cstate state) 1961 { 1962 struct smu_context *smu = handle; 1963 int ret = 0; 1964 1965 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1966 return -EOPNOTSUPP; 1967 1968 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 1969 return 0; 1970 1971 ret = smu->ppt_funcs->set_df_cstate(smu, state); 1972 if (ret) 1973 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 1974 1975 return ret; 1976 } 1977 1978 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 1979 { 1980 int ret = 0; 1981 1982 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1983 return -EOPNOTSUPP; 1984 1985 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 1986 return 0; 1987 1988 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 1989 if (ret) 1990 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 1991 1992 return ret; 1993 } 1994 1995 int smu_write_watermarks_table(struct smu_context *smu) 1996 { 1997 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1998 return -EOPNOTSUPP; 1999 2000 return smu_set_watermarks_table(smu, NULL); 2001 } 2002 2003 static int smu_set_watermarks_for_clock_ranges(void *handle, 2004 struct pp_smu_wm_range_sets *clock_ranges) 2005 { 2006 struct smu_context *smu = handle; 2007 2008 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2009 return -EOPNOTSUPP; 2010 2011 if (smu->disable_watermark) 2012 return 0; 2013 2014 return smu_set_watermarks_table(smu, clock_ranges); 2015 } 2016 2017 int smu_set_ac_dc(struct smu_context *smu) 2018 { 2019 int ret = 0; 2020 2021 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2022 return -EOPNOTSUPP; 2023 2024 /* controlled by firmware */ 2025 if (smu->dc_controlled_by_gpio) 2026 return 0; 2027 2028 ret = smu_set_power_source(smu, 2029 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2030 SMU_POWER_SOURCE_DC); 2031 if (ret) 2032 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2033 smu->adev->pm.ac_power ? "AC" : "DC"); 2034 2035 return ret; 2036 } 2037 2038 const struct amd_ip_funcs smu_ip_funcs = { 2039 .name = "smu", 2040 .early_init = smu_early_init, 2041 .late_init = smu_late_init, 2042 .sw_init = smu_sw_init, 2043 .sw_fini = smu_sw_fini, 2044 .hw_init = smu_hw_init, 2045 .hw_fini = smu_hw_fini, 2046 .late_fini = smu_late_fini, 2047 .suspend = smu_suspend, 2048 .resume = smu_resume, 2049 .is_idle = NULL, 2050 .check_soft_reset = NULL, 2051 .wait_for_idle = NULL, 2052 .soft_reset = NULL, 2053 .set_clockgating_state = smu_set_clockgating_state, 2054 .set_powergating_state = smu_set_powergating_state, 2055 }; 2056 2057 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 2058 { 2059 .type = AMD_IP_BLOCK_TYPE_SMC, 2060 .major = 11, 2061 .minor = 0, 2062 .rev = 0, 2063 .funcs = &smu_ip_funcs, 2064 }; 2065 2066 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 2067 { 2068 .type = AMD_IP_BLOCK_TYPE_SMC, 2069 .major = 12, 2070 .minor = 0, 2071 .rev = 0, 2072 .funcs = &smu_ip_funcs, 2073 }; 2074 2075 const struct amdgpu_ip_block_version smu_v13_0_ip_block = 2076 { 2077 .type = AMD_IP_BLOCK_TYPE_SMC, 2078 .major = 13, 2079 .minor = 0, 2080 .rev = 0, 2081 .funcs = &smu_ip_funcs, 2082 }; 2083 2084 static int smu_load_microcode(void *handle) 2085 { 2086 struct smu_context *smu = handle; 2087 struct amdgpu_device *adev = smu->adev; 2088 int ret = 0; 2089 2090 if (!smu->pm_enabled) 2091 return -EOPNOTSUPP; 2092 2093 /* This should be used for non PSP loading */ 2094 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2095 return 0; 2096 2097 if (smu->ppt_funcs->load_microcode) { 2098 ret = smu->ppt_funcs->load_microcode(smu); 2099 if (ret) { 2100 dev_err(adev->dev, "Load microcode failed\n"); 2101 return ret; 2102 } 2103 } 2104 2105 if (smu->ppt_funcs->check_fw_status) { 2106 ret = smu->ppt_funcs->check_fw_status(smu); 2107 if (ret) { 2108 dev_err(adev->dev, "SMC is not ready\n"); 2109 return ret; 2110 } 2111 } 2112 2113 return ret; 2114 } 2115 2116 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2117 { 2118 int ret = 0; 2119 2120 if (smu->ppt_funcs->set_gfx_cgpg) 2121 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2122 2123 return ret; 2124 } 2125 2126 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2127 { 2128 struct smu_context *smu = handle; 2129 int ret = 0; 2130 2131 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2132 return -EOPNOTSUPP; 2133 2134 if (!smu->ppt_funcs->set_fan_speed_rpm) 2135 return -EOPNOTSUPP; 2136 2137 if (speed == U32_MAX) 2138 return -EINVAL; 2139 2140 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2141 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2142 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2143 smu->user_dpm_profile.fan_speed_rpm = speed; 2144 2145 /* Override custom PWM setting as they cannot co-exist */ 2146 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2147 smu->user_dpm_profile.fan_speed_pwm = 0; 2148 } 2149 2150 return ret; 2151 } 2152 2153 /** 2154 * smu_get_power_limit - Request one of the SMU Power Limits 2155 * 2156 * @handle: pointer to smu context 2157 * @limit: requested limit is written back to this variable 2158 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2159 * @pp_power_type: &pp_power_type type of power 2160 * Return: 0 on success, <0 on error 2161 * 2162 */ 2163 int smu_get_power_limit(void *handle, 2164 uint32_t *limit, 2165 enum pp_power_limit_level pp_limit_level, 2166 enum pp_power_type pp_power_type) 2167 { 2168 struct smu_context *smu = handle; 2169 struct amdgpu_device *adev = smu->adev; 2170 enum smu_ppt_limit_level limit_level; 2171 uint32_t limit_type; 2172 int ret = 0; 2173 2174 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2175 return -EOPNOTSUPP; 2176 2177 switch(pp_power_type) { 2178 case PP_PWR_TYPE_SUSTAINED: 2179 limit_type = SMU_DEFAULT_PPT_LIMIT; 2180 break; 2181 case PP_PWR_TYPE_FAST: 2182 limit_type = SMU_FAST_PPT_LIMIT; 2183 break; 2184 default: 2185 return -EOPNOTSUPP; 2186 break; 2187 } 2188 2189 switch(pp_limit_level){ 2190 case PP_PWR_LIMIT_CURRENT: 2191 limit_level = SMU_PPT_LIMIT_CURRENT; 2192 break; 2193 case PP_PWR_LIMIT_DEFAULT: 2194 limit_level = SMU_PPT_LIMIT_DEFAULT; 2195 break; 2196 case PP_PWR_LIMIT_MAX: 2197 limit_level = SMU_PPT_LIMIT_MAX; 2198 break; 2199 case PP_PWR_LIMIT_MIN: 2200 default: 2201 return -EOPNOTSUPP; 2202 break; 2203 } 2204 2205 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2206 if (smu->ppt_funcs->get_ppt_limit) 2207 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2208 } else { 2209 switch (limit_level) { 2210 case SMU_PPT_LIMIT_CURRENT: 2211 switch (adev->ip_versions[MP1_HWIP][0]) { 2212 case IP_VERSION(13, 0, 2): 2213 case IP_VERSION(11, 0, 7): 2214 case IP_VERSION(11, 0, 11): 2215 case IP_VERSION(11, 0, 12): 2216 case IP_VERSION(11, 0, 13): 2217 ret = smu_get_asic_power_limits(smu, 2218 &smu->current_power_limit, 2219 NULL, 2220 NULL); 2221 break; 2222 default: 2223 break; 2224 } 2225 *limit = smu->current_power_limit; 2226 break; 2227 case SMU_PPT_LIMIT_DEFAULT: 2228 *limit = smu->default_power_limit; 2229 break; 2230 case SMU_PPT_LIMIT_MAX: 2231 *limit = smu->max_power_limit; 2232 break; 2233 default: 2234 break; 2235 } 2236 } 2237 2238 return ret; 2239 } 2240 2241 static int smu_set_power_limit(void *handle, uint32_t limit) 2242 { 2243 struct smu_context *smu = handle; 2244 uint32_t limit_type = limit >> 24; 2245 int ret = 0; 2246 2247 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2248 return -EOPNOTSUPP; 2249 2250 limit &= (1<<24)-1; 2251 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2252 if (smu->ppt_funcs->set_power_limit) 2253 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2254 2255 if (limit > smu->max_power_limit) { 2256 dev_err(smu->adev->dev, 2257 "New power limit (%d) is over the max allowed %d\n", 2258 limit, smu->max_power_limit); 2259 return -EINVAL; 2260 } 2261 2262 if (!limit) 2263 limit = smu->current_power_limit; 2264 2265 if (smu->ppt_funcs->set_power_limit) { 2266 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2267 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2268 smu->user_dpm_profile.power_limit = limit; 2269 } 2270 2271 return ret; 2272 } 2273 2274 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2275 { 2276 int ret = 0; 2277 2278 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2279 return -EOPNOTSUPP; 2280 2281 if (smu->ppt_funcs->print_clk_levels) 2282 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2283 2284 return ret; 2285 } 2286 2287 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2288 { 2289 enum smu_clk_type clk_type; 2290 2291 switch (type) { 2292 case PP_SCLK: 2293 clk_type = SMU_SCLK; break; 2294 case PP_MCLK: 2295 clk_type = SMU_MCLK; break; 2296 case PP_PCIE: 2297 clk_type = SMU_PCIE; break; 2298 case PP_SOCCLK: 2299 clk_type = SMU_SOCCLK; break; 2300 case PP_FCLK: 2301 clk_type = SMU_FCLK; break; 2302 case PP_DCEFCLK: 2303 clk_type = SMU_DCEFCLK; break; 2304 case PP_VCLK: 2305 clk_type = SMU_VCLK; break; 2306 case PP_DCLK: 2307 clk_type = SMU_DCLK; break; 2308 case OD_SCLK: 2309 clk_type = SMU_OD_SCLK; break; 2310 case OD_MCLK: 2311 clk_type = SMU_OD_MCLK; break; 2312 case OD_VDDC_CURVE: 2313 clk_type = SMU_OD_VDDC_CURVE; break; 2314 case OD_RANGE: 2315 clk_type = SMU_OD_RANGE; break; 2316 case OD_VDDGFX_OFFSET: 2317 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2318 case OD_CCLK: 2319 clk_type = SMU_OD_CCLK; break; 2320 default: 2321 clk_type = SMU_CLK_COUNT; break; 2322 } 2323 2324 return clk_type; 2325 } 2326 2327 static int smu_print_ppclk_levels(void *handle, 2328 enum pp_clock_type type, 2329 char *buf) 2330 { 2331 struct smu_context *smu = handle; 2332 enum smu_clk_type clk_type; 2333 2334 clk_type = smu_convert_to_smuclk(type); 2335 if (clk_type == SMU_CLK_COUNT) 2336 return -EINVAL; 2337 2338 return smu_print_smuclk_levels(smu, clk_type, buf); 2339 } 2340 2341 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2342 { 2343 struct smu_context *smu = handle; 2344 enum smu_clk_type clk_type; 2345 2346 clk_type = smu_convert_to_smuclk(type); 2347 if (clk_type == SMU_CLK_COUNT) 2348 return -EINVAL; 2349 2350 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2351 return -EOPNOTSUPP; 2352 2353 if (!smu->ppt_funcs->emit_clk_levels) 2354 return -ENOENT; 2355 2356 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2357 2358 } 2359 2360 static int smu_od_edit_dpm_table(void *handle, 2361 enum PP_OD_DPM_TABLE_COMMAND type, 2362 long *input, uint32_t size) 2363 { 2364 struct smu_context *smu = handle; 2365 int ret = 0; 2366 2367 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2368 return -EOPNOTSUPP; 2369 2370 if (smu->ppt_funcs->od_edit_dpm_table) { 2371 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2372 } 2373 2374 return ret; 2375 } 2376 2377 static int smu_read_sensor(void *handle, 2378 int sensor, 2379 void *data, 2380 int *size_arg) 2381 { 2382 struct smu_context *smu = handle; 2383 struct smu_umd_pstate_table *pstate_table = 2384 &smu->pstate_table; 2385 int ret = 0; 2386 uint32_t *size, size_val; 2387 2388 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2389 return -EOPNOTSUPP; 2390 2391 if (!data || !size_arg) 2392 return -EINVAL; 2393 2394 size_val = *size_arg; 2395 size = &size_val; 2396 2397 if (smu->ppt_funcs->read_sensor) 2398 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2399 goto unlock; 2400 2401 switch (sensor) { 2402 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2403 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2404 *size = 4; 2405 break; 2406 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2407 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2408 *size = 4; 2409 break; 2410 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2411 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2412 *size = 8; 2413 break; 2414 case AMDGPU_PP_SENSOR_UVD_POWER: 2415 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2416 *size = 4; 2417 break; 2418 case AMDGPU_PP_SENSOR_VCE_POWER: 2419 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2420 *size = 4; 2421 break; 2422 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2423 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2424 *size = 4; 2425 break; 2426 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2427 *(uint32_t *)data = 0; 2428 *size = 4; 2429 break; 2430 default: 2431 *size = 0; 2432 ret = -EOPNOTSUPP; 2433 break; 2434 } 2435 2436 unlock: 2437 // assign uint32_t to int 2438 *size_arg = size_val; 2439 2440 return ret; 2441 } 2442 2443 static int smu_get_power_profile_mode(void *handle, char *buf) 2444 { 2445 struct smu_context *smu = handle; 2446 2447 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2448 !smu->ppt_funcs->get_power_profile_mode) 2449 return -EOPNOTSUPP; 2450 if (!buf) 2451 return -EINVAL; 2452 2453 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 2454 } 2455 2456 static int smu_set_power_profile_mode(void *handle, 2457 long *param, 2458 uint32_t param_size) 2459 { 2460 struct smu_context *smu = handle; 2461 2462 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2463 !smu->ppt_funcs->set_power_profile_mode) 2464 return -EOPNOTSUPP; 2465 2466 return smu_bump_power_profile_mode(smu, param, param_size); 2467 } 2468 2469 2470 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 2471 { 2472 struct smu_context *smu = handle; 2473 2474 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2475 return -EOPNOTSUPP; 2476 2477 if (!smu->ppt_funcs->get_fan_control_mode) 2478 return -EOPNOTSUPP; 2479 2480 if (!fan_mode) 2481 return -EINVAL; 2482 2483 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 2484 2485 return 0; 2486 } 2487 2488 static int smu_set_fan_control_mode(void *handle, u32 value) 2489 { 2490 struct smu_context *smu = handle; 2491 int ret = 0; 2492 2493 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2494 return -EOPNOTSUPP; 2495 2496 if (!smu->ppt_funcs->set_fan_control_mode) 2497 return -EOPNOTSUPP; 2498 2499 if (value == U32_MAX) 2500 return -EINVAL; 2501 2502 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2503 if (ret) 2504 goto out; 2505 2506 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2507 smu->user_dpm_profile.fan_mode = value; 2508 2509 /* reset user dpm fan speed */ 2510 if (value != AMD_FAN_CTRL_MANUAL) { 2511 smu->user_dpm_profile.fan_speed_pwm = 0; 2512 smu->user_dpm_profile.fan_speed_rpm = 0; 2513 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 2514 } 2515 } 2516 2517 out: 2518 return ret; 2519 } 2520 2521 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 2522 { 2523 struct smu_context *smu = handle; 2524 int ret = 0; 2525 2526 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2527 return -EOPNOTSUPP; 2528 2529 if (!smu->ppt_funcs->get_fan_speed_pwm) 2530 return -EOPNOTSUPP; 2531 2532 if (!speed) 2533 return -EINVAL; 2534 2535 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 2536 2537 return ret; 2538 } 2539 2540 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 2541 { 2542 struct smu_context *smu = handle; 2543 int ret = 0; 2544 2545 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2546 return -EOPNOTSUPP; 2547 2548 if (!smu->ppt_funcs->set_fan_speed_pwm) 2549 return -EOPNOTSUPP; 2550 2551 if (speed == U32_MAX) 2552 return -EINVAL; 2553 2554 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 2555 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2556 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 2557 smu->user_dpm_profile.fan_speed_pwm = speed; 2558 2559 /* Override custom RPM setting as they cannot co-exist */ 2560 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 2561 smu->user_dpm_profile.fan_speed_rpm = 0; 2562 } 2563 2564 return ret; 2565 } 2566 2567 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2568 { 2569 struct smu_context *smu = handle; 2570 int ret = 0; 2571 2572 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2573 return -EOPNOTSUPP; 2574 2575 if (!smu->ppt_funcs->get_fan_speed_rpm) 2576 return -EOPNOTSUPP; 2577 2578 if (!speed) 2579 return -EINVAL; 2580 2581 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 2582 2583 return ret; 2584 } 2585 2586 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 2587 { 2588 struct smu_context *smu = handle; 2589 2590 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2591 return -EOPNOTSUPP; 2592 2593 return smu_set_min_dcef_deep_sleep(smu, clk); 2594 } 2595 2596 static int smu_get_clock_by_type_with_latency(void *handle, 2597 enum amd_pp_clock_type type, 2598 struct pp_clock_levels_with_latency *clocks) 2599 { 2600 struct smu_context *smu = handle; 2601 enum smu_clk_type clk_type; 2602 int ret = 0; 2603 2604 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2605 return -EOPNOTSUPP; 2606 2607 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 2608 switch (type) { 2609 case amd_pp_sys_clock: 2610 clk_type = SMU_GFXCLK; 2611 break; 2612 case amd_pp_mem_clock: 2613 clk_type = SMU_MCLK; 2614 break; 2615 case amd_pp_dcef_clock: 2616 clk_type = SMU_DCEFCLK; 2617 break; 2618 case amd_pp_disp_clock: 2619 clk_type = SMU_DISPCLK; 2620 break; 2621 default: 2622 dev_err(smu->adev->dev, "Invalid clock type!\n"); 2623 return -EINVAL; 2624 } 2625 2626 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2627 } 2628 2629 return ret; 2630 } 2631 2632 static int smu_display_clock_voltage_request(void *handle, 2633 struct pp_display_clock_request *clock_req) 2634 { 2635 struct smu_context *smu = handle; 2636 int ret = 0; 2637 2638 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2639 return -EOPNOTSUPP; 2640 2641 if (smu->ppt_funcs->display_clock_voltage_request) 2642 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2643 2644 return ret; 2645 } 2646 2647 2648 static int smu_display_disable_memory_clock_switch(void *handle, 2649 bool disable_memory_clock_switch) 2650 { 2651 struct smu_context *smu = handle; 2652 int ret = -EINVAL; 2653 2654 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2655 return -EOPNOTSUPP; 2656 2657 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2658 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2659 2660 return ret; 2661 } 2662 2663 static int smu_set_xgmi_pstate(void *handle, 2664 uint32_t pstate) 2665 { 2666 struct smu_context *smu = handle; 2667 int ret = 0; 2668 2669 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2670 return -EOPNOTSUPP; 2671 2672 if (smu->ppt_funcs->set_xgmi_pstate) 2673 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2674 2675 if(ret) 2676 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2677 2678 return ret; 2679 } 2680 2681 static int smu_get_baco_capability(void *handle, bool *cap) 2682 { 2683 struct smu_context *smu = handle; 2684 2685 *cap = false; 2686 2687 if (!smu->pm_enabled) 2688 return 0; 2689 2690 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2691 *cap = smu->ppt_funcs->baco_is_support(smu); 2692 2693 return 0; 2694 } 2695 2696 static int smu_baco_set_state(void *handle, int state) 2697 { 2698 struct smu_context *smu = handle; 2699 int ret = 0; 2700 2701 if (!smu->pm_enabled) 2702 return -EOPNOTSUPP; 2703 2704 if (state == 0) { 2705 if (smu->ppt_funcs->baco_exit) 2706 ret = smu->ppt_funcs->baco_exit(smu); 2707 } else if (state == 1) { 2708 if (smu->ppt_funcs->baco_enter) 2709 ret = smu->ppt_funcs->baco_enter(smu); 2710 } else { 2711 return -EINVAL; 2712 } 2713 2714 if (ret) 2715 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 2716 (state)?"enter":"exit"); 2717 2718 return ret; 2719 } 2720 2721 bool smu_mode1_reset_is_support(struct smu_context *smu) 2722 { 2723 bool ret = false; 2724 2725 if (!smu->pm_enabled) 2726 return false; 2727 2728 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2729 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2730 2731 return ret; 2732 } 2733 2734 bool smu_mode2_reset_is_support(struct smu_context *smu) 2735 { 2736 bool ret = false; 2737 2738 if (!smu->pm_enabled) 2739 return false; 2740 2741 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 2742 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 2743 2744 return ret; 2745 } 2746 2747 int smu_mode1_reset(struct smu_context *smu) 2748 { 2749 int ret = 0; 2750 2751 if (!smu->pm_enabled) 2752 return -EOPNOTSUPP; 2753 2754 if (smu->ppt_funcs->mode1_reset) 2755 ret = smu->ppt_funcs->mode1_reset(smu); 2756 2757 return ret; 2758 } 2759 2760 static int smu_mode2_reset(void *handle) 2761 { 2762 struct smu_context *smu = handle; 2763 int ret = 0; 2764 2765 if (!smu->pm_enabled) 2766 return -EOPNOTSUPP; 2767 2768 if (smu->ppt_funcs->mode2_reset) 2769 ret = smu->ppt_funcs->mode2_reset(smu); 2770 2771 if (ret) 2772 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2773 2774 return ret; 2775 } 2776 2777 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 2778 struct pp_smu_nv_clock_table *max_clocks) 2779 { 2780 struct smu_context *smu = handle; 2781 int ret = 0; 2782 2783 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2784 return -EOPNOTSUPP; 2785 2786 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2787 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2788 2789 return ret; 2790 } 2791 2792 static int smu_get_uclk_dpm_states(void *handle, 2793 unsigned int *clock_values_in_khz, 2794 unsigned int *num_states) 2795 { 2796 struct smu_context *smu = handle; 2797 int ret = 0; 2798 2799 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2800 return -EOPNOTSUPP; 2801 2802 if (smu->ppt_funcs->get_uclk_dpm_states) 2803 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2804 2805 return ret; 2806 } 2807 2808 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 2809 { 2810 struct smu_context *smu = handle; 2811 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2812 2813 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2814 return -EOPNOTSUPP; 2815 2816 if (smu->ppt_funcs->get_current_power_state) 2817 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2818 2819 return pm_state; 2820 } 2821 2822 static int smu_get_dpm_clock_table(void *handle, 2823 struct dpm_clocks *clock_table) 2824 { 2825 struct smu_context *smu = handle; 2826 int ret = 0; 2827 2828 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2829 return -EOPNOTSUPP; 2830 2831 if (smu->ppt_funcs->get_dpm_clock_table) 2832 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 2833 2834 return ret; 2835 } 2836 2837 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 2838 { 2839 struct smu_context *smu = handle; 2840 2841 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2842 return -EOPNOTSUPP; 2843 2844 if (!smu->ppt_funcs->get_gpu_metrics) 2845 return -EOPNOTSUPP; 2846 2847 return smu->ppt_funcs->get_gpu_metrics(smu, table); 2848 } 2849 2850 static int smu_enable_mgpu_fan_boost(void *handle) 2851 { 2852 struct smu_context *smu = handle; 2853 int ret = 0; 2854 2855 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2856 return -EOPNOTSUPP; 2857 2858 if (smu->ppt_funcs->enable_mgpu_fan_boost) 2859 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 2860 2861 return ret; 2862 } 2863 2864 static int smu_gfx_state_change_set(void *handle, 2865 uint32_t state) 2866 { 2867 struct smu_context *smu = handle; 2868 int ret = 0; 2869 2870 if (smu->ppt_funcs->gfx_state_change_set) 2871 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 2872 2873 return ret; 2874 } 2875 2876 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 2877 { 2878 int ret = 0; 2879 2880 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 2881 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 2882 2883 return ret; 2884 } 2885 2886 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 2887 { 2888 int ret = -EOPNOTSUPP; 2889 2890 if (smu->ppt_funcs && 2891 smu->ppt_funcs->get_ecc_info) 2892 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 2893 2894 return ret; 2895 2896 } 2897 2898 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 2899 { 2900 struct smu_context *smu = handle; 2901 struct smu_table_context *smu_table = &smu->smu_table; 2902 struct smu_table *memory_pool = &smu_table->memory_pool; 2903 2904 if (!addr || !size) 2905 return -EINVAL; 2906 2907 *addr = NULL; 2908 *size = 0; 2909 if (memory_pool->bo) { 2910 *addr = memory_pool->cpu_addr; 2911 *size = memory_pool->size; 2912 } 2913 2914 return 0; 2915 } 2916 2917 static const struct amd_pm_funcs swsmu_pm_funcs = { 2918 /* export for sysfs */ 2919 .set_fan_control_mode = smu_set_fan_control_mode, 2920 .get_fan_control_mode = smu_get_fan_control_mode, 2921 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 2922 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 2923 .force_clock_level = smu_force_ppclk_levels, 2924 .print_clock_levels = smu_print_ppclk_levels, 2925 .emit_clock_levels = smu_emit_ppclk_levels, 2926 .force_performance_level = smu_force_performance_level, 2927 .read_sensor = smu_read_sensor, 2928 .get_performance_level = smu_get_performance_level, 2929 .get_current_power_state = smu_get_current_power_state, 2930 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 2931 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 2932 .get_pp_num_states = smu_get_power_num_states, 2933 .get_pp_table = smu_sys_get_pp_table, 2934 .set_pp_table = smu_sys_set_pp_table, 2935 .switch_power_profile = smu_switch_power_profile, 2936 /* export to amdgpu */ 2937 .dispatch_tasks = smu_handle_dpm_task, 2938 .load_firmware = smu_load_microcode, 2939 .set_powergating_by_smu = smu_dpm_set_power_gate, 2940 .set_power_limit = smu_set_power_limit, 2941 .get_power_limit = smu_get_power_limit, 2942 .get_power_profile_mode = smu_get_power_profile_mode, 2943 .set_power_profile_mode = smu_set_power_profile_mode, 2944 .odn_edit_dpm_table = smu_od_edit_dpm_table, 2945 .set_mp1_state = smu_set_mp1_state, 2946 .gfx_state_change_set = smu_gfx_state_change_set, 2947 /* export to DC */ 2948 .get_sclk = smu_get_sclk, 2949 .get_mclk = smu_get_mclk, 2950 .display_configuration_change = smu_display_configuration_change, 2951 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 2952 .display_clock_voltage_request = smu_display_clock_voltage_request, 2953 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 2954 .set_active_display_count = smu_set_display_count, 2955 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 2956 .get_asic_baco_capability = smu_get_baco_capability, 2957 .set_asic_baco_state = smu_baco_set_state, 2958 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 2959 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 2960 .asic_reset_mode_2 = smu_mode2_reset, 2961 .set_df_cstate = smu_set_df_cstate, 2962 .set_xgmi_pstate = smu_set_xgmi_pstate, 2963 .get_gpu_metrics = smu_sys_get_gpu_metrics, 2964 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 2965 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 2966 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 2967 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 2968 .get_dpm_clock_table = smu_get_dpm_clock_table, 2969 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 2970 }; 2971 2972 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 2973 uint64_t event_arg) 2974 { 2975 int ret = -EINVAL; 2976 2977 if (smu->ppt_funcs->wait_for_event) 2978 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 2979 2980 return ret; 2981 } 2982 2983 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 2984 { 2985 2986 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 2987 return -EOPNOTSUPP; 2988 2989 /* Confirm the buffer allocated is of correct size */ 2990 if (size != smu->stb_context.stb_buf_size) 2991 return -EINVAL; 2992 2993 /* 2994 * No need to lock smu mutex as we access STB directly through MMIO 2995 * and not going through SMU messaging route (for now at least). 2996 * For registers access rely on implementation internal locking. 2997 */ 2998 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 2999 } 3000 3001 #if defined(CONFIG_DEBUG_FS) 3002 3003 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3004 { 3005 struct amdgpu_device *adev = filp->f_inode->i_private; 3006 struct smu_context *smu = adev->powerplay.pp_handle; 3007 unsigned char *buf; 3008 int r; 3009 3010 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3011 if (!buf) 3012 return -ENOMEM; 3013 3014 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3015 if (r) 3016 goto out; 3017 3018 filp->private_data = buf; 3019 3020 return 0; 3021 3022 out: 3023 kvfree(buf); 3024 return r; 3025 } 3026 3027 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3028 loff_t *pos) 3029 { 3030 struct amdgpu_device *adev = filp->f_inode->i_private; 3031 struct smu_context *smu = adev->powerplay.pp_handle; 3032 3033 3034 if (!filp->private_data) 3035 return -EINVAL; 3036 3037 return simple_read_from_buffer(buf, 3038 size, 3039 pos, filp->private_data, 3040 smu->stb_context.stb_buf_size); 3041 } 3042 3043 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3044 { 3045 kvfree(filp->private_data); 3046 filp->private_data = NULL; 3047 3048 return 0; 3049 } 3050 3051 /* 3052 * We have to define not only read method but also 3053 * open and release because .read takes up to PAGE_SIZE 3054 * data each time so and so is invoked multiple times. 3055 * We allocate the STB buffer in .open and release it 3056 * in .release 3057 */ 3058 static const struct file_operations smu_stb_debugfs_fops = { 3059 .owner = THIS_MODULE, 3060 .open = smu_stb_debugfs_open, 3061 .read = smu_stb_debugfs_read, 3062 .release = smu_stb_debugfs_release, 3063 .llseek = default_llseek, 3064 }; 3065 3066 #endif 3067 3068 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3069 { 3070 #if defined(CONFIG_DEBUG_FS) 3071 3072 struct smu_context *smu = adev->powerplay.pp_handle; 3073 3074 if (!smu || (!smu->stb_context.stb_buf_size)) 3075 return; 3076 3077 debugfs_create_file_size("amdgpu_smu_stb_dump", 3078 S_IRUSR, 3079 adev_to_drm(adev)->primary->debugfs_root, 3080 adev, 3081 &smu_stb_debugfs_fops, 3082 smu->stb_context.stb_buf_size); 3083 #endif 3084 } 3085 3086 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3087 { 3088 int ret = 0; 3089 3090 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3091 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3092 3093 return ret; 3094 } 3095 3096 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3097 { 3098 int ret = 0; 3099 3100 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3101 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3102 3103 return ret; 3104 } 3105