1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "aldebaran_ppt.h" 38 #include "yellow_carp_ppt.h" 39 #include "cyan_skillfish_ppt.h" 40 #include "smu_v13_0_0_ppt.h" 41 #include "smu_v13_0_4_ppt.h" 42 #include "smu_v13_0_5_ppt.h" 43 #include "smu_v13_0_7_ppt.h" 44 #include "amd_pcie.h" 45 46 /* 47 * DO NOT use these for err/warn/info/debug messages. 48 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 49 * They are more MGPU friendly. 50 */ 51 #undef pr_err 52 #undef pr_warn 53 #undef pr_info 54 #undef pr_debug 55 56 static const struct amd_pm_funcs swsmu_pm_funcs; 57 static int smu_force_smuclk_levels(struct smu_context *smu, 58 enum smu_clk_type clk_type, 59 uint32_t mask); 60 static int smu_handle_task(struct smu_context *smu, 61 enum amd_dpm_forced_level level, 62 enum amd_pp_task task_id); 63 static int smu_reset(struct smu_context *smu); 64 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 65 static int smu_set_fan_control_mode(void *handle, u32 value); 66 static int smu_set_power_limit(void *handle, uint32_t limit); 67 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 68 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 69 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 70 71 static int smu_sys_get_pp_feature_mask(void *handle, 72 char *buf) 73 { 74 struct smu_context *smu = handle; 75 76 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 77 return -EOPNOTSUPP; 78 79 return smu_get_pp_feature_mask(smu, buf); 80 } 81 82 static int smu_sys_set_pp_feature_mask(void *handle, 83 uint64_t new_mask) 84 { 85 struct smu_context *smu = handle; 86 87 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 88 return -EOPNOTSUPP; 89 90 return smu_set_pp_feature_mask(smu, new_mask); 91 } 92 93 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 94 { 95 if (!smu->ppt_funcs->set_gfx_off_residency) 96 return -EINVAL; 97 98 return smu_set_gfx_off_residency(smu, value); 99 } 100 101 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 102 { 103 if (!smu->ppt_funcs->get_gfx_off_residency) 104 return -EINVAL; 105 106 return smu_get_gfx_off_residency(smu, value); 107 } 108 109 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 110 { 111 if (!smu->ppt_funcs->get_gfx_off_entrycount) 112 return -EINVAL; 113 114 return smu_get_gfx_off_entrycount(smu, value); 115 } 116 117 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 118 { 119 if (!smu->ppt_funcs->get_gfx_off_status) 120 return -EINVAL; 121 122 *value = smu_get_gfx_off_status(smu); 123 124 return 0; 125 } 126 127 int smu_set_soft_freq_range(struct smu_context *smu, 128 enum smu_clk_type clk_type, 129 uint32_t min, 130 uint32_t max) 131 { 132 int ret = 0; 133 134 if (smu->ppt_funcs->set_soft_freq_limited_range) 135 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 136 clk_type, 137 min, 138 max); 139 140 return ret; 141 } 142 143 int smu_get_dpm_freq_range(struct smu_context *smu, 144 enum smu_clk_type clk_type, 145 uint32_t *min, 146 uint32_t *max) 147 { 148 int ret = -ENOTSUPP; 149 150 if (!min && !max) 151 return -EINVAL; 152 153 if (smu->ppt_funcs->get_dpm_ultimate_freq) 154 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 155 clk_type, 156 min, 157 max); 158 159 return ret; 160 } 161 162 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 163 { 164 if (!smu->ppt_funcs && !smu->ppt_funcs->set_gfx_power_up_by_imu) 165 return -EOPNOTSUPP; 166 167 return smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 168 } 169 170 static u32 smu_get_mclk(void *handle, bool low) 171 { 172 struct smu_context *smu = handle; 173 uint32_t clk_freq; 174 int ret = 0; 175 176 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 177 low ? &clk_freq : NULL, 178 !low ? &clk_freq : NULL); 179 if (ret) 180 return 0; 181 return clk_freq * 100; 182 } 183 184 static u32 smu_get_sclk(void *handle, bool low) 185 { 186 struct smu_context *smu = handle; 187 uint32_t clk_freq; 188 int ret = 0; 189 190 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 191 low ? &clk_freq : NULL, 192 !low ? &clk_freq : NULL); 193 if (ret) 194 return 0; 195 return clk_freq * 100; 196 } 197 198 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 199 bool enable) 200 { 201 struct smu_power_context *smu_power = &smu->smu_power; 202 struct smu_power_gate *power_gate = &smu_power->power_gate; 203 int ret = 0; 204 205 if (!smu->ppt_funcs->dpm_set_vcn_enable) 206 return 0; 207 208 if (atomic_read(&power_gate->vcn_gated) ^ enable) 209 return 0; 210 211 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 212 if (!ret) 213 atomic_set(&power_gate->vcn_gated, !enable); 214 215 return ret; 216 } 217 218 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 219 bool enable) 220 { 221 struct smu_power_context *smu_power = &smu->smu_power; 222 struct smu_power_gate *power_gate = &smu_power->power_gate; 223 int ret = 0; 224 225 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 226 return 0; 227 228 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 229 return 0; 230 231 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 232 if (!ret) 233 atomic_set(&power_gate->jpeg_gated, !enable); 234 235 return ret; 236 } 237 238 /** 239 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 240 * 241 * @handle: smu_context pointer 242 * @block_type: the IP block to power gate/ungate 243 * @gate: to power gate if true, ungate otherwise 244 * 245 * This API uses no smu->mutex lock protection due to: 246 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 247 * This is guarded to be race condition free by the caller. 248 * 2. Or get called on user setting request of power_dpm_force_performance_level. 249 * Under this case, the smu->mutex lock protection is already enforced on 250 * the parent API smu_force_performance_level of the call path. 251 */ 252 static int smu_dpm_set_power_gate(void *handle, 253 uint32_t block_type, 254 bool gate) 255 { 256 struct smu_context *smu = handle; 257 int ret = 0; 258 259 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 260 dev_WARN(smu->adev->dev, 261 "SMU uninitialized but power %s requested for %u!\n", 262 gate ? "gate" : "ungate", block_type); 263 return -EOPNOTSUPP; 264 } 265 266 switch (block_type) { 267 /* 268 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 269 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 270 */ 271 case AMD_IP_BLOCK_TYPE_UVD: 272 case AMD_IP_BLOCK_TYPE_VCN: 273 ret = smu_dpm_set_vcn_enable(smu, !gate); 274 if (ret) 275 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 276 gate ? "gate" : "ungate"); 277 break; 278 case AMD_IP_BLOCK_TYPE_GFX: 279 ret = smu_gfx_off_control(smu, gate); 280 if (ret) 281 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 282 gate ? "enable" : "disable"); 283 break; 284 case AMD_IP_BLOCK_TYPE_SDMA: 285 ret = smu_powergate_sdma(smu, gate); 286 if (ret) 287 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 288 gate ? "gate" : "ungate"); 289 break; 290 case AMD_IP_BLOCK_TYPE_JPEG: 291 ret = smu_dpm_set_jpeg_enable(smu, !gate); 292 if (ret) 293 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 294 gate ? "gate" : "ungate"); 295 break; 296 default: 297 dev_err(smu->adev->dev, "Unsupported block type!\n"); 298 return -EINVAL; 299 } 300 301 return ret; 302 } 303 304 /** 305 * smu_set_user_clk_dependencies - set user profile clock dependencies 306 * 307 * @smu: smu_context pointer 308 * @clk: enum smu_clk_type type 309 * 310 * Enable/Disable the clock dependency for the @clk type. 311 */ 312 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 313 { 314 if (smu->adev->in_suspend) 315 return; 316 317 if (clk == SMU_MCLK) { 318 smu->user_dpm_profile.clk_dependency = 0; 319 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 320 } else if (clk == SMU_FCLK) { 321 /* MCLK takes precedence over FCLK */ 322 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 323 return; 324 325 smu->user_dpm_profile.clk_dependency = 0; 326 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 327 } else if (clk == SMU_SOCCLK) { 328 /* MCLK takes precedence over SOCCLK */ 329 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 330 return; 331 332 smu->user_dpm_profile.clk_dependency = 0; 333 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 334 } else 335 /* Add clk dependencies here, if any */ 336 return; 337 } 338 339 /** 340 * smu_restore_dpm_user_profile - reinstate user dpm profile 341 * 342 * @smu: smu_context pointer 343 * 344 * Restore the saved user power configurations include power limit, 345 * clock frequencies, fan control mode and fan speed. 346 */ 347 static void smu_restore_dpm_user_profile(struct smu_context *smu) 348 { 349 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 350 int ret = 0; 351 352 if (!smu->adev->in_suspend) 353 return; 354 355 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 356 return; 357 358 /* Enable restore flag */ 359 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 360 361 /* set the user dpm power limit */ 362 if (smu->user_dpm_profile.power_limit) { 363 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 364 if (ret) 365 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 366 } 367 368 /* set the user dpm clock configurations */ 369 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 370 enum smu_clk_type clk_type; 371 372 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 373 /* 374 * Iterate over smu clk type and force the saved user clk 375 * configs, skip if clock dependency is enabled 376 */ 377 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 378 smu->user_dpm_profile.clk_mask[clk_type]) { 379 ret = smu_force_smuclk_levels(smu, clk_type, 380 smu->user_dpm_profile.clk_mask[clk_type]); 381 if (ret) 382 dev_err(smu->adev->dev, 383 "Failed to set clock type = %d\n", clk_type); 384 } 385 } 386 } 387 388 /* set the user dpm fan configurations */ 389 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 390 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 391 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 392 if (ret != -EOPNOTSUPP) { 393 smu->user_dpm_profile.fan_speed_pwm = 0; 394 smu->user_dpm_profile.fan_speed_rpm = 0; 395 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 396 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 397 } 398 399 if (smu->user_dpm_profile.fan_speed_pwm) { 400 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 401 if (ret != -EOPNOTSUPP) 402 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 403 } 404 405 if (smu->user_dpm_profile.fan_speed_rpm) { 406 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 407 if (ret != -EOPNOTSUPP) 408 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 409 } 410 } 411 412 /* Restore user customized OD settings */ 413 if (smu->user_dpm_profile.user_od) { 414 if (smu->ppt_funcs->restore_user_od_settings) { 415 ret = smu->ppt_funcs->restore_user_od_settings(smu); 416 if (ret) 417 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 418 } 419 } 420 421 /* Disable restore flag */ 422 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 423 } 424 425 static int smu_get_power_num_states(void *handle, 426 struct pp_states_info *state_info) 427 { 428 if (!state_info) 429 return -EINVAL; 430 431 /* not support power state */ 432 memset(state_info, 0, sizeof(struct pp_states_info)); 433 state_info->nums = 1; 434 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 435 436 return 0; 437 } 438 439 bool is_support_sw_smu(struct amdgpu_device *adev) 440 { 441 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 442 if (adev->asic_type == CHIP_VEGA20) 443 return false; 444 445 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0)) 446 return true; 447 448 return false; 449 } 450 451 bool is_support_cclk_dpm(struct amdgpu_device *adev) 452 { 453 struct smu_context *smu = adev->powerplay.pp_handle; 454 455 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 456 return false; 457 458 return true; 459 } 460 461 462 static int smu_sys_get_pp_table(void *handle, 463 char **table) 464 { 465 struct smu_context *smu = handle; 466 struct smu_table_context *smu_table = &smu->smu_table; 467 468 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 469 return -EOPNOTSUPP; 470 471 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 472 return -EINVAL; 473 474 if (smu_table->hardcode_pptable) 475 *table = smu_table->hardcode_pptable; 476 else 477 *table = smu_table->power_play_table; 478 479 return smu_table->power_play_table_size; 480 } 481 482 static int smu_sys_set_pp_table(void *handle, 483 const char *buf, 484 size_t size) 485 { 486 struct smu_context *smu = handle; 487 struct smu_table_context *smu_table = &smu->smu_table; 488 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 489 int ret = 0; 490 491 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 492 return -EOPNOTSUPP; 493 494 if (header->usStructureSize != size) { 495 dev_err(smu->adev->dev, "pp table size not matched !\n"); 496 return -EIO; 497 } 498 499 if (!smu_table->hardcode_pptable) { 500 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 501 if (!smu_table->hardcode_pptable) 502 return -ENOMEM; 503 } 504 505 memcpy(smu_table->hardcode_pptable, buf, size); 506 smu_table->power_play_table = smu_table->hardcode_pptable; 507 smu_table->power_play_table_size = size; 508 509 /* 510 * Special hw_fini action(for Navi1x, the DPMs disablement will be 511 * skipped) may be needed for custom pptable uploading. 512 */ 513 smu->uploading_custom_pp_table = true; 514 515 ret = smu_reset(smu); 516 if (ret) 517 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 518 519 smu->uploading_custom_pp_table = false; 520 521 return ret; 522 } 523 524 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 525 { 526 struct smu_feature *feature = &smu->smu_feature; 527 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 528 int ret = 0; 529 530 /* 531 * With SCPM enabled, the allowed featuremasks setting(via 532 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 533 * That means there is no way to let PMFW knows the settings below. 534 * Thus, we just assume all the features are allowed under 535 * such scenario. 536 */ 537 if (smu->adev->scpm_enabled) { 538 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 539 return 0; 540 } 541 542 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 543 544 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 545 SMU_FEATURE_MAX/32); 546 if (ret) 547 return ret; 548 549 bitmap_or(feature->allowed, feature->allowed, 550 (unsigned long *)allowed_feature_mask, 551 feature->feature_num); 552 553 return ret; 554 } 555 556 static int smu_set_funcs(struct amdgpu_device *adev) 557 { 558 struct smu_context *smu = adev->powerplay.pp_handle; 559 560 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 561 smu->od_enabled = true; 562 563 switch (adev->ip_versions[MP1_HWIP][0]) { 564 case IP_VERSION(11, 0, 0): 565 case IP_VERSION(11, 0, 5): 566 case IP_VERSION(11, 0, 9): 567 navi10_set_ppt_funcs(smu); 568 break; 569 case IP_VERSION(11, 0, 7): 570 case IP_VERSION(11, 0, 11): 571 case IP_VERSION(11, 0, 12): 572 case IP_VERSION(11, 0, 13): 573 sienna_cichlid_set_ppt_funcs(smu); 574 break; 575 case IP_VERSION(12, 0, 0): 576 case IP_VERSION(12, 0, 1): 577 renoir_set_ppt_funcs(smu); 578 break; 579 case IP_VERSION(11, 5, 0): 580 vangogh_set_ppt_funcs(smu); 581 break; 582 case IP_VERSION(13, 0, 1): 583 case IP_VERSION(13, 0, 3): 584 case IP_VERSION(13, 0, 8): 585 yellow_carp_set_ppt_funcs(smu); 586 break; 587 case IP_VERSION(13, 0, 4): 588 smu_v13_0_4_set_ppt_funcs(smu); 589 break; 590 case IP_VERSION(13, 0, 5): 591 smu_v13_0_5_set_ppt_funcs(smu); 592 break; 593 case IP_VERSION(11, 0, 8): 594 cyan_skillfish_set_ppt_funcs(smu); 595 break; 596 case IP_VERSION(11, 0, 2): 597 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 598 arcturus_set_ppt_funcs(smu); 599 /* OD is not supported on Arcturus */ 600 smu->od_enabled =false; 601 break; 602 case IP_VERSION(13, 0, 2): 603 aldebaran_set_ppt_funcs(smu); 604 /* Enable pp_od_clk_voltage node */ 605 smu->od_enabled = true; 606 break; 607 case IP_VERSION(13, 0, 0): 608 case IP_VERSION(13, 0, 10): 609 smu_v13_0_0_set_ppt_funcs(smu); 610 break; 611 case IP_VERSION(13, 0, 7): 612 smu_v13_0_7_set_ppt_funcs(smu); 613 break; 614 default: 615 return -EINVAL; 616 } 617 618 return 0; 619 } 620 621 static int smu_early_init(void *handle) 622 { 623 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 624 struct smu_context *smu; 625 626 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 627 if (!smu) 628 return -ENOMEM; 629 630 smu->adev = adev; 631 smu->pm_enabled = !!amdgpu_dpm; 632 smu->is_apu = false; 633 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 634 smu->smu_baco.platform_support = false; 635 smu->user_dpm_profile.fan_mode = -1; 636 637 mutex_init(&smu->message_lock); 638 639 adev->powerplay.pp_handle = smu; 640 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 641 642 return smu_set_funcs(adev); 643 } 644 645 static int smu_set_default_dpm_table(struct smu_context *smu) 646 { 647 struct smu_power_context *smu_power = &smu->smu_power; 648 struct smu_power_gate *power_gate = &smu_power->power_gate; 649 int vcn_gate, jpeg_gate; 650 int ret = 0; 651 652 if (!smu->ppt_funcs->set_default_dpm_table) 653 return 0; 654 655 vcn_gate = atomic_read(&power_gate->vcn_gated); 656 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 657 658 ret = smu_dpm_set_vcn_enable(smu, true); 659 if (ret) 660 return ret; 661 662 ret = smu_dpm_set_jpeg_enable(smu, true); 663 if (ret) 664 goto err_out; 665 666 ret = smu->ppt_funcs->set_default_dpm_table(smu); 667 if (ret) 668 dev_err(smu->adev->dev, 669 "Failed to setup default dpm clock tables!\n"); 670 671 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 672 err_out: 673 smu_dpm_set_vcn_enable(smu, !vcn_gate); 674 return ret; 675 } 676 677 static int smu_apply_default_config_table_settings(struct smu_context *smu) 678 { 679 struct amdgpu_device *adev = smu->adev; 680 int ret = 0; 681 682 ret = smu_get_default_config_table_settings(smu, 683 &adev->pm.config_table); 684 if (ret) 685 return ret; 686 687 return smu_set_config_table(smu, &adev->pm.config_table); 688 } 689 690 static int smu_late_init(void *handle) 691 { 692 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 693 struct smu_context *smu = adev->powerplay.pp_handle; 694 int ret = 0; 695 696 smu_set_fine_grain_gfx_freq_parameters(smu); 697 698 if (!smu->pm_enabled) 699 return 0; 700 701 ret = smu_post_init(smu); 702 if (ret) { 703 dev_err(adev->dev, "Failed to post smu init!\n"); 704 return ret; 705 } 706 707 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || 708 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) 709 return 0; 710 711 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 712 ret = smu_set_default_od_settings(smu); 713 if (ret) { 714 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 715 return ret; 716 } 717 } 718 719 ret = smu_populate_umd_state_clk(smu); 720 if (ret) { 721 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 722 return ret; 723 } 724 725 ret = smu_get_asic_power_limits(smu, 726 &smu->current_power_limit, 727 &smu->default_power_limit, 728 &smu->max_power_limit); 729 if (ret) { 730 dev_err(adev->dev, "Failed to get asic power limits!\n"); 731 return ret; 732 } 733 734 if (!amdgpu_sriov_vf(adev)) 735 smu_get_unique_id(smu); 736 737 smu_get_fan_parameters(smu); 738 739 smu_handle_task(smu, 740 smu->smu_dpm.dpm_level, 741 AMD_PP_TASK_COMPLETE_INIT); 742 743 ret = smu_apply_default_config_table_settings(smu); 744 if (ret && (ret != -EOPNOTSUPP)) { 745 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 746 return ret; 747 } 748 749 smu_restore_dpm_user_profile(smu); 750 751 return 0; 752 } 753 754 static int smu_init_fb_allocations(struct smu_context *smu) 755 { 756 struct amdgpu_device *adev = smu->adev; 757 struct smu_table_context *smu_table = &smu->smu_table; 758 struct smu_table *tables = smu_table->tables; 759 struct smu_table *driver_table = &(smu_table->driver_table); 760 uint32_t max_table_size = 0; 761 int ret, i; 762 763 /* VRAM allocation for tool table */ 764 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 765 ret = amdgpu_bo_create_kernel(adev, 766 tables[SMU_TABLE_PMSTATUSLOG].size, 767 tables[SMU_TABLE_PMSTATUSLOG].align, 768 tables[SMU_TABLE_PMSTATUSLOG].domain, 769 &tables[SMU_TABLE_PMSTATUSLOG].bo, 770 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 771 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 772 if (ret) { 773 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 774 return ret; 775 } 776 } 777 778 /* VRAM allocation for driver table */ 779 for (i = 0; i < SMU_TABLE_COUNT; i++) { 780 if (tables[i].size == 0) 781 continue; 782 783 if (i == SMU_TABLE_PMSTATUSLOG) 784 continue; 785 786 if (max_table_size < tables[i].size) 787 max_table_size = tables[i].size; 788 } 789 790 driver_table->size = max_table_size; 791 driver_table->align = PAGE_SIZE; 792 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 793 794 ret = amdgpu_bo_create_kernel(adev, 795 driver_table->size, 796 driver_table->align, 797 driver_table->domain, 798 &driver_table->bo, 799 &driver_table->mc_address, 800 &driver_table->cpu_addr); 801 if (ret) { 802 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 803 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 804 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 805 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 806 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 807 } 808 809 return ret; 810 } 811 812 static int smu_fini_fb_allocations(struct smu_context *smu) 813 { 814 struct smu_table_context *smu_table = &smu->smu_table; 815 struct smu_table *tables = smu_table->tables; 816 struct smu_table *driver_table = &(smu_table->driver_table); 817 818 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 819 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 820 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 821 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 822 823 amdgpu_bo_free_kernel(&driver_table->bo, 824 &driver_table->mc_address, 825 &driver_table->cpu_addr); 826 827 return 0; 828 } 829 830 /** 831 * smu_alloc_memory_pool - allocate memory pool in the system memory 832 * 833 * @smu: amdgpu_device pointer 834 * 835 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 836 * and DramLogSetDramAddr can notify it changed. 837 * 838 * Returns 0 on success, error on failure. 839 */ 840 static int smu_alloc_memory_pool(struct smu_context *smu) 841 { 842 struct amdgpu_device *adev = smu->adev; 843 struct smu_table_context *smu_table = &smu->smu_table; 844 struct smu_table *memory_pool = &smu_table->memory_pool; 845 uint64_t pool_size = smu->pool_size; 846 int ret = 0; 847 848 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 849 return ret; 850 851 memory_pool->size = pool_size; 852 memory_pool->align = PAGE_SIZE; 853 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 854 855 switch (pool_size) { 856 case SMU_MEMORY_POOL_SIZE_256_MB: 857 case SMU_MEMORY_POOL_SIZE_512_MB: 858 case SMU_MEMORY_POOL_SIZE_1_GB: 859 case SMU_MEMORY_POOL_SIZE_2_GB: 860 ret = amdgpu_bo_create_kernel(adev, 861 memory_pool->size, 862 memory_pool->align, 863 memory_pool->domain, 864 &memory_pool->bo, 865 &memory_pool->mc_address, 866 &memory_pool->cpu_addr); 867 if (ret) 868 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 869 break; 870 default: 871 break; 872 } 873 874 return ret; 875 } 876 877 static int smu_free_memory_pool(struct smu_context *smu) 878 { 879 struct smu_table_context *smu_table = &smu->smu_table; 880 struct smu_table *memory_pool = &smu_table->memory_pool; 881 882 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 883 return 0; 884 885 amdgpu_bo_free_kernel(&memory_pool->bo, 886 &memory_pool->mc_address, 887 &memory_pool->cpu_addr); 888 889 memset(memory_pool, 0, sizeof(struct smu_table)); 890 891 return 0; 892 } 893 894 static int smu_alloc_dummy_read_table(struct smu_context *smu) 895 { 896 struct smu_table_context *smu_table = &smu->smu_table; 897 struct smu_table *dummy_read_1_table = 898 &smu_table->dummy_read_1_table; 899 struct amdgpu_device *adev = smu->adev; 900 int ret = 0; 901 902 dummy_read_1_table->size = 0x40000; 903 dummy_read_1_table->align = PAGE_SIZE; 904 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 905 906 ret = amdgpu_bo_create_kernel(adev, 907 dummy_read_1_table->size, 908 dummy_read_1_table->align, 909 dummy_read_1_table->domain, 910 &dummy_read_1_table->bo, 911 &dummy_read_1_table->mc_address, 912 &dummy_read_1_table->cpu_addr); 913 if (ret) 914 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 915 916 return ret; 917 } 918 919 static void smu_free_dummy_read_table(struct smu_context *smu) 920 { 921 struct smu_table_context *smu_table = &smu->smu_table; 922 struct smu_table *dummy_read_1_table = 923 &smu_table->dummy_read_1_table; 924 925 926 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 927 &dummy_read_1_table->mc_address, 928 &dummy_read_1_table->cpu_addr); 929 930 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 931 } 932 933 static int smu_smc_table_sw_init(struct smu_context *smu) 934 { 935 int ret; 936 937 /** 938 * Create smu_table structure, and init smc tables such as 939 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 940 */ 941 ret = smu_init_smc_tables(smu); 942 if (ret) { 943 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 944 return ret; 945 } 946 947 /** 948 * Create smu_power_context structure, and allocate smu_dpm_context and 949 * context size to fill the smu_power_context data. 950 */ 951 ret = smu_init_power(smu); 952 if (ret) { 953 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 954 return ret; 955 } 956 957 /* 958 * allocate vram bos to store smc table contents. 959 */ 960 ret = smu_init_fb_allocations(smu); 961 if (ret) 962 return ret; 963 964 ret = smu_alloc_memory_pool(smu); 965 if (ret) 966 return ret; 967 968 ret = smu_alloc_dummy_read_table(smu); 969 if (ret) 970 return ret; 971 972 ret = smu_i2c_init(smu); 973 if (ret) 974 return ret; 975 976 return 0; 977 } 978 979 static int smu_smc_table_sw_fini(struct smu_context *smu) 980 { 981 int ret; 982 983 smu_i2c_fini(smu); 984 985 smu_free_dummy_read_table(smu); 986 987 ret = smu_free_memory_pool(smu); 988 if (ret) 989 return ret; 990 991 ret = smu_fini_fb_allocations(smu); 992 if (ret) 993 return ret; 994 995 ret = smu_fini_power(smu); 996 if (ret) { 997 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 998 return ret; 999 } 1000 1001 ret = smu_fini_smc_tables(smu); 1002 if (ret) { 1003 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1004 return ret; 1005 } 1006 1007 return 0; 1008 } 1009 1010 static void smu_throttling_logging_work_fn(struct work_struct *work) 1011 { 1012 struct smu_context *smu = container_of(work, struct smu_context, 1013 throttling_logging_work); 1014 1015 smu_log_thermal_throttling(smu); 1016 } 1017 1018 static void smu_interrupt_work_fn(struct work_struct *work) 1019 { 1020 struct smu_context *smu = container_of(work, struct smu_context, 1021 interrupt_work); 1022 1023 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1024 smu->ppt_funcs->interrupt_work(smu); 1025 } 1026 1027 static int smu_sw_init(void *handle) 1028 { 1029 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1030 struct smu_context *smu = adev->powerplay.pp_handle; 1031 int ret; 1032 1033 smu->pool_size = adev->pm.smu_prv_buffer_size; 1034 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1035 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1036 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1037 1038 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1039 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1040 atomic64_set(&smu->throttle_int_counter, 0); 1041 smu->watermarks_bitmap = 0; 1042 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1043 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1044 1045 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1046 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1047 1048 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1049 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1050 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1051 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1052 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1053 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1054 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1055 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1056 1057 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1058 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1059 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1060 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1061 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1062 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1063 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1064 smu->display_config = &adev->pm.pm_display_cfg; 1065 1066 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1067 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1068 1069 ret = smu_init_microcode(smu); 1070 if (ret) { 1071 dev_err(adev->dev, "Failed to load smu firmware!\n"); 1072 return ret; 1073 } 1074 1075 ret = smu_smc_table_sw_init(smu); 1076 if (ret) { 1077 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1078 return ret; 1079 } 1080 1081 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1082 ret = smu_get_vbios_bootup_values(smu); 1083 if (ret) { 1084 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1085 return ret; 1086 } 1087 1088 ret = smu_init_pptable_microcode(smu); 1089 if (ret) { 1090 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1091 return ret; 1092 } 1093 1094 ret = smu_register_irq_handler(smu); 1095 if (ret) { 1096 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1097 return ret; 1098 } 1099 1100 /* If there is no way to query fan control mode, fan control is not supported */ 1101 if (!smu->ppt_funcs->get_fan_control_mode) 1102 smu->adev->pm.no_fan = true; 1103 1104 return 0; 1105 } 1106 1107 static int smu_sw_fini(void *handle) 1108 { 1109 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1110 struct smu_context *smu = adev->powerplay.pp_handle; 1111 int ret; 1112 1113 ret = smu_smc_table_sw_fini(smu); 1114 if (ret) { 1115 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1116 return ret; 1117 } 1118 1119 smu_fini_microcode(smu); 1120 1121 return 0; 1122 } 1123 1124 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1125 { 1126 struct amdgpu_device *adev = smu->adev; 1127 struct smu_temperature_range *range = 1128 &smu->thermal_range; 1129 int ret = 0; 1130 1131 if (!smu->ppt_funcs->get_thermal_temperature_range) 1132 return 0; 1133 1134 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1135 if (ret) 1136 return ret; 1137 1138 adev->pm.dpm.thermal.min_temp = range->min; 1139 adev->pm.dpm.thermal.max_temp = range->max; 1140 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1141 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1142 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1143 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1144 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1145 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1146 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1147 1148 return ret; 1149 } 1150 1151 static int smu_smc_hw_setup(struct smu_context *smu) 1152 { 1153 struct smu_feature *feature = &smu->smu_feature; 1154 struct amdgpu_device *adev = smu->adev; 1155 uint32_t pcie_gen = 0, pcie_width = 0; 1156 uint64_t features_supported; 1157 int ret = 0; 1158 1159 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1160 dev_info(adev->dev, "dpm has been enabled\n"); 1161 /* this is needed specifically */ 1162 switch (adev->ip_versions[MP1_HWIP][0]) { 1163 case IP_VERSION(11, 0, 7): 1164 case IP_VERSION(11, 0, 11): 1165 case IP_VERSION(11, 5, 0): 1166 case IP_VERSION(11, 0, 12): 1167 ret = smu_system_features_control(smu, true); 1168 if (ret) 1169 dev_err(adev->dev, "Failed system features control!\n"); 1170 break; 1171 default: 1172 break; 1173 } 1174 return ret; 1175 } 1176 1177 ret = smu_init_display_count(smu, 0); 1178 if (ret) { 1179 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1180 return ret; 1181 } 1182 1183 ret = smu_set_driver_table_location(smu); 1184 if (ret) { 1185 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1186 return ret; 1187 } 1188 1189 /* 1190 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1191 */ 1192 ret = smu_set_tool_table_location(smu); 1193 if (ret) { 1194 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1195 return ret; 1196 } 1197 1198 /* 1199 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1200 * pool location. 1201 */ 1202 ret = smu_notify_memory_pool_location(smu); 1203 if (ret) { 1204 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1205 return ret; 1206 } 1207 1208 ret = smu_setup_pptable(smu); 1209 if (ret) { 1210 dev_err(adev->dev, "Failed to setup pptable!\n"); 1211 return ret; 1212 } 1213 1214 /* smu_dump_pptable(smu); */ 1215 1216 /* 1217 * With SCPM enabled, PSP is responsible for the PPTable transferring 1218 * (to SMU). Driver involvement is not needed and permitted. 1219 */ 1220 if (!adev->scpm_enabled) { 1221 /* 1222 * Copy pptable bo in the vram to smc with SMU MSGs such as 1223 * SetDriverDramAddr and TransferTableDram2Smu. 1224 */ 1225 ret = smu_write_pptable(smu); 1226 if (ret) { 1227 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1228 return ret; 1229 } 1230 } 1231 1232 /* issue Run*Btc msg */ 1233 ret = smu_run_btc(smu); 1234 if (ret) 1235 return ret; 1236 1237 /* 1238 * With SCPM enabled, these actions(and relevant messages) are 1239 * not needed and permitted. 1240 */ 1241 if (!adev->scpm_enabled) { 1242 ret = smu_feature_set_allowed_mask(smu); 1243 if (ret) { 1244 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1245 return ret; 1246 } 1247 } 1248 1249 ret = smu_system_features_control(smu, true); 1250 if (ret) { 1251 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1252 return ret; 1253 } 1254 1255 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1256 if (ret) { 1257 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1258 return ret; 1259 } 1260 bitmap_copy(feature->supported, 1261 (unsigned long *)&features_supported, 1262 feature->feature_num); 1263 1264 if (!smu_is_dpm_running(smu)) 1265 dev_info(adev->dev, "dpm has been disabled\n"); 1266 1267 /* 1268 * Set initialized values (get from vbios) to dpm tables context such as 1269 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1270 * type of clks. 1271 */ 1272 ret = smu_set_default_dpm_table(smu); 1273 if (ret) { 1274 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1275 return ret; 1276 } 1277 1278 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1279 pcie_gen = 3; 1280 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1281 pcie_gen = 2; 1282 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1283 pcie_gen = 1; 1284 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1285 pcie_gen = 0; 1286 1287 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1288 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1289 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1290 */ 1291 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1292 pcie_width = 6; 1293 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1294 pcie_width = 5; 1295 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1296 pcie_width = 4; 1297 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1298 pcie_width = 3; 1299 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1300 pcie_width = 2; 1301 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1302 pcie_width = 1; 1303 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1304 if (ret) { 1305 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1306 return ret; 1307 } 1308 1309 ret = smu_get_thermal_temperature_range(smu); 1310 if (ret) { 1311 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1312 return ret; 1313 } 1314 1315 ret = smu_enable_thermal_alert(smu); 1316 if (ret) { 1317 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1318 return ret; 1319 } 1320 1321 ret = smu_notify_display_change(smu); 1322 if (ret) { 1323 dev_err(adev->dev, "Failed to notify display change!\n"); 1324 return ret; 1325 } 1326 1327 /* 1328 * Set min deep sleep dce fclk with bootup value from vbios via 1329 * SetMinDeepSleepDcefclk MSG. 1330 */ 1331 ret = smu_set_min_dcef_deep_sleep(smu, 1332 smu->smu_table.boot_values.dcefclk / 100); 1333 1334 return ret; 1335 } 1336 1337 static int smu_start_smc_engine(struct smu_context *smu) 1338 { 1339 struct amdgpu_device *adev = smu->adev; 1340 int ret = 0; 1341 1342 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1343 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) { 1344 if (smu->ppt_funcs->load_microcode) { 1345 ret = smu->ppt_funcs->load_microcode(smu); 1346 if (ret) 1347 return ret; 1348 } 1349 } 1350 } 1351 1352 if (smu->ppt_funcs->check_fw_status) { 1353 ret = smu->ppt_funcs->check_fw_status(smu); 1354 if (ret) { 1355 dev_err(adev->dev, "SMC is not ready\n"); 1356 return ret; 1357 } 1358 } 1359 1360 /* 1361 * Send msg GetDriverIfVersion to check if the return value is equal 1362 * with DRIVER_IF_VERSION of smc header. 1363 */ 1364 ret = smu_check_fw_version(smu); 1365 if (ret) 1366 return ret; 1367 1368 return ret; 1369 } 1370 1371 static int smu_hw_init(void *handle) 1372 { 1373 int ret; 1374 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1375 struct smu_context *smu = adev->powerplay.pp_handle; 1376 1377 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1378 smu->pm_enabled = false; 1379 return 0; 1380 } 1381 1382 ret = smu_start_smc_engine(smu); 1383 if (ret) { 1384 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1385 return ret; 1386 } 1387 1388 if (smu->is_apu) { 1389 if ((smu->ppt_funcs->set_gfx_power_up_by_imu) && 1390 likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 1391 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 1392 if (ret) { 1393 dev_err(adev->dev, "Failed to Enable gfx imu!\n"); 1394 return ret; 1395 } 1396 } 1397 1398 smu_dpm_set_vcn_enable(smu, true); 1399 smu_dpm_set_jpeg_enable(smu, true); 1400 smu_set_gfx_cgpg(smu, true); 1401 } 1402 1403 if (!smu->pm_enabled) 1404 return 0; 1405 1406 ret = smu_get_driver_allowed_feature_mask(smu); 1407 if (ret) 1408 return ret; 1409 1410 ret = smu_smc_hw_setup(smu); 1411 if (ret) { 1412 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1413 return ret; 1414 } 1415 1416 /* 1417 * Move maximum sustainable clock retrieving here considering 1418 * 1. It is not needed on resume(from S3). 1419 * 2. DAL settings come between .hw_init and .late_init of SMU. 1420 * And DAL needs to know the maximum sustainable clocks. Thus 1421 * it cannot be put in .late_init(). 1422 */ 1423 ret = smu_init_max_sustainable_clocks(smu); 1424 if (ret) { 1425 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1426 return ret; 1427 } 1428 1429 adev->pm.dpm_enabled = true; 1430 1431 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1432 1433 return 0; 1434 } 1435 1436 static int smu_disable_dpms(struct smu_context *smu) 1437 { 1438 struct amdgpu_device *adev = smu->adev; 1439 int ret = 0; 1440 bool use_baco = !smu->is_apu && 1441 ((amdgpu_in_reset(adev) && 1442 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1443 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1444 1445 /* 1446 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1447 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1448 */ 1449 switch (adev->ip_versions[MP1_HWIP][0]) { 1450 case IP_VERSION(13, 0, 0): 1451 case IP_VERSION(13, 0, 7): 1452 return 0; 1453 default: 1454 break; 1455 } 1456 1457 /* 1458 * For custom pptable uploading, skip the DPM features 1459 * disable process on Navi1x ASICs. 1460 * - As the gfx related features are under control of 1461 * RLC on those ASICs. RLC reinitialization will be 1462 * needed to reenable them. That will cost much more 1463 * efforts. 1464 * 1465 * - SMU firmware can handle the DPM reenablement 1466 * properly. 1467 */ 1468 if (smu->uploading_custom_pp_table) { 1469 switch (adev->ip_versions[MP1_HWIP][0]) { 1470 case IP_VERSION(11, 0, 0): 1471 case IP_VERSION(11, 0, 5): 1472 case IP_VERSION(11, 0, 9): 1473 case IP_VERSION(11, 0, 7): 1474 case IP_VERSION(11, 0, 11): 1475 case IP_VERSION(11, 5, 0): 1476 case IP_VERSION(11, 0, 12): 1477 case IP_VERSION(11, 0, 13): 1478 return 0; 1479 default: 1480 break; 1481 } 1482 } 1483 1484 /* 1485 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1486 * on BACO in. Driver involvement is unnecessary. 1487 */ 1488 if (use_baco) { 1489 switch (adev->ip_versions[MP1_HWIP][0]) { 1490 case IP_VERSION(11, 0, 7): 1491 case IP_VERSION(11, 0, 0): 1492 case IP_VERSION(11, 0, 5): 1493 case IP_VERSION(11, 0, 9): 1494 case IP_VERSION(13, 0, 7): 1495 return 0; 1496 default: 1497 break; 1498 } 1499 } 1500 1501 /* 1502 * For gpu reset, runpm and hibernation through BACO, 1503 * BACO feature has to be kept enabled. 1504 */ 1505 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1506 ret = smu_disable_all_features_with_exception(smu, 1507 SMU_FEATURE_BACO_BIT); 1508 if (ret) 1509 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1510 } else { 1511 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1512 if (!adev->scpm_enabled) { 1513 ret = smu_system_features_control(smu, false); 1514 if (ret) 1515 dev_err(adev->dev, "Failed to disable smu features.\n"); 1516 } 1517 } 1518 1519 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) && 1520 adev->gfx.rlc.funcs->stop) 1521 adev->gfx.rlc.funcs->stop(adev); 1522 1523 return ret; 1524 } 1525 1526 static int smu_smc_hw_cleanup(struct smu_context *smu) 1527 { 1528 struct amdgpu_device *adev = smu->adev; 1529 int ret = 0; 1530 1531 cancel_work_sync(&smu->throttling_logging_work); 1532 cancel_work_sync(&smu->interrupt_work); 1533 1534 ret = smu_disable_thermal_alert(smu); 1535 if (ret) { 1536 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1537 return ret; 1538 } 1539 1540 ret = smu_disable_dpms(smu); 1541 if (ret) { 1542 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1543 return ret; 1544 } 1545 1546 return 0; 1547 } 1548 1549 static int smu_hw_fini(void *handle) 1550 { 1551 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1552 struct smu_context *smu = adev->powerplay.pp_handle; 1553 1554 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1555 return 0; 1556 1557 smu_dpm_set_vcn_enable(smu, false); 1558 smu_dpm_set_jpeg_enable(smu, false); 1559 1560 adev->vcn.cur_state = AMD_PG_STATE_GATE; 1561 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 1562 1563 if (!smu->pm_enabled) 1564 return 0; 1565 1566 adev->pm.dpm_enabled = false; 1567 1568 return smu_smc_hw_cleanup(smu); 1569 } 1570 1571 static void smu_late_fini(void *handle) 1572 { 1573 struct amdgpu_device *adev = handle; 1574 struct smu_context *smu = adev->powerplay.pp_handle; 1575 1576 kfree(smu); 1577 } 1578 1579 static int smu_reset(struct smu_context *smu) 1580 { 1581 struct amdgpu_device *adev = smu->adev; 1582 int ret; 1583 1584 ret = smu_hw_fini(adev); 1585 if (ret) 1586 return ret; 1587 1588 ret = smu_hw_init(adev); 1589 if (ret) 1590 return ret; 1591 1592 ret = smu_late_init(adev); 1593 if (ret) 1594 return ret; 1595 1596 return 0; 1597 } 1598 1599 static int smu_suspend(void *handle) 1600 { 1601 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1602 struct smu_context *smu = adev->powerplay.pp_handle; 1603 int ret; 1604 uint64_t count; 1605 1606 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1607 return 0; 1608 1609 if (!smu->pm_enabled) 1610 return 0; 1611 1612 adev->pm.dpm_enabled = false; 1613 1614 ret = smu_smc_hw_cleanup(smu); 1615 if (ret) 1616 return ret; 1617 1618 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1619 1620 smu_set_gfx_cgpg(smu, false); 1621 1622 /* 1623 * pwfw resets entrycount when device is suspended, so we save the 1624 * last value to be used when we resume to keep it consistent 1625 */ 1626 ret = smu_get_entrycount_gfxoff(smu, &count); 1627 if (!ret) 1628 adev->gfx.gfx_off_entrycount = count; 1629 1630 return 0; 1631 } 1632 1633 static int smu_resume(void *handle) 1634 { 1635 int ret; 1636 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1637 struct smu_context *smu = adev->powerplay.pp_handle; 1638 1639 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1640 return 0; 1641 1642 if (!smu->pm_enabled) 1643 return 0; 1644 1645 dev_info(adev->dev, "SMU is resuming...\n"); 1646 1647 ret = smu_start_smc_engine(smu); 1648 if (ret) { 1649 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1650 return ret; 1651 } 1652 1653 ret = smu_smc_hw_setup(smu); 1654 if (ret) { 1655 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1656 return ret; 1657 } 1658 1659 smu_set_gfx_cgpg(smu, true); 1660 1661 smu->disable_uclk_switch = 0; 1662 1663 adev->pm.dpm_enabled = true; 1664 1665 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1666 1667 return 0; 1668 } 1669 1670 static int smu_display_configuration_change(void *handle, 1671 const struct amd_pp_display_configuration *display_config) 1672 { 1673 struct smu_context *smu = handle; 1674 int index = 0; 1675 int num_of_active_display = 0; 1676 1677 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1678 return -EOPNOTSUPP; 1679 1680 if (!display_config) 1681 return -EINVAL; 1682 1683 smu_set_min_dcef_deep_sleep(smu, 1684 display_config->min_dcef_deep_sleep_set_clk / 100); 1685 1686 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1687 if (display_config->displays[index].controller_id != 0) 1688 num_of_active_display++; 1689 } 1690 1691 return 0; 1692 } 1693 1694 static int smu_set_clockgating_state(void *handle, 1695 enum amd_clockgating_state state) 1696 { 1697 return 0; 1698 } 1699 1700 static int smu_set_powergating_state(void *handle, 1701 enum amd_powergating_state state) 1702 { 1703 return 0; 1704 } 1705 1706 static int smu_enable_umd_pstate(void *handle, 1707 enum amd_dpm_forced_level *level) 1708 { 1709 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1710 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1711 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1712 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1713 1714 struct smu_context *smu = (struct smu_context*)(handle); 1715 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1716 1717 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1718 return -EINVAL; 1719 1720 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1721 /* enter umd pstate, save current level, disable gfx cg*/ 1722 if (*level & profile_mode_mask) { 1723 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1724 smu_gpo_control(smu, false); 1725 smu_gfx_ulv_control(smu, false); 1726 smu_deep_sleep_control(smu, false); 1727 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1728 } 1729 } else { 1730 /* exit umd pstate, restore level, enable gfx cg*/ 1731 if (!(*level & profile_mode_mask)) { 1732 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1733 *level = smu_dpm_ctx->saved_dpm_level; 1734 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1735 smu_deep_sleep_control(smu, true); 1736 smu_gfx_ulv_control(smu, true); 1737 smu_gpo_control(smu, true); 1738 } 1739 } 1740 1741 return 0; 1742 } 1743 1744 static int smu_bump_power_profile_mode(struct smu_context *smu, 1745 long *param, 1746 uint32_t param_size) 1747 { 1748 int ret = 0; 1749 1750 if (smu->ppt_funcs->set_power_profile_mode) 1751 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1752 1753 return ret; 1754 } 1755 1756 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1757 enum amd_dpm_forced_level level, 1758 bool skip_display_settings) 1759 { 1760 int ret = 0; 1761 int index = 0; 1762 long workload; 1763 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1764 1765 if (!skip_display_settings) { 1766 ret = smu_display_config_changed(smu); 1767 if (ret) { 1768 dev_err(smu->adev->dev, "Failed to change display config!"); 1769 return ret; 1770 } 1771 } 1772 1773 ret = smu_apply_clocks_adjust_rules(smu); 1774 if (ret) { 1775 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1776 return ret; 1777 } 1778 1779 if (!skip_display_settings) { 1780 ret = smu_notify_smc_display_config(smu); 1781 if (ret) { 1782 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1783 return ret; 1784 } 1785 } 1786 1787 if (smu_dpm_ctx->dpm_level != level) { 1788 ret = smu_asic_set_performance_level(smu, level); 1789 if (ret) { 1790 dev_err(smu->adev->dev, "Failed to set performance level!"); 1791 return ret; 1792 } 1793 1794 /* update the saved copy */ 1795 smu_dpm_ctx->dpm_level = level; 1796 } 1797 1798 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1799 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1800 index = fls(smu->workload_mask); 1801 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1802 workload = smu->workload_setting[index]; 1803 1804 if (smu->power_profile_mode != workload) 1805 smu_bump_power_profile_mode(smu, &workload, 0); 1806 } 1807 1808 return ret; 1809 } 1810 1811 static int smu_handle_task(struct smu_context *smu, 1812 enum amd_dpm_forced_level level, 1813 enum amd_pp_task task_id) 1814 { 1815 int ret = 0; 1816 1817 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1818 return -EOPNOTSUPP; 1819 1820 switch (task_id) { 1821 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1822 ret = smu_pre_display_config_changed(smu); 1823 if (ret) 1824 return ret; 1825 ret = smu_adjust_power_state_dynamic(smu, level, false); 1826 break; 1827 case AMD_PP_TASK_COMPLETE_INIT: 1828 case AMD_PP_TASK_READJUST_POWER_STATE: 1829 ret = smu_adjust_power_state_dynamic(smu, level, true); 1830 break; 1831 default: 1832 break; 1833 } 1834 1835 return ret; 1836 } 1837 1838 static int smu_handle_dpm_task(void *handle, 1839 enum amd_pp_task task_id, 1840 enum amd_pm_state_type *user_state) 1841 { 1842 struct smu_context *smu = handle; 1843 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1844 1845 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 1846 1847 } 1848 1849 static int smu_switch_power_profile(void *handle, 1850 enum PP_SMC_POWER_PROFILE type, 1851 bool en) 1852 { 1853 struct smu_context *smu = handle; 1854 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1855 long workload; 1856 uint32_t index; 1857 1858 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1859 return -EOPNOTSUPP; 1860 1861 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1862 return -EINVAL; 1863 1864 if (!en) { 1865 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1866 index = fls(smu->workload_mask); 1867 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1868 workload = smu->workload_setting[index]; 1869 } else { 1870 smu->workload_mask |= (1 << smu->workload_prority[type]); 1871 index = fls(smu->workload_mask); 1872 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1873 workload = smu->workload_setting[index]; 1874 } 1875 1876 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1877 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1878 smu_bump_power_profile_mode(smu, &workload, 0); 1879 1880 return 0; 1881 } 1882 1883 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 1884 { 1885 struct smu_context *smu = handle; 1886 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1887 1888 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1889 return -EOPNOTSUPP; 1890 1891 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1892 return -EINVAL; 1893 1894 return smu_dpm_ctx->dpm_level; 1895 } 1896 1897 static int smu_force_performance_level(void *handle, 1898 enum amd_dpm_forced_level level) 1899 { 1900 struct smu_context *smu = handle; 1901 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1902 int ret = 0; 1903 1904 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1905 return -EOPNOTSUPP; 1906 1907 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1908 return -EINVAL; 1909 1910 ret = smu_enable_umd_pstate(smu, &level); 1911 if (ret) 1912 return ret; 1913 1914 ret = smu_handle_task(smu, level, 1915 AMD_PP_TASK_READJUST_POWER_STATE); 1916 1917 /* reset user dpm clock state */ 1918 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1919 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 1920 smu->user_dpm_profile.clk_dependency = 0; 1921 } 1922 1923 return ret; 1924 } 1925 1926 static int smu_set_display_count(void *handle, uint32_t count) 1927 { 1928 struct smu_context *smu = handle; 1929 1930 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1931 return -EOPNOTSUPP; 1932 1933 return smu_init_display_count(smu, count); 1934 } 1935 1936 static int smu_force_smuclk_levels(struct smu_context *smu, 1937 enum smu_clk_type clk_type, 1938 uint32_t mask) 1939 { 1940 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1941 int ret = 0; 1942 1943 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1944 return -EOPNOTSUPP; 1945 1946 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1947 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1948 return -EINVAL; 1949 } 1950 1951 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 1952 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1953 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 1954 smu->user_dpm_profile.clk_mask[clk_type] = mask; 1955 smu_set_user_clk_dependencies(smu, clk_type); 1956 } 1957 } 1958 1959 return ret; 1960 } 1961 1962 static int smu_force_ppclk_levels(void *handle, 1963 enum pp_clock_type type, 1964 uint32_t mask) 1965 { 1966 struct smu_context *smu = handle; 1967 enum smu_clk_type clk_type; 1968 1969 switch (type) { 1970 case PP_SCLK: 1971 clk_type = SMU_SCLK; break; 1972 case PP_MCLK: 1973 clk_type = SMU_MCLK; break; 1974 case PP_PCIE: 1975 clk_type = SMU_PCIE; break; 1976 case PP_SOCCLK: 1977 clk_type = SMU_SOCCLK; break; 1978 case PP_FCLK: 1979 clk_type = SMU_FCLK; break; 1980 case PP_DCEFCLK: 1981 clk_type = SMU_DCEFCLK; break; 1982 case PP_VCLK: 1983 clk_type = SMU_VCLK; break; 1984 case PP_DCLK: 1985 clk_type = SMU_DCLK; break; 1986 case OD_SCLK: 1987 clk_type = SMU_OD_SCLK; break; 1988 case OD_MCLK: 1989 clk_type = SMU_OD_MCLK; break; 1990 case OD_VDDC_CURVE: 1991 clk_type = SMU_OD_VDDC_CURVE; break; 1992 case OD_RANGE: 1993 clk_type = SMU_OD_RANGE; break; 1994 default: 1995 return -EINVAL; 1996 } 1997 1998 return smu_force_smuclk_levels(smu, clk_type, mask); 1999 } 2000 2001 /* 2002 * On system suspending or resetting, the dpm_enabled 2003 * flag will be cleared. So that those SMU services which 2004 * are not supported will be gated. 2005 * However, the mp1 state setting should still be granted 2006 * even if the dpm_enabled cleared. 2007 */ 2008 static int smu_set_mp1_state(void *handle, 2009 enum pp_mp1_state mp1_state) 2010 { 2011 struct smu_context *smu = handle; 2012 int ret = 0; 2013 2014 if (!smu->pm_enabled) 2015 return -EOPNOTSUPP; 2016 2017 if (smu->ppt_funcs && 2018 smu->ppt_funcs->set_mp1_state) 2019 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2020 2021 return ret; 2022 } 2023 2024 static int smu_set_df_cstate(void *handle, 2025 enum pp_df_cstate state) 2026 { 2027 struct smu_context *smu = handle; 2028 int ret = 0; 2029 2030 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2031 return -EOPNOTSUPP; 2032 2033 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2034 return 0; 2035 2036 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2037 if (ret) 2038 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2039 2040 return ret; 2041 } 2042 2043 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 2044 { 2045 int ret = 0; 2046 2047 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2048 return -EOPNOTSUPP; 2049 2050 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 2051 return 0; 2052 2053 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 2054 if (ret) 2055 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 2056 2057 return ret; 2058 } 2059 2060 int smu_write_watermarks_table(struct smu_context *smu) 2061 { 2062 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2063 return -EOPNOTSUPP; 2064 2065 return smu_set_watermarks_table(smu, NULL); 2066 } 2067 2068 static int smu_set_watermarks_for_clock_ranges(void *handle, 2069 struct pp_smu_wm_range_sets *clock_ranges) 2070 { 2071 struct smu_context *smu = handle; 2072 2073 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2074 return -EOPNOTSUPP; 2075 2076 if (smu->disable_watermark) 2077 return 0; 2078 2079 return smu_set_watermarks_table(smu, clock_ranges); 2080 } 2081 2082 int smu_set_ac_dc(struct smu_context *smu) 2083 { 2084 int ret = 0; 2085 2086 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2087 return -EOPNOTSUPP; 2088 2089 /* controlled by firmware */ 2090 if (smu->dc_controlled_by_gpio) 2091 return 0; 2092 2093 ret = smu_set_power_source(smu, 2094 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2095 SMU_POWER_SOURCE_DC); 2096 if (ret) 2097 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2098 smu->adev->pm.ac_power ? "AC" : "DC"); 2099 2100 return ret; 2101 } 2102 2103 const struct amd_ip_funcs smu_ip_funcs = { 2104 .name = "smu", 2105 .early_init = smu_early_init, 2106 .late_init = smu_late_init, 2107 .sw_init = smu_sw_init, 2108 .sw_fini = smu_sw_fini, 2109 .hw_init = smu_hw_init, 2110 .hw_fini = smu_hw_fini, 2111 .late_fini = smu_late_fini, 2112 .suspend = smu_suspend, 2113 .resume = smu_resume, 2114 .is_idle = NULL, 2115 .check_soft_reset = NULL, 2116 .wait_for_idle = NULL, 2117 .soft_reset = NULL, 2118 .set_clockgating_state = smu_set_clockgating_state, 2119 .set_powergating_state = smu_set_powergating_state, 2120 }; 2121 2122 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 2123 { 2124 .type = AMD_IP_BLOCK_TYPE_SMC, 2125 .major = 11, 2126 .minor = 0, 2127 .rev = 0, 2128 .funcs = &smu_ip_funcs, 2129 }; 2130 2131 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 2132 { 2133 .type = AMD_IP_BLOCK_TYPE_SMC, 2134 .major = 12, 2135 .minor = 0, 2136 .rev = 0, 2137 .funcs = &smu_ip_funcs, 2138 }; 2139 2140 const struct amdgpu_ip_block_version smu_v13_0_ip_block = 2141 { 2142 .type = AMD_IP_BLOCK_TYPE_SMC, 2143 .major = 13, 2144 .minor = 0, 2145 .rev = 0, 2146 .funcs = &smu_ip_funcs, 2147 }; 2148 2149 static int smu_load_microcode(void *handle) 2150 { 2151 struct smu_context *smu = handle; 2152 struct amdgpu_device *adev = smu->adev; 2153 int ret = 0; 2154 2155 if (!smu->pm_enabled) 2156 return -EOPNOTSUPP; 2157 2158 /* This should be used for non PSP loading */ 2159 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2160 return 0; 2161 2162 if (smu->ppt_funcs->load_microcode) { 2163 ret = smu->ppt_funcs->load_microcode(smu); 2164 if (ret) { 2165 dev_err(adev->dev, "Load microcode failed\n"); 2166 return ret; 2167 } 2168 } 2169 2170 if (smu->ppt_funcs->check_fw_status) { 2171 ret = smu->ppt_funcs->check_fw_status(smu); 2172 if (ret) { 2173 dev_err(adev->dev, "SMC is not ready\n"); 2174 return ret; 2175 } 2176 } 2177 2178 return ret; 2179 } 2180 2181 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2182 { 2183 int ret = 0; 2184 2185 if (smu->ppt_funcs->set_gfx_cgpg) 2186 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2187 2188 return ret; 2189 } 2190 2191 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2192 { 2193 struct smu_context *smu = handle; 2194 int ret = 0; 2195 2196 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2197 return -EOPNOTSUPP; 2198 2199 if (!smu->ppt_funcs->set_fan_speed_rpm) 2200 return -EOPNOTSUPP; 2201 2202 if (speed == U32_MAX) 2203 return -EINVAL; 2204 2205 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2206 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2207 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2208 smu->user_dpm_profile.fan_speed_rpm = speed; 2209 2210 /* Override custom PWM setting as they cannot co-exist */ 2211 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2212 smu->user_dpm_profile.fan_speed_pwm = 0; 2213 } 2214 2215 return ret; 2216 } 2217 2218 /** 2219 * smu_get_power_limit - Request one of the SMU Power Limits 2220 * 2221 * @handle: pointer to smu context 2222 * @limit: requested limit is written back to this variable 2223 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2224 * @pp_power_type: &pp_power_type type of power 2225 * Return: 0 on success, <0 on error 2226 * 2227 */ 2228 int smu_get_power_limit(void *handle, 2229 uint32_t *limit, 2230 enum pp_power_limit_level pp_limit_level, 2231 enum pp_power_type pp_power_type) 2232 { 2233 struct smu_context *smu = handle; 2234 struct amdgpu_device *adev = smu->adev; 2235 enum smu_ppt_limit_level limit_level; 2236 uint32_t limit_type; 2237 int ret = 0; 2238 2239 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2240 return -EOPNOTSUPP; 2241 2242 switch(pp_power_type) { 2243 case PP_PWR_TYPE_SUSTAINED: 2244 limit_type = SMU_DEFAULT_PPT_LIMIT; 2245 break; 2246 case PP_PWR_TYPE_FAST: 2247 limit_type = SMU_FAST_PPT_LIMIT; 2248 break; 2249 default: 2250 return -EOPNOTSUPP; 2251 break; 2252 } 2253 2254 switch(pp_limit_level){ 2255 case PP_PWR_LIMIT_CURRENT: 2256 limit_level = SMU_PPT_LIMIT_CURRENT; 2257 break; 2258 case PP_PWR_LIMIT_DEFAULT: 2259 limit_level = SMU_PPT_LIMIT_DEFAULT; 2260 break; 2261 case PP_PWR_LIMIT_MAX: 2262 limit_level = SMU_PPT_LIMIT_MAX; 2263 break; 2264 case PP_PWR_LIMIT_MIN: 2265 default: 2266 return -EOPNOTSUPP; 2267 break; 2268 } 2269 2270 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2271 if (smu->ppt_funcs->get_ppt_limit) 2272 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2273 } else { 2274 switch (limit_level) { 2275 case SMU_PPT_LIMIT_CURRENT: 2276 switch (adev->ip_versions[MP1_HWIP][0]) { 2277 case IP_VERSION(13, 0, 2): 2278 case IP_VERSION(11, 0, 7): 2279 case IP_VERSION(11, 0, 11): 2280 case IP_VERSION(11, 0, 12): 2281 case IP_VERSION(11, 0, 13): 2282 ret = smu_get_asic_power_limits(smu, 2283 &smu->current_power_limit, 2284 NULL, 2285 NULL); 2286 break; 2287 default: 2288 break; 2289 } 2290 *limit = smu->current_power_limit; 2291 break; 2292 case SMU_PPT_LIMIT_DEFAULT: 2293 *limit = smu->default_power_limit; 2294 break; 2295 case SMU_PPT_LIMIT_MAX: 2296 *limit = smu->max_power_limit; 2297 break; 2298 default: 2299 break; 2300 } 2301 } 2302 2303 return ret; 2304 } 2305 2306 static int smu_set_power_limit(void *handle, uint32_t limit) 2307 { 2308 struct smu_context *smu = handle; 2309 uint32_t limit_type = limit >> 24; 2310 int ret = 0; 2311 2312 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2313 return -EOPNOTSUPP; 2314 2315 limit &= (1<<24)-1; 2316 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2317 if (smu->ppt_funcs->set_power_limit) 2318 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2319 2320 if (limit > smu->max_power_limit) { 2321 dev_err(smu->adev->dev, 2322 "New power limit (%d) is over the max allowed %d\n", 2323 limit, smu->max_power_limit); 2324 return -EINVAL; 2325 } 2326 2327 if (!limit) 2328 limit = smu->current_power_limit; 2329 2330 if (smu->ppt_funcs->set_power_limit) { 2331 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2332 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2333 smu->user_dpm_profile.power_limit = limit; 2334 } 2335 2336 return ret; 2337 } 2338 2339 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2340 { 2341 int ret = 0; 2342 2343 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2344 return -EOPNOTSUPP; 2345 2346 if (smu->ppt_funcs->print_clk_levels) 2347 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2348 2349 return ret; 2350 } 2351 2352 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2353 { 2354 enum smu_clk_type clk_type; 2355 2356 switch (type) { 2357 case PP_SCLK: 2358 clk_type = SMU_SCLK; break; 2359 case PP_MCLK: 2360 clk_type = SMU_MCLK; break; 2361 case PP_PCIE: 2362 clk_type = SMU_PCIE; break; 2363 case PP_SOCCLK: 2364 clk_type = SMU_SOCCLK; break; 2365 case PP_FCLK: 2366 clk_type = SMU_FCLK; break; 2367 case PP_DCEFCLK: 2368 clk_type = SMU_DCEFCLK; break; 2369 case PP_VCLK: 2370 clk_type = SMU_VCLK; break; 2371 case PP_DCLK: 2372 clk_type = SMU_DCLK; break; 2373 case OD_SCLK: 2374 clk_type = SMU_OD_SCLK; break; 2375 case OD_MCLK: 2376 clk_type = SMU_OD_MCLK; break; 2377 case OD_VDDC_CURVE: 2378 clk_type = SMU_OD_VDDC_CURVE; break; 2379 case OD_RANGE: 2380 clk_type = SMU_OD_RANGE; break; 2381 case OD_VDDGFX_OFFSET: 2382 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2383 case OD_CCLK: 2384 clk_type = SMU_OD_CCLK; break; 2385 default: 2386 clk_type = SMU_CLK_COUNT; break; 2387 } 2388 2389 return clk_type; 2390 } 2391 2392 static int smu_print_ppclk_levels(void *handle, 2393 enum pp_clock_type type, 2394 char *buf) 2395 { 2396 struct smu_context *smu = handle; 2397 enum smu_clk_type clk_type; 2398 2399 clk_type = smu_convert_to_smuclk(type); 2400 if (clk_type == SMU_CLK_COUNT) 2401 return -EINVAL; 2402 2403 return smu_print_smuclk_levels(smu, clk_type, buf); 2404 } 2405 2406 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2407 { 2408 struct smu_context *smu = handle; 2409 enum smu_clk_type clk_type; 2410 2411 clk_type = smu_convert_to_smuclk(type); 2412 if (clk_type == SMU_CLK_COUNT) 2413 return -EINVAL; 2414 2415 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2416 return -EOPNOTSUPP; 2417 2418 if (!smu->ppt_funcs->emit_clk_levels) 2419 return -ENOENT; 2420 2421 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2422 2423 } 2424 2425 static int smu_od_edit_dpm_table(void *handle, 2426 enum PP_OD_DPM_TABLE_COMMAND type, 2427 long *input, uint32_t size) 2428 { 2429 struct smu_context *smu = handle; 2430 int ret = 0; 2431 2432 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2433 return -EOPNOTSUPP; 2434 2435 if (smu->ppt_funcs->od_edit_dpm_table) { 2436 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2437 } 2438 2439 return ret; 2440 } 2441 2442 static int smu_read_sensor(void *handle, 2443 int sensor, 2444 void *data, 2445 int *size_arg) 2446 { 2447 struct smu_context *smu = handle; 2448 struct smu_umd_pstate_table *pstate_table = 2449 &smu->pstate_table; 2450 int ret = 0; 2451 uint32_t *size, size_val; 2452 2453 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2454 return -EOPNOTSUPP; 2455 2456 if (!data || !size_arg) 2457 return -EINVAL; 2458 2459 size_val = *size_arg; 2460 size = &size_val; 2461 2462 if (smu->ppt_funcs->read_sensor) 2463 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2464 goto unlock; 2465 2466 switch (sensor) { 2467 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2468 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2469 *size = 4; 2470 break; 2471 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2472 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2473 *size = 4; 2474 break; 2475 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2476 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2477 *size = 8; 2478 break; 2479 case AMDGPU_PP_SENSOR_UVD_POWER: 2480 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2481 *size = 4; 2482 break; 2483 case AMDGPU_PP_SENSOR_VCE_POWER: 2484 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2485 *size = 4; 2486 break; 2487 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2488 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2489 *size = 4; 2490 break; 2491 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2492 *(uint32_t *)data = 0; 2493 *size = 4; 2494 break; 2495 default: 2496 *size = 0; 2497 ret = -EOPNOTSUPP; 2498 break; 2499 } 2500 2501 unlock: 2502 // assign uint32_t to int 2503 *size_arg = size_val; 2504 2505 return ret; 2506 } 2507 2508 static int smu_get_power_profile_mode(void *handle, char *buf) 2509 { 2510 struct smu_context *smu = handle; 2511 2512 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2513 !smu->ppt_funcs->get_power_profile_mode) 2514 return -EOPNOTSUPP; 2515 if (!buf) 2516 return -EINVAL; 2517 2518 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 2519 } 2520 2521 static int smu_set_power_profile_mode(void *handle, 2522 long *param, 2523 uint32_t param_size) 2524 { 2525 struct smu_context *smu = handle; 2526 2527 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2528 !smu->ppt_funcs->set_power_profile_mode) 2529 return -EOPNOTSUPP; 2530 2531 return smu_bump_power_profile_mode(smu, param, param_size); 2532 } 2533 2534 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 2535 { 2536 struct smu_context *smu = handle; 2537 2538 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2539 return -EOPNOTSUPP; 2540 2541 if (!smu->ppt_funcs->get_fan_control_mode) 2542 return -EOPNOTSUPP; 2543 2544 if (!fan_mode) 2545 return -EINVAL; 2546 2547 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 2548 2549 return 0; 2550 } 2551 2552 static int smu_set_fan_control_mode(void *handle, u32 value) 2553 { 2554 struct smu_context *smu = handle; 2555 int ret = 0; 2556 2557 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2558 return -EOPNOTSUPP; 2559 2560 if (!smu->ppt_funcs->set_fan_control_mode) 2561 return -EOPNOTSUPP; 2562 2563 if (value == U32_MAX) 2564 return -EINVAL; 2565 2566 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2567 if (ret) 2568 goto out; 2569 2570 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2571 smu->user_dpm_profile.fan_mode = value; 2572 2573 /* reset user dpm fan speed */ 2574 if (value != AMD_FAN_CTRL_MANUAL) { 2575 smu->user_dpm_profile.fan_speed_pwm = 0; 2576 smu->user_dpm_profile.fan_speed_rpm = 0; 2577 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 2578 } 2579 } 2580 2581 out: 2582 return ret; 2583 } 2584 2585 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 2586 { 2587 struct smu_context *smu = handle; 2588 int ret = 0; 2589 2590 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2591 return -EOPNOTSUPP; 2592 2593 if (!smu->ppt_funcs->get_fan_speed_pwm) 2594 return -EOPNOTSUPP; 2595 2596 if (!speed) 2597 return -EINVAL; 2598 2599 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 2600 2601 return ret; 2602 } 2603 2604 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 2605 { 2606 struct smu_context *smu = handle; 2607 int ret = 0; 2608 2609 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2610 return -EOPNOTSUPP; 2611 2612 if (!smu->ppt_funcs->set_fan_speed_pwm) 2613 return -EOPNOTSUPP; 2614 2615 if (speed == U32_MAX) 2616 return -EINVAL; 2617 2618 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 2619 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2620 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 2621 smu->user_dpm_profile.fan_speed_pwm = speed; 2622 2623 /* Override custom RPM setting as they cannot co-exist */ 2624 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 2625 smu->user_dpm_profile.fan_speed_rpm = 0; 2626 } 2627 2628 return ret; 2629 } 2630 2631 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2632 { 2633 struct smu_context *smu = handle; 2634 int ret = 0; 2635 2636 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2637 return -EOPNOTSUPP; 2638 2639 if (!smu->ppt_funcs->get_fan_speed_rpm) 2640 return -EOPNOTSUPP; 2641 2642 if (!speed) 2643 return -EINVAL; 2644 2645 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 2646 2647 return ret; 2648 } 2649 2650 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 2651 { 2652 struct smu_context *smu = handle; 2653 2654 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2655 return -EOPNOTSUPP; 2656 2657 return smu_set_min_dcef_deep_sleep(smu, clk); 2658 } 2659 2660 static int smu_get_clock_by_type_with_latency(void *handle, 2661 enum amd_pp_clock_type type, 2662 struct pp_clock_levels_with_latency *clocks) 2663 { 2664 struct smu_context *smu = handle; 2665 enum smu_clk_type clk_type; 2666 int ret = 0; 2667 2668 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2669 return -EOPNOTSUPP; 2670 2671 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 2672 switch (type) { 2673 case amd_pp_sys_clock: 2674 clk_type = SMU_GFXCLK; 2675 break; 2676 case amd_pp_mem_clock: 2677 clk_type = SMU_MCLK; 2678 break; 2679 case amd_pp_dcef_clock: 2680 clk_type = SMU_DCEFCLK; 2681 break; 2682 case amd_pp_disp_clock: 2683 clk_type = SMU_DISPCLK; 2684 break; 2685 default: 2686 dev_err(smu->adev->dev, "Invalid clock type!\n"); 2687 return -EINVAL; 2688 } 2689 2690 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2691 } 2692 2693 return ret; 2694 } 2695 2696 static int smu_display_clock_voltage_request(void *handle, 2697 struct pp_display_clock_request *clock_req) 2698 { 2699 struct smu_context *smu = handle; 2700 int ret = 0; 2701 2702 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2703 return -EOPNOTSUPP; 2704 2705 if (smu->ppt_funcs->display_clock_voltage_request) 2706 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2707 2708 return ret; 2709 } 2710 2711 2712 static int smu_display_disable_memory_clock_switch(void *handle, 2713 bool disable_memory_clock_switch) 2714 { 2715 struct smu_context *smu = handle; 2716 int ret = -EINVAL; 2717 2718 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2719 return -EOPNOTSUPP; 2720 2721 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2722 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2723 2724 return ret; 2725 } 2726 2727 static int smu_set_xgmi_pstate(void *handle, 2728 uint32_t pstate) 2729 { 2730 struct smu_context *smu = handle; 2731 int ret = 0; 2732 2733 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2734 return -EOPNOTSUPP; 2735 2736 if (smu->ppt_funcs->set_xgmi_pstate) 2737 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2738 2739 if(ret) 2740 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2741 2742 return ret; 2743 } 2744 2745 static int smu_get_baco_capability(void *handle, bool *cap) 2746 { 2747 struct smu_context *smu = handle; 2748 2749 *cap = false; 2750 2751 if (!smu->pm_enabled) 2752 return 0; 2753 2754 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2755 *cap = smu->ppt_funcs->baco_is_support(smu); 2756 2757 return 0; 2758 } 2759 2760 static int smu_baco_set_state(void *handle, int state) 2761 { 2762 struct smu_context *smu = handle; 2763 int ret = 0; 2764 2765 if (!smu->pm_enabled) 2766 return -EOPNOTSUPP; 2767 2768 if (state == 0) { 2769 if (smu->ppt_funcs->baco_exit) 2770 ret = smu->ppt_funcs->baco_exit(smu); 2771 } else if (state == 1) { 2772 if (smu->ppt_funcs->baco_enter) 2773 ret = smu->ppt_funcs->baco_enter(smu); 2774 } else { 2775 return -EINVAL; 2776 } 2777 2778 if (ret) 2779 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 2780 (state)?"enter":"exit"); 2781 2782 return ret; 2783 } 2784 2785 bool smu_mode1_reset_is_support(struct smu_context *smu) 2786 { 2787 bool ret = false; 2788 2789 if (!smu->pm_enabled) 2790 return false; 2791 2792 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2793 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2794 2795 return ret; 2796 } 2797 2798 bool smu_mode2_reset_is_support(struct smu_context *smu) 2799 { 2800 bool ret = false; 2801 2802 if (!smu->pm_enabled) 2803 return false; 2804 2805 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 2806 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 2807 2808 return ret; 2809 } 2810 2811 int smu_mode1_reset(struct smu_context *smu) 2812 { 2813 int ret = 0; 2814 2815 if (!smu->pm_enabled) 2816 return -EOPNOTSUPP; 2817 2818 if (smu->ppt_funcs->mode1_reset) 2819 ret = smu->ppt_funcs->mode1_reset(smu); 2820 2821 return ret; 2822 } 2823 2824 static int smu_mode2_reset(void *handle) 2825 { 2826 struct smu_context *smu = handle; 2827 int ret = 0; 2828 2829 if (!smu->pm_enabled) 2830 return -EOPNOTSUPP; 2831 2832 if (smu->ppt_funcs->mode2_reset) 2833 ret = smu->ppt_funcs->mode2_reset(smu); 2834 2835 if (ret) 2836 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2837 2838 return ret; 2839 } 2840 2841 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 2842 struct pp_smu_nv_clock_table *max_clocks) 2843 { 2844 struct smu_context *smu = handle; 2845 int ret = 0; 2846 2847 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2848 return -EOPNOTSUPP; 2849 2850 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2851 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2852 2853 return ret; 2854 } 2855 2856 static int smu_get_uclk_dpm_states(void *handle, 2857 unsigned int *clock_values_in_khz, 2858 unsigned int *num_states) 2859 { 2860 struct smu_context *smu = handle; 2861 int ret = 0; 2862 2863 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2864 return -EOPNOTSUPP; 2865 2866 if (smu->ppt_funcs->get_uclk_dpm_states) 2867 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2868 2869 return ret; 2870 } 2871 2872 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 2873 { 2874 struct smu_context *smu = handle; 2875 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2876 2877 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2878 return -EOPNOTSUPP; 2879 2880 if (smu->ppt_funcs->get_current_power_state) 2881 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2882 2883 return pm_state; 2884 } 2885 2886 static int smu_get_dpm_clock_table(void *handle, 2887 struct dpm_clocks *clock_table) 2888 { 2889 struct smu_context *smu = handle; 2890 int ret = 0; 2891 2892 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2893 return -EOPNOTSUPP; 2894 2895 if (smu->ppt_funcs->get_dpm_clock_table) 2896 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 2897 2898 return ret; 2899 } 2900 2901 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 2902 { 2903 struct smu_context *smu = handle; 2904 2905 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2906 return -EOPNOTSUPP; 2907 2908 if (!smu->ppt_funcs->get_gpu_metrics) 2909 return -EOPNOTSUPP; 2910 2911 return smu->ppt_funcs->get_gpu_metrics(smu, table); 2912 } 2913 2914 static int smu_enable_mgpu_fan_boost(void *handle) 2915 { 2916 struct smu_context *smu = handle; 2917 int ret = 0; 2918 2919 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2920 return -EOPNOTSUPP; 2921 2922 if (smu->ppt_funcs->enable_mgpu_fan_boost) 2923 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 2924 2925 return ret; 2926 } 2927 2928 static int smu_gfx_state_change_set(void *handle, 2929 uint32_t state) 2930 { 2931 struct smu_context *smu = handle; 2932 int ret = 0; 2933 2934 if (smu->ppt_funcs->gfx_state_change_set) 2935 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 2936 2937 return ret; 2938 } 2939 2940 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 2941 { 2942 int ret = 0; 2943 2944 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 2945 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 2946 2947 return ret; 2948 } 2949 2950 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 2951 { 2952 int ret = -EOPNOTSUPP; 2953 2954 if (smu->ppt_funcs && 2955 smu->ppt_funcs->get_ecc_info) 2956 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 2957 2958 return ret; 2959 2960 } 2961 2962 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 2963 { 2964 struct smu_context *smu = handle; 2965 struct smu_table_context *smu_table = &smu->smu_table; 2966 struct smu_table *memory_pool = &smu_table->memory_pool; 2967 2968 if (!addr || !size) 2969 return -EINVAL; 2970 2971 *addr = NULL; 2972 *size = 0; 2973 if (memory_pool->bo) { 2974 *addr = memory_pool->cpu_addr; 2975 *size = memory_pool->size; 2976 } 2977 2978 return 0; 2979 } 2980 2981 static const struct amd_pm_funcs swsmu_pm_funcs = { 2982 /* export for sysfs */ 2983 .set_fan_control_mode = smu_set_fan_control_mode, 2984 .get_fan_control_mode = smu_get_fan_control_mode, 2985 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 2986 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 2987 .force_clock_level = smu_force_ppclk_levels, 2988 .print_clock_levels = smu_print_ppclk_levels, 2989 .emit_clock_levels = smu_emit_ppclk_levels, 2990 .force_performance_level = smu_force_performance_level, 2991 .read_sensor = smu_read_sensor, 2992 .get_performance_level = smu_get_performance_level, 2993 .get_current_power_state = smu_get_current_power_state, 2994 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 2995 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 2996 .get_pp_num_states = smu_get_power_num_states, 2997 .get_pp_table = smu_sys_get_pp_table, 2998 .set_pp_table = smu_sys_set_pp_table, 2999 .switch_power_profile = smu_switch_power_profile, 3000 /* export to amdgpu */ 3001 .dispatch_tasks = smu_handle_dpm_task, 3002 .load_firmware = smu_load_microcode, 3003 .set_powergating_by_smu = smu_dpm_set_power_gate, 3004 .set_power_limit = smu_set_power_limit, 3005 .get_power_limit = smu_get_power_limit, 3006 .get_power_profile_mode = smu_get_power_profile_mode, 3007 .set_power_profile_mode = smu_set_power_profile_mode, 3008 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3009 .set_mp1_state = smu_set_mp1_state, 3010 .gfx_state_change_set = smu_gfx_state_change_set, 3011 /* export to DC */ 3012 .get_sclk = smu_get_sclk, 3013 .get_mclk = smu_get_mclk, 3014 .display_configuration_change = smu_display_configuration_change, 3015 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3016 .display_clock_voltage_request = smu_display_clock_voltage_request, 3017 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3018 .set_active_display_count = smu_set_display_count, 3019 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3020 .get_asic_baco_capability = smu_get_baco_capability, 3021 .set_asic_baco_state = smu_baco_set_state, 3022 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3023 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3024 .asic_reset_mode_2 = smu_mode2_reset, 3025 .set_df_cstate = smu_set_df_cstate, 3026 .set_xgmi_pstate = smu_set_xgmi_pstate, 3027 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3028 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3029 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3030 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3031 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3032 .get_dpm_clock_table = smu_get_dpm_clock_table, 3033 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3034 }; 3035 3036 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3037 uint64_t event_arg) 3038 { 3039 int ret = -EINVAL; 3040 3041 if (smu->ppt_funcs->wait_for_event) 3042 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3043 3044 return ret; 3045 } 3046 3047 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3048 { 3049 3050 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3051 return -EOPNOTSUPP; 3052 3053 /* Confirm the buffer allocated is of correct size */ 3054 if (size != smu->stb_context.stb_buf_size) 3055 return -EINVAL; 3056 3057 /* 3058 * No need to lock smu mutex as we access STB directly through MMIO 3059 * and not going through SMU messaging route (for now at least). 3060 * For registers access rely on implementation internal locking. 3061 */ 3062 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3063 } 3064 3065 #if defined(CONFIG_DEBUG_FS) 3066 3067 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3068 { 3069 struct amdgpu_device *adev = filp->f_inode->i_private; 3070 struct smu_context *smu = adev->powerplay.pp_handle; 3071 unsigned char *buf; 3072 int r; 3073 3074 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3075 if (!buf) 3076 return -ENOMEM; 3077 3078 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3079 if (r) 3080 goto out; 3081 3082 filp->private_data = buf; 3083 3084 return 0; 3085 3086 out: 3087 kvfree(buf); 3088 return r; 3089 } 3090 3091 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3092 loff_t *pos) 3093 { 3094 struct amdgpu_device *adev = filp->f_inode->i_private; 3095 struct smu_context *smu = adev->powerplay.pp_handle; 3096 3097 3098 if (!filp->private_data) 3099 return -EINVAL; 3100 3101 return simple_read_from_buffer(buf, 3102 size, 3103 pos, filp->private_data, 3104 smu->stb_context.stb_buf_size); 3105 } 3106 3107 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3108 { 3109 kvfree(filp->private_data); 3110 filp->private_data = NULL; 3111 3112 return 0; 3113 } 3114 3115 /* 3116 * We have to define not only read method but also 3117 * open and release because .read takes up to PAGE_SIZE 3118 * data each time so and so is invoked multiple times. 3119 * We allocate the STB buffer in .open and release it 3120 * in .release 3121 */ 3122 static const struct file_operations smu_stb_debugfs_fops = { 3123 .owner = THIS_MODULE, 3124 .open = smu_stb_debugfs_open, 3125 .read = smu_stb_debugfs_read, 3126 .release = smu_stb_debugfs_release, 3127 .llseek = default_llseek, 3128 }; 3129 3130 #endif 3131 3132 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3133 { 3134 #if defined(CONFIG_DEBUG_FS) 3135 3136 struct smu_context *smu = adev->powerplay.pp_handle; 3137 3138 if (!smu || (!smu->stb_context.stb_buf_size)) 3139 return; 3140 3141 debugfs_create_file_size("amdgpu_smu_stb_dump", 3142 S_IRUSR, 3143 adev_to_drm(adev)->primary->debugfs_root, 3144 adev, 3145 &smu_stb_debugfs_fops, 3146 smu->stb_context.stb_buf_size); 3147 #endif 3148 } 3149 3150 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3151 { 3152 int ret = 0; 3153 3154 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3155 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3156 3157 return ret; 3158 } 3159 3160 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3161 { 3162 int ret = 0; 3163 3164 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3165 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3166 3167 return ret; 3168 } 3169