1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "aldebaran_ppt.h" 38 #include "yellow_carp_ppt.h" 39 #include "cyan_skillfish_ppt.h" 40 #include "smu_v13_0_0_ppt.h" 41 #include "smu_v13_0_5_ppt.h" 42 #include "smu_v13_0_7_ppt.h" 43 #include "amd_pcie.h" 44 45 /* 46 * DO NOT use these for err/warn/info/debug messages. 47 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 48 * They are more MGPU friendly. 49 */ 50 #undef pr_err 51 #undef pr_warn 52 #undef pr_info 53 #undef pr_debug 54 55 static const struct amd_pm_funcs swsmu_pm_funcs; 56 static int smu_force_smuclk_levels(struct smu_context *smu, 57 enum smu_clk_type clk_type, 58 uint32_t mask); 59 static int smu_handle_task(struct smu_context *smu, 60 enum amd_dpm_forced_level level, 61 enum amd_pp_task task_id); 62 static int smu_reset(struct smu_context *smu); 63 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 64 static int smu_set_fan_control_mode(void *handle, u32 value); 65 static int smu_set_power_limit(void *handle, uint32_t limit); 66 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 67 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 68 69 static int smu_sys_get_pp_feature_mask(void *handle, 70 char *buf) 71 { 72 struct smu_context *smu = handle; 73 74 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 75 return -EOPNOTSUPP; 76 77 return smu_get_pp_feature_mask(smu, buf); 78 } 79 80 static int smu_sys_set_pp_feature_mask(void *handle, 81 uint64_t new_mask) 82 { 83 struct smu_context *smu = handle; 84 85 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 86 return -EOPNOTSUPP; 87 88 return smu_set_pp_feature_mask(smu, new_mask); 89 } 90 91 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 92 { 93 if (!smu->ppt_funcs->get_gfx_off_status) 94 return -EINVAL; 95 96 *value = smu_get_gfx_off_status(smu); 97 98 return 0; 99 } 100 101 int smu_set_soft_freq_range(struct smu_context *smu, 102 enum smu_clk_type clk_type, 103 uint32_t min, 104 uint32_t max) 105 { 106 int ret = 0; 107 108 if (smu->ppt_funcs->set_soft_freq_limited_range) 109 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 110 clk_type, 111 min, 112 max); 113 114 return ret; 115 } 116 117 int smu_get_dpm_freq_range(struct smu_context *smu, 118 enum smu_clk_type clk_type, 119 uint32_t *min, 120 uint32_t *max) 121 { 122 int ret = -ENOTSUPP; 123 124 if (!min && !max) 125 return -EINVAL; 126 127 if (smu->ppt_funcs->get_dpm_ultimate_freq) 128 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 129 clk_type, 130 min, 131 max); 132 133 return ret; 134 } 135 136 static u32 smu_get_mclk(void *handle, bool low) 137 { 138 struct smu_context *smu = handle; 139 uint32_t clk_freq; 140 int ret = 0; 141 142 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 143 low ? &clk_freq : NULL, 144 !low ? &clk_freq : NULL); 145 if (ret) 146 return 0; 147 return clk_freq * 100; 148 } 149 150 static u32 smu_get_sclk(void *handle, bool low) 151 { 152 struct smu_context *smu = handle; 153 uint32_t clk_freq; 154 int ret = 0; 155 156 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 157 low ? &clk_freq : NULL, 158 !low ? &clk_freq : NULL); 159 if (ret) 160 return 0; 161 return clk_freq * 100; 162 } 163 164 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 165 bool enable) 166 { 167 struct smu_power_context *smu_power = &smu->smu_power; 168 struct smu_power_gate *power_gate = &smu_power->power_gate; 169 int ret = 0; 170 171 if (!smu->ppt_funcs->dpm_set_vcn_enable) 172 return 0; 173 174 if (atomic_read(&power_gate->vcn_gated) ^ enable) 175 return 0; 176 177 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 178 if (!ret) 179 atomic_set(&power_gate->vcn_gated, !enable); 180 181 return ret; 182 } 183 184 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 185 bool enable) 186 { 187 struct smu_power_context *smu_power = &smu->smu_power; 188 struct smu_power_gate *power_gate = &smu_power->power_gate; 189 int ret = 0; 190 191 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 192 return 0; 193 194 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 195 return 0; 196 197 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 198 if (!ret) 199 atomic_set(&power_gate->jpeg_gated, !enable); 200 201 return ret; 202 } 203 204 /** 205 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 206 * 207 * @handle: smu_context pointer 208 * @block_type: the IP block to power gate/ungate 209 * @gate: to power gate if true, ungate otherwise 210 * 211 * This API uses no smu->mutex lock protection due to: 212 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 213 * This is guarded to be race condition free by the caller. 214 * 2. Or get called on user setting request of power_dpm_force_performance_level. 215 * Under this case, the smu->mutex lock protection is already enforced on 216 * the parent API smu_force_performance_level of the call path. 217 */ 218 static int smu_dpm_set_power_gate(void *handle, 219 uint32_t block_type, 220 bool gate) 221 { 222 struct smu_context *smu = handle; 223 int ret = 0; 224 225 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 226 dev_WARN(smu->adev->dev, 227 "SMU uninitialized but power %s requested for %u!\n", 228 gate ? "gate" : "ungate", block_type); 229 return -EOPNOTSUPP; 230 } 231 232 switch (block_type) { 233 /* 234 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 235 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 236 */ 237 case AMD_IP_BLOCK_TYPE_UVD: 238 case AMD_IP_BLOCK_TYPE_VCN: 239 ret = smu_dpm_set_vcn_enable(smu, !gate); 240 if (ret) 241 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 242 gate ? "gate" : "ungate"); 243 break; 244 case AMD_IP_BLOCK_TYPE_GFX: 245 ret = smu_gfx_off_control(smu, gate); 246 if (ret) 247 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 248 gate ? "enable" : "disable"); 249 break; 250 case AMD_IP_BLOCK_TYPE_SDMA: 251 ret = smu_powergate_sdma(smu, gate); 252 if (ret) 253 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 254 gate ? "gate" : "ungate"); 255 break; 256 case AMD_IP_BLOCK_TYPE_JPEG: 257 ret = smu_dpm_set_jpeg_enable(smu, !gate); 258 if (ret) 259 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 260 gate ? "gate" : "ungate"); 261 break; 262 default: 263 dev_err(smu->adev->dev, "Unsupported block type!\n"); 264 return -EINVAL; 265 } 266 267 return ret; 268 } 269 270 /** 271 * smu_set_user_clk_dependencies - set user profile clock dependencies 272 * 273 * @smu: smu_context pointer 274 * @clk: enum smu_clk_type type 275 * 276 * Enable/Disable the clock dependency for the @clk type. 277 */ 278 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 279 { 280 if (smu->adev->in_suspend) 281 return; 282 283 if (clk == SMU_MCLK) { 284 smu->user_dpm_profile.clk_dependency = 0; 285 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 286 } else if (clk == SMU_FCLK) { 287 /* MCLK takes precedence over FCLK */ 288 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 289 return; 290 291 smu->user_dpm_profile.clk_dependency = 0; 292 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 293 } else if (clk == SMU_SOCCLK) { 294 /* MCLK takes precedence over SOCCLK */ 295 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 296 return; 297 298 smu->user_dpm_profile.clk_dependency = 0; 299 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 300 } else 301 /* Add clk dependencies here, if any */ 302 return; 303 } 304 305 /** 306 * smu_restore_dpm_user_profile - reinstate user dpm profile 307 * 308 * @smu: smu_context pointer 309 * 310 * Restore the saved user power configurations include power limit, 311 * clock frequencies, fan control mode and fan speed. 312 */ 313 static void smu_restore_dpm_user_profile(struct smu_context *smu) 314 { 315 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 316 int ret = 0; 317 318 if (!smu->adev->in_suspend) 319 return; 320 321 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 322 return; 323 324 /* Enable restore flag */ 325 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 326 327 /* set the user dpm power limit */ 328 if (smu->user_dpm_profile.power_limit) { 329 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 330 if (ret) 331 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 332 } 333 334 /* set the user dpm clock configurations */ 335 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 336 enum smu_clk_type clk_type; 337 338 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 339 /* 340 * Iterate over smu clk type and force the saved user clk 341 * configs, skip if clock dependency is enabled 342 */ 343 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 344 smu->user_dpm_profile.clk_mask[clk_type]) { 345 ret = smu_force_smuclk_levels(smu, clk_type, 346 smu->user_dpm_profile.clk_mask[clk_type]); 347 if (ret) 348 dev_err(smu->adev->dev, 349 "Failed to set clock type = %d\n", clk_type); 350 } 351 } 352 } 353 354 /* set the user dpm fan configurations */ 355 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 356 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 357 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 358 if (ret != -EOPNOTSUPP) { 359 smu->user_dpm_profile.fan_speed_pwm = 0; 360 smu->user_dpm_profile.fan_speed_rpm = 0; 361 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 362 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 363 } 364 365 if (smu->user_dpm_profile.fan_speed_pwm) { 366 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 367 if (ret != -EOPNOTSUPP) 368 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 369 } 370 371 if (smu->user_dpm_profile.fan_speed_rpm) { 372 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 373 if (ret != -EOPNOTSUPP) 374 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 375 } 376 } 377 378 /* Restore user customized OD settings */ 379 if (smu->user_dpm_profile.user_od) { 380 if (smu->ppt_funcs->restore_user_od_settings) { 381 ret = smu->ppt_funcs->restore_user_od_settings(smu); 382 if (ret) 383 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 384 } 385 } 386 387 /* Disable restore flag */ 388 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 389 } 390 391 static int smu_get_power_num_states(void *handle, 392 struct pp_states_info *state_info) 393 { 394 if (!state_info) 395 return -EINVAL; 396 397 /* not support power state */ 398 memset(state_info, 0, sizeof(struct pp_states_info)); 399 state_info->nums = 1; 400 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 401 402 return 0; 403 } 404 405 bool is_support_sw_smu(struct amdgpu_device *adev) 406 { 407 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 408 if (adev->asic_type == CHIP_VEGA20) 409 return false; 410 411 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0)) 412 return true; 413 414 return false; 415 } 416 417 bool is_support_cclk_dpm(struct amdgpu_device *adev) 418 { 419 struct smu_context *smu = adev->powerplay.pp_handle; 420 421 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 422 return false; 423 424 return true; 425 } 426 427 428 static int smu_sys_get_pp_table(void *handle, 429 char **table) 430 { 431 struct smu_context *smu = handle; 432 struct smu_table_context *smu_table = &smu->smu_table; 433 434 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 435 return -EOPNOTSUPP; 436 437 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 438 return -EINVAL; 439 440 if (smu_table->hardcode_pptable) 441 *table = smu_table->hardcode_pptable; 442 else 443 *table = smu_table->power_play_table; 444 445 return smu_table->power_play_table_size; 446 } 447 448 static int smu_sys_set_pp_table(void *handle, 449 const char *buf, 450 size_t size) 451 { 452 struct smu_context *smu = handle; 453 struct smu_table_context *smu_table = &smu->smu_table; 454 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 455 int ret = 0; 456 457 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 458 return -EOPNOTSUPP; 459 460 if (header->usStructureSize != size) { 461 dev_err(smu->adev->dev, "pp table size not matched !\n"); 462 return -EIO; 463 } 464 465 if (!smu_table->hardcode_pptable) { 466 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 467 if (!smu_table->hardcode_pptable) 468 return -ENOMEM; 469 } 470 471 memcpy(smu_table->hardcode_pptable, buf, size); 472 smu_table->power_play_table = smu_table->hardcode_pptable; 473 smu_table->power_play_table_size = size; 474 475 /* 476 * Special hw_fini action(for Navi1x, the DPMs disablement will be 477 * skipped) may be needed for custom pptable uploading. 478 */ 479 smu->uploading_custom_pp_table = true; 480 481 ret = smu_reset(smu); 482 if (ret) 483 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 484 485 smu->uploading_custom_pp_table = false; 486 487 return ret; 488 } 489 490 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 491 { 492 struct smu_feature *feature = &smu->smu_feature; 493 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 494 int ret = 0; 495 496 /* 497 * With SCPM enabled, the allowed featuremasks setting(via 498 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 499 * That means there is no way to let PMFW knows the settings below. 500 * Thus, we just assume all the features are allowed under 501 * such scenario. 502 */ 503 if (smu->adev->scpm_enabled) { 504 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 505 return 0; 506 } 507 508 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 509 510 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 511 SMU_FEATURE_MAX/32); 512 if (ret) 513 return ret; 514 515 bitmap_or(feature->allowed, feature->allowed, 516 (unsigned long *)allowed_feature_mask, 517 feature->feature_num); 518 519 return ret; 520 } 521 522 static int smu_set_funcs(struct amdgpu_device *adev) 523 { 524 struct smu_context *smu = adev->powerplay.pp_handle; 525 526 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 527 smu->od_enabled = true; 528 529 switch (adev->ip_versions[MP1_HWIP][0]) { 530 case IP_VERSION(11, 0, 0): 531 case IP_VERSION(11, 0, 5): 532 case IP_VERSION(11, 0, 9): 533 navi10_set_ppt_funcs(smu); 534 break; 535 case IP_VERSION(11, 0, 7): 536 case IP_VERSION(11, 0, 11): 537 case IP_VERSION(11, 0, 12): 538 case IP_VERSION(11, 0, 13): 539 sienna_cichlid_set_ppt_funcs(smu); 540 break; 541 case IP_VERSION(12, 0, 0): 542 case IP_VERSION(12, 0, 1): 543 renoir_set_ppt_funcs(smu); 544 break; 545 case IP_VERSION(11, 5, 0): 546 vangogh_set_ppt_funcs(smu); 547 break; 548 case IP_VERSION(13, 0, 1): 549 case IP_VERSION(13, 0, 3): 550 case IP_VERSION(13, 0, 8): 551 yellow_carp_set_ppt_funcs(smu); 552 break; 553 case IP_VERSION(13, 0, 5): 554 smu_v13_0_5_set_ppt_funcs(smu); 555 break; 556 case IP_VERSION(11, 0, 8): 557 cyan_skillfish_set_ppt_funcs(smu); 558 break; 559 case IP_VERSION(11, 0, 2): 560 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 561 arcturus_set_ppt_funcs(smu); 562 /* OD is not supported on Arcturus */ 563 smu->od_enabled =false; 564 break; 565 case IP_VERSION(13, 0, 2): 566 aldebaran_set_ppt_funcs(smu); 567 /* Enable pp_od_clk_voltage node */ 568 smu->od_enabled = true; 569 break; 570 case IP_VERSION(13, 0, 0): 571 smu_v13_0_0_set_ppt_funcs(smu); 572 break; 573 case IP_VERSION(13, 0, 7): 574 smu_v13_0_7_set_ppt_funcs(smu); 575 break; 576 default: 577 return -EINVAL; 578 } 579 580 return 0; 581 } 582 583 static int smu_early_init(void *handle) 584 { 585 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 586 struct smu_context *smu; 587 588 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 589 if (!smu) 590 return -ENOMEM; 591 592 smu->adev = adev; 593 smu->pm_enabled = !!amdgpu_dpm; 594 smu->is_apu = false; 595 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 596 smu->smu_baco.platform_support = false; 597 smu->user_dpm_profile.fan_mode = -1; 598 599 adev->powerplay.pp_handle = smu; 600 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 601 602 return smu_set_funcs(adev); 603 } 604 605 static int smu_set_default_dpm_table(struct smu_context *smu) 606 { 607 struct smu_power_context *smu_power = &smu->smu_power; 608 struct smu_power_gate *power_gate = &smu_power->power_gate; 609 int vcn_gate, jpeg_gate; 610 int ret = 0; 611 612 if (!smu->ppt_funcs->set_default_dpm_table) 613 return 0; 614 615 vcn_gate = atomic_read(&power_gate->vcn_gated); 616 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 617 618 ret = smu_dpm_set_vcn_enable(smu, true); 619 if (ret) 620 return ret; 621 622 ret = smu_dpm_set_jpeg_enable(smu, true); 623 if (ret) 624 goto err_out; 625 626 ret = smu->ppt_funcs->set_default_dpm_table(smu); 627 if (ret) 628 dev_err(smu->adev->dev, 629 "Failed to setup default dpm clock tables!\n"); 630 631 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 632 err_out: 633 smu_dpm_set_vcn_enable(smu, !vcn_gate); 634 return ret; 635 } 636 637 static int smu_apply_default_config_table_settings(struct smu_context *smu) 638 { 639 struct amdgpu_device *adev = smu->adev; 640 int ret = 0; 641 642 ret = smu_get_default_config_table_settings(smu, 643 &adev->pm.config_table); 644 if (ret) 645 return ret; 646 647 return smu_set_config_table(smu, &adev->pm.config_table); 648 } 649 650 static int smu_late_init(void *handle) 651 { 652 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 653 struct smu_context *smu = adev->powerplay.pp_handle; 654 int ret = 0; 655 656 smu_set_fine_grain_gfx_freq_parameters(smu); 657 658 if (!smu->pm_enabled) 659 return 0; 660 661 ret = smu_post_init(smu); 662 if (ret) { 663 dev_err(adev->dev, "Failed to post smu init!\n"); 664 return ret; 665 } 666 667 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || 668 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) 669 return 0; 670 671 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 672 ret = smu_set_default_od_settings(smu); 673 if (ret) { 674 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 675 return ret; 676 } 677 } 678 679 ret = smu_populate_umd_state_clk(smu); 680 if (ret) { 681 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 682 return ret; 683 } 684 685 ret = smu_get_asic_power_limits(smu, 686 &smu->current_power_limit, 687 &smu->default_power_limit, 688 &smu->max_power_limit); 689 if (ret) { 690 dev_err(adev->dev, "Failed to get asic power limits!\n"); 691 return ret; 692 } 693 694 if (!amdgpu_sriov_vf(adev)) 695 smu_get_unique_id(smu); 696 697 smu_get_fan_parameters(smu); 698 699 smu_handle_task(smu, 700 smu->smu_dpm.dpm_level, 701 AMD_PP_TASK_COMPLETE_INIT); 702 703 ret = smu_apply_default_config_table_settings(smu); 704 if (ret && (ret != -EOPNOTSUPP)) { 705 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 706 return ret; 707 } 708 709 smu_restore_dpm_user_profile(smu); 710 711 return 0; 712 } 713 714 static int smu_init_fb_allocations(struct smu_context *smu) 715 { 716 struct amdgpu_device *adev = smu->adev; 717 struct smu_table_context *smu_table = &smu->smu_table; 718 struct smu_table *tables = smu_table->tables; 719 struct smu_table *driver_table = &(smu_table->driver_table); 720 uint32_t max_table_size = 0; 721 int ret, i; 722 723 /* VRAM allocation for tool table */ 724 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 725 ret = amdgpu_bo_create_kernel(adev, 726 tables[SMU_TABLE_PMSTATUSLOG].size, 727 tables[SMU_TABLE_PMSTATUSLOG].align, 728 tables[SMU_TABLE_PMSTATUSLOG].domain, 729 &tables[SMU_TABLE_PMSTATUSLOG].bo, 730 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 731 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 732 if (ret) { 733 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 734 return ret; 735 } 736 } 737 738 /* VRAM allocation for driver table */ 739 for (i = 0; i < SMU_TABLE_COUNT; i++) { 740 if (tables[i].size == 0) 741 continue; 742 743 if (i == SMU_TABLE_PMSTATUSLOG) 744 continue; 745 746 if (max_table_size < tables[i].size) 747 max_table_size = tables[i].size; 748 } 749 750 driver_table->size = max_table_size; 751 driver_table->align = PAGE_SIZE; 752 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 753 754 ret = amdgpu_bo_create_kernel(adev, 755 driver_table->size, 756 driver_table->align, 757 driver_table->domain, 758 &driver_table->bo, 759 &driver_table->mc_address, 760 &driver_table->cpu_addr); 761 if (ret) { 762 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 763 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 764 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 765 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 766 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 767 } 768 769 return ret; 770 } 771 772 static int smu_fini_fb_allocations(struct smu_context *smu) 773 { 774 struct smu_table_context *smu_table = &smu->smu_table; 775 struct smu_table *tables = smu_table->tables; 776 struct smu_table *driver_table = &(smu_table->driver_table); 777 778 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 779 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 780 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 781 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 782 783 amdgpu_bo_free_kernel(&driver_table->bo, 784 &driver_table->mc_address, 785 &driver_table->cpu_addr); 786 787 return 0; 788 } 789 790 /** 791 * smu_alloc_memory_pool - allocate memory pool in the system memory 792 * 793 * @smu: amdgpu_device pointer 794 * 795 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 796 * and DramLogSetDramAddr can notify it changed. 797 * 798 * Returns 0 on success, error on failure. 799 */ 800 static int smu_alloc_memory_pool(struct smu_context *smu) 801 { 802 struct amdgpu_device *adev = smu->adev; 803 struct smu_table_context *smu_table = &smu->smu_table; 804 struct smu_table *memory_pool = &smu_table->memory_pool; 805 uint64_t pool_size = smu->pool_size; 806 int ret = 0; 807 808 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 809 return ret; 810 811 memory_pool->size = pool_size; 812 memory_pool->align = PAGE_SIZE; 813 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 814 815 switch (pool_size) { 816 case SMU_MEMORY_POOL_SIZE_256_MB: 817 case SMU_MEMORY_POOL_SIZE_512_MB: 818 case SMU_MEMORY_POOL_SIZE_1_GB: 819 case SMU_MEMORY_POOL_SIZE_2_GB: 820 ret = amdgpu_bo_create_kernel(adev, 821 memory_pool->size, 822 memory_pool->align, 823 memory_pool->domain, 824 &memory_pool->bo, 825 &memory_pool->mc_address, 826 &memory_pool->cpu_addr); 827 if (ret) 828 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 829 break; 830 default: 831 break; 832 } 833 834 return ret; 835 } 836 837 static int smu_free_memory_pool(struct smu_context *smu) 838 { 839 struct smu_table_context *smu_table = &smu->smu_table; 840 struct smu_table *memory_pool = &smu_table->memory_pool; 841 842 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 843 return 0; 844 845 amdgpu_bo_free_kernel(&memory_pool->bo, 846 &memory_pool->mc_address, 847 &memory_pool->cpu_addr); 848 849 memset(memory_pool, 0, sizeof(struct smu_table)); 850 851 return 0; 852 } 853 854 static int smu_alloc_dummy_read_table(struct smu_context *smu) 855 { 856 struct smu_table_context *smu_table = &smu->smu_table; 857 struct smu_table *dummy_read_1_table = 858 &smu_table->dummy_read_1_table; 859 struct amdgpu_device *adev = smu->adev; 860 int ret = 0; 861 862 dummy_read_1_table->size = 0x40000; 863 dummy_read_1_table->align = PAGE_SIZE; 864 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 865 866 ret = amdgpu_bo_create_kernel(adev, 867 dummy_read_1_table->size, 868 dummy_read_1_table->align, 869 dummy_read_1_table->domain, 870 &dummy_read_1_table->bo, 871 &dummy_read_1_table->mc_address, 872 &dummy_read_1_table->cpu_addr); 873 if (ret) 874 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 875 876 return ret; 877 } 878 879 static void smu_free_dummy_read_table(struct smu_context *smu) 880 { 881 struct smu_table_context *smu_table = &smu->smu_table; 882 struct smu_table *dummy_read_1_table = 883 &smu_table->dummy_read_1_table; 884 885 886 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 887 &dummy_read_1_table->mc_address, 888 &dummy_read_1_table->cpu_addr); 889 890 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 891 } 892 893 static int smu_smc_table_sw_init(struct smu_context *smu) 894 { 895 int ret; 896 897 /** 898 * Create smu_table structure, and init smc tables such as 899 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 900 */ 901 ret = smu_init_smc_tables(smu); 902 if (ret) { 903 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 904 return ret; 905 } 906 907 /** 908 * Create smu_power_context structure, and allocate smu_dpm_context and 909 * context size to fill the smu_power_context data. 910 */ 911 ret = smu_init_power(smu); 912 if (ret) { 913 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 914 return ret; 915 } 916 917 /* 918 * allocate vram bos to store smc table contents. 919 */ 920 ret = smu_init_fb_allocations(smu); 921 if (ret) 922 return ret; 923 924 ret = smu_alloc_memory_pool(smu); 925 if (ret) 926 return ret; 927 928 ret = smu_alloc_dummy_read_table(smu); 929 if (ret) 930 return ret; 931 932 ret = smu_i2c_init(smu); 933 if (ret) 934 return ret; 935 936 return 0; 937 } 938 939 static int smu_smc_table_sw_fini(struct smu_context *smu) 940 { 941 int ret; 942 943 smu_i2c_fini(smu); 944 945 smu_free_dummy_read_table(smu); 946 947 ret = smu_free_memory_pool(smu); 948 if (ret) 949 return ret; 950 951 ret = smu_fini_fb_allocations(smu); 952 if (ret) 953 return ret; 954 955 ret = smu_fini_power(smu); 956 if (ret) { 957 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 958 return ret; 959 } 960 961 ret = smu_fini_smc_tables(smu); 962 if (ret) { 963 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 964 return ret; 965 } 966 967 return 0; 968 } 969 970 static void smu_throttling_logging_work_fn(struct work_struct *work) 971 { 972 struct smu_context *smu = container_of(work, struct smu_context, 973 throttling_logging_work); 974 975 smu_log_thermal_throttling(smu); 976 } 977 978 static void smu_interrupt_work_fn(struct work_struct *work) 979 { 980 struct smu_context *smu = container_of(work, struct smu_context, 981 interrupt_work); 982 983 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 984 smu->ppt_funcs->interrupt_work(smu); 985 } 986 987 static int smu_sw_init(void *handle) 988 { 989 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 990 struct smu_context *smu = adev->powerplay.pp_handle; 991 int ret; 992 993 smu->pool_size = adev->pm.smu_prv_buffer_size; 994 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 995 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 996 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 997 998 mutex_init(&smu->message_lock); 999 1000 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1001 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1002 atomic64_set(&smu->throttle_int_counter, 0); 1003 smu->watermarks_bitmap = 0; 1004 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1005 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1006 1007 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1008 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1009 1010 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1011 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1012 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1013 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1014 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1015 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1016 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1017 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1018 1019 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1020 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1021 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1022 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1023 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1024 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1025 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1026 smu->display_config = &adev->pm.pm_display_cfg; 1027 1028 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1029 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1030 1031 ret = smu_init_microcode(smu); 1032 if (ret) { 1033 dev_err(adev->dev, "Failed to load smu firmware!\n"); 1034 return ret; 1035 } 1036 1037 ret = smu_smc_table_sw_init(smu); 1038 if (ret) { 1039 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1040 return ret; 1041 } 1042 1043 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1044 ret = smu_get_vbios_bootup_values(smu); 1045 if (ret) { 1046 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1047 return ret; 1048 } 1049 1050 ret = smu_init_pptable_microcode(smu); 1051 if (ret) { 1052 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1053 return ret; 1054 } 1055 1056 ret = smu_register_irq_handler(smu); 1057 if (ret) { 1058 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1059 return ret; 1060 } 1061 1062 /* If there is no way to query fan control mode, fan control is not supported */ 1063 if (!smu->ppt_funcs->get_fan_control_mode) 1064 smu->adev->pm.no_fan = true; 1065 1066 return 0; 1067 } 1068 1069 static int smu_sw_fini(void *handle) 1070 { 1071 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1072 struct smu_context *smu = adev->powerplay.pp_handle; 1073 int ret; 1074 1075 ret = smu_smc_table_sw_fini(smu); 1076 if (ret) { 1077 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1078 return ret; 1079 } 1080 1081 smu_fini_microcode(smu); 1082 1083 return 0; 1084 } 1085 1086 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1087 { 1088 struct amdgpu_device *adev = smu->adev; 1089 struct smu_temperature_range *range = 1090 &smu->thermal_range; 1091 int ret = 0; 1092 1093 if (!smu->ppt_funcs->get_thermal_temperature_range) 1094 return 0; 1095 1096 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1097 if (ret) 1098 return ret; 1099 1100 adev->pm.dpm.thermal.min_temp = range->min; 1101 adev->pm.dpm.thermal.max_temp = range->max; 1102 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1103 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1104 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1105 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1106 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1107 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1108 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1109 1110 return ret; 1111 } 1112 1113 static int smu_smc_hw_setup(struct smu_context *smu) 1114 { 1115 struct smu_feature *feature = &smu->smu_feature; 1116 struct amdgpu_device *adev = smu->adev; 1117 uint32_t pcie_gen = 0, pcie_width = 0; 1118 uint64_t features_supported; 1119 int ret = 0; 1120 1121 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1122 dev_info(adev->dev, "dpm has been enabled\n"); 1123 /* this is needed specifically */ 1124 switch (adev->ip_versions[MP1_HWIP][0]) { 1125 case IP_VERSION(11, 0, 7): 1126 case IP_VERSION(11, 0, 11): 1127 case IP_VERSION(11, 5, 0): 1128 case IP_VERSION(11, 0, 12): 1129 ret = smu_system_features_control(smu, true); 1130 if (ret) 1131 dev_err(adev->dev, "Failed system features control!\n"); 1132 break; 1133 default: 1134 break; 1135 } 1136 return ret; 1137 } 1138 1139 ret = smu_init_display_count(smu, 0); 1140 if (ret) { 1141 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1142 return ret; 1143 } 1144 1145 ret = smu_set_driver_table_location(smu); 1146 if (ret) { 1147 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1148 return ret; 1149 } 1150 1151 /* 1152 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1153 */ 1154 ret = smu_set_tool_table_location(smu); 1155 if (ret) { 1156 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1157 return ret; 1158 } 1159 1160 /* 1161 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1162 * pool location. 1163 */ 1164 ret = smu_notify_memory_pool_location(smu); 1165 if (ret) { 1166 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1167 return ret; 1168 } 1169 1170 ret = smu_setup_pptable(smu); 1171 if (ret) { 1172 dev_err(adev->dev, "Failed to setup pptable!\n"); 1173 return ret; 1174 } 1175 1176 /* smu_dump_pptable(smu); */ 1177 1178 /* 1179 * With SCPM enabled, PSP is responsible for the PPTable transferring 1180 * (to SMU). Driver involvement is not needed and permitted. 1181 */ 1182 if (!adev->scpm_enabled) { 1183 /* 1184 * Copy pptable bo in the vram to smc with SMU MSGs such as 1185 * SetDriverDramAddr and TransferTableDram2Smu. 1186 */ 1187 ret = smu_write_pptable(smu); 1188 if (ret) { 1189 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1190 return ret; 1191 } 1192 } 1193 1194 /* issue Run*Btc msg */ 1195 ret = smu_run_btc(smu); 1196 if (ret) 1197 return ret; 1198 1199 /* 1200 * With SCPM enabled, these actions(and relevant messages) are 1201 * not needed and permitted. 1202 */ 1203 if (!adev->scpm_enabled) { 1204 ret = smu_feature_set_allowed_mask(smu); 1205 if (ret) { 1206 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1207 return ret; 1208 } 1209 } 1210 1211 ret = smu_system_features_control(smu, true); 1212 if (ret) { 1213 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1214 return ret; 1215 } 1216 1217 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1218 if (ret) { 1219 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1220 return ret; 1221 } 1222 bitmap_copy(feature->supported, 1223 (unsigned long *)&features_supported, 1224 feature->feature_num); 1225 1226 if (!smu_is_dpm_running(smu)) 1227 dev_info(adev->dev, "dpm has been disabled\n"); 1228 1229 /* 1230 * Set initialized values (get from vbios) to dpm tables context such as 1231 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1232 * type of clks. 1233 */ 1234 ret = smu_set_default_dpm_table(smu); 1235 if (ret) { 1236 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1237 return ret; 1238 } 1239 1240 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1241 pcie_gen = 3; 1242 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1243 pcie_gen = 2; 1244 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1245 pcie_gen = 1; 1246 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1247 pcie_gen = 0; 1248 1249 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1250 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1251 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1252 */ 1253 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1254 pcie_width = 6; 1255 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1256 pcie_width = 5; 1257 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1258 pcie_width = 4; 1259 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1260 pcie_width = 3; 1261 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1262 pcie_width = 2; 1263 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1264 pcie_width = 1; 1265 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1266 if (ret) { 1267 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1268 return ret; 1269 } 1270 1271 ret = smu_get_thermal_temperature_range(smu); 1272 if (ret) { 1273 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1274 return ret; 1275 } 1276 1277 ret = smu_enable_thermal_alert(smu); 1278 if (ret) { 1279 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1280 return ret; 1281 } 1282 1283 ret = smu_notify_display_change(smu); 1284 if (ret) { 1285 dev_err(adev->dev, "Failed to notify display change!\n"); 1286 return ret; 1287 } 1288 1289 /* 1290 * Set min deep sleep dce fclk with bootup value from vbios via 1291 * SetMinDeepSleepDcefclk MSG. 1292 */ 1293 ret = smu_set_min_dcef_deep_sleep(smu, 1294 smu->smu_table.boot_values.dcefclk / 100); 1295 1296 return ret; 1297 } 1298 1299 static int smu_start_smc_engine(struct smu_context *smu) 1300 { 1301 struct amdgpu_device *adev = smu->adev; 1302 int ret = 0; 1303 1304 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1305 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) { 1306 if (smu->ppt_funcs->load_microcode) { 1307 ret = smu->ppt_funcs->load_microcode(smu); 1308 if (ret) 1309 return ret; 1310 } 1311 } 1312 } 1313 1314 if (smu->ppt_funcs->check_fw_status) { 1315 ret = smu->ppt_funcs->check_fw_status(smu); 1316 if (ret) { 1317 dev_err(adev->dev, "SMC is not ready\n"); 1318 return ret; 1319 } 1320 } 1321 1322 /* 1323 * Send msg GetDriverIfVersion to check if the return value is equal 1324 * with DRIVER_IF_VERSION of smc header. 1325 */ 1326 ret = smu_check_fw_version(smu); 1327 if (ret) 1328 return ret; 1329 1330 return ret; 1331 } 1332 1333 static int smu_hw_init(void *handle) 1334 { 1335 int ret; 1336 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1337 struct smu_context *smu = adev->powerplay.pp_handle; 1338 1339 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1340 smu->pm_enabled = false; 1341 return 0; 1342 } 1343 1344 ret = smu_start_smc_engine(smu); 1345 if (ret) { 1346 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1347 return ret; 1348 } 1349 1350 if (smu->is_apu) { 1351 smu_dpm_set_vcn_enable(smu, true); 1352 smu_dpm_set_jpeg_enable(smu, true); 1353 smu_set_gfx_cgpg(smu, true); 1354 } 1355 1356 if (!smu->pm_enabled) 1357 return 0; 1358 1359 ret = smu_get_driver_allowed_feature_mask(smu); 1360 if (ret) 1361 return ret; 1362 1363 ret = smu_smc_hw_setup(smu); 1364 if (ret) { 1365 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1366 return ret; 1367 } 1368 1369 /* 1370 * Move maximum sustainable clock retrieving here considering 1371 * 1. It is not needed on resume(from S3). 1372 * 2. DAL settings come between .hw_init and .late_init of SMU. 1373 * And DAL needs to know the maximum sustainable clocks. Thus 1374 * it cannot be put in .late_init(). 1375 */ 1376 ret = smu_init_max_sustainable_clocks(smu); 1377 if (ret) { 1378 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1379 return ret; 1380 } 1381 1382 adev->pm.dpm_enabled = true; 1383 1384 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1385 1386 return 0; 1387 } 1388 1389 static int smu_disable_dpms(struct smu_context *smu) 1390 { 1391 struct amdgpu_device *adev = smu->adev; 1392 int ret = 0; 1393 /* 1394 * TODO: (adev->in_suspend && !adev->in_s0ix) is added to pair 1395 * the workaround which always reset the asic in suspend. 1396 * It's likely that workaround will be dropped in the future. 1397 * Then the change here should be dropped together. 1398 */ 1399 bool use_baco = !smu->is_apu && 1400 (((amdgpu_in_reset(adev) || (adev->in_suspend && !adev->in_s0ix)) && 1401 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1402 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1403 1404 /* 1405 * For custom pptable uploading, skip the DPM features 1406 * disable process on Navi1x ASICs. 1407 * - As the gfx related features are under control of 1408 * RLC on those ASICs. RLC reinitialization will be 1409 * needed to reenable them. That will cost much more 1410 * efforts. 1411 * 1412 * - SMU firmware can handle the DPM reenablement 1413 * properly. 1414 */ 1415 if (smu->uploading_custom_pp_table) { 1416 switch (adev->ip_versions[MP1_HWIP][0]) { 1417 case IP_VERSION(11, 0, 0): 1418 case IP_VERSION(11, 0, 5): 1419 case IP_VERSION(11, 0, 9): 1420 case IP_VERSION(11, 0, 7): 1421 case IP_VERSION(11, 0, 11): 1422 case IP_VERSION(11, 5, 0): 1423 case IP_VERSION(11, 0, 12): 1424 case IP_VERSION(11, 0, 13): 1425 return 0; 1426 default: 1427 break; 1428 } 1429 } 1430 1431 /* 1432 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1433 * on BACO in. Driver involvement is unnecessary. 1434 */ 1435 if (use_baco) { 1436 switch (adev->ip_versions[MP1_HWIP][0]) { 1437 case IP_VERSION(11, 0, 7): 1438 case IP_VERSION(11, 0, 0): 1439 case IP_VERSION(11, 0, 5): 1440 case IP_VERSION(11, 0, 9): 1441 return 0; 1442 default: 1443 break; 1444 } 1445 } 1446 1447 /* 1448 * For gpu reset, runpm and hibernation through BACO, 1449 * BACO feature has to be kept enabled. 1450 */ 1451 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1452 ret = smu_disable_all_features_with_exception(smu, 1453 SMU_FEATURE_BACO_BIT); 1454 if (ret) 1455 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1456 } else { 1457 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1458 if (!adev->scpm_enabled) { 1459 ret = smu_system_features_control(smu, false); 1460 if (ret) 1461 dev_err(adev->dev, "Failed to disable smu features.\n"); 1462 } 1463 } 1464 1465 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) && 1466 adev->gfx.rlc.funcs->stop) 1467 adev->gfx.rlc.funcs->stop(adev); 1468 1469 return ret; 1470 } 1471 1472 static int smu_smc_hw_cleanup(struct smu_context *smu) 1473 { 1474 struct amdgpu_device *adev = smu->adev; 1475 int ret = 0; 1476 1477 cancel_work_sync(&smu->throttling_logging_work); 1478 cancel_work_sync(&smu->interrupt_work); 1479 1480 ret = smu_disable_thermal_alert(smu); 1481 if (ret) { 1482 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1483 return ret; 1484 } 1485 1486 ret = smu_disable_dpms(smu); 1487 if (ret) { 1488 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1489 return ret; 1490 } 1491 1492 return 0; 1493 } 1494 1495 static int smu_hw_fini(void *handle) 1496 { 1497 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1498 struct smu_context *smu = adev->powerplay.pp_handle; 1499 1500 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1501 return 0; 1502 1503 smu_dpm_set_vcn_enable(smu, false); 1504 smu_dpm_set_jpeg_enable(smu, false); 1505 1506 adev->vcn.cur_state = AMD_PG_STATE_GATE; 1507 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 1508 1509 if (!smu->pm_enabled) 1510 return 0; 1511 1512 adev->pm.dpm_enabled = false; 1513 1514 return smu_smc_hw_cleanup(smu); 1515 } 1516 1517 static void smu_late_fini(void *handle) 1518 { 1519 struct amdgpu_device *adev = handle; 1520 struct smu_context *smu = adev->powerplay.pp_handle; 1521 1522 kfree(smu); 1523 } 1524 1525 static int smu_reset(struct smu_context *smu) 1526 { 1527 struct amdgpu_device *adev = smu->adev; 1528 int ret; 1529 1530 ret = smu_hw_fini(adev); 1531 if (ret) 1532 return ret; 1533 1534 ret = smu_hw_init(adev); 1535 if (ret) 1536 return ret; 1537 1538 ret = smu_late_init(adev); 1539 if (ret) 1540 return ret; 1541 1542 return 0; 1543 } 1544 1545 static int smu_suspend(void *handle) 1546 { 1547 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1548 struct smu_context *smu = adev->powerplay.pp_handle; 1549 int ret; 1550 1551 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1552 return 0; 1553 1554 if (!smu->pm_enabled) 1555 return 0; 1556 1557 adev->pm.dpm_enabled = false; 1558 1559 ret = smu_smc_hw_cleanup(smu); 1560 if (ret) 1561 return ret; 1562 1563 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1564 1565 smu_set_gfx_cgpg(smu, false); 1566 1567 return 0; 1568 } 1569 1570 static int smu_resume(void *handle) 1571 { 1572 int ret; 1573 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1574 struct smu_context *smu = adev->powerplay.pp_handle; 1575 1576 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1577 return 0; 1578 1579 if (!smu->pm_enabled) 1580 return 0; 1581 1582 dev_info(adev->dev, "SMU is resuming...\n"); 1583 1584 ret = smu_start_smc_engine(smu); 1585 if (ret) { 1586 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1587 return ret; 1588 } 1589 1590 ret = smu_smc_hw_setup(smu); 1591 if (ret) { 1592 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1593 return ret; 1594 } 1595 1596 smu_set_gfx_cgpg(smu, true); 1597 1598 smu->disable_uclk_switch = 0; 1599 1600 adev->pm.dpm_enabled = true; 1601 1602 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1603 1604 return 0; 1605 } 1606 1607 static int smu_display_configuration_change(void *handle, 1608 const struct amd_pp_display_configuration *display_config) 1609 { 1610 struct smu_context *smu = handle; 1611 int index = 0; 1612 int num_of_active_display = 0; 1613 1614 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1615 return -EOPNOTSUPP; 1616 1617 if (!display_config) 1618 return -EINVAL; 1619 1620 smu_set_min_dcef_deep_sleep(smu, 1621 display_config->min_dcef_deep_sleep_set_clk / 100); 1622 1623 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1624 if (display_config->displays[index].controller_id != 0) 1625 num_of_active_display++; 1626 } 1627 1628 return 0; 1629 } 1630 1631 static int smu_set_clockgating_state(void *handle, 1632 enum amd_clockgating_state state) 1633 { 1634 return 0; 1635 } 1636 1637 static int smu_set_powergating_state(void *handle, 1638 enum amd_powergating_state state) 1639 { 1640 return 0; 1641 } 1642 1643 static int smu_enable_umd_pstate(void *handle, 1644 enum amd_dpm_forced_level *level) 1645 { 1646 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1647 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1648 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1649 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1650 1651 struct smu_context *smu = (struct smu_context*)(handle); 1652 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1653 1654 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1655 return -EINVAL; 1656 1657 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1658 /* enter umd pstate, save current level, disable gfx cg*/ 1659 if (*level & profile_mode_mask) { 1660 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1661 smu_gpo_control(smu, false); 1662 smu_gfx_ulv_control(smu, false); 1663 smu_deep_sleep_control(smu, false); 1664 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1665 } 1666 } else { 1667 /* exit umd pstate, restore level, enable gfx cg*/ 1668 if (!(*level & profile_mode_mask)) { 1669 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1670 *level = smu_dpm_ctx->saved_dpm_level; 1671 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1672 smu_deep_sleep_control(smu, true); 1673 smu_gfx_ulv_control(smu, true); 1674 smu_gpo_control(smu, true); 1675 } 1676 } 1677 1678 return 0; 1679 } 1680 1681 static int smu_bump_power_profile_mode(struct smu_context *smu, 1682 long *param, 1683 uint32_t param_size) 1684 { 1685 int ret = 0; 1686 1687 if (smu->ppt_funcs->set_power_profile_mode) 1688 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1689 1690 return ret; 1691 } 1692 1693 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1694 enum amd_dpm_forced_level level, 1695 bool skip_display_settings) 1696 { 1697 int ret = 0; 1698 int index = 0; 1699 long workload; 1700 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1701 1702 if (!skip_display_settings) { 1703 ret = smu_display_config_changed(smu); 1704 if (ret) { 1705 dev_err(smu->adev->dev, "Failed to change display config!"); 1706 return ret; 1707 } 1708 } 1709 1710 ret = smu_apply_clocks_adjust_rules(smu); 1711 if (ret) { 1712 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1713 return ret; 1714 } 1715 1716 if (!skip_display_settings) { 1717 ret = smu_notify_smc_display_config(smu); 1718 if (ret) { 1719 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1720 return ret; 1721 } 1722 } 1723 1724 if (smu_dpm_ctx->dpm_level != level) { 1725 ret = smu_asic_set_performance_level(smu, level); 1726 if (ret) { 1727 dev_err(smu->adev->dev, "Failed to set performance level!"); 1728 return ret; 1729 } 1730 1731 /* update the saved copy */ 1732 smu_dpm_ctx->dpm_level = level; 1733 } 1734 1735 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1736 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1737 index = fls(smu->workload_mask); 1738 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1739 workload = smu->workload_setting[index]; 1740 1741 if (smu->power_profile_mode != workload) 1742 smu_bump_power_profile_mode(smu, &workload, 0); 1743 } 1744 1745 return ret; 1746 } 1747 1748 static int smu_handle_task(struct smu_context *smu, 1749 enum amd_dpm_forced_level level, 1750 enum amd_pp_task task_id) 1751 { 1752 int ret = 0; 1753 1754 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1755 return -EOPNOTSUPP; 1756 1757 switch (task_id) { 1758 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1759 ret = smu_pre_display_config_changed(smu); 1760 if (ret) 1761 return ret; 1762 ret = smu_adjust_power_state_dynamic(smu, level, false); 1763 break; 1764 case AMD_PP_TASK_COMPLETE_INIT: 1765 case AMD_PP_TASK_READJUST_POWER_STATE: 1766 ret = smu_adjust_power_state_dynamic(smu, level, true); 1767 break; 1768 default: 1769 break; 1770 } 1771 1772 return ret; 1773 } 1774 1775 static int smu_handle_dpm_task(void *handle, 1776 enum amd_pp_task task_id, 1777 enum amd_pm_state_type *user_state) 1778 { 1779 struct smu_context *smu = handle; 1780 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1781 1782 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 1783 1784 } 1785 1786 static int smu_switch_power_profile(void *handle, 1787 enum PP_SMC_POWER_PROFILE type, 1788 bool en) 1789 { 1790 struct smu_context *smu = handle; 1791 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1792 long workload; 1793 uint32_t index; 1794 1795 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1796 return -EOPNOTSUPP; 1797 1798 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1799 return -EINVAL; 1800 1801 if (!en) { 1802 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1803 index = fls(smu->workload_mask); 1804 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1805 workload = smu->workload_setting[index]; 1806 } else { 1807 smu->workload_mask |= (1 << smu->workload_prority[type]); 1808 index = fls(smu->workload_mask); 1809 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1810 workload = smu->workload_setting[index]; 1811 } 1812 1813 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1814 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1815 smu_bump_power_profile_mode(smu, &workload, 0); 1816 1817 return 0; 1818 } 1819 1820 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 1821 { 1822 struct smu_context *smu = handle; 1823 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1824 1825 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1826 return -EOPNOTSUPP; 1827 1828 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1829 return -EINVAL; 1830 1831 return smu_dpm_ctx->dpm_level; 1832 } 1833 1834 static int smu_force_performance_level(void *handle, 1835 enum amd_dpm_forced_level level) 1836 { 1837 struct smu_context *smu = handle; 1838 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1839 int ret = 0; 1840 1841 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1842 return -EOPNOTSUPP; 1843 1844 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1845 return -EINVAL; 1846 1847 ret = smu_enable_umd_pstate(smu, &level); 1848 if (ret) 1849 return ret; 1850 1851 ret = smu_handle_task(smu, level, 1852 AMD_PP_TASK_READJUST_POWER_STATE); 1853 1854 /* reset user dpm clock state */ 1855 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1856 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 1857 smu->user_dpm_profile.clk_dependency = 0; 1858 } 1859 1860 return ret; 1861 } 1862 1863 static int smu_set_display_count(void *handle, uint32_t count) 1864 { 1865 struct smu_context *smu = handle; 1866 1867 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1868 return -EOPNOTSUPP; 1869 1870 return smu_init_display_count(smu, count); 1871 } 1872 1873 static int smu_force_smuclk_levels(struct smu_context *smu, 1874 enum smu_clk_type clk_type, 1875 uint32_t mask) 1876 { 1877 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1878 int ret = 0; 1879 1880 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1881 return -EOPNOTSUPP; 1882 1883 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1884 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1885 return -EINVAL; 1886 } 1887 1888 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 1889 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1890 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 1891 smu->user_dpm_profile.clk_mask[clk_type] = mask; 1892 smu_set_user_clk_dependencies(smu, clk_type); 1893 } 1894 } 1895 1896 return ret; 1897 } 1898 1899 static int smu_force_ppclk_levels(void *handle, 1900 enum pp_clock_type type, 1901 uint32_t mask) 1902 { 1903 struct smu_context *smu = handle; 1904 enum smu_clk_type clk_type; 1905 1906 switch (type) { 1907 case PP_SCLK: 1908 clk_type = SMU_SCLK; break; 1909 case PP_MCLK: 1910 clk_type = SMU_MCLK; break; 1911 case PP_PCIE: 1912 clk_type = SMU_PCIE; break; 1913 case PP_SOCCLK: 1914 clk_type = SMU_SOCCLK; break; 1915 case PP_FCLK: 1916 clk_type = SMU_FCLK; break; 1917 case PP_DCEFCLK: 1918 clk_type = SMU_DCEFCLK; break; 1919 case PP_VCLK: 1920 clk_type = SMU_VCLK; break; 1921 case PP_DCLK: 1922 clk_type = SMU_DCLK; break; 1923 case OD_SCLK: 1924 clk_type = SMU_OD_SCLK; break; 1925 case OD_MCLK: 1926 clk_type = SMU_OD_MCLK; break; 1927 case OD_VDDC_CURVE: 1928 clk_type = SMU_OD_VDDC_CURVE; break; 1929 case OD_RANGE: 1930 clk_type = SMU_OD_RANGE; break; 1931 default: 1932 return -EINVAL; 1933 } 1934 1935 return smu_force_smuclk_levels(smu, clk_type, mask); 1936 } 1937 1938 /* 1939 * On system suspending or resetting, the dpm_enabled 1940 * flag will be cleared. So that those SMU services which 1941 * are not supported will be gated. 1942 * However, the mp1 state setting should still be granted 1943 * even if the dpm_enabled cleared. 1944 */ 1945 static int smu_set_mp1_state(void *handle, 1946 enum pp_mp1_state mp1_state) 1947 { 1948 struct smu_context *smu = handle; 1949 int ret = 0; 1950 1951 if (!smu->pm_enabled) 1952 return -EOPNOTSUPP; 1953 1954 if (smu->ppt_funcs && 1955 smu->ppt_funcs->set_mp1_state) 1956 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 1957 1958 return ret; 1959 } 1960 1961 static int smu_set_df_cstate(void *handle, 1962 enum pp_df_cstate state) 1963 { 1964 struct smu_context *smu = handle; 1965 int ret = 0; 1966 1967 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1968 return -EOPNOTSUPP; 1969 1970 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 1971 return 0; 1972 1973 ret = smu->ppt_funcs->set_df_cstate(smu, state); 1974 if (ret) 1975 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 1976 1977 return ret; 1978 } 1979 1980 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 1981 { 1982 int ret = 0; 1983 1984 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1985 return -EOPNOTSUPP; 1986 1987 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 1988 return 0; 1989 1990 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 1991 if (ret) 1992 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 1993 1994 return ret; 1995 } 1996 1997 int smu_write_watermarks_table(struct smu_context *smu) 1998 { 1999 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2000 return -EOPNOTSUPP; 2001 2002 return smu_set_watermarks_table(smu, NULL); 2003 } 2004 2005 static int smu_set_watermarks_for_clock_ranges(void *handle, 2006 struct pp_smu_wm_range_sets *clock_ranges) 2007 { 2008 struct smu_context *smu = handle; 2009 2010 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2011 return -EOPNOTSUPP; 2012 2013 if (smu->disable_watermark) 2014 return 0; 2015 2016 return smu_set_watermarks_table(smu, clock_ranges); 2017 } 2018 2019 int smu_set_ac_dc(struct smu_context *smu) 2020 { 2021 int ret = 0; 2022 2023 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2024 return -EOPNOTSUPP; 2025 2026 /* controlled by firmware */ 2027 if (smu->dc_controlled_by_gpio) 2028 return 0; 2029 2030 ret = smu_set_power_source(smu, 2031 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2032 SMU_POWER_SOURCE_DC); 2033 if (ret) 2034 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2035 smu->adev->pm.ac_power ? "AC" : "DC"); 2036 2037 return ret; 2038 } 2039 2040 const struct amd_ip_funcs smu_ip_funcs = { 2041 .name = "smu", 2042 .early_init = smu_early_init, 2043 .late_init = smu_late_init, 2044 .sw_init = smu_sw_init, 2045 .sw_fini = smu_sw_fini, 2046 .hw_init = smu_hw_init, 2047 .hw_fini = smu_hw_fini, 2048 .late_fini = smu_late_fini, 2049 .suspend = smu_suspend, 2050 .resume = smu_resume, 2051 .is_idle = NULL, 2052 .check_soft_reset = NULL, 2053 .wait_for_idle = NULL, 2054 .soft_reset = NULL, 2055 .set_clockgating_state = smu_set_clockgating_state, 2056 .set_powergating_state = smu_set_powergating_state, 2057 }; 2058 2059 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 2060 { 2061 .type = AMD_IP_BLOCK_TYPE_SMC, 2062 .major = 11, 2063 .minor = 0, 2064 .rev = 0, 2065 .funcs = &smu_ip_funcs, 2066 }; 2067 2068 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 2069 { 2070 .type = AMD_IP_BLOCK_TYPE_SMC, 2071 .major = 12, 2072 .minor = 0, 2073 .rev = 0, 2074 .funcs = &smu_ip_funcs, 2075 }; 2076 2077 const struct amdgpu_ip_block_version smu_v13_0_ip_block = 2078 { 2079 .type = AMD_IP_BLOCK_TYPE_SMC, 2080 .major = 13, 2081 .minor = 0, 2082 .rev = 0, 2083 .funcs = &smu_ip_funcs, 2084 }; 2085 2086 static int smu_load_microcode(void *handle) 2087 { 2088 struct smu_context *smu = handle; 2089 struct amdgpu_device *adev = smu->adev; 2090 int ret = 0; 2091 2092 if (!smu->pm_enabled) 2093 return -EOPNOTSUPP; 2094 2095 /* This should be used for non PSP loading */ 2096 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2097 return 0; 2098 2099 if (smu->ppt_funcs->load_microcode) { 2100 ret = smu->ppt_funcs->load_microcode(smu); 2101 if (ret) { 2102 dev_err(adev->dev, "Load microcode failed\n"); 2103 return ret; 2104 } 2105 } 2106 2107 if (smu->ppt_funcs->check_fw_status) { 2108 ret = smu->ppt_funcs->check_fw_status(smu); 2109 if (ret) { 2110 dev_err(adev->dev, "SMC is not ready\n"); 2111 return ret; 2112 } 2113 } 2114 2115 return ret; 2116 } 2117 2118 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2119 { 2120 int ret = 0; 2121 2122 if (smu->ppt_funcs->set_gfx_cgpg) 2123 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2124 2125 return ret; 2126 } 2127 2128 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2129 { 2130 struct smu_context *smu = handle; 2131 int ret = 0; 2132 2133 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2134 return -EOPNOTSUPP; 2135 2136 if (!smu->ppt_funcs->set_fan_speed_rpm) 2137 return -EOPNOTSUPP; 2138 2139 if (speed == U32_MAX) 2140 return -EINVAL; 2141 2142 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2143 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2144 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2145 smu->user_dpm_profile.fan_speed_rpm = speed; 2146 2147 /* Override custom PWM setting as they cannot co-exist */ 2148 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2149 smu->user_dpm_profile.fan_speed_pwm = 0; 2150 } 2151 2152 return ret; 2153 } 2154 2155 /** 2156 * smu_get_power_limit - Request one of the SMU Power Limits 2157 * 2158 * @handle: pointer to smu context 2159 * @limit: requested limit is written back to this variable 2160 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2161 * @pp_power_type: &pp_power_type type of power 2162 * Return: 0 on success, <0 on error 2163 * 2164 */ 2165 int smu_get_power_limit(void *handle, 2166 uint32_t *limit, 2167 enum pp_power_limit_level pp_limit_level, 2168 enum pp_power_type pp_power_type) 2169 { 2170 struct smu_context *smu = handle; 2171 struct amdgpu_device *adev = smu->adev; 2172 enum smu_ppt_limit_level limit_level; 2173 uint32_t limit_type; 2174 int ret = 0; 2175 2176 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2177 return -EOPNOTSUPP; 2178 2179 switch(pp_power_type) { 2180 case PP_PWR_TYPE_SUSTAINED: 2181 limit_type = SMU_DEFAULT_PPT_LIMIT; 2182 break; 2183 case PP_PWR_TYPE_FAST: 2184 limit_type = SMU_FAST_PPT_LIMIT; 2185 break; 2186 default: 2187 return -EOPNOTSUPP; 2188 break; 2189 } 2190 2191 switch(pp_limit_level){ 2192 case PP_PWR_LIMIT_CURRENT: 2193 limit_level = SMU_PPT_LIMIT_CURRENT; 2194 break; 2195 case PP_PWR_LIMIT_DEFAULT: 2196 limit_level = SMU_PPT_LIMIT_DEFAULT; 2197 break; 2198 case PP_PWR_LIMIT_MAX: 2199 limit_level = SMU_PPT_LIMIT_MAX; 2200 break; 2201 case PP_PWR_LIMIT_MIN: 2202 default: 2203 return -EOPNOTSUPP; 2204 break; 2205 } 2206 2207 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2208 if (smu->ppt_funcs->get_ppt_limit) 2209 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2210 } else { 2211 switch (limit_level) { 2212 case SMU_PPT_LIMIT_CURRENT: 2213 switch (adev->ip_versions[MP1_HWIP][0]) { 2214 case IP_VERSION(13, 0, 2): 2215 case IP_VERSION(11, 0, 7): 2216 case IP_VERSION(11, 0, 11): 2217 case IP_VERSION(11, 0, 12): 2218 case IP_VERSION(11, 0, 13): 2219 ret = smu_get_asic_power_limits(smu, 2220 &smu->current_power_limit, 2221 NULL, 2222 NULL); 2223 break; 2224 default: 2225 break; 2226 } 2227 *limit = smu->current_power_limit; 2228 break; 2229 case SMU_PPT_LIMIT_DEFAULT: 2230 *limit = smu->default_power_limit; 2231 break; 2232 case SMU_PPT_LIMIT_MAX: 2233 *limit = smu->max_power_limit; 2234 break; 2235 default: 2236 break; 2237 } 2238 } 2239 2240 return ret; 2241 } 2242 2243 static int smu_set_power_limit(void *handle, uint32_t limit) 2244 { 2245 struct smu_context *smu = handle; 2246 uint32_t limit_type = limit >> 24; 2247 int ret = 0; 2248 2249 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2250 return -EOPNOTSUPP; 2251 2252 limit &= (1<<24)-1; 2253 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2254 if (smu->ppt_funcs->set_power_limit) 2255 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2256 2257 if (limit > smu->max_power_limit) { 2258 dev_err(smu->adev->dev, 2259 "New power limit (%d) is over the max allowed %d\n", 2260 limit, smu->max_power_limit); 2261 return -EINVAL; 2262 } 2263 2264 if (!limit) 2265 limit = smu->current_power_limit; 2266 2267 if (smu->ppt_funcs->set_power_limit) { 2268 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2269 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2270 smu->user_dpm_profile.power_limit = limit; 2271 } 2272 2273 return ret; 2274 } 2275 2276 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2277 { 2278 int ret = 0; 2279 2280 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2281 return -EOPNOTSUPP; 2282 2283 if (smu->ppt_funcs->print_clk_levels) 2284 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2285 2286 return ret; 2287 } 2288 2289 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2290 { 2291 enum smu_clk_type clk_type; 2292 2293 switch (type) { 2294 case PP_SCLK: 2295 clk_type = SMU_SCLK; break; 2296 case PP_MCLK: 2297 clk_type = SMU_MCLK; break; 2298 case PP_PCIE: 2299 clk_type = SMU_PCIE; break; 2300 case PP_SOCCLK: 2301 clk_type = SMU_SOCCLK; break; 2302 case PP_FCLK: 2303 clk_type = SMU_FCLK; break; 2304 case PP_DCEFCLK: 2305 clk_type = SMU_DCEFCLK; break; 2306 case PP_VCLK: 2307 clk_type = SMU_VCLK; break; 2308 case PP_DCLK: 2309 clk_type = SMU_DCLK; break; 2310 case OD_SCLK: 2311 clk_type = SMU_OD_SCLK; break; 2312 case OD_MCLK: 2313 clk_type = SMU_OD_MCLK; break; 2314 case OD_VDDC_CURVE: 2315 clk_type = SMU_OD_VDDC_CURVE; break; 2316 case OD_RANGE: 2317 clk_type = SMU_OD_RANGE; break; 2318 case OD_VDDGFX_OFFSET: 2319 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2320 case OD_CCLK: 2321 clk_type = SMU_OD_CCLK; break; 2322 default: 2323 clk_type = SMU_CLK_COUNT; break; 2324 } 2325 2326 return clk_type; 2327 } 2328 2329 static int smu_print_ppclk_levels(void *handle, 2330 enum pp_clock_type type, 2331 char *buf) 2332 { 2333 struct smu_context *smu = handle; 2334 enum smu_clk_type clk_type; 2335 2336 clk_type = smu_convert_to_smuclk(type); 2337 if (clk_type == SMU_CLK_COUNT) 2338 return -EINVAL; 2339 2340 return smu_print_smuclk_levels(smu, clk_type, buf); 2341 } 2342 2343 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2344 { 2345 struct smu_context *smu = handle; 2346 enum smu_clk_type clk_type; 2347 2348 clk_type = smu_convert_to_smuclk(type); 2349 if (clk_type == SMU_CLK_COUNT) 2350 return -EINVAL; 2351 2352 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2353 return -EOPNOTSUPP; 2354 2355 if (!smu->ppt_funcs->emit_clk_levels) 2356 return -ENOENT; 2357 2358 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2359 2360 } 2361 2362 static int smu_od_edit_dpm_table(void *handle, 2363 enum PP_OD_DPM_TABLE_COMMAND type, 2364 long *input, uint32_t size) 2365 { 2366 struct smu_context *smu = handle; 2367 int ret = 0; 2368 2369 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2370 return -EOPNOTSUPP; 2371 2372 if (smu->ppt_funcs->od_edit_dpm_table) { 2373 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2374 } 2375 2376 return ret; 2377 } 2378 2379 static int smu_read_sensor(void *handle, 2380 int sensor, 2381 void *data, 2382 int *size_arg) 2383 { 2384 struct smu_context *smu = handle; 2385 struct smu_umd_pstate_table *pstate_table = 2386 &smu->pstate_table; 2387 int ret = 0; 2388 uint32_t *size, size_val; 2389 2390 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2391 return -EOPNOTSUPP; 2392 2393 if (!data || !size_arg) 2394 return -EINVAL; 2395 2396 size_val = *size_arg; 2397 size = &size_val; 2398 2399 if (smu->ppt_funcs->read_sensor) 2400 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2401 goto unlock; 2402 2403 switch (sensor) { 2404 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2405 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2406 *size = 4; 2407 break; 2408 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2409 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2410 *size = 4; 2411 break; 2412 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2413 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2414 *size = 8; 2415 break; 2416 case AMDGPU_PP_SENSOR_UVD_POWER: 2417 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2418 *size = 4; 2419 break; 2420 case AMDGPU_PP_SENSOR_VCE_POWER: 2421 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2422 *size = 4; 2423 break; 2424 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2425 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2426 *size = 4; 2427 break; 2428 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2429 *(uint32_t *)data = 0; 2430 *size = 4; 2431 break; 2432 default: 2433 *size = 0; 2434 ret = -EOPNOTSUPP; 2435 break; 2436 } 2437 2438 unlock: 2439 // assign uint32_t to int 2440 *size_arg = size_val; 2441 2442 return ret; 2443 } 2444 2445 static int smu_get_power_profile_mode(void *handle, char *buf) 2446 { 2447 struct smu_context *smu = handle; 2448 2449 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2450 !smu->ppt_funcs->get_power_profile_mode) 2451 return -EOPNOTSUPP; 2452 if (!buf) 2453 return -EINVAL; 2454 2455 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 2456 } 2457 2458 static int smu_set_power_profile_mode(void *handle, 2459 long *param, 2460 uint32_t param_size) 2461 { 2462 struct smu_context *smu = handle; 2463 2464 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2465 !smu->ppt_funcs->set_power_profile_mode) 2466 return -EOPNOTSUPP; 2467 2468 return smu_bump_power_profile_mode(smu, param, param_size); 2469 } 2470 2471 2472 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 2473 { 2474 struct smu_context *smu = handle; 2475 2476 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2477 return -EOPNOTSUPP; 2478 2479 if (!smu->ppt_funcs->get_fan_control_mode) 2480 return -EOPNOTSUPP; 2481 2482 if (!fan_mode) 2483 return -EINVAL; 2484 2485 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 2486 2487 return 0; 2488 } 2489 2490 static int smu_set_fan_control_mode(void *handle, u32 value) 2491 { 2492 struct smu_context *smu = handle; 2493 int ret = 0; 2494 2495 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2496 return -EOPNOTSUPP; 2497 2498 if (!smu->ppt_funcs->set_fan_control_mode) 2499 return -EOPNOTSUPP; 2500 2501 if (value == U32_MAX) 2502 return -EINVAL; 2503 2504 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2505 if (ret) 2506 goto out; 2507 2508 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2509 smu->user_dpm_profile.fan_mode = value; 2510 2511 /* reset user dpm fan speed */ 2512 if (value != AMD_FAN_CTRL_MANUAL) { 2513 smu->user_dpm_profile.fan_speed_pwm = 0; 2514 smu->user_dpm_profile.fan_speed_rpm = 0; 2515 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 2516 } 2517 } 2518 2519 out: 2520 return ret; 2521 } 2522 2523 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 2524 { 2525 struct smu_context *smu = handle; 2526 int ret = 0; 2527 2528 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2529 return -EOPNOTSUPP; 2530 2531 if (!smu->ppt_funcs->get_fan_speed_pwm) 2532 return -EOPNOTSUPP; 2533 2534 if (!speed) 2535 return -EINVAL; 2536 2537 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 2538 2539 return ret; 2540 } 2541 2542 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 2543 { 2544 struct smu_context *smu = handle; 2545 int ret = 0; 2546 2547 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2548 return -EOPNOTSUPP; 2549 2550 if (!smu->ppt_funcs->set_fan_speed_pwm) 2551 return -EOPNOTSUPP; 2552 2553 if (speed == U32_MAX) 2554 return -EINVAL; 2555 2556 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 2557 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2558 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 2559 smu->user_dpm_profile.fan_speed_pwm = speed; 2560 2561 /* Override custom RPM setting as they cannot co-exist */ 2562 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 2563 smu->user_dpm_profile.fan_speed_rpm = 0; 2564 } 2565 2566 return ret; 2567 } 2568 2569 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2570 { 2571 struct smu_context *smu = handle; 2572 int ret = 0; 2573 2574 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2575 return -EOPNOTSUPP; 2576 2577 if (!smu->ppt_funcs->get_fan_speed_rpm) 2578 return -EOPNOTSUPP; 2579 2580 if (!speed) 2581 return -EINVAL; 2582 2583 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 2584 2585 return ret; 2586 } 2587 2588 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 2589 { 2590 struct smu_context *smu = handle; 2591 2592 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2593 return -EOPNOTSUPP; 2594 2595 return smu_set_min_dcef_deep_sleep(smu, clk); 2596 } 2597 2598 static int smu_get_clock_by_type_with_latency(void *handle, 2599 enum amd_pp_clock_type type, 2600 struct pp_clock_levels_with_latency *clocks) 2601 { 2602 struct smu_context *smu = handle; 2603 enum smu_clk_type clk_type; 2604 int ret = 0; 2605 2606 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2607 return -EOPNOTSUPP; 2608 2609 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 2610 switch (type) { 2611 case amd_pp_sys_clock: 2612 clk_type = SMU_GFXCLK; 2613 break; 2614 case amd_pp_mem_clock: 2615 clk_type = SMU_MCLK; 2616 break; 2617 case amd_pp_dcef_clock: 2618 clk_type = SMU_DCEFCLK; 2619 break; 2620 case amd_pp_disp_clock: 2621 clk_type = SMU_DISPCLK; 2622 break; 2623 default: 2624 dev_err(smu->adev->dev, "Invalid clock type!\n"); 2625 return -EINVAL; 2626 } 2627 2628 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2629 } 2630 2631 return ret; 2632 } 2633 2634 static int smu_display_clock_voltage_request(void *handle, 2635 struct pp_display_clock_request *clock_req) 2636 { 2637 struct smu_context *smu = handle; 2638 int ret = 0; 2639 2640 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2641 return -EOPNOTSUPP; 2642 2643 if (smu->ppt_funcs->display_clock_voltage_request) 2644 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2645 2646 return ret; 2647 } 2648 2649 2650 static int smu_display_disable_memory_clock_switch(void *handle, 2651 bool disable_memory_clock_switch) 2652 { 2653 struct smu_context *smu = handle; 2654 int ret = -EINVAL; 2655 2656 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2657 return -EOPNOTSUPP; 2658 2659 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2660 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2661 2662 return ret; 2663 } 2664 2665 static int smu_set_xgmi_pstate(void *handle, 2666 uint32_t pstate) 2667 { 2668 struct smu_context *smu = handle; 2669 int ret = 0; 2670 2671 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2672 return -EOPNOTSUPP; 2673 2674 if (smu->ppt_funcs->set_xgmi_pstate) 2675 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2676 2677 if(ret) 2678 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2679 2680 return ret; 2681 } 2682 2683 static int smu_get_baco_capability(void *handle, bool *cap) 2684 { 2685 struct smu_context *smu = handle; 2686 2687 *cap = false; 2688 2689 if (!smu->pm_enabled) 2690 return 0; 2691 2692 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2693 *cap = smu->ppt_funcs->baco_is_support(smu); 2694 2695 return 0; 2696 } 2697 2698 static int smu_baco_set_state(void *handle, int state) 2699 { 2700 struct smu_context *smu = handle; 2701 int ret = 0; 2702 2703 if (!smu->pm_enabled) 2704 return -EOPNOTSUPP; 2705 2706 if (state == 0) { 2707 if (smu->ppt_funcs->baco_exit) 2708 ret = smu->ppt_funcs->baco_exit(smu); 2709 } else if (state == 1) { 2710 if (smu->ppt_funcs->baco_enter) 2711 ret = smu->ppt_funcs->baco_enter(smu); 2712 } else { 2713 return -EINVAL; 2714 } 2715 2716 if (ret) 2717 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 2718 (state)?"enter":"exit"); 2719 2720 return ret; 2721 } 2722 2723 bool smu_mode1_reset_is_support(struct smu_context *smu) 2724 { 2725 bool ret = false; 2726 2727 if (!smu->pm_enabled) 2728 return false; 2729 2730 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2731 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2732 2733 return ret; 2734 } 2735 2736 bool smu_mode2_reset_is_support(struct smu_context *smu) 2737 { 2738 bool ret = false; 2739 2740 if (!smu->pm_enabled) 2741 return false; 2742 2743 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 2744 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 2745 2746 return ret; 2747 } 2748 2749 int smu_mode1_reset(struct smu_context *smu) 2750 { 2751 int ret = 0; 2752 2753 if (!smu->pm_enabled) 2754 return -EOPNOTSUPP; 2755 2756 if (smu->ppt_funcs->mode1_reset) 2757 ret = smu->ppt_funcs->mode1_reset(smu); 2758 2759 return ret; 2760 } 2761 2762 static int smu_mode2_reset(void *handle) 2763 { 2764 struct smu_context *smu = handle; 2765 int ret = 0; 2766 2767 if (!smu->pm_enabled) 2768 return -EOPNOTSUPP; 2769 2770 if (smu->ppt_funcs->mode2_reset) 2771 ret = smu->ppt_funcs->mode2_reset(smu); 2772 2773 if (ret) 2774 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2775 2776 return ret; 2777 } 2778 2779 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 2780 struct pp_smu_nv_clock_table *max_clocks) 2781 { 2782 struct smu_context *smu = handle; 2783 int ret = 0; 2784 2785 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2786 return -EOPNOTSUPP; 2787 2788 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2789 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2790 2791 return ret; 2792 } 2793 2794 static int smu_get_uclk_dpm_states(void *handle, 2795 unsigned int *clock_values_in_khz, 2796 unsigned int *num_states) 2797 { 2798 struct smu_context *smu = handle; 2799 int ret = 0; 2800 2801 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2802 return -EOPNOTSUPP; 2803 2804 if (smu->ppt_funcs->get_uclk_dpm_states) 2805 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2806 2807 return ret; 2808 } 2809 2810 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 2811 { 2812 struct smu_context *smu = handle; 2813 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2814 2815 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2816 return -EOPNOTSUPP; 2817 2818 if (smu->ppt_funcs->get_current_power_state) 2819 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2820 2821 return pm_state; 2822 } 2823 2824 static int smu_get_dpm_clock_table(void *handle, 2825 struct dpm_clocks *clock_table) 2826 { 2827 struct smu_context *smu = handle; 2828 int ret = 0; 2829 2830 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2831 return -EOPNOTSUPP; 2832 2833 if (smu->ppt_funcs->get_dpm_clock_table) 2834 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 2835 2836 return ret; 2837 } 2838 2839 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 2840 { 2841 struct smu_context *smu = handle; 2842 2843 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2844 return -EOPNOTSUPP; 2845 2846 if (!smu->ppt_funcs->get_gpu_metrics) 2847 return -EOPNOTSUPP; 2848 2849 return smu->ppt_funcs->get_gpu_metrics(smu, table); 2850 } 2851 2852 static int smu_enable_mgpu_fan_boost(void *handle) 2853 { 2854 struct smu_context *smu = handle; 2855 int ret = 0; 2856 2857 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2858 return -EOPNOTSUPP; 2859 2860 if (smu->ppt_funcs->enable_mgpu_fan_boost) 2861 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 2862 2863 return ret; 2864 } 2865 2866 static int smu_gfx_state_change_set(void *handle, 2867 uint32_t state) 2868 { 2869 struct smu_context *smu = handle; 2870 int ret = 0; 2871 2872 if (smu->ppt_funcs->gfx_state_change_set) 2873 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 2874 2875 return ret; 2876 } 2877 2878 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 2879 { 2880 int ret = 0; 2881 2882 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 2883 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 2884 2885 return ret; 2886 } 2887 2888 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 2889 { 2890 int ret = -EOPNOTSUPP; 2891 2892 if (smu->ppt_funcs && 2893 smu->ppt_funcs->get_ecc_info) 2894 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 2895 2896 return ret; 2897 2898 } 2899 2900 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 2901 { 2902 struct smu_context *smu = handle; 2903 struct smu_table_context *smu_table = &smu->smu_table; 2904 struct smu_table *memory_pool = &smu_table->memory_pool; 2905 2906 if (!addr || !size) 2907 return -EINVAL; 2908 2909 *addr = NULL; 2910 *size = 0; 2911 if (memory_pool->bo) { 2912 *addr = memory_pool->cpu_addr; 2913 *size = memory_pool->size; 2914 } 2915 2916 return 0; 2917 } 2918 2919 static const struct amd_pm_funcs swsmu_pm_funcs = { 2920 /* export for sysfs */ 2921 .set_fan_control_mode = smu_set_fan_control_mode, 2922 .get_fan_control_mode = smu_get_fan_control_mode, 2923 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 2924 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 2925 .force_clock_level = smu_force_ppclk_levels, 2926 .print_clock_levels = smu_print_ppclk_levels, 2927 .emit_clock_levels = smu_emit_ppclk_levels, 2928 .force_performance_level = smu_force_performance_level, 2929 .read_sensor = smu_read_sensor, 2930 .get_performance_level = smu_get_performance_level, 2931 .get_current_power_state = smu_get_current_power_state, 2932 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 2933 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 2934 .get_pp_num_states = smu_get_power_num_states, 2935 .get_pp_table = smu_sys_get_pp_table, 2936 .set_pp_table = smu_sys_set_pp_table, 2937 .switch_power_profile = smu_switch_power_profile, 2938 /* export to amdgpu */ 2939 .dispatch_tasks = smu_handle_dpm_task, 2940 .load_firmware = smu_load_microcode, 2941 .set_powergating_by_smu = smu_dpm_set_power_gate, 2942 .set_power_limit = smu_set_power_limit, 2943 .get_power_limit = smu_get_power_limit, 2944 .get_power_profile_mode = smu_get_power_profile_mode, 2945 .set_power_profile_mode = smu_set_power_profile_mode, 2946 .odn_edit_dpm_table = smu_od_edit_dpm_table, 2947 .set_mp1_state = smu_set_mp1_state, 2948 .gfx_state_change_set = smu_gfx_state_change_set, 2949 /* export to DC */ 2950 .get_sclk = smu_get_sclk, 2951 .get_mclk = smu_get_mclk, 2952 .display_configuration_change = smu_display_configuration_change, 2953 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 2954 .display_clock_voltage_request = smu_display_clock_voltage_request, 2955 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 2956 .set_active_display_count = smu_set_display_count, 2957 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 2958 .get_asic_baco_capability = smu_get_baco_capability, 2959 .set_asic_baco_state = smu_baco_set_state, 2960 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 2961 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 2962 .asic_reset_mode_2 = smu_mode2_reset, 2963 .set_df_cstate = smu_set_df_cstate, 2964 .set_xgmi_pstate = smu_set_xgmi_pstate, 2965 .get_gpu_metrics = smu_sys_get_gpu_metrics, 2966 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 2967 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 2968 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 2969 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 2970 .get_dpm_clock_table = smu_get_dpm_clock_table, 2971 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 2972 }; 2973 2974 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 2975 uint64_t event_arg) 2976 { 2977 int ret = -EINVAL; 2978 2979 if (smu->ppt_funcs->wait_for_event) 2980 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 2981 2982 return ret; 2983 } 2984 2985 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 2986 { 2987 2988 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 2989 return -EOPNOTSUPP; 2990 2991 /* Confirm the buffer allocated is of correct size */ 2992 if (size != smu->stb_context.stb_buf_size) 2993 return -EINVAL; 2994 2995 /* 2996 * No need to lock smu mutex as we access STB directly through MMIO 2997 * and not going through SMU messaging route (for now at least). 2998 * For registers access rely on implementation internal locking. 2999 */ 3000 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3001 } 3002 3003 #if defined(CONFIG_DEBUG_FS) 3004 3005 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3006 { 3007 struct amdgpu_device *adev = filp->f_inode->i_private; 3008 struct smu_context *smu = adev->powerplay.pp_handle; 3009 unsigned char *buf; 3010 int r; 3011 3012 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3013 if (!buf) 3014 return -ENOMEM; 3015 3016 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3017 if (r) 3018 goto out; 3019 3020 filp->private_data = buf; 3021 3022 return 0; 3023 3024 out: 3025 kvfree(buf); 3026 return r; 3027 } 3028 3029 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3030 loff_t *pos) 3031 { 3032 struct amdgpu_device *adev = filp->f_inode->i_private; 3033 struct smu_context *smu = adev->powerplay.pp_handle; 3034 3035 3036 if (!filp->private_data) 3037 return -EINVAL; 3038 3039 return simple_read_from_buffer(buf, 3040 size, 3041 pos, filp->private_data, 3042 smu->stb_context.stb_buf_size); 3043 } 3044 3045 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3046 { 3047 kvfree(filp->private_data); 3048 filp->private_data = NULL; 3049 3050 return 0; 3051 } 3052 3053 /* 3054 * We have to define not only read method but also 3055 * open and release because .read takes up to PAGE_SIZE 3056 * data each time so and so is invoked multiple times. 3057 * We allocate the STB buffer in .open and release it 3058 * in .release 3059 */ 3060 static const struct file_operations smu_stb_debugfs_fops = { 3061 .owner = THIS_MODULE, 3062 .open = smu_stb_debugfs_open, 3063 .read = smu_stb_debugfs_read, 3064 .release = smu_stb_debugfs_release, 3065 .llseek = default_llseek, 3066 }; 3067 3068 #endif 3069 3070 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3071 { 3072 #if defined(CONFIG_DEBUG_FS) 3073 3074 struct smu_context *smu = adev->powerplay.pp_handle; 3075 3076 if (!smu || (!smu->stb_context.stb_buf_size)) 3077 return; 3078 3079 debugfs_create_file_size("amdgpu_smu_stb_dump", 3080 S_IRUSR, 3081 adev_to_drm(adev)->primary->debugfs_root, 3082 adev, 3083 &smu_stb_debugfs_fops, 3084 smu->stb_context.stb_buf_size); 3085 #endif 3086 } 3087 3088 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3089 { 3090 int ret = 0; 3091 3092 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3093 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3094 3095 return ret; 3096 } 3097 3098 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3099 { 3100 int ret = 0; 3101 3102 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3103 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3104 3105 return ret; 3106 } 3107